ATtiny202/204/402/404/406
Automotive
tinyAVR® 0-series
Introduction
The ATtiny202/204/402/404/406 Automotive are members of the tinyAVR® 0-series of microcontrollers, using the
AVR® processor with hardware multiplier, running at up to 16 MHz, with 2/4 KB Flash, 128/256 bytes of SRAM, and
64/128 bytes of EEPROM in an 8-, 14-, 20-pin package. The tinyAVR® 0-series uses the latest technologies, with a
flexible, low-power architecture including Event System and SleepWalking, accurate analog features, and Core
Independent Peripherals.
Features
•
•
•
•
CPU:
– AVR® CPU
– Running at up to 16 MHz
– Single-cycle I/O access
– Two-level interrupt controller
– Two-cycle hardware multiplier
Memories:
– 2/4 KB In-system self-programmable Flash memory
– 64/128B EEPROM
– 128/256B SRAM
– Write/erase endurance:
• Flash: 10,000 cycles
• EEPROM: 100,000 cycles
– Data retention: 40 years at 55°C
System:
– Power-on Reset (POR)
– Brown-out Detector (BOD)
– Clock Options:
• 16 MHz low-power internal RC oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
• External clock input
– Single-pin Unified Program and Debug Interface (UPDI)
– Three sleep modes:
• Idle with all peripherals running for immediate wake-up
• Standby
– Configurable operation of selected peripherals
– SleepWalking peripherals
• Power-Down with full data retention
Peripherals:
– One 16-bit Timer/Counter Type A (TCA) with a dedicated period register and three compare channels
– One 16-bit Timer/Counter Type B (TCB) with input capture
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 1
ATtiny202/204/402/404/406 Automotiv...
–
–
–
–
–
•
•
•
One 16-bit Real-Time Counter (RTC) running from the internal RC oscillator
Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator
One USART with fractional baud rate generator, auto-baud, and start-of-frame detection
One master/slave Serial Peripheral Interface (SPI)
One Two-Wire Interface (TWI) with dual address match
• Philips I2C compatible
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– One Analog Comparator (AC) with a low propagation delay
– One 10-bit 115 ksps Analog-to-Digital Converter (ADC)
– Multiple voltage references (VREF):
• 0.55V
• 1.1V
• 1.5V
• 2.5V
• 4.3V
– Event System (EVSYS) for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with two programmable look-up tables
– Automated CRC memory scan (CRCSCAN)
– External interrupt on all general purpose pins
I/O and Packages:
– 6/12/18 programmable I/O lines
– 8-pin SOIC150
– 14-pin SOIC150
– 20-pin VQFN 3x3 mm with wettable flanks
– 20-pin SOIC300
Temperature Ranges:
– -40°C to 105°C
– -40°C to 125°C
Speed Grades:
– 0-8 MHz @ 2.7V – 5.5V
– 0-16 MHz @ 4.5V – 5.5V
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 2
ATtiny202/204/402/404/406 Automotiv...
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
1.
Silicon Errata and Data Sheet Clarification Document............................................................................9
2.
tinyAVR® 0-Series Overview................................................................................................................. 10
2.1.
Configuration Summary..............................................................................................................10
3.
Block Diagram.......................................................................................................................................12
4.
Pinout.................................................................................................................................................... 15
4.1.
4.2.
4.3.
4.4.
5.
8-Pin SOIC................................................................................................................................. 15
14-Pin SOIC............................................................................................................................... 15
20-Pin VQFN.............................................................................................................................. 16
20-Pin SOIC............................................................................................................................... 17
I/O Multiplexing and Considerations..................................................................................................... 18
5.1.
5.2.
5.3.
20-pins: I/O Multiplexing.............................................................................................................18
14-pins: I/O Multiplexing.............................................................................................................18
8-pins: I/O Multiplexing...............................................................................................................19
6.
Automotive Quality Grade..................................................................................................................... 20
7.
Memories.............................................................................................................................................. 21
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
8.
Peripherals and Architecture.................................................................................................................43
8.1.
8.2.
8.3.
9.
Overview.................................................................................................................................... 21
Memory Map.............................................................................................................................. 22
In-System Reprogrammable Flash Program Memory................................................................22
SRAM Data Memory.................................................................................................................. 23
EEPROM Data Memory............................................................................................................. 23
User Row....................................................................................................................................23
Signature Bytes.......................................................................................................................... 24
Memory Section Access from CPU and UPDI on Locked Device..............................................24
I/O Memory.................................................................................................................................25
Configuration and User Fuses (FUSE).......................................................................................28
Peripheral Module Address Map................................................................................................ 43
Interrupt Vector Mapping............................................................................................................ 44
System Configuration (SYSCFG)...............................................................................................45
AVR® CPU............................................................................................................................................ 48
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
Features..................................................................................................................................... 48
Overview.................................................................................................................................... 48
Architecture................................................................................................................................ 48
Arithmetic Logic Unit (ALU)........................................................................................................ 50
Functional Description................................................................................................................50
Register Summary - CPU...........................................................................................................55
Register Description................................................................................................................... 55
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 3
ATtiny202/204/402/404/406 Automotiv...
10. Nonvolatile Memory Controller (NVMCTRL)......................................................................................... 59
10.1.
10.2.
10.3.
10.4.
10.5.
Features..................................................................................................................................... 59
Overview.................................................................................................................................... 59
Functional Description................................................................................................................60
Register Summary - NVMCTRL................................................................................................. 66
Register Description................................................................................................................... 66
11. Clock Controller (CLKCTRL).................................................................................................................74
11.1.
11.2.
11.3.
11.4.
11.5.
Features..................................................................................................................................... 74
Overview.................................................................................................................................... 74
Functional Description................................................................................................................77
Register Summary - CLKCTRL.................................................................................................. 81
Register Description................................................................................................................... 81
12. Sleep Controller (SLPCTRL).................................................................................................................90
12.1.
12.2.
12.3.
12.4.
12.5.
Features..................................................................................................................................... 90
Overview.................................................................................................................................... 90
Functional Description................................................................................................................91
Register Summary - SLPCTRL.................................................................................................. 94
Register Description................................................................................................................... 94
13. Reset Controller (RSTCTRL)................................................................................................................ 96
13.1.
13.2.
13.3.
13.4.
13.5.
Features..................................................................................................................................... 96
Overview.................................................................................................................................... 96
Functional Description................................................................................................................96
Register Summary - RSTCTRL..................................................................................................99
Register Description................................................................................................................... 99
14. CPU Interrupt Controller (CPUINT).....................................................................................................102
14.1.
14.2.
14.3.
14.4.
14.5.
Features................................................................................................................................... 102
Overview.................................................................................................................................. 102
Functional Description..............................................................................................................104
Register Summary - CPUINT................................................................................................... 109
Register Description................................................................................................................. 109
15. Event System (EVSYS)....................................................................................................................... 114
15.1.
15.2.
15.3.
15.4.
15.5.
Features................................................................................................................................... 114
Overview...................................................................................................................................114
Functional Description.............................................................................................................. 117
Register Summary - EVSYS.....................................................................................................119
Register Description................................................................................................................. 119
16. Port Multiplexer (PORTMUX).............................................................................................................. 127
16.1. Overview.................................................................................................................................. 127
16.2. Register Summary - PORTMUX.............................................................................................. 128
16.3. Register Description................................................................................................................. 128
17. I/O Pin Configuration (PORT)..............................................................................................................133
17.1. Features................................................................................................................................... 133
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 4
ATtiny202/204/402/404/406 Automotiv...
17.2.
17.3.
17.4.
17.5.
17.6.
17.7.
Overview.................................................................................................................................. 133
Functional Description..............................................................................................................135
Register Summary - PORT...................................................................................................... 139
Register Description - Ports..................................................................................................... 139
Register Summary - VPORT.................................................................................................... 151
Register Description - Virtual Ports.......................................................................................... 151
18. Brown-Out Detector (BOD)................................................................................................................. 156
18.1.
18.2.
18.3.
18.4.
18.5.
Features................................................................................................................................... 156
Overview.................................................................................................................................. 156
Functional Description..............................................................................................................158
Register Summary - BOD.........................................................................................................160
Register Description................................................................................................................. 160
19. Voltage Reference (VREF)..................................................................................................................167
19.1.
19.2.
19.3.
19.4.
19.5.
Features................................................................................................................................... 167
Overview.................................................................................................................................. 167
Functional Description..............................................................................................................167
Register Summary - VREF.......................................................................................................168
Register Description................................................................................................................. 168
20. Watchdog Timer (WDT).......................................................................................................................171
20.1.
20.2.
20.3.
20.4.
20.5.
Features................................................................................................................................... 171
Overview.................................................................................................................................. 171
Functional Description..............................................................................................................173
Register Summary - WDT........................................................................................................ 176
Register Description................................................................................................................. 176
21. 16-bit Timer/Counter Type A (TCA).....................................................................................................179
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
21.7.
Features................................................................................................................................... 179
Overview.................................................................................................................................. 179
Functional Description..............................................................................................................183
Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0)............................................. 192
Register Description - Normal Mode........................................................................................ 192
Register Summary - TCA in Split Mode (CTRLD.SPLITM=1).................................................. 212
Register Description - Split Mode.............................................................................................212
22. 16-bit Timer/Counter Type B (TCB).....................................................................................................228
22.1.
22.2.
22.3.
22.4.
22.5.
Features................................................................................................................................... 228
Overview.................................................................................................................................. 228
Functional Description..............................................................................................................230
Register Summary - TCB......................................................................................................... 238
Register Description................................................................................................................. 238
23. Real-Time Counter (RTC)................................................................................................................... 249
23.1.
23.2.
23.3.
23.4.
Features................................................................................................................................... 249
Overview.................................................................................................................................. 249
RTC Functional Description..................................................................................................... 251
PIT Functional Description....................................................................................................... 252
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 5
ATtiny202/204/402/404/406 Automotiv...
23.5. Events...................................................................................................................................... 254
23.6. Interrupts.................................................................................................................................. 255
23.7. Sleep Mode Operation............................................................................................................. 255
23.8. Synchronization........................................................................................................................255
23.9. Configuration Change Protection............................................................................................. 256
23.10. Register Summary - RTC.........................................................................................................257
23.11. Register Description................................................................................................................. 257
24. Universal Synchronous and Asynchronous Receiver and Transmitter (USART)................................273
24.1.
24.2.
24.3.
24.4.
24.5.
Features................................................................................................................................... 273
Overview.................................................................................................................................. 273
Functional Description..............................................................................................................276
Register Summary - USART.................................................................................................... 289
Register Description................................................................................................................. 289
25. Serial Peripheral Interface (SPI)......................................................................................................... 305
25.1.
25.2.
25.3.
25.4.
25.5.
Features................................................................................................................................... 305
Overview.................................................................................................................................. 305
Functional Description..............................................................................................................308
Register Summary - SPI...........................................................................................................315
Register Description................................................................................................................. 315
26. Two-Wire Interface (TWI).................................................................................................................... 321
26.1.
26.2.
26.3.
26.4.
26.5.
Features................................................................................................................................... 321
Overview.................................................................................................................................. 321
Functional Description..............................................................................................................323
Register Summary - TWI..........................................................................................................335
Register Description................................................................................................................. 335
27. Cyclic Redundancy Check Memory Scan (CRCSCAN)......................................................................352
27.1.
27.2.
27.3.
27.4.
27.5.
Features................................................................................................................................... 352
Overview.................................................................................................................................. 352
Functional Description..............................................................................................................354
Register Summary - CRCSCAN...............................................................................................356
Register Description................................................................................................................. 356
28. Configurable Custom Logic (CCL)...................................................................................................... 360
28.1.
28.2.
28.3.
28.4.
28.5.
Features................................................................................................................................... 360
Overview.................................................................................................................................. 360
Functional Description..............................................................................................................362
Register Summary - CCL......................................................................................................... 370
Register Description................................................................................................................. 370
29. Analog Comparator (AC).....................................................................................................................377
29.1.
29.2.
29.3.
29.4.
29.5.
Features................................................................................................................................... 377
Overview.................................................................................................................................. 377
Functional Description..............................................................................................................379
Register Summary - AC........................................................................................................... 381
Register Description................................................................................................................. 381
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 6
ATtiny202/204/402/404/406 Automotiv...
30. Analog-to-Digital Converter (ADC)......................................................................................................386
30.1.
30.2.
30.3.
30.4.
30.5.
Features................................................................................................................................... 386
Overview.................................................................................................................................. 386
Functional Description..............................................................................................................390
Register Summary - ADCn.......................................................................................................396
Register Description................................................................................................................. 396
31. Unified Program and Debug Interface (UPDI).....................................................................................414
31.1.
31.2.
31.3.
31.4.
31.5.
Features................................................................................................................................... 414
Overview.................................................................................................................................. 414
Functional Description..............................................................................................................416
Register Summary....................................................................................................................435
Register Description................................................................................................................. 435
32. Electrical Characteristics.....................................................................................................................446
32.1. Disclaimer.................................................................................................................................446
32.2. Absolute Maximum Ratings .....................................................................................................446
32.3. General Operating Ratings ......................................................................................................447
32.4. Power Consumption................................................................................................................. 447
32.5. Wake-Up Time..........................................................................................................................448
32.6. Peripherals Power Consumption..............................................................................................449
32.7. BOD and POR Characteristics................................................................................................. 450
32.8. External Reset Characteristics................................................................................................. 450
32.9. Oscillators and Clocks..............................................................................................................450
32.10. I/O Pin Characteristics............................................................................................................. 452
32.11. USART..................................................................................................................................... 453
32.12. SPI........................................................................................................................................... 454
32.13. TWI...........................................................................................................................................455
32.14. VREF........................................................................................................................................457
32.15. ADC..........................................................................................................................................458
32.16. AC............................................................................................................................................ 460
32.17. UPDI Timing.............................................................................................................................460
32.18. Programming Time...................................................................................................................461
33. Typical Characteristics........................................................................................................................ 462
33.1.
33.2.
33.3.
33.4.
33.5.
33.6.
33.7.
33.8.
33.9.
Power Consumption................................................................................................................. 462
GPIO........................................................................................................................................ 469
VREF Characteristics............................................................................................................... 475
BOD Characteristics.................................................................................................................477
ADC Characteristics................................................................................................................. 479
AC Characteristics....................................................................................................................484
OSC20M Characteristics..........................................................................................................487
OSCULP32K Characteristics................................................................................................... 489
TWI SDA Hold timing .............................................................................................................. 490
34. Ordering Information........................................................................................................................... 491
34.1. Product Information.................................................................................................................. 491
34.2. Product Identification System...................................................................................................491
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 7
ATtiny202/204/402/404/406 Automotiv...
35. Package Drawings.............................................................................................................................. 492
35.1.
35.2.
35.3.
35.4.
35.5.
Online Package Drawings........................................................................................................ 492
8-Pin SOIC150......................................................................................................................... 493
14-Pin SOIC150....................................................................................................................... 497
20-Pin SOIC300....................................................................................................................... 501
20-Pin VQFN............................................................................................................................ 505
36. Thermal Considerations...................................................................................................................... 509
36.1. Thermal Resistance Data.........................................................................................................509
36.2. Junction Temperature...............................................................................................................509
37. Instruction Set Summary.....................................................................................................................510
38. Conventions........................................................................................................................................ 515
38.1.
38.2.
38.3.
38.4.
Numerical Notation...................................................................................................................515
Memory Size and Type.............................................................................................................515
Frequency and Time.................................................................................................................515
Registers and Bits.................................................................................................................... 516
39. Acronyms and Abbreviations.............................................................................................................. 517
40. Data Sheet Revision History............................................................................................................... 520
40.1. Rev. A - 12/2019.......................................................................................................................520
The Microchip Website...............................................................................................................................521
Product Change Notification Service..........................................................................................................521
Customer Support...................................................................................................................................... 521
Microchip Devices Code Protection Feature.............................................................................................. 521
Legal Notice............................................................................................................................................... 521
Trademarks................................................................................................................................................ 522
Quality Management System..................................................................................................................... 522
Worldwide Sales and Service.....................................................................................................................523
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 8
ATtiny202/204/402/404/406 Automotiv...
Silicon Errata and Data Sheet Clarification ...
1.
Silicon Errata and Data Sheet Clarification Document
Our intention is to provide our customers with the best documentation possible to ensure successful use of Microchip
products. Between data sheet updates, a Silicon Errata and Data Sheet Clarification Document will contain the most
recent information for the data sheet. The ATtiny202/204/402/404/406 Automotive Silicon Errata and Data Sheet
Clarification Document is available at the device product page on https://www.microchip.com.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 9
ATtiny202/204/402/404/406 Automotiv...
tinyAVR® 0-Series Overview
2.
tinyAVR® 0-Series Overview
The figure below shows the tinyAVR® 0-series, laying out pin count variants and memory sizes:
•
•
Vertical migration upwards is possible without code modification, as these devices are pin compatible and
provide the same or more features.
Horizontal migration to the left reduces the pin count and therefore, the available features.
Figure 2-1. Device Family Overview
Legend:
Devices
Flash
ATtiny~~
ATtiny~~
Common data sheet
16 KB
8 KB
4 KB
ATtiny402
ATtiny404
2 KB
ATtiny202
ATtiny204
8
ATtiny406
14
20
Pins
24
Devices with different Flash memory size typically also have different SRAM and EEPROM.
2.1
Configuration Summary
2.1.1
Peripheral Summary
ATtiny202
ATtiny204
ATtiny402
ATtiny404
ATtiny406
Table 2-1. Peripheral Summary
Pins
8
14
8
14
20
SRAM
128B
128B
256B
256B
256B
Flash
2 KB
2 KB
4 KB
4 KB
4 KB
EEPROM
64B
64B
128B
128B
128B
Max. frequency (MHz)
16
16
16
16
16
16-bit Timer/Counter type A (TCA)
1
1
1
1
1
16-bit Timer/Counter type B (TCB)
1
1
1
1
1
12-bit Timer/Counter type D (TCD)
No
No
No
No
No
Real-Time Counter (RTC)
1
1
1
1
1
USART
1
1
1
1
1
SPI
1
1
1
1
1
TWI (I2C)
1
1
1
1
1
ADC
1
1
1
1
1
ADC channels
6
10
6
10
12
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 10
ATtiny202/204/402/404/406 Automotiv...
tinyAVR® 0-Series Overview
ATtiny202
ATtiny204
ATtiny402
ATtiny404
ATtiny406
...........continued
DAC
No
No
No
No
No
AC
1
1
1
1
1
AC inputs
1p/1n
1p/1n
1p/1n
1p/1n
2p/2n
Peripheral Touch Controller (PTC)
No
No
No
No
No
Configurable Custom Logic
1
1
1
1
1
Window Watchdog
1
1
1
1
1
Event System channels
3
3
3
3
3
General purpose I/O
6
12
6
12
18
External interrupts
6
12
6
12
18
CRCSCAN
1
1
1
1
1
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 11
ATtiny202/204/402/404/406 Automotiv...
Block Diagram
3.
Block Diagram
Figure 3-1. ATtiny202/402 Automotive
UPDI
UPDI / RESET
CRC
CPU
OCD
To
detectors
M
M
Flash
M
S
SRAM
BUS Matrix
S
EEPROM
S
S
AINP0
AINN0
OUT
NVMCTRL
PORTS
AC0
GPIOR
AIN[7, 6,3:0]
ADC0
EVOUT[n:0]
EVSYS
LUTn-IN[2:0]
LUTn-OUT
CCL
WO[3:0]
WO
RXD
TXD
XCK
XDIR
TCA0
TCB0
USART0
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
CPUINT
System
Management
RSTCTRL
I
N
/
O
U
T
D
A
T
A
B
U
S
PA[7:0]
Detectors/
references
RST/12V
POR
Bandgap
BOD/
VLM
CLKCTRL
SLPCTRL
Clock generation
WDT
OSC20M
EXTCLK
OSC32K
MISO
MOSI
SCK
SS
SPI0
SDA
SCL
TWI0
© 2019 Microchip Technology Inc.
RTC
Complete Datasheet
DS40002159A-page 12
ATtiny202/204/402/404/406 Automotiv...
Block Diagram
Figure 3-2. ATtiny204/404 Automotive
UPDI
UPDI / RESET
CRC
CPU
OCD
To
detectors
M
M
Flash
M
S
SRAM
BUS Matrix
S
EEPROM
S
S
AINP0
AINN0
OUT
NVMCTRL
PORTS
AC0
GPIOR
AIN[11:0]
ADC0
EVOUT[n:0]
EVSYS
LUTn-IN[2:0]
LUTn-OUT
CCL
WO[5:0]
WO
RXD
TXD
XCK
XDIR
TCA0
TCB0
USART0
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
CPUINT
System
Management
RSTCTRL
I
N
/
O
U
T
D
A
T
A
B
U
S
PA[7:0]
PB[3:0]
Detectors/
references
RST/12V
POR
Bandgap
BOD/
VLM
CLKCTRL
SLPCTRL
Clock generation
WDT
OSC20M
EXTCLK
OSC32K
MISO
MOSI
SCK
SS
SPI0
SDA
SCL
TWI0
© 2019 Microchip Technology Inc.
RTC
Complete Datasheet
DS40002159A-page 13
ATtiny202/204/402/404/406 Automotiv...
Block Diagram
Figure 3-3. ATtiny406 Automotive
UPDI
UPDI / RESET
CRC
CPU
OCD
To
detectors
M
M
Flash
M
S
SRAM
BUS Matrix
S
EEPROM
S
S
AINP0
AINN0
OUT
NVMCTRL
PORTS
AC0
GPIOR
AIN[11:0]
ADC0
EVOUT[n:0]
EVSYS
LUTn-IN[2:0]
LUTn-OUT
CCL
WO[5:0]
WO
RXD
TXD
XCK
XDIR
TCA0
TCB0
USART0
E
V
E
N
T
R
O
U
T
I
N
G
N
E
T
W
O
R
K
D
A
T
A
B
U
S
CPUINT
System
management
RSTCTRL
I
N
/
O
U
T
D
A
T
A
B
U
S
PA[7:0]
PB[5:0]
PC[3:0]
Detectors/
references
RST/12V
POR
Bandgap
BOD/
VLM
CLKCTRL
SLPCTRL
Clock generation
CLKOUT
WDT
OSC20M
EXTCLK
OSC32K
MISO
MOSI
SCK
SS
SPI0
SDA
SCL
TWI0
© 2019 Microchip Technology Inc.
RTC
Complete Datasheet
DS40002159A-page 14
ATtiny202/204/402/404/406 Automotiv...
Pinout
4.
Pinout
4.1
8-Pin SOIC
VDD
1
8
GND
PA6
2
7
PA3/EXTCLK
PA7
3
6
PA0/RESET/UPDI
PA1
4
5
PA2
Input supply
Programming, Debug, Reset
Ground
Clock, crystal
GPIO VDD power domain
Digital function only
Analog function
4.2
14-Pin SOIC
VDD
1
14
GND
PA4
2
13
PA3/EXTCLK
PA5
3
12
PA2
PA6
4
11
PA1
PA7
5
10
PA0/RESET/UPDI
PB3
6
9
PB0
PB2
7
8
PB1
Input supply
Programming, Debug, Reset
Ground
Clock
GPIO VDD power domain
Digital function only
Analog function
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 15
ATtiny202/204/402/404/406 Automotiv...
Pinout
PA1
PA0/RESET/UPDI
PC3
PC2
PC1
20
19
18
17
16
20-Pin VQFN
3
13
PB1
VDD
4
12
PB2
PA4
5
11
PB3
10
GND
PB4
PB0
9
14
PB5
2
8
EXTCLK /PA3
PA7
PC0
7
15
PA6
1
6
PA2
PA5
4.3
Input supply
Programming, Debug, Reset
Ground
Clock
GPIO VDD power domain
Digital function only
Analog function
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 16
ATtiny202/204/402/404/406 Automotiv...
Pinout
4.4
20-Pin SOIC
VDD
1
20
GND
PA4
2
19
PA3/EXTCLK
PA5
3
18
PA2
PA6
4
17
PA1
PA7
5
16
PA0/RESET/UPDI
PB5
6
15
PC3
PB4
7
14
PC2
PB3
8
13
PC1
PB2
9
12
PC0
PB1
10
11
PB0
Input supply
Programming, Debug, Reset
Ground
Clock
GPIO VDD power domain
Digital function only
Analog function
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 17
ATtiny202/204/402/404/406 Automotiv...
I/O Multiplexing and Considerations
5.1
20-pins: I/O Multiplexing
SOIC 20-Pin
I/O Multiplexing and Considerations
VQFN 20-Pin
5.
Pin Name (1,2)
19
16
PA0
20
17
PA1
1
18
PA2
EVOUT0
AIN2
RxD(3)
MISO
EXTCLK
AIN3
XCK(3)
SCK
WO3
XDIR(3)
SS
WO4
Other/Special
ADC0
RESET/UPDI
AIN0
AC0
USART0
SPI0
AIN1
TxD(3)
MOSI
LUT0-IN1
LUT0-IN2
19
PA3
3
20
GND
4
1
VDD
5
2
PA4
AIN4
6
3
PA5
AIN5
OUT
7
4
PA6
AIN6
AINN0
8
5
PA7
AIN7
AINP0
9
6
PB5
AIN8
AINP1
10
7
PB4
AIN9
AINN1
11
8
PB3
12
9
PB2
13
10
PB1
AIN10
XCK
14
11
PB0
AIN11
XDIR
15
12
PC0
SCK(3)
PC1
MISO(3)
MOSI(3)
16
13
17
14
PC2
18
15
PC3
TCA0
TCB0
CCL
LUT0-IN0
2
CLKOUT
TWI0
WO5
LUT1-OUT
WO2(3)
WO1(3)
TxD
EVOUT2
LUT0-OUT(3)
WO0(3)
RxD
EVOUT1
LUT0-OUT
WO
WO2
SDA
WO1
SCL
WO0
WO(3)
LUT1-OUT(3)
SS(3)
WO3(3)
LUT1-IN0
Note:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
14-pins: I/O Multiplexing
SOIC 14-Pin
5.2
Pin Name (1,2)
Other/Special
ADC0
10
PA0
RESET/UPDI
AIN0
11
PA1
12
PA2
13
PA3
14
GND
1
VDD
2
PA4
AIN4
3
PA5
AIN5
OUT
4
PA6
AIN6
AINN0
MOSI(3)
5
PA7
AIN7
AINP0
MISO(3)
6
PB3
AC0
USART0
SPI0
AIN1
TxD(3)
MOSI
LUT0-IN1
EVOUT0
AIN2
RxD(3)
MISO
LUT0-IN2
EXTCLK
AIN3
XCK(3)
SCK
WO3
XDIR(3)
SS
WO4
TCA0
TCB0
CCL
LUT0-IN0
WO5
RxD
© 2019 Microchip Technology Inc.
TWI0
Complete Datasheet
LUT0-OUT
WO
LUT1-OUT
WO0(3)
DS40002159A-page 18
ATtiny202/204/402/404/406 Automotiv...
I/O Multiplexing and Considerations
SOIC 14-Pin
...........continued
Pin Name (1,2)
Other/Special
7
PB2
EVOUT1
8
PB1
AIN10
XCK
SDA
WO1
9
PB0
AIN11
XDIR
SCL
WO0
ADC0
AC0
USART0
SPI0
TWI0
TxD
TCA0
TCB0
CCL
WO2
Note:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
8-pins: I/O Multiplexing
SOIC 8-pin
5.3
Pin Name (1,2)
Other/Special
ADC0
6
PA0
RESET/UPDI
4
PA1
5
PA2
EVOUT0
AIN2
7
PA3
EXTCLK
AIN3
OUT
8
GND
1
VDD
2
PA6
AIN6
3
PA7
AIN7
AC0
USART0
SPI0
TWI0
TCA0
AIN0
XDIR
SS
AIN1
TxD(3)
TCB0
CCL
MOSI
SDA
WO1
LUT0-IN1
RxD(3)
MISO
SCL
WO2
LUT0-IN2
XCK
SCK
AINN0
TxD
MOSI(3)
AINP0
RxD
MISO(3)
LUT0-IN0
WO0/WO3
WO0
WO0(3)
LUT0-OUT
LUT1-OUT
Note:
1. Pin names are of type Pxn, with x being the PORT instance (A, B) and n the pin number. Notation for signals is
PORTx_PINn. All pins can be used as event input.
2. All pins can be used for external interrupt, where pins Px2 and Px6 of each port have full asynchronous
detection.
3. Alternate pin positions. For selecting the alternate positions, refer to the PORTMUX documentation.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 19
ATtiny202/204/402/404/406 Automotiv...
Automotive Quality Grade
6.
Automotive Quality Grade
The devices have been manufactured according to the most stringent requirements of the international standard
ISO/TS 16949. This data sheet contains limit values extracted from the results of extensive characterization
(temperature and voltage).
The quality and reliability have been verified during regular product qualification as per AEC-Q100 grade 1 (–40°C to
+125°C) and grade 2 (–40°C to +105°C).
Table 6-1. Temperature Grade Identification for Automotive Products
Temperature (°C)
Temperature Identifier
Comments
–40 to +125
Z
Automotive temperature grade 1
–40 to +105
B
Automotive temperature grade 2
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 20
ATtiny202/204/402/404/406 Automotiv...
Memories
7.
Memories
7.1
Overview
The main memories are SRAM data memory, EEPROM data memory, and Flash program memory. In addition, the
peripheral registers are located in the I/O memory space.
Table 7-1. Physical Properties of Flash Memory
Property
ATtiny202/ATtiny204
ATtiny402/ATtiny404/ATtiny406
Size
2 KB
4 KB
Page size
64B
64B
Number of pages
32
64
Start address
0x8000
0x8000
Table 7-2. Physical Properties of SRAM
Property
ATtiny202/ATtiny204
ATtiny402/ATtiny404/ATtiny406
Size
128B
256B
Start address
0x3F80
0x3F00
Table 7-3. Physical Properties of EEPROM
Property
ATtiny202/ATtiny204
ATtiny402/ATtiny404/ATtiny406
Size
64B
128B
Page size
32B
32B
Number of pages
2
4
Start address
0x1400
0x1400
Related Links
7.9 I/O Memory
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 21
ATtiny202/204/402/404/406 Automotiv...
Memories
7.2
Memory Map
Figure 7-1. Memory Map: Flash 2/4 KB, Internal SRAM 128/256B, EEPROM 64/128B
CPU Code space
0x0000
PDI/CPU Data space
64 I/O Registers
0x0000 – 0x003F
960 Ext I/O Registers
0x0040 – 0x0FFF
NVM I/O Registers and
data
0x1000 – 0x13FF
0x1400
EEPROM 64/128B
0x1440 (For EEPROM 64B)/
0x1480 (For EEPROM 128B)
(Reserved)
0x3F80/0x3F00
Flash code
2/4KB
Internal SRAM
128/256B
0x3FFF
(Reserved)
0x8000
Flash code
2/4KB
0x87FF (For Flash 2K)/
0x8FFF (For Flash 4K)
7.3
In-System Reprogrammable Flash Program Memory
The ATtiny202/204/402/404/406 Automotive contains 2/4 KB on-chip in-system reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For write
protection, the Flash program memory space can be divided into three sections (see the illustration below):
Bootloader section, application code section, and application data section, with restricted access rights among them.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 22
ATtiny202/204/402/404/406 Automotiv...
Memories
The Program Counter (PC) is 11 bits wide to address the whole program memory. The procedure for writing Flash
memory is described in detail in the documentation of the Nonvolatile Memory Controller (NVMCTRL) peripheral.
The entire Flash memory is mapped in the memory space and is accessible with normal LD/ST instructions as well
as the LPM instruction. For LD/ST instructions, the Flash is mapped from address 0x8000. For the LPM instruction,
the Flash start address is 0x0000.
The ATtiny202/204/402/404/406 Automotive also has a CRC peripheral that is a master on the bus.
Figure 7-2. Flash and the Three Sections
FLASHSTART: 0x8000
BO OT
BOOTEND>0: 0x8000+BOOTEND*256
FLASH
AP PL ICA TIO N
CO DE
APPEND>0: 0x8000+APPEND*256
AP PL ICA TIO N
DA TA
FLASHEND
Related Links
2.1 Configuration Summary
10. Nonvolatile Memory Controller (NVMCTRL)
7.4
SRAM Data Memory
The 128B/256B SRAM is used for data storage and stack.
Related Links
9. AVR CPU
9.5.4 Stack and Stack Pointer
7.5
EEPROM Data Memory
The ATtiny202/204/402/404/406 Automotive has 64/128 bytes of EEPROM data memory, see Memory Map section.
The EEPROM memory supports single byte read and write. The EEPROM is controlled by the Nonvolatile Memory
Controller (NVMCTRL).
Related Links
7.2 Memory Map
10. Nonvolatile Memory Controller (NVMCTRL)
7.6
User Row
In addition to the EEPROM, the ATtiny202/204/402/404/406 Automotive has one extra page of EEPROM memory
that can be used for firmware settings, the User Row (USERROW). This memory supports single byte read and write
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 23
ATtiny202/204/402/404/406 Automotiv...
Memories
as the normal EEPROM. The CPU can write and read this memory as normal EEPROM and the UPDI can write and
read it as a normal EEPROM memory if the part is unlocked. The User Row can be written by the UPDI when the
part is locked. USERROW is not affected by a chip erase.
Related Links
7.2 Memory Map
10. Nonvolatile Memory Controller (NVMCTRL)
31. Unified Program and Debug Interface (UPDI)
7.7
Signature Bytes
All tinyAVR® microcontrollers have a 3-byte signature code that identifies the device. The three bytes reside in a
separate address space. For the device, the signature bytes are given in the following table.
Note: When the device is locked, only the System Information Block (SIB) can be accessed.
Table 7-4. Device ID
Device Name
Signature Bytes Address
0x00
0x01
0x02
ATtiny204
0x1E
0x91
0x22
ATtiny202
0x1E
0x91
0x23
ATtiny406
0x1E
0x92
0x25
ATtiny404
0x1E
0x92
0x26
ATtiny402
0x1E
0x92
0x27
Related Links
31.3.6 System Information Block
7.8
Memory Section Access from CPU and UPDI on Locked Device
The device can be locked so that the memories cannot be read using the UPDI. The locking protects both the Flash
(all BOOT, APPCODE, and APPDATA sections), SRAM, and the EEPROM including the FUSE data. This prevents
successful reading of application data or code using the debugger interface. Regular memory access from within the
application still is enabled.
The device is locked by writing any non-valid value to the LOCKBIT bit field in FUSE.LOCKBIT.
Table 7-5. Memory Access in Unlocked Mode (FUSE.LOCKBIT Valid)(1)
Memory Section
CPU Access
UPDI Access
Read
Write
Read
Write
SRAM
Yes
Yes
Yes
Yes
Registers
Yes
Yes
Yes
Yes
Flash
Yes
Yes
Yes
Yes
EEPROM
Yes
No
Yes
Yes
USERROW
Yes
Yes
Yes
Yes
SIGROW
Yes
No
Yes
No
Other Fuses
Yes
No
Yes
Yes
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 24
ATtiny202/204/402/404/406 Automotiv...
Memories
Table 7-6. Memory Access in Locked Mode (FUSE.LOCKBIT Invalid)(1)
Memory Section
CPU Access
UPDI Access
Read
Write
Read
Write
SRAM
Yes
Yes
No
No
Registers
Yes
Yes
No
No
Flash
Yes
Yes
No
No
EEPROM
Yes
No
No
No
USERROW
Yes
Yes
No
Yes(2)
SIGROW
Yes
No
Yes
No
Other Fuses
Yes
No
No
No
Note:
1. Read operations marked No in the tables may appear to be successful, but the data is corrupt. Hence, any
attempt of code validation through the UPDI will fail on these memory sections.
2. In Locked mode, the USERROW can be written blindly using the fuse Write command, but the current
USERROW values cannot be read out.
Important: The only way to unlock a device is a CHIPERASE, which will erase all device memories to
factory default so that no application data is retained.
Related Links
7.10.3 Fuse Summary - FUSE
7.10.4.8 LOCKBIT
31. Unified Program and Debug Interface (UPDI)
31.3.7 Enabling of KEY Protected Interfaces
7.9
I/O Memory
All ATtiny202/204/402/404/406 Automotive I/Os and peripherals are located in the I/O memory space. The I/O
address range from 0x00 to 0x3F can be accessed in a single cycle using IN and OUT instructions. The extended I/O
memory space from 0x0040 - 0x0FFF can be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring
data between the 32 general purpose working registers and the I/O memory space.
I/O registers within the address range 0x00 - 0x1F are directly bit accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
Instruction Set section for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the interrupt flags are cleared by writing a '1' to them. On ATtiny202/204/402/404/406 Automotive devices,
the CBI and SBI instructions will only operate on the specified bit, and can be used on registers containing such
interrupt flags. The CBI and SBI instructions work with registers 0x00 - 0x1F only.
General Purpose I/O Registers
The ATtiny202/204/402/404/406 Automotive devices provide four general purpose I/O registers. These registers can
be used for storing any information, and they are particularly useful for storing global variables and interrupt flags.
general purpose I/O registers, which reside in the address range 0x1C - 0x1F, are directly bit accessible using the
SBI, CBI, SBIS, and SBIC instructions.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 25
ATtiny202/204/402/404/406 Automotiv...
Memories
Related Links
7.2 Memory Map
8.1 Peripheral Module Address Map
37. Instruction Set Summary
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 26
ATtiny202/204/402/404/406 Automotiv...
Memories
7.9.1
Register Summary - GPIOR
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
GPIOR0
GPIOR1
GPIOR2
GPIOR3
7:0
7:0
7:0
7:0
7.9.2
GPIOR[7:0]
GPIOR[7:0]
GPIOR[7:0]
GPIOR[7:0]
Register Description - GPIOR
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 27
ATtiny202/204/402/404/406 Automotiv...
Memories
7.9.2.1
General Purpose I/O Register n
Name:
Offset:
Reset:
Property:
GPIOR
0x00 + n*0x01 [n=0..3]
0x00
-
These are general purpose registers that can be used to store data, such as global variables and flags, in the bit
accessible I/O memory space.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
GPIOR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – GPIOR[7:0] GPIO Register byte
7.10
Configuration and User Fuses (FUSE)
Fuses are part of the nonvolatile memory and hold factory calibration data and device configuration. The fuses are
available from device power-up. The fuses can be read by the CPU or the UPDI, but can only be programmed or
cleared by the UPDI. The configuration and calibration values stored in the fuses are written to their respective target
registers at the end of the start-up sequence.
The content of the Signature Row fuses (SIGROW) is pre-programmed and cannot be altered. SIGROW holds
information such as device ID, serial number, and calibration values.
The fuses for peripheral configuration (FUSE) are pre-programmed but can be altered by the user. Altered values in
the configuration fuse will be effective only after a Reset.
Note: When writing the fuses write all reserved bits to ‘1’.
This device provides a User Row fuse area (USERROW) that can hold application data. The USERROW can be
programmed on a locked device by the UPDI. This can be used for final configuration without having programming or
debugging capabilities enabled.
Related Links
7.10.2 Signature Row Description
7.10.4 Fuse Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 28
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.1
Signature Row Summary - SIGROW
Offset
Name
Bit Pos.
0x00
DEVICEID0
7:0
DEVICEID[7:0]
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
...
0x21
0x22
0x23
DEVICEID1
DEVICEID2
SERNUM0
SERNUM1
SERNUM2
SERNUM3
SERNUM4
SERNUM5
SERNUM6
SERNUM7
SERNUM8
SERNUM9
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
DEVICEID[7:0]
DEVICEID[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
SERNUM[7:0]
7:0
7:0
OSC16ERR3V[7:0]
OSC16ERR5V[7:0]
7.10.2
Reserved
OSC16ERR3V
OSC16ERR5V
Signature Row Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 29
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.2.1 Device ID n
Name:
Offset:
Reset:
Property:
DEVICEIDn
0x00 + n*0x01 [n=0..2]
[Device ID]
-
Each device has a device ID identifying the device and its properties; such as memory sizes, pin count, and die
revision. This can be used to identify a device and hence, the available features by software. The Device ID consists
of three bytes: SIGROW.DEVICEID[2:0].
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
DEVICEID[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – DEVICEID[7:0] Byte n of the Device ID
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 30
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.2.2 Serial Number Byte n
Name:
Offset:
Reset:
Property:
SERNUMn
0x03 + n*0x01 [n=0..9]
[device serial number]
-
Each device has an individual serial number, representing a unique ID. This can be used to identify a specific device
in the field. The serial number consists of ten bytes: SIGROW.SERNUM[9:0].
Bit
7
6
5
4
3
2
1
0
R
x
R
x
R
x
R
x
SERNUM[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 7:0 – SERNUM[7:0] Serial Number Byte n
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 31
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.2.3 OSC16 Error at 3V
Name:
Offset:
Reset:
Property:
OSC16ERR3V
0x22
[Oscillator frequency error value]
-
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
OSC16ERR3V[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – OSC16ERR3V[7:0] OSC16 Error at 3V
These registers contain the signed oscillator frequency error value when running at internal 16 MHz at 3V, as
measured during production.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 32
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.2.4 OSC16 Error at 5V
Name:
Offset:
Reset:
Property:
OSC16ERR5V
0x23
[Oscillator frequency error value]
-
Bit
7
6
5
Access
Reset
R
x
R
x
R
x
4
3
OSC16ERR5V[7:0]
R
R
x
x
2
1
0
R
x
R
x
R
x
Bits 7:0 – OSC16ERR5V[7:0] OSC16 Error at 5V
These registers contain the signed oscillator frequency error value when running at internal 16 MHz at 5V, as
measured during production.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 33
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.3
Fuse Summary - FUSE
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
...
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
WDTCFG
BODCFG
OSCCFG
7:0
7:0
7:0
7.10.4
WINDOW[3:0]
LVL[2:0]
PERIOD[3:0]
SAMPFREQ
ACTIVE[1:0]
OSCLOCK
SLEEP[1:0]
FREQSEL[1:0]
Reserved
SYSCFG0
SYSCFG1
APPEND
BOOTEND
Reserved
LOCKBIT
7:0
7:0
7:0
7:0
7:0
CRCSRC[1:0]
RSTPINCFG[1:0]
EESAVE
SUT[2:0]
APPEND[7:0]
BOOTEND[7:0]
LOCKBIT[7:0]
Fuse Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 34
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.1 Watchdog Configuration
Name:
Offset:
Reset:
Property:
Bit
7
WDTCFG
0x00
-
6
5
4
3
2
WINDOW[3:0]
Access
Reset
R
0
R
0
1
0
R
0
R
0
PERIOD[3:0]
R
0
R
0
R
0
R
0
Bits 7:4 – WINDOW[3:0] Watchdog Window Time-out Period
This value is loaded into the WINDOW bit field of the Watchdog Control A register (WDT.CTRLA) during Reset.
Bits 3:0 – PERIOD[3:0] Watchdog Time-out Period
This value is loaded into the PERIOD bit field of the Watchdog Control A register (WDT.CTRLA) during Reset.
Related Links
20.4 Register Summary - WDT
13. Reset Controller (RSTCTRL)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 35
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.2 BOD Configuration
Name:
Offset:
Reset:
Property:
BODCFG
0x01
-
The settings of the BOD will be reloaded from this Fuse after a Power-on Reset. For all other Resets, the BOD
configuration remains unchanged.
Bit
Access
Reset
7
R
0
6
LVL[2:0]
R
0
5
R
0
4
SAMPFREQ
R
0
3
2
1
ACTIVE[1:0]
R
0
0
SLEEP[1:0]
R
0
R
0
R
0
Bits 7:5 – LVL[2:0] BOD Level
This value is loaded into the LVL bit field of the BOD Control B register (BOD.CTRLB) during Reset.
Value
Name
Description
0x2
BODLEVEL2
2.6V
0x7
BODLEVEL7
4.2V
Note:
• Values in the description are typical values.
• Refer to the BOD and POR Characteristics in Electrical Characteristics for maximum and minimum values.
Bit 4 – SAMPFREQ BOD Sample Frequency
This value is loaded into the SAMPFREQ bit of the BOD Control A register (BOD.CTRLA) during Reset.
Value
Description
0x0
Sample frequency is 1 kHz
0x1
Sample frequency is 125 Hz
Bits 3:2 – ACTIVE[1:0] BOD Operation Mode in Active and Idle
This value is loaded into the ACTIVE bit field of the BOD Control A register (BOD.CTRLA) during Reset.
Value
Description
0x0
Disabled
0x1
Enabled
0x2
Sampled
0x3
Enabled with wake-up halted until BOD is ready
Bits 1:0 – SLEEP[1:0] BOD Operation Mode in Sleep
This value is loaded into the SLEEP bit field of the BOD Control A register (BOD.CTRLA) during Reset.
Value
Description
0x0
Disabled
0x1
Enabled
0x2
Sampled
0x3
Reserved
Related Links
18.4 Register Summary - BOD
13. Reset Controller (RSTCTRL)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 36
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.3 Oscillator Configuration
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
OSCLOCK
R
0
OSCCFG
0x02
-
6
5
4
3
2
1
0
FREQSEL[1:0]
R
R
0
1
Bit 7 – OSCLOCK Oscillator Lock
This fuse bit is loaded to LOCK in CLKCTRL.OSC20MCALIBB during Reset.
Value
Description
0
Calibration registers of the OSC20M oscillator are accessible
1
Calibration registers of the OSC20M oscillator are locked
Bits 1:0 – FREQSEL[1:0] Frequency Select
These bits select the operation frequency of the OSC20M oscillator and determine the respective factory calibration
values to be written to CAL20M in CLKCTRL.OSC20MCALIBA and TEMPCAL20M in CLKCTRL.OSC20MCALIBB
Value
Description
0x1
Run at 16 MHz with corresponding factory calibration
Other
Reserved
Related Links
11.4 Register Summary - CLKCTRL
13. Reset Controller (RSTCTRL)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 37
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.4 System Configuration 0
Name:
Offset:
Reset:
Property:
Bit
SYSCFG0
0x05
0xC4
-
7
6
5
4
CRCSRC[1:0]
Access
Reset
R
1
R
1
3
2
RSTPINCFG[1:0]
R
R
0
1
1
0
EESAVE
R
0
Bits 7:6 – CRCSRC[1:0] CRC Source
See the CRC description for more information about the functionality.
Value
Name
Description
00
FLASH
CRC of full Flash (boot, application code and application data)
01
BOOT
CRC of the boot section
10
BOOTAPP
CRC of application code and boot sections
11
NOCRC
No CRC
Bits 3:2 – RSTPINCFG[1:0] Reset Pin Configuration
These bits select the Reset/UPDI pin configuration.
Value
Description
0x0
GPIO
0x1
UPDI
0x2
RESET
0x3
Reserved
Note: When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively driving the
output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K
cycles after a System Reset. Enable any interrupts for this pin only after this period.
Bit 0 – EESAVE EEPROM Save During Chip Erase
If the device is locked, the EEPROM is always erased by a chip erase, regardless of this bit.
Value
Description
0
EEPROM erased during chip erase
1
EEPROM not erased under chip erase
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 38
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.5 System Configuration 1
Name:
Offset:
Reset:
Property:
Bit
7
SYSCFG1
0x06
-
6
5
4
3
Access
Reset
2
R
1
1
SUT[2:0]
R
1
0
R
1
Bits 2:0 – SUT[2:0] Start-Up Time Setting
These bits select the start-up time between power-on and code execution.
Value
Description
0x0
0 ms
0x1
1 ms
0x2
2 ms
0x3
4 ms
0x4
8 ms
0x5
16 ms
0x6
32 ms
0x7
64 ms
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 39
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.6 Application Code End
Name:
Offset:
Reset:
Property:
Bit
7
APPEND
0x07
-
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
APPEND[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – APPEND[7:0] Application Code Section End
These bits set the end of the application code section in blocks of 256 bytes. The end of the application code section
should be set as BOOT size plus application code size. The remaining Flash will be application data. A value of 0x00
defines the Flash from BOOTEND*256 to end of Flash as application code. When both FUSE.APPEND and
FUSE.BOOTEND are 0x00, the entire Flash is BOOT section.
Related Links
10. Nonvolatile Memory Controller (NVMCTRL)
10.3.1.1 Flash
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 40
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.7 Boot End
Name:
Offset:
Reset:
Property:
BOOTEND
0x08
-
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
4
3
BOOTEND[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 7:0 – BOOTEND[7:0] Boot Section End
These bits set the end of the boot section in blocks of 256 bytes. A value of 0x00 defines the whole Flash as BOOT
section. When both FUSE.APPEND and FUSE.BOOTEND are 0x00, the entire Flash is BOOT section.
Related Links
10. Nonvolatile Memory Controller (NVMCTRL)
10.3.1.1 Flash
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 41
ATtiny202/204/402/404/406 Automotiv...
Memories
7.10.4.8 Lockbits
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
LOCKBIT
0x0A
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
LOCKBIT[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LOCKBIT[7:0] Lockbits
When the part is locked, UPDI cannot access the system bus, so it cannot read out anything but CS-space.
Value
Description
0xC5
Valid key - the device is open
other
Invalid - The device is locked
Related Links
7.8 Memory Section Access from CPU and UPDI on Locked Device
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 42
ATtiny202/204/402/404/406 Automotiv...
Peripherals and Architecture
8.
Peripherals and Architecture
8.1
Peripheral Module Address Map
The address map shows the base address for each peripheral. For complete register description and summary for
each peripheral module, refer to the respective module chapters.
Table 8-1. Peripheral Module Address Map
Base Address
Name
Description
0x0000
VPORTA
Virtual Port A
0x0004
VPORTB
Virtual Port B
0x0008
VPORTC
Virtual Port C
0x001C
GPIO
General Purpose I/O registers
0x0030
CPU
CPU
0x0040
RSTCTRL
Reset Controller
0x0050
SLPCTRL
Sleep Controller
0x0060
CLKCTRL
Clock Controller
0x0080
BOD
Brown-Out Detector
0x00A0
VREF
Voltage Reference
0x0100
WDT
Watchdog Timer
0x0110
CPUINT
Interrupt Controller
0x0120
CRCSCAN
Cyclic Redundancy Check Memory Scan
0x0140
RTC
Real-Time Counter
0x0180
EVSYS
Event System
0x01C0
CCL
Configurable Custom Logic
0x0200
PORTMUX
Port Multiplexer
0x0400
PORTA
Port A Configuration
0x0420
PORTB
Port B Configuration
0x0440
PORTC
Port C Configuration
0x0600
ADC0
Analog-to-Digital Converter/Peripheral Touch Controller
0x0680
AC0
Analog Comparator 0
0x0800
USART0
Universal Synchronous Asynchronous Receiver Transmitter
0x0810
TWI0
Two-Wire Interface
0x0820
SPI0
Serial Peripheral Interface
0x0A00
TCA0
Timer/Counter Type A instance 0
0x0A40
TCB0
Timer/Counter Type B instance 0
0x0F00
SYSCFG
System Configuration
0x1000
NVMCTRL
Nonvolatile Memory Controller
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 43
ATtiny202/204/402/404/406 Automotiv...
Peripherals and Architecture
...........continued
8.2
Base Address
Name
Description
0x1100
SIGROW
Signature Row
0x1280
FUSES
Device-specific fuses
0x1300
USERROW
User Row
Interrupt Vector Mapping
Each of the interrupt vectors is connected to one peripheral instance, as shown in the table below. A peripheral can
have one or more interrupt sources, see the “Interrupt” section in the “Functional Description” of the respective
peripheral for more details on the available interrupt sources.
When the interrupt condition occurs, an Interrupt Flag (nameIF) is set in the Interrupt Flags register of the peripheral
(peripheral.INTFLAGS).
An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable bit (nameIE) in the peripheral's
Interrupt Control register (peripheral.INTCTRL).
The naming of the registers may vary slightly in some peripherals.
An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Interrupts must be enabled globally for interrupt requests to be generated.
Table 8-2. Interrupt Vector Mapping
Vector Number
Peripheral Source
Definition
0
RESET
RESET
1
CRCSCAN_NMI
NMI - Non-Maskable Interrupt from CRC
2
BOD_VLM
VLM - Voltage Level Monitor
3
PORTA_PORT
PORTA - Port A
4
PORTB_PORT
PORTB - Port B
5
PORTC_PORT
PORTC - Port C
6
RTC_CNT
RTC - Real-Time Counter
7
RTC_PIT
PIT - Periodic Interrupt Timer (in RTC peripheral)
8
TCA0_LUNF/TCA0_OVF
TCA0 - Timer Counter Type A, LUNF/OVF
9
TCA0_HUNF
TCA0, HUNF
10
TCA0_LCMP0/TCA0_CMP0
TCA0, LCMP0/CMP0
11
TCA0_LCMP1/TCA0_CMP1
TCA0, LCMP1/CMP1
12
TCA0_CMP2/TCA0_LCMP2
TCA0, LCMP2/CMP2
13
TCB0_INT
TCB0 - Timer Counter Type B
14
-
Reserved
15
-
Reserved
16
AC0_AC
AC0 – Analog Comparator
17
ADC0_RESRDY
ADC0 – Analog-to-Digital Converter, RESRDY
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 44
ATtiny202/204/402/404/406 Automotiv...
Peripherals and Architecture
...........continued
Vector Number
Peripheral Source
Definition
18
ADC0_WCOMP
ADC0, WCOMP
19
TWI0_TWIS
TWI0 - Two-Wire Interface/I2C, TWIS
20
TWI0_TWIM
TWI0, TWIM
21
SPI0_INT
SPI0 - Serial Peripheral Interface
22
USART0_RXC
USART0 - Universal Asynchronous Receiver-Transmitter, RXC
23
USART0_DRE
USART0, DRE
24
USART0_TXC
USART0, TXC
25
NVMCTRL_EE
NVM - Nonvolatile Memory
Related Links
10. Nonvolatile Memory Controller (NVMCTRL)
17. I/O Pin Configuration (PORT)
23. Real-Time Counter (RTC)
25. Serial Peripheral Interface (SPI)
24. Universal Synchronous and Asynchronous Receiver and Transmitter (USART)
26. Two-Wire Interface (TWI)
27. Cyclic Redundancy Check Memory Scan (CRCSCAN)
21. 16-bit Timer/Counter Type A (TCA)
22. 16-bit Timer/Counter Type B (TCB)
29. Analog Comparator (AC)
30. Analog-to-Digital Converter (ADC)
8.3
System Configuration (SYSCFG)
The system configuration contains the revision ID of the part. The revision ID is readable from the CPU, making it
useful for implementing application changes between part revisions.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 45
ATtiny202/204/402/404/406 Automotiv...
Peripherals and Architecture
8.3.1
Register Summary - SYSCFG
Offset
Name
Bit Pos.
0x00
0x01
Reserved
REVID
7:0
8.3.2
REVID[7:0]
Register Description - SYSCFG
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 46
ATtiny202/204/402/404/406 Automotiv...
Peripherals and Architecture
8.3.2.1
Device Revision ID Register
Name:
Offset:
Reset:
Property:
REVID
0x01
[revision ID]
-
This register is read-only and displays the device revision ID.
Bit
7
6
5
4
3
2
1
0
R
R
R
R
REVID[7:0]
Access
Reset
R
R
R
R
Bits 7:0 – REVID[7:0] Revision ID
These bits contain the device revision. 0x00 = A, 0x01 = B, and so on.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 47
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
9.
AVR® CPU
9.1
Features
•
•
•
•
•
•
•
•
9.2
8-Bit, High-Performance AVR RISC CPU:
– 135 instructions
– Hardware multiplier
32 8-Bit Registers Directly Connected to the Arithmetic Logic Unit (ALU)
Stack in RAM
Stack Pointer Accessible in I/O Memory Space
Direct Addressing of up to 64 KB of Unified Memory:
– Entire Flash accessible with all LD/ST instructions
True 16-Bit Access to 16-Bit I/O Registers
Efficient Support for 8-, 16-, and 32-Bit Arithmetic
Configuration Change Protection for System Critical Features
Overview
All AVR devices use the 8-bit AVR CPU. The CPU is able to access memories, perform calculations, control
peripherals, and execute instructions in the program memory. Interrupt handling is described in a separate section.
Related Links
7. Memories
10. Nonvolatile Memory Controller (NVMCTRL)
14. CPU Interrupt Controller (CPUINT)
9.3
Architecture
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for
program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction
is being executed, the next instruction is prefetched from the program memory. This enables instructions to be
executed on every clock cycle.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 48
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
Figure 9-1. AVR® CPU Architecture
Register file
R31 (ZH)
R29 (YH)
R27 (XH)
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
R30 (ZL)
R28 (YL)
R26 (XL)
R24
R22
R20
R18
R16
R14
R12
R10
R8
R6
R4
R2
R0
Program
Counter
Flash Program
Memory
Instruction
Register
Instruction
Decode
Data Memory
Stack
Pointer
STATUS
Register
ALU
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant
and a register. Also, single-register operations can be executed in the ALU. After an arithmetic operation, the
STATUS register is updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit Address Pointers for program and data
space addressing, enabling efficient address calculations.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 49
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
The program memory bus is connected to Flash, and the first program memory Flash address is 0x0000.
The data memory space is divided into I/O registers, SRAM, EEPROM, and Flash.
All I/O status and control registers reside in the lowest 4 KB addresses of the data memory. This is referred to as the
I/O memory space. The lowest 64 addresses are accessed directly with single-cycle IN/OUT instructions, or as the
data space locations from 0x00 to 0x3F. These addresses can be accessed using load (LD/LDS/LDD) and store
(ST/STS/STD) instructions. The lowest 32 addresses can even be accessed with single-cycle SBI/CBI instructions
and SBIS/SBIC instructions. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. The I/O
registers here must be accessed as data space locations using load and store instructions.
Data addresses 0x1000 to 0x1800 are reserved for memory mapping of fuses, the NVM controller and EEPROM.
The addresses from 0x1800 to 0x7FFF are reserved for other memories, such as SRAM.
The Flash is mapped in the data space from 0x8000 and above. The Flash can be accessed with all load and store
instructions by using addresses above 0x8000. The LPM instruction accesses the Flash similar to the code space,
where the Flash starts at address 0x0000.
For a summary of all AVR instructions, refer to the Instruction Set Summary section. For details of all AVR
instructions, refer to http://www.microchip.com/design-centers/8-bit.
Related Links
10. Nonvolatile Memory Controller (NVMCTRL)
7. Memories
37. Instruction Set Summary
9.4
Arithmetic Logic Unit (ALU)
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers, or between a constant
and a register. Also, single-register operations can be executed.
The ALU operates in direct connection with all 32 general purpose registers. Arithmetic operations between general
purpose registers or between a register and an immediate are executed in a single clock cycle, and the result is
stored in the register file. After an arithmetic or logic operation, the Status register (CPU.SREG) is updated to reflect
information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic are supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
9.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports
different variations of signed and unsigned integer and fractional numbers:
•
•
•
•
Multiplication of signed/unsigned integers
Multiplication of signed/unsigned fractional numbers
Multiplication of a signed integer with an unsigned integer
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
9.5
Functional Description
9.5.1
Program Flow
After Reset, the CPU will execute instructions from the lowest address in the Flash program memory, 0x0000. The
Program Counter (PC) addresses the next instruction to be fetched.
Program flow is supported by conditional and unconditional JUMP and CALL instructions, capable of addressing the
whole address space directly. Most AVR instructions use a 16-bit word format, and a limited number use a 32-bit
format.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 50
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
During interrupts and subroutine calls, the return address PC is stored on the stack as a Word Pointer. The stack is
allocated in the general data SRAM, and consequently, the stack size is only limited by the total SRAM size and the
usage of the SRAM. After Reset, the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP
is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas.
The data SRAM can easily be accessed through the five different addressing modes supported by the AVR CPU.
9.5.2
Instruction Execution Timing
The AVR CPU is clocked by the CPU clock: CLK_CPU. No internal clock division is applied. The figure below shows
the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access
register file concept. This is the basic pipelining concept enabling up to 1 MIPS/MHz performance with high efficiency.
Figure 9-2. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
The following figure shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed and the result is stored in the destination register.
Figure 9-3. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
9.5.3
Status Register
The Status register (CPU.SREG) contains information about the result of the most recently executed arithmetic or
logic instruction. This information can be used for altering program flow in order to perform conditional operations.
CPU.SREG is updated after all ALU operations, as specified in the Instruction Set Summary. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
CPU.SREG is not automatically stored/restored when entering/returning from an Interrupt Service Routine.
Maintaining the Status register between context switches must, therefore, be handled by user-defined software.
CPU.SREG is accessible in the I/O memory space.
Related Links
37. Instruction Set Summary
9.5.4
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. Also, it can be used for storing
temporary data. The Stack Pointer (SP) always points to the top of the stack. The SP is defined by the Stack Pointer
bits in the Stack Pointer register (CPU.SP). The CPU.SP is implemented as two 8-bit registers that are accessible in
the I/O memory space.
Data is pushed and popped from the stack using the PUSH and POP instructions. The stack grows from higher to
lower memory locations. This implies that pushing data onto the stack decreases the SP, and popping data off the
stack increases the SP. The Stack Pointer is automatically set to the highest address of the internal SRAM after
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 51
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
Reset. If the stack is changed, it must be set to point above address 0x2000, and it must be defined before any
subroutine calls are executed and before interrupts are enabled.
During interrupts or subroutine calls the return address is automatically pushed on the stack as a Word Pointer and
the SP is decremented by '2'. The return address consists of two bytes and the Least Significant Byte is pushed on
the stack first (at the higher address). As an example, a Byte Pointer return address of 0x0006 is saved on the stack
as 0x0003 (shifted one bit to the right), pointing to the fourth 16-bit instruction word in the program memory. The
return address is popped off the stack with RETI (when returning from interrupts) and RET (when returning from
subroutine calls) and the SP is incremented by two.
The SP is decremented by '1' when data is pushed on the stack with the PUSH instruction, and incremented by '1'
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the Stack Pointer from software, a write to SPL will automatically disable
interrupts for up to four instructions or until the next I/O memory write.
9.5.5
Register File
The register file consists of 32 8-bit general purpose working registers with single clock cycle access time. The
register file supports the following input/output schemes:
•
•
•
•
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit Address Register Pointers for data space addressing, enabling
efficient address calculations.
Figure 9-4. AVR® CPU General Purpose Working Registers
0 Addr.
7
0x00
R0
0x01
R1
0x02
R2
...
R13
R14
R15
R16
R17
...
0x0D
0x0E
0x0F
0x10
0x11
X-register Low Byte
0x1A
X-register High Byte
0x1B
Y-register Low Byte
0x1C
Y-register High Byte
0x1D
Z-register Low Byte
0x1E
Z-register High Byte
0x1F
The register file is located in a separate address space and is, therefore, not accessible through instructions
operation on data memory.
R26
R27
R28
R29
R30
R31
9.5.5.1
The X-, Y-, and Z-Registers
Registers R26...R31 have added functions besides their general purpose usage.
These registers can form 16-bit Address Pointers for addressing data memory. These three address registers are
called the X-register, Y-register, and Z-register. Load and store instructions can use all X-, Y-, and Z-registers, while
the LPM instructions can only use the Z-register. Indirect calls and jumps (ICALL and IJMP) also use the Z-register.
Refer to the instruction set or Instruction Set Summary for more information about how the X-, Y-, and Z-registers are
used.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 52
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
Figure 9-5. The X-, Y-, and Z-Registers
Bit (individually)
7
X-register
15
Bit (individually)
7
Y-register
Bit (individually)
R29
7
7
R31
8
7
0
7
8
7
0
0
7
8
7
0
R28
0
YL
ZH
15
R26
XL
YH
15
Z-register
Bit (Z-register)
0
XH
Bit (X-register)
Bit (Y-register)
R27
0
R30
0
ZL
0
The lowest register address holds the Least Significant Byte (LSB), and the highest register address holds the Most
Significant Byte (MSB). In the different addressing modes, these address registers function as fixed displacement,
automatic increment, and automatic decrement.
Related Links
37. Instruction Set Summary
9.5.6
Accessing 16-Bit Registers
The AVR data bus is 8-bits wide, and so accessing 16-bit registers requires atomic operations. These registers must
be byte accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary
register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then
written into the temporary register. When the high byte of the 16-bit register is written, the temporary register is
copied into the low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register
is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as
the low byte is read. When the high byte is read, it is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or
writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an
atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.
The temporary registers can be read and written directly from user software.
9.5.7
Configuration Change Protection (CCP)
System critical I/O register settings are protected from accidental modification. Flash self-programming (via store to
NVM controller) is protected from accidental execution. This is handled globally by the Configuration Change
Protection (CCP) register.
Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible after the CPU
writes a signature to the CCP register. The different signatures are listed in the description of the CCP register
(CPU.CCP).
There are two modes of operation: one for protected I/O registers, and one for the protected self-programming.
Related Links
9.7.1 CCP
9.5.7.1
Sequence for Write Operation to Configuration Change Protected I/O Registers
In order to write to registers protected by CCP, these steps are required:
1.
2.
The software writes the signature that enables change of protected I/O registers to the CCP bit field in the
CPU.CCP register.
Within four instructions, the software must write the appropriate data to the protected register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 53
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
Most protected registers also contain a write enable/change enable/lock bit. This bit must be written to '1' in
the same operation as the data are written.
The protected change is immediately disabled if the CPU performs write operations to the I/O register or data
memory, if load or store accesses to Flash, NVMCTRL, EEPROM are conducted, or if the SLEEP instruction is
executed.
9.5.7.2
Sequence for Execution of Self-Programming
In order to execute self-programming (the execution of writes to the NVM controller's command register), the
following steps are required:
1.
2.
The software temporarily enables self-programming by writing the SPM signature to the CCP register
(CPU.CCP).
Within four instructions, the software must execute the appropriate instruction. The protected change is
immediately disabled if the CPU performs accesses to the Flash, NVMCTRL, or EEPROM, or if the SLEEP
instruction is executed.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the configuration
change enable period. Any interrupt request (including non-maskable interrupts) during the CCP period will set the
corresponding interrupt flag as normal, and the request is kept pending. After the CCP period is completed, any
pending interrupts are executed according to their level and priority.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 54
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
9.6
Offset
0x00
...
0x03
0x04
0x05
...
0x0C
Register Summary - CPU
Name
Reserved
CCP
7:0
CCP[7:0]
7:0
15:8
7:0
SP[7:0]
SP[15:8]
Reserved
0x0D
SP
0x0F
SREG
9.7
Bit Pos.
I
T
H
S
V
N
Z
C
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 55
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
9.7.1
Configuration Change Protection
Name:
Offset:
Reset:
Property:
Bit
7
CCP
0x04
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CCP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CCP[7:0] Configuration Change Protection
Writing the correct signature to this bit field allows changing protected I/O registers or executing protected
instructions within the next four CPU instructions executed.
All interrupts are ignored during these cycles. After these cycles, interrupts will automatically be handled again by the
CPU, and any pending interrupts will be executed according to their level and priority.
When the protected I/O register signature is written, CCP[0] will read as '1' as long as the CCP feature is enabled.
When the protected self-programming signature is written, CCP[1] will read as '1' as long as the CCP feature is
enabled.
CCP[7:2] will always read as zero.
Value
Name
Description
0x9D
SPM
Allow Self-Programming
0xD8
IOREG
Un-protect protected I/O registers
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 56
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
9.7.2
Stack Pointer
Name:
Offset:
Reset:
Property:
SP
0x0D
0xxxxx
-
The CPU.SP holds the Stack Pointer (SP) that points to the top of the stack. After Reset, the Stack Pointer points to
the highest internal SRAM address.
Only the number of bits required to address the available data memory including external memory (up to 64 KB) is
implemented for each device. Unused bits will always read as zero.
The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
To prevent corruption when updating the SP from software, a write to CPU.SPL will automatically disable interrupts
for the next four instructions or until the next I/O memory write.
Bit
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
SP[15:8]
Access
Reset
Bit
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
SP[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 15:8 – SP[15:8] Stack Pointer High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – SP[7:0] Stack Pointer Low Byte
These bits hold the LSB of the 16-bit register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 57
ATtiny202/204/402/404/406 Automotiv...
AVR® CPU
9.7.3
STATUS Register
Name:
Offset:
Reset:
Property:
SREG
0x0F
0x00
-
The STATUS register contains information about the result of the most recently executed arithmetic or logic
instruction. For details about the bits in this register and how they are affected by the different instructions, see the
Instruction Set Summary.
Bit
Access
Reset
7
I
R/W
0
6
T
R/W
0
5
H
R/W
0
4
S
R/W
0
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
Bit 7 – I Global Interrupt Enable
Writing a '1' to this bit enables interrupts on the device.
Writing a '0' to this bit disables interrupts on the device, independent of the individual interrupt enable settings of the
peripherals.
This bit is not cleared by hardware after an interrupt has occurred.
This bit can be set and cleared by software with the SEI and CLI instructions.
Changing the I flag through the I/O register results in a one-cycle Wait state on the access.
Bit 6 – T Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for the operated bit.
A bit from a register in the register file can be copied into this bit by the BST instruction, and this bit can be copied into
a bit in a register in the register file by the BLD instruction.
Bit 5 – H Half Carry Flag
This bit indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.
Bit 4 – S Sign Bit, S = N ⊕ V
The sign bit (S) is always an exclusive or (xor) between the negative flag (N) and the two’s complement overflow flag
(V).
Bit 3 – V Two’s Complement Overflow Flag
The two’s complement overflow flag (V) supports two’s complement arithmetic.
Bit 2 – N Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation.
Bit 1 – Z Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation.
Bit 0 – C Carry Flag
The carry flag (C) indicates a carry in an arithmetic or logic operation.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 58
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.
Nonvolatile Memory Controller (NVMCTRL)
10.1
Features
•
•
•
•
•
•
10.2
Unified Memory
In-System Programmable
Self-Programming and Boot Loader Support
Configurable Sections for Write Protection:
– Boot section for boot loader code or application code
– Application code section for application code
– Application data section for application code or data storage
Signature Row for Factory-Programmed Data:
– ID for each device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
User Row for Application Data:
– 32 bytes in size
– Can be read and written from software
– Can be written from UPDI on locked device
– Content is kept after chip erase
Overview
The NVM Controller (NVMCTRL) is the interface between the device, the Flash, and the EEPROM. The Flash and
EEPROM are reprogrammable memory blocks that retain their values even when not powered. The Flash is mainly
used for program storage, and can be used for data storage. The EEPROM is used for data storage and can be
programmed while the CPU is running the program from the Flash.
10.2.1
Block Diagram
Figure 10-1. NVMCTRL Block Diagram
NVM Block
Program Memory Bus
Flash
NVMCTRL
Data Memory Bus
EEPROM
Signature Row
User Row
10.2.2
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 59
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
Table 10-1. NVMCTRL System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
Yes
CPUINT
Events
No
-
Debug
Yes
UPDI
Related Links
10.2.2.1 Clocks
10.2.2.5 Debug Operation
10.2.2.3 Interrupts
10.2.2.1 Clocks
This peripheral always runs on the CPU clock (CLK_CPU). It will request this clock also in sleep modes if a write/
erase is ongoing.
Related Links
11. Clock Controller (CLKCTRL)
10.2.2.2 I/O Lines and Connections
Not applicable.
10.2.2.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
10.2.2.4 Events
Not applicable.
10.2.2.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
Related Links
31. Unified Program and Debug Interface (UPDI)
10.3
Functional Description
10.3.1
Memory Organization
10.3.1.1 Flash
The Flash is divided into a set of pages. A page is the basic unit addressed when programming the Flash. It is only
possible to write or erase a whole page at a time. One page consists of several words.
The Flash can be divided into three sections in blocks of 256 bytes for different security. The three different sections
are BOOT, Application Code (APPCODE), and Application Data (APPDATA).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 60
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
Figure 10-2. Flash Sections
FLASHSTART: 0x8000
BO OT
BOOTEND>0: 0x8000+BOOTEND*256
AP PL ICA TIO N
CO DE
APPEND>0: 0x8000+APPEND*256
AP PL ICA TIO N
DA TA
Section Sizes
The sizes of these sections are set by the Boot Section End fuse (FUSE.BOOTEND) and Application Code Section
End fuse (FUSE.APPEND).
The fuses select the section sizes in blocks of 256 bytes. As shown in Figure 10-2, the BOOT section stretches from
the start of the Flash until BOOTEND. The APPCODE section runs from BOOTEND until APPEND. The remaining
area is the APPDATA section. If APPEND is written to 0, the APPCODE section runs from BOOTEND to the end of
Flash (removing the APPDATA section). If BOOTEND and APPEND are written to 0, the entire Flash is regarded as
BOOT section. APPEND should either be set to 0 or a value greater or equal than BOOTEND.
Table 10-2. Setting Up Flash Sections
BOOTEND
APPEND
BOOT Section
APPCODE Section
APPDATA Section
0
0
0 to FLASHEND
-
-
>0
0
0 to 256*BOOTEND
256*BOOTEND to
FLASHEND
-
>0
==
BOOTEND
0 to 256*BOOTEND
-
256*BOOTEND to
FLASHEND
>0
>
BOOTEND
0 to 256*BOOTEND
256*BOOTEND to
256*APPEND
256*APPEND to
FLASHEND
Note:
• See also the 7.10.4.7 BOOTEND and 7.10.4.6 APPEND descriptions.
• Interrupt vectors are by default located after the BOOT section. This can be changed in the interrupt controller.
Refer to 14.3.2.2 Interrupt Vector Locations.
If FUSE.BOOTEND is written to 0x04 and FUSE.APPEND is written to 0x08, the first 4*256 bytes
will be BOOT, the next 4*256 bytes will be APPCODE, and the remaining Flash will be APPDATA.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 61
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
Inter-Section Write Protection
Between the three Flash sections, a directional write protection is implemented:
• Code in the BOOT section can write to APPCODE and APPDATA
• Code in APPCODE can write to APPDATA
• Code in APPDATA cannot write to Flash or EEPROM
Boot Section Lock and Application Code Section Write Protection
The two lockbits (APCWP and BOOTLOCK in NVMCTRL.CTRLB) can be set to lock further updates of the
respective APPCODE or BOOT section until the next Reset.
The CPU can never write to the BOOT section. NVMCTRL_CTRLB.BOOTLOCK prevents reads and execution of
code from the BOOT section.
10.3.1.2 EEPROM
The EEPROM is divided into a set of pages where one page consists of multiple bytes. The EEPROM has byte
granularity on erase write. Within one page only the bytes marked to be updated will be erased/written. The byte is
marked by writing a new value to the page buffer for that address location.
10.3.1.3 User Row
The User Row is one extra page of EEPROM. This page can be used to store various data, such as calibration/
configuration data and serial numbers. This page is not erased by a chip erase. The User Row is written as normal
EEPROM, but in addition, it can be written through UPDI on a locked device.
10.3.2
Memory Access
10.3.2.1 Read
Reading of the Flash and EEPROM is done by using load instructions with an address according to the memory map.
Reading any of the arrays while a write or erase is in progress will result in a bus wait, and the instruction will be
suspended until the ongoing operation is complete.
10.3.2.2 Page Buffer Load
The page buffer is loaded by writing directly to the memories as defined in the memory map. Flash, EEPROM and
User Row share the same page buffer so only one section can be programmed at one time. The Least Significant bits
(LSb) of the address are used to select where in the page buffer the data is written. The resulting data will be a binary
and operation between the new and the previous content of the page buffer. The page buffer will automatically be
erased (all bits set) after:
• A device Reset
• Any page write or erase operation
• A Clear Page Buffer command
• The device wakes up from any sleep mode
10.3.2.3 Programming
For page programming, filling the page buffer and writing the page buffer into Flash, User Row, and EEPROM are
two separate operations.
Before programming a Flash page with the data in the page buffer, the Flash page must be erased. The page buffer
is also erased when the device enters sleep mode. Programming an unerased Flash page will corrupt its content.
The Flash can either be written with the erase and write separately, or one command handling both:
Alternative 1:
• Fill the page buffer
• Write the page buffer to Flash with the Erase/Write Page command
Alternative 2:
• Write to a location in the page to set up the address
• Perform a Erase Page command
• Fill the page buffer
• Perform a Write Page command
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 62
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
The NVM command set supports both a single erase and write operation, and split Page Erase and Page Write
commands. This split commands enable shorter programming time for each command, and the erase operations can
be done during non-time-critical programming execution.
The EEPROM programming is similar, but only the bytes updated in the page buffer will be written or erased in the
EEPROM.
10.3.2.4 Commands
Reading of the Flash/EEPROM and writing of the page buffer is handled with normal load/store instructions. Other
operations, such as writing and erasing the memory arrays, are handled by commands in the NVM.
To execute a command in the NVM:
1. Confirm that any previous operation is completed by reading the Busy Flags (EEBUSY and FBUSY) in the
NVMCTRL.STATUS register.
2. Write the NVM command unlock to the Configuration Change Protection register in the CPU (CPU.CCP).
3. Write the desired command value to the CMD bits in the Control A register (NVMCTRL.CTRLA) within the next
four instructions.
10.3.2.4.1 Write Command
The Write command of the Flash controller writes the content of the page buffer to the Flash or EEPROM.
If the write is to the Flash, the CPU will stop executing code as long as the Flash is busy with the write operation. If
the write is to the EEPROM, the CPU can continue executing code while the operation is ongoing.
The page buffer will be automatically cleared after the operation is finished.
10.3.2.4.2 Erase Command
The Erase command erases the current page. There must be one byte written in the page buffer for the Erase
command to take effect.
For erasing the Flash, first, write to one address in the desired page, then execute the command. The whole page in
the Flash will then be erased. The CPU will be halted while the erase is ongoing.
For the EEPROM, only the bytes written in the page buffer will be erased when the command is executed. To erase a
specific byte, write to its corresponding address before executing the command. To erase a whole page all the bytes
in the page buffer have to be updated before executing the command. The CPU can continue running code while the
operation is ongoing.
The page buffer will be automatically cleared after the operation is finished.
10.3.2.4.3 Erase-Write Operation
The Erase/Write command is a combination of the Erase and Write command, but without clearing the page buffer
after the Erase command: The erase/write operation first erases the selected page, then it writes the content of the
page buffer to the same page.
When executed on the Flash, the CPU will be halted when the operations are ongoing. When executed on EEPROM,
the CPU can continue executing code.
The page buffer will be automatically cleared after the operation is finished.
10.3.2.4.4 Page Buffer Clear Command
The Page Buffer Clear command clears the page buffer. The contents of the page buffer will be all ones after the
operation. The CPU will be halted when the operation executes (seven CPU cycles).
10.3.2.4.5 Chip Erase Command
The Chip Erase command erases the Flash and the EEPROM. The EEPROM is unaltered if the EEPROM Save
During Chip Erase (EESAVE) fuse in FUSE.SYSCFG0 is set. The Flash will not be protected by Boot Section Lock
(BOOTLOCK) or Application Code Section Write Protection (APCWP) in NVMCTRL.CTRLB. The memory will be all
ones after the operation.
10.3.2.4.6 EEPROM Erase Command
The EEPROM Erase command erases the EEPROM. The EEPROM will be all ones after the operation. The CPU will
be halted while the EEPROM is being erased.
10.3.2.4.7 Fuse Write Command
The Fuse Write command writes the fuses. It can only be used by the UPDI, the CPU cannot start this command.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 63
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
Follow this procedure to use this command:
• Write the address of the fuse to the Address register (NVMCTRL.ADDR)
• Write the data to be written to the fuse to the Data register (NVMCTRL.DATA)
• Execute the Fuse Write command.
• After the fuse is written, a Reset is required for the updated value to take effect.
For reading fuses, use a regular read on the memory location.
10.3.3
Preventing Flash/EEPROM Corruption
During periods of low VDD, the Flash program or EEPROM data can be corrupted if the supply voltage is too low for
the CPU and the Flash/EEPROM to operate properly. These issues are the same as for board level systems using
Flash/EEPROM, and the same design solutions should be applied.
A Flash/EEPROM corruption can be caused by two situations when the voltage is too low: First, a regular write
sequence to the Flash requires a minimum voltage to operate correctly. Also, the CPU itself can execute instructions
incorrectly when the supply voltage is too low. See the Electrical Characteristics chapter for Maximum Frequency vs.
VDD.
Flash/EEPROM corruption can be avoided by these measures:
Keep the device in Reset during periods of insufficient power supply voltage. This can be done by enabling the
internal Brown-Out Detector (BOD).
The voltage level monitor in the BOD can be used to prevent starting a write to the EEPROM close to the BOD level.
If the detection levels of the internal BOD does not match the required detection level, an external low VDD Reset
protection circuit can be used. If a Reset occurs while a write operation is ongoing, the write operation will be aborted.
Related Links
32.3 General Operating Ratings
18. Brown-Out Detector (BOD)
10.3.4
Interrupts
Table 10-3. Available Interrupt Vectors and Sources
Offset
Name
Vector Description
Conditions
0x00
EEREADY
NVM
The EEPROM is ready for new write/erase operations.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (NVMCTRL.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt Enable
register (NVMCTRL.INTEN).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
10.3.5
Sleep Mode Operation
If there is no ongoing write operation, the NVMCTRL will enter sleep mode when the system enters sleep mode.
If a write operation is ongoing when the system enters a sleep mode, the NVM block, the NVM Controller, and the
system clock will remain on until the write is finished. This is valid for all sleep modes, including Power-Down Sleep
mode.
The EEPROM Ready interrupt will wake-up the device only from Idle Sleep mode.
The page buffer is cleared when waking up from Sleep.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 64
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.3.6
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a
certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four
CPU instructions.
It is possible to try writing to these registers any time, but the values are not altered.
The following registers are under CCP:
Table 10-4. NVMCTRL - Registers under Configuration Change Protection
Register
Key
NVMCTRL.CTRLA
SPM
Related Links
9.5.7.2 Sequence for Execution of Self-Programming
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 65
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.4
Register Summary - NVMCTRL
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
CTRLA
CTRLB
STATUS
INTCTRL
INTFLAGS
Reserved
7:0
7:0
7:0
7:0
7:0
0x06
DATA
0x08
ADDR
10.5
7:0
15:8
7:0
15:8
WRERROR
CMD[2:0]
BOOTLOCK
EEBUSY
APCWP
FBUSY
EEREADY
EEREADY
DATA[7:0]
DATA[15:8]
ADDR[7:0]
ADDR[15:8]
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 66
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
R/W
0
1
CMD[2:0]
R/W
0
0
R/W
0
Bits 2:0 – CMD[2:0] Command
Write this bit field to issue a command. The Configuration Change Protection key for self-programming (SPM) has to
be written within four instructions before this write.
Value
Name
Description
0x0
No command
0x1
WP
Write page buffer to memory (NVMCTRL.ADDR selects which memory)
0x2
ER
Erase page (NVMCTRL.ADDR selects which memory)
0x3
ERWP Erase and write page (NVMCTRL.ADDR selects which memory)
0x4
PBC
Page buffer clear
0x5
CHER Chip erase: erase Flash and EEPROM (unless EESAVE in FUSE.SYSCFG is '1')
0x6
EEER
EEPROM Erase
0x7
WFU
Write fuse (only accessible through UPDI)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 67
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
-
6
5
4
3
Access
Reset
2
1
BOOTLOCK
R/W
0
0
APCWP
R/W
0
Bit 1 – BOOTLOCK Boot Section Lock
Writing a '1' to this bit locks the boot section from read and instruction fetch.
If this bit is '1', a read from the boot section will return '0'. A fetch from the boot section will also return 0 as
instruction.
This bit can be written from the boot section only. It can only be cleared to '0' by a Reset.
This bit will take effect only when the boot section is left the first time after the bit is written.
Bit 0 – APCWP Application Code Section Write Protection
Writing a '1' to this bit protects the application code section from further writes.
This bit can only be written to '1'. It is cleared to '0' only by Reset.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 68
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.3
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x02
0x00
-
6
5
4
3
Access
Reset
2
WRERROR
R
0
1
EEBUSY
R
0
0
FBUSY
R
0
Bit 2 – WRERROR Write Error
This bit will read '1' when a write error has happened. A write error could be writing to different sections before doing
a page write or writing to a protected area. This bit is valid for the last operation.
Bit 1 – EEBUSY EEPROM Busy
This bit will read '1' when the EEPROM is busy with a command.
Bit 0 – FBUSY Flash Busy
This bit will read '1' when the Flash is busy with a command.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 69
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
EEREADY
R/W
0
Bit 0 – EEREADY EEPROM Ready Interrupt
Writing a '1' to this bit enables the interrupt, which indicates that the EEPROM is ready for new write/erase
operations.
This is a level interrupt that will be triggered only when the EEREADY flag in the INTFLAGS register is set to zero.
Thus, the interrupt should not be enabled before triggering an NVM command, as the EEREADY flag will not be set
before the NVM command issued. The interrupt should be disabled in the interrupt handler.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 70
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.5
Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x04
0x00
-
6
5
4
3
Access
Reset
2
1
0
EEREADY
R/W
0
Bit 0 – EEREADY EEREADY Interrupt Flag
Interrupt flag for the EEPROM interrupt. This bit is cleared by writing a '1' to it. When this interrupt is enabled, it will
immediately request an interrupt, and it will continue to request interrupts - even if no EEPROM writes are initiated.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 71
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.6
Data
Name:
Offset:
Reset:
Property:
DATA
0x06
0x00
-
The NVMCTRL.DATAL and NVMCTRL.DATAH register pair represents the 16-bit value, NVMCTRL.DATA. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset
+ 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DATA[15:0] Data Register
This register is used by the UPDI for fuse write operations.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 72
ATtiny202/204/402/404/406 Automotiv...
Nonvolatile Memory Controller (NVMCTRL)
10.5.7
Address
Name:
Offset:
Reset:
Property:
ADDR
0x08
0x00
-
The NVMCTRL.ADDRL and NVMCTRL.ADDRH register pair represents the 16-bit value, NVMCTRL.ADDR. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset
+ 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADDR[15:0] Address
The Address register contains the address to the last memory location that has been updated.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 73
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.
Clock Controller (CLKCTRL)
11.1
Features
•
•
•
•
11.2
All clocks and clock sources are automatically enabled when requested by peripherals
Internal Oscillators:
– 16 MHz Oscillator (OSC20M)
– 32 KHz Ultra Low-Power Oscillator (OSCULP32K)
External Clock Options:
– External clock
Main Clock Features:
– Safe run-time switching
– Prescaler with 1x to 64x division in 12 different settings
Overview
The Clock Controller peripheral (CLKCTRL) controls, distributes, and prescales the clock signals from the available
oscillators. The CLKCTRL supports internal and external clock sources.
The CLKCTRL is based on an automatic clock request system, implemented in all peripherals on the device. The
peripherals will automatically request the clocks needed. If multiple clock sources are available, the request is routed
to the correct clock source.
The Main Clock (CLK_MAIN) is used by the CPU, RAM, and the I/O bus. The main clock source can be selected and
prescaled. Some peripherals can share the same clock source as the main clock, or run asynchronously to the main
clock domain.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 74
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.2.1
Block Diagram - CLKCTRL
Figure 11-1. ATtiny202/402 Automotive/ATtiny204/404 Automotive
NVM
RAM
CLK_CPU
RTC
Other
Peripherals
CPU
CLK_PER
WDT
INT
BOD
PRESCALER
CLK_RTC
CLK_WDT
CLK_BOD
Main Clock Prescaler
CLK_MAIN
RTC
CLKSEL
Main Clock Switch
DIV32
OSCULP32K
OSC20M
OSC20M
int. Oscillator
32 kHz ULP
Int. Oscillator
© 2019 Microchip Technology Inc.
EXTCLK
Complete Datasheet
DS40002159A-page 75
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
Figure 11-2. ATtiny406 Automotive
NVM
RAM
CPU
CLK_CPU
CLKOUT
CLK_PER
RTC
Other
Peripherals
WDT
INT
BOD
PRESCALER
CLK_RTC
CLK_WDT
CLK_BOD
Main Clock Prescaler
CLK_MAIN
RTC
CLKSEL
Main Clock Switch
DIV32
OSCULP32K
OSC20M
OSC20M
int. Oscillator
32 kHz ULP
Int. Oscillator
EXTCLK
The clock system consists of the Main Clock and other asynchronous clocks:
• Main Clock
This clock is used by the CPU, RAM, Flash, the IO bus and all peripherals connected to the IO bus. It is always
running in Active and Idle sleep mode, and can be running in Standby sleep mode if requested.
•
The main clock CLK_MAIN is prescaled and distributed by the Clock Controller:
• CLK_CPU is used by the CPU, SRAM and the NVMCTRL peripheral to access the non-volatile memory
• CLK_PER is used by all peripherals that are not listed under asynchronous clocks.
Clocks running asynchronously to the Main Clock domain:
– CLK_RTC is used by the RTC/PIT. It will be requested when the RTC/PIT is enabled. The clock source for
CLK_RTC should only be changed if the peripheral is disabled.
– CLK_WDT is used by the WDT. It will be requested when the WDT is enabled.
– CLK_BOD is used by the BOD. It will be requested when the BOD is enabled in Sampled Mode.
The clock source for the for the Main Clock domain is configured by writing to the Clock Select bits (CLKSEL) in the
Main Clock Control A register (CLKCTRL.MCLKCTRLA). The asynchronous clock sources are configured by
registers in the respective peripheral.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 76
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.2.2
Signal Description
Signal
Type
Description
CLKOUT
Digital output
CLK_PER output
Related Links
5. I/O Multiplexing and Considerations
11.3
Functional Description
11.3.1
Sleep Mode Operation
When a clock source is not used/requested it will turn off. It is possible to request a clock source directly by writing a
'1' to the Run Standby bit (RUNSTDBY) in the respective oscillator's Control A register (CLKCTRL.[osc]CTRLA). This
will cause the oscillator to run constantly, except for Power-Down Sleep mode. Additionally, when this bit is written to
'1' the oscillator start-up time is eliminated when the clock source is requested by a peripheral.
The main clock will always run in Active and Idle Sleep mode. In Standby Sleep mode, the main clock will only run if
any peripheral is requesting it, or the Run in Standby bit (RUNSTDBY) in the respective oscillator's Control A register
(CLKCTRL.[osc]CTRLA) is written to '1'.
In Power-Down Sleep mode, the main clock will stop after all NVM operations are completed.
11.3.2
Main Clock Selection and Prescaler
All internal oscillators can be used as the main clock source for CLK_MAIN. The main clock source is selectable from
software, and can be safely changed during normal operation.
Built-in hardware protection prevents unsafe clock switching:
Upon selection of an external clock source, a switch to the chosen clock source will only occur if edges are detected,
indicating it is stable. Until a sufficient number of clock edges are detected, the switch will not occur and it will not be
possible to change to another clock source again without executing a Reset.
An ongoing clock source switch is indicated by the System Oscillator Changing flag (SOSC) in the Main Clock Status
register (CLKCTRL.MCLKSTATUS). The stability of the external clock sources is indicated by the respective status
flags (EXTS in CLKCTRL.MCLKSTATUS).
CAUTION
If an external clock source fails while used as CLK_MAIN source, only the WDT can provide a mechanism
to switch back via System Reset.
CLK_MAIN is fed into a prescaler before it is used by the peripherals (CLK_PER) in the device. The prescaler divide
CLK_MAIN by a factor from 1 to 64.
Figure 11-3. Main Clock and Prescaler
OSC20M
32kHz Osc.
External clock
CLK_MAIN
Main Clock Prescaler
(Div 1, 2, 4, 8, 16, 32,
64, 6, 10, 24, 48)
CLK_PER
The Main Clock and Prescaler configuration registers (CLKCTRL.MCLKCTRLA, CLKCTRL.MCLKCTRLB) are
protected by the Configuration Change Protection Mechanism, employing a timed write procedure for changing these
registers.
Related Links
9.5.7 Configuration Change Protection (CCP)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 77
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.3.3
Main Clock After Reset
After any Reset, CLK_MAIN is provided by the 16 MHz Oscillator (OSC20M) and with a prescaler division factor of 6.
Since the actual frequency of the OSC20M is determined by the Frequency Select bits (FREQSEL) of the Oscillator
Configuration fuse (FUSE.OSCCFG), these frequencies are possible after Reset:
Table 11-1. Peripheral Clock Frequencies After Reset
CLK_MAIN
as Per FREQSEL in FUSE.OSCCFG
Resulting CLK_PER
16 MHz
2.66 MHz
See the OSC20M description for further details.
Related Links
11.3.4.1.1 16 MHz Oscillator (OSC20M)
11.3.4
Clock Sources
All internal clock sources are enabled automatically when they are requested by a peripheral.
The respective Oscillator Status bits in the Main Clock Status register (CLKCTRL.MCLKSTATUS) indicate whether
the clock source is running and stable.
Related Links
7.10 Configuration and User Fuses (FUSE)
9.5.7 Configuration Change Protection (CCP)
11.3.4.1 Internal Oscillators
The internal oscillators do not require any external components to run. See the related links for accuracy and
electrical characteristics.
Related Links
32. Electrical Characteristics
11.3.4.1.1 16 MHz Oscillator (OSC20M)
This oscillator can operate at multiple frequencies, selected by the value of the Frequency Select bits (FREQSEL) in
the Oscillator Configuration Fuse (FUSE.OSCCFG). The center frequencies are:
• 16 MHz
After a system Reset, FUSE.OSCCFG determines the initial frequency of CLK_MAIN.
During Reset the calibration values for the OSC20M are loaded from fuses. There are two different calibration bit
fields. The Calibration bit field (CAL20M) in the Calibration A register (CLKCTRL.OSC20MCALIBA) enables
calibration around the current center frequency. The Oscillator Temperature Coefficient Calibration bit field
(TEMPCAL20M) in the Calibration B register (CLKCTRL.OSC20MCALIBB) enables adjustment of the slope of the
temperature drift compensation.
For applications requiring more fine-tuned frequency setting than the oscillator calibration provides, factory stored
frequency error after calibrations are available.
The oscillator calibration can be locked by the Oscillator Lock (OSCLOCK) Fuse (FUSE.OSCCFG). When this fuse is
'1', it is not possible to change the calibration. The calibration is locked if this oscillator is used as main clock source
and the Lock Enable bit (LOCKEN) in the Control B register (CLKCTRL.OSC20MCALIBB) is '1'.
The calibration bits are protected by the Configuration Change Protection Mechanism, requiring a timed write
procedure for changing the main clock and prescaler settings.
The start-up time of this oscillator is analog start-up time plus four oscillator cycles. Refer to the Electrical
Characteristics section for the start-up time.
When changing the oscillator calibration value, the frequency may overshoot. If the oscillator is used as the main
clock (CLK_MAIN) it is recommended to change the main clock prescaler so that the main clock frequency does not
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 78
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
exceed ¼ of the maximum operation main clock frequency as described in the General Operating Ratings section.
The system clock prescaler can be changed back after the oscillator calibration value has been updated.
Related Links
7.10 Configuration and User Fuses (FUSE)
11.3.5 Configuration Change Protection
32.3 General Operating Ratings
11.3.3 Main Clock After Reset
32.9 Oscillators and Clocks
OSC20M Stored Frequency Error Compensation
This oscillator can operate at multiple frequencies, selected by the value of the Frequency Select bits (FREQSEL) in
the Oscillator Configuration fuse (FUSE.OSCCFG) at Reset. As previously mentioned appropriate calibration values
are loaded to adjust to center frequency (OSC20M), and temperature drift compensation (TEMPCAL20M), meeting
the specifications defined in the internal oscillator characteristics. For applications requiring wider operating range,
the relative factory stored frequency error after calibrations can be used. The four errors are measured at different
settings and are available in the signature row as signed byte values.
•
•
SIGROW.OSC16ERR3V is the frequency error from 16 MHz measured at 3V
SIGROW.OSC16ERR5V is the frequency error from 16 MHz measured at 5V
The error is stored as a compressed Q1.10 fixed point 8-bit value, in order not to lose resolution, where the MSB is
the sign bit and the seven LSBs the lower bits of the Q.10.
BAUDact��� = BAUD����� +
BAUD����� * �����������
1024
The minimum legal BAUD register value is 0x40, the target BAUD register value should therefore not be lower than
0x4A to ensure that the compensated BAUD value stays within the legal range, even for parts with negative
compensation values. The example code below, demonstrates how to apply this value for more accurate USART
baud rate:
#include
/* Baud rate compensated with factory stored frequency error */
/* Asynchronous communication without Auto-baud (Sync Field) */
/* 16MHz Clock, 3V and 600 BAUD
*/
int8_t sigrow_val
int32_t baud_reg_val
= SIGROW.OSC16ERR3V;
= 600;
assert (baud_reg_val >= 0x4A);
value with max neg comp
baud_reg_val *= (1024 + sigrow_val);
baud_reg_val /= 1024;
USART0.BAUD = (int16_t) baud_reg_val;
// read signed error
// ideal BAUD register value
// Verify legal min BAUD register
// sum resolution + error
// divide by resolution
// set adjusted baud rate
Related Links
32.9 Oscillators and Clocks
11.3.4.1.2 32 KHz Oscillator (OSCULP32K)
The 32 KHz oscillator is optimized for Ultra Low-Power (ULP) operation.
This oscillator provides the 1 KHz signal for the Real-Time Counter (RTC), the Watchdog Timer (WDT), and the
Brown-out Detector (BOD).
The start-up time of this oscillator is the oscillator start-up time plus four oscillator cycles. Refer to the Electrical
Characteristics chapter for the start-up time.
Related Links
18. Brown-Out Detector (BOD)
20. Watchdog Timer (WDT)
23. Real-Time Counter (RTC)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 79
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.3.4.2 External Clock Sources
This external clock source is available:
• External Clock from pin. (EXTCLK).
11.3.4.2.1 External Clock (EXTCLK)
The EXTCLK is taken directly from the pin. This GPIO pin is automatically configured for EXTCLK if any peripheral is
requesting this clock.
This clock source has a start-up time of two cycles when first requested.
11.3.5
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a
certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four
CPU instructions.
It is possible to try writing to these registers any time, but the values are not altered.
The following registers are under CCP:
Table 11-2. CLKCTRL - Registers Under Configuration Change Protection
Register
Key
CLKCTRL.MCLKCTRLB
IOREG
CLKCTRL.MCLKLOCK
IOREG
CLKCTRL.MCLKCTRLA
IOREG
CLKCTRL.OSC20MCTRLA
IOREG
CLKCTRL.OSC20MCALIBA
IOREG
CLKCTRL.OSC20MCALIBB
IOREG
CLKCTRL.OSC32KCTRLA
IOREG
Related Links
9.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 80
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.4
Register Summary - CLKCTRL
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
...
0x0F
0x10
0x11
0x12
0x13
...
0x17
0x18
MCLKCTRLA
MCLKCTRLB
MCLKLOCK
MCLKSTATUS
7:0
7:0
7:0
7:0
11.5
CLKOUT
PDIV[3:0]
EXTS
OSC32KS
OSC20MS
CLKSEL[1:0]
PEN
LOCKEN
SOSC
Reserved
OSC20MCTRLA
OSC20MCALIBA
OSC20MCALIBB
7:0
7:0
7:0
RUNSTDBY
CAL20M[5:0]
TEMPCAL20M[3:0]
LOCK
Reserved
OSC32KCTRLA
7:0
RUNSTDBY
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 81
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.1
Main Clock Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CLKOUT
R/W
0
MCLKCTRLA
0x00
0x00
Configuration Change Protection
6
5
4
3
2
R
0
R
0
R
0
R
0
R
0
1
0
CLKSEL[1:0]
R/W
R/W
0
0
Bit 7 – CLKOUT System Clock Out
When this bit is written to '1', the system clock is output to CLKOUT pin.
When the device is in a Sleep mode, there is no clock output unless a peripheral is using the system clock.
Bits 1:0 – CLKSEL[1:0] Clock Select
This bit field selects the source for the Main Clock (CLK_MAIN).
Value
Name
Description
0x0
OSC20M
16 MHz internal oscillator
0x1
OSCULP32K
32 KHz internal ultra low-power oscillator
0x2
Reserved
Reserved
0x3
EXTCLK
External clock
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 82
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.2
Main Clock Control B
Name:
Offset:
Reset:
Property:
Bit
7
MCLKCTRLB
0x01
0x11
Configuration Change Protection
6
5
4
3
2
1
R/W
0
R/W
0
PDIV[3:0]
Access
Reset
R
0
R
0
R
0
R/W
1
R/W
0
0
PEN
R/W
1
Bits 4:1 – PDIV[3:0] Prescaler Division
If the Prescaler Enable (PEN) bit is written to '1', these bits define the division ratio of the main clock prescaler.
These bits can be written during run-time to vary the clock frequency of the system to suit the application
requirements.
User software must ensure a correct configuration of input frequency (CLK_MAIN) and prescaler settings, such that
the resulting frequency of CLK_PER never exceeds the allowed maximum (see Electrical Characteristics).
Value
Description
Value
Division
0x0
2
0x1
4
0x2
8
0x3
16
0x4
32
0x5
64
0x8
6
0x9
10
0xA
12
0xB
24
0xC
48
other
Reserved
Bit 0 – PEN Prescaler Enable
This bit must be written '1' to enable the prescaler. When enabled, the division ratio is selected by the PDIV bit field.
When this bit is written to '0', the main clock will pass through undivided (CLK_PER=CLK_MAIN), regardless of the
value of PDIV.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 83
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.3
Main Clock Lock
Name:
Offset:
Reset:
Property:
MCLKLOCK
0x02
0x00
Configuration Change Protection
Bit
7
6
5
4
3
2
1
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
LOCKEN
R/W
x
Bit 0 – LOCKEN Lock Enable
Writing this bit to '1' will lock the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers, and, if applicable,
the calibration settings for the current main clock source from further software updates. Once locked, the
CLKCTRL.MCLKLOCK registers cannot be accessed until the next hardware Reset.
This provides protection for the CLKCTRL.MCLKCTRLA and CLKCTRL.MCLKCTRLB registers and calibration
settings for the main clock source from unintentional modification by software.
Related Links
7.10 Configuration and User Fuses (FUSE)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 84
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.4
Main Clock Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
EXTS
R
0
MCLKSTATUS
0x03
0x00
-
6
5
OSC32KS
R
0
4
OSC20MS
R
0
3
2
1
R
0
R
0
R
0
0
SOSC
R
0
Bit 7 – EXTS External Clock Status
Value
Description
0
EXTCLK has not started
1
EXTCLK has started
Bit 5 – OSC32KS OSCULP32K Status
The Status bit will only be available if the source is requested as the main clock or by another module. If the oscillator
RUNSTDBY bit is set but the oscillator is unused/not requested, this bit will be 0.
Value
Description
0
OSCULP32K is not stable
1
OSCULP32K is stable
Bit 4 – OSC20MS OSC20M Status
The Status bit will only be available if the source is requested as the main clock or by another module. If the oscillator
RUNSTDBY bit is set but the oscillator is unused/not requested, this bit will be 0.
Value
Description
0
OSC20M is not stable
1
OSC20M is stable
Bit 0 – SOSC Main Clock Oscillator Changing
Value
Description
0
The clock source for CLK_MAIN is not undergoing a switch
1
The clock source for CLK_MAIN is undergoing a switch, and will change as soon as the new source is
stable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 85
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.5
16 MHz Oscillator Control A
Name:
Offset:
Reset:
Property:
OSC20MCTRLA
0x10
0x00
Configuration Change Protection
Bit
7
6
5
4
3
2
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
1
RUNSTDBY
R/W
0
0
R
0
Bit 1 – RUNSTDBY Run Standby
This bit forces the oscillator ON in all modes, even when unused by the system. In Standby Sleep mode this can be
used to ensure immediate wake-up and not waiting for oscillator start-up time.
When not requested by peripherals, no oscillator output is provided.
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up time will be
removed when this bit is set.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 86
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.6
16 MHz Oscillator Calibration A
Name:
Offset:
Reset:
Property:
Bit
7
OSC20MCALIBA
0x11
Based on FREQSEL in FUSE.OSCCFG
Configuration Change Protection
6
Access
Reset
5
4
R/W
x
R/W
x
3
2
CAL20M[5:0]
R/W
R/W
x
x
1
0
R/W
x
R/W
x
Bits 5:0 – CAL20M[5:0] Calibration
These bits change the frequency around the current center frequency of the OSC20M for fine-tuning.
At Reset, the factory calibrated values are loaded based on the FREQSEL bits in FUSE.OSCCFG.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 87
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.7
16 MHz Oscillator Calibration B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
LOCK
R
x
OSC20MCALIBB
0x12
Based on FUSE.OSCCFG
Configuration Change Protection
6
5
4
3
R/W
x
2
1
TEMPCAL20M[3:0]
R/W
R/W
x
x
0
R/W
x
Bit 7 – LOCK Oscillator Calibration Locked by Fuse
When this bit is set, the calibration settings in CLKCTRL.OSC20MCALIBA and CLKCTRL.OSC20MCALIBB cannot
be changed.
At Reset, the value is loaded from the OSCLOCK bit in the Oscillator Configuration Fuse (FUSE.OSCCFG).
Bits 3:0 – TEMPCAL20M[3:0] Oscillator Temperature Coefficient Calibration
These bits tune the slope of the temperature compensation.
At Reset, the factory calibrated values are loaded based on the FREQSEL bits in FUSE.OSCCFG.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 88
ATtiny202/204/402/404/406 Automotiv...
Clock Controller (CLKCTRL)
11.5.8
32 KHz Oscillator Control A
Name:
Offset:
Reset:
Property:
Bit
7
OSC32KCTRLA
0x18
0x00
Configuration Change Protection
6
5
4
3
Access
Reset
2
1
RUNSTDBY
R/W
0
0
Bit 1 – RUNSTDBY Run Standby
This bit forces the oscillator ON in all modes, even when unused by the system. In Standby Sleep mode this can be
used to ensure immediate wake-up and not waiting for the oscillator start-up time.
When not requested by peripherals, no oscillator output is provided.
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up time will be
removed when this bit is set.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 89
ATtiny202/204/402/404/406 Automotiv...
Sleep Controller (SLPCTRL)
12.
Sleep Controller (SLPCTRL)
12.1
Features
•
•
12.2
Three sleep modes:
– Idle
– Standby
– Power-Down
Configurable Standby Sleep mode where peripherals can be configured as ON or OFF.
Overview
Sleep modes are used to shut down peripherals and clock domains in the device in order to save power. The Sleep
Controller (SLPCTRL) controls and handles the transitions between active and sleep mode.
There are in total four modes available, one active mode in which software is executed, and three sleep modes. The
available sleep modes are; Idle, Standby, and Power-Down.
When the device enters a sleep mode, program execution is stopped, and depending on the entered sleep mode,
different peripherals and clock domains are turned off.
To enter a sleep mode, the SLPCTRL must be enabled and the desired sleep mode must be stated. The software
decides when to enter that sleep mode by using a dedicated SLEEP instruction.
Interrupts are used to wake-up the device from sleep. The available interrupt wake-up sources depend on the
configured sleep mode. When an interrupt occurs, the device will wake-up and execute the interrupt service routine
before continuing normal program execution from the first instruction after the SLEEP instruction. Any Reset will take
the device out of a sleep mode.
The content of the register file, SRAM and registers are kept during sleep. If a Reset occurs during sleep, the device
will reset, start-up, and execute from the Reset vector.
12.2.1
Block Diagram
Figure 12-1. Sleep Controller in System
SLEEP Instruction
SLPCTRL
Interrupt Request
CPU
Sleep State
Interrupt Request
Peripheral
12.2.2
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 90
ATtiny202/204/402/404/406 Automotiv...
Sleep Controller (SLPCTRL)
Table 12-1. SLPCTRL System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
No
-
Events
No
-
Debug
Yes
UPDI
12.2.2.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
11. Clock Controller (CLKCTRL)
12.2.2.2 I/O Lines and Connections
Not applicable.
12.2.2.3 Interrupts
Not applicable.
12.2.2.4 Events
Not applicable.
12.2.2.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. The SLPCTRL is only affected by a break in
debug operation: If the SLPCTRL is in a sleep mode when a break occurs, the device will wake-up and the SLPCTRL
will go to Active mode, even if there are no pending interrupt requests.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
12.3
Functional Description
12.3.1
Initialization
To put the device into a sleep mode, follow these steps:
• Configure and enable the interrupts that should wake-up the device from sleep. Also enable global interrupts.
WARNING
•
12.3.2
If there are no interrupts enabled when going to sleep, the device cannot wake-up again. Only a
Reset will allow the device to continue operation.
Select the sleep mode to be entered and enable the Sleep Controller by writing to the Sleep Mode bits
(SMODE) and the Enable bit (SEN) in the Control A register (SLPCTRL.CTRLA). A SLEEP instruction must be
run to make the device actually go to sleep.
Operation
12.3.2.1 Sleep Modes
In addition to Active mode, there are three different sleep modes, with decreasing power consumption and
functionality.
Idle
The CPU stops executing code, no peripherals are disabled.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 91
ATtiny202/204/402/404/406 Automotiv...
Sleep Controller (SLPCTRL)
Standby
PowerDown
All interrupt sources can wake-up the device.
The user can configure peripherals to be enabled or not, using the respective RUNSTBY bit. This
means that the power consumption is highly dependent on what functionality is enabled, and thus may
vary between the Idle and Power-Down levels.
SleepWalking is available for the ADC module.
The wake-up sources are pin interrupts, TWI address match, UART Start-of-Frame interrupt (if USART
is enabled to run in Standby), RTC interrupt (if RTC enabled to run in Standby), and TCB interrupt.
Only the WDT and the PIT (a component of the RTC) are active.
The only wake-up sources are the pin change interrupt and TWI address match.
Table 12-2. Sleep Mode Activity Overview
Group
Peripheral
Active in Sleep Mode
Clock
Active Clock
Domain
Oscillators
Wake-Up
Sources
Idle
Standby
Power-Down
CPU
CLK_CPU
Peripherals
CLK_PER
X
RTC
CLK_RTC
X
X*
ADC
CLK_PER
X
X*
PIT (RTC)
CLK_RTC
X
X
X
WDT
CLK_WDT
X
X
X
Main Clock Source
X
X*
RTC Clock Source
X
X*
WDT Oscillator
X
X
X
INTn and Pin Change
X
X
X
TWI Address Match
X
X
X
Periodic Interrupt Timer
X
X
X
UART Start-of-Frame
X
X*
ADC Window
X
X*
RTC Interrupt
X
X*
All other Interrupts
X
Note:
• X means active. X* indicates that the RUNSTBY bit of the corresponding peripheral must be set to enter the
active state.
12.3.2.2 Wake-Up Time
The normal wake-up time for the device is six main clock cycles (CLK_PER), plus the time it takes to start up the
main clock source:
• In Idle Sleep mode, the main clock source is kept running so it will not be any extra wake-up time.
• In Standby Sleep mode, the main clock might be running so it depends on the peripheral configuration.
• In Power-Down Sleep mode, only the ULP 32 KHz oscillator and RTC clock may be running if it is used by the
BOD or WDT. All other clock sources will be OFF.
Table 12-3. Sleep Modes and Start-Up Time
Sleep Mode
Start-Up Time
IDLE
6 CLK
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 92
ATtiny202/204/402/404/406 Automotiv...
Sleep Controller (SLPCTRL)
...........continued
Sleep Mode
Start-Up Time
Standby
6 CLK + OSC start-up
Power-Down
6 CLK + OSC start-up
The start-up time for the different clock sources is described in the Clock Controller (CLKCTRL) section.
In addition to the normal wake-up time it is possible to make the device wait until the BOD is ready before executing
code. This is done by writing 0x3 to the BOD Operation mode in Active and Idle bits (ACTIVE) in the BOD
Configuration fuse (FUSE.BODCFG). If the BOD is ready before the normal wake-up time, the net wake-up time will
be the same. If the BOD takes longer than the normal wake-up time, the wake-up time will be extended until the BOD
is ready. This ensures correct supply voltage whenever code is executed.
12.3.3
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 93
ATtiny202/204/402/404/406 Automotiv...
Sleep Controller (SLPCTRL)
12.4
Register Summary - SLPCTRL
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
12.5
SMODE[1:0]
SEN
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 94
ATtiny202/204/402/404/406 Automotiv...
Sleep Controller (SLPCTRL)
12.5.1
Control A
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x00
-
Bit
7
6
5
4
3
Access
Reset
R
0
R
0
R
0
R
0
R
0
2
1
SMODE[1:0]
R/W
R/W
0
0
0
SEN
R/W
0
Bits 2:1 – SMODE[1:0] Sleep Mode
Writing these bits selects the sleep mode entered when the Sleep Enable bit (SEN) is written to '1' and the SLEEP
instruction is executed.
Value
Name
Description
0x0
IDLE
Idle Sleep mode enabled
0x1
STANDBY
Standby Sleep mode enabled
0x2
PDOWN
Power-Down Sleep mode enabled
other
Reserved
Bit 0 – SEN Sleep Enable
This bit must be written to '1' before the SLEEP instruction is executed to make the MCU enter the selected sleep
mode.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 95
ATtiny202/204/402/404/406 Automotiv...
Reset Controller (RSTCTRL)
13.
Reset Controller (RSTCTRL)
13.1
Features
•
•
•
Reset the device and set it to an initial state.
Reset Flag register for identifying the Reset source in software.
Multiple Reset sources:
– Power supply Reset sources: Brown-out Detect (BOD), Power-on Reset (POR)
– User Reset sources: External Reset pin (RESET), Watchdog Reset (WDT), Software Reset (SW), and
UPDI Reset.
13.2
Overview
The Reset Controller (RSTCTRL) manages the Reset of the device. It issues a device Reset, sets the device to its
initial state, and allows the Reset source to be identified by software.
13.2.1
Block Diagram
Figure 13-1. Reset System Overview
RESET SOURCES
VDD
POR
Pull-up
Resistor
RESET
RESET CONTROLLER
BOD
FILTER
UPDI
External Reset
WDT
All other
Peripherals
UPDI
CPU (SW)
13.2.2
Signal Description
Signal
Description
Type
RESET
External Reset (active-low)
Digital input
13.3
Functional Description
13.3.1
Initialization
The Reset Controller (RSTCTRL) is always enabled, but some of the Reset sources must be enabled (either by fuses
or by software) before they can request a Reset.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 96
ATtiny202/204/402/404/406 Automotiv...
Reset Controller (RSTCTRL)
After any Reset, the Reset source that caused the Reset is found in the Reset Flag register (RSTCTRL.RSTFR).
After a Power-on Reset, only the POR flag will be set.
The flags are kept until they are cleared by writing a '1' to them.
After Reset from any source, all registers that are loaded from fuses are reloaded.
13.3.2
Operation
13.3.2.1 Reset Sources
There are two kinds of sources for Resets:
• Power supply Resets, which are caused by changes in the power supply voltage: Power-on Reset (POR) and
Brown-out Detector (BOD).
• User Resets, which are issued by the application, by the debug operation or by pin changes (Software Reset,
Watchdog Reset, UPDI Reset, and external Reset pin RESET).
13.3.2.1.1 Power-On Reset (POR)
A Power-on-Reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VDD rises until
it reaches the POR threshold voltage. The POR is always enabled and will also detect when the VDD falls below the
threshold voltage.
All volatile logic is reset on POR. All fuses are reloaded after the Reset is released.
13.3.2.1.2 Brown-Out Detector (BOD) Reset Source
The on-chip Brown-out Detection circuit will monitor the VDD level during operation by comparing it to a fixed trigger
level. The trigger level for the BOD can be selected by fuses. If BOD is unused in the application, it is forced to a
configured level in order to ensure safe operation during chip erase.
All logic is reset on BOD Reset, except the BOD configuration. All fuses are reloaded after the Reset is released.
Related Links
18. Brown-Out Detector (BOD)
13.3.2.1.3 Software Reset
The software Reset makes it possible to issue a system Reset from software. The Reset is generated by writing a '1'
to the Software Reset Enable bit (SWRE) in the Software Reset register (RSTCTRL.SWRR).
The Reset will take place immediately after the bit is written and the device will be kept in reset until the Reset
sequence is completed. All logic is reset on software Reset, except UPDI and BOD configuration. All fuses are
reloaded after the Reset is released.
13.3.2.1.4 External Reset
The external Reset is enabled by fuse (see fuse map).
When enabled, the external Reset requests a Reset as long as the RESET pin is low. The device will stay in Reset
until RESET is high again. All logic is reset on external reset, except UPDI and BOD configuration. All fuses are
reloaded after the Reset is released.
Related Links
7.10 Configuration and User Fuses (FUSE)
13.3.2.1.5 Watchdog Reset
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset
from software according to the programmed time-out period, a Watchdog Reset will be issued. See the WDT
documentation for further details.
All logic is reset on WDT Reset, except UPDI and BOD configuration. All fuses are reloaded after the Reset is
released.
Related Links
20. Watchdog Timer (WDT)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 97
ATtiny202/204/402/404/406 Automotiv...
Reset Controller (RSTCTRL)
13.3.2.1.6 Universal Program Debug Interface (UPDI) Reset
The UPDI contains a separate Reset source that is used to reset the device during external programming and
debugging. The Reset source is accessible only from external debuggers and programmers. All logic is reset on
UPDI Reset, except the UPDI itself and BOD configuration. All fuses are reloaded after the Reset is released. See
UPDI chapter on how to generate a UPDI Reset request.
Related Links
31. Unified Program and Debug Interface (UPDI)
13.3.2.2 Reset Time
The Reset time can be split in two.
The first part is when any of the Reset sources are active. This part depends on the input to the Reset sources. The
external Reset is active as long as the RESET pin is low, the Power-on Reset (POR) and Brown-out Detector (BOD)
is active as long as the supply voltage is below Reset source threshold.
When all the Reset sources are released, an internal Reset initialization of the device is done. This time will be
increased with the start-up time given by the start-up time fuse setting (SUT in FUSE.SYSCFG1). The internal Reset
initialization time will also increase if the CRC source is set up to run (CRCSRC in FUSE.SYSCFG0).
13.3.3
Sleep Mode Operation
The Reset Controller continues to operate in all active and sleep modes.
13.3.4
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a
certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four
CPU instructions.
It is possible to try writing to these registers any time, but the values are not altered.
The following registers are under CCP:
Table 13-1. RSTCTRL - Registers Under Configuration Change Protection
Register
Key
RSTCTRL.SWRR
IOREG
Related Links
9.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 98
ATtiny202/204/402/404/406 Automotiv...
Reset Controller (RSTCTRL)
13.4
Register Summary - RSTCTRL
Offset
Name
Bit Pos.
0x00
0x01
RSTFR
SWRR
7:0
7:0
13.5
UPDIRF
SWRF
WDRF
EXTRF
BORF
PORF
SWRE
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 99
ATtiny202/204/402/404/406 Automotiv...
Reset Controller (RSTCTRL)
13.5.1
Reset Flag Register
Name:
Offset:
Reset:
Property:
RSTFR
0x00
0xXX
-
All flags are cleared by writing a '1' to them. They are also cleared by a Power-on Reset, with the exception of the
Power-On Reset Flag (PORF).
Bit
7
6
Access
Reset
R
0
R
0
5
UPDIRF
R/W
x
4
SWRF
R/W
x
3
WDRF
R/W
x
2
EXTRF
R/W
x
1
BORF
R/W
x
0
PORF
R/W
x
Bit 5 – UPDIRF UPDI Reset Flag
This bit is set if a UPDI Reset occurs.
Bit 4 – SWRF Software Reset Flag
This bit is set if a Software Reset occurs.
Bit 3 – WDRF Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs.
Bit 2 – EXTRF External Reset Flag
This bit is set if an External Reset occurs.
Bit 1 – BORF Brown-Out Reset Flag
This bit is set if a Brown-out Reset occurs.
Bit 0 – PORF Power-On Reset Flag
This bit is set if a Power-on Reset occurs.
This flag is only cleared by writing a '1' to it.
After a POR, only the POR flag is set and all other flags are cleared. No other flags can be set before a full system
boot is run after the POR.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 100
ATtiny202/204/402/404/406 Automotiv...
Reset Controller (RSTCTRL)
13.5.2
Software Reset Register
Name:
Offset:
Reset:
Property:
SWRR
0x01
0x00
Configuration Change Protection
Bit
7
6
5
4
3
2
1
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
SWRE
R/W
0
Bit 0 – SWRE Software Reset Enable
When this bit is written to '1', a software Reset will occur.
This bit will always read as '0'.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 101
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.
CPU Interrupt Controller (CPUINT)
14.1
Features
•
•
•
•
•
•
•
•
•
14.2
Short and Predictable Interrupt Response Time
Separate Interrupt Configuration and Vector Address for Each Interrupt
Interrupt Prioritizing by Level and Vector Address
Two Interrupt Priority Levels: 0 (normal) and 1 (high)
Higher Priority for One Interrupt
Optional Round Robin Priority Scheme for Priority Level 0 Interrupts
Non-Maskable Interrupts (NMI) for Critical Functions
Interrupt Vectors Optionally Placed in the Application Section or the Boot Loader Section
Selectable Compact Vector Table
Overview
An interrupt request signals a change of state inside a peripheral, and can be used to alter program execution.
Peripherals can have one or more interrupts, and all are individually enabled and configured.
When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition occurs.
The CPU Interrupt Controller (CPUINT) handles and prioritizes interrupt requests. When an interrupt is enabled and
the interrupt condition occurs, the CPUINT will receive the interrupt request. Based on the interrupt's priority level and
the priority level of any ongoing interrupts, the interrupt request is either acknowledged or kept pending until it has
priority. When an interrupt request is acknowledged by the CPUINT, the Program Counter is set to point to the
interrupt vector. The interrupt vector is normally a jump to the interrupt handler (i.e., the software routine that handles
the interrupt). After returning from the interrupt handler, program execution continues from where it was before the
interrupt occurred. One instruction is always executed before any pending interrupt is served.
The CPUINT Status register (CPUINT.STATUS) contains state information that ensures that the CPUINT returns to
the correct interrupt level when the RETI (interrupt return) instruction is executed at the end of an interrupt handler.
Returning from an interrupt will return the CPUINT to the state it had before entering the interrupt. CPUINT.STATUS
is not saved automatically upon an interrupt request.
By default, all peripherals are priority level 0. It is possible to set one single interrupt vector to the higher priority level
1. Interrupts are prioritized according to their priority level and their interrupt vector address. Priority level 1 interrupts
will interrupt level 0 interrupt handlers. Among priority level 0 interrupts, the priority is determined from the interrupt
vector address, where the lowest interrupt vector address has the highest interrupt priority.
Optionally, a round robin scheduling scheme can be enabled for priority level 0 interrupts. This ensures that all
interrupts are serviced within a certain amount of time.
Interrupt generation must be globally enabled by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status
register (CPU.SREG). This bit is not cleared when an interrupt is acknowledged.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 102
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.2.1
Block Diagram
Figure 14-1. CPUINT Block Diagram
Interrupt Controller
Priority
Decoder
Peripheral 1
INT REQ
CPU "RETI"
CPU INT ACK
CPU
INT LEVEL
Peripheral
n
INT REQ
CPU INT REQ
INT REQ
INT ACK
14.2.2
STATUS
LVL0PRI
LVL1VEC
Global
Interrupt
Enable
Wake-up
CPU.SREG
Sleep
Controller
Signal Description
Not applicable.
14.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 14-1. CPUINT System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
No
-
Events
No
-
Debug
Yes
UPDI
Related Links
14.2.3.5 Debug Operation
14.2.3.1 Clocks
14.2.3.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
11. Clock Controller (CLKCTRL)
14.2.3.2 I/O Lines and Connections
Not applicable.
14.2.3.3 Interrupts
Not applicable.
14.2.3.4 Events
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 103
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
Related Links
31. Unified Program and Debug Interface (UPDI)
14.3
Functional Description
14.3.1
Initialization
An interrupt must be initialized in the following order:
1.
2.
3.
14.3.2
Configure the CPUINT if the default configuration is not adequate (optional):
– Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control A register
(CPUINT.CTRLA).
– Vector prioritizing by round robin is enabled by writing a '1' to the Round Robin Priority Enable bit
(LVL0RR) in CPUINT.CTRLA.
– Select the priority level 1 vector by writing its address to the Interrupt Vector (LVL1VEC) in the Level 1
Priority register (CPUINT.LVL1VEC).
Configure the interrupt conditions within the peripheral, and enable the peripheral's interrupt.
Enable interrupts globally by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status register
(CPU.SREG).
Operation
14.3.2.1 Enabling, Disabling, and Resetting
Global enabling of interrupts is done by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status register
(CPU.SREG). To disable interrupts globally, write a '0' to the I bit in CPU.SREG.
The desired interrupt lines must also be enabled in the respective peripheral, by writing to the peripheral's Interrupt
Control register ([peripheral].INTCTRL).
Interrupt flags are not automatically cleared after the interrupt is executed. The respective INTFLAGS register
descriptions provide information on how to clear specific flags.
14.3.2.2 Interrupt Vector Locations
The table below shows Reset addresses and Interrupt vector placement, dependent on the value of Interrupt Vector
Select bit (IVSEL) in the Control A register (CPUINT.CTRLA).
If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can
be placed at these locations.
Table 14-2. Reset and Interrupt Vector Placement
IVSEL
Reset Address
Interrupt Vectors Start Address
0
0x0000
Application start address + Interrupt
vector offset address
1
0x0000
Interrupt vector offset address
14.3.2.3 Interrupt Response Time
The minimum interrupt response time for all enabled interrupts is three CPU clock cycles: one cycle to finish the
ongoing instruction, two cycles to store the Program Counter to the stack, and three cycles(1) to jump to the interrupt
handler (JMP).
After the Program Counter is pushed on the stack, the program vector for the interrupt is executed. See the figure
below, first diagram.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 104
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
The jump to the interrupt handler takes three clock cycles(1). If an interrupt occurs during execution of a multicycle
instruction, this instruction is completed before the interrupt is served. See the figure below, second diagram.
If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five
clock cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the Program
Counter. During these clock cycles, the Program Counter is popped from the stack and the Stack Pointer is
incremented. See the figure above, third diagram.
Figure 14-2. Interrupt Execution of a Single Cycle Instruction, Multicycle Instruction, and From Sleep(1)
Single Cycle Instruction
Multicycle Instruction
Sleep
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 105
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
Note:
1. Devices with 8kB of Flash or less use RJMP instead of JMP, which takes only two clock cycles.
14.3.2.4 Interrupt Level
The interrupt level is default on level 0 (normal) for all interrupt sources. It is possible to select one interrupt source to
level 1 (high) by writing interrupt address to CPUINT.LVL1VEC register. This source will have higher priority than
normal level interrupts.
An interrupt request from a level 1 source will interrupt any ongoing interrupt handler from a level 0 interrupt. When
returning from the level 1 interrupt handler, the execution of the level 0 interrupt handler will continue.
14.3.2.5 Interrupt Priority
14.3.2.5.1 Non-Maskable Interrupts (NMI)
An NMI will be executed regardless of the setting of the I bit in CPU.SREG, and it will never change the I bit. No other
interrupt can interrupt an NMI handler. If more than one NMI is requested at the same time, priority is static according
to the interrupt vector address, where the lowest address has the highest priority.
Which interrupts are non-maskable is device-dependent and not subject to configuration. Non-maskable interrupts
must be enabled before they can be used. Refer to the Interrupt Vector Mapping of the device for available NMI lines.
Related Links
8.2 Interrupt Vector Mapping
14.3.2.5.2 Static Priority
Interrupt Vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector address decides the
priority within normal interrupt level, where the lowest interrupt vector address has the highest priority. Refer to the
Interrupt Vector Mapping of the device for available interrupt lines and their base address offset.
Figure 14-3. Static Priority
Lowest Address
IVEC 0
Highest Priority
:
:
:
IVEC x
IVEC x+1
:
:
:
Highest Address
IVEC n
Lowest Priority
Related Links
8.2 Interrupt Vector Mapping
14.3.2.5.3 Round Robin Scheduling
To avoid "starvation" for priority level 0 (LVL0) interrupt requests with static priority (i.e. some interrupts might never
be served), the CPUINT offers round robin scheduling for LVL0 interrupts.
Round robin scheduling for LVL0 interrupt requests is enabled by writing a '1' to the Round Robin Priority Enable bit
(LVL0RR) in the Control A register (CPUINT.CTRLA).
When round robin scheduling is enabled, the interrupt vector address for the last acknowledged LVL0 interrupt will
have the lowest priority the next time one or more LVL0 interrupts are requested, as illustrated in the figure below.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 106
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
Figure 14-4. Round Robin Scheduling
IVEC x last acknowledge
interrupt
IVEC x+1 last acknowledge
interrupt
IVEC 0
IVEC 0
:
:
:
:
:
:
IVEC x
Lowest Priority
IVEC x
IVEC x+1
Highest Priority
IVEC x+1
Lowest Priority
IVEC x+2
Highest Priority
:
:
:
IVEC n
:
:
:
IVEC n
14.3.2.5.4 Compact Vector Table
The Compact Vector Table (CVT) is a feature to allow writing of compact code.
When CVT is enabled by writing a '1' to the CVT bit in the Control A register (CPUINT.CTRLA), the vector table
contains these three interrupt vectors:
1. The non-maskable interrupts (NMI) at vector address 1.
2. The priority level 1 (LVL1) interrupt at vector address 2.
3. All priority level 0 (LVL0) interrupts share vector address 3.
This feature is most suitable for applications using a small number of interrupt generators.
14.3.3
Events
Not applicable.
14.3.4
Sleep Mode Operation
Not applicable.
14.3.5
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a
certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four
CPU instructions.
It is possible to try writing to these registers any time, but the values are not altered.
The following registers are under CCP:
Table 14-3. INTCTRL - Registers under Configuration Change Protection
Register
Key
IVSEL in CPUINT.CTRLA
IOREG
CVT in CPUINT.CTRLA
IOREG
Related Links
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 107
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
9.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 108
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.4
Register Summary - CPUINT
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
CTRLA
STATUS
LVL0PRI
LVL1VEC
7:0
7:0
7:0
7:0
14.5
IVSEL
CVT
NMIEX
LVL1EX
LVL0RR
LVL0EX
LVL0PRI[7:0]
LVL1VEC[7:0]
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 109
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
Configuration Change Protection
6
IVSEL
R/W
0
5
CVT
R/W
0
4
3
2
1
0
LVL0RR
R/W
0
Bit 6 – IVSEL Interrupt Vector Select
If the boot section is defined, it will be placed before the application section. The actual start address of the
application section is determined by the BOOTEND fuse.
This bit is protected by the Configuration Change Protection mechanism.
Value
Description
0
Interrupt vectors are placed at the start of the application section of the Flash
1
Interrupt vectors are placed at the start of the boot section of the Flash
Bit 5 – CVT Compact Vector Table
This bit is protected by the Configuration Change Protection mechanism.
Value
Description
0
Compact Vector Table function is disabled
1
Compact Vector Table function is enabled
Bit 0 – LVL0RR Round Robin Priority Enable
This bit is not protected by the Configuration Change Protection mechanism.
Value
Description
0
Priority is fixed for priority level 0 interrupt requests: The lowest interrupt vector address has highest
priority.
1
Round Robin priority scheme is enabled for priority level 0 interrupt requests
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 110
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.5.2
Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
NMIEX
R
0
STATUS
0x01
0x00
-
6
5
4
3
2
1
LVL1EX
R
0
0
LVL0EX
R
0
Bit 7 – NMIEX Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag is cleared when returning (RETI) from the interrupt
handler.
Bit 1 – LVL1EX Level 1 Interrupt Executing
This flag is set when a priority level 1 interrupt is executing, or when the interrupt handler has been interrupted by an
NMI. The flag is cleared when returning (RETI) from the interrupt handler.
Bit 0 – LVL0EX Level 0 Interrupt Executing
This flag is set when a priority level 0 interrupt is executing, or when the interrupt handler has been interrupted by a
priority level 1 interrupt or an NMI. The flag is cleared when returning (RETI) from the interrupt handler.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 111
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.5.3
Interrupt Priority Level 0
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
LVL0PRI
0x02
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
LVL0PRI[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LVL0PRI[7:0] Interrupt Priority Level 0
When Round Robin is enabled (LVL0RR bit in CPUINT.CTRLA is '1'), this bit field stores the vector of the last
acknowledged priority level 0 (LVL0) interrupt. The stored vector will have the lowest priority next time one or more
LVL0 interrupts are pending.
If Round Robin is disabled (LVL0RR in CPUINT.CTRLA is '0'), the vector address-based priority scheme (lowest
address has the highest priority) is governing the priorities of LVL0 interrupt requests.
If a system Reset is asserted, the lowest interrupt vector address will have the highest priority within the LVL0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 112
ATtiny202/204/402/404/406 Automotiv...
CPU Interrupt Controller (CPUINT)
14.5.4
Interrupt Vector with Priority Level 1
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
LVL1VEC
0x03
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
LVL1VEC[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LVL1VEC[7:0] Interrupt Vector with Priority Level 1
This bit field contains the address of the single vector with increased priority level 1 (LVL1).
If this bit field has the value 0x00, no vector has LVL1. Consequently, the LVL1 interrupt is disabled.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 113
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.
Event System (EVSYS)
15.1
Features
•
•
•
•
•
•
•
•
15.2
System for Direct Peripheral-to-Peripheral Signaling
Peripherals can Directly Produce, Use, and React to Peripheral Events
Short Response Time
Up to Three Parallel Event Channels Available; Two Asynchronous and One Synchronous
Channels can be Configured to Have One Triggering Peripheral Action and Multiple Peripheral Users
Peripherals can Directly Trigger and React to Events from Other Peripherals
Events can be Sent and/or Received by Most Peripherals, and by Software
Works in Active mode and Standby Sleep mode
Overview
The Event System (EVSYS) enables direct peripheral-to-peripheral signaling. It allows a change in one peripheral
(the event generator) to trigger actions in other peripherals (the event users) through event channels, without using
the CPU. It is designed to provide short and predictable response times between peripherals, allowing for
autonomous peripheral control and interaction, and also for the synchronized timing of actions in several peripheral
modules. It is thus a powerful tool for reducing the complexity, size, and the execution time of the software.
A change of the event generator's state is referred to as an event and usually corresponds to one of the peripheral's
interrupt conditions. Events can be directly forwarded to other peripherals using the dedicated event routing network.
The routing of each channel is configured in software, including event generation and use.
Only one trigger from an event generator peripheral can be routed on each channel, but multiple channels can use
the same generator source. Multiple peripherals can use events from the same channel.
A channel path can be either asynchronous or synchronous to the main clock. The mode must be selected based on
the requirements of the application.
The Event System can directly connect analog and digital converters, analog comparators, I/O port pins, the real-time
counter, timer/counters, and the configurable custom logic peripheral. Events can also be generated from software
and the peripheral clock.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 114
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.2.1
Block Diagram
Figure 15-1. Block Diagram
Sync user x
Sync event channel ”k”
Sync event channel 0
Sync source 0
Sync source 1
Sync user 0
Sync source n
SYNCCH
SYNCSTROBE
..
.
..
.
..
.
Async source m
ASYNCCH
SYNCUSER
Async user y
Async user 0
Async event channel ”l”
Async event channel 0
Async source 0
Async source 1
To sync user
..
.
..
.
ASYNCSTROBE
To async user
ASYNCUSER
Figure 15-2. Example of Event Source, Generator, User, and Action
Event Generator
Event User
Timer/Counter
ADC
Compare Match
Over-/Underflow
|
Event
Routing
Network
Error
Channel Sweep
Single
Conversion
Event Action Selection
Event Source
Event Action
Note:
1. For an overview of peripherals supporting events, refer the block diagram of the device.
2. For a list of event generators, refer to the Channel n Generator Selection registers (EVSYS.SYNCCH and
EVSYS.ASYNCCH).
3. For a list of event users, refer to the User Channel n Input Selection registers (EVSYS.SYNCUSER and
EVSYS.ASYNCUSER).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 115
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.2.2
Signal Description
Internal Event Signaling
The event signaling can happen either synchronously or asynchronously to the main clock (CLK_MAIN).
Depending on the underlying event, the event signal can be a pulse with a duration of one clock cycle, or a level
signal (similar to a status flag).
Event Output to Pin
Signal
Type
Description
EVOUT[2:0]
Digital Output
Event Output
Related Links
15.2.3.2 I/O Lines
15.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 15-1. EVSYS System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORTMUX
Interrupts
No
-
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
15.2.3.1 Clocks
15.3.5 Debug Operation
15.2.3.1 Clocks
The EVSYS uses the peripheral clock for I/O registers and software events. When set up correctly, the routing
network can also be used in sleep modes without any clock. Software events will not work in sleep modes where the
peripheral clock is halted.
Related Links
11. Clock Controller (CLKCTRL)
15.2.3.2 I/O Lines
The EVSYS can output three event channels asynchronously on pins. The output signals are called EVOUT[2:0].
1. Configure which event channel (one of SYNCCH[1:0] or ASYNCCH[3:0]) is output on which EVOUTn bit by
writing to EVSYS.ASYNCUSER10, EVSYS.ASYNCUSER9, or EVSYS.ASYNCUSER8, respectively.
2. Optional: configure the pin properties using the port peripheral.
3. Enable the pin output by writing '1' to the respective EVOUTn bit in the Control A register of the PORTMUX
peripheral (PORTMUX.CTRLA).
Related Links
16. Port Multiplexer (PORTMUX)
17. I/O Pin Configuration (PORT)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 116
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.3
Functional Description
15.3.1
Initialization
Before enabling events within the device, the event users multiplexer and event channels must be configured.
Related Links
15.3.2.1 Event User Multiplexer Setup
15.3.2.2 Event System Channel
15.3.2
Operation
15.3.2.1 Event User Multiplexer Setup
The event user multiplexer selects the channel for an event user. Each event user has one dedicated event user
multiplexer. Each multiplexer is connected to the supported event channel outputs and can be configured to select
one of these channels.
Event users which support asynchronous events also support synchronous events. There are also event users that
support only synchronous events.
The event user multiplexers are configured by writing to the corresponding registers:
• Event users supporting both synchronous and asynchronous events are configured by writing to the respective
asynchronous User Channel Input Selection n register (EVSYS.ASYNCUSERn).
• The users of synchronous-only events are configured by writing to the respective Synchronous User Channel
Input Selection n register (EVSYS.SYNCUSERn).
The default setup of all user multiplexers is OFF.
15.3.2.2 Event System Channel
An event channel can be connected to one of the event generators. Event channels support either asynchronous
generators or synchronous generators.
The source for each asynchronous event channel is configured by writing to the respective Asynchronous Channel n
Input Selection register (EVSYS.ASYNCCHn).
The source for each synchronous event channel is configured by writing to the respective Synchronous Channel n
Input Selection register (EVSYS.SYNCCHn).
15.3.2.3 Event Generators
Each event channel can receive the events from several event generators. For details on event generation, refer to
the documentation of the corresponding peripheral.
For each event channel, there are several possible event generators, only one of which can be selected at a time.
The event generator trigger is selected for each channel by writing to the respective channel registers
(EVSYS.ASYNCCHn, EVSYS.SYNCCHn). By default, the channels are not connected to any event generator.
15.3.2.4 Software Event
In a software event, the CPU will “strobe” an event channel by inverting the current value for one system clock cycle.
A software event is triggered on a channel by writing a '1' to the respective Strobe bit in the appropriate Channel
Strobe register:
• Software events on asynchronous channel l are initiated by writing a '1' to the ASYNCSTROBE[l] bit in the
Asynchronous Channel Strobe register (EVSYS.ASYNCSTROBE).
• Software events on synchronous channel k are initiated by writing a '1' to the SYNCSTROBE[k] bit in the
Synchronous Channel Strobe register (EVSYS.SYNCSTROBE).
Software events are no different to those produced by event generator peripherals with respect to event users: when
the bit is written to '1', an event will be generated on the respective channel, and received and processed by the
event user.
15.3.3
Interrupts
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 117
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.3.4
Sleep Mode Operation
When configured, the Event System will work in all sleep modes. One exception is software events that require a
system clock.
15.3.5
Debug Operation
This peripheral is unaffected by entering Debug mode.
Related Links
31. Unified Program and Debug Interface (UPDI)
15.3.6
Synchronization
Asynchronous events are synchronized and handled by the compatible event users. Event user peripherals not
compatible with asynchronous events can only be configured to listen to synchronous event channels.
15.3.7
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 118
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.4
Register Summary - EVSYS
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
...
0x09
0x0A
0x0B
...
0x11
0x12
...
0x1C
0x1D
...
0x21
0x22
0x23
ASYNCSTROBE
SYNCSTROBE
ASYNCCH0
ASYNCCH1
7:0
7:0
7:0
7:0
ASYNCSTROBE[7:0]
SYNCSTROBE[7:0]
ASYNCCH[7:0]
ASYNCCH[7:0]
7:0
SYNCCH[7:0]
ASYNCUSER0
7:0
ASYNCUSER[7:0]
ASYNCUSER10
7:0
ASYNCUSER[7:0]
7:0
7:0
SYNCUSER[7:0]
SYNCUSER[7:0]
15.5
Reserved
SYNCCH0
Reserved
Reserved
SYNCUSER0
SYNCUSER1
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 119
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.5.1
Asynchronous Channel Strobe
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
ASYNCSTROBE
0x00
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
ASYNCSTROBE[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ASYNCSTROBE[7:0] Asynchronous Channel Strobe
If the Strobe register location is written, each event channel will be inverted for one system clock cycle (i.e., a single
event is generated).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 120
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.5.2
Synchronous Channel Strobe
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
SYNCSTROBE
0x01
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
SYNCSTROBE[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – SYNCSTROBE[7:0] Synchronous Channel Strobe
If the Strobe register location is written, each event channel will be inverted for one system clock cycle (i.e., a single
event is generated).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 121
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.5.3
Asynchronous Channel n Generator Selection
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
ASYNCCH
0x02 + n*0x01 [n=0..1]
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
ASYNCCH[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ASYNCCH[7:0] Asynchronous Channel Generator Selection
Table 15-2. ASYNCCH0
Value
Description
0x00
OFF
0x01
CCL_LUT0
0x02
CCL_LUT1
0x03
AC0_OUT
0x04
Reserved
0x05
Reserved
0x06
Reserved
0x07
Reserved
0x08
RTC_OVF
0x09
RTC_CMP
0x0A
PORTA0
0x0B
PORTA1
0x0C
PORTA2
0x0D
PORTA3
0x0E
PORTA4
0x0F
PORTA5
0x10
PORTA6
0x11
PORTA7
0x12
UPDI
Other
Reserved
Table 15-3. ASYNCCH1
Value
Description
0x00
OFF
0x01
CCL_LUT0
0x02
CCL_LUT1
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 122
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
...........continued
Value
Description
0x03
AC0_OUT
0x04
Reserved
0x05
Reserved
0x06
Reserved
0x07
Reserved
0x08
RTC_OVF
0x09
RTC_CMP
0x0A
PORTB0
0x0B
PORTB1
0x0C
PORTB2
0x0D
PORTB3
0x0E
PORTB4
0x0F
PORTB5
0x10
PORTB6
0x11
PORTB7
Other
Reserved
Note: Not all pins of a port are actually available on devices with low pin counts. Check the Pinout Diagram and/or
the I/O Multiplexing table for details.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 123
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.5.4
Synchronous Channel n Generator Selection
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
SYNCCH
0x0A
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
SYNCCH[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – SYNCCH[7:0] Synchronous Channel Generator Selection
Table 15-4. SYNCCH0
Value
Description
0x00
OFF
0x01
TCB0
0x02
TCA0_OVF_LUNF
0x03
TCA0_HUNF
0x04
TCA0_CMP0
0x05
TCA0_CMP1
0x06
TCA0_CMP2
0x07
PORTC0
0x08
PORTC1
0x09
PORTC2
0x0A
PORTC3
0x0B
PORTC4
0x0C
PORTC5
0x0D
PORTA0
0x0E
PORTA1
0x0F
PORTA2
0x10
PORTA3
0x11
PORTA4
0x12
PORTA5
0x13
PORTA6
0x14
PORTA7
Other
Reserved
Note: Not all pins of a port are actually available on devices with low pin counts. Check the Pinout Diagram and/or
the I/O Multiplexing table for details.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 124
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.5.5
Asynchronous User Channel n Input Selection
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
ASYNCUSER
0x12 + n*0x01 [n=0..10]
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
ASYNCUSER[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ASYNCUSER[7:0] Asynchronous User Channel Selection
Table 15-5. User Multiplexer Numbers
USERn
User Multiplexer
Description
n=0
TCB0
Timer/Counter B 0
n=1
ADC0
ADC 0
n=2
CCL_LUT0EV0
CCL LUT0 Event 0
n=3
CCL_LUT1EV0
CCL LUT1 Event 0
n=4
CCL_LUT0EV1
CCL LUT0 Event 1
n=5
CCL_LUT1EV1
CCL LUT1 Event 1
n=6,7
Reserved
Reserved
n=8
EVOUT0
Event OUT 0
n=9
EVOUT1
Event OUT 1
n=10
EVOUT2
Event OUT 2
Value
0x0
0x1
0x3
0x4
Description
OFF
SYNCCH0
ASYNCCH0
ASYNCCH1
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 125
ATtiny202/204/402/404/406 Automotiv...
Event System (EVSYS)
15.5.6
Synchronous User Channel n Input Selection
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
SYNCUSER
0x22 + n*0x01 [n=0..1]
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
SYNCUSER[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – SYNCUSER[7:0] Synchronous User Channel Selection
Table 15-6. User Multiplexer Numbers
USERn
User Multiplexer
Description
n=0
TCA0
Timer/Counter A
n=1
USART0
USART
Value
0x0
0x1
Name
OFF
SYNCCH0
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 126
ATtiny202/204/402/404/406 Automotiv...
Port Multiplexer (PORTMUX)
16.
16.1
Port Multiplexer (PORTMUX)
Overview
The Port Multiplexer (PORTMUX) can either enable or disable functionality of pins, or change between default and
alternative pin positions. This depends on the actual pin and property and is described in detail in the PORTMUX
register map.
For available pins and functionalities, refer to the Multiplexed Signals table.
Related Links
5. I/O Multiplexing and Considerations
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 127
ATtiny202/204/402/404/406 Automotiv...
Port Multiplexer (PORTMUX)
16.2
Register Summary - PORTMUX
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
CTRLA
CTRLB
CTRLC
CTRLD
7:0
7:0
7:0
7:0
16.3
LUT1
LUT0
TCA05
TCA04
TCA03
EVOUT2
SPI0
TCA02
EVOUT1
TCA01
EVOUT0
USART0
TCA00
TCB0
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 128
ATtiny202/204/402/404/406 Automotiv...
Port Multiplexer (PORTMUX)
16.3.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
Access
Reset
5
LUT1
R/W
0
4
LUT0
R/W
0
3
2
EVOUT2
R/W
0
1
EVOUT1
R/W
0
0
EVOUT0
R/W
0
Bit 5 – LUT1 CCL LUT 1 output
Write this bit to '1' to select alternative pin location for CCL LUT 1.
Bit 4 – LUT0 CCL LUT 0 output
Write this bit to '1' to select alternative pin location for CCL LUT 0.
Bit 2 – EVOUT2 Event Output 2
Write this bit to '1' to enable event output 2.
Bit 1 – EVOUT1 Event Output 1
Write this bit to '1' to enable event output 1.
Bit 0 – EVOUT0 Event Output 0
Write this bit to '1' to enable event output 0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 129
ATtiny202/204/402/404/406 Automotiv...
Port Multiplexer (PORTMUX)
16.3.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
-
6
5
4
3
Access
Reset
2
SPI0
R/W
0
1
0
USART0
R/W
0
Bit 2 – SPI0 SPI 0 communication
Write this bit to '1' to select alternative communication pins for SPI 0.
Bit 0 – USART0 USART 0 communication
Write this bit to '1' to select alternative communication pins for USART 0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 130
ATtiny202/204/402/404/406 Automotiv...
Port Multiplexer (PORTMUX)
16.3.3
Control C
Name:
Offset:
Reset:
Property:
Bit
7
CTRLC
0x02
0x00
-
6
Access
Reset
5
TCA05
R/W
0
4
TCA04
R/W
0
3
TCA03
R/W
0
2
TCA02
R/W
0
1
TCA01
R/W
0
0
TCA00
R/W
0
Bit 5 – TCA05 TCA0 Waveform output 5
Write this bit to '1' to select alternative output pin for TCA0 waveform output 5 in Split mode.
Not applicable when TCA in normal mode.
Bit 4 – TCA04 TCA0 Waveform output 4
Write this bit to '1' to select alternative output pin for TCA0 waveform output 4 in Split mode.
Not applicable when TCA in normal mode.
Bit 3 – TCA03 TCA0 Waveform output 3
Write this bit to '1' to select alternative output pin for TCA0 waveform output 3 in Split mode.
Not applicable when TCA in normal mode.
Bit 2 – TCA02 TCA0 Waveform output 2
Write this bit to '1' to select alternative output pin for TCA0 waveform output 2.
In Split Mode, this bit controls output from low byte compare channel 2.
Bit 1 – TCA01 TCA0 Waveform output 1
Write this bit to '1' to select alternative output pin for TCA0 waveform output 1.
In Split mode, this bit controls output from low byte compare channel 1.
Bit 0 – TCA00 TCA0 Waveform output 0
Write this bit to '1' to select alternative output pin for TCA0 waveform output 0.
In Split mode, this bit controls output from low byte compare channel 0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 131
ATtiny202/204/402/404/406 Automotiv...
Port Multiplexer (PORTMUX)
16.3.4
Control D
Name:
Offset:
Reset:
Property:
Bit
7
CTRLD
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
TCB0
R/W
0
Bit 0 – TCB0 TCB0 output
Write this bit to '1' to select alternative output pin for 16-bit timer/counter B 0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 132
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.
I/O Pin Configuration (PORT)
17.1
Features
•
•
•
•
•
17.2
General Purpose Input and Output Pins with Individual Configuration
Output Driver with Configurable Inverted I/O and Pullup
Input with Interrupts and Events:
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
Asynchronous Pin Change Sensing That Can Wake the Device From all Sleep Modes
Efficient and Safe Access to Port Pins
– Hardware read-modify-write through dedicated toggle/clear/set registers
– Mapping of often-used PORT registers into bit-accessible I/O memory space (virtual ports)
Overview
The I/O pins of the device are controlled by instances of the port peripheral registers. This device has the following
instances of the I/O pin configuration (PORT): PORTA, PORTB, and PORTC.
Refer to the I/O Multiplexing table to see which pins are controlled by what instance of port. The offsets of the port
instances and of the corresponding virtual port instances are listed in the Peripherals and Architecture section.
Each of the port pins has a corresponding bit in the Data Direction (PORT.DIR) and Data Output Value (PORT.OUT)
registers to enable that pin as an output and to define the output state. For example, pin PA3 is controlled by DIR[3]
and OUT[3] of the PORTA instance.
The Data Input Value (PORT.IN) is set as the input value of a port pin with resynchronization to the main clock. To
reduce power consumption, these input synchronizers are not clocked if the Input Sense Configuration bit field (ISC)
in PORT.PINnCTRL is INPUT_DISABLE. The value of the pin can always be read, whether the pin is configured as
input or output.
The port also supports synchronous and asynchronous input sensing with interrupts for selectable pin change
conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes,
including the modes where no clocks are running.
All pin functions are configurable individually per pin. The pins have hardware read-modify-write (RMW) functionality
for a safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be
changed without unintentionally changing the direction of any other pin.
The port pin configuration also controls input and output selection of other device functions.
Related Links
5. I/O Multiplexing and Considerations
8. Peripherals and Architecture
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 133
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.2.1
Block Diagram
Figure 17-1. PORT Block Diagram
Pullup enable
Invert Enable
OUTn
Q
D
Pxn
OUT Override
R
DIRn
Q
D
DIR
Override
R
Input Disable
Input
Disable
Override
Synchronizer
INn
Synchronized
input
Q
D Q
R
D
R
Digital Input /
Asynchronous event
Analog input/output
17.2.2
Signal Description
Signal
Type
Description
EXTINT
Digital input
External interrupt - available on all I/O pins
Related Links
5. I/O Multiplexing and Considerations
17.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 134
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
Table 17-1. PORT System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
No
-
Related Links
17.2.3.4 Events
17.2.3.1 Clocks
17.2.3.3 Interrupts
17.2.3.1 Clocks
This peripheral depends on the peripheral clock.
17.2.3.2 I/O Lines and Connections
Not applicable.
17.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
17.3.3 Interrupts
9.7.3 SREG
17.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
17.2.3.5 Debug Operation
This peripheral is unaffected by entering Debug mode.
17.3
Functional Description
17.3.1
Initialization
After Reset, all standard function device I/O pads are connected to the port with outputs tri-stated and input buffers
enabled, even if there is no clock running.
For best power consumption, disable the input of unused pins and pins that are used as analog inputs or outputs.
Specific pins, such as those used for connecting a debugger, may be configured differently, as required by their
special function.
17.3.2
Operation
17.3.2.1 Basic Functions
Each I/O pin Pxn can be controlled by the registers in PORTx. Each pin group x has its own set of PORT registers.
The base address of the register set for pin n is at the byte address PORT + 0x10 + � . The index within that register
set is n.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 135
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
To use pin number n as an output only, write bit n of the PORTx.DIR register to '1'. This can be done by writing bit n in
the PORTx.DIRSET register to '1', which will avoid disturbing the configuration of other pins in that group. The nth bit
in the PORTx.OUT register must be written to the desired output value.
Similarly, writing a PORTx.OUTSET bit to '1' will set the corresponding bit in the PORTx.OUT register to '1'. Writing a
bit in PORTx.OUTCLR to '1' will clear that bit in PORTx.OUT to zero. Writing a bit in PORTx.OUTTGL or PORTx.IN to
'1' will toggle that bit in PORTx.OUT.
To use pin n as an input, bit n in the PORTx.DIR register must be written to '0' to disable the output driver. This can
be done by writing bit n in the PORTx.DIRCLR register to '1', which will avoid disturbing the configuration of other
pins in that group. The input value can be read from bit n in register PORTx.IN as long as the ISC bit is not set to
INPUT_DISABLE.
Writing a bit to '1' in PORTx.DIRTGL will toggle that bit in PORTx.DIR and toggle the direction of the corresponding
pin.
17.3.2.2 Virtual Ports
The Virtual PORT registers map the most frequently used regular PORT registers into the bit-accessible I/O space.
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for memoryspecific instructions, such as bit-manipulation instructions, which are not valid for the extended I/O memory space
where the regular PORT registers reside.
Table 17-2. Virtual Port Mapping
Regular PORT Register
Mapped to Virtual PORT Register
PORT.DIR
VPORT.DIR
PORT.OUT
VPORT.OUT
PORT.IN
VPORT.IN
PORT.INTFLAG
VPORT.INTFLAG
Related Links
17.6 Register Summary - VPORT
5. I/O Multiplexing and Considerations
8. Peripherals and Architecture
17.3.2.3 Pin Configuration
The Pin n Configuration register (PORT.PINnCTRL) is used to configure inverted I/O, pullup, and input sensing of a
pin.
All input and output on the respective pin n can be inverted by writing a '1' to the Inverted I/O Enable bit (INVEN) in
PORT.PINnCTRL.
Toggling the INVEN bit causes an edge on the pin, which can be detected by all peripherals using this pin, and is
seen by interrupts or events if enabled.
Pullup of pin n is enabled by writing a '1' to the Pullup Enable bit (PULLUPEN) in PORT.PINnCTRL.
Changes of the signal on a pin can trigger an interrupt. The exact conditions are defined by writing to the Input/Sense
bit field (ISC) in PORT.PINnCTRL.
When setting or changing interrupt settings, take these points into account:
• If an INVEN bit is toggled in the same cycle as the interrupt setting, the edge caused by the inversion toggling
may not cause an interrupt request.
• If an input is disabled while synchronizing an interrupt, that interrupt may be requested on re-enabling the input,
even if it is re-enabled with a different interrupt setting.
• If the interrupt setting is changed while synchronizing an interrupt, that interrupt may not be accepted.
• Only a few pins support full asynchronous interrupt detection, see I/O Multiplexing and Considerations. These
limitations apply for waking the system from sleep:
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 136
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
Interrupt Type
Fully Asynchronous Pins
Other Pins
BOTHEDGES
Will wake system
Will wake system
RISING
Will wake system
Will not wake system
FALLING
Will wake system
Will not wake system
LEVEL
Will wake system
Will wake system
Related Links
5. I/O Multiplexing and Considerations
17.3.3
Interrupts
Table 17-3. Available Interrupt Vectors and Sources
Offset Name
0x00
Vector Description
Conditions
PORTx PORT A, B, C interrupt INTn in PORT.INTFLAGS is raised as configured by ISC bit in
PORT.PINnCTRL.
Each port pin n can be configured as an interrupt source. Each interrupt can be individually enabled or disabled by
writing to ISC in PORT.PINCTRL.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Asynchronous Sensing Pin Properties
Table 17-4. Behavior Comparison of Fully/Partly Asynchronous Sense Pin
Property
Synchronous or Partly Asynchronous Sense
Support
Full Asynchronous Sense
Support
Minimum pulse-width to Minimum one system clock cycle
trigger interrupt
Less than a system clock cycle
Waking the device from From all interrupt sense configurations from sleep
sleep
modes with main clock running. Only from
BOTHEDGES or LEVEL interrupt sense configuration
from sleep modes with main clock stopped.
From all interrupt sense
configurations from all sleep
modes
Interrupt "dead time"
No new interrupt for three cycles after the previous
No limitation
Minimum wake-up
pulse length
Value on pad must be kept until the system clock has
restarted
No limitation
Related Links
9. AVR CPU
9.7.3 SREG
17.3.4
Events
All PORT pins are asynchronous event system generators, PORT has as many event generators as there are PORT
pins in the device. Each event system output from PORT is the value present on the corresponding pin if the digital
input driver is enabled. If a pin input driver is disabled, the corresponding event system output is zero.
PORT has no event inputs.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 137
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.3.5
Sleep Mode Operation
With the exception of interrupts and input synchronization, all pin configurations are independent of the Sleep mode.
Peripherals connected to the ports can be affected by Sleep modes, described in the respective peripherals'
documentation.
The port peripheral will always use the main clock. Input synchronization will halt when this clock stops.
17.3.6
Synchronization
Not applicable.
17.3.7
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 138
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.4
Register Summary - PORT
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
...
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
DIR
DIRSET
DIRCLR
DIRTGL
OUT
OUTSET
OUTCLR
OUTTGL
IN
INTFLAGS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
17.5
DIR[7:0]
DIRSET[7:0]
DIRCLR[7:0]
DIRTGL[7:0]
OUT[7:0]
OUTSET[7:0]
OUTCLR[7:0]
OUTTGL[7:0]
IN[7:0]
INT[7:0]
Reserved
PIN0CTRL
PIN1CTRL
PIN2CTRL
PIN3CTRL
PIN4CTRL
PIN5CTRL
PIN6CTRL
PIN7CTRL
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
INVEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
PULLUPEN
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
ISC[2:0]
Register Description - Ports
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 139
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.1
Data Direction
Name:
Offset:
Reset:
Property:
Bit
7
DIR
0x00
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DIR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIR[7:0] Data Direction
This bit field selects the data direction for the individual pins n of the port.
Writing a '1' to PORT.DIR[n] configures and enables pin n as an output pin.
Writing a '0' to PORT.DIR[n] configures pin n as an input pin. It can be configured by writing to the ISC bit in
PORT.PINnCTRL.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 140
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.2
Data Direction Set
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DIRSET
0x01
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
DIRSET[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIRSET[7:0] Data Direction Set
This bit field can be used instead of a read-modify-write to set individual pins as output.
Writing a '1' to DIRSET[n] will set the corresponding PORT.DIR[n] bit.
Reading this bit field will always return the value of PORT.DIR.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 141
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.3
Data Direction Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DIRCLR
0x02
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
DIRCLR[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIRCLR[7:0] Data Direction Clear
This register can be used instead of a read-modify-write to configure individual pins as input.
Writing a '1' to DIRCLR[n] will clear the corresponding bit in PORT.DIR.
Reading this bit field will always return the value of PORT.DIR.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 142
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.4
Data Direction Toggle
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
DIRTGL
0x03
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
DIRTGL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIRTGL[7:0] Data Direction Toggle
This bit field can be used instead of a read-modify-write to toggle the direction of individual pins.
Writing a '1' to DIRTGL[n] will toggle the corresponding bit in PORT.DIR.
Reading this bit field will always return the value of PORT.DIR.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 143
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.5
Output Value
Name:
Offset:
Reset:
Property:
Bit
7
OUT
0x04
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
OUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUT[7:0] Output Value
This bit field defines the data output value for the individual pins n of the port.
If OUT[n] is written to '1', pin n is driven high.
If OUT[n] is written to '0', pin n is driven low.
In order to have any effect, the pin direction must be configured as output.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 144
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.6
Output Value Set
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
OUTSET
0x05
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
OUTSET[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUTSET[7:0] Output Value Set
This bit field can be used instead of a read-modify-write to set the output value of individual pins to '1'.
Writing a '1' to OUTSET[n] will set the corresponding bit in PORT.OUT.
Reading this bit field will always return the value of PORT.OUT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 145
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.7
Output Value Clear
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
OUTCLR
0x06
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
OUTCLR[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUTCLR[7:0] Output Value Clear
This register can be used instead of a read-modify-write to clear the output value of individual pins to '0'.
Writing a '1' to OUTCLR[n] will clear the corresponding bit in PORT.OUT.
Reading this bit field will always return the value of PORT.OUT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 146
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.8
Output Value Toggle
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
OUTTGL
0x07
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
OUTTGL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUTTGL[7:0] Output Value Toggle
This register can be used instead of a read-modify-write to toggle the output value of individual pins.
Writing a '1' to OUTTGL[n] will toggle the corresponding bit in PORT.OUT.
Reading this bit field will always return the value of PORT.OUT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 147
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.9
Input Value
Name:
Offset:
Reset:
Property:
Bit
7
IN
0x08
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – IN[7:0] Input Value
This register shows the value present on the pins if the digital input driver is enabled. IN[n] shows the value of pin n of
the port. The input is not sampled and cannot be read if the digital input buffers are disabled.
Writing to a bit of PORT.IN will toggle the corresponding bit in PORT.OUT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 148
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.10 Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x09
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
INT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – INT[7:0] Interrupt Pin Flag
The INT Flag is set when a pin change/state matches the pin's input sense configuration.
Writing a '1' to a flag's bit location will clear the flag.
For enabling and executing the interrupt, refer to ISC bit description in PORT.PINnCTRL.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 149
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.5.11 Pin n Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INVEN
R/W
0
PINCTRL
0x10 + n*0x01 [n=0..7]
0x00
-
6
5
4
3
PULLUPEN
R/W
0
2
R/W
0
1
ISC[2:0]
R/W
0
0
R/W
0
Bit 7 – INVEN Inverted I/O Enable
Value
Description
0
I/O on pin n not inverted
1
I/O on pin n inverted
Bit 3 – PULLUPEN Pullup Enable
Value
Description
0
Pullup disabled for pin n
1
Pullup enabled for pin n
Bits 2:0 – ISC[2:0] Input/Sense Configuration
These bits configure the input and sense configuration of pin n. The sense configuration determines how a port
interrupt can be triggered. If the input buffer is disabled, the input cannot be read in the IN register.
Value
Name
Description
0x0
INTDISABLE
Interrupt disabled but input buffer enabled
0x1
BOTHEDGES
Sense both edges
0x2
RISING
Sense rising edge
0x3
FALLING
Sense falling edge
0x4
INPUT_DISABLE
Digital input buffer disabled
0x5
LEVEL
Sense low level
other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 150
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.6
Register Summary - VPORT
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
DIR
OUT
IN
INTFLAGS
7:0
7:0
7:0
7:0
17.7
DIR[7:0]
OUT[7:0]
IN[7:0]
INT[7:0]
Register Description - Virtual Ports
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 151
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.7.1
Data Direction
Name:
Offset:
Reset:
Property:
DIR
0x00
0x00
-
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for memoryspecific instructions, such as bit-manipulation instructions, which are not valid for the extended I/O memory space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DIR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DIR[7:0] Data Direction
This bit field selects the data direction for the individual pins in the port.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 152
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.7.2
Output Value
Name:
Offset:
Reset:
Property:
OUT
0x01
0x00
-
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for memoryspecific instructions, such as bit-manipulation instructions, which are not valid for the extended I/O memory space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
OUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – OUT[7:0] Output Value
This bit field selects the data output value for the individual pins in the port.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 153
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.7.3
Input Value
Name:
Offset:
Reset:
Property:
IN
0x02
0x00
-
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for memoryspecific instructions, such as bit-manipulation instructions, which are not valid for the extended I/O memory space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
IN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – IN[7:0] Input Value
This bit field holds the value present on the pins if the digital input buffer is enabled.
Writing to a bit of VPORT.IN will toggle the corresponding bit in VPORT.OUT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 154
ATtiny202/204/402/404/406 Automotiv...
I/O Pin Configuration (PORT)
17.7.4
Interrupt Flag
Name:
Offset:
Reset:
Property:
INTFLAGS
0x03
0x00
-
Writing to the Virtual PORT registers has the same effect as writing to the regular registers, but allows for memoryspecific instructions, such as bit-manipulation instructions, which are not valid for the extended I/O memory space
where the regular PORT registers reside.
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
INT[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – INT[7:0] Interrupt Pin Flag
The INT flag is set when a pin change/state matches the pin's input sense configuration, and the pin is configured as
source for port interrupt.
Writing a '1' to this flag's bit location will clear the flag.
For enabling and executing the interrupt, refer to PORT_PINnCTRL.ISC.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 155
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.
Brown-Out Detector (BOD)
18.1
Features
•
•
•
•
•
18.2
Brown-out Detection monitors the power supply to avoid operation below a programmable level
There are three modes:
– Enabled
– Sampled
– Disabled
Separate selection of mode for Active and Sleep modes
Voltage Level Monitor (VLM) with Interrupt
Programmable VLM Level Relative to the BOD Level
Overview
The Brown-out Detector (BOD) monitors the power supply and compares the voltage with two programmable brownout threshold levels. The brown-out threshold level defines when to generate a Reset. A Voltage Level Monitor (VLM)
monitors the power supply and compares it to a threshold higher than the BOD threshold. The VLM can then
generate an interrupt request as an "early warning" when the supply voltage is about to drop below the VLM
threshold. The VLM threshold level is expressed as a percentage above the BOD threshold level.
The BOD is mainly controlled by fuses. The mode used in Standby Sleep mode and Power-Down Sleep mode can be
altered in normal program execution. The VLM part of the BOD is controlled by I/O registers as well.
When activated, the BOD can operate in Enabled mode, where the BOD is continuously active, and in Sampled
mode, where the BOD is activated briefly at a given period to check the supply voltage level.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 156
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.2.1
Block Diagram
Figure 18-1. BOD Block Diagram
VDD
BOD Level
and
Calibration
+
Bandgap
Brown-out
Detection
VLM Interrupt Level
Bandgap
18.2.2
+
VLM Interrupt
Detection
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 18-1. BOD System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
18.2.2.1 Clocks
18.2.2.5 Debug Operation
18.2.2.3 Interrupts
18.2.2.4 Events
18.2.2.1 Clocks
The BOD uses the 32 KHz oscillator (OSCULP32K) as clock source for CLK_BOD.
18.2.2.2 I/O Lines and Connections
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 157
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.2.2.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
18.3.2 Interrupts
18.2.2.4 Events
Not applicable.
18.2.2.5 Debug Operation
This peripheral is unaffected by entering Debug mode.
The VLM interrupt will not be executed if the CPU is halted in Debug mode.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
18.3
Functional Description
18.3.1
Initialization
The BOD settings are loaded from fuses during Reset. The BOD level and operating mode in Active and Idle Sleep
mode are set by fuses and cannot be changed by the CPU. The operating mode in Standby and Power-Down Sleep
mode is loaded from fuses and can be changed by software.
The Voltage Level Monitor function can be enabled by writing a '1' to the VLM Interrupt Enable bit (VLMIE) in the
Interrupt Control register (BOD.INTCTRL). The VLM interrupt is configured by writing the VLM Configuration bits
(VLMCFG) in BOD.INTCTRL. An interrupt is requested when the supply voltage crosses the VLM threshold either
from above, from below, or from any direction.
The VLM functionality will follow the BOD mode. If the BOD is turned off, the VLM will not be enabled, even if the
VLMIE is '1'. If the BOD is using Sampled mode, the VLM will also be sampled. When enabling VLM interrupt, the
interrupt flag will always be set if VLMCFG equals 0x2 and may be set if VLMCFG is configured to 0x0 or 0x1.
The VLM threshold is defined by writing the VLM Level bits (VLMLVL) in the Control A register (BOD.VLMCTRLA).
If the BOD/VLM is enabled in Sampled mode, only VLMCFG=0x1 (crossing threshold from above) in BOD.INTCTRL
will trigger an interrupt.
18.3.2
Interrupts
Table 18-2. Available Interrupt Vectors and Sources
Offset Name Vector Description
0x00
VLM
Conditions
Voltage Level Monitor Supply voltage crossing the VLM threshold as configured by VLMCFG in
BOD.INTCTRL
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's Interrupt
Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Related Links
9. AVR CPU
9.7.3 SREG
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 158
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.3.3
Sleep Mode Operation
There are two separate fuses defining the BOD configuration in different sleep modes; One fuse defines the mode
used in Active mode and Idle Sleep mode (ACTIVE in FUSE.BODCFG), and is written to the ACTIVE bits in the
Control A register (BOD.CTRLA). The second fuse (SLEEP in FUSE.BODCFG) selects the mode used in Standby
Sleep mode and Power-Down Sleep mode, and is loaded into the SLEEP bits in the Control A register
(BOD.CTRLA).
The operating mode in Active mode and Idle Sleep mode (i.e., ACTIVE in BOD.CTRLA) cannot be altered by
software. The operating mode in Standby Sleep mode and Power-Down Sleep mode can be altered by writing to the
SLEEP bits in the Control A register (BOD.CTRLA).
When the device is going into Standby Sleep mode or Power-Down Sleep mode, the BOD will change operation
mode as defined by SLEEP in BOD.CTRLA. When the device is waking up from Standby or Power-Down Sleep
mode, the BOD will operate in the mode defined by the ACTIVE bit field in BOD.CTRLA.
18.3.4
Synchronization
Not applicable.
18.3.5
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a
certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four
CPU instructions.
It is possible to try writing to these registers any time, but the values are not altered.
The following registers are under CCP:
Table 18-3. Registers Under Configuration Change Protection
Register
Key
SLEEP in BOD.CTRLA
IOREG
Related Links
9.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 159
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.4
Register Summary - BOD
Offset
Name
Bit Pos.
0x00
0x01
0x02
...
0x07
0x08
0x09
0x0A
0x0B
CTRLA
CTRLB
7:0
7:0
18.5
SAMPFREQ
ACTIVE[1:0]
SLEEP[1:0]
LVL[2:0]
Reserved
VLMCTRLA
INTCTRL
INTFLAGS
STATUS
7:0
7:0
7:0
7:0
VLMCFG[1:0]
VLMLVL[1:0]
VLMIE
VLMIF
VLMS
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 160
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
R
0
CTRLA
0x00
Loaded from fuse
Configuration Change Protection
6
R
0
5
R
0
4
SAMPFREQ
R
x
3
2
1
ACTIVE[1:0]
R
x
0
SLEEP[1:0]
R
x
R/W
x
R/W
x
Bit 4 – SAMPFREQ Sample Frequency
This bit selects the BOD sample frequency.
The Reset value is loaded from the SAMPFREQ bit in FUSE.BODCFG. This bit is under Configuration Change
Protection (CCP).
Value
Description
0x0
Sample frequency is 1 kHz
0x1
Sample frequency is 125 Hz
Bits 3:2 – ACTIVE[1:0] Active
These bits select the BOD operation mode when the device is in Active or Idle mode.
The Reset value is loaded from the ACTIVE bits in FUSE.BODCFG.
Value
Description
0x0
Disabled
0x1
Enabled
0x2
Sampled
0x3
Enabled with wake-up halted until BOD is ready
Bits 1:0 – SLEEP[1:0] Sleep
These bits select the BOD operation mode when the device is in Standby or Power-Down Sleep mode. The Reset
value is loaded from the SLEEP bits in FUSE.BODCFG.
These bits are under Configuration Change Protection (CCP).
Value
Description
0x0
Disabled
0x1
Enabled
0x2
Sampled
0x3
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 161
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.5.2
Control B
Name:
Offset:
Reset:
Property:
CTRLB
0x01
Loaded from fuse
-
Bit
7
6
5
4
3
2
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
x
1
LVL[2:0]
R
x
0
R
x
Bits 2:0 – LVL[2:0] BOD Level
These bits select the BOD threshold level.
The Reset value is loaded from the BOD Level bits (LVL) in the BOD Configuration Fuse (FUSE.BODCFG).
Value
Name
Description
0x2
BODLEVEL2
2.6V
0x7
BODLEVEL7
4.2V
Note:
• Values in the description are typical values.
• Refer to the BOD and POR Characteristics in Electrical Characteristics for maximum and minimum values.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 162
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.5.3
VLM Control A
Name:
Offset:
Reset:
Property:
VLMCTRLA
0x08
0x00
-
Bit
7
6
5
4
3
2
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
1
0
VLMLVL[1:0]
R/W
R/W
0
0
Bits 1:0 – VLMLVL[1:0] VLM Level
These bits select the VLM threshold relative to the BOD threshold (LVL in BOD.CTRLB).
Value
Description
0x0
VLM threshold 5% above BOD threshold
0x1
VLM threshold 15% above BOD threshold
0x2
VLM threshold 25% above BOD threshold
other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 163
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
INTCTRL
0x09
0x00
-
Bit
7
6
5
4
3
Access
Reset
R
0
R
0
R
0
R
0
R
0
2
1
VLMCFG[1:0]
R/W
R/W
0
0
0
VLMIE
R/W
0
Bits 2:1 – VLMCFG[1:0] VLM Configuration
These bits select which incidents will trigger a VLM interrupt.
Value
Description
0x0
Voltage crosses VLM threshold from above
0x1
Voltage crosses VLM threshold from below
0x2
Either direction is triggering an interrupt request
Other
Reserved
Bit 0 – VLMIE VLM Interrupt Enable
Writing a '1' to this bit enables the VLM interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 164
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.5.5
VLM Interrupt Flags
Name:
Offset:
Reset:
Property:
INTFLAGS
0x0A
0x00
-
Bit
7
6
5
4
3
2
1
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
VLMIF
R/W
0
Bit 0 – VLMIF VLM Interrupt Flag
This flag is set when a trigger from the VLM is given, as configured by the VLMCFG bit in the BOD.INTCTRL register.
The flag is only updated when the BOD is enabled.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 165
ATtiny202/204/402/404/406 Automotiv...
Brown-Out Detector (BOD)
18.5.6
VLM Status
Name:
Offset:
Reset:
Property:
STATUS
0x0B
0x00
-
Bit
7
6
5
4
3
2
1
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
VLMS
R
0
Bit 0 – VLMS VLM Status
This bit is only valid when the BOD is enabled.
Value
Description
0
The voltage is above the VLM threshold level
1
The voltage is below the VLM threshold level
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 166
ATtiny202/204/402/404/406 Automotiv...
Voltage Reference (VREF)
19.
Voltage Reference (VREF)
19.1
Features
•
•
19.2
Programmable Voltage Reference Sources:
– One for each ADC peripheral
– One for each AC peripheral
Each Reference Source Supports Five Different Voltages:
– 0.55V
– 1.1V
– 1.5V
– 2.5V
– 4.3V
Overview
The Voltage Reference (VREF) peripheral provides control registers for the voltage reference sources used by
several peripherals. The user can select the reference voltages for the ADC0 by writing to the ADC0 Reference
Select bit field (ADC0REFSEL) in the Control A register (VREF.CTRLA), and for AC0 by writing to the AC0 Reference
Select bit field DAC0REFSEL in VREF.CTRLA.
A voltage reference source is enabled automatically when requested by a peripheral. The user can enable the
reference voltage sources (and thus, override the automatic disabling of unused sources) by writing to the respective
Force Enable bit (ADC0REFEN) in the Control B register (VREF.CTRLB). This may be desirable to decrease start-up
time, at the cost of increased power consumption.
19.2.1
Block Diagram
Figure 19-1. VREF Block Diagram
Reference reque st
Reference enable
Reference se lect
Bandgap
Reference
Gen erator
Ban dgap
ena ble
19.3
Functional Description
19.3.1
Initialization
0.55V
1.1V
1.5V
2.5V
4.3V
BUF
Inte rnal
Reference
The default configuration will enable the respective source when the ADC0, AC0 is requesting a reference voltage.
The default reference voltages are 0.55V but can be configured by writing to the respective Reference Select bit field
(ADC0REFSEL, DAC0REFSEL) in the Control A register (VREF.CTRLA).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 167
ATtiny202/204/402/404/406 Automotiv...
Voltage Reference (VREF)
19.4
Register Summary - VREF
Offset
Name
Bit Pos.
0x00
0x01
CTRLA
CTRLB
7:0
7:0
19.5
ADC0REFSEL[2:0]
DAC0REFSEL[2:0]
ADC0REFEN DAC0REFEN
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 168
ATtiny202/204/402/404/406 Automotiv...
Voltage Reference (VREF)
19.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
R/W
0
5
ADC0REFSEL[2:0]
R/W
0
4
3
R/W
0
2
R/W
0
1
DAC0REFSEL[2:0]
R/W
0
0
R/W
0
Bits 6:4 – ADC0REFSEL[2:0] ADC0 Reference Select
These bits select the reference voltage for the ADC0.
Value
Description
0x0
0.55V
0x1
1.1V
0x2
2.5V
0x3
4.3V
0x4
1.5V
other
Reserved
Bits 2:0 – DAC0REFSEL[2:0] AC0 Reference Select
These bits select the reference voltage for the AC0.
Value
Description
0x0
0.55V
0x1
1.1V
0x2
2.5V
0x3
4.3V
0x4
1.5V
other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 169
ATtiny202/204/402/404/406 Automotiv...
Voltage Reference (VREF)
19.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
-
6
5
4
3
Access
Reset
2
1
ADC0REFEN
R/W
0
0
DAC0REFEN
R/W
0
Bit 1 – ADC0REFEN ADC0 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the ADC0 to be running, even if it is not requested.
Writing a '0' to this bit allows automatic enable/disable of the reference source by the peripheral.
Bit 0 – DAC0REFEN AC0 Reference Force Enable
Writing a '1' to this bit forces the voltage reference for the AC0 to be running, even if it is not requested.
Writing a '0' to this bit allows automatic enable/disable of the reference source by the peripheral.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 170
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
20.
Watchdog Timer (WDT)
20.1
Features
•
•
•
•
•
•
•
20.2
Issues a System Reset if the Watchdog Timer is not Cleared Before its Time-out Period
Operating Asynchronously from System Clock Using an Independent Oscillator
Using the 1 kHz Output of the 32 kHz Ultra Low-Power Oscillator (OSCULP32K)
11 Selectable Time-out Periods, from 8 ms to 8s
Two Operation modes:
– Normal mode
– Window mode
Configuration Lock to Prevent Unwanted Changes
Closed Period Timer Activation After First WDT Instruction for Easy Setup
Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It allows the system to
recover from situations such as runaway or deadlocked code, by issuing a Reset. When enabled, the WDT is a
constantly running timer configured to a predefined time-out period. If the WDT is not reset within the time-out period,
it will issue a system Reset. The WDT is reset by executing the WDR (Watchdog Timer Reset) instruction from
software.
The WDT has two modes of operation; Normal mode and Window mode. The settings in the Control A register
(WDT.CTRLA) determine the mode of operation.
A Window mode defines a time slot or "window" inside the time-out period during which the WDT must be reset. If the
WDT is reset outside this window, either too early or too late, a system Reset will be issued. Compared to the Normal
mode, the Window mode can catch situations where a code error causes constant WDR execution.
When enabled, the WDT will run in Active mode and all Sleep modes. It is asynchronous (i.e., running from a CPU
independent clock source). For this reason, it will continue to operate and be able to issue a system Reset even if the
main clock fails.
The CCP mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a
configuration for locking the WDT settings is available.
Related Links
9.5.7 Configuration Change Protection (CCP)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 171
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
20.2.1
Block Diagram
Figure 20-1. WDT Block Diagram
"Inside closed window"
CTRLA
WINDOW
CLK_WDT
"Enable
open window
and clear count"
=
COUNT
PERIOD
=
System
Reset
CTRLA
WDR
(instruction)
20.2.2
Signal Description
Not applicable.
20.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 20-1. WDT System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
No
-
Events
No
-
Debug
Yes
UPDI
Related Links
20.2.3.1 Clocks
20.2.3.5 Debug Operation
20.2.3.1 Clocks
A 1 KHz Oscillator Clock (CLK_WDT_OSC) is sourced from the internal Ultra Low-Power Oscillator, OSCULP32K.
Due to the ultra low-power design, the oscillator is not very accurate, and so the exact time-out period may vary from
device to device. This variation must be kept in mind when designing software that uses the WDT to ensure that the
time-out periods used are valid for all devices.
The Counter Clock CLK_WDT_OSC is asynchronous to the system clock. Due to this asynchronicity, writing to WDT
Control register will require synchronization between the clock domains.
Related Links
32. Electrical Characteristics
20.2.3.2 I/O Lines and Connections
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 172
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
20.2.3.3 Interrupts
Not applicable.
20.2.3.4 Events
Not applicable.
20.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
When halting the CPU in Debug mode, the WDT counter is reset.
When starting the CPU again and the WDT was operating in Window mode, the first closed window time-out period
will be disabled, and a Normal mode time-out period is executed.
Related Links
20.3.2.2 Window Mode
20.3
Functional Description
20.3.1
Initialization
•
•
The WDT is enabled when a non-zero value is written to the Period bits (PERIOD) in the Control A register
(WDT.CTRLA).
Optional: Write a non-zero value to the Window bits (WINDOW) in WDT.CTRLA to enable Window mode
operation.
All bits in the Control A register and the Lock bit (LOCK) in the STATUS register (WDT.STATUS) are write protected
by the Configuration Change Protection mechanism.
The Reset value of WDT.CTRLA is defined by a fuse (FUSE.WDTCFG), so the WDT can be enabled at boot time. If
this is the case, the LOCK bit in WDT.STATUS is set at boot time.
Related Links
20.4 Register Summary - WDT
20.3.2
Operation
20.3.2.1 Normal Mode
In Normal mode operation, a single time-out period is set for the WDT. If the WDT is not reset from software using the
WDR any time before the time out occurs, the WDT will issue a system Reset.
A new WDT time-out period will be started each time the WDT is reset by WDR.
There are 11 possible WDT time-out periods (TOWDT), selectable from 8 ms to 8s by writing to the Period bit field
(PERIOD) in the Control A register (WDT.CTRLA).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 173
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
Figure 20-2. Normal Mode Operation
WDT Count
Timely WDT Reset (WDR)
WDT Timeout
System Reset
Here:
TO WDT = 16ms
5
10
15
20
25
30
TOWDT
35
t [ms]
Normal mode is enabled as long as the WINDOW bit field in the Control A register (WDT.CTRLA) is 0x0.
Related Links
20.4 Register Summary - WDT
20.3.2.2 Window Mode
In Window mode operation, the WDT uses two different time-out periods; a closed Window Time-out period
(TOWDTW) and the normal time out period (TOWDT):
• The closed window time-out period defines a duration from 8 ms to 8s where the WDT cannot be reset. If the
WDT is reset during this period, the WDT will issue a system Reset.
• The normal WDT time-out period, which is also 8 ms to 8s, defines the duration of the open period during which
the WDT can (and should) be reset. The open period will always follow the closed period, so the total duration of
the time-out period is the sum of the closed window and the open window time-out periods.
When enabling Window mode or when going out of Debug mode, the first closed period is activated after the first WDR
instruction.
If a second WDR is issued while a previous WDR is being synchronized, the second one will be ignored.
Figure 20-3. Window Mode Operation
WDT Count
Open
Timely WDT Reset (WDR)
Closed
WDR too early:
System Reset
Here:
TOWDTW =TOWDT = 8ms
5
10
15
20
TOWDTW
25
30
TOWDT
35
t [ms]
The Window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control A register
(WDT.CTRLA), and disabled by writing WINDOW=0x0.
20.3.2.3 Configuration Protection and Lock
The WDT provides two security mechanisms to avoid unintentional changes to the WDT settings:
The first mechanism is the Configuration Change Protection mechanism, employing a timed write procedure for
changing the WDT control registers.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 174
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
The second mechanism locks the configuration by writing a '1' to the LOCK bit in the STATUS register
(WDT.STATUS). When this bit is '1', the Control A register (WDT.CTRLA) cannot be changed. Consequently, the
WDT cannot be disabled from software.
LOCK in WDT.STATUS can only be written to '1'. It can only be cleared in Debug mode.
If the WDT configuration is loaded from fuses, LOCK is automatically set in WDT.STATUS.
Related Links
9.5.7 Configuration Change Protection (CCP)
20.3.3
Events
Not applicable.
20.3.4
Interrupts
Not applicable.
20.3.5
Sleep Mode Operation
The WDT will continue to operate in any sleep mode where the source clock is active.
20.3.6
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A register
(WDT.CTRLA) is synchronized when written. The Synchronization Busy flag (SYNCBUSY) in the STATUS register
(WDT.STATUS) indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.
The following registers are synchronized when written:
• PERIOD bits in Control A register (WDT.CTRLA)
• Window Period bits (WINDOW) in WDT.CTRLA
The WDR instruction will need two to three cycles of the WDT clock in order to be synchronized. Issuing a new WDR
instruction while a WDR instruction is being synchronized will be ignored.
20.3.7
Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to these, a
certain key must be written to the CPU.CCP register first, followed by a write access to the protected bits within four
CPU instructions.
It is possible to try writing to these registers any time, but the values are not altered.
The following registers are under CCP:
Table 20-2. WDT - Registers Under Configuration Change Protection
Register
Key
WDT.CTRLA
IOREG
LOCK bit in WDT.STATUS
IOREG
List of bits/registers protected by CCP.
•
•
•
Period bits in Control A register (CTRLA.PERIOD)
Window Period bits in Control A register (CTRLA.WINDOW)
LOCK bit in STATUS register (STATUS.LOCK)
Related Links
9.5.7 Configuration Change Protection (CCP)
9.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
9.7.1 CCP
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 175
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
20.4
Register Summary - WDT
Offset
Name
Bit Pos.
0x00
0x01
CTRLA
STATUS
7:0
7:0
20.5
WINDOW[3:0]
LOCK
PERIOD[3:0]
SYNCBUSY
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 176
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
20.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
R/W
x
CTRLA
0x00
From FUSE.WDTCFG
Configuration Change Protection
6
5
WINDOW[3:0]
R/W
R/W
x
x
4
3
R/W
x
R/W
x
2
1
PERIOD[3:0]
R/W
R/W
x
x
0
R/W
x
Bits 7:4 – WINDOW[3:0] Window
Writing a non-zero value to these bits enables the Window mode, and selects the duration of the closed period
accordingly.
The bits are optionally lock-protected:
• If LOCK bit in WDT.STATUS is '1', all bits are change-protected (Access = R)
• If LOCK bit in WDT.STATUS is '0', all bits can be changed (Access = R/W)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
other
Name
OFF
8CLK
16CLK
32CLK
64CLK
128CLK
256CLK
512CLK
1KCLK
2KCLK
4KCLK
8KCLK
-
Description
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
1.0s
2.0s
4.0s
8.0s
Reserved
Bits 3:0 – PERIOD[3:0] Period
Writing a non-zero value to this bit enables the WDT, and selects the time-out period in Normal mode accordingly. In
Window mode, these bits select the duration of the open window.
The bits are optionally lock-protected:
• If LOCK in WDT.STATUS is '1', all bits are change-protected (Access = R)
• If LOCK in WDT.STATUS is '0', all bits can be changed (Access = R/W)
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
other
Name
OFF
8CLK
16CLK
32CLK
64CLK
128CLK
256CLK
512CLK
1KCLK
2KCLK
4KCLK
8KCLK
-
© 2019 Microchip Technology Inc.
Description
7.8125 ms
15.25 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
1.0s
2.0s
4.0s
8.0s
Reserved
Complete Datasheet
DS40002159A-page 177
ATtiny202/204/402/404/406 Automotiv...
Watchdog Timer (WDT)
20.5.2
Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
LOCK
R/W
0
STATUS
0x01
0x00
Configuration Change Protection
6
5
4
3
2
1
0
SYNCBUSY
R
0
Bit 7 – LOCK Lock
Writing this bit to '1' write protects the WDT.CTRLA register.
It is only possible to write this bit to '1'. This bit can only be cleared in Debug mode.
If the PERIOD bits in WDT.CTRLA are different from zero after boot code, the lock will automatically be set.
This bit is under CCP.
Bit 0 – SYNCBUSY Synchronization Busy
This bit is set after writing to the WDT.CTRLA register while the data is being synchronized from the system clock
domain to the WDT clock domain.
This bit is cleared by the system after the synchronization is finished.
This bit is not under CCP.
Related Links
20.3.6 Synchronization
20.3.7 Configuration Change Protection
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 178
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.
16-bit Timer/Counter Type A (TCA)
21.1
Features
•
•
•
•
•
•
•
•
•
21.2
16-Bit Timer/Counter
Three Compare Channels
Double Buffered Timer Period Setting
Double Buffered Compare Channels
Waveform Generation:
– Frequency generation
– Single-slope PWM (pulse-width modulation)
– Dual-slope PWM
Count on Event
Timer Overflow Interrupts/Events
One Compare Match per Compare Channel
Two 8-Bit Timer/Counters in Split Mode
Overview
The flexible 16-bit PWM Timer/Counter type A (TCA) provides accurate program execution timing, frequency and
waveform generation, and command execution.
A TCA consists of a base counter and a set of compare channels. The base counter can be used to count clock
cycles or events or let events control how it counts clock cycles. It has direction control and period setting that can be
used for timing. The compare channels can be used together with the base counter to do compare match control,
frequency generation, and pulse width waveform modulation.
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each timer/
counter clock or event input.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control or to synchronize operations.
By default, the TCA is a 16-bit timer/counter. The timer/counter has a Split mode feature that splits it into two 8-bit
timer/counters with three compare channels each. In Split mode each compare channel only supports single-slope
PWM waveform generation.
A block diagram of the 16-bit timer/counter with closely related peripheral modules (in grey) is shown in the figure
below.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 179
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Figure 21-1. 16-bit Timer/Counter and Closely Related Peripherals
Timer/Counter
Base Counter
Timer Period
Counter
Prescaler
Control Logic
Comparator
Buffer
Event
System
PORTS
Compare Channel 0
Compare Channel 1
Compare Channel 2
CLK_PER
Waveform
Generation
This device provides one instance of the TCA peripheral, TCA0.
21.2.1
Block Diagram
The figure below shows a detailed block diagram of the timer/counter.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 180
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Figure 21-2. Timer/Counter Block Diagram
Base Coun ter
PERB
CTRLA
PER
EVCTRL
Clock Select
Event
Select
"count"
"clear"
"load"
"direction"
Counter
CNT
=
=0
OVF/UNF
(INT Req.)
Control Logi c
TOP
"ev"
UPDATE
BV
BOTTOM
Compare
(Unit x = {A,B,C})
BV
CMPnBUF
Control Logi c
CMPn
=
Wav efo rm
Generation
"match"
WOn Out
CMPn
(INT Req.)
The counter register (TCAn.CNT), period registers with buffer (TCAn.PER and TCAn.PERBUF), and compare
registers with buffers (TCAn.CMPx and TCAn.CMPBUFx) are 16-bit registers. All buffer registers have a buffer valid
(BV) flag that indicates when the buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to
determine whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the TCAn.CMPx registers. These comparisons can be used to generate
interrupt requests. The Waveform Generator modes use these comparisons to set the waveform period or pulse
width.
A prescaled peripheral clock and events from the event system can be used to control the counter.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 181
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Figure 21-3. Timer/Counter Clock Logic
CLK_PER
Prescaler
Event System
event
CKSEL
EVACT
(Encoding)
CLK_TCA
CNT
CNTEI
21.2.2
Signal Description
Signal
Description(1)
Type
WO[2:0]
Digital output
Waveform output
WO[5:3]
Digital output
Waveform output - Split mode only
Note:
1. Refer to the I/O Multiplexing and Considerations section to see the availability of WOn on pins.
21.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 21-1. TCA System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
WO[5:0]WO[3:0]
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
21.2.3.1 Clocks
21.2.3.5 Debug Operation
21.2.3.3 Interrupts
21.2.3.4 Events
21.2.3.1 Clocks
This peripheral uses the system clock CLK_PER, and has its own prescaler.
Related Links
11. Clock Controller (CLKCTRL)
21.2.3.2 I/O Lines and Connections
Using the I/O lines of the peripheral requires configuration of the I/O pins.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 182
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Related Links
5. I/O Multiplexing and Considerations
17. I/O Pin Configuration (PORT)
21.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
21.3.5 Interrupts
21.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
21.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
This peripheral can be forced to operate with halted CPU by writing a '1' to the Debug Run bit (DBGRUN) in the
Debug Control register of the peripheral (peripheral.DBGCTRL).
Related Links
31. Unified Program and Debug Interface (UPDI)
21.3
Functional Description
21.3.1
Definitions
The following definitions are used throughout the documentation:
Table 21-2. Timer/Counter Definitions
Name
Description
BOTTOM The counter reaches BOTTOM when it becomes zero.
MAX
The counter reaches MAXimum when it becomes all ones.
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence.
UPDATE The update condition is met when the timer/counter reaches BOTTOM or TOP, depending on the
Waveform Generator mode.
CNT
Counter register value.
CMP
Compare register value.
In general, the term timer is used when the timer/counter is counting periodic clock ticks. The term counter is used
when the input signal has sporadic or irregular ticks.
21.3.2
Initialization
To start using the timer/counter in a basic mode, follow these steps:
• Write a TOP value to the Period register (TCAn.PER)
• Enable the peripheral by writing a '1' to the ENABLE bit in the Control A register (TCAn.CTRLA).
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit field
(CLKSEL) in TCAn.CTRLA.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 183
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
•
•
21.3.3
Optional: By writing a '1' to the Enable Count on Event Input bit (CNTEI) in the Event Control register
(TCAn.EVCTRL), event inputs are counted instead of clock ticks.
The counter value can be read from the Counter bit field (CNT) in the Counter register (TCAn.CNT).
Operation
21.3.3.1 Normal Operation
In normal operation, the counter is counting clock ticks in the direction selected by the Direction bit (DIR) in the
Control E register (TCAn.CTRLE), until it reaches TOP or BOTTOM. The clock ticks are from the peripheral clock
CLK_PER, optionally prescaled, depending on the Clock Select bit field (CLKSEL) in the Control A register
(TCAn.CTRLA).
When up-counting and TOP are reached, the counter will wrap to zero at the next clock tick. When down-counting,
the counter is reloaded with the Period register value (TCAn.PER) when BOTTOM is reached.
Figure 21-4. Normal Operation
CNT written
MAX
"update"
CNT
TOP
BOTTOM
DIR
It is possible to change the counter value in the Counter register (TCAn.CNT) when the counter is running. The write
access to TCAn.CNT has higher priority than count, clear, or reload, and will be immediate. The direction of the
counter can also be changed during normal operation by writing to DIR in TCAn.CTRLE.
21.3.3.2 Double Buffering
The Period register value (TCAn.PER) and the Compare n register values (TCAn.CMPn) are all double buffered
(TCAn.PERBUF and TCAn.CMPnBUF).
Each buffer register has a Buffer Valid flag (PERBV, CMPnBV) in the Control F register (TCAn.CTRLF), which
indicates that the buffer register contains a valid (i.e., new, value that can be copied into the corresponding Period or
Compare register). When the Period register and Compare n registers are used for a compare operation, the BV flag
is set when data is written to the buffer register and cleared on an UPDATE condition. This is shown for a Compare
register below.
Figure 21-5. Period and Compare Double Buffering
BV
UPDATE
"write enable"
"data write"
EN
CMPnBUF
EN
CMPn
CNT
=
"match"
Both the TCAn.CMPn and TCAn.CMPnBUF registers are available as I/O registers. This allows initialization and
bypassing of the buffer register and the double buffering function.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 184
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.3.3.3 Changing the Period
The Counter period is changed by writing a new TOP value to the Period register (TCAn.PER).
No Buffering: If double buffering is not used, any period update is immediate.
Figure 21-6. Changing the Period Without Buffering
Counter wraparound
MAX
"update"
"write"
CNT
BOTTOM
New TOP written to
New TOP written to
PER that is higher
PER that is lower
than current CNT.
than current CNT.
A counter wrap-around can occur in any mode of operation when up-counting without buffering. This is due to the fact
that the registers TCAn.CNT and TCAn.PER are continuously compared: if a new TOP value is written to TCAn.PER
that is lower than current TCAn.CNT, the counter will wrap first, before a compare match happens.
Figure 21-7. Unbuffered Dual-Slope Operation
Counter wraparound
MAX
"update"
"write"
CNT
BOTTOM
New TOP written to
PER that is higher
than current CNT.
New TOP written to
PER that is lower
than current CNT.
With Buffering: When double buffering is used, the buffer can be written at any time and still maintain correct
operation. The TCAn.PER is always updated on the UPDATE condition, as shown for dual-slope operation in the
figure below. This prevents wrap-around and the generation of odd waveforms.
Figure 21-8. Changing the Period Using Buffering
MAX
"update"
"write"
CNT
BOTTOM
New Period written to
PERB that is higher
than current CNT.
New Period written to
PERB that is lower
than current CNT.
New PER is updated
with PERB value.
21.3.3.4 Compare Channel
Each Compare Channel n continuously compares the counter value (TCAn.CNT) with the Compare n register
(TCAn.CMPn). If TCAn.CNT equals TCAn.CMPn, the comparator n signals a match. The match will set the Compare
Channel's interrupt flag at the next timer clock cycle, and the optional interrupt is generated.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 185
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
The Compare n Buffer register (TCAn.CMPnBUF) provides double buffer capability equivalent to that for the period
buffer. The double buffering synchronizes the update of the TCAn.CMPn register with the buffer value to either the
TOP or BOTTOM of the counting sequence, according to the UPDATE condition. The synchronization prevents the
occurrence of odd-length, non-symmetrical pulses for glitch-free output.
21.3.3.4.1 Waveform Generation
The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform
visible on the connected port pin, the following requirements must be met:
1.
2.
3.
4.
5.
A Waveform Generation mode must be selected by writing the WGMODE bit field in TCAn.CTRLB.
The TCA is counting clock ticks, not events (CNTEI=0 in TCAn.EVCTRL).
The compare channels used must be enabled (CMPnEN=1 in TCAn.CTRLB). This will override the
corresponding port pin output register. An alternative pin can be selected by writing to the respective TCA
Waveform Output n bit (TCA0n) in the Control C register of the Port Multiplexer (PORTMUX.CTRLC).
The direction for the associated port pin n must be configured as an output (PORTx.DIR[n]=1).
Optional: Enable inverted waveform output for the associated port pin n (INVEN=1 in PORTx.PINn).
21.3.3.4.2 Frequency (FRQ) Waveform Generation
For frequency generation, the period time (T) is controlled by a TCAn.CMPn register instead of the Period register
(TCAn.PER). The waveform generation output WG is toggled on each compare match between the TCAn.CNT and
TCAn.CMPn registers.
Figure 21-9. Frequency Waveform Generation
Period (T)
Direction change
CNT written
MAX
"update"
TOP
CNT
BOTTOM
WG Output
The waveform frequency (fFRQ) is defined by the following equation:
�FRQ =
f CLK_PER
2� CMPn+1
where N represents the prescaler divider used (CLKSEL in TCAn.CTRLA), and fCLK_PER is the system clock for the
peripherals.
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER/2) when
TCAn.CMPn is written to zero (0x0000) and no prescaling is used (N=1, CLKSEL=0x0 in TCAn.CTRLA).
21.3.3.4.3 Single-Slope PWM Generation
For single-slope Pulse-Width Modulation (PWM) generation, the period (T) is controlled by TCAn.PER, while the
values of TCAn.CMPn control the duty cycle of the WG output. The figure below shows how the counter counts from
BOTTOM to TOP and then restarts from BOTTOM. The waveform generator (WO) output is set at TOP and cleared
on the compare match between the TCAn.CNT and TCAn.CMPn registers.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 186
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Figure 21-10. Single-Slope Pulse-Width Modulation
Period (T)
CMPn=BOTTOM
CMPn=TOP
MAX
TOP
"update"
"match"
CNT
CMPn
BOTTOM
Output WOn
The TCAn.PER register defines the PWM resolution. The minimum resolution is 2 bits (TCA.PER=0x0003), and the
maximum resolution is 16 bits (TCA.PER=MAX).
The following equation calculates the exact resolution for single-slope PWM (RPWM_SS):
�PWM_SS =
log PER+1
log 2
�PWM_SS =
�CLK_PER
� PER+1
The single-slope PWM frequency (fPWM_SS) depends on the period setting (TCA_PER), the system's peripheral clock
frequency fCLK_PER, and the TCA prescaler (CLKSEL in TCAn.CTRLA). It is calculated by the following equation
where N represents the prescaler divider used.:
21.3.3.4.4 Dual-Slope PWM
For dual-slope PWM generation, the period (T) is controlled by TCAn.PER, while the values of TCAn.CMPn control
the duty cycle of the WG output.
The figure below shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP and then from
TOP to BOTTOM. The waveform generator output is set on BOTTOM, cleared on compare match when up-counting,
and set on compare match when down-counting.
Figure 21-11. Dual-Slope Pulse-Width Modulation
Period (T)
CMPn=BOTTOM
CMPn=TOP
"update"
"match"
MAX
CMPn
CNT
TOP
BOTTOM
Waveform Output WOn
Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slope PWM
operation.
The period register (TCAn.PER) defines the PWM resolution. The minimum resolution is 2 bits (TCAn.PER=0x0003),
and the maximum resolution is 16 bits (TCAn.PER=MAX).
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS):
�PWM_DS =
log PER+1
log 2
The PWM frequency depends on the period setting (TCAn.PER), the peripheral clock frequency (fCLK_PER), and the
prescaler divider used (CLKSEL in TCAn.CTRLA). It is calculated by the following equation:
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 187
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
�PWM_DS =
�CLK_PER
2� ⋅ PER
N represents the prescaler divider used.
21.3.3.4.5 Port Override for Waveform Generation
To make the waveform generation available on the port pins, the corresponding port pin direction must be set as
output (PORTx.DIR[n]=1). The TCA will override the port pin values when the compare channel is enabled
(CMPnEN=1 in TCAn.CTRLB) and a Waveform Generation mode is selected.
The figure below shows the port override for TCA. The timer/counter compare channel will override the port pin
output value (OUT) on the corresponding port pin. Enabling inverted I/O on the port pin (INVEN=1 in PORT.PINn)
inverts the corresponding WG output.
Figure 21-12. Port Override for Timer/Counter Type A
OUT
WOn
Waveform
CMPnEN
INVEN
21.3.3.5 Timer/Counter Commands
A set of commands can be issued by software to immediately change the state of the peripheral. These commands
give direct control of the UPDATE, RESTART, and RESET signals. A command is issued by writing the respective
value to the Command bit field (CMD) in the Control E register (TCAn.CTRLESET).
An Update command has the same effect as when an update condition occurs, except that the Update command is
not affected by the state of the Lock Update bit (LUPD) in the Control E register (TCAn.CTRLE).
The software can force a restart of the current waveform period by issuing a Restart command. In this case the
counter, direction, and all compare outputs are set to zero.
A Reset command will set all timer/counter registers to their initial values. A Reset can be issued only when the timer/
counter is not running (ENABLE=0 in TCAn.CTRLA).
21.3.3.6 Split Mode - Two 8-Bit Timer/Counters
Split Mode Overview
To double the number of timers and PWM channels in the TCA, a Split mode is provided. In this Split mode, the 16-bit
timer/counter acts as two separate 8-bit timers, which each have three compare channels for PWM generation. The
Split mode will only work with single-slope down-count. Split mode does not support event action controlled
operation.
Split Mode Differences to Normal Mode
• Count;
– Down-count only
– Timer/counter counter high and low byte are independent (TCAn.LCNT, TCAn.HCNT)
• Waveform Generation:
– Single-slope PWM only (WGMODE=SINGLESLOPE in TCAn.CTRLB)
• Interrupt:
– No change for low byte Timer/Counter (TCAn.LCNT)
– Underflow interrupt for high byte Timer/Counter (TCAn.HCNT)
– No compare interrupt or flag for High-byte Compare n registers (TCAn.HCMPn)
• Event Actions: Not Compatible
• Buffer registers and Buffer Valid Flags: Unused
• Register Access: Byte Access to all registers
• Temp register: Unused, 16-bit register of the Normal mode are Accessed as 8-bit 'TCA_H' and 'TCA_L',
Respectively
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 188
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Block Diagram
Figure 21-13. Timer/Counter Block Diagram Split Mode
Base Counter
HPER
LPER
"count high"
"load high"
"count low"
"load low"
Counter
HCNT
Clock Select
CTRLA
LCNT
HUNF
Control Logic
(INT Req.)
LUNF
(INT Req.)
=0
BOTTOML
BOTTOMH
=0
Compare
(Unit n = {0,1,2})
LCMPn
Waveform
Generation
"match"
=
WOn Out
LCMPn
(INT Req.)
Compare
(Unit n = {0,1,2})
HCMPn
=
Waveform
Generation
WO[n+3] Out
"match"
Split Mode Initialization
When shifting between Normal mode and Split mode, the functionality of some registers and bits change, but their
values do not. For this reason, disabling the peripheral (ENABLE=0 in TCAn.CTRLA) and doing a hard Reset
(CMD=RESET in TCAn.CTRLESET) is recommended when changing the mode to avoid unexpected behavior.
To start using the timer/counter in basic Split mode after a hard Reset, follow these steps:
• Enable Split mode by writing a '1' to the Split mode enable bit in the Control D register (SPLITM in
TCAn.CTRLD)
• Write a TOP value to the Period registers (TCAn.PER)
• Enable the peripheral by writing a '1' to the ENABLE bit in the Control A register (TCAn.CTRLA).
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit field
(CLKSEL) in TCAn.CTRLA.
• The counter values can be read from the Counter bit field in the Counter registers (TCAn.CNT)
Activating Split mode results in changes to the functionality of some registers and register bits. The modifications are
described in a separate register map.
21.3.4
Events
The TCA is an event generator. The following events will generate a one-cycle strobe on the event channel outputs:
• Timer overflow
• Timer underflow in Split mode
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 189
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
•
•
•
Compare match channel 0
Compare match channel 1
Compare match channel 2
The peripheral can take the following actions on an input event:
•
•
•
•
The counter counts positive edges of the event signal.
The counter counts both positive and negative edges of the event signal.
The counter counts prescaled clock cycles as long as the event signal is high.
The counter counts prescaled clock cycles. The event signal controls the direction of counting. Up-counting
when the event signal is low and down-counting when the event signal is high.
The specific action is selected by writing to the Event Action bits (EVACT) in the Event Control register
(TCAn.EVCTRL). Events as input are enabled by writing a '1' to the Enable Count on Event Input bit (CNTEI in
TCAn.EVCTRL).
Event controlled inputs are not used in Split mode.
21.3.5
Interrupts
Table 21-3. Available Interrupt Vectors and Sources in Normal Mode
Offset Name Vector Description
Conditions
0x00
OVF
The counter has reached its top value and wrapped to zero.
0x04
CMP0 Compare channel 0 interrupt
Match between the counter value and the Compare 0
register.
0x06
CMP1 Compare channel 1 interrupt
Match between the counter value and the Compare 1
register.
0x08
CMP2 Compare channel 2 interrupt
Match between the counter value and the Compare 2
register.
Overflow and compare match
interrupt
Table 21-4. Available Interrupt Vectors and Sources in Split Mode
Offset Name
Vector Description
Conditions
0x00
LUNF
Low byte underflow interrupt Low byte timer reaches BOTTOM.
0x02
HUNF
High byte underflow interrupt High byte timer reaches BOTTOM.
0x04
LCMP0 Compare channel 0 interrupt Match between the counter value and the low byte of Compare 0
register.
0x06
LCMP1 Compare channel 1 interrupt Match between the counter value and the low byte of Compare 1
register.
0x08
LCMP2 Compare channel 2 interrupt Match between the counter value and the low byte of the Compare
2 register.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's Interrupt
Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Related Links
9. AVR CPU
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 190
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
9.7.3 SREG
21.3.6
Sleep Mode Operation
The timer/counter will continue operation in Idle Sleep mode.
21.3.7
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 191
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.4
Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0)
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
...
0x0D
0x0E
0x0F
0x10
...
0x1F
CTRLA
CTRLB
CTRLC
CTRLD
CTRLECLR
CTRLESET
CTRLFCLR
CTRLFSET
Reserved
EVCTRL
INTCTRL
INTFLAGS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0x20
CNT
0x22
...
0x25
Reserved
0x26
PER
0x28
CMP0
0x2A
CMP1
0x2C
CMP2
0x2E
...
0x35
Reserved
0x36
PERBUF
0x38
CMP0nBUF
0x3A
CMP1nBUF
0x3C
CMP2nBUF
21.5
7:0
7:0
7:0
CLKSEL[2:0]
CMP2EN
CMP1EN
CMP0EN
ALUPD
CMP2OV
CMD[1:0]
CMD[1:0]
CMP2BV
CMP1BV
CMP2BV
CMP1BV
ENABLE
WGMODE[2:0]
CMP1OV
LUPD
LUPD
CMP0BV
CMP0BV
EVACT[1:0]
CMP2
CMP2
CMP1
CMP1
CMP0
CMP0
CMP0OV
SPLITM
DIR
DIR
PERBV
PERBV
CNTEI
OVF
OVF
Reserved
DBGCTRL
TEMP
7:0
7:0
TEMP[7:0]
DBGRUN
7:0
15:8
CNT[7:0]
CNT[15:8]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PER[7:0]
PER[15:8]
CMP[7:0]
CMP[15:8]
CMP[7:0]
CMP[15:8]
CMP[7:0]
CMP[15:8]
Reserved
7:0
PERBUF[7:0]
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PERBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
CMPBUF[7:0]
CMPBUF[15:8]
Register Description - Normal Mode
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 192
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
5
Access
Reset
4
3
R/W
0
2
CLKSEL[2:0]
R/W
0
1
R/W
0
0
ENABLE
R/W
0
Bits 3:1 – CLKSEL[2:0] Clock Select
These bits select the clock frequency for the timer/counter.
Value
Name
Description
0x0
DIV1
fTCA = fCLK_PER/1
0x1
DIV2
fTCA = fCLK_PER/2
0x2
DIV4
fTCA = fCLK_PER/4
0x3
DIV8
fTCA = fCLK_PER/8
0x4
DIV16
fTCA = fCLK_PER/16
0x5
DIV64
fTCA = fCLK_PER/64
0x6
DIV256
fTCA = fCLK_PER/256
0x7
DIV1024
fTCA = fCLK_PER/1024
Bit 0 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 193
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.2
Control B - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x01
0x00
-
7
6
CMP2EN
R/W
0
Access
Reset
5
CMP1EN
R/W
0
4
CMP0EN
R/W
0
3
ALUPD
R/W
0
2
R/W
0
1
WGMODE[2:0]
R/W
0
0
R/W
0
Bits 4, 5, 6 – CMPEN Compare n Enable
In the FRQ or PWM Waveform Generation mode, these bits will override the PORT output register for the
corresponding pin.
Value
Description
0
Port output settings for the pin with WOn output respected
1
Port output settings for pin with WOn output overridden in FRQ or PWM Waveform Generation mode
Bit 3 – ALUPD Auto-Lock Update
The Auto-Lock Update feature controls the Lock Update (LUPD) bit in the TCAn.CTRLE register. When ALUPD is
written to ‘1’, LUPD will be set to ‘1’ until the Buffer Valid (CMPnBV) bits of all enabled compare channels are ‘1’. This
condition will clear LUPD.
It will remain cleared until the next UPDATE condition, where the buffer values will be transferred to the CMPn
registers and LUPD will be set to ‘1’ again. This makes sure that CMPnBUF register values are not transferred to the
CMPn registers until all enabled compare buffers are written.
Value
Description
0
LUPD in TCA.CTRLE not altered by system
1
LUPD in TCA.CTRLE set and cleared automatically
Bits 2:0 – WGMODE[2:0] Waveform Generation Mode
These bits select the Waveform Generation mode and control the counting sequence of the counter, TOP value,
UPDATE condition, interrupt condition, and type of waveform that is generated.
No waveform generation is performed in the Normal mode of operation. For all other modes, the result from the
waveform generator will only be directed to the port pins if the corresponding CMPnEN bit has been set to enable
this. The port pin direction must be set as output.
Table 21-5. Timer Waveform Generation Mode
WGMODE[2:0]
Group Configuration
000
NORMAL
001
Value
0x0
0x1
0x3
Mode of Operation
Top
Update
OVF
Normal
PER
TOP
TOP
FRQ
Frequency
CMP0
TOP
TOP
010
-
Reserved
-
-
-
011
SINGLESLOPE
Single-slope PWM
PER
BOTTOM
BOTTOM
100
-
Reserved
-
-
-
101
DSTOP
Dual-slope PWM
PER
BOTTOM
TOP
110
DSBOTH
Dual-slope PWM
PER
BOTTOM
TOP and BOTTOM
111
DSBOTTOM
Dual-slope PWM
PER
BOTTOM
BOTTOM
Name
NORMAL
FRQ
SINGLESLOPE
© 2019 Microchip Technology Inc.
Description
Normal operation mode
Frequency mode
Single-slope PWM mode
Complete Datasheet
DS40002159A-page 194
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
Value
0x5
0x6
0x7
Other
Name
DSTOP
DSBOTH
DSBOTTOM
-
© 2019 Microchip Technology Inc.
Description
Dual-slope PWM mode
Dual-slope PWM mode
Dual-slope PWM mode
Reserved
Complete Datasheet
DS40002159A-page 195
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.3
Control C - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
7
CTRLC
0x02
0x00
-
6
5
4
3
Access
Reset
2
CMP2OV
R/W
0
1
CMP1OV
R/W
0
0
CMP0OV
R/W
0
Bit 2 – CMP2OV Compare Output Value 2
See CMP0OV.
Bit 1 – CMP1OV Compare Output Value 1
See CMP0OV.
Bit 0 – CMP0OV Compare Output Value 0
The CMPnOV bits allow direct access to the waveform generator's output compare value when the timer/counter is
not enabled. This is used to set or clear the WG output value when the timer/counter is not running.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 196
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.4
Control D
Name:
Offset:
Reset:
Property:
Bit
7
CTRLD
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
SPLITM
R/W
0
Bit 0 – SPLITM Enable Split Mode
This bit sets the timer/counter in Split mode operation. It will then work as two 8-bit timer/counters. The register map
will change compared to normal 16-bit mode.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 197
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.5
Control Register E Clear - Normal Mode
Name:
Offset:
Reset:
Property:
CTRLECLR
0x04
0x00
-
The individual Status bit can be cleared by writing a one to its bit location. This allows each bit to be cleared without
the use of a read-modify-write operation on a single register.
Each Status bit can be read out either by reading TCAn.CTRLESET or TCAn.CTRLECLR.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 3:2 – CMD[1:0] Command
These bits are used for software control of update, restart, and reset of the timer/counter. The command bits are
always read as zero.
Value
Name
Description
0x0
NONE
No command
0x1
UPDATE
Force update
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if TC is enabled)
Bit 1 – LUPD Lock Update
Lock update can be used to ensure that all buffers are valid before an update is performed.
Value
Description
0
The buffered registers are updated as soon as an UPDATE condition has occurred.
1
No update of the buffered registers is performed, even though an UPDATE condition has occurred.
Bit 0 – DIR Counter Direction
Normally this bit is controlled in hardware by the Waveform Generation mode or by event actions, but this bit can also
be changed from software.
Value
Description
0
The counter is counting up (incrementing)
1
The counter is counting down (decrementing)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 198
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.6
Control Register E Set - Normal Mode
Name:
Offset:
Reset:
Property:
CTRLESET
0x05
0x00
-
The individual Status bit can be set by writing a '1' to its bit location. This allows each bit to be set without the use of a
read-modify-write operation on a single register.
Each Status bit can be read out either by reading TCAn.CTRLESET or TCAn.CTRLECLR.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 3:2 – CMD[1:0] Command
These bits are used for software control of update, restart, and reset the timer/counter. The command bits are always
read as zero.
Value
Name
Description
0x0
NONE
No command
0x1
UPDATE
Force update
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if TC is enabled)
Bit 1 – LUPD Lock Update
Locking the update ensures that all buffers are valid before an update is performed.
Value
Description
0
The buffered registers are updated as soon as an UPDATE condition has occurred.
1
No update of the buffered registers is performed, even though an UPDATE condition has occurred.
Bit 0 – DIR Counter Direction
Normally this bit is controlled in hardware by the Waveform Generation mode or by event actions, but this bit can also
be changed from software.
Value
Description
0
The counter is counting up (incrementing)
1
The counter is counting down (decrementing)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 199
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.7
Control Register F Clear
Name:
Offset:
Reset:
Property:
CTRLFCLR
0x06
0x00
-
The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be cleared without the
use of a read-modify-write operation on a single register.
Bit
7
6
5
Access
Reset
4
3
CMP2BV
R/W
0
2
CMP1BV
R/W
0
1
CMP0BV
R/W
0
0
PERBV
R/W
0
Bit 3 – CMP2BV Compare 2 Buffer Valid
See CMP0BV.
Bit 2 – CMP1BV Compare 1 Buffer Valid
See CMP0BV.
Bit 1 – CMP0BV Compare 0 Buffer Valid
The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register. These bits are
automatically cleared on an UPDATE condition.
Bit 0 – PERBV Period Buffer Valid
This bit is set when a new value is written to the TCAn.PERBUF register. This bit is automatically cleared on an
UPDATE condition.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 200
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.8
Control Register F Set
Name:
Offset:
Reset:
Property:
CTRLFSET
0x07
0x00
-
The individual status bit can be set by writing a one to its bit location. This allows each bit to be set without the use of
a read-modify-write operation on a single register.
Bit
7
6
5
Access
Reset
4
3
CMP2BV
R/W
0
2
CMP1BV
R/W
0
1
CMP0BV
R/W
0
0
PERBV
R/W
0
Bit 3 – CMP2BV Compare 2 Buffer Valid
See CMP0BV.
Bit 2 – CMP1BV Compare 1 Buffer Valid
See CMP0BV.
Bit 1 – CMP0BV Compare 0 Buffer Valid
The CMPnBV bits are set when a new value is written to the corresponding TCAn.CMPnBUF register. These bits are
automatically cleared on an UPDATE condition.
Bit 0 – PERBV Period Buffer Valid
This bit is set when a new value is written to the TCAn.PERBUF register. This bit is automatically cleared on an
UPDATE condition.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 201
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x09
0x00
-
6
5
4
3
2
1
EVACT[1:0]
Access
Reset
R/W
0
R/W
0
0
CNTEI
R/W
0
Bits 2:1 – EVACT[1:0] Event Action
These bits define what type of event action the counter will increment or decrement.
Value
Name
Description
0x0
EVACT_POSEDGE Count on positive edge event
0x1
EVACT_ANYEDGE Count on any edge event
0x2
EVACT_HIGHLVL Count on prescaled clock while event line is 1.
0x3
EVACT_UPDOWN Count on prescaled clock. The Event controls the count direction. Up-counting
when the event line is 0, down-counting when the event line is 1.
Bit 0 – CNTEI Enable Count on Event Input
Value
Description
0
Counting on Event input is disabled
1
Counting on Event input is enabled according to EVACT bit field
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 202
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.10 Interrupt Control Register - Normal Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INTCTRL
0x0A
0x00
-
6
CMP2
R/W
0
5
CMP1
R/W
0
4
CMP0
R/W
0
3
2
1
0
OVF
R/W
0
Bit 6 – CMP2 Compare Channel 2 Interrupt Enable
See CMP0.
Bit 5 – CMP1 Compare Channel 1 Interrupt Enable
See CMP0.
Bit 4 – CMP0 Compare Channel 0 Interrupt Enable
Writing CMPn bit to '1' enables compare interrupt from channel n.
Bit 0 – OVF Timer Overflow/Underflow Interrupt Enable
Writing OVF bit to '1' enables overflow interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 203
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.11 Interrupt Flag Register - Normal Mode
Name:
Offset:
Reset:
Property:
INTFLAGS
0x0B
0x00
-
The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be set without the use
of a read-modify-write operation on a single register.
Bit
Access
Reset
7
6
CMP2
R/W
0
5
CMP1
R/W
0
4
CMP0
R/W
0
3
2
1
0
OVF
R/W
0
Bit 6 – CMP2 Compare Channel 2 Interrupt Flag
See CMP0 flag description.
Bit 5 – CMP1 Compare Channel 1 Interrupt Flag
See CMP0 flag description.
Bit 4 – CMP0 Compare Channel 0 Interrupt Flag
The Compare Interrupt flag (CMPn) is set on a compare match on the corresponding compare channel.
For all modes of operation, the CMPn flag will be set when a compare match occurs between the Count register
(TCAn.CNT) and the corresponding Compare register (TCAn.CMPn). The CMPn flag will not be cleared
automatically and has to be cleared by software. This is done by writing a one to its bit location.
Bit 0 – OVF Overflow/Underflow Interrupt Flag
This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting.
OVF is not automatically cleared and needs to be cleared by software. This is done by writing a one to its bit location.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 204
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.12 Debug Control Register
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0E
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 205
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.13 Temporary Bits for 16-Bit Access
Name:
Offset:
Reset:
Property:
TEMP
0x0F
0x00
-
The Temporary register is used by the CPU for single-cycle, 16-bit access to the 16-bit registers of this peripheral. It
can be read and written by software. There is one common Temporary register for all the 16-bit registers of this
peripheral.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary Bits for 16-bit Access
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 206
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.14 Counter Register - Normal Mode
Name:
Offset:
Reset:
Property:
CNT
0x20
0x00
-
The TCAn.CNTL and TCAn.CNTH register pair represents the 16-bit value, TCAn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
CPU and UPDI write access has priority over internal updates of the register.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CNT[15:8] Counter High Byte
These bits hold the MSB of the 16-bit counter register.
Bits 7:0 – CNT[7:0] Counter Low Byte
These bits hold the LSB of the 16-bit counter register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 207
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.15 Period Register - Normal Mode
Name:
Offset:
Reset:
Property:
PER
0x26
0xFFFF
-
TCAn.PER contains the 16-bit TOP value in the timer/counter.
The TCAn.PERL and TCAn.PERH register pair represents the 16-bit value, TCAn.PER. The low byte [7:0] (suffix L)
is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PER[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:8 – PER[15:8] Periodic High Byte
These bits hold the MSB of the 16-bit period register.
Bits 7:0 – PER[7:0] Periodic Low Byte
These bits hold the LSB of the 16-bit period register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 208
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.16 Compare n Register - Normal Mode
Name:
Offset:
Reset:
Property:
CMPn
0x28 + n*0x02 [n=0..2]
0x00
-
This register is continuously compared to the counter value. Normally, the outputs from the comparators are then
used for generating waveforms.
TCAn.CMPn registers are updated with the buffer value from their corresponding TCAn.CMPnBUF register when an
UPDATE condition occurs.
The TCAn.CMPnL and TCAn.CMPnH register pair represents the 16-bit value, TCAn.CMPn. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMP[15:8] Compare High Byte
These bits hold the MSB of the 16-bit compare register.
Bits 7:0 – CMP[7:0] Compare Low Byte
These bits hold the LSB of the 16-bit compare register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 209
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.17 Period Buffer Register
Name:
Offset:
Reset:
Property:
PERBUF
0x36
0xFFFF
-
This register serves as the buffer for the period register (TCAn.PER). Accessing this register using the CPU or UPDI
will affect the PERBV flag.
The TCAn.PERBUFL and TCAn.PERBUFH register pair represents the 16-bit value, TCAn.PERBUF. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
12
11
PERBUF[15:8]
R/W
R/W
1
1
4
3
PERBUF[7:0]
R/W
R/W
1
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 15:8 – PERBUF[15:8] Period Buffer High Byte
These bits hold the MSB of the 16-bit period buffer register.
Bits 7:0 – PERBUF[7:0] Period Buffer Low Byte
These bits hold the LSB of the 16-bit period buffer register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 210
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.5.18 Compare n Buffer Register
Name:
Offset:
Reset:
Property:
CMPnBUF
0x38 + n*0x02 [n=0..2]
0x00
-
This register serves as the buffer for the associated compare registers (TCAn.CMPn). Accessing any of these
registers using the CPU or UPDI will affect the corresponding CMPnBV status bit.
The TCAn.CMPnBUFL and TCAn.CMPnBUFH register pair represents the 16-bit value, TCAn.CMPnBUF. The low
byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset
+ 0x01.
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
CMPBUF[15:8]
R/W
R/W
0
0
4
3
CMPBUF[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMPBUF[15:8] Compare High Byte
These bits hold the MSB of the 16-bit compare buffer register.
Bits 7:0 – CMPBUF[7:0] Compare Low Byte
These bits hold the LSB of the 16-bit compare buffer register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 211
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.6
Register Summary - TCA in Split Mode (CTRLD.SPLITM=1)
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
...
0x09
0x0A
0x0B
0x0C
...
0x0D
0x0E
0x0F
...
0x1F
0x20
0x21
0x22
...
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
CTRLA
CTRLB
CTRLC
CTRLD
CTRLECLR
CTRLESET
7:0
7:0
7:0
7:0
7:0
7:0
21.7
HCMP2EN
HCMP2OV
HCMP1EN
HCMP1OV
HCMP0EN
HCMP0OV
CLKSEL[2:0]
LCMP2EN
LCMP2OV
CMD[1:0]
CMD[1:0]
ENABLE
LCMP0EN
LCMP0OV
SPLITM
CMDEN[1:0]
CMDEN[1:0]
LCMP1EN
LCMP1OV
Reserved
INTCTRL
INTFLAGS
7:0
7:0
LCMP2
LCMP2
LCMP1
LCMP1
LCMP0
LCMP0
HUNF
HUNF
LUNF
LUNF
Reserved
DBGCTRL
7:0
DBGRUN
Reserved
LCNT
HCNT
7:0
7:0
LCNT[7:0]
HCNT[7:0]
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
LPER[7:0]
HPER[7:0]
LCMP[7:0]
HCMP[7:0]
LCMP[7:0]
HCMP[7:0]
LCMP[7:0]
HCMP[7:0]
Reserved
LPER
HPER
LCMP0
HCMP0
LCMP1
HCMP1
LCMP2
HCMP2
Register Description - Split Mode
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 212
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
5
Access
Reset
4
3
R/W
0
2
CLKSEL[2:0]
R/W
0
1
R/W
0
0
ENABLE
R/W
0
Bits 3:1 – CLKSEL[2:0] Clock Select
These bits select the clock frequency for the timer/counter.
Value
Name
Description
0x0
DIV1
fTCA = fCLK_PER/1
0x1
DIV2
fTCA = fCLK_PER/2
0x2
DIV4
fTCA = fCLK_PER/4
0x3
DIV8
fTCA = fCLK_PER/8
0x4
DIV16
fTCA = fCLK_PER/16
0x5
DIV64
fTCA = fCLK_PER/64
0x6
DIV256
fTCA = fCLK_PER/256
0x7
DIV1024
fTCA = fCLK_PER/1024
Bit 0 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 213
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.2
Control B - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLB
0x01
0x00
-
6
HCMP2EN
R/W
0
5
HCMP1EN
R/W
0
4
HCMP0EN
R/W
0
3
2
LCMP2EN
R/W
0
1
LCMP1EN
R/W
0
0
LCMP0EN
R/W
0
Bit 6 – HCMP2EN High byte Compare 2 Enable
See LCMP0EN.
Bit 5 – HCMP1EN High byte Compare 1 Enable
See LCMP0EN.
Bit 4 – HCMP0EN High byte Compare 0 Enable
See LCMP0EN.
Bit 2 – LCMP2EN Low byte Compare 2 Enable
See LCMP0EN.
Bit 1 – LCMP1EN Low byte Compare 1 Enable
See LCMP0EN.
Bit 0 – LCMP0EN Low byte Compare 0 Enable
Setting the LCMPnEN/HCMPnEN bits in the FRQ or PWM Waveform Generation mode of operation will override the
port output register for the corresponding WOn pin.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 214
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.3
Control C - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLC
0x02
0x00
-
6
HCMP2OV
R/W
0
5
HCMP1OV
R/W
0
4
HCMP0OV
R/W
0
3
2
LCMP2OV
R/W
0
1
LCMP1OV
R/W
0
0
LCMP0OV
R/W
0
Bit 6 – HCMP2OV High byte Compare 2 Output Value
See LCMP0OV.
Bit 5 – HCMP1OV High byte Compare 1 Output Value
See LCMP0OV.
Bit 4 – HCMP0OV High byte Compare 0 Output Value
See LCMP0OV.
Bit 2 – LCMP2OV Low byte Compare 2 Output Value
See LCMP0OV.
Bit 1 – LCMP1OV Low byte Compare 1 Output Value
See LCMP0OV.
Bit 0 – LCMP0OV Low byte Compare 0 Output Value
The LCMPnOV/HCMPn bits allow direct access to the waveform generator's output compare value when the timer/
counter is not enabled. This is used to set or clear the WOn output value when the timer/counter is not running.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 215
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.4
Control D
Name:
Offset:
Reset:
Property:
Bit
7
CTRLD
0x03
0x00
-
6
5
4
3
Access
Reset
2
1
0
SPLITM
R/W
0
Bit 0 – SPLITM Enable Split Mode
This bit sets the timer/counter in Split mode operation. It will then work as two 8-bit timer/counters. The register map
will change compared to normal 16-bit mode.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 216
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.5
Control Register E Clear - Split Mode
Name:
Offset:
Reset:
Property:
CTRLECLR
0x04
0x00
-
The individual Status bit can be cleared by writing a '1' to its bit location. This allows each bit to be cleared without the
use of a read-modify-write operation on a single register.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
0
CMDEN[1:0]
R/W
R/W
0
0
Bits 3:2 – CMD[1:0] Command
These bits are used for software control of update, restart, and reset of the timer/counter. The command bits are
always read as zero.
Value
Name
Description
0x0
NONE
No command
0x1
Reserved
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if TC is enabled)
Bits 1:0 – CMDEN[1:0] Command enable
These bits are used to indicate for which timer/counter the command (CMD) is valid.
Value
Name
Description
0x0
NONE
None
0x1
LOW
Command valid for low-byte T/C
0x2
HIGH
Command valid for high-byte T/C
0x3
BOTH
Command valid for both low-byte and high-byte T/C
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 217
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.6
Control Register E Set - Split Mode
Name:
Offset:
Reset:
Property:
CTRLESET
0x05
0x00
-
The individual Status bit can be set by writing a '1' to its bit location. This allows each bit to be set without the use of a
read-modify-write operation on a single register.
Bit
7
6
5
4
3
2
CMD[1:0]
Access
Reset
R/W
0
R/W
0
1
0
CMDEN[1:0]
R/W
R/W
0
0
Bits 3:2 – CMD[1:0] Command
These bits are used for software control of update, restart, and reset of the timer/counter. The command bits are
always read as zero. The CMD bits must be used together with CMDEN. Using the reset command requires that both
low-byte and high-byte timer/counter is selected.
Value
Name
Description
0x0
NONE
No command
0x1
Reserved
0x2
RESTART
Force restart
0x3
RESET
Force hard Reset (ignored if TC is enabled)
Bits 1:0 – CMDEN[1:0] Command enable
These bits are used to indicate for which timer/counter the command (CMD) is valid.
Value
Name
Description
0x0
NONE
None
0x1
LOW
Command valid for low-byte T/C
0x2
HIGH
Command valid for high-byte T/C
0x3
BOTH
Command valid for both low-byte and high-byte T/C
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 218
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.7
Interrupt Control Register - Split Mode
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
INTCTRL
0x0A
0x00
-
6
LCMP2
R/W
0
5
LCMP1
R/W
0
4
LCMP0
R/W
0
3
2
1
HUNF
R/W
0
0
LUNF
R/W
0
Bit 6 – LCMP2 Low byte Compare Channel 0 Interrupt Enable
See LCMP0.
Bit 5 – LCMP1 Low byte Compare Channel 1 Interrupt Enable
See LCMP0.
Bit 4 – LCMP0 Low byte Compare Channel 0 Interrupt Enable
Writing LCMPn bit to '1' enables low byte compare interrupt from channel n.
Bit 1 – HUNF High byte Underflow Interrupt Enable
Writing HUNF bit to '1' enables high byte underflow interrupt.
Bit 0 – LUNF Low byte Underflow Interrupt Enable
Writing HUNF bit to '1' enables low byte underflow interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 219
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.8
Interrupt Flag Register - Split Mode
Name:
Offset:
Reset:
Property:
INTFLAGS
0x0B
0x00
-
The individual Status bit can be cleared by writing a ‘1’ to its bit location. This allows each bit to be set without the use
of a read-modify-write operation on a single register.
Bit
Access
Reset
7
6
LCMP2
R/W
0
5
LCMP1
R/W
0
4
LCMP0
R/W
0
3
2
1
HUNF
R/W
0
0
LUNF
R/W
0
Bit 6 – LCMP2 Low byte Compare Channel 0 Interrupt Flag
See LCMP0 flag description.
Bit 5 – LCMP1 Low byte Compare Channel 0 Interrupt Flag
See LCMP0 flag description.
Bit 4 – LCMP0 Low byte Compare Channel 0 Interrupt Flag
The Compare Interrupt flag (LCMPn) is set on a compare match on the corresponding compare channel.
For all modes of operation, the LCMPn flag will be set when a compare match occurs between the Low Byte Count
register (TCAn.LCNT) and the corresponding compare register (TCAn.LCMPn). The LCMPn flag will not be cleared
automatically and has to be cleared by software. This is done by writing a ‘1’ to its bit location.
Bit 1 – HUNF High byte Underflow Interrupt Flag
This flag is set on a high byte timer BOTTOM (underflow) condition. HUNF is not automatically cleared and needs to
be cleared by software. This is done by writing a ‘1’ to its bit location.
Bit 0 – LUNF Low byte Underflow Interrupt Flag
This flag is set on a low byte timer BOTTOM (underflow) condition. LUNF is not automatically cleared and needs to
be cleared by software. This is done by writing a ‘1’ to its bit location.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 220
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.9
Debug Control Register
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0E
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Run in Debug
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 221
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.10 Low Byte Timer Counter Register - Split Mode
Name:
Offset:
Reset:
Property:
LCNT
0x20
0x00
-
TCAn.LCNT contains the counter value in low byte timer. CPU and UPDI write access has priority over count, clear,
or reload of the counter.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LCNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LCNT[7:0] Counter Value for Low Byte Timer
These bits define the counter value of the low byte timer.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 222
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.11 High Byte Timer Counter Register - Split Mode
Name:
Offset:
Reset:
Property:
HCNT
0x21
0x00
-
TCAn.HCNT contains the counter value in high byte timer. CPU and UPDI write access has priority over count, clear,
or reload of the counter.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
HCNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – HCNT[7:0] Counter Value for High Byte Timer
These bits define the counter value in high byte timer.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 223
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.12 Low Byte Timer Period Register - Split Mode
Name:
Offset:
Reset:
Property:
LPER
0x26
0x00
-
The TCAn.LPER register contains the TOP value of low byte timer.
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
LPER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – LPER[7:0] Period Value Low Byte Timer
These bits hold the TOP value of low byte timer.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 224
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.13 High Byte Period Register - Split Mode
Name:
Offset:
Reset:
Property:
HPER
0x27
0x00
-
The TCAn.HPER register contains the TOP value of high byte timer.
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
HPER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – HPER[7:0] Period Value High Byte Timer
These bits hold the TOP value of high byte timer.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 225
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.14 Compare Register n For Low Byte Timer - Split Mode
Name:
Offset:
Reset:
Property:
LCMP
0x28 + n*0x02 [n=0..2]
0x00
-
The TCAn.LCMPn register represents the compare value of compare channel n for low byte Timer. This register is
continuously compared to the counter value of the low byte timer, TCAn.LCNT. Normally, the outputs from the
comparators are then used for generating waveforms.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
LCMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LCMP[7:0] Compare Value of Channel n
These bits hold the compare value of channel n that is compared to TCAn.LCNT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 226
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type A (TCA)
21.7.15 High Byte Compare Register n - Split Mode
Name:
Offset:
Reset:
Property:
HCMP
0x29 + n*0x02 [n=0..2]
0x00
-
The TCAn.HCMPn register represents the compare value of compare channel n for high byte timer. This register is
continuously compared to the counter value of the high byte timer, TCAn.HCNT. Normally, the outputs from the
comparators are then used for generating waveforms.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
HCMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – HCMP[7:0] Compare Value of Channel n
These bits hold the compare value of channel n that is compared to TCAn.HCNT.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 227
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.
16-bit Timer/Counter Type B (TCB)
22.1
Features
•
•
•
22.2
16-Bit Counter Operation Modes:
– Periodic interrupt
– Time-out check
– Input capture
• On event
• Frequency measurement
• Pulse-width measurement
• Frequency and pulse-width measurement
– Single shot
– 8-bit Pulse-Width Modulation (PWM)
Noise Canceler on Event Input
Optional: Operation Synchronous with TCA0
Overview
The capabilities of the 16-bit Timer/Counter type B (TCB) include frequency and waveform generation, and input
capture on event with time and frequency measurement of digital signals. The TCB consists of a base counter and
control logic which can be set in one of eight different modes, each mode providing unique functionality. The base
counter is clocked by the peripheral clock with optional prescaling.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 228
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.2.1
Block Diagram
Figure 22-1. Timer/Counter Type B Block Diagram
TCB
ClockSelect
CTRLA
Mode
CTRLB
EVCTRL
Edge Select
CCMP
DIV2
Counter
"count"
"clear"
CNT
CLK_PER
Control
Logic
CLK_TCA
Event System
IF
(INT Req.)
=
TOP
BOTTOM
=0
Mode, Output enable, initial value
Synchronous
output
Output control
and
Asynchronous logic
Asynchronous
output
22.2.1.1 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filter scheme. When the noise filter is enabled,
the peripheral monitors the event channel and keeps a record of the last four observed samples. If four consecutive
samples are equal, the input is considered to be stable and the signal is fed to the edge detector.
When enabled, the noise canceler introduces an additional delay of four system clock cycles between a change
applied to the input and the update of the input compare register.
The noise canceler uses the system clock and is, therefore, not affected by the prescaler.
22.2.2
Signal Description
Signal
Description
Type
WO
Digital Asynchronous Output
Waveform Output
Related Links
5. I/O Multiplexing and Considerations
22.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 22-1. TCB System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
WO
Interrupts
Yes
CPUINT
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 229
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
...........continued
Dependency
Applicable
Peripheral
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
22.2.3.1 Clocks
22.2.3.5 Debug Operation
22.2.3.3 Interrupts
22.2.3.4 Events
22.2.3.1 Clocks
This peripheral uses the system's peripheral clock CLK_PER. The peripheral has its own local prescaler, or can be
configured to run off the prescaled clock signal of the Timer Counter type A (TCA).
Related Links
11. Clock Controller (CLKCTRL)
22.2.3.2 I/O Lines and Connections
Using the I/O lines of the peripheral requires configuration of the I/O pins.
Related Links
5. I/O Multiplexing and Considerations
17. I/O Pin Configuration (PORT)
22.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
22.3.5 Interrupts
22.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
22.2.3.5 Debug Operation
When the CPU is halted in Debug mode, this peripheral will halt normal operation. This peripheral can be forced to
continue operation during debugging.
This peripheral can be forced to operate with halted CPU by writing a '1' to the Debug Run bit (DBGRUN) in the
Debug Control register of the peripheral (peripheral.DBGCTRL).
Related Links
31. Unified Program and Debug Interface (UPDI)
22.3
Functional Description
22.3.1
Definitions
The following definitions are used throughout the documentation:
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 230
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
Table 22-2. Timer/Counter Definitions
Name
Description
BOTTOM The counter reaches BOTTOM when it becomes zero.
MAX
The counter reaches MAXimum when it becomes all ones.
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence.
UPDATE The update condition is met when the timer/counter reaches BOTTOM or TOP, depending on the
Waveform Generator mode.
CNT
Counter register value.
CCMP
Capture/Compare register value.
In general, the term timer is used when the timer/counter is counting periodic clock ticks. The term counter is used
when the input signal has sporadic or irregular ticks.
22.3.2
Initialization
By default, the TCB is in Periodic Interrupt mode. Follow these steps to start using it:
• Write a TOP value to the Compare/Capture register (TCBn.CCMP).
• Enable the counter by writing a '1' to the ENABLE bit in the Control A register (TCBn.CTRLA).
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bit field (CLKSEL
in TCBn.CTRLA).
• The counter value can be read from the Count register (TCBn.CNT). The peripheral will generate an interrupt
when the CNT value reaches TOP.
22.3.3
Operation
22.3.3.1 Modes
The timer can be configured to run in one of the eight different modes listed below. The event pulse needs to be
longer than one system clock cycle in order to ensure edge detection.
22.3.3.1.1 Periodic Interrupt Mode
In the Periodic Interrupt mode, the counter counts to the capture value and restarts from zero. An interrupt is
generated when the counter is equal to TOP. If TOP is updated to a value lower than count, the counter will continue
until MAX and wrap-around without generating an interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 231
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
Figure 22-2. Periodic Interrupt Mode
TOP changed to a value
lower than CNT
Counter wraps around
MAX
"Interrupt"
TOP
CNT
BOTTOM
22.3.3.1.2 Time-out Check Mode
In this mode, the counter counts to MAX and wraps-around. On the first edge the counter is restarted and on the
second edge, the counter is stopped. If the count register (TCBn.CNT) reaches TOP before the second edge, an
interrupt will be generated. In Freeze state, the counter will restart on a new edge. Reading count (TCBn.CNT) or
compare/capture (TCBn.CCMP) register, or writing run bit (RUN in TCBn.STATUS) in Freeze state will have no effect.
Figure 22-3. Time-out Check Mode
Event Input
TOP changed to a value
lower than CNT
Edge detector
Counter wraps
around
MAX
“ Inter rupt”
CNT
TOP
BOTTOM
22.3.3.1.3 Input Capture on Event Mode
The counter will count from BOTTOM to MAX continuously. When an event is detected the counter value will be
transferred to the Compare/Capture register (TCBn.CCMP) and interrupt is generated. The module has an edge
detector that can be configured to trigger count capture on either rising or falling edges.
The figure below shows the input capture unit configured to capture on falling edge on the event input signal. The
interrupt flag is automatically cleared after the high byte of the Capture register has been read.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 232
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
Figure 22-4. Input Capture on Event
" Interrupt"
Event Input
Edge detector
MAX
CNT
BOTTOM
Co py CN T to CCMP
an d in ter rup t
W rap aro un d
Co py CN T to CCMP
an d in ter rup t
It is recommended to write zero to the TCBn.CNT register when entering this mode from any other mode.
22.3.3.1.4 Input Capture Frequency Measurement Mode
In this mode, the TCB captures the counter value and restarts on either a positive or negative edge of the event input
signal.
The interrupt flag is automatically cleared after the high byte of the Compare/Capture register (TCBn.CCMP) has
been read, and an interrupt request is generated.
The figure below illustrates this mode when configured to act on rising edge.
Figure 22-5. Input Capture Frequency Measurement
" Interrupt "
Event Input
Edge detector
MAX
CNT
BOTTOM
Copy CNT to CCMP,
interrupt and restart
Copy CNT to CCMP,
interrupt and restart
Copy CNT to CCMP,
interrupt and restart
22.3.3.1.5 Input Capture Pulse-Width Measurement Mode
The input capture pulse-width measurement will restart the counter on a positive edge and capture on the next falling
edge before an interrupt request is generated. The interrupt flag is automatically cleared when the high byte of the
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 233
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
capture register is read. The timer will automatically switch between rising and falling edge detection, but a minimum
edge separation of two clock cycles is required for correct behavior.
Figure 22-6. Input Capture Pulse-Width Measurement
" Interrupt "
Event Input
Edge detector
MAX
CNT
BOTTOM
Re sta rt
co unter
Co py CN T to CCMP
an d in ter rup t
Re sta rt
co unter
Co py CN T to CCMP
an d g ive inte rru pt
Re sta rt
co unter
22.3.3.1.6 Input Capture Frequency and Pulse-Width Measurement Mode
In this mode the timer will start counting when a positive edge is detected on the even input signal. On the following
falling edge, the count value is captured. The counter stops when the second rising edge of the event input signal is
detected and this will set the interrupt flag.
Reading the capture will clear the interrupt flag. When the capture register is read or the interrupt flag is cleared the
TC is ready for a new capture sequence. The counter register should, therefore, be read before the capture register
as this is reset to zero at the next positive edge.
Figure 22-7. Input Capture Frequency and Pulse-Width Measurement
Ignore till
Capture is read
Trigger next
capture sequence
Event Input
Edge detector
MAX
" Interrupt"
CNT
BOTTOM
Start
counter
© 2019 Microchip Technology Inc.
Copy CNT to
CCMP
Stop counter and
interrupt
Complete Datasheet
CPU reads the
CCMP register
DS40002159A-page 234
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.3.3.1.7 Single-Shot Mode
This mode can be used to generate a pulse with a duration that is defined by the Compare register (TCBn.CCMP),
every time a rising or falling edge is observed on a connected event channel.
When the counter is stopped, the output pin is driven to low. If an event is detected on the connected event channel,
the timer will reset and start counting from zero to TOP while driving its output high. The RUN bit in the STATUS
register can be read to see if the counter is counting or not. When the counter register reaches the CCMP register
value, the counter will stop and the output pin will go low for at least one prescaler cycle. If a new event arrives during
this time, that event will be ignored. The following figure shows an example waveform. There is a two clock cycle
delay from when the event is received until the output is set high. If the ASYNC bit in TCBn.CTRLB is written to '1', an
asynchronous edge detector is used for input events to give immediate action. When the EDGE bit of the
TCBn.EVCTRL register is written to '1', any edge can trigger the start of the counter. If the EDGE bit is '0', only
positive edges will trigger the start.
The counter will start as soon as the module is enabled, even without triggering event. This is prevented by writing
TOP to the counter register.
Similar behavior is seen if the EDGE bit in the TCBn.EVCTRL register is '1' while the module is enabled. Writing TOP
to the Counter register prevents this as well.
It is not recommended to change configuration while the module is enabled.
Figure 22-8. Single-Shot Mode
Ignored
Ignored
Edge detector
TOP
CNT
" Interrupt"
BOTTOM
Output
Event starts
counter
Counter reaches
TOP value
Event starts
counter
Counter reaches
TOP value
If the ASYNC bit in TCBn.CTRLB is '0', the event pulse needs to be longer than one system clock cycle in order to
ensure edge detection.
22.3.3.1.8 8-Bit PWM Mode
This timer can be configured to run in 8-bit PWM mode where each of the register pairs in the 16-bit Compare/
Capture register (TCBn.CCMPH and TCBn.CCMPL) are used as individual compare registers. The counter will
continuously count from zero to CCMPL and the output will be set at BOTTOM and cleared when the counter
reaches CCMPH.
When this peripheral is enabled and in PWM mode, changing the value of the Compare/Capture register will change
the output, but the transition may output invalid values. It is hence recommended to:
1. Disable the peripheral.
2. Write Compare/Capture register to {CCMPH, CCMPL}.
3. Write 0x0000 to count register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 235
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
4.
Re-enable the module.
CCMPH is the number of cycles for which the output will be driven high, CCMPL+1 is the period of the output pulse.
Output of the module for different capture register values are explained below.
•
•
•
CCMPL = 0
Output = 0
CCMPL = 0xFF
• CCMPH = 0
Output = 0
Output = 1 for CCMPH cycles, low for the rest of the period
• 0 < CCMPH ≤ 0xFF
For 0 < CCMPL < 0xFF
• CCMPH = 0
Output = 0
Output = 1 for CCMPH cycles, low for the rest of the period
• If 0 < CCMPH ≤ CCMPL
• CCMPH = CCMPL + 1
Output = 1
Figure 22-9. 8-Bit PWM Mode
" Interrupt "
CCMPL
CNT
CCMPH
BOTTOM
Output
(CNT == CCMPL) and
output goes high
(CNT == CCMPH) and
output goes low
22.3.3.2 Output
If ASYNC in TCBn.CTRLB is written to '0' ('1'), the output pin is driven synchronously (asynchronously) to the TCB
clock. The bits CCMPINIT, CCMPEN, and CNTMODE in TCBn.CTRLB control how the synchronous output is driven.
The different configurations and their impact on the output are listed in the table below.
Table 22-3. Synchronous Output
CNTMODE
Output, CTRLB=’0’, CCMPEN=1
Output, CTRLB=’1’, CCMPEN=1
Single-Shot mode
Output high when the counter starts
and output low when counter stops
Output high when event arrives and
output low when the counter stops
8-bit PWM mode
PWM mode output
PWM mode output
Modes except single shot and PWM
Bit CCMPINIT in TCBn.CTRLB
Bit CCMPINIT in TCBn.CTRLB
22.3.3.3 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filter scheme. When the noise filter is enabled,
the peripheral monitors the event channel and keeps a record of the last four observed samples. If four consecutive
samples are equal, the input is considered to be stable and the signal is fed to the edge detector.
When enabled, the noise canceler introduces an additional delay of four system clock cycles between a change
applied to the input and the update of the input compare register.
The noise canceler uses the system clock and is, therefore, not affected by the prescaler.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 236
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.3.3.4 Synchronized with TCAn
TCB can be configured to use the clock (CLK_TCA) of the Timer/Counter type A (TCAn) by writing to the Clock
Select bit field (CLKSEL) in the Control A register (TCBn.CTRLA). In this setting, the TCB will count on the exect
same clocks sources as selected in TCA.
When the Synchronize Update bit (SYNCUPD) in the Control A register (TCBn.CTRLA) is written to '1', the TCB
counter will restart when the TCA counter restarts.
Related Links
22.2.1 Block Diagram
22.3.4
Events
The TCB is an event generator. Any condition that causes the CAPT flag in TCBn.INTFLAGS to be set, will also
generate a one-cycle strobe on the event channel output.
The peripheral accepts one event input. If the Capture Event Input Enable bit (CAPTEI) in the Event Control register
(TCBn.EVCTRL) is written to '1', incoming events will result in an event action as defined by the Event Edge bit
(EDGE) in TCBn.EVCTRL. The Single-Shot mode event is edge triggered and will capture changes on the event
input shorter than one system clock cycle. In all other modes, the event line must be held for at least one system
clock cycle to ensure detection of an incoming event.
Related Links
22.5.3 EVCTRL
15. Event System (EVSYS)
22.3.5
Interrupts
Table 22-4. Available Interrupt Vectors and Sources
Offset Name Vector Description
Conditions
0x00
Depending on operating mode. See description of CAPT in TCB.INTFLAG.
CAPT TCB interrupt
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's Interrupt
Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Related Links
14. CPU Interrupt Controller (CPUINT)
22.5.5 INTFLAGS
22.3.6
Sleep Mode Operation
TCB will halt operation in the Power-Down Sleep mode. Standby sleep operation is dependent on the Run in Standby
bit (RUNSTDBY) in the Control A register (TCB.CTRLA).
22.3.7
Synchronization
Not applicable.
22.3.8
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 237
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.4
Register Summary - TCB
Offset
Name
Bit Pos.
0x00
0x01
0x02
...
0x03
0x04
0x05
0x06
0x07
0x08
0x09
CTRLA
CTRLB
7:0
7:0
RUNSTDBY
ASYNC
EVCTRL
INTCTRL
INTFLAGS
STATUS
DBGCTRL
TEMP
FILTER
0x0A
CNT
0x0C
CCMP
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
22.5
CCMPINIT
SYNCUPD
CCMPEN
CLKSEL[1:0]
CNTMODE[2:0]
ENABLE
Reserved
EDGE
CAPTEI
CAPT
CAPT
RUN
DBGRUN
TEMP[7:0]
CNT[7:0]
CNT[15:8]
CCMP[7:0]
CCMP[15:8]
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 238
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
RUNSTDBY
R/W
0
5
4
SYNCUPD
R/W
0
3
2
1
CLKSEL[1:0]
R/W
R/W
0
0
0
ENABLE
R/W
0
Bit 6 – RUNSTDBY Run Standby
Writing a '1' to this bit will enable the peripheral to run in Standby Sleep mode. Not applicable when CLKSEL is set to
0x2 (CLK_TCA).
Bit 4 – SYNCUPD Synchronize Update
When this bit is written to '1', the TCB will restart whenever the TCA0 counter is restarted.
Bits 2:1 – CLKSEL[1:0] Clock Select
Writing these bits selects the clock source for this peripheral.
Value
Description
0x0
CLK_PER
0x1
CLK_PER / 2
0x2
Use CLK_TCA from TCA0
0x3
Reserved
Bit 0 – ENABLE Enable
Writing this bit to '1' enables the Timer/Counter type B peripheral.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 239
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLB
0x01
0x00
-
6
ASYNC
R/W
0
5
CCMPINIT
R/W
0
4
CCMPEN
R/W
0
3
2
R/W
0
1
CNTMODE[2:0]
R/W
0
0
R/W
0
Bit 6 – ASYNC Asynchronous Enable
Writing this bit to '1' will allow asynchronous updates of the TCB output signal in Single-Shot mode.
Value
Description
0
The output will go HIGH when the counter actually starts
1
The output will go HIGH when an event arrives
Bit 5 – CCMPINIT Compare/Capture Pin Initial Value
This bit is used to set the initial output value of the pin when a pin output is used.
Value
Description
0
Initial pin state is LOW
1
Initial pin state is HIGH
Bit 4 – CCMPEN Compare/Capture Output Enable
This bit is used to set the output value of the Compare/Capture Output.
Value
Description
0
Compare/Capture Output is zero
1
Compare/Capture Output has a valid value
Bits 2:0 – CNTMODE[2:0] Timer Mode
Writing these bits selects the Timer mode.
Value
Description
0x0
Periodic Interrupt mode
0x1
Time-out Check mode
0x2
Input Capture on Event mode
0x3
Input Capture Frequency Measurement mode
0x4
Input Capture Pulse-Width Measurement mode
0x5
Input Capture Frequency and Pulse-Width Measurement mode
0x6
Single-Shot mode
0x7
8-Bit PWM mode
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 240
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.3
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x04
0x00
-
7
Access
Reset
6
FILTER
R/W
0
5
4
EDGE
R/W
0
3
2
1
0
CAPTEI
R/W
0
Bit 6 – FILTER Input Capture Noise Cancellation Filter
Writing this bit to '1' enables the input capture noise cancellation unit.
Bit 4 – EDGE Event Edge
This bit is used to select the event edge. The effect of this bit is dependent on the selected Count Mode (CNTMODE)
in TCBn.CTRLB. "-" means that an event or edge has no effect in this mode.
Count Mode
EDGE Positive Edge
Negative Edge
Periodic Interrupt mode
0
-
-
1
-
-
0
Start counter
Stop counter
1
Stop counter
Start counter
0
Input Capture, interrupt
-
1
-
Input Capture, interrupt
0
Input Capture, clear and restart
counter, interrupt
-
1
-
Input Capture, clear and restart
counter, interrupt
0
Clear and restart counter
Input Capture, interrupt
1
Input Capture, interrupt
Clear and restart counter
Timeout Check mode
Input Capture on Event mode
Input Capture Frequency
Measurement mode
Input Capture Pulse-Width
Measurement mode
Input Capture Frequency and Pulse
Width Measurement mode
0
On
1st
Positive: Clear and restart counter
On following Negative: Input Capture
2nd Positive: Stop counter, interrupt
1
On 1st Negative: Clear and restart counter
On following Positive: Input Capture
2nd Negative: Stop counter, interrupt
Single-Shot mode
8-Bit PWM mode
0
Start counter
-
1
-
Start counter
0
-
-
1
-
-
Bit 0 – CAPTEI Capture Event Input Enable
Writing this bit to '1' enables the input capture event.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 241
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.4
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x05
0x00
-
6
5
4
3
Access
Reset
2
1
0
CAPT
R/W
0
Bit 0 – CAPT Capture Interrupt Enable
Writing this bit to '1' enables the Capture interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 242
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.5
Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
INTFLAGS
0x06
0x00
-
7
6
5
4
3
Access
Reset
2
1
0
CAPT
R/W
0
Bit 0 – CAPT Interrupt Flag
This bit is set when an interrupt occurs. The interrupt conditions are dependent on the Counter Mode (CNTMODE) in
TCBn.CTRLB.
This bit is cleared by writing a '1' to it or when the Capture register is read in Capture mode.
Counter Mode
Interrupt Set Condition
Periodic Interrupt mode
Set when the counter reaches TOP
Timeout Check mode
Set when the counter reaches TOP
Input Capture on Event mode
Set when an event occurs and the Capture register is loaded, flag clears
when capture is read
Input Capture Frequency Measurement
mode
Set on edge when the Capture register is loaded and count initialized,
flag clears when capture is read
Input Capture Pulse-Width
Measurement mode
Set on a edge when the Capture register is loaded, previous edge
initialized the count, flag clears when capture is read
Input Capture Frequency and PulseWidth Measurement mode
Set on second (positive or negative) edge when the counter is stopped,
flag clears when capture is read
Single-Shot mode
Set when counter reaches TOP
8-Bit PWM mode
Set when the counter reaches CCH
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 243
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.6
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x07
0x00
-
6
5
4
3
2
1
Access
Reset
0
RUN
R
0
Bit 0 – RUN Run
When the counter is running, this bit is set to '1'. When the counter is stopped, this bit is cleared to '0'.
The bit is read-only and cannot be set by UPDI.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 244
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.7
Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x08
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 245
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.8
Temporary Value
Name:
Offset:
Reset:
Property:
TEMP
0x09
0x00
-
The Temporary register is used by the CPU for single-cycle, 16-bit access to the 16-bit registers of this peripheral. It
can be read and written by software. There is one common Temporary register for all the 16-bit registers of this
peripheral.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary Value
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 246
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.9
Count
Name:
Offset:
Reset:
Property:
CNT
0x0A
0x00
-
The TCBn.CNTL and TCBn.CNTH register pair represents the 16-bit value TCBn.CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
CPU and UPDI write access has priority over internal updates of the register.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CNT[15:8] Count Value High
These bits hold the MSB of the 16-bit Counter register.
Bits 7:0 – CNT[7:0] Count Value Low
These bits hold the LSB of the 16-bit Counter register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 247
ATtiny202/204/402/404/406 Automotiv...
16-bit Timer/Counter Type B (TCB)
22.5.10 Capture/Compare
Name:
Offset:
Reset:
Property:
CCMP
0x0C
0x00
-
The TCBn.CCMPL and TCBn.CCMPH register pair represents the 16-bit value TCBn.CCMP. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
This register has different functions depending on the mode of operation:
• For capture operation, these registers contain the captured value of the counter at the time the capture occurs
• In periodic interrupt/time-out and Single-Shot mode, this register acts as the TOP value
• In 8-bit PWM mode, TCBn.CCMPL and TCBn.CCMPH act as two independent registers
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
CCMP[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CCMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CCMP[15:8] Capture/Compare Value High Byte
These bits hold the MSB of the 16-bit compare, capture, and top value.
Bits 7:0 – CCMP[7:0] Capture/Compare Value Low Byte
These bits hold the LSB of the 16-bit compare, capture, and top value.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 248
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.
Real-Time Counter (RTC)
23.1
Features
•
•
•
•
•
•
•
•
23.2
16-Bit Resolution
Selectable Clock Source:
– External clock
– 32 kHz internal ULP oscillator (OSCULP32K)
– OSCULP32K divided by 32
Programmable 15-Bit Clock Prescaling
One Compare Register
One Period Register
Clear Timer On Period Overflow
Optional Interrupt/Event on Overflow and Compare Match
Periodic Interrupt and Event
Overview
The RTC peripheral offers two timing functions: the Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
The PIT functionality can be enabled independently of the RTC functionality.
RTC - Real-Time Counter
The RTC counts (prescaled) clock cycles in a Counter register, and compares the content of the Counter register to a
Period register and a Compare register.
The RTC can generate both interrupts and events on compare match or overflow. It will generate a compare interrupt
and/or event at the first count after the counter equals the Compare register value, and an overflow interrupt and/or
event at the first count after the counter value equals the Period register value. The overflow will also reset the
counter value to zero.
The RTC peripheral typically runs continuously, including in Low-Power Sleep modes, to keep track of time. It can
wake-up the device from Sleep modes and/or interrupt the device at regular intervals.
The RTC can be clocked from an external clock signal, the 32 kHz internal Ultra Low-Power Oscillator
(OSCULP32K), or the OSCULP32K divided by 32.
The RTC peripheral includes a 15-bit programmable prescaler that can scale down the reference clock before it
reaches the counter. A wide range of resolutions and time-out periods can be configured for the RTC. With a 32.768
kHz clock source, the maximum resolution is 30.5 μs, and timeout periods can be up to two seconds. With a
resolution of 1s, the maximum timeout period is more than 18 hours (65536 seconds). The RTC can give a compare
interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event
when it equals the period register value.
PIT - Periodic Interrupt Timer
Using the same clock source as the RTC function, the PIT can request an interrupt or trigger an output event on
every nth clock period. n can be selected from {4, 8, 16,.. 32768} for interrupts, and from {64, 128, 256,... 8192} for
events.
The PIT uses the same clock source (CLK_RTC) as the RTC function.
Related Links
23.3 RTC Functional Description
23.4 PIT Functional Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 249
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.2.1
Block Diagram
Figure 23-1. Block Diagram
Pxn
32KHz ULP int. Osc.
DIV32
RTC
CLK_RTC
23.2.2
Signal Description
Not applicable.
23.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 23-1. RTC System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
23.2.3.1 Clocks
23.2.3.2 I/O Lines and Connections
23.2.3.5 Debug Operation
23.2.3.3 Interrupts
23.2.3.4 Events
23.2.3.1 Clocks
System clock (CLK_PER) is required to be at least four times faster than RTC clock (CLK_RTC) for reading counter
value, and this is regardless of the RTC_PRESC setting.
Related Links
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 250
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
11. Clock Controller (CLKCTRL)
23.2.3.2 I/O Lines and Connections
An external clock can be used.
Related Links
11. Clock Controller (CLKCTRL)
32. Electrical Characteristics
23.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
23.6 Interrupts
23.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
23.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
This peripheral can be forced to operate with halted CPU by writing a '1' to the Debug Run bit (DBGRUN) in the
Debug Control register of the peripheral (peripheral.DBGCTRL).
Related Links
31. Unified Program and Debug Interface (UPDI)
23.3
RTC Functional Description
The RTC peripheral offers two timing functions: the Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
This subsection describes the RTC.
Related Links
23.4 PIT Functional Description
23.3.1
Initialization
To operate the RTC, the source clock for the RTC counter must be configured before enabling the RTC peripheral,
and the desired actions (interrupt requests, output Events).
Related Links
11. Clock Controller (CLKCTRL)
23.4 PIT Functional Description
23.3.1.1 Configure the Clock CLK_RTC
To configure CLK_RTC, follow these steps:
1.
2.
Configure the desired oscillator to operate as required, in the Clock Controller peripheral (CLKCTRL).
Write the Clock Select bits (CLKSEL) in the Clock Selection register (RTC.CLKSEL) accordingly.
The CLK_RTC clock configuration is used by both RTC and PIT functionality.
23.3.1.2 Configure RTC
To operate the RTC, follow these steps:
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 251
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
1.
2.
3.
4.
Configure the RTC-internal prescaler by writing the PRESCALER bit field in the Control A register
(RTC.CTRLA).
Set the Compare value in the Compare register (RTC.CMP), and/or the Overflow value in the Top register
(RTC.PER).
Enable the desired Interrupts by writing to the respective Interrupt Enable bits (CMP, OVF) in the Interrupt
Control register (RTC.INTCTRL).
Enable the RTC by writing a '1' to the RTC Enable bit (RTCEN) in the Control A register (RTC.CTRLA).
Note: The RTC peripheral is used internally during device start-up. Always check the Busy bits in the RTC.STATUS
and RTC.PITSTATUS registers, also on initial configuration.
23.3.2
Operation - RTC
23.3.2.1 Enabling, Disabling, and Resetting
The RTC is enabled by setting the Enable bit in the Control A register (ENABLE bit in RTC.CTRLA to 1). The RTC is
disabled by writing ENABLE bit in RTC.CTRLA to 0.
23.4
PIT Functional Description
The RTC peripheral offers two timing functions: the Real-Time Counter (RTC) and a Periodic Interrupt Timer (PIT).
This subsection describes the PIT.
Related Links
23.3 RTC Functional Description
23.4.1
Initialization
To operate the PIT, follow these steps:
1. Configure the RTC clock CLK_RTC as described in 23.3.1.1 Configure the Clock CLK_RTC.
2. Select the period for the interrupt by writing the PERIOD bit field in the PIT Control A register
(RTC.PITCTRLA).
3. Enable the interrupt by writing a '1' to the Periodic Interrupt bit (PI) in the PIT Interrupt Control register
(RTC.PITINTCTRL).
4. Enable the PIT by writing a '1' to the PIT Enable bit (PITEN) in the PIT Control A register (RTC.PITCTRLA).
Note: The RTC peripheral is used internally during device start-up. Always check the Busy bits in the RTC.STATUS
and RTC.PITSTATUS registers, also on initial configuration.
23.4.2
Operation - PIT
23.4.2.1 Enabling, Disabling, and Resetting
The PIT is enabled by setting the Enable bit in the PIT Control A register (the PITEN bit in RTC.PITCTRLA to 1). The
PIT is disabled by writing the PITEN bit in RTC.PITCTRLA to 0.
23.4.2.2 PIT Interrupt Timing
Timing of the First Interrupt
The PIT function and the RTC function are running off the same counter inside the prescaler, but both functions’
periods can be configured independently:
• The RTC period is configured by writing the PRESCALER bit field in RTC.CTRLA.
• The PIT period is configured by writing the PERIOD bit field in RTC.PITCTRLA.
The prescaler is off when both functions are off (RTC Enable bit (RTCEN) in RTC.CTRLA and PIT Enable bit (PITEN)
in RTC.PITCTRLA are zero), but it is running (i.e. its internal counter is counting) when either function is enabled.
For this reason, the timing of the first PIT interrupt output is depending on whether the RTC function is already
enabled or not:
• When RTCEN in RTC.CTRLA is zero and PITEN in RTC.PITCTRLA is written to ‘1’, the prescaler will start
operating at the next edge of CLK_RTC, counting from zero. The PIT interrupt output will then toggle from ‘0’ to
‘1’ after ½ period.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 252
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
•
When the RTC function is already enabled (RTCEN is ‘1’), the prescaler is already running, too. The timing of
the first interrupt output from the PIT is depending at which exact counter value the prescaler is enabled. Since
the application can’t access that value, the first interrupt output may occur any time between writing PITEN to ‘1’
and after a full PIT period.
Continuous Operation
After the first interrupt output, the PIT will continue toggling every ½ PIT period, resulting in a full PIT period signal.
Example 23-1. PIT Timing Diagram for PERIOD=CYC16
For PERIOD=CYC16 in RTC.PITCTRLA, the PIT output effectively follows the state of prescaler
counter bit 3, so the resulting interrupt output has a period of 16 CLK_RTC cycles.
When both RTC and PIT functions are disabled, the prescaler is off. The delay between writing
PITEN to ‘1’ and the first interrupt output is always ½ PIT period, with an uncertainty of one leading
CLK_RTC cycle.
When the RTC and hence the prescaler are already enabled with any PRESCALER=DIVn, the time
between writing PITEN to ‘1’ and the first PIT interrupt can vary between virtually 0 and a full PIT
period of 16 CLK_RTC cycles. The precise delay between enabling the PIT and its first output is
depending on the prescaler’s counting phase: the depicted first interrupt in the lower figure is
produced by writing PITEN to ‘1’ at any time inside the leading time window.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 253
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
Figure 23-2. Timing Between PIT Enable and First Interrupt
Enabling PIT with RTC/Prescaler Disabled
CLK_RTC
..000000
..000001
..000010
..000011
..000100
..000101
..000110
..000111
..001000
..001001
..001010
..001011
..001100
..001101
..001110
..001111
..010000
..010001
..010010
..010011
..010100
..010101
..010110
..010111
..011000
..011001
..011010
..011011
..011100
..011101
..011110
..011111
..100000
..100001
..100010
..100011
..100100
..100101
prescaler
counter
value (LSb)
prescaler bit 3
(CYC16)
Continuous Operation
PITENABLE=0
1/2 PIT period
(8 CLK_RTC)
PIT output
write PITENABLE=1
first PIT output
Enabling PIT with RTC/Prescaler Enabled
prescaler
counter
value (LSb)
..000000
..000001
..000010
..000011
..000100
..000101
..000110
..000111
..001000
..001001
..001010
..001011
..001100
..001101
..001110
..001111
..010000
..010001
..010010
..010011
..010100
..010101
..010110
..010111
..011000
..011001
..011010
..011011
..011100
..011101
..011110
..011111
..100000
..100001
..100010
..100011
..100100
..100101
..100110
..100111
..101000
..101001
..101010
..101011
..101100
..101101
..101110
..101111
CLK_RTC
prescaler bit 3
(CYC16)
Continuous Operation
PITENABLE=0
PIT output
time window for writing
PITENABLE=1
first PIT output
23.5
Events
The RTC, when enabled, will generate the following output events:
•
•
Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero. The generated
strobe is synchronous with CLK_RTC and lasts one CLK_RTC cycle.
Compare (CMP): Indicates a match between the counter value and the Compare register. The generated strobe
is synchronous with CLK_RTC and lasts one CLK_RTC cycle.
When enabled, the PIT generates the following 50% duty cycle clock signals on its event outputs:
•
•
•
•
•
Event 0: Clock period = 8192 RTC clock cycles
Event 1: Clock period = 4096 RTC clock cycles
Event 2: Clock period = 2048 RTC clock cycles
Event 3: Clock period = 1024 RTC clock cycles
Event 4: Clock period = 512 RTC clock cycles
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 254
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
•
•
•
Event 5: Clock period = 256 RTC clock cycles
Event 6: Clock period = 128 RTC clock cycles
Event 7: Clock period = 64 RTC clock cycles
The event users are configured by the Event System (EVSYS).
Related Links
15. Event System (EVSYS)
23.6
Interrupts
Table 23-2. Available Interrupt Vectors and Sources
Offset Name Vector Description
0x00
RTC
Real-time counter overflow
and compare match interrupt
Conditions
•
•
0x02
PIT
Periodic Interrupt Timer
interrupt
Overflow (OVF): The counter has reached its top value and
wrapped to zero.
Compare (CMP): Match between the counter value and the
compare register.
A time period has passed, as configured in
RTC_PITCTRLA.PERIOD.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's Interrupt
Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Related Links
14. CPU Interrupt Controller (CPUINT)
23.11.3 INTCTRL
23.11.13 PITINTCTRL
23.7
Sleep Mode Operation
The RTC will continue to operate in Idle Sleep mode. It will run in Standby Sleep mode if the RUNSTDBY bit in
RTC.CTRLA is set.
The PIT will continue to operate in any sleep mode.
Related Links
23.11.1 CTRLA
23.8
Synchronization
Both the RTC and the PIT are asynchronous, operating from a different clock source (CLK_RTC) independently of
the main clock (CLK_PER). For Control and Count register updates, it will take a number of RTC clock and/or
peripheral clock cycles before an updated register value is available in a register or until a configuration change has
an effect on the RTC or PIT, respectively. This synchronization time is described for each register in the Register
Description.
For some RTC registers, a Synchronization Busy flag is available (CMPBUSY, PERBUSY, CNTBUSY, CTRLABUSY)
in the STATUS register (RTC.STATUS).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 255
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
For the RTC.PITCTRLA register, a Synchronization Busy flag (SYNCBUSY) is available in the PIT STATUS register
(RTC.PITSTATUS).
Check for busy should be performed before writing to the mentioned registers.
Related Links
11. Clock Controller (CLKCTRL)
23.9
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 256
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.10
Register Summary - RTC
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
STATUS
INTCTRL
INTFLAGS
TEMP
DBGCTRL
Reserved
CLKSEL
7:0
7:0
7:0
7:0
7:0
7:0
0x08
CNT
0x0A
PER
0x0C
CMP
0x0E
...
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
23.11
RUNSTDBY
PRESCALER[3:0]
CMPBUSY
PERBUSY
CNTBUSY
CMP
CMP
RTCEN
CTRLABUSY
OVF
OVF
TEMP[7:0]
DBGRUN
7:0
7:0
15:8
7:0
15:8
7:0
15:8
CLKSEL[1:0]
CNT[7:0]
CNT[15:8]
PER[7:0]
PER[15:8]
CMP[7:0]
CMP[15:8]
Reserved
PITCTRLA
PITSTATUS
PITINTCTRL
PITINTFLAGS
Reserved
PITDBGCTRL
7:0
7:0
7:0
7:0
PERIOD[3:0]
7:0
PITEN
CTRLBUSY
PI
PI
DBGRUN
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 257
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.1 Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RUNSTDBY
R/W
0
CTRLA
0x00
0x00
-
6
R/W
0
5
4
PRESCALER[3:0]
R/W
R/W
0
0
3
R/W
0
2
1
0
RTCEN
R/W
0
Bit 7 – RUNSTDBY Run in Standby
Value
Description
0
RTC disabled in Standby Sleep mode
1
RTC enabled in Standby Sleep mode
Bits 6:3 – PRESCALER[3:0] Prescaler
These bits define the prescaling of the CLK_RTC clock signal. Due to synchronization between the RTC clock and
system clock domains, there is a latency of two RTC clock cycles from updating the register until this has an effect.
Application software needs to check that the CTRLABUSY flag in RTC.STATUS is cleared before writing to this
register.
Value
Name
Description
0x0
DIV1
RTC clock/1 (no prescaling)
0x1
DIV2
RTC clock/2
0x2
DIV4
RTC clock/4
0x3
DIV8
RTC clock/8
0x4
DIV16
RTC clock/16
0x5
DIV32
RTC clock/32
0x6
DIV64
RTC clock/64
0x7
DIV128
RTC clock/128
0x8
DIV256
RTC clock/256
0x9
DIV512
RTC clock/512
0xA
DIV1024
RTC clock/1024
0xB
DIV2048
RTC clock/2048
0xC
DIV4096
RTC clock/4096
0xD
DIV8192
RTC clock/8192
0xE
DIV16384
RTC clock/16384
0xF
DIV32768
RTC clock/32768
Bit 0 – RTCEN RTC Enable
Value
Description
0
RTC disabled
1
RTC enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 258
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.2 Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x01
0x00
-
6
Access
Reset
5
4
3
CMPBUSY
R
0
2
PERBUSY
R
0
1
CNTBUSY
R
0
0
CTRLABUSY
R
0
Bit 3 – CMPBUSY Compare Synchronization Busy
This bit is indicating whether the RTC is busy synchronizing the Compare register (RTC.CMP) in RTC clock domain.
Bit 2 – PERBUSY Period Synchronization Busy
This bit is indicating whether the RTC is busy synchronizing the Period register (RTC.PER) in RTC clock domain.
Bit 1 – CNTBUSY Counter Synchronization Busy
This bit is indicating whether the RTC is busy synchronizing the Count register (RTC.CNT) in RTC clock domain.
Bit 0 – CTRLABUSY Control A Synchronization Busy
This bit is indicating whether the RTC is busy synchronizing the Control A register (RTC.CTRLA) in RTC clock
domain.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 259
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.3 Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x02
0x00
-
6
5
4
3
Access
Reset
2
1
CMP
R/W
0
0
OVF
R/W
0
Bit 1 – CMP Compare Match Interrupt Enable
Enable interrupt-on-compare match (i.e., when the Counter value (CNT) matches the Compare value (CMP)).
Bit 0 – OVF Overflow Interrupt Enable
Enable interrupt-on-counter overflow (i.e., when the Counter value (CNT) matched the Period value (PER) and wraps
around to zero).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 260
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.4 Interrupt Flag
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x03
0x00
-
6
5
4
3
2
Access
Reset
1
CMP
R
0
0
OVF
R
0
Bit 1 – CMP Compare Match Interrupt Flag
This flag is set when the Counter value (CNT) matches the Compare value (CMP).
Writing a '1' to this bit clears the flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set when the Counter value (CNT) has reached the Period value (PER) and wrapped to zero.
Writing a '1' to this bit clears the flag.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 261
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.5 Temporary
Name:
Offset:
Reset:
Property:
TEMP
0x4
0x00
-
The Temporary register is used by the CPU for single-cycle, 16-bit access to the 16-bit registers of this peripheral. It
can be read and written by software. There is one common Temporary register for all the 16-bit registers of this
peripheral.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 262
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.6 Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x05
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 263
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.7 Clock Selection
Name:
Offset:
Reset:
Property:
Bit
7
CLKSEL
0x07
0x00
-
6
5
4
3
Access
Reset
2
1
0
CLKSEL[1:0]
R/W
R/W
0
0
Bits 1:0 – CLKSEL[1:0] Clock Select
Writing these bits select the source for the RTC clock (CLK_RTC).
Value
Name
Description
0x0
INT32K
32.768 kHz from OSCULP32K
0x1
INT1K
1.024 kHz from OSCULP32K
0x2
Reserved
0x3
EXTCLK
External clock from EXTCLK pin
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 264
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.8 Count
Name:
Offset:
Reset:
Property:
CNT
0x08
0x00
-
The RTC.CNTL and RTC.CNTH register pair represents the 16-bit value, CNT. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the CNTBUSY flag in
RTC.STATUS is cleared before writing to this register.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CNT[15:8] Counter High Byte
These bits hold the MSB of the 16-bit Counter register.
Bits 7:0 – CNT[7:0] Counter Low Byte
These bits hold the LSB of the 16-bit Counter register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 265
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.9 Period
Name:
Offset:
Reset:
Property:
PER
0x0A
0xFF
-
The RTC.PERL and RTC.PERH register pair represents the 16-bit value, PER. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the PERBUSY flag in
RTC.STATUS is cleared before writing to this register.
Bit
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PER[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PER[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:8 – PER[15:8] Period High Byte
These bits hold the MSB of the 16-bit Period register.
Bits 7:0 – PER[7:0] Period Low Byte
These bits hold the LSB of the 16-bit Period register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 266
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.10 Compare
Name:
Offset:
Reset:
Property:
CMP
0x0C
0x00
-
The RTC.CMPL and RTC.CMPH register pair represents the 16-bit value, CMP. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CMP[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – CMP[15:8] Compare High Byte
These bits hold the MSB of the 16-bit Compare register.
Bits 7:0 – CMP[7:0] Compare Low Byte
These bits hold the LSB of the 16-bit Compare register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 267
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.11 Periodic Interrupt Timer Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
PITCTRLA
0x10
0x00
-
6
R/W
0
5
4
PERIOD[3:0]
R/W
R/W
0
0
3
2
R/W
0
1
0
PITEN
R/W
0
Bits 6:3 – PERIOD[3:0] Period
Writing this bit field selects the number of RTC clock cycles between each interrupt.
Value
Name
Description
0x0
OFF
No interrupt
0x1
CYC4
4 cycles
0x2
CYC8
8 cycles
0x3
CYC16
16 cycles
0x4
CYC32
32 cycles
0x5
CYC64
64 cycles
0x6
CYC128
128 cycles
0x7
CYC256
256 cycles
0x8
CYC512
512 cycles
0x9
CYC1024
1024 cycles
0xA
CYC2048
2048 cycles
0xB
CYC4096
4096 cycles
0xC
CYC8192
8192 cycles
0xD
CYC16384
16384 cycles
0xE
CYC32768
32768 cycles
0xF
Reserved
Bit 0 – PITEN Periodic Interrupt Timer Enable
Writing a '1' to this bit enables the Periodic Interrupt Timer.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 268
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.12 Periodic Interrupt Timer Status
Name:
Offset:
Reset:
Property:
Bit
7
PITSTATUS
0x11
0x00
-
6
5
4
3
2
1
Access
Reset
0
CTRLBUSY
R
0
Bit 0 – CTRLBUSY PITCTRLA Synchronization Busy
This bit indicates whether the RTC is busy synchronizing the Periodic Interrupt Timer Control A register
(RTC.PITCTRLA) in the RTC clock domain.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 269
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.13 PIT Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
PITINTCTRL
0x12
0x00
-
6
5
4
3
Access
Reset
2
1
0
PI
R/W
0
Bit 0 – PI Periodic interrupt
Value
Description
0
The periodic interrupt is disabled
1
The periodic interrupt is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 270
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.14 PIT Interrupt Flag
Name:
Offset:
Reset:
Property:
Bit
7
PITINTFLAGS
0x13
0x00
-
6
5
4
3
Access
Reset
2
1
0
PI
R
0
Bit 0 – PI Periodic interrupt Flag
This flag is set when a periodic interrupt is issued.
Writing a '1' clears the flag.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 271
ATtiny202/204/402/404/406 Automotiv...
Real-Time Counter (RTC)
23.11.15 Periodic Interrupt Timer Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
PITDBGCTRL
0x15
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Writing this bit to '1' will enable the PIT to run in Debug mode while the CPU is halted.
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 272
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.
Universal Synchronous and Asynchronous Receiver and Transmitter
(USART)
24.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
24.2
Full-Duplex or One-Wire Half-Duplex Operation
Asynchronous or Synchronous Operation:
– Synchronous clock rates up to 1/2 of the device clock frequency
– Asynchronous clock rates up to 1/8 of the device clock frequency
Supports Serial Frames with:
– 5, 6, 7, 8, or 9 data bits
– Optionally even and odd parity bits
– 1 or 2 Stop bits
Fractional Baud Rate Generator:
– Can generate desired baud rate from any system clock frequency
– No need for external oscillator with certain frequencies
Built-In Error Detection and Correction Schemes:
– Odd or even parity generation and parity check
– Data overrun and framing error detection
– Noise filtering includes false Start bit detection and digital low-pass filter
Separate Interrupts for:
– Transmit complete
– Transmit Data register empty
– Receive complete
Multiprocessor Communication mode:
– Addressing scheme to address specific devices on a multi-device bus
– Enable unaddressed devices to automatically ignore all frames
Start Frame Detection in UART mode
Master SPI mode:
– Double buffered operation
– Configurable data order
– Operation up to 1/2 of the peripheral clock frequency
IRCOM Module for IrDA Compliant Pulse Modulation/Demodulation
LIN Slave Support:
– Auto-baud and Break character detection
RS-485 Support
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) peripheral is a fast and
flexible serial communication module. The USART supports full duplex communication, asynchronous and
synchronous operation, and one-wire configurations. The USART can be set in SPI Master mode and used for SPI
communication.
The USART uses three communication lines for data transfer:
•
•
•
RxD for receiving
TxD for transmitting
XCK for the transmission clock in synchronous operation
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 273
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
Communication is frame based, and the frame format can be customized to support a wide range of standards. One
frame can be directly followed by a new frame, or the communication line can return to the idle (high) state. A serial
frame consists of:
• 1 Start bit
• 5, 6, 7, 8, or 9 data bits (MSb or LSb first)
• Parity bit: Even, odd, or none
• 1 or 2 Stop bits
The USART is buffered in both directions, enabling continued data transmission without any delay between frames.
Separate interrupts for receive and transmit completion allow fully interrupt driven communication. Frame error and
buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and
parity check can also be enabled.
The main functional blocks are the clock generator, the transmitter, and the receiver:
•
•
•
The clock generator includes a fractional Baud Rate Generator that is able to generate a wide range of USART
baud rates from any system clock frequencies. This removes the need to use an oscillator with a specific
frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
The transmitter consists of a single write buffer (DATA), a shift register, and a parity generator. The write buffer
allows continuous data transmission without any delay between frames.
The receiver consists of a two-level receive buffer (DATA) and a Shift register. Data and clock recovery units
ensure robust synchronization and noise filtering during asynchronous data reception. It includes frame error,
buffer overflow, and parity error detection.
When the USART is set in one-wire mode, the transmitter and the receiver share the same TxD I/O pin.
When the USART is set in Master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, Shift registers, and Baud Rate Generator enabled. Pin control and interrupt generation are identical in both
modes. The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2 kbps.
The USART can be linked to the Configurable Custom Logic unit (CCL). When used with the CCL, the TxD/RxD data
can be encoded/decoded before the signal is fed into the USART receiver or after the signal is output from the
transmitter when the USART is connected to CCL LUT outputs.
This device provides one instance of the USART peripheral, USART0.
24.2.1
Signal Description
Signal
Type
Description
RxD
Input
Receiving line
TxD
Input/Output
Transmitting line
XCK
Input/output
Clock for synchronous operation
XDIR
Output
Transmit Enable for RS485
Related Links
5. I/O Multiplexing and Considerations
24.2.2
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 24-1. USART System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 274
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
...........continued
Dependency
Applicable
Peripheral
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
24.2.2.5 Debug Operation
24.2.2.1 Clocks
24.2.2.2 I/O Lines and Connections
24.2.2.3 Interrupts
24.2.2.4 Events
24.2.2.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
11. Clock Controller (CLKCTRL)
24.2.2.2 I/O Lines and Connections
Using the I/O lines of the peripheral requires configuration of the I/O pins.
Related Links
17. I/O Pin Configuration (PORT)
5. I/O Multiplexing and Considerations
24.2.2.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
24.3.4 Interrupts
24.2.2.4 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
24.2.2.5 Debug Operation
When the CPU is halted in Debug mode, this peripheral will continue normal operation. If the peripheral is configured
to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. This peripheral can be forced to halt operation during debugging.
Related Links
31. Unified Program and Debug Interface (UPDI)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 275
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.2.2.6 Block Diagram
Figure 24-1. USART Block Diagram
CLOCK GENERATOR
BAUD
XCK
Baud Rate Generator
TRANSMITTER
XDIR
TXDATA
TX Shift Register
TXD
RECEIVER
RX Buffer
RX Shift Register
RXD
RXDATA
24.3
Functional Description
24.3.1
Initialization
For setting the USART in Full-Duplex mode, the following initialization sequence is recommended:
1.
2.
3.
4.
5.
Set the TxD pin value high, and optionally set the XCK pin low (OUT[n] in PORTx.OUT).
Set the TxD and optionally the XCK pin as an output (DIR[n] in PORTx.DIR).
Set the baud rate (in the USARTn.BAUD register) and frame format.
Set the mode of operation (enables XCK pin output in Synchronous mode).
Enable the transmitter or the receiver, depending on the usage.
For interrupt-driven USART operation, global interrupts should be disabled during the initialization.
Before doing a re-initialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed.
For setting the USART in One-Wire mode, the following initialization sequence is recommended:
1.
2.
3.
4.
5.
6.
Set the TxD/RxD pin value high, and optionally set the XCK pin low.
Optionally, write the ODME bit in the USARTn.CTRLB register to '1' for Wired-AND functionality.
Set the TxD/RxD and optionally the XCK pin as an output.
Select the baud rate and frame format.
Select the mode of operation (enables XCK pin output in Synchronous mode).
Enable the transmitter or the receiver, depending on the usage.
For interrupt-driven USART operation, global interrupts should be disabled during the initialization.
Before doing a re-initialization with a changed baud rate or frame format, be sure that there are no ongoing
transmissions while the registers are changed.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 276
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.3.2
Operation
24.3.2.1 Clock Generation
The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the
fractional Baud Rate Generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are
supported; Normal and Double-Speed Asynchronous mode, Master and Slave Synchronous mode, and Master SPI
mode.
Figure 24-2. Clock Generation Logic Block Diagram
BAUD
RXMODE
BAUD Rate
Generator
fBAUD
/2
/4
0
txclk
1
DDR_XCK
PORT_INV
XCK
Pin
0
1
CLK_PER
xcki
/2
Sync
Register
Edge
Detector
CMODE[0]
0
1
xcko
1
0
DDR_XCK
rxclk
24.3.2.1.1 Internal Clock Generation - The Fractional Baud Rate Generator
The Baud Rate Generator is used for internal clock generation for Asynchronous modes, Aynchronous Master mode,
and Master SPI mode operation. The output frequency generated (fBAUD) is determined by the baud register value
(USARTn.BAUD) and the peripheral clock frequency (fCLK_PER). The following table contains equations for calculating
the baud rate (in bits per second) and for calculating the USARTn.BAUD value for each mode of operation. It also
shows the maximum baud rate versus peripheral clock frequency. For asynchronous operation, the USARTn.BAUD
register value is 16 bits. The 10 MSBs (BAUD[15:6]) hold the integer part, while the 6 LSBs (BAUD[5:0]) hold the
fractional part. In Synchronous mode, only the integer part of the BAUD register determine the baud rate.
Table 24-2. Equations for Calculating Baud Rate Register Setting
Operating Mode Conditions
Asynchronous
Synchronous
����� ≤
����� ≤
Baud Rate (Bits Per Seconds) USART.BAUD Register Value
Calculation
����_���
64 × ����_���
����� =
�
� × ����
����_���
����_���
����� =
2
2 × ���� 15: 6
���� =
64 × ����_���
� × �����
���� 15: 6 =
����_���
2 × �����
S is the number of samples per bit. In Asynchronous operating mode (CMODE[0]=0), it could be set as 16 (NORMAL
mode) or 8 (CLK2X mode) by RXMODE in USARTn.CTRLB. For Synchronous operating mode (CMODE[0]=1), S
equals 2.
24.3.2.1.2 External Clock
External clock (XCK) is used in Synchronous Slave mode operation. The XCK clock input is sampled on the
peripheral clock frequency and the maximum XCK clock frequency (fXCK) is limited by the following:
����<
����_���
4
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 277
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
For each high and low period, the XCK clock cycles must be sampled twice by the peripheral clock. If the XCK clock
has jitter, or if the high/low period duty cycle is not 50/50, the maximum XCK clock speed must be reduced
accordingly.
24.3.2.1.3 Double Speed Operation
Double speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock
frequencies. This operation mode is enabled by writing the RXMODE bit in the Control B register (USARTn.CTRLB)
to CLK2X.
When enabled, the baud rate for a given asynchronous baud rate setting shown in Table 24-2 will be doubled. In this
mode, the receiver will use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery.
This requires a more accurate baud rate setting and peripheral clock. See 24.3.2.4.6 Asynchronous Data Reception
for more details.
24.3.2.1.4 Synchronous Clock Operation
When Synchronous mode is used, the XCK pin controls whether the transmission clock is input (Slave mode) or
output (Saster mode). The corresponding port pin must be set to output for Master mode or to input for Slave mode
(PORTx.DIR[n]). The normal port operation of the XCK pin will be overridden. The dependency between the clock
edges and data sampling or data change is the same. Data input (on RxD) is sampled at the XCK clock edge which
is opposite the edge where data output (TxD) is changed.
Figure 24-3. Synchronous Mode XCK Timing
INVEN = 1
XCK
RxD / TxD
Sample
INVEN = 0
XCK
RxD / TxD
Sample
The I/O pin can be inverted by writing a '1' to the Inverted I/O Enable bit (INVEN) in the Pin n Control register of the
port peripheral (PORTx.PINnCTRL). Using the inverted I/O setting for the corresponding XCK port pin, the XCK clock
edges used for data sampling and data change can be selected. If inverted I/O is disabled (INVEN=0), data will be
changed at the rising XCK clock edge and sampled at the falling XCK clock edge. If inverted I/O is enabled
(INVEN=1), data will be changed at the falling XCK clock edge and sampled at the rising XCK clock edge.
24.3.2.1.5 Master SPI Mode Clock Generation
For Master SPI mode operation, only internal clock generation is supported. This is identical to the USART
Synchronous Master mode, and the baud rate or BAUD setting is calculated using the same equations (see Table
24-2).
There are four combinations of the SPI clock (SCK) phase and polarity with respect to the serial data, and these are
determined by the Clock Phase bit (UCPHA) in the Control C register (USARTn.CTRLC) and the Inverted I/O Enable
bit (INVEN) in the Pin n Control register of the port peripheral (PORTx.PINnCTRL). The data transfer timing diagrams
are shown in Figure 24-4.
Data bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient time for data signals
to stabilize. The settings are summarized in the table below. Changing the setting of any of these bits during
transmission will corrupt both the receiver and transmitter.
Table 24-3. Functionality of INVEN in PORTx.PINnCTRL and UCPHA in USARTn.CTRLC
SPI Mode
INVEN
UCPHA
Leading Edge
Trailing Edge
0
0
0
Rising, sample
Falling, setup
1
0
1
Rising, setup
Falling, sample
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 278
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
...........continued
SPI Mode
INVEN
UCPHA
Leading Edge
Trailing Edge
2
1
0
Falling, sample
Rising, setup
3
1
1
Falling, setup
Rising, sample
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
Figure 24-4. UCPHA and INVEN Data Transfer Timing Diagrams
UCPHA=0
UCPHA=1
INVEN=0
INVEN=1
SPI Mode 1
SPI Mode 3
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
SPI Mode 0
SPI Mode 2
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
Related Links
24.5.9 CTRLC
24.3.2.2 Frame Formats
Data transfer is frame based, where a serial frame consists of one character of data bits with synchronization bits
(Start and Stop bits) and an optional parity bit for error checking. This does not apply to master SPI operation (see
24.3.2.2.2 SPI Frame Formats.) The USART accepts all combinations of the following as valid frame formats:
•
•
•
•
1 Start bit
5, 6, 7, 8, or 9 Data bits
No, even, or odd Parity bit
1 or 2 Stop bits
Figure 24-5 illustrates the possible combinations of frame formats. Bits inside brackets are optional.
Figure 24-5. Frame Formats
St Start bit, always low.
(n) Data bits (0 to 8).
P Parity bit, may be odd or even.
Sp Stop bit, always high.
IDLE No transfer on the communication line (RxD or TxD). The IDLE state is always high.
24.3.2.2.1 Parity
Even or odd parity can be selected for error checking by writing the Parity Mode bits (PMODE) in the Control C
register (USARTn.CTRLC). If even parity is selected, the parity bit is set to '1' if the number of logical one data bits is
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 279
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
odd (making the total number of logical ones even). If odd parity is selected, the parity bit is set to '1' if the number of
logical one data bits is even (making the total number of ones odd).
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result
with the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is set.
24.3.2.2.2 SPI Frame Formats
The serial frame in SPI mode is defined to be one character of eight data bits. The USART in master SPI mode has
two valid frame formats:
•
•
8-bit data, MSb first
8-bit data, LSb first
The data order is selected by writing to the Data Order bit (UDORD) in the Control C register (USARTn.CTRLC).
After a complete frame is transmitted, a new frame can directly follow it, or the communication line can return to the
idle (high) state.
24.3.2.3 Data Transmission - USART Transmitter
When the transmitter has been enabled, the normal port operation of the TxD pin is overridden by the USART and
given the function as the transmitter's serial output. The direction of the pin n must be configured as output by writing
the Direction register for the corresponding port (PORTx.DIR[n]). If the USART is configured for one-wire operation,
the USART will automatically override the RxD/TxD pin to output, when the transmitter is enabled.
Related Links
16. Port Multiplexer (PORTMUX)
17. I/O Pin Configuration (PORT)
24.3.2.3.1 Sending Frames
A data transmission is initiated by loading the Transmit buffer (DATA in USARTn.TXDATA) with the data to be sent.
The data in the transmit buffer is moved to the Shift register when the Shift register is empty and ready to send a new
frame. The Shift register is loaded if it is in Idle state (no ongoing transmission) or immediately after the last Stop bit
of the previous frame is transmitted. When the Shift register is loaded with data, it will transfer one complete frame.
When the entire frame in the Shift register has been shifted out and there is no new data present in the transmit
buffer, the Transmit Complete Interrupt Flag (TXCIF in USARTn.STATUS) is set and the optional interrupt is
generated.
TXDATA can only be written when the Data Register Empty Flag (DREIF in USARTn.STATUS) is set, indicating that
the register is empty and ready for new data.
When using frames with fewer than eight bits, the Most Significant bits written to TXDATA are ignored. If 9-bit
characters are used, DATA[8] in USARTn.TXDATAH has to be written before DATA[7:0] in USARTn.TXDATAL.
24.3.2.3.2 Disabling the Transmitter
A disabling of the transmitter will not become effective until ongoing and pending transmissions are completed; I.e.,
when the Transmit Shift register and Transmit Buffer register do not contain data to be transmitted. When the
transmitter is disabled, it will no longer override the TxDn pin, and the PORT module regains control over the pin. To
protect external circuitry the pin is automatically configured as an input by hardware. The pin can now be used as a
normal I/O pin with no port override from the USART.
24.3.2.4 Data Reception - USART Receiver
When the receiver is enabled, the RxD pin functions as the receiver's serial input. The direction of the pin n must be
set as an input in the Direction register of the Port (PORTx.DIR[n]=0), which is the default pin setting.
24.3.2.4.1 Receiving Frames
The receiver starts data reception when it detects a valid Start bit. Each bit that follows the Start bit will be sampled at
the baud rate or XCK clock, and shifted into the Receive Shift register until the first Stop bit of a frame is received. A
second Stop bit will be ignored by the receiver. When the first Stop bit is received and a complete serial frame is
present in the Receive Shift register, the contents of the Shift register will be moved into the receive buffer. The
receive complete interrupt flag (RXCIF in USARTn.STATUS) is set, and the optional interrupt is generated.
The receiver buffer can be read by reading RXDATA, comprising of DATA[7:0] in USARTn.RXDATAL, and DATA[8] in
USARTn.RXDATAH. RXDATA should not be read unless the Receive Complete Interrupt Flag (RXCIF in
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 280
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
USARTn.STATUS) is set. When using frames with fewer than eight bits, the unused Most Significant bits are read as
zero. If 9-bit characters are used, the ninth bit (DATA[8] in USARTn.RXDATAH) must be read before the low byte
(DATA[7.0] in USARTn.RXDATAL).
24.3.2.4.2 Receiver Error Flags
The USART receiver has three error flags in the Receiver Data Register High Byte register (USARTn.RXDATAH):
• Frame Error (FERR)
• Buffer Overflow (BUFOVF)
• Parity Error (PERR)
The error flags are located in the receive FIFO buffer together with their corresponding frame. Due to the buffering of
the error flags, the USARTn.RXDATAH must be read before the USARTn.RXDATAL, since reading the
USARTn.RXDATAL changes the FIFO buffer.
24.3.2.4.3 Parity Checker
When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result
with the parity bit of the corresponding frame. If a parity error is detected, the Parity Error flag (PERR in
USARTn.RXDATAH) is set.
If USART LIN mode is enabled (by writing RXMODE to '1' in USARTn.CTRLB), a parity check is only performed on
the protected identifier field. A parity error is detected if one of the equations below is not true which sets PERR in
USARTn.RXDATAH.
�0 = ��0 ⊕ ��1 ⊕ ��2 ⊕ ��4
�1 = ¬ ��1 ⊕ ��3 ⊕ ��4 ⊕ ��5
Figure 24-6. Protected Identifier Field and Mapping of Identifier and Parity Bits
Protected identifier field
St
ID0 ID1 ID2 ID3 ID4 ID5 P0
P1
Sp
24.3.2.4.4 Disabling the Receiver
A disabling of the receiver will be immediate. The receiver buffer will be flushed, and data from ongoing receptions
will be lost.
24.3.2.4.5 Flushing the Receive Buffer
If the receive buffer has to be flushed during normal operation, read the DATA location (USARTn.RXDATAH and
USARTn.RXDATAL registers) until the Receive Complete Interrupt Flag (RXCIF in USARTn.RXDATAH) is cleared.
24.3.2.4.6 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception.
The clock recovery unit is used for synchronizing the incoming asynchronous serial frames at the RxD pin to the
internally generated baud rate clock. It samples and low-pass filters each incoming bit, thereby improving the noise
immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the internal
baud rate clock, the rate of the incoming frames, and the frame size in a number of bits.
Asynchronous Clock Recovery
The clock recovery unit synchronizes the internal clock to the incoming serial frames. Figure 24-7 illustrates the
sampling process for the Start bit of an incoming frame:
• In Normal mode, the sample rate is 16 times the baud rate.
• In Double-Speed mode, the sample rate is eight times the baud rate.
• The horizontal arrows illustrate the synchronization variation due to the sampling process. Note that in DoubleSpeed mode, the variation is larger.
• Samples denoted as zero are sampled with the RxD line idle (i.e., when there is no communication activity).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 281
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
Figure 24-7. Start Bit Sampling
RxD
IDLE
START
BIT 0
Sample
(RXMODE = 0x0)
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Sample
(RXMODE = 0x1)
0
1
2
3
4
5
6
7
8
1
2
When the clock recovery logic detects a high-to-low (i.e., idle-to-start) transition on the RxD line, the Start bit
detection sequence is initiated. Sample 1 denotes the first zero-sample, as shown in the figure. The clock recovery
logic then uses three subsequent samples (samples 8, 9, and 10 in Normal mode, samples 4, 5, and 6 in DoubleSpeed mode) to decide if a valid Start bit is received:
• If two or three samples have a low level, the Start bit is accepted. The clock recovery unit is synchronized, and
the data recovery can begin.
• If two or three samples have a high level, the Start bit is rejected as a noise spike, and the receiver looks for the
next high-to-low transition.
The process is repeated for each Start bit.
Asynchronous Data Recovery
The data recovery unit uses sixteen samples in Normal mode and eight samples in Double-Speed mode for each bit.
The following figure shows the sampling process of data and parity bits.
Figure 24-8. Sampling of Data and Parity Bits
RxD
BIT n
Sample
(CLK2X = 0)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample
(CLK2X = 1)
1
2
3
4
5
6
7
8
1
As for Start bit detection, an identical majority voting technique is used on the three center samples for deciding of
the logic level of the received bit. The process is repeated for each bit until a complete frame is received. It includes
the first Stop bit but excludes additional ones. If the sampled Stop bit is a '0' value, the Frame Error (FERR in
USARTn.RXDATAH) flag will be set. The next figure shows the sampling of the Stop bit in relation to the earliest
possible beginning of the next frame's Start bit.
Figure 24-9. Stop Bit and Next Start Bit Sampling
RxD
STOP 1
(A)
(B)
(C)
Sample
(CLK2X = 0)
1
2
3
4
5
6
7
8
9
10
0/1
0/1
0/1
Sample
(CLK2X = 1)
1
2
3
4
5
6
0/1
A new high-to-low transition indicating the Start bit of a new frame can come right after the last of the bits used for
majority voting. For Normal-Speed mode, the first low-level sample can be at the point marked (A) in Stop Bit
Sampling and Next Start Bit Sampling. For Double-Speed mode, the first low level must be delayed to point (B). Point
(C) marks a Stop bit of full length at the nominal baud rate. The early Start bit detection influences the operational
range of the receiver.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 282
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.3.2.4.7 Asynchronous Operational Range
The operational range of the receiver is dependent on the mismatch between the received bit rate and the internally
generated baud rate. If an external transmitter is sending using bit rates that are too fast or too slow, or if the
internally generated baud rate of the receiver does not match the external source’s base frequency, the receiver will
not be able to synchronize the frames to the Start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate.
����� =
16 � + 1
16 � + 1 + 6
����� =
D Sum of character size and parity size (D = 5 to 10 bit).
16 � + 2
16 � + 1 + 8
Rslow Is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate.
Rfast Is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate.
The following tables list the maximum receiver baud rate error that can be tolerated. Normal Speed mode has higher
toleration of baud rate variations.
Table 24-4. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (CLK2X = 0)
D #(Data + Parity Bit)
Rslow [%]
Rfast [%] Maximum Total Error [%]
Receiver Max. Receiver Error [%]
5
93.20
106.67
+6.67/-6.80
±3.0
6
94.12
105.79
+5.79/-5.88
±2.5
7
94.81
105.11
+5.11/-5.19
±2.0
8
95.36
104.58
+4.58/-4.54
±2.0
9
95.81
104.14
+4.14/-4.19
±1.5
10
96.17
103.78
+3.78/-3.83
±1.5
Table 24-5. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (CLK2X = 1)
D #(Data + Parity Bit)
Rslow [%]
Rfast [%] Maximum Total Error [%]
Receiver Max. Receiver Error [%]
5
94.12
105.66
+5.66/-5.88
±2.5
6
94.92
104.92
+4.92/-5.08
±2.0
7
95.52
104.35
+4.35/-4.48
±1.5
8
96.00
103.90
+3.90/-4.00
±1.5
9
96.39
103.53
+3.53/-3.61
±1.5
10
96.70
103.23
+3.23/-3.30
±1.0
The recommendations of the maximum receiver baud rate error were made under the assumption that the receiver
and transmitter equally divide the maximum total error.
24.3.2.5 USART in Master SPI mode
Using the USART in Master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled
to serve as the serial input. The XCK pin will be used as the transfer clock.
As for the USART, a data transfer is initiated by writing to the USARTn.DATA register. This is the case for both
sending and receiving data since the transmitter controls the transfer clock. The data written to USARTn.DATA are
moved from the transmit buffer to the Shift register when the Shift register is ready to send a new frame.
The transmitter and receiver interrupt flags and corresponding USART interrupts used in Master SPI mode are
identical in function to their use in normal USART operation. The receiver error status flags are not in use and are
always read as zero.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 283
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
Disabling of the USART transmitter or receiver in Master SPI mode is identical to their disabling in normal USART
operation.
Related Links
24.5.9 CTRLC
24.3.2.5.1 USART SPI vs. SPI
The USART in Master SPI mode is fully compatible with the stand-alone SPI module in that:
•
•
•
Timing diagrams are the same
UCPHA bit functionality is identical to that of the SPI CPHA bit
UDORD bit functionality is identical to that of the SPI DORD bit
When the USART is set in Master SPI mode, configuration and use are in some cases different from those of the
stand-alone SPI module. In addition, the following difference exists:
•
The USART in Master SPI mode does not include the SPI (Write Collision) feature
The USART in Master SPI mode does not include the SPI Double-Speed mode feature, but this can be achieved by
configuring the Baud Rate Generator accordingly:
•
•
Interrupt timing is not compatible
Pin control differs due to the master-only operation of the USART in SPI Master mode
A comparison of the USART in Master SPI mode and the SPI pins is shown in Table 24-6.
Table 24-6. Comparison of USART in Master SPI Mode and SPI Pins
USART
SPI
Comment
TxD
MOSI
Master out only
RxD
MISO
Master in only
XCK
SCK
Functionally identical
-
SS
Not supported by USART in Master SPI mode
Related Links
24.5.9 CTRLC
24.3.2.6 RS-485 Mode of Operation
The RS-485 feature enables the support of external components to comply with the RS-485 standard.
Either an external line driver is supported as shown in the figure below (RS-485=0x1 in USARTn.CTRLA), or control
of the transmitter driving the TxD pin is provided (RS-485=0x2).
While operating in RS-485 mode, the Transmit Direction pin (XDIR) is driven high when the transmitter is active.
Figure 24-10. RS-485 Bus Connection
VDD
USART
RxD
XDIR
Differential
bus
TxD
The XDIR pin goes high one baud clock cycle in advance of data being shifted out, to allow some guard time to
enable the external line driver. The XDIR pin will remain high for the complete frame including Stop bit(s).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 284
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
Figure 24-11. XDIR Drive Timing
TxD
St
0
1
2
3
4
5
6
7
Sp1
XDIR
Guard
time
Stop
Related Links
24.2.1 Signal Description
24.3.2.7 Start Frame Detection
The start frame detection is supported in UART mode only. The UART start frame detector is limited to Standby
Sleep mode only and can wake-up the system when a Start bit is detected.
When a high-to-low transition is detected on RxDn, the oscillator is powered up and the UART clock is enabled. After
start-up, the rest of the data frame can be received, provided that the baud rate is slow enough in relation to the
oscillator start-up time. Start-up time of the oscillators varies with supply voltage and temperature. For details on
oscillator start-up time characteristics, refer to the Electrical Characteristics.
If a false Start bit is detected and if the system has not been woken-up by another source, the clock will automatically
be turned off and the UART waits for the next transition.
The UART start frame detection works in Asynchronous mode only. It is enabled by writing the Start Frame Detection
bit (SFDEN) in USARTn.CTLB. If the Start bit is detected while the device is in Standby Sleep mode, the UART Start
Interrupt Flag (RXSIF) bit is set.
In Active, Idle, and Power-Down Sleep modes, the asynchronous detection is automatically disabled.
The UART receive complete flag and UART start interrupt flag share the same interrupt line, but each has its
dedicated interrupt settings. Table 21-5 shows the USART start frame detection modes, depending on interrupt
setting.
Table 24-7. USART Start Frame Detection Modes
SFDEN RXSIF Interrupt RXCIF Interrupt Comment
0
x
x
Standard mode.
1
Disabled
Disabled
Only the oscillator is powered during the frame reception. If the
interrupts are disabled and buffer overflow is ignored, all incoming
frames will be lost.
1 (1)
Disabled
Enabled
System/all clocks are awakened on Receive Complete interrupt.
(1)
Enabled
x
System/all clocks are awakened on UART Start Detection.
1
Note:
1. The SLEEP instruction will not shut down the oscillator if there is ongoing communication.
Related Links
32. Electrical Characteristics
24.3.2.8 Break Character Detection and Auto-Baud
When USART receive mode is set to LINAUTO mode (RXMODE in USARTn.CTRLB), it follows the LIN format. All
LIN frames start with a break field followed by a sync field. The USART uses a break detection threshold of greater
than 11 nominal bit times at the configured baud rate. At any time, if more than 11 consecutive dominant bits are
detected on the bus, the USART detects a break field. When a break field has been detected, the USART expects
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 285
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
the sync field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized. If
the received sync character is not 0x55, then the Inconsistent Sync Field Error flag (ISFIF in USARTn.STATUS) is set
and the baud rate is unchanged.
Figure 24-12. LIN Break and Sync Fields
Break Field
Sync Field
Tbit
8 Tbit
After a break field is detected and the Start bit of the sync field is detected, a counter is started. The counter is then
incremented for the next eight Tbit of the sync field. At the end of these 8-bit times, the counter is stopped. At this
moment, the ten Most Significant bits of the counter (value divided by 64) gives the new clock divider and the six
Least Significant bits of this value (the remainder) gives the new fractional part. When the sync field has been
received and all bits are found valid, the clock divider and the fractional part are updated in the Baud Rate Generator
register (USARTn.BAUD). After the break and sync fields, n characters of data can be received.
When the USART receive mode is set to GENAUTO mode, a generic Auto-baud mode is enabled. In this mode there
are no checks of the sync character to equal 0x55. After detection of a break field, the USART expects the next
character to be a sync field, counting eight low and high bit times. If the measured sync field results in a valid BAUD
value (0x0064-0xffff), the BAUD register is updated. Setting the Wait for Break bit (WFB in USARTn.STATUS) before
receiving the next break character, the next negative plus positive edge of RxD line is detected as a break. This
makes it possible to set an arbitrary new baud rate without knowing the current baud rate.
24.3.2.9 One-Wire Mode
In this mode, the TxD output is fed directly into the Receiver Data Register. If the receiver is enabled when
transmitting, it will receive what the transmitter is sending. This can be used to check that no one else is trying to
transmit since received data will not be the same as the transmitted data.
24.3.2.10 Multiprocessor Communication Mode
The Multiprocessor Communication mode (MCPM) effectively reduces the number of incoming frames that have to
be handled by the receiver in a system with multiple microcontrollers communicating via the same serial bus. This
mode is enabled by writing a '1' to the MCPM bit in the Control B register (USARTn.CTRLB). In this mode, a
dedicated bit in the frames is used to indicate whether the frame is an address or data frame type.
If the receiver is set up to receive frames that contain five to eight data bits, the first Stop bit is used to indicate the
frame type. If the receiver is set up for frames with nine data bits, the ninth bit is used to indicate frame type. When
the frame type bit is one, the frame contains an address. When the frame type bit is zero, the frame is a data frame. If
5- to 8-bit character frames are used, the transmitter must be set to use two Stop bits, since the first Stop bit is used
for indicating the frame type.
If a particular slave MCU has been addressed, it will receive the following data frames as usual, while the other slave
MCUs will ignore the frames until another address frame is received.
24.3.2.10.1 Using Multiprocessor Communication Mode
The following procedure should be used to exchange data in Multiprocessor Communication mode (MPCM):
1.
2.
3.
4.
5.
All slave MCUs are in Multiprocessor Communication mode.
The master MCU sends an address frame, and all slaves receive and read this frame.
Each slave MCU determines if it has been selected.
The addressed MCU will disable MPCM and receive all data frames. The other slave MCUs will ignore the
data frames.
When the addressed MCU has received the last data frame, it must enable MPCM again and wait for a new
address frame from the master.
The process then repeats from step 2.
Using any of the 5- to 8-bit character frame formats is impractical, as the receiver must change between using n and
n+1 character frame formats. This makes full-duplex operation difficult since the transmitter and receiver must use
the same character size setting.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 286
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.3.2.11 IRCOM Mode of Operation
®
The IRCOM mode enables IrDA 1.4 compliant modulation and demodulation for baud rates up to 115.2 kbps. When
IRCOM mode is enabled, Double-Speed mode cannot be used for the USART.
24.3.2.11.1 Overview
A USART can be configured in infrared communication mode (IRCOM) that is IrDA compatible for baud rates up to
115.2 kbps. When enabled, the IRCOM mode enables infrared pulse encoding/decoding for the USART.
A USART is set in IRCOM mode by writing 0x2 to the CMODE bits in USARTn.CTRLC.. The data on the TX/RX pins
are the inverted value of the transmitted/received infrared pulse. It is also possible to select an event channel from
the Event System as an input for the IRCOM receiver. This will disable the RX input from the USART pin.
For transmission, three pulse modulation schemes are available:
•
•
•
3/16 of the baud rate period
Fixed programmable pulse time based on the peripheral clock frequency
Pulse modulation disabled
For the reception, a fixed programmable minimum high-level pulse width for the pulse to be decoded as a logical '0' is
used. Shorter pulses will then be discarded, and the bit will be decoded to logical '1' as if no pulse was received.
24.3.2.11.2 Block Diagram
Figure 24-13. Block Diagram
IRCOM
Event System
Events
Encoded RXD
Pulse
Decoding
Decoded RXD
USART
Pulse
Encoding
RXD
TXD
Decoded RXD
Encoded RXD
24.3.2.11.3 IRCOM and Event System
The Event System can be used as the receiver input. This enables the IRCOM or USART input from the I/O pins or
sources other than the corresponding RX pin. If the Event System input is enabled, input from the USART's RX pin is
automatically disabled.
Related Links
15. Event System (EVSYS)
24.3.3
Events
The USART can accept the following input events:
•
IREI - IrDA Event Input
The event is enabled by writing a '1' to the IrDA Event Input bit (IREI) in the Event Control register (USART.EVCTRL).
Related Links
15. Event System (EVSYS)
24.5.12 EVCTRL
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 287
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.3.4
Interrupts
Table 24-8. Available Interrupt Vectors and Sources
Offset Name Vector Description
Conditions
0x00
RXC
Receive Complete
Interrupt
•
•
•
There are unread data in the receive buffer (RXCIE)
Receive of Start-of-Frame detected (RXSIE)
Auto-Baud Error/ISFIF flag set (ABEIE)
0x02
DRE
Data Register Empty
Interrupt
The transmit buffer is empty/ready to receive new data (DREIE).
0x04
TXC
Transmit Complete
Interrupt
The entire frame in the Transmit Shift register has been shifted out and
there are no new data in the transmit buffer (TXCIE).
When an interrupt condition occurs, the corresponding interrupt flag is set in the STATUS register (USART.STATUS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the Control A register
(USART.CTRLA).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the USART.STATUS register for details on how
to clear interrupt flags.
Related Links
14. CPU Interrupt Controller (CPUINT)
24.5.5 STATUS
24.5.6 CTRLA
24.3.5
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 288
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.4
Register Summary - USART
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x07
RXDATAL
RXDATAH
TXDATAL
TXDATAH
STATUS
CTRLA
CTRLB
CTRLC
CTRLC
0x08
BAUD
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
0x0A
0x0B
0x0C
0x0D
0x0E
Reserved
DBGCTRL
EVCTRL
TXPLCTRL
RXPLCTRL
24.5
DATA[7:0]
RXCIF
BUFOVF
FERR
PERR
DATA[8]
DATA[7:0]
RXCIF
TXCIF
RXCIE
TXCIE
RXEN
TXEN
CMODE[1:0]
CMODE[1:0]
7:0
7:0
7:0
7:0
DREIF
DREIE
RXSIF
RXSIE
SFDEN
PMODE[1:0]
ISFIF
LBME
ODME
SBMODE
DATA[8]
BDF
WFB
ABEIE
RS-485[1:0]
RXMODE[1:0]
MPCM
CHSIZE[2:0]
UDORD
UCPHA
BAUD[7:0]
BAUD[15:8]
DBGRUN
IREI
TXPL[7:0]
RXPL[6:0]
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 289
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.1
Receiver Data Register Low Byte
Name:
Offset:
Reset:
Property:
RXDATAL
0x00
0x00
R
Reading the USARTn.RXDATAL Register will return the contents of the Receive Data Buffer register (RXB).
The receive buffer consists of a two-level FIFO. The FIFO and the corresponding flags in the high byte of RXDATA
will change state whenever the receive buffer is accessed (read). If CHSIZE in USARTn.CTRLC is set to 9BIT Low
byte first, read USARTn.RXDATAL before USARTn.RXDATAH. Otherwise, always read USARTn.RXDATAH before
USARTn.RXDATAL in order to get the correct flags.
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
DATA[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – DATA[7:0] Receiver Data Register
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 290
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.2
Receiver Data Register High Byte
Name:
Offset:
Reset:
Property:
RXDATAH
0x01
0x00
-
Reading the USARTn.RXDATAH register location will return the contents of the ninth DATA bit plus Status bits.
The receive buffer consists of a two-level FIFO. The FIFO and the corresponding flags in the high byte of
USARTn.RXDATAH will change state whenever the receive buffer is accessed (read). If CHSIZE in USARTn.CTRLC
is set to 9BIT Low byte first, read USARTn.RXDATAL before USARTn.RXDATAH. Otherwise, always read
USARTn.RXDATAH before USARTn.RXDATAL in order to get the correct flags.
Bit
Access
Reset
7
RXCIF
R
0
6
BUFOVF
R
0
5
4
3
2
FERR
R
0
1
PERR
R
0
0
DATA[8]
R
0
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty (i.e.,
does not contain any unread data). When the receiver is disabled, the receive buffer will be flushed and
consequently, the RXCIF will become zero.
Bit 6 – BUFOVF Buffer Overflow
The BUFOVF flag indicates data loss due to a receiver buffer full condition. This flag is set if a Buffer Overflow
condition is detected. A Buffer Overflow occurs when the receive buffer is full (two characters), it is a new character
waiting in the Receive Shift register, and a new Start bit is detected. This flag is valid until the receive buffer
(USARTn.RXDATAL) is read.
This flag is not used in Master SPI mode of operation.
Bit 2 – FERR Frame Error
The FERR flag indicates the state of the first Stop bit of the next readable frame stored in the receive buffer. The bit is
set if the received character had a Frame Error (i.e., when the first Stop bit was zero and cleared when the Stop bit of
the received data is '1'. This bit is valid until the receive buffer (USARTn.RXDATAL) is read. The FERR is not affected
by the SBMODE bit in USARTn.CTRLC since the receiver ignores all, except for the first Stop bit.
This flag is not used in Master SPI mode of operation.
Bit 1 – PERR Parity Error
If parity checking is enabled and the next character in the receive buffer has a Parity Error this flag is set. If Parity
Check is not enabled the PERR will always be read as zero. This bit is valid until the receive buffer
(USARTn.RXDATAL) is read. For details on parity calculation refer to 24.3.2.2.1 Parity . If USART is set to LINAUTO
mode, this bit will be a Parity Check of the protected identifier field and will be valid when DATA[8] in
USARTn.RXDATAH reads low.
This flag is not used in Master SPI mode of operation.
Bit 0 – DATA[8] Receiver Data Register
When USART receiver is set to LINAUTO mode, this bit indicates if the received data is within the response space of
a LIN frame. If the received data is the protected identifier field, this bit will be read as zero. Otherwise, the bit will be
read as one. For Receiver mode other than LINAUTO mode, DATA[8] holds the ninth data bit in the received
character when operating with serial frames with nine data bits.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 291
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.3
Transmit Data Register Low Byte
Name:
Offset:
Reset:
Property:
TXDATAL
0x02
0x00
R/W
The Transmit Data Buffer (TXB) register will be the destination for data written to the USARTn.TXDATAL register
location.
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver.
The transmit buffer can only be written when the DREIF flag in the USARTn.STATUS register is set. Data written to
DATA when the DREIF flag is not set will be ignored by the USART transmitter. When data is written to the transmit
buffer, and the transmitter is enabled, the transmitter will load the data into the Transmit Shift register when the Shift
register is empty. The data is then transmitted on the TxD pin.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Transmit Data Register
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 292
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.4
Transmit Data Register High Byte
Name:
Offset:
Reset:
Property:
TXDATAH
0x03
0x00
-
USARTn.TXDATAH holds the ninth data bit in the character to be transmitted when operating with serial frames with
nine data bits. When used this bit must be written before writing to USARTn.TXDATAL except if CHSIZE in
USARTn.CTRLC is set to 9BIT Low byte first where USARTn.TXDATAL should be written first.
This bit is unused in Master SPI mode of operation.
Bit
7
6
5
4
3
Access
Reset
2
1
0
DATA[8]
W
0
Bit 0 – DATA[8] Transmit Data Register
This bit is used when CHSIZE=9BIT in USARTn.CTRLC.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 293
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.5
USART Status Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIF
R
0
STATUS
0x04
0x00
-
6
TXCIF
R/W
0
5
DREIF
R
0
4
RXSIF
R/W
0
3
ISFIF
R/W
0
2
1
BDF
R/W
0
0
WFB
R/W
0
Bit 7 – RXCIF USART Receive Complete Interrupt Flag
This flag is set to '1' when there is unread data in the receive buffer and cleared when the receive buffer is empty
(i.e., does not contain any unread data). When the receiver is disabled, the receive buffer will be flushed and
consequently, the RXCIF will become zero.
When interrupt-driven data reception is used, the receive complete interrupt routine must read the received data from
RXDATA in order to clear the RXCIF. If not, a new interrupt will occur directly after the return from the current
interrupt.
Bit 6 – TXCIF USART Transmit Complete Interrupt Flag
This flag is set when the entire frame in the Transmit Shift register has been shifted out and there are no new data in
the transmit buffer (TXDATA).
This flag is automatically cleared when the transmit complete interrupt vector is executed. The flag can also be
cleared by writing a '1' to its bit location.
Bit 5 – DREIF USART Data Register Empty Flag
The DREIF indicates if the transmit buffer (TXDATA) is ready to receive new data. The flag is set to '1' when the
transmit buffer is empty and is '0' when the transmit buffer contains data to be transmitted that has not yet been
moved into the Shift register. DREIF is set after a Reset to indicate that the transmitter is ready. Always write this bit
to '0' when writing the STATUS register.
DREIF is cleared to '0' by writing TXDATAL. When interrupt-driven data transmission is used, the Data Register
Empty interrupt routine must either write new data to TXDATA in order to clear DREIF or disable the Data Register
Empty interrupt. If not, a new interrupt will occur directly after the return from the current interrupt.
Bit 4 – RXSIF USART Receive Start Interrupt Flag
The RXSIF flag indicates a valid Start condition on RxD line. The flag is set when the system is in standby modes
and a high (IDLE) to low (START) valid transition is detected on the RxD line. If the start detection is not enabled, the
RXSIF will always be read as zero. This flag can only be cleared by writing a '1' to its bit location. This flag is not used
in the Master SPI mode operation.
Bit 3 – ISFIF Inconsistent Sync Field Interrupt Flag
This bit is set when the auto-baud is enabled and the sync field bit time are too fast or too slow to give a valid baud
setting. It will also be set when USART is set to LINAUTO mode and the SYNC character differ from data value 0x55.
Writing a '1' to this bit will clear the flag and bring the USART back to Idle state.
Bit 1 – BDF Break Detected Flag
This bit is intended for USART configured to LINAUTO receive mode. The break detector has a fixed threshold of 11
bits low for a Break to be detected. The BDF bit is set after a valid BREAK and SYNC character is detected. The bit is
automatically cleared when next data is received. The bit will behave identically when USART is set to GENAUTO
mode. In NORMAL or CLK2X receive mode, the BDF bit is unused.
This bit is cleared by writing a '1' to it.
Bit 0 – WFB Wait For Break
Writing this bit to '1' will register the next low and high transition on RxD line as a Break character. This can be used
to wait for a Break character of arbitrary width. Combined with USART set to GENAUTO mode, this allows the user to
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 294
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
set any BAUD rate through BREAK and SYNC as long as it falls within the valid range of the USARTn.BAUD register.
This bit will always read '0'.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 295
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.6
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIE
R/W
0
CTRLA
0x05
0x00
-
6
TXCIE
R/W
0
5
DREIE
R/W
0
4
RXSIE
R/W
0
3
LBME
R/W
0
2
ABEIE
R/W
0
1
0
RS-485[1:0]
R/W
0
R/W
0
Bit 7 – RXCIE Receive Complete Interrupt Enable
The bit enables the Receive Complete Interrupt (interrupt vector RXC). The enabled interrupt will be triggered when
RXCIF in the USARTn.STATUS register is set.
Bit 6 – TXCIE Transmit Complete Interrupt Enable
This bit enables the Transmit Complete Interrupt (interrupt vector TXC). The enabled interrupt will be triggered when
the TXCIF in the USARTn.STATUS register is set.
Bit 5 – DREIE Data Register Empty Interrupt Enable
This bit enables the Data Register Empty Interrupt (interrupt vector DRE). The enabled interrupt will be triggered
when the DREIF in the USART.STATUS register is set.
Bit 4 – RXSIE Receiver Start Frame Interrupt Enable
Writing a '1' to this bit enables the Start Frame Detector to generate an interrupt on interrupt vector RXC when a
start-of-frame condition is detected.
Bit 3 – LBME Loop-back Mode Enable
Writing this bit to '1' enables an internal connection between the TxD and RxD pin.
Bit 2 – ABEIE Auto-baud Error Interrupt Enable
Writing this bit to '1' enables the auto-baud error interrupt on interrupt vector RXC. The enabled interrupt will trigger
for conditions where the ISFIF flag is set.
Bits 1:0 – RS-485[1:0] RS-485 Mode
These bits enable the RS-485 and select the operation mode.
Value
Name Description
0x0
OFF Disabled.
0x1
EXT Enables RS-485 mode with control of an external line driver through a dedicated Transmit
Enable (TE) pin.
0x2
INT
Enables RS-485 mode with control of the internal USART transmitter.
0x3
Reserved.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 296
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.7
Control B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXEN
R/W
0
CTRLB
0x06
0x00
-
6
TXEN
R/W
0
5
4
SFDEN
R/W
0
3
ODME
R/W
0
2
1
RXMODE[1:0]
R/W
R/W
0
0
0
MPCM
R/W
0
Bit 7 – RXEN Receiver Enable
Writing this bit to ‘1’ enables the USART receiver. The receiver will override normal port operation for the RxD pin
when enabled. Disabling the receiver will flush the receive buffer invalidating the FERR, BUFOVF, and PERR flags.
In GENAUTO and LINAUTO mode, disabling the receiver will reset the auto-baud detection logic.
Bit 6 – TXEN Transmitter Enable
Writing this bit to ‘1’ enables the USART transmitter. The transmitter will override normal port operation for the TxD
pin when enabled. Disabling the transmitter (writing TXEN to '0') will not become effective until ongoing and pending
transmissions are completed (i.e. when the Transmit Shift register and Transmit Buffer register does not contain data
to be transmitted). When the transmitter is disabled, it will no longer override the TxDn pin, and the pin direction is set
as input automatically by hardware, even if it was configured as output by the user.
Bit 4 – SFDEN Start Frame Detection Enable
Writing this bit to ‘1’ enables the USART Start Frame Detection mode. The Start Frame detector is able to wake up
the system from Idle or Standby Sleep modes when a high (IDLE) to low (START) transition is detected on the RxD
line.
Bit 3 – ODME Open Drain Mode Enable
Writing this bit to ‘1’ makes the TxD pin to have open-drain functionality. A pull-up resistor is needed to prevent the
line from floating when a logic '1' is output to the TxD pin.
Bits 2:1 – RXMODE[1:0] Receiver Mode
In CLK2X mode, the divisor of the baud rate divider will be reduced from 16 to 8 effectively doubling the transfer rate
for asynchronous communication modes. For synchronous operation, the CLK2X mode has no effect and RXMODE
should always be written to '0'. RXMODE must be '0' when the USART Communication mode is configured to
IRCOM. Setting RXMODE to GENAUTO enables generic auto-baud where the SYNC character is valid when eight
low and high bits have been registered. In this mode, any SYNC character that gives a valid BAUD rate will be
accepted. In LINAUTO mode the SYNC character is constrained and found valid if every two bits falls within 16 ±3
baud samples of the internal baud rate and match data value 0x55. The GENAUTO and LINAUTO mode is only
supported for USART operated in Asynchronous Slave mode.
Value
Name
Description
0x0
NORMAL
Normal USART mode, Standard Transmission Speed
0x1
CLK2X
Normal USART mode, Double Transmission Speed
0x2
GENAUTO
Generic Auto-baud mode
0x3
LINAUTO
LIN Constrained Auto-baud mode
Bit 0 – MPCM Multi-Processor Communication Mode
Writing a ‘1’ to this bit enables the Multi-Processor Communication mode: the USART receiver ignores all the
incoming frames that do not contain address information. The transmitter is unaffected by the MPCM setting. For
more detailed information see 24.3.2.10 Multiprocessor Communication Mode.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 297
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.8
Control C - Async Mode
Name:
Offset:
Reset:
Property:
CTRLC
0x07
0x03
-
This register description is valid for all modes except Master SPI mode. When the USART Communication mode bits
(CMODE) in this register are written to 'MSPI', see Control C - Master SPI Mode for the correct description.
Bit
Access
Reset
7
6
CMODE[1:0]
R/W
R/W
0
0
5
4
PMODE[1:0]
R/W
R/W
0
0
3
SBMODE
R/W
0
2
R/W
0
1
CHSIZE[2:0]
R/W
1
0
R/W
1
Bits 7:6 – CMODE[1:0] USART Communication Mode
Writing these bits select the Communication mode of the USART.
Writing a 0x3 to these bits alters the available bit fields in this register, see Control C - Master SPI Mode.
Value
Name
Description
0x0
ASYNCHRONOUS
Asynchronous USART
0x1
SYNCHRONOUS
Synchronous USART
0x2
IRCOM
Infrared Communication
0x3
MSPI
Master SPI
Bits 5:4 – PMODE[1:0] Parity Mode
Writing these bits enable and select the type of parity generation.
When enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each
frame. The receiver will generate a parity value for the incoming data, compare it to the PMODE setting, and set the
Parity Error flag (PERR) in the STATUS register (USARTn.STATUS) if a mismatch is detected.
Value
Name
Description
0x0
DISABLED
Disabled
0x1
Reserved
0x2
EVEN
Enabled, Even Parity
0x3
ODD
Enabled, Odd Parity
Bit 3 – SBMODE Stop Bit Mode
Writing this bit selects the number of Stop bits to be inserted by the transmitter.
The receiver ignores this setting.
Value
Description
0
1 Stop bit
1
2 Stop bits
Bits 2:0 – CHSIZE[2:0] Character Size
Writing these bits select the number of data bits in a frame. The receiver and transmitter use the same setting. For
9BIT character size, the order of which byte to read or write first, low or high byte of RXDATA or TXDATA is
selectable.
Value
Name
Description
0x0
5BIT
5-bit
0x1
6BIT
6-bit
0x2
7BIT
7-bit
0x3
8BIT
8-bit
0x4
Reserved
0x5
Reserved
0x6
9BITL
9-bit (Low byte first)
0x7
9BITH
9-bit (High byte first)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 298
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.9
Control C - Master SPI Mode
Name:
Offset:
Reset:
Property:
CTRLC
0x07
0x00
-
This register description is valid only when the USART is in Master SPI mode (CMODE written to MSPI). For other
CMODE values, see Control C - Async Mode.
See 24.3.2.5 USART in Master SPI mode for a full description of the Master SPI mode operation.
Bit
Access
Reset
7
6
CMODE[1:0]
R/W
R/W
0
0
5
4
3
2
UDORD
R/W
0
1
UCPHA
R/W
0
0
Bits 7:6 – CMODE[1:0] USART Communication Mode
Writing these bits select the communication mode of the USART.
Writing a value different than 0x3 to these bits alters the available bit fields in this register, see Control C - Async
Mode.
Value
Name
Description
0x0
ASYNCHRONOUS
Asynchronous USART
0x1
SYNCHRONOUS
Synchronous USART
0x2
IRCOM
Infrared Communication
0x3
MSPI
Master SPI
Bit 2 – UDORD Data Order
Writing this bit selects the frame format.
The receiver and transmitter use the same setting. Changing the setting of UDORD will corrupt all ongoing
communication for both the receiver and the transmitter.
Value
Description
0
MSB of the data word is transmitted first
1
LSB of the data word is transmitted first
Bit 1 – UCPHA Clock Phase
The UCPHA bit setting determines if data is sampled on the leading (first) edge or tailing (last) edge of XCKn. Refer
to the 24.3.2.1.5 Master SPI Mode Clock Generation for details.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 299
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.10 Baud Register
Name:
Offset:
Reset:
Property:
BAUD
0x08
0x00
-
The USARTn.BAUDL and USARTn.BAUDH register pair represents the 16-bit value, USARTn.BAUD. The low byte
[7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Ongoing transmissions of the transmitter and receiver will be corrupted if the baud rate is changed. Writing this
register will trigger an immediate update of the baud rate prescaler. For more information on how to set the baud rate,
see Table 24-2.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – BAUD[15:8] USART Baud Rate High Byte
These bits hold the MSB of the 16-bit Baud register.
Bits 7:0 – BAUD[7:0] USART Baud Rate Low Byte
These bits hold the LSB of the 16-bit Baud register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 300
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.11 Debug Control Register
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0B
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 301
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.12 IrDA Control Register
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x0C
0x00
-
6
5
4
3
Access
Reset
2
1
0
IREI
R/W
0
Bit 0 – IREI IrDA Event Input Enable
This bit enables the event source for the IRCOM Receiver. If event input is selected for the IRCOM Receiver, the
input from the USART’s RX pin is automatically disabled.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 302
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.13 IRCOM Transmitter Pulse Length Control Register
Name:
Offset:
Reset:
Property:
Bit
7
TXPLCTRL
0x0D
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TXPL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TXPL[7:0] Transmitter Pulse Length
The 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will have effect only if
IRCOM mode is selected by a USART. By leaving this register value to zero, 3/16 of the baud rate period pulse
modulation is used. Setting this value from 1 to 254 will give a fixed pulse length coding. The 8-bit value sets the
number of system clock periods for the pulse. The start of the pulse will be synchronized with the rising edge of the
baud rate clock. Setting the value to 255 (0xFF) will disable pulse coding, letting the RX and TX signals pass through
the IRCOM module unaltered. This enables other features through the IRCOM module, such as half duplex USART,
Loop-back testing, and USART RX input from an event channel.
TXPL must be configured before the USART transmitter is enabled (TXEN).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 303
ATtiny202/204/402/404/406 Automotiv...
Universal Synchronous and Asynchronous Recei...
24.5.14 IRCOM Receiver Pulse Length Control Register
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXPLCTRL
0x0E
0x00
-
6
5
4
R/W
0
R/W
0
R/W
0
3
RXPL[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 6:0 – RXPL[6:0] Receiver Pulse Length
The 8-bit value sets the filter coefficient for the IRCOM transceiver. Setting this register will only have effect if IRCOM
mode is selected by a USART.
By leaving this register value to zero, filtering is disabled. Setting this value between 0x01 and 0xFF will enable
filtering, where x+1 equal samples are required for the pulse to be accepted.
RXPL must be configured before USART receiver is enabled (RXEN).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 304
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.
Serial Peripheral Interface (SPI)
25.1
Features
•
•
•
•
•
•
•
•
25.2
Full-Duplex, Three-Wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double-Speed (CK/2) Master SPI Mode
Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows full-duplex communication between an AVR device and peripheral devices or between several
microcontrollers. The SPI peripheral can be configured as either master or slave. The master initiates and controls all
data transactions.
The interconnection between master and slave devices with SPI is shown in the block diagram. The system consists
of two shift registers and a master clock generator. The SPI master initiates the communication cycle by pulling the
desired slave's slave select (SS) signal low. Master and slave prepare the data to be sent to their respective Shift
registers, and the master generates the required clock pulses on the SCK line to exchange data. Data is always
shifted from master to slave on the master output, slave input (MOSI) line, and from slave to master on the master
input, slave output (MISO) line.
This device provides one instance of the SPI peripheral, SPI0.
Related Links
25.2.1 Block Diagram
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 305
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.2.1
Block Diagram
Figure 25-1. SPI Block Diagram
MASTER
SLAVE
Transmit Data Register
(DATA)
Transmit Data Register
(DATA)
Transmit Buffer
Register
Transmit Buffer
Register
LSb
MSb
MISO
MISO
MOSI
MOSI
SCK
SCK
SS
SS
8-bit Shift Register
MSb
LSb
8-bit Shift Register
SPI CLOCK
GENERATOR
First Receive Buffer
Register
First Receive Buffer
Register
Receive Buffer
Register
Second Receive Buffer
Register
Receive Data Register
(DATA)
Receive Data Register
(DATA)
The SPI is built around an 8-bit Shift register that will shift data out and in at the same time. The Transmit Data
register and the Receive Data register are not physical registers but are mapped to other registers when written or
read: Writing the Transmit Data register (SPIn.DATA) will write the Shift register in Normal mode and the Transmit
Buffer register in Buffer mode. Reading the Receive Data register (SPIn.DATA) will read the First Receive Buffer
register in normal mode and the Second Receive Data register in Buffer mode.
In Master mode the SPI has a clock generator to generate the SCK clock. In Slave mode the received SCK clock is
synchronized and sampled to trigger the shifting of data in the Shift register.
25.2.2
Signal Description
Table 25-1. Signals in Master and Slave Mode
Signal
Description
Pin Configuration
Master Mode
Slave Mode
MOSI
Master Out Slave In
User defined
Input
MISO
Master In Slave Out
Input
User defined
SCK
Slave clock
User defined
Input
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 306
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
...........continued
Signal
SS
Description
Slave select
Pin Configuration
Master Mode
Slave Mode
User defined
Input
When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 25-1.
The data direction of the pins with "User defined" pin configuration is not controlled by the SPI: The data direction is
controlled by the application software configuring the port peripheral. If these pins are configured with data direction
as input, they can be used as regular I/O pin inputs. If these pins are configured with data direction as output, their
output value is controlled by the SPI. The MISO pin has a special behavior: When the SPI is in Slave mode and the
MISO pin is configured as an output, the SS pin controls the output buffer of the pin: If SS is low, the output buffer
drives the pin, if SS is high, the pin is tri-stated.
The data direction of the pins with "Input" pin configuration is controlled by the SPI hardware.
Related Links
5. I/O Multiplexing and Considerations
25.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 25-2. SPI System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
25.2.3.2 I/O Lines and Connections
25.2.3.5 Debug Operation
25.2.3.3 Interrupts
25.2.3.1 Clocks
25.2.3.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
11. Clock Controller (CLKCTRL)
25.2.3.2 I/O Lines and Connections
The SPI signals (MOSI, MISO, SCK, SS) are either inputs or outputs, depending on whether the SPI is in Master or
Slave mode, as described in the Signal Description.
Using the I/O lines requires configuration of the I/O pins as described in the Signal Description.
Related Links
5. I/O Multiplexing and Considerations
17. I/O Pin Configuration (PORT)
25.2.2 Signal Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 307
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
25.3.3 Interrupts
25.2.3.4 Events
Not applicable.
25.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
Related Links
31. Unified Program and Debug Interface (UPDI)
25.3
Functional Description
25.3.1
Initialization
Initialize the SPI to a basic functional state by following these steps:
1. Configure the SS pin in the port peripheral.
2. Select SPI Master/Slave operation by writing the Master/Slave Select bit (MASTER) in the Control A register
(SPIn.CTRLA).
3. In Master mode, select the clock speed by writing the Prescaler bits (PRESC) and the Clock Double bit
(CLK2X) in SPIn.CTRLA.
4. Optional: Select the Data Transfer mode by writing to the MODE bits in the Control B register (SPIn.CTRLB).
5. Optional: Write the Data Order bit (DORD) in SPIn.CTRLA.
6. Optional: Setup Buffer mode by writing BUFEN and BUFWR bits in the Control B register (SPIn.CTRLB).
7. Optional: To disable the multimaster support in Master mode, write '1' to the Slave Select Disable bit (SSD) in
SPIn.CTRLB.
8. Enable the SPI by writing a '1' to the ENABLE bit in SPIn.CTRLA.
Related Links
5. I/O Multiplexing and Considerations
17. I/O Pin Configuration (PORT)
25.2.2 Signal Description
25.3.2
Operation
25.3.2.1 Master Mode Operation
When the SPI is configured in Master mode, a write to the SPIn.DATA register will start a new transfer. The SPI clock
generator starts and the hardware shifts the eight bits into the selected slave. After the byte is shifted out the interrupt
flag is set (IF flag in SPIn.INTFLAGS). The SPI master can operate in two modes, Normal and Buffered, as explained
below.
25.3.2.1.1 SS Pin Functionality in Master Mode - Multi-Master Support
In Master mode, the Slave Select Disable bit in Control Register B (SSD bit in SPIn.CTRLB) controls how the SPI
uses the SS pin.
•
If SSD in SPIn.CTRLB is ‘0’, the SPI can use the SS pin to transition from Master to Slave mode. This allows
multiple SPI masters on the same SPI bus.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 308
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
•
•
If SSD in SPIn.CTRLB is ‘0’, and the SS pin is configured as an output pin, it can be used as a regular I/O pin or
by other peripheral modules, and will not affect the SPI system.
If SSD in SPIn.CTRLB is ‘1’, the SPI does not use the SS pin, and it can be used as a regular I/O pin, or by
other peripheral modules.
If the SSD bit in SPIn.CTRLB is ‘0’, and the SS is configured as an input pin, the SS pin must be held high to ensure
master SPI operation. A low level will be interpreted as another master is trying to take control of the bus. This will
switch the SPI into Slave mode, and the hardware of the SPI will perform the following actions:
1. The Master bit in the SPI Control A Register (MASTER in SPIn.CTRLA) is cleared, and the SPI system
becomes a slave. The direction of the SPI pins will be switched when conditions in Table 25-3 are met.
2. The Interrupt Flag in the Interrupt Flags register (IF in SPIn.INTFLAGS) will be set. If the interrupt is enabled
and the global interrupts are enabled, the interrupt routine will be executed.
Table 25-3. Overview of the SS Pin Functionality when the SSD Bit in SPIn.CTRLB is ‘0’
SS Configuration
Input
Output
SS Pin-Level
Description
High
Master activated (selected)
Low
Master deactivated, switched to
Slave mode
High
Master activated (selected)
Low
Note: If the device is in Master mode and it cannot be ensured that the SS pin will stay high between two
transmissions, the status of the Master bit (the MASTER bit in SPIn.CTRLA) has to be checked before a new byte is
written. After the Master bit has been cleared by a low level on the SS line, it must be set by the application to reenable the SPI Master mode.
25.3.2.1.2 Normal Mode
In Normal mode, the system is single buffered in the transmit direction and double buffered in the receive direction.
This influences the data handling in the following ways:
1. New bytes to be sent cannot be written to the Data register (SPIn.DATA) before the entire transfer has
completed. A premature write will cause corruption of the transmitted data, and the hardware will set the Write
Collision Flag (WRCOL flag in SPIn.INTFLAGS).
2. Received bytes are written to First Receive Buffer register immediately after the transmission is completed.
3. The First Receive Buffer register has to be read before the next transmission is completed or data will be lost.
This register is read by reading SPIn.DATA.
4. The Transmit Buffer register and Second Receive Buffer register are not used in Normal mode.
After a transfer has completed, the Interrupt Flag will be set in the Interrupt Flags register (IF flag in SPI.INTFLAGS).
This will cause the corresponding interrupt to be executed if this interrupt and the global interrupts are enabled.
Setting the Interrupt Enable (IE) bit in the Interrupt Control register (SPIn.INTCTRL) will enable the interrupt.
25.3.2.1.3 Buffer Mode
The Buffer mode is enabled by setting the BUFEN bit in SPIn.CTRLB. The BUFWR bit in SPIn.CTRLB has no effect
in Master mode. In Buffer mode the system is double buffered in the transmit direction and triple buffered in the
receive direction. This influences the data handling the following ways:
1. New bytes to be sent can be written to the Data register (SPIn.DATA) as long as the Data Register Empty
Interrupt Flag (DREIF) in the Interrupt Flag Register (SPIn.INTFLAGS) is set. The first write will be transmitted
right away and a following write will go to the Transmit Buffer register.
2. A received byte is placed in a two-entry RX FIFO comprised of the First and Second Receive Buffer registers
immediately after the transmission is completed.
3. The Data register is used to read from the RX FIFO. The RX FIFO must be read at least every second transfer
to avoid any loss of data.
If both the Shift register and the Transmit Buffer register becomes empty, the Transfer Complete Interrupt Flag
(TXCIF) in the Interrupt Flags register (SPIn.INTFLAGS) will be set. This will cause the corresponding interrupt to be
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 309
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
executed if this interrupt and the global interrupts are enabled. Setting the Transfer Complete Interrupt Enable
(TXCIE) in the Interrupt Control register (SPIn.INTCTRL) enables the Transfer Complete Interrupt.
25.3.2.2 Slave Mode
In Slave mode, the SPI peripheral receives SPI clock and Slave Select from a Master. Slave mode supports three
operational modes: One unbuffered mode and two buffered modes. In Slave mode, the control logic will sample the
incoming signal on the SCK pin. To ensure correct sampling of this clock signal, the minimum low and high periods
must each be longer than two peripheral clock cycles.
25.3.2.2.1 SS Pin Functionality in Slave Mode
The Slave Select (SS) pin plays a central role in the operation of the SPI. Depending on the mode the SPI is in and
the configuration of this pin, it can be used to activate or deactivate devices. The SS pin is used as a Chip Select pin.
In Slave mode, SS, MOSI, and SCK are always inputs. The behavior of the MISO pin depends on the configured data
direction of the pin in the port peripheral and the value of SS: When SS is driven low, the SPI is activated and will
respond to received SCK pulses by clocking data out on MISO if the user has configured the data direction of the
MISO pin as an output. When SS is driven high the SPI is deactivated, meaning that it will not receive incoming data.
If the MISO pin data direction is configured as an output, the MISO pin will be tristated. The following table shows an
overview of the SS pin functionality.
Table 25-4. Overview of the SS Pin Functionality
SS Configuration
Always Input
SS Pin-Level
Description
MISO Pin Mode
Port Direction =
Output
Port Direction =
Input
High
Slave deactivated
(deselected)
Tri-stated
Input
Low
Slave activated
(selected)
Output
Input
Note:
In Slave mode, the SPI state machine will be reset when the SS pin is brought high. If the SS is brought high during a
transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be
considered as lost. As the SS pin is used to signal the start and end of a transfer, it is useful for achieving packet/byte
synchronization, and keeping the Slave bit counter synchronized with the master clock generator.
25.3.2.2.2 Normal Mode
In Normal mode, the SPI peripheral will remain idle as long as the SS pin is driven high. In this state, the software
may update the contents of the SPIn.DATA register, but the data will not be shifted out by incoming clock pulses on
the SCK pin until the SS pin is driven low. If SS is driven low, the slave will start to shift out data on the first SCK clock
pulse. When one byte has been completely shifted, the SPI Interrupt flag (IF) in SPIn.INTFLAGS is set.
The user application may continue placing new data to be sent into the SPIn.DATA register before reading the
incoming data. New bytes to be sent cannot be written to SPIn.DATA before the entire transfer has completed. A
premature write will be ignored, and the hardware will set the Write Collision Flag (WRCOL in SPIn.INTFLAGS).
When SS is driven high, the SPI logic is halted, and the SPI slave will not receive any new data. Any partially
received packet in the shift register will be lost.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 310
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
Figure 25-2. SPI Timing Diagram in Normal Mode (Buffer Mode Not Enabled)
SS
SCK
Write DATA
Write value
0x43
0x46
0x45
0x44
WRCOL
IF
Shift Register
0x43
Data sent
0x46
0x44
0x43
0x44
0x46
The figure shows three transfers and one write to the DATA register while the SPI is busy with a transfer. This write
will be ignored and the Write Collision Flag (WRCOL in SPIn.INTFLAGS) is set.
25.3.2.2.3 Buffer Mode
To avoid data collisions, the SPI peripheral can be configured in buffered mode by writing a '1' to the Buffer Mode
Enable bit in the Control B register (BUFEN in SPIn.CTRLB). In this mode, the SPI has additional interrupt flags and
extra buffers. The extra buffers are shown in Figure 25-1. There are two different modes for the Buffer mode,
selected with the Buffer mode Wait for Receive bit (BUFWR). The two different modes are described below with
timing diagrams.
Figure 25-3. SPI Timing Diagram in Buffer Mode with BUFWR in SPIn.CTRLB Set to Zero
SS
SCK
Write DATA
Write value
0x43
0x44
0x45
0x46
DREIF
TXCIF
RXCIF
Transmit Buffer
Shift Register
Data sent
0x43
Dummy
Dummy
0x46
0x44
0x44
0x43
0x43
0x44
0x46
0x46
All writes to the Data register goes to the Transmit Buffer register. The figure above shows that the value 0x43 is
written to the Data register, but it is not immediately transferred to the shift register so the first byte sent will be a
dummy byte. The value of the dummy byte is whatever was in the shift register at the time, usually the last received
byte. After the first dummy transfer is completed the value 0x43 is transferred to the Shift register. Then 0x44 is
written to the Data register and goes to the Transmit Buffer register. A new transfer is started and 0x43 will be sent.
The value 0x45 is written to the Data register, but the Transmit Buffer register is not updated since it is already full
containing 0x44 and the Data Register Empty Interrupt Flag (DREIF in SPIn.INTFLAGS) is low. The value 0x45 will
be lost. After the transfer, the value 0x44 is moved to the Shift register. During the next transfer, 0x46 is written to the
Data register and 0x44 is sent out. After the transfer is complete 0x46 is copied into the Shift register and sent out in
the next transfer.
The Data Register Empty Interrupt Flag (DREIF in SPIn.INTFLAGS) goes low every time the Transmit Buffer register
is written and goes high after a transfer when the previous value in the Transmit Buffer register is copied into the Shift
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 311
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
register. The Receive Complete Interrupt Flag (RXCIF in SPIn.INTFLAGS) is set one cycle after the Data Register
Empty Interrupt Flag goes high. The Transfer Complete Interrupt Flag is set one cycle after the Receive Complete
Interrupt Flag is set when both the value in the shift register and the Transmit Buffer register have been sent.
Figure 25-4. SPI Timing Diagram in Buffer Mode with CTRLB.BUFWR Set to One
SS
SCK
Write DATA
Write value
0x43
0x44
0x45
0x46
DREIF
TXCIF
RXCIF
Transmit Buffer
Shift Register
Data sent
0x46
0x44
0x43
0x43
0x46
0x44
0x43
0x44
0x46
All writes to the Data register goes to the transmit buffer. The figure above shows that the value 0x43 is written to the
Data register and since the Slave Select pin is high it is copied to the Shift register the next cycle. Then the next write
(0x44) will go to the Transmit Buffer register. During the first transfer, the value 0x43 will be shifted out. In the figure,
the value 0x45 is written to the Data register, but the Transmit Buffer register is not updated since the Data Register
Empty Interrupt Flag is low. After the transfer is completed the value 0x44 from the Transmit Buffer register is copied
over to the Shift register. The value 0x46 is written to the Transmit Buffer register. During the next two transfers, 0x44
and 0x46 are shifted out. The flags behave the same as with Buffer mode Wait for Receive Bit (BUFWR in
SPIn.CTRLB) set to zero.
25.3.2.3 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data. The desired combination is
selected by writing to the MODE bits in the Control B register (SPIn.CTRLB).
The SPI data transfer formats are shown below. Data bits are shifted out and latched in on opposite edges of the
SCK signal, ensuring sufficient time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 312
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
Figure 25-5. SPI Data Transfer Modes
SPI Mode 0
Cycle #
4
3
SS
SCK
sampling
MISO
4
MOSI
4
SPI Mode 1
Cycle #
4
SS
SCK
sampling
MISO
4
MOSI
4
SPI Mode 2
Cycle #
4
SS
SCK
sampling
MISO
4
MOSI
4
SPI Mode 3
Cycle #
4
SS
SCK
sampling
MISO
MOSI
25.3.3
Interrupts
Table 25-5. Available Interrupt Vectors and Sources
Offset
Name
Vector Description
0x00
SPI
SPI interrupt
© 2019 Microchip Technology Inc.
Conditions
•
•
•
•
SSI: Slave Select Trigger Interrupt
DRE: Data Register Empty Interrupt
TXC: Transfer Complete Interrupt
RXC: Receive Complete Interrupt
Complete Datasheet
DS40002159A-page 313
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's Interrupt
Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
Related Links
9.7.3 SREG
14. CPU Interrupt Controller (CPUINT)
25.3.4
Sleep Mode Operation
The SPI will continue working in Idle Sleep mode. When entering any deeper sleep mode, an active transaction will
be stopped.
Related Links
12. Sleep Controller (SLPCTRL)
25.3.5
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 314
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.4
Register Summary - SPI
Offset
Name
Bit Pos.
0x00
0x01
0x02
CTRLA
CTRLB
INTCTRL
7:0
7:0
7:0
BUFEN
RXCIE
0x03
INTFLAGS
7:0
RXCIF/IF
0x04
DATA
7:0
25.5
DORD
BUFWR
TXCIE
TXCIF/
WRCOL
MASTER
CLK2X
PRESC[1:0]
SSD
DREIE
SSIE
ENABLE
MODE[1:0]
IE
DREIF
SSIF
BUFOVF
DATA[7:0]
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 315
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
DORD
R/W
0
5
MASTER
R/W
0
4
CLK2X
R/W
0
3
2
1
PRESC[1:0]
R/W
R/W
0
0
0
ENABLE
R/W
0
Bit 6 – DORD Data Order
Value
Description
0
The MSB of the data word is transmitted first
1
The LSB of the data word is transmitted first
Bit 5 – MASTER Master/Slave Select
Write this bit to configure SPI in desired mode.
If SS is configured as input and driven low while this bit is '1', this bit is cleared, and the IF flag in SPIn.INTFLAGS is
set. The user has to write MASTER=1 again to re-enable SPI Master mode.
This behavior is controlled by the Slave Select Disable bit (SSD) in SPIn.CTRLB.
Value
Description
0
SPI Slave mode selected
1
SPI Master mode selected
Bit 4 – CLK2X Clock Double
When this bit is written to '1' the SPI speed (SCK frequency, after internal prescaler) is doubled in Master mode.
Value
Description
0
SPI speed (SCK frequency) is not doubled
1
SPI speed (SCK frequency) is doubled in Master mode
Bits 2:1 – PRESC[1:0] Prescaler
This bit field controls the SPI clock rate configured in Master mode. These bits have no effect in Slave mode. The
relationship between SCK and the peripheral clock frequency (fCLK_PER) is shown below.
The output of the SPI prescaler can be doubled by writing the CLK2X bit to '1'.
Value
Name
Description
0x0
DIV4
CLK_PER/4
0x1
DIV16
CLK_PER/16
0x2
DIV64
CLK_PER/64
0x3
DIV128
CLK_PER/128
Bit 0 – ENABLE SPI Enable
Value
Description
0
SPI is disabled
1
SPI is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 316
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BUFEN
R/W
0
CTRLB
0x01
0x00
-
6
BUFWR
R/W
0
5
4
3
2
SSD
R/W
0
1
0
MODE[1:0]
R/W
0
R/W
0
Bit 7 – BUFEN Buffer Mode Enable
Writing this bit to '1' enables Buffer mode, meaning two buffers in receive direction, one buffer in transmit direction,
and separate interrupt flags for both transmit complete and receive complete.
Bit 6 – BUFWR Buffer Mode Wait for Receive
When writing this bit to '0' the first data transferred will be a dummy sample.
Value
Description
0
One SPI transfer must be completed before the data is copied into the Shift register.
1
When writing to the data register when the SPI is enabled and SS is high, the first write will go directly
to the Shift register.
Bit 2 – SSD Slave Select Disable
When this bit is set and when operating as SPI Master (MASTER=1 in SPIn.CTRLA), SS does not disable Master
mode.
Value
Description
0
Enable the Slave Select line when operating as SPI Master
1
Disable the Slave Select line when operating as SPI Master
Bits 1:0 – MODE[1:0] Mode
These bits select the Transfer mode. The four combinations of SCK phase and polarity with respect to the serial data
are shown in the table below. These bits decide whether the first edge of a clock cycle (leading edge) is rising or
falling and whether data setup and sample occur on the leading or trailing edge. When the leading edge is rising, the
SCK signal is low when idle, and when the leading edge is falling, the SCK signal is high when idle.
Value
Name
Description
0x0
0
Leading edge: Rising, sample
Trailing edge: Falling, setup
0x1
1
Leading edge: Rising, setup
Trailing edge: Falling, sample
0x2
2
Leading edge: Falling, sample
Trailing edge: Rising, setup
0x3
3
Leading edge: Falling, setup
Trailing edge: Rising, sample
Related Links
25.3.2.3 Data Modes
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 317
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.5.3
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIE
R/W
0
INTCTRL
0x02
0x00
-
6
TXCIE
R/W
0
5
DREIE
R/W
0
4
SSIE
R/W
0
3
2
1
0
IE
R/W
0
Bit 7 – RXCIE Receive Complete Interrupt Enable
In Buffer mode, this bit enables the receive complete interrupt. The enabled interrupt will be triggered when the
RXCIF flag in the SPIn.INTFLAGS register is set. In Non-Buffer mode this bit is zero.
Bit 6 – TXCIE Transfer Complete Interrupt Enable
In Buffer mode, this bit enables the transfer complete interrupt. The enabled interrupt will be triggered when the
TXCIF flag in the SPIn.INTFLAGS register is set. In Non-Buffer mode, this bit is zero.
Bit 5 – DREIE Data Register Empty Interrupt Enable
In Buffer mode this bit enables the data register empty interrupt. The enabled interrupt will be triggered when the
DREIF flag in the SPIn.INTFLAGS register is set. In Non-Buffer mode, this bit is zero.
Bit 4 – SSIE Slave Select Trigger Interrupt Enable
In Buffer mode, this bit enables the Slave Select interrupt. The enabled interrupt will be triggered when the SSIF flag
in the SPIn.INTFLAGS register is set. In Non-Buffer mode, this bit is zero.
Bit 0 – IE Interrupt Enable
This bit enables the SPI interrupt when the SPI is not in Buffer mode. The enabled interrupt will be triggered when
RXCIF/IF is set in the SPIn.INTFLAGS register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 318
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.5.4
Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RXCIF/IF
R/W
0
INTFLAGS
0x03
0x00
-
6
TXCIF/WRCOL
R/W
0
5
DREIF
R/W
0
4
SSIF
R/W
0
3
2
1
0
BUFOVF
R/W
0
Bit 7 – RXCIF/IF Receive Complete Interrupt Flag/Interrupt Flag
RXCIF: In Buffer mode, this flag is set when there is unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). In Non-Buffer mode, this bit does not have any effect.
When interrupt-driven data reception is used, the receive complete interrupt routine must read the received data from
SPIn.DATA in order to clear RXCIF. If not, a new interrupt will occur directly after the return from the current interrupt.
This flag can also be cleared by writing a 1 to its bit location.
IF: This flag is set when a serial transfer is complete and one byte is completely shifted in/out of the SPIn.DATA
register. If SS is configured as input and is driven low when the SPI is in Master mode, this will also set this flag. IF is
cleared by hardware when executing the corresponding interrupt vector. Alternatively, the IF flag can be cleared by
first reading the SPIn.INTFLAGS register when IF is set, and then accessing the SPIn.DATA register.
Bit 6 – TXCIF/WRCOL Transfer Complete Interrupt Flag/Write Collision Flag
TXCIF: In Buffer mode, this flag is set when all the data in the transmit shift register has been shifted out and there is
no new data in the transmit buffer (SPIn.DATA). The flag is cleared by writing a 1 to its bit location. In Non-Buffer
mode, this bit does not have any effect.
WRCOL: The WRCOL flag is set if the SPIn.DATA register is written to before a complete byte has been shifted out.
This flag is cleared by first reading the SPIn.INTFLAGS register when WRCOL is set, and then accessing the
SPIn.DATA register.
Bit 5 – DREIF Data Register Empty Interrupt Flag
In Buffer mode, this flag indicates whether the transmit buffer (SPIn.DATA) is ready to receive new data. The flag is 1
when the transmit buffer is empty and 0 when the transmit buffer contains data to be transmitted that has not yet
been moved into the Shift register. DREIF is set to '0' after a reset to indicate that the transmitter is ready. In NonBuffer mode, this bit is always 0.
DREIF is cleared by writing SPIn.DATA. When interrupt-driven data transmission is used, the Data register empty
interrupt routine must either write new data to SPIn.DATA in order to clear DREIF or disable the Data register empty
interrupt. If not, a new interrupt will occur directly after the return from the current interrupt.
Bit 4 – SSIF Slave Select Trigger Interrupt Flag
In Buffer mode, this flag indicates that the SPI has been in Master mode and the SS line has been pulled low
externally so the SPI is now working in Slave mode. The flag will only be set if the Slave Select Disable bit (SSD) is
not '1'. The flag is cleared by writing a 1 to its bit location. In Non-Buffer mode, this bit is always 0.
Bit 0 – BUFOVF Buffer Overflow
This flag is only used in Buffer mode. This flag indicates data loss due to a receiver buffer full condition. This flag is
set if a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full (two characters)
and a third byte has been received in the Shift register. If there is no transmit data the buffer overflow will not be set
before the start of a new serial transfer. This flag is valid until the receive buffer (SPIn.DATA) is read. Always write
this bit location to 0 when writing the SPIn.INTFLAGS register. In Non-Buffer mode, this bit is always 0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 319
ATtiny202/204/402/404/406 Automotiv...
Serial Peripheral Interface (SPI)
25.5.5
Data
Name:
Offset:
Reset:
Property:
Bit
7
DATA
0x04
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] SPI Data
The SPIn.DATA register is used for sending and receiving data. Writing to the register initiates the data transmission,
and the byte written to the register will be shifted out on the SPI output line.
Reading this register in Buffer mode will read the second receive buffer and the contents of the first receive buffer will
be moved to the second receive buffer.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 320
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.
Two-Wire Interface (TWI)
26.1
Features
•
•
•
•
•
•
26.2
Bidirectional, Two-Wire Communication Interface
Philips I2C compatible:
– Standard mode (Sm/100 kHz with slew-rate limited output)
– Fast mode (Fm/400 kHz with slew-rate limited output)
– Fast mode plus (Fm+/1 MHz with ×10 output drive strength)
System Management Bus (SMBus) Compatible (100 kHz with Slew-Rate Limited Output):
– Support arbitration between start/repeated start and data bit
– Slave arbitration allows support for the Address Resolution Protocol (ARP)
– Configurable SMBus Layer 1 time-outs in hardware
Independent Master and Slave Operation:
– Single or multi-master bus operation with full arbitration support
Flexible Slave Address Match Hardware Operating in All Sleep Modes, Including Power-Down:
– 7-bit and general call address recognition
– 10-bit addressing support in collaboration with software
– Address mask register allows address range masking - alternatively, it can be used as a secondary address
match
– Optional software address recognition for an unlimited number of addresses
Input Filter For Bus Noise Suppression
Overview
The Two-Wire Interface (TWI) peripheral is a bidirectional, two-wire communication interface. It is I2C and System
Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up
resistor on each bus line.
Any device connected to the bus must act as a master or a slave. The master initiates a data transaction by
addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many
slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more
than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the
protocol.
The TWI peripheral supports master and slave functionality. The master and slave functionality are separated from
each other and can be enabled and configured separately. The master module supports multi-master bus operation
and arbitration. It contains the Baud Rate Generator. All 100 kHz, 400 kHz, and 1 MHz bus frequencies are
supported. Quick command and Smart mode can be enabled to auto-trigger operations and reduce software
complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit
addressing is supported. A dedicated Address Mask register can act as a Second Address match register or as a
register for address range masking. The slave continues to operate in all Sleep modes, including Power-Down mode.
This enables the slave to wake-up the device from all Sleep modes on TWI address match. It is possible to disable
the address matching to let this be handled in software instead.
The TWI peripheral will detect Start and Stop conditions, bus collisions, and bus errors. Arbitration lost, errors,
collision, and clock hold on the bus are also detected and indicated in separate status flags available in both Master
and Slave modes.
This device provides one instance of the TWI peripheral; TWI0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 321
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.2.1
Block Diagram
Figure 26-1. TWI Block Diagram
Master
BAUD
TxDATA
0
baud rate generator
Slave
TxDATA
SCL
SCL hold low
0
SCL hold low
shift register
shift register
0
SDA
0
RxDATA
26.2.2
ADDR/ADDRMASK
RxDATA
==
Signal Description
Signal
Description
Type
SCL
Serial clock line
Digital I/O
SDA
Serial data line
Digital I/O
Related Links
5. I/O Multiplexing and Considerations
26.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 26-1. TWI System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
Yes
CPUINT
Events
No
-
Debug
Yes
UPDI
Related Links
26.2.3.1 Clocks
26.2.3.5 Debug Operation
26.2.3.2 I/O Lines and Connections
26.2.3.3 Interrupts
26.2.3.1 Clocks
This peripheral requires the system clock (CLK_PER). The relationship between CLK_PER and the TWI bus clock
(SCL) is explained in the TWI.MBAUD register.
Related Links
11. Clock Controller (CLKCTRL)
26.5.6 MBAUD
26.2.3.2 I/O Lines and Connections
Using the I/O lines of the peripheral requires configuration of the I/O pins.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 322
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
26.2.3.4 Events
Not applicable.
26.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
This peripheral can be forced to operate with halted CPU by writing a '1' to the Debug Run bit (DBGRUN) in the
Debug Control register of the peripheral (peripheral.DBGCTRL).
When the CPU is halted in Debug mode and DBGRUN=1, reading/writing the DATA register will neither trigger a bus
operation nor cause transmit and clear flags.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
Related Links
31. Unified Program and Debug Interface (UPDI)
26.3
Functional Description
26.3.1
Initialization
Before enabling the master or the slave unit, ensure that the correct settings for SDASETUP, SDAHOLD, and, if
used, Fast-mode plus (FMPEN) are stored in TWI.CTRLA.
Master Operation
It is recommended to write to the Master Baud Rate register (TWIn.BAUD) before enabling the TWI master since
TIMEOUT is dependent on the baud rate setting. To start the TWI master, write a ‘1’ to the ENABLE bit and configure
an appropriate TIMEOUT if using the TWI in an SMBus environment. The ENABLE and TIMEOUT bits are all located
in the Master Control A register (TWIn.MCTRLA). If no TIMEOUT value is set, which is the case for I²C operation, the
bus state must be manually set to IDLE by writing 0x1 to BUSSTATE in TWIn.MSTATUS at a safe point in time. Note
that unlike the SMBus specification, the I²C specification does not specify when it is safe to assume that the bus is
idle in a multi-master system. The application can solve this by ensuring that after all masters connected to the bus
are enabled, one supervising master performs a transfer before any of the other masters. The stop condition of this
initial transfer will indicate to the Bus State Monitor logic that the bus is idle and ready.
Slave Operation
To start the TWI slave, write the Slave Address (TWIn.SADDR), and write a '1' to the ENABLE bit in the Slave Control
A register (TWIn.SCTRLA). The TWI peripheral will wait to receive a byte addressed to it.
26.3.2
General TWI Bus Concepts
The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial clock line (SCL) and a
serial data line (SDA). The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only
external components needed to drive the bus. The pull-up resistors provide a high level on the lines when none of the
connected devices are driving the bus.
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus. A device connected
to the bus can be a master or slave, where the master controls the bus and all communication.
Figure 26-2 illustrates the TWI bus topology.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 323
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Figure 26-2. TWI Bus Topology
VCC
RP
RP
TWI
DEVICE #1
TWI
DEVICE #2
TWI
DEVICE #N
RS
RS
RS
RS
RS
RS
SDA
SCL
Note: RS is optional
A unique address is assigned to all slave devices connected to the bus, and the master will use this to address a
slave and initiate a data transaction.
Several masters can be connected to the same bus, called a multi-master environment. An arbitration mechanism is
provided for resolving bus ownership among masters, since only one master device may own the bus at any given
time.
A device can contain both master and slave logic and can emulate multiple slave devices by responding to more than
one address.
A master indicates the start of a transaction by issuing a Start condition (S) on the bus. An address packet with a
slave address (ADDRESS) and an indication whether the master wishes to read or write data (R/W) are then sent.
After all data packets (DATA) are transferred, the master issues a Stop condition (P) on the bus to end the
transaction. The receiver must acknowledge (A) or not-acknowledge (A) each byte received.
Figure 26-3 shows a TWI transaction.
Figure 26-3. Basic TWI Transaction Diagram Topology for a 7-bit Address Bus
SDA
SCL
6 ... 0
S
ADDRESS
S
ADDRESS
7 ... 0
R/W
R/W
ACK
DATA
DATA
A
7 ... 0
ACK
A
DATA
P
ACK/NACK
A/A
DATA
P
Direction
Address Packet
Data Packet #0
Data Packet #1
Transaction
The master provides data on the bus
The master or slave can provide data on the bus
The slave provides data on the bus
The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the
low-level period of the clock to decrease the clock speed.
26.3.2.1 Start and Stop Conditions
Two unique bus conditions are used for marking the beginning (Start) and end (Stop) of a transaction. The master
issues a Start condition (S) by indicating a high-to-low transition on the SDA line while the SCL line is kept high. The
master completes the transaction by issuing a Stop condition (P), indicated by a low-to-high transition on the SDA
line while the SCL line is kept high.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 324
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Figure 26-4. Start and Stop Conditions
SDA
SCL
S
P
START
Condition
STOP
Condition
Multiple Start conditions can be issued during a single transaction. A Start condition that is not directly following a
Stop condition is called a repeated Start condition (Sr).
26.3.2.2 Bit Transfer
As illustrated by Figure 26-5, a bit transferred on the SDA line must be stable for the entire high period of the SCL
line. Consequently, the SDA value can only be changed during the low period of the clock. This is ensured in
hardware by the TWI module.
Figure 26-5. Data Validity
SDA
SCL
DATA
Valid
Change
Allowed
Combining bit transfers result in the formation of address and data packets. These packets consist of eight data bits
(one byte) with the Most Significant bit transferred first, plus a single-bit not-Acknowledge (NACK) or Acknowledge
(ACK) response. The addressed device signals ACK by pulling the SCL line low during the ninth clock cycle, and
signals NACK by leaving the line SCL high.
26.3.2.3 Address Packet
After the Start condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is always transmitted by the
master. A slave recognizing its address will ACK the address by pulling the data line low for the next SCL cycle, while
all other slaves should keep the TWI lines released and wait for the next Start and address. The address, R/W bit,
and Acknowledge bit combined is the address packet. Only one address packet for each Start condition is allowed,
also when 10-bit addressing is used.
The R/W bit specifies the direction of the transaction. If the R/W bit is low, it indicates a master write transaction, and
the master will transmit its data after the slave has acknowledged its address. If the R/W bit is high, it indicates a
master read transaction, and the slave will transmit its data after acknowledging its address.
26.3.2.4 Data Packet
An address packet is followed by one or more data packets. All data packets are nine bits long, consisting of one
data byte and one Acknowledge bit. The direction bit in the previous address packet determines the direction in which
the data is transferred.
26.3.2.5 Transaction
A transaction is the complete transfer from a Start to a Stop condition, including any repeated Start conditions in
between. The TWI standard defines three fundamental transaction modes: Master write, master read, and a
combined transaction.
Figure 26-6 illustrates the master write transaction. The master initiates the transaction by issuing a Start condition
(S) followed by an address packet with the direction bit set to zero (ADDRESS+W).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 325
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Figure 26-6. Master Write Transaction
Transaction
Data Packet
Address Packet
S
ADDRESS
W
A
DATA
A
DATA
A/A
P
N data packets
Assuming the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK
or NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a
Stop condition (P) directly after the address packet. There are no limitations to the number of data packets that can
be transferred. If the slave signals a NACK to the data, the master must assume that the slave cannot receive any
more data and terminate the transaction.
Figure 26-7 illustrates the master read transaction. The master initiates the transaction by issuing a Start condition
followed by an address packet with the direction bit set to one (ADDRESS+R). The addressed slave must
acknowledge the address for the master to be allowed to continue the transaction.
Figure 26-7. Master Read Transaction
Transaction
Data Packet
Address Packet
S
R
ADDRESS
A
DATA
A
DATA
A
P
N data packets
Assuming the slave acknowledges the address, the master can start receiving data from the slave. There are no
limitations to the number of data packets that can be transferred. The slave transmits the data while the master
signals ACK or NACK after each data byte. The master terminates the transfer with a NACK before issuing a Stop
condition.
Figure 26-8 illustrates a combined transaction. A combined transaction consists of several read and write
transactions separated by repeated Start conditions (Sr).
Figure 26-8. Combined Transaction
Transaction
Address Packet #1
S
ADDRESS
R/W
Address Packet #2
N Data Packets
A
DATA
A/A Sr
ADDRESS
R/W
M Data Packets
A
DATA
A/A
P
Direction
Direction
26.3.2.6 Clock and Clock Stretching
All devices connected to the bus are allowed to stretch the low period of the clock to slow down the overall clock
frequency or to insert Wait states while processing data. A device that needs to stretch the clock can do this by
holding/forcing the SCL line low after it detects a low level on the line.
Three types of clock stretching can be defined, as shown in Figure 26-9.
Figure 26-9. Clock Stretching (1)
SDA
bit 7
bit 6
bit 0
ACK/NACK
SCL
S
Wakeup clock
stretching
Periodic clock
stretching
Random clock
stretching
Note: Clock stretching is not supported by all I2C slaves and masters.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 326
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
If a slave device is in Sleep mode and a Start condition is detected, the clock stretching normally works during the
wake-up period. For AVR devices, the clock stretching will be either directly before or after the ACK/NACK bit, as
AVR devices do not need to wake-up for transactions that are not addressed to it.
A slave device can slow down the bus frequency by stretching the clock periodically on a bit level. This allows the
slave to run at a lower system clock frequency. However, the overall performance of the bus will be reduced
accordingly. Both the master and slave device can randomly stretch the clock on a byte level basis before and after
the ACK/NACK bit. This provides time to process incoming or prepare outgoing data or perform other time-critical
tasks.
In the case where the slave is stretching the clock, the master will be forced into a Wait state until the slave is ready,
and vice versa.
26.3.2.7 Arbitration
A master can start a bus transaction only if it has detected that the bus is idle. As the TWI bus is a multi-master bus,
it is possible that two devices may initiate a transaction at the same time. This results in multiple masters owning the
bus simultaneously. This is solved using an arbitration scheme where the master loses control of the bus if it is not
able to transmit a high level on the SDA line. The masters who lose arbitration must then wait until the bus becomes
idle (i.e., wait for a Stop condition) before attempting to reacquire bus ownership. Slave devices are not involved in
the arbitration procedure.
Figure 26-10. TWI Arbitration
DEVICE1 Loses arbitration
DEVICE1_SDA
DEVICE2_SDA
SDA
(wired-AND)
bit 7
bit 6
bit 5
bit 4
SCL
S
Figure 26-10 shows an example where two TWI masters are contending for bus ownership. Both devices are able to
issue a Start condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2
is transmitting a low level.
Arbitration between a repeated start condition and a data bit, a Stop condition and a data bit, or a repeated Start
condition and a Stop condition are not allowed and will require special handling by software.
26.3.2.8 Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is trying to control
the SCL line at the same time. The algorithm is based on the same principles used for the clock stretching previously
described. Figure 26-11 shows an example where two masters are competing for control over the bus clock. The SCL
line is the wired-AND result of the two masters clock outputs.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 327
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Figure 26-11. Clock Synchronization
Low Period
Count
Wait
State
High Period
Count
DEVICE1_SCL
DEVICE2_SCL
SCL
(wired-AND)
A high-to-low transition on the SCL line will force the line low for all masters on the bus, and they will start timing their
low clock period. The timing length of the low clock period can vary among the masters. When a master (DEVICE1 in
this case) has completed its low period, it releases the SCL line. However, the SCL line will not go high until all
masters have released it. Consequently, the SCL line will be held low by the device with the longest low period
(DEVICE2). Devices with shorter low periods must insert a wait state until the clock is released. All masters start their
high period when the SCL line is released by all devices and has gone high. The device, which first completes its
high period (DEVICE1), forces the clock line low, and the procedure is then repeated. The result is that the device
with the shortest clock period determines the high period, while the low period of the clock is determined by the
device with the longest clock period.
26.3.3
TWI Bus State Logic
The bus state logic continuously monitors the activity on the TWI bus lines when the master is enabled. It continues
to operate in all Sleep modes, including power-down.
The bus state logic includes Start and Stop condition detectors, collision detection, inactive bus time-out detection,
and a bit counter. These are used to determine the bus state. The software can get the current bus state by reading
the Bus State bits in the master STATUS register. The bus state can be unknown, idle, busy, or owner, and is
determined according to the state diagram shown in Figure 26-12. The values of the Bus State bits according to
state, are shown in binary in the figure below.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 328
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Figure 26-12. Bus State, State Diagram
RESET
UNKNOWN
(0b00)
P + Timeout
S
IDLE
BUSY
P + Timeout
(0b01)
Sr
(0b11)
Command P
Write ADDRESS
(S)
OWNER
Arbitration
Lost
(0b10)
Write
ADDRESS(Sr)
After a system Reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to
enter idle by writing to the Bus State bits accordingly. If no state is set by the application software, the bus state will
become idle when the first Stop condition is detected. If the master inactive bus timeout is enabled, the bus state will
change to idle on the occurrence of a timeout. After a known bus state is established, only a system Reset or
disabling of the TWI master will set the state to unknown.
When the bus is idle, it is ready for a new transaction. If a Start condition generated externally is detected, the bus
becomes busy until a Stop condition is detected. The Stop condition will change the bus state to idle. If the master
inactive bus timeout is enabled, the bus state will change from busy to idle on the occurrence of a timeout.
If a Start condition is generated internally while in an Idle state, the owner state is entered. If the complete transaction
was performed without interference (i.e., no collisions are detected), the master will issue a Stop condition and the
bus state will change back to idle. If a collision is detected, the arbitration is assumed lost and the bus state becomes
busy until a Stop condition is detected. A repeated Start condition will only change the bus state if arbitration is lost
during the issuing of the repeated Start. Arbitration during repeated Start can be lost only if the arbitration has been
ongoing since the first Start condition. This happens if two masters send the exact same ADDRESS+DATA before
one of the masters' issues a repeated Start (Sr).
26.3.4
Operation
26.3.4.1 Electrical Characteristics
The TWI module in AVR devices follows the electrical specifications and timing of I2C bus and SMBus. These
specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus time-out period should be
set in TWI Master mode. Refer to 26.3.4.2 TWI Master Operation for more details.
26.3.4.2 TWI Master Operation
The TWI master is byte-oriented, with an optional interrupt after each byte. There are separate interrupt flags for
master write and master read. Interrupt flags can also be used for polled operation. There are dedicated status flags
for indicating ACK/NACK received, bus error, arbitration lost, clock hold, and bus state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data,
and will in most cases require software interaction. Figure 26-13 shows the TWI master operation. The diamondshaped symbols (SW) indicate where software interaction is required. Clearing the interrupt flags releases the SCL
line.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 329
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Figure 26-13. TWI Master Operation
APPLICATION
MASTER WRITE INTERRUPT + HOLD
M1
M3
M2
BUSY
P
IDLE
S
Wait for
IDLE
SW
M4
ADDRESS
R/W BUSY
SW
R/W
A
SW
P
W
A
SW
Sr
M2
IDLE
M3
BUSY
M4
A/A
DATA
SW
SW
M1
BUSY
Driver software
MASTER READ INTERRUPT + HOLD
The master provides data
on the bus
SW
Slave provides data on
the bus
A
A/A
BUSY
P
Bus state
Mn
A/A Sr
Diagram connections
IDLE
M4
M2
M3
A/A
R
A
DATA
The number of interrupts generated is kept to a minimum by an automatic handling of most conditions.
26.3.4.2.1 Clock Generation
The BAUD must be set to a value that results in a TWI bus clock frequency (fSCL) equal or less than 100 kHz/400
kHz/1 MHz, dependent on the mode used by the application (Standard mode Sm/Fast mode Fm/Fast mode plus Fm
+).
The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and
fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be
considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been
detected.
Figure 26-14. SCL Timing
RISE
•
•
•
•
TLOW – Low period of SCL clock
TSU;STO – Set-up time for Stop condition
TBUF – Bus free time between Stop and Start conditions
THD;STA – Hold time (repeated) Start condition
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 330
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
•
•
•
•
TSU;STA – Set-up time for repeated Start condition
THIGH is timed using the SCL high time count from TWI.MBAUD
TRISE is determined by the bus impedance; for internal pull-ups. Refer to Electrical Characteristics.
TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer
to Electrical Characteristics for details.
The SCL frequency is given by:
�SCL =
1
�LOW + �HIGH + �RISE
�SCL =
�CLK_PER
10 + 2���� + �CLK_PER ⋅ �RISE
The TWI.MBAUD value is used to time both SCL high and SCL low which gives the following formula of SCL
frequency:
If the TWI is in Fm+ mode, only TWI.MBAUD value of three or higher is supported. This means that for Fm+ mode to
achieve baud rate of 1 MHz, the peripheral clock (CLK_PER) has to run at 16 MHz or faster.
26.3.4.2.2 Transmitting Address Packets
After issuing a Start condition, the master starts performing a bus transaction when the Master Address register is
written with the 7-bit slave address and direction bit. If the bus is busy, the TWI master will wait until the bus becomes
idle before issuing the Start condition.
Depending on arbitration and the R/W direction bit, one of four distinct cases (M1 to M4) arises following the address
packet. The different cases must be handled in software.
Case M1: Arbitration Lost or Bus Error during Address Packet
If arbitration is lost during the sending of the address packet, both the Master Write Interrupt Flag (WIF in
TWIn.MSTATUS) and Arbitration Lost Flag (ARBLOST in TWIn.MSTATUS) are set. Serial data output to the SDA line
is disabled, and the SCL line is released. The master is no longer allowed to perform any operation on the bus until
the bus state has changed back to idle.
A bus error will behave in the same way as an arbitration lost condition, but the Bus Error Flag (BUSERR in
TWIn.MSTATUS) is set in addition to the write interrupt and arbitration lost flags.
Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave
If no slave device responds to the address, the Master Write Interrupt Flag (WIF in TWIn.MSTATUS) and the Master
Received Acknowledge Flag (RXACK in TWIn.MSTATUS) are set. The RXACK flag reflects the physical state of the
ACK bit (i.e.< no slave did pull the ACK bit low). The clock hold is active at this point, preventing further activity on the
bus.
Case M3: Address Packet Transmit Complete - Direction Bit Cleared
If the master receives an ACK from the slave, the Master Write Interrupt Flag (WIF in TWIn.MSTATUS) is set and the
Master Received Acknowledge Flag (RXACK in TWIn.MSTATUS) is cleared. The clock hold is active at this point,
preventing further activity on the bus.
Case M4: Address Packet Transmit Complete - Direction Bit Set
If the master receives an ACK from the slave, the master proceeds to receive the next byte of data from the slave.
When the first data byte is received, the Master Read Interrupt Flag (RIF in TWIn.MSTATUS) is set and the Master
Received Acknowledge Flag (RXACK in TWIn.MSTATUS) is cleared. The clock hold is active at this point, preventing
further activity on the bus.
26.3.4.2.3 Transmitting Data Packets
The slave will know when an address packet with R/W direction bit set has been successfully received. It can then
start sending data by writing to the slave data register. When a data packet transmission is completed, the data
interrupt flag is set. If the master indicates NACK, the slave must stop transmitting data and expect a Stop or
repeated Start condition.
26.3.4.2.4 Receiving Data Packets
The slave will know when an address packet with R/W direction bit cleared has been successfully received. After
acknowledging this, the slave must be ready to receive data. When a data packet is received, the data interrupt flag
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 331
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
is set and the slave must indicate ACK or NACK. After indicating a NACK, the slave must expect a Stop or repeated
Start condition.
26.3.4.2.5 Quick Command Mode
With Quick Command enabled (QCEN in TWIn.MCTRLA), the R/W# bit of the slave address denotes the command.
This is a SMBus specific command where the R/W bit may be used to simply turn a device function ON or OFF, or
enable/disable a low-power Standby mode. There is no data sent or received.
After the master receives an acknowledge from the slave, either RIF or WIF flag in TWIn.MSTATUS will be set
depending on the polarity of R/W. When either RIF or WIF flag is set after issuing a Quick Command, the TWI will
accept a stop command through writing the CMD bits in TWIn.MCTRLB.
Figure 26-15. Quick Command Frame Format
S
Address
R/W
A
P
26.3.4.3 TWI Slave Operation
The TWI slave is byte-oriented with optional interrupts after each byte. There are separate slave data and address/
stop interrupt flags. Interrupt flags can also be used for polled operation. There are dedicated status flags for
indicating ACK/NACK received, clock hold, collision, bus error, and read/write direction.
When an interrupt flag is set, the SCL line is forced low. This will give the slave time to respond or handle data, and
will in most cases require software interaction. Figure 26-16 shows the TWI slave operation. The diamond shaped
symbols (SW) indicate where software interaction is required.
Figure 26-16. TWI Slave Operation
SLAVE ADDRESS INTERRUPT
S1
S3
S2
S
A
ADDRESS
R
SW
P
S2
Sr
S3
DATA
SW
S1
P
S2
Sr
S3
A/A
Driversoftware
The master provides data
on the bus
Slave provides data on
the bus
Sn
S1
A
A
SW
SLAVE DATA INTERRUPT
W
SW
Interrupton STOP
ConditionEnabled
SW
A/A
DATA
SW
A/A
Diagramconnections
The number of interrupts generated is kept to a minimum by automatic handling of most conditions. Quick command
can be enabled to auto-trigger operations and reduce software complexity.
Address Recognition mode can be enabled to allow the slave to respond to all received addresses.
26.3.4.3.1 Receiving Address Packets
When the TWI slave is properly configured, it will wait for a Start condition to be detected. When this happens, the
successive address byte will be received and checked by the address match logic, and the slave will ACK a correct
address and store the address in the TWIn.DATA register. If the received address is not a match, the slave will not
acknowledge and store the address, but wait for a new Start condition.
The slave address/stop interrupt flag is set when a Start condition succeeded by a valid address byte is detected. A
general call address will also set the interrupt flag.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 332
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
A Start condition immediately followed by a Stop condition is an illegal operation and the bus error flag is set.
The R/W direction flag reflects the direction bit received with the address. This can be read by software to determine
the type of operation currently in progress.
Depending on the R/W direction bit and bus condition, one of four distinct cases (S1 to S4) arises following the
address packet. The different cases must be handled in software.
Case S1: Address Packet Accepted - Direction Bit Set
If the R/W direction flag is set, this indicates a master read operation. The SCL line is forced low by the slave,
stretching the bus clock. If ACK is sent by the slave, the slave hardware will set the data interrupt flag indicating data
is needed for transmit. Data, repeated Start, or Stop can be received after this. If NACK is sent by the slave, the slave
will wait for a new Start condition and address match.
Case S2: Address Packet Accepted - Direction Bit Cleared
If the R/W direction flag is cleared, this indicates a master write operation. The SCL line is forced low, stretching the
bus clock. If ACK is sent by the slave, the slave will wait for data to be received. Data, repeated Start, or Stop can be
received after this. If NACK is sent, the slave will wait for a new Start condition and address match.
Case S3: Collision
If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and
acknowledge output from the slave logic. The clock hold is released. A Start or repeated Start condition will be
accepted.
Case S4: STOP Condition Received
When the Stop condition is received, the slave address/stop flag will be set, indicating that a Stop condition, and not
an address match, occurred.
26.3.4.3.2 Receiving Data Packets
The slave will know when an address packet with R/W direction bit cleared has been successfully received. After
acknowledging this, the slave must be ready to receive data. When a data packet is received, the data interrupt flag
is set and the slave must indicate ACK or NACK. After indicating a NACK, the slave must expect a Stop or repeated
Start condition.
26.3.4.3.3 Transmitting Data Packets
The slave will know when an address packet with R/W direction bit set has been successfully received. It can then
start sending data by writing to the slave data register. When a data packet transmission is completed, the data
interrupt flag is set. If the master indicates NACK, the slave must stop transmitting data and expect a Stop or
repeated Start condition.
26.3.4.4 Smart Mode
The TWI interface has a Smart mode that simplifies application code and minimizes the user interaction needed to
adhere to the I2C protocol. For TWI Master, Smart mode accomplishes this by automatically sending an ACK as soon
as data register TWI.MDATA is read. This feature is only active when the ACKACT bit in TWIn.MCTRLA register is
set to ACK. If ACKACT is set to NACK, the TWI Master will not generate a NACK bit followed by reading the Data
register.
With Smart mode enabled for TWI Slave (SMEN bit in TWIn.SCTRLA), DIF (Data Interrupt Flag) will automatically be
cleared if Data register (TWIn.SDATA) is read or written.
26.3.5
Events
Not applicable.
26.3.6
Interrupts
Table 26-2. Available Interrupt Vectors and Sources
Offset
Name
Vector Description
0x00
Slave
TWI Slave interrupt
© 2019 Microchip Technology Inc.
Conditions
•
•
DIF: Data Interrupt Flag in 26.5.11 SSTATUS set
APIF: Address or Stop Interrupt Flag in 26.5.11 SSTATUS set
Complete Datasheet
DS40002159A-page 333
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
...........continued
Offset
Name
Vector Description
0x02
Master
TWI Master interrupt
Conditions
•
•
RIF: Read Interrupt Flag in 26.5.5 MSTATUS set
WIF: Write Interrupt Flag in 26.5.5 MSTATUS set
When an interrupt condition occurs, the corresponding interrupt flag is set in the Master register (TWI.MSTATUS) or
Slave Status register (TWI.SSTATUS).
When several interrupt request conditions are supported by an interrupt vector, the interrupt requests are ORed
together into one combined interrupt request to the interrupt controller. The user must read the peripheral's
INTFLAGS register to determine which of the interrupt conditions are present.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
26.3.7
Sleep Mode Operation
The bus state logic and slave continue to operate in all Sleep modes, including Power-Down Sleep mode. If a slave
device is in Sleep mode and a Start condition is detected, clock stretching is active during the wake-up period until
the system clock is available. The master will stop operation in all Sleep modes.
26.3.8
Synchronization
Not applicable.
26.3.9
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 334
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.4
Register Summary - TWI
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
CTRLA
Reserved
DBGCTRL
MCTRLA
MCTRLB
MSTATUS
MBAUD
MADDR
MDATA
SCTRLA
SCTRLB
SSTATUS
SADDR
SDATA
SADDRMASK
7:0
26.5
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
SDASETUP
RIEN
WIEN
RIF
WIF
DIEN
APIEN
DIF
APIF
QCEN
SDAHOLD[1:0]
TIMEOUT[1:0]
FLUSH
ACKACT
CLKHOLD
RXACK
ARBLOST
BUSERR
BAUD[7:0]
ADDR[7:0]
DATA[7:0]
PIEN
PMEN
ACKACT
CLKHOLD
RXACK
COLL
BUSERR
ADDR[7:0]
DATA[7:0]
ADDRMASK[6:0]
FMPEN
DBGRUN
SMEN
ENABLE
MCMD[1:0]
BUSSTATE[1:0]
SMEN
ENABLE
SCMD[1:0]
DIR
AP
ADDREN
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 335
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
-
6
5
4
SDASETUP
R/W
0
Access
Reset
3
2
SDAHOLD[1:0]
R/W
R/W
0
0
1
FMPEN
R/W
0
0
Bit 4 – SDASETUP SDA Setup Time
By default, there are four clock cycles of setup time on SDA out signal while reading from the slave part of the TWI
module. Writing this bit to '1' will change the setup time to eight clocks.
Value
Name
Description
0
4CYC
SDA setup time is four clock cycles
1
8CYC
SDA setup time is eight clock cycle
Bits 3:2 – SDAHOLD[1:0] SDA Hold Time
Writing these bits selects the SDA hold time.
Table 26-3. SDA Hold Time
SDAHOLD[1:0] Nominal Hold Time Hold Time Range Across All
Corners (ns)
Description
0x0
OFF
0
Hold time off.
0x1
50 ns
36 - 131
Backward compatible setting.
0x2
300 ns
180 - 630
Meets SMBus specification under
typical conditions.
0x3
500 ns
300 - 1050
Meets SMBus specification across all
corners.
Bit 1 – FMPEN FM Plus Enable
Writing these bits selects the 1 MHz bus speed (Fast mode plus, Fm+) for the TWI in default configuration.
Value
Description
0
Fm+ disabled
1
Fm+ enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 336
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.2
Debug Control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x02
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 337
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.3
Master Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RIEN
R/W
0
MCTRLA
0x03
0x00
-
6
WIEN
R/W
0
5
4
QCEN
R/W
0
3
2
TIMEOUT[1:0]
R/W
R/W
0
0
1
SMEN
R/W
0
0
ENABLE
R/W
0
Bit 7 – RIEN Read Interrupt Enable
Writing this bit to '1' enables interrupt on the Master Read Interrupt Flag (RIF) in the Master Status register
(TWIn.MSTATUS). A TWI Master read interrupt would be generated only if this bit, the RIF, and the Global Interrupt
Flag (I) in CPU.SREG are all '1'.
Bit 6 – WIEN Write Interrupt Enable
Writing this bit to '1' enables interrupt on the Master Write Interrupt Flag (WIF) in the Master Status register
(TWIn.MSTATUS). A TWI Master write interrupt will be generated only if this bit, the WIF, and the Global Interrupt
Flag (I) in CPU.SREG are all '1'.
Bit 4 – QCEN Quick Command Enable
Writing this bit to '1' enables Quick Command. When Quick Command is enabled, the corresponding interrupt flag is
set immediately after the slave acknowledges the address. At this point, the software can either issue a Stop
command or a repeated Start by writing either the Command bits (CMD) in the Master Control B register
(TWIn.MCTRLB) or the Master Address register (TWIn.MADDR).
Bits 3:2 – TIMEOUT[1:0] Inactive Bus Timeout
Setting the inactive bus timeout (TIMEOUT) bits to a non-zero value will enable the inactive bus time-out supervisor.
If the bus is inactive for longer than the TIMEOUT setting, the bus state logic will enter the Idle state.
Value
Name
Description
0x0
DISABLED
Bus timeout disabled. I2C.
0x1
50US
50 µs - SMBus (assume baud is set to 100 kHz)
0x2
100US
100 µs (assume baud is set to 100 kHz)
0x3
200US
200 µs (assume baud is set to 100 kHz)
Bit 1 – SMEN Smart Mode Enable
Writing this bit to '1' enables the Master Smart mode. When Smart mode is enabled, the acknowledge action is sent
immediately after reading the Master Data (TWIn.MDATA) register.
Bit 0 – ENABLE Enable TWI Master
Writing this bit to '1' enables the TWI as master.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 338
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.4
Master Control B
Name:
Offset:
Reset:
Property:
Bit
MCTRLB
0x04
0x00
-
7
6
5
Access
Reset
4
3
FLUSH
R/W
0
2
ACKACT
R/W
0
1
0
MCMD[1:0]
R/W
0
R/W
0
Bit 3 – FLUSH Flush
Writing a '1' to this bit generates a strobe for one clock cycle disabling and then enabling the master.
Writing '0' has no effect.
The purpose is to clear the internal state of master: For TWI master to transmit successfully, it is recommended to
write the Master Address register (TWIn.MADDR) first and then the Master Data register (TWIn.MDATA).
The peripheral will transmit invalid data if TWIn.MDATA is written before TWIn.MADDR. To avoid this invalid
transmission, write '1' to this bit to clear both registers.
Bit 2 – ACKACT Acknowledge Action
This bit defines the master’s behavior under certain conditions defined by the bus protocol state and software
interaction. The acknowledge action is performed when DATA is read, or when an execute command is written to the
CMD bits.
The ACKACT bit is not a flag or strobe, but an ordinary read/write accessible register bit. The default ACKACT for
master read interrupt is “Send ACK” (0). For master write, the code will know that no acknowledge should be sent
since it is itself sending data.
Value
Description
0
Send ACK
1
Send NACK
Bits 1:0 – MCMD[1:0] Command
The master command bits are strobes. These bits are always read as zero.
Writing to these bits triggers a master operation as defined by the table below.
Table 26-4. Command Settings
MCMD[1:0]
DIR
Description
0x0
X
NOACT - No action
0x1
X
REPSTART - Execute Acknowledge Action succeeded by repeated Start.
0x2
0
RECVTRANS - Execute Acknowledge Action succeeded by a byte read operation.
1
Execute Acknowledge Action (no action) succeeded by a byte send operation.(1)
X
STOP - Execute Acknowledge Action succeeded by issuing a Stop condition.
0x3
Note:
1. For a master being a sender, it will normally wait for new data written to the Master Data register
(TWIn.MDATA).
The acknowledge action bits and command bits can be written at the same time.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 339
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.5
Master Status
Name:
Offset:
Reset:
Property:
MSTATUS
0x05
0x00
-
Normal TWI operation dictates that this register is regarded purely as a read-only register. Clearing any of the status
flags is done indirectly by accessing the Master Transmits Address (TWIn.MADDR), Master Data register
(TWIn.MDATA), or the Command bits (CMD) in the Master Control B register (TWIn.MCTRLB).
Bit
Access
Reset
7
RIF
R/W
0
6
WIF
R/W
0
5
CLKHOLD
R/W
0
4
RXACK
R
0
3
ARBLOST
R/W
0
2
BUSERR
R/W
0
1
0
BUSSTATE[1:0]
R/W
R/W
0
0
Bit 7 – RIF Read Interrupt Flag
This bit is set to '1' when the master byte read operation is successfully completed (i.e., no arbitration lost or bus error
occurred during the operation). The read operation is triggered by software reading DATA or writing to ADDR
registers with bit ADDR[0] written to '1'. A slave device must have responded with an ACK to the address and
direction byte transmitted by the master for this flag to be set.
Writing a '1' to this bit will clear the RIF. However, normal use of the TWI does not require the flag to be cleared by
this method.
Clearing the RIF bit will follow the same software interaction as the CLKHOLD flag.
The RIF flag can generate a master read interrupt (see description of the RIEN control bit in the TWIn.MCTRLA
register).
Bit 6 – WIF Write Interrupt Flag
This bit is set when a master transmit address or byte write is completed, regardless of the occurrence of a bus error
or an arbitration lost condition.
Writing a '1' to this bit will clear the WIF. However, normal use of the TWI does not require the flag to be cleared by
this method.
Clearing the WIF bit will follow the same software interaction as the CLKHOLD flag.
The WIF flag can generate a master write interrupt (see description of the WIEN control bit in the TWIn.MCTRLA
register).
Bit 5 – CLKHOLD Clock Hold
If read as '1', this bit indicates that the master is currently holding the TWI clock (SCL) low, stretching the TWI clock
period.
Writing a '1' to this bit will clear the CLKHOLD flag. However, normal use of the TWI does not require the CLKHOLD
flag to be cleared by this method, since the flag is automatically cleared when accessing several other TWI registers.
The CLKHOLD flag can be cleared by:
1. Writing a '1' to it.
2. Writing to the TWIn.MADDR register.
3. Writing to the TWIn.MDATA register.
4. Reading the TWIn.DATA register while the ACKACT control bits in TWIn.MCTRLB are set to either send ACK
or NACK.
5. Writing a valid command to the TWIn.MCTRLB register.
Bit 4 – RXACK Received Acknowledge
This bit is read-only and contains the most recently received Acknowledge bit from the slave.
Bit 3 – ARBLOST Arbitration Lost
If read as '1' this bit indicates that the master has lost arbitration while transmitting a high data or NACK bit, or while
issuing a Start or repeated Start condition (S/Sr) on the bus.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 340
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Writing a '1' to it will clear the ARBLOST flag. However, normal use of the TWI does not require the flag to be cleared
by this method. However, as for the CLKHOLD flag, clearing the ARBLOST flag is not required during normal use of
the TWI.
Clearing the ARBLOST bit will follow the same software interaction as the CLKHOLD flag.
Given the condition where the bus ownership is lost to another master, the software must either abort operation or
resend the data packet. Either way, the next required software interaction is in both cases to write to the
TWIn.MADDR register. A write access to the TWIn.MADDR register will then clear the ARBLOST flag.
Bit 2 – BUSERR Bus Error
The BUSERR flag indicates that an illegal bus condition has occurred. An illegal bus condition is detected if a
protocol violating Start (S), repeated Start (Sr), or Stop (P) is detected on the TWI bus lines. A Start condition directly
followed by a Stop condition is one example of protocol violation.
Writing a '1' to this bit will clear the BUSERR. However, normal use of the TWI does not require the BUSERR to be
cleared by this method.
A robust TWI driver software design will treat the bus error flag similarly to the ARBLOST flag, assuming the bus
ownership is lost when the bus error flag is set. As for the ARBLOST flag, the next software operation of writing the
TWIn.MADDR register will consequently clear the BUSERR flag. For bus error to be detected, the bus state logic
must be enabled and the system frequency must be 4x the SCL frequency.
Bits 1:0 – BUSSTATE[1:0] Bus State
These bits indicate the current TWI bus state as defined in the table below. After a System Reset or re-enabling, the
TWI master bus state will be unknown. The change of bus state is dependent on bus activity.
Writing 0x1 to the BUSSTATE bits forces the bus state logic into its Idle state. However, the bus state logic cannot be
forced into any other state. When the master is disabled, the bus state is 'unknown'.
Value
Name
Description
0x0
UNKNOWN
Unknown bus state
0x1
IDLE
Bus is idle
0x2
OWNER
This TWI controls the bus
0x3
BUSY
The bus is busy
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 341
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.6
Master Baud Rate
Name:
Offset:
Reset:
Property:
Bit
7
MBAUD
0x06
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BAUD[7:0] Baud Rate
This bit field is used to derive the SCL high and low time and should be written while the master is disabled (ENABLE
bit in TWIn.MCTRLA is '0').
For more information on how to calculate the frequency, see 26.3.4.2.1 Clock Generation.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 342
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.7
Master Address
Name:
Offset:
Reset:
Property:
Bit
7
MADDR
0x07
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADDR[7:0] Address
When this bit field is written, a Start condition and slave address protocol sequence is initiated dependent on the bus
state.
If the bus state is unknown the Master Write Interrupt Flag (WIF) and Bus Error flag (BUSERR) in the Master Status
register (TWIn.MSTATUS) are set and the operation is terminated.
If the bus is busy the master awaits further operation until the bus becomes idle. When the bus is or becomes idle,
the master generates a Start condition on the bus, copies the ADDR value into the Data Shift register (TWIn.MDATA)
and performs a byte transmit operation by sending the contents of the Data register onto the bus. The master then
receives the response (i.e., the Acknowledge bit from the slave). After completing the operation the bus clock (SCL)
is forced and held low only if arbitration was not lost. The CLKHOLD bit in the Master Setup register (TWIn.MSETUP)
is set accordingly. Completing the operation sets the WIF in the Master Status register (TWIn.MSTATUS).
If the bus is already owned, a repeated Start (Sr) sequence is performed. In two ways the repeated Start (Sr)
sequence deviates from the Start sequence. Firstly, since the bus is already owned by the master, no wait for idle bus
state is necessary. Secondly, if the previous transaction was a read, the acknowledge action is sent before the
Repeated Start bus condition is issued on the bus.
The master receives one data byte from the slave before the master sets the Master Read Interrupt Flag (RIF) in the
Master Status register (TWIn.MSTATUS). All TWI Master flags are cleared automatically when this bit field is written.
This includes bus error, arbitration lost, and both master interrupt flags.
This register can be read at any time without interfering with ongoing bus activity, since a read access does not
trigger the master logic to perform any bus protocol related operations.
The master control logic uses bit 0 of the TWIn.MADDR register as the bus protocol’s Read/Write flag (R/W).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 343
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.8
Master DATA
Name:
Offset:
Reset:
Property:
Bit
7
MDATA
0x08
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Data
The bit field gives direct access to the master's physical Shift register which is used both to shift data out onto the bus
(write) and to shift in data received from the bus (read).
The direct access implies that the Data register cannot be accessed during byte transmissions. Built-in logic prevents
any write access to this register during the shift operations. Reading valid data or writing data to be transmitted can
only be successfully done when the bus clock (SCL) is held low by the master (i.e., when the CLKHOLD bit in the
Master Status register (TWIn.MSTATUS) is set). However, it is not necessary to check the CLKHOLD bit in software
before accessing this register if the software keeps track of the present protocol state by using interrupts or observing
the interrupt flags.
Accessing this register assumes that the master clock hold is active, auto-triggers bus operations dependent of the
state of the Acknowledge Action Command bit (ACKACT) in TWIn.MSTATUS and type of register access (read or
write).
A write access to this register will, independent of ACKACT in TWIn.MSTATUS, command the master to perform a
byte transmit operation on the bus directly followed by receiving the Acknowledge bit from the slave. When the
Acknowledge bit is received, the Master Write Interrupt Flag (WIF) in TWIn.MSTATUS is set regardless of any bus
errors or arbitration. If operating in a multi-master environment, the interrupt handler or application software must
check the Arbitration Lost Status Flag (ARBLOST) in TWIn.MSTATUS before continuing from this point. If the
arbitration was lost, the application software must decide to either abort or to resend the packet by rewriting this
register. The entire operation is performed (i.e., all bits are clocked), regardless of winning or losing arbitration before
the write interrupt flag is set. When arbitration is lost, only '1's are transmitted for the remainder of the operation,
followed by a write interrupt with ARBLOST flag set.
Both TWI Master Interrupt Flags are cleared automatically when this register is written. However, the Master
Arbitration Lost and Bus Error flags are left unchanged.
Reading this register triggers a bus operation, dependent on the setting of the Acknowledge Action Command bit
(ACKACT) in TWIn.MSTATUS. Normally the ACKACT bit is preset to either ACK or NACK before the register read
operation. If ACK or NACK action is selected, the transmission of the acknowledge bit precedes the release of the
clock hold. The clock is released for one byte, allowing the slave to put one byte of data on the bus. The Master Read
Interrupt flag RIF in TWIn.MSTATUS is then set if the procedure was successfully executed. However, if arbitration
was lost when sending NACK, or a bus error occurred during the time of operation, the Master Write Interrupt flag
(WIF) is set instead. Observe that the two Master Interrupt Flags are mutually exclusive (i.e., both flags will not be set
simultaneously).
Both TWI Master Interrupt Flags are cleared automatically if this register is read while ACKACT is set to either ACK
or NACK. However, arbitration lost and bus error flags are left unchanged.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 344
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.9
Slave Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
DIEN
R/W
0
SCTRLA
0x09
0x00
-
6
APIEN
R/W
0
5
PIEN
R/W
0
4
3
2
PMEN
R/W
0
1
SMEN
R/W
0
0
ENABLE
R/W
0
Bit 7 – DIEN Data Interrupt Enable
Writing this bit to '1' enables interrupt on the Slave Data Interrupt Flag (DIF) in the Slave Status register
(TWIn.SSTATUS). A TWI slave data interrupt will be generated only if this bit, the DIF, and the Global Interrupt Flag
(I) in CPU.SREG are all '1'.
Bit 6 – APIEN Address or Stop Interrupt Enable
Writing this bit to '1' enables interrupt on the Slave Address or Stop Interrupt Flag (APIF) in the Slave Status register
(TWIn.SSTATUS). A TWI slave address or stop interrupt will be generated only if the this bit, APIF, PIEN in this
register, and the Global Interrupt Flag (I) in CPU.SREG are all '1'.
The slave stop interrupt shares the interrupt vector with the slave address interrupt. The AP bit determines what
caused the interrupt.
Bit 5 – PIEN Stop Interrupt Enable
Writing this bit to '1' enables APIF to be set when a Stop condition occurs. To use this feature the system frequency
must be 4x the SCL frequency.
Bit 2 – PMEN Address Recognition Mode
If this bit is written to '1', the slave address match logic responds to all received addresses.
If this bit is written to '0', the address match logic uses the Slave Address register (TWIn.SADDR) to determine which
address to recognize as the slaves own address.
Bit 1 – SMEN Smart Mode Enable
Writing this bit to '1' enables the slave Smart mode. When the Smart mode is enabled, issuing a command with CMD
or reading/writing DATA resets the interrupt and operation continues. If the Smart mode is disabled, the slave always
waits for a CMD command before continuing.
Bit 0 – ENABLE Enable TWI Slave
Writing this bit to '1' enables the TWI slave.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 345
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.10 Slave Control B
Name:
Offset:
Reset:
Property:
Bit
SCTRLB
0x0A
0x00
-
7
6
5
4
3
Access
Reset
2
ACKACT
R/W
0
1
0
SCMD[1:0]
R/W
0
R/W
0
Bit 2 – ACKACT Acknowledge Action
This bit defines the slave’s behavior under certain conditions defined by the bus protocol state and software
interaction. The table below lists the acknowledge procedure performed by the slave if action is initiated by software.
The acknowledge action is performed when TWIn.SDATA is read or written, or when an execute command is written
to the CMD bits in this register.
The ACKACT bit is not a flag or strobe, but an ordinary read/write accessible register bit.
Value
Name
Description
0
ACK
Send ACK
1
NACK
Send NACK
Bits 1:0 – SCMD[1:0] Command
Unlike the acknowledge action bits, the Slave command bits are strobes. These bits always read as zero. Writing to
these bits trigger a slave operation as defined in the table below.
Table 26-5. Command Settings
SCMD[1:0]
DIR Description
0x0
X
NOACT - No action
0x1
X
Reserved
0x2 - COMPTRANS
Used to complete a transaction.
0x3 - RESPONSE
0
Execute Acknowledge Action succeeded by waiting for any Start (S/Sr) condition.
1
Wait for any Start (S/Sr) condition.
Used in response to an address interrupt (APIF).
0
Execute Acknowledge Action succeeded by reception of next byte.
1
Execute Acknowledge Action succeeded by slave data interrupt.
Used in response to a data interrupt (DIF).
0
Execute Acknowledge Action succeeded by reception of next byte.
1
Execute a byte read operation followed by Acknowledge Action.
The acknowledge action bits and command bits can be written at the same time.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 346
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.11 Slave Status
Name:
Offset:
Reset:
Property:
SSTATUS
0x0B
0x00
-
Normal TWI operation dictates that the Slave Status register should be regarded purely as a read-only register.
Clearing any of the status flags will indirectly be done when accessing the Slave Data (TWIn.SDATA) register or the
CMD bits in the Slave Control B register (TWIn.SCTRLB).
Bit
Access
Reset
7
DIF
R/W
0
6
APIF
R/W
0
5
CLKHOLD
R
0
4
RXACK
R
0
3
COLL
R/W
0
2
BUSERR
R/W
0
1
DIR
R
0
0
AP
R
0
Bit 7 – DIF Data Interrupt Flag
This flag is set when a slave byte transmit or byte receive operation is successfully completed without any bus error.
The flag can be set with an unsuccessful transaction in case of collision detection (see the description of the COLL
Status bit). Writing a '1' to its bit location will clear the DIF. However, normal use of the TWI does not require the DIF
flag to be cleared by using this method, since the flag is automatically cleared when:
1. Writing to the Slave DATA register.
2. Reading the Slave DATA register.
3. Writing a valid command to the CTRLB register.
The DIF flag can be used to generate a slave data interrupt (see the description of the DIEN control bit in
TWIn.CTRLA).
Bit 6 – APIF Address or Stop Interrupt Flag
This flag is set when the slave address match logic detects that a valid address has been received or by a Stop
condition. Writing a '1' to its bit location will clear the APIF. However, normal use of the TWI does not require the flag
to be cleared by this method since the flag is cleared using the same software interactions as described for the DIF
flag.
The APIF flag can be used to generate a slave address or stop interrupt (see the description of the AIEN control bit in
TWIn.CTRLA). Take special note of that the slave stop interrupt shares the interrupt vector with slave address
interrupt.
Bit 5 – CLKHOLD Clock Hold
If read as '1', the slave clock hold flag indicates that the slave is currently holding the TWI clock (SCL) low, stretching
the TWI clock period. This is a read-only bit that is set when an address or data interrupt is set. Resetting the
corresponding interrupt will indirectly reset this flag.
Bit 4 – RXACK Received Acknowledge
This bit is read-only and contains the most recently received Acknowledge bit from the master.
Bit 3 – COLL Collision
If read as '1', the transmit collision flag indicates that the slave has not been able to transmit a high data or NACK bit.
If a slave transmit collision is detected, the slave will commence its operation as normal, except no low values will be
shifted out onto the SDA line (i.e., when the COLL flag is set to '1' it disables the data and acknowledge output from
the slave logic). The DIF flag will be set to '1' at the end as a result of the internal completion of an unsuccessful
transaction. Similarly, when a collision occurs because the slave has not been able to transmit NACK bit, it means the
address match already happened and APIF flag is set as a result. APIF/DIF flags can only generate interrupt whose
handlers can be used to check for the collision. Writing a '1' to its bit location will clear the COLL flag. However, the
flag is automatically cleared if any Start condition (S/Sr) is detected.
This flag is intended for systems where address resolution protocol (ARP) is employed. However, a detected collision
in non-ARP situations indicates that there has been a protocol violation and should be treated as a bus error.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 347
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
Bit 2 – BUSERR Bus Error
The BUSERR flag indicates that an illegal bus condition has occurred. An illegal bus condition is detected if a
protocol violating Start (S), Repeated Start (Sr), or Stop (P) is detected on the TWI bus lines. A Start condition
directly followed by a Stop condition is one example of protocol violation. Writing a '1' to its bit location will clear the
BUSERR flag. However, normal use of the TWI does not require the BUSERR to be cleared by this method. A robust
TWI driver software design will assume that the entire packet of data has been corrupted and restart by waiting for a
new Start condition (S). The TWI bus error detector is part of the TWI Master circuitry. For bus errors to be detected,
the TWI Master must be enabled (ENABLE bit in TWIn.MCTRLA is '1'), and the system clock frequency must be at
least four times the SCL frequency.
Bit 1 – DIR Read/Write Direction
This bit is read-only and indicates the current bus direction state. The DIR bit reflects the direction bit value from the
last address packet received from a master TWI device. If this bit is read as '1', a master read operation is in
progress. Consequently, a '0' indicates that a master write operation is in progress.
Bit 0 – AP Address or Stop
When the TWI slave address or Stop Interrupt Flag (APIF) is set, this bit determines whether the interrupt is due to
address detection or a Stop condition.
Value
Name
Description
0
STOP
A Stop condition generated the interrupt on APIF
1
ADR
Address detection generated the interrupt on APIF
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 348
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.12 Slave Address
Name:
Offset:
Reset:
Property:
Bit
7
SADDR
0x0C
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADDR[7:0] Address
The Slave Address register in combination with the Slave Address Mask register (TWIn.SADDRMASK) is used by the
slave address match logic to determine if a master TWI device has addressed the TWI slave. The Slave Address
Interrupt Flag (APIF) is set to 1 if the received address is recognized. The slave address match logic supports
recognition of 7- and 10-bits addresses, and general call address.
When using 7-bit or 10-bit Address Recognition mode, the upper seven bits of the Address register (ADDR[7:1])
represents the slave address and the Least Significant bit (ADDR[0]) is used for general call address recognition.
Setting the ADDR[0] bit, in this case, enables the general call address recognition logic. The TWI slave address
match logic only supports recognition of the first byte of a 10-bit address (i.e., by setting ADDRA[7:1] = “0b11110aa”
where “aa” represents bit 9 and 8, or the slave address). The second 10-bit address byte must be handled by
software.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 349
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.13 Slave Data
Name:
Offset:
Reset:
Property:
Bit
7
SDATA
0x0D
0x00
-
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – DATA[7:0] Data
The Slave Data register I/O location (DATA) provides direct access to the slave's physical Shift register, which is used
both to shift data out onto the bus (transmit) and to shift in data received from the bus (receive). The direct access
implies that the Data register cannot be accessed during byte transmissions. Built-in logic prevents any write
accesses to the Data register during the shift operations. Reading valid data or writing data to be transmitted can only
be successfully done when the bus clock (SCL) is held low by the slave (i.e., when the slave CLKHOLD bit is set).
However, it is not necessary to check the CLKHOLD bit in software before accessing the slave DATA register if the
software keeps track of the present protocol state by using interrupts or observing the interrupt flags. Accessing the
slave DATA register, assumed that clock hold is active, auto-trigger bus operations dependent of the state of the
Slave Acknowledge Action Command bits (ACKACT) and type of register access (read or write).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 350
ATtiny202/204/402/404/406 Automotiv...
Two-Wire Interface (TWI)
26.5.14 Slave Address Mask
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
SADDRMASK
0x0E
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
ADDRMASK[6:0]
R/W
0
3
2
1
R/W
0
R/W
0
R/W
0
0
ADDREN
R/W
0
Bits 7:1 – ADDRMASK[6:0] Address Mask
The ADDRMASK register acts as a second address match register, or an address mask register depending on the
ADDREN setting.
If ADDREN is written to '0', ADDRMASK can be loaded with a 7-bit Slave Address mask. Each of the bits in the
TWIn.SADDRMASK register can mask (disable) the corresponding address bits in the TWI slave Address Register
(TWIn.SADDR). If the mask bit is written to '1' then the address match logic ignores the compare between the
incoming address bit and the corresponding bit in slave TWIn.SADDR register. In other words, masked bits will
always match.
If ADDREN is written to '1', the TWIn.SADDRMASK can be loaded with a second slave address in addition to the
TWIn.SADDR register. In this mode, the slave will match on two unique addresses, one in TWIn.SADDR and the
other in TWIn.SADDRMASK.
Bit 0 – ADDREN Address Mask Enable
If this bit is written to '1', the slave address match logic responds to the two unique addresses in slave TWIn.SADDR
and TWIn.SADDRMASK.
If this bit is '0', the TWIn.SADDRMASK register acts as a mask to the TWIn.SADDR register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 351
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
27.
Cyclic Redundancy Check Memory Scan (CRCSCAN)
27.1
Features
•
•
•
•
•
•
27.2
CRC-16-CCITT
Can Check Full Flash, Application Code and/or Boot Section
Priority Check Mode
Selectable NMI Trigger on Failure
User Configurable Check During Internal Reset Initialization
Paused in all CPU Sleep Modes
Overview
A Cyclic Redundancy Check (CRC) takes a data stream of bytes from the NVM (either entire Flash, only Boot
section, or both application code and Boot section) and generates a checksum. The CRC peripheral (CRCSCAN) can
be used to detect errors in program memory.
The last location in the section to check has to contain the correct pre-calculated checksum for comparison. If the
checksum calculated by the CRCSCAN and the pre-calculated checksums match, a Status bit in the CRCSCAN is
set. If they do not match, the Status register will indicate that it failed. The user can choose to let the CRCSCAN
generate a Non-Maskable Interrupt (NMI) if the checksums do not match.
An n-bit CRC, applied to a data block of arbitrary length, will detect any single alteration (error burst) up to n bits in
length. For longer error bursts, a fraction 1-2-n will be detected.
The CRC-generator supports CRC-16-CCITT.
Polynomial:
•
CRC-16-CCITT: x16 + x12 + x5 + 1
The CRC reads in byte-by-byte of the content of the section(s) it is set up to check, starting with byte 0, and
generates a new checksum per byte. The byte is sent through an implementation corresponding to Figure 27-1,
starting with the Most Significant bit. If the last two bytes in the section contain the correct checksum, the CRC will
pass. See 27.3.2.1 Checksum for how to place the checksum. The initial value of the Checksum register is 0xFFFF.
Figure 27-1. CRC Implementation Description
data
15
x14
x13
x12
x11
x10
x9
x8
x7
x6
x5
x4
x3
x2
x1
x0
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
Q D
x
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 352
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
27.2.1
Block Diagram
Figure 27-2. Cyclic Redundancy Check Block Diagram
CTRLA
Enable, Reset
Memory
(Boot, App., Flash)
CTRLB
Mode, Source
BUSY
CRC-16-CCIT
CHECKSUM
STATUS
CRC OK
Non-Maskable
Interrupt
27.2.2
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 27-1. System Product Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
No
-
Interrupts
Yes
CPUINT
Events
No
-
Debug
Yes
UPDI
Related Links
12.2.2.1 Clocks
27.2.2.3 Interrupts
27.2.2.1 Clocks
This peripheral depends on the peripheral clock.
Related Links
11. Clock Controller (CLKCTRL)
27.2.2.2 I/O Lines and Connections
Not applicable.
27.2.2.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
27.3.3 Interrupts
27.2.2.4 Events
Not applicable.
27.2.2.5 Debug Operation
Whenever the debugger accesses the device, for instance, reading or writing a peripheral or memory location, the
CRCSCAN peripheral will be disabled.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 353
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
If the CRCSCAN is busy when the debugger accesses the device, the CRCSCAN will restart the ongoing operation
when the debugger accesses an internal register or when the debugger disconnects.
The BUSY bit in the Status register (CRCSCAN.STATUS) will read '1' if the CRCSCAN was busy when the debugger
caused it to disable, but it will not actively check any section as long as the debugger keeps it disabled. There are
synchronized CRC Status bits in the debugger's internal register space, which can be read by the debugger without
disabling the CRCSCAN. Reading the debugger's internal CRC status bits will make sure that the CRCSCAN is
enabled.
It is possible to write the CRCSCAN.STATUS register directly from the debugger:
• BUSY bit in CRCSCAN.STATUS:
– Writing the BUSY bit to '0' will stop the ongoing CRC operation (so that the CRCSCAN does not restart its
operation when the debugger allows it).
– Writing the BUSY bit to '1' will make the CRC start a single check with the settings in the Control B register
(CRCSCAN.CTRLB), but not until the debugger allows it.
•
As long as the BUSY bit in CRCSCAN.STATUS is '1', CRCSCAN.CRCTRLB and the Non-Maskable Interrupt
Enable bit (NMIEN) in the Control A register (CRCSCAN.CTRLA) cannot be altered.
OK bit in CRCSCAN.STATUS:
– Writing the OK bit to '0' can trigger a Non-Maskable Interrupt (NMI) if the NMIEN bit in CRCSCAN.CTRLA
is '1'. If an NMI has been triggered, no writes to the CRCSCAN are allowed.
– Writing the OK bit to '1' will make the OK bit read as '1' when the BUSY bit in CRCSCAN.STATUS is '0'.
Writes to CRCSCAN.CTRLA and CRCSCAN.CTRLB from the debugger are treated in the same way as writes from
the CPU.
Related Links
31. Unified Program and Debug Interface (UPDI)
27.5.1 CTRLA
27.5.2 CTRLB
27.3
Functional Description
27.3.1
Initialization
To enable a CRC in software (or via the debugger):
1. Write the Source (SRC) bit field of the Control B register (CRCSCAN.CTRLB) to select the desired source
settings. Ensure that the MODE bit field in CRCSCAN.CTRLB is 0x0.
2. Enable the CRCSCAN by writing a '1' to the ENABLE bit in the Control A register (CRCSCAN.CTRLA).
3. The CRC will start after three cycles, and the CPU will continue executing during these three cycles.
The CRCSCAN can be enabled during the internal Reset initialization to ensure the Flash is OK before letting the
CPU execute code. If the CRCSCAN fails during the internal Reset initialization, the CPU is not allowed to start
normal code execution - the device remains in Reset state instead of executing code with unexpected behavior. The
full source settings are available during the internal Reset initialization. See the Fuse description for more
information.
If the CRCSCAN was enabled during the internal Reset initialization, the CRC Control A and B registers will reflect
this when normal code execution is started:
• The ENABLE bit in CRCSCAN.CTRLA will be '1'
• The MODE bit field in CRCSCAN.CTRLB will be non-zero
• The SRC bit field in CRCSCAN.CTRLB will reflect the checked section(s).
The CRCSCAN can be enabled during Reset by configuring the CRCSRC fuse in FUSE.SYSCFG0.
Related Links
27.5.1 CTRLA
27.5.2 CTRLB
7.10 Configuration and User Fuses (FUSE)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 354
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
13.3.2.2 Reset Time
27.3.2
Operation
The CRC is operating in Priority mode: the CRC peripheral has priority access to the Flash and will stall the CPU until
completed.
In Priority mode, the CRC fetches a new word (16-bit) on every third main clock cycle, or when the CRC peripheral is
configured to do a scan from start-up.
27.3.2.1 Checksum
The pre-calculated checksum must be present in the last location of the section to be checked. If the BOOT section
should be checked, the 16-bit checksum must be saved in the last two bytes of the BOOT section, and similarly for
APPLICATION and entire Flash. Table 27-2 shows explicitly how the checksum should be stored for the different
sections. Also, see the CRCSCAN.CTRLB register description for how to configure which section to check and the
device fuse description for how to configure the BOOTEND and APPEND fuses.
Table 27-2. How to Place the Pre-Calculated 16-Bit Checksum in Flash
27.3.3
Section to Check
CHECKSUM[15:8]
CHECKSUM[7:0]
BOOT
FUSE_BOOTEND*256-2
FUSE_BOOTEND*256-1
BOOT and APPLICATION
FUSE_APPEND*256-2
FUSE_APPEND*256-1
Full Flash
FLASHEND-1
FLASHEND
Interrupts
Table 27-3. Available Interrupt Vectors and Sources
Offset
Name
Vector Description
Conditions
0x00
NMI
Non-Maskable Interrupt
Generated on CRC failure
When the interrupt condition occurs, the OK flag in the Status register (CRCSCAN.STATUS) is cleared to '0'.
An interrupt is enabled by writing a '1' to the respective Enable bit (NMIEN) in the Control A register
(CRCSCAN.CTRLA), but can only be disabled with a system Reset. An NMI is generated when the OK flag in
CRCSCAN.STATUS is cleared and the NMIEN bit is '1'. The NMI request remains active until a system Reset, and
cannot be disabled.
A non-maskable interrupt can be triggered even if interrupts are not globally enabled.
Related Links
27.5.1 CTRLA
27.5.3 STATUS
14. CPU Interrupt Controller (CPUINT)
27.3.4
Sleep Mode Operation
CRCSCAN is halted in all sleep modes. In all CPU Sleep modes, the CRCSCAN peripheral is halted and will resume
operation when the CPU wakes up.
The CRCSCAN starts operation three cycles after writing the EN bit in CRCSCAN.CTRLA. During these three cycles,
it is possible to enter Sleep mode. In this case:
1. The CRCSCAN will not start until the CPU is woken up.
2. Any interrupt handler will execute after CRCSCAN has finished.
27.3.5
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 355
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
27.4
Register Summary - CRCSCAN
Offset
Name
Bit Pos.
0x00
0x01
0x02
CTRLA
CTRLB
STATUS
7:0
7:0
7:0
27.5
RESET
MODE[1:0]
NMIEN
ENABLE
SRC[1:0]
OK
BUSY
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 356
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
27.5.1
Control A
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x00
-
If an NMI has been triggered, this register is not writable.
Bit
Access
Reset
7
RESET
R/W
0
6
5
4
3
2
1
NMIEN
R/W
0
0
ENABLE
R/W
0
Bit 7 – RESET Reset CRCSCAN
Writing this bit to '1' resets the CRCSCAN peripheral: The CRCSCAN Control registers and STATUS register
(CTRLA, CTRLB, STATUS) will be cleared one clock cycle after the RESET bit was written to '1'.
If NMIEN is '0', this bit is writable both when the CRCSCAN is busy (the BUSY bit in CRCSCAN.STATUS is '1') and
not busy (the BUSY bit is '0'), and will take effect immediately.
If NMIEN is '1', this bit is only writable when the CRCSCAN is not busy (the BUSY bit in CRCSCAN.STATUS is '0').
The RESET bit is a strobe bit.
Bit 1 – NMIEN Enable NMI Trigger
When this bit is written to '1', any CRC failure will trigger an NMI.
This can only be cleared by a system Reset - it is not cleared by a write to the RESET bit.
This bit can only be written to '1' when the CRCSCAN is not busy (the BUSY bit in CRCSCAN.STATUS is '0').
Bit 0 – ENABLE Enable CRCSCAN
Writing this bit to '1' enables the CRCSCAN peripheral with the current settings. It will stay '1' even after a CRC check
has completed, but writing it to ‘1’ again will start a new check.
Writing the bit to '0' will disable the CRCSCAN after the ongoing check is completed (after reaching the end of the
section it is set up to check). A failure in the ongoing check will still be detected and can cause an NMI if the NMIEN
bit is '1'.
The CRCSCAN can be enabled during the internal Reset initialization to verify Flash sections before letting the CPU
start normal code execution (see device data sheet fuse description). If the CRCSCAN is enabled during the internal
Reset initialization, the ENABLE bit will read as '1' when normal code execution starts.
To see whether the CRCSCAN peripheral is busy with an ongoing check, poll the Busy bit (BUSY) in the STATUS
register (CRCSCAN.STATUS).
Related Links
7.10 Configuration and User Fuses (FUSE)
13.3.2.2 Reset Time
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 357
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
27.5.2
Control B
Name:
Offset:
Reset:
Property:
CTRLB
0x01
0x00
-
The CTRLB register contains the mode and source settings for the CRC. It is not writable when the CRC is busy or
when an NMI has been triggered.
Bit
7
6
5
4
3
2
1
MODE[1:0]
Access
Reset
R/W
0
0
SRC[1:0]
R/W
0
R/W
0
R/W
0
Bits 5:4 – MODE[1:0] CRC Flash Access Mode
The CRC can be enabled during internal Reset initialization to verify Flash sections before letting the CPU start (see
the device data sheet fuse description). If the CRC is enabled during internal Reset initialization, the MODE bit field
will read out non-zero when normal code execution starts. To ensure proper operation of the CRC under code
execution, write the MODE bit to 0x0 again.
Value
Name
Description
0x0
PRIORITY The CRC module runs a single check with priority to Flash. The CPU is halted until the
CRC completes.
other
Reserved
Bits 1:0 – SRC[1:0] CRC Source
The SRC bit field selects which section of the Flash the CRC module should check. To set up section sizes, refer to
the fuse description.
The CRC can be enabled during internal Reset initialization to verify Flash sections before letting the CPU start (see
fuse description). If the CRC is enabled during internal Reset initialization, the SRC bit field will read out as FLASH,
BOOTAPP, or BOOT when normal code execution starts (depending on the configuration).
Value
Name
Description
0x0
FLASH
The CRC is performed on the entire Flash (boot, application code, and application data
sections).
0x1
BOOTAPP The CRC is performed on the boot and application code sections of Flash.
0x2
BOOT
The CRC is performed on the boot section of Flash.
0x3
Reserved.
Related Links
7.10 Configuration and User Fuses (FUSE)
13.3.2.2 Reset Time
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 358
ATtiny202/204/402/404/406 Automotiv...
Cyclic Redundancy Check Memory Scan (CRCSCAN...
27.5.3
Status
Name:
Offset:
Reset:
Property:
STATUS
0x02
0x02
-
The STATUS register contains the busy and OK information. It is not writable, only readable.
Bit
7
6
5
4
3
Access
Reset
2
1
OK
R
1
0
BUSY
R
0
Bit 1 – OK CRC OK
When this bit is read as 1, the previous CRC completed successfully. The bit is set to '1' from Reset but is cleared to
'0' when enabling. As long as the CRC module is busy, it will be read '0'. When running continuously, the CRC status
must be assumed OK until it fails or is stopped by the user.
Bit 0 – BUSY CRC Busy
When this bit is read as 1, the CRC module is busy. As long as the module is busy, the access to the control registers
is limited.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 359
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.
Configurable Custom Logic (CCL)
28.1
Features
•
•
•
•
•
•
•
•
28.2
Glue Logic for General Purpose PCB Design
Up to two Programmable Look-Up Tables LUT[1:0]
Combinatorial Logic Functions: Any Logic Expression That is a Function of up to Three Inputs.
Sequential Logic Functions:
Gated D Flip-Flop, JK Flip-Flop, gated D Latch, RS Latch
Flexible Look-Up Table Inputs Selection:
– I/Os
– Events
– Subsequent LUT output
– Internal peripherals
• Analog comparator
• Timer/counters
• USART
• SPI
Clocked by System Clock or Other Peripherals
Output Can be Connected to I/O pins or Event System
Optional Synchronizer, Filter, or Edge Detector Available on Each LUT Output
Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device
pins, to events, or to other internal peripherals. The CCL can serve as "glue logic" between the device peripherals
and external devices. The CCL can eliminate the need for external logic components, and can also help the designer
to overcome real-time constraints by combining core independent peripherals to handle the most time-critical parts of
the application independent of the CPU.
The CCL peripheral has one pair of Look-Up Tables (LUT). Each LUT consists of three inputs, a truth table, and a
filter/edge detector. Each LUT can generate an output as a user programmable logic expression with three inputs.
Inputs can be individually masked.
The output can be generated from the inputs combinatorially and can be filtered to remove spikes. An optional
sequential module can be enabled. The inputs to the sequential module are individually controlled by two
independent, adjacent LUT (LUT0/LUT1) outputs, enabling complex waveform generation.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 360
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.2.1
Block Diagram
Figure 28-1. Configurable Custom Logic
LUT0
INSEL
Internal
Events
I/O
Peripherals
FILTSEL
TRUTH
Filter/
Synch
CLKSRC
EDGEDET
Edge
Detector
LUT0-OUT
CLK_MUX_OUT
LUT0-IN[2]
clkCCL
SEQSEL
Sequential
ENABLE
LUT1
INSEL
Internal
Events
I/O
Peripherals
FILTSEL
TRUTH
Filter/
Synch
CLKSRC
LUT1-IN[2]
clkCCL
EDGEDET
Edge
Detector
LUT1-OUT
CLK_MUX_OUT
ENABLE
28.2.2
Signal Description
Pin Name
Type
Description
LUTn-OUT
Digital output
Output from look-up table
LUTn-IN[2:0]
Digital input
Input to look-up table
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped to several pins.
Related Links
5. I/O Multiplexing and Considerations
28.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 28-1. CCL System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
28.2.3.1 Clocks
By default, the CCL is using the peripheral clock of the device (CLK_PER).
Alternatively, the CCL can be clocked by a peripheral input that is available on LUT n input line 2 (LUTn_IN[2]). This
is configured by writing a '1' to the Clock Source Selection bit (CLKSRC) in the LUTn Control A register
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 361
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
(CCL.LUTnCTRLA). The sequential block is clocked by the same clock as that of the even LUT in the LUT pair
(SEQn.clk = LUT2n.clk). It is advised to disable the peripheral by writing a '0' to the Enable bit (ENABLE) in the
Control A register (CCL.CTRLA) before configuring the CLKSRC bit in CCL.LUTnCTRLA.
Alternatively, the input line 2 (IN[2]) of an LUT can be used to clock the LUT and the corresponding Sequential block.
This is enabled by writing a '1' to the Clock Source Selection bit (CLKSRC) in the LUTn Control A register
(CCL.LUTnCTRLA).
The CCL must be disabled before changing the LUT clock source: write a '0' to the Enable bit (ENABLE) in Control A
register (CCL.CTRLA).
Related Links
11. Clock Controller (CLKCTRL)
28.2.3.2 I/O Lines
The CCL can take inputs and generate output through I/O pins. For this to function properly, the I/O pins must be
configured to be used by a Look Up Table (LUT).
Related Links
17. I/O Pin Configuration (PORT)
28.2.3.3 Interrupts
Not applicable.
28.2.3.4 Events
The CCL can use events from other peripherals and generate events that can be used by other peripherals. For this
feature to function, the events have to be configured properly. Refer to the Related Links below for more information
about the event users and event generators.
28.2.3.5 Debug Operation
When the CPU is halted in Debug mode the CCL continues normal operation. However, the CCL cannot be halted
when the CPU is halted in Debug mode. If the CCL is configured in a way that requires it to be periodically serviced
by the CPU, improper operation or data loss may result during debugging.
28.3
Functional Description
28.3.1
Initialization
The following bits are enable-protected, meaning that they can only be written when the corresponding even LUT is
disabled (ENABLE=0 in CCL.LUT0CTRLA):
•
Sequential Selection (SEQSEL) in Sequential Control 0 register (CCL.SEQCTRL0)
The following registers are enable-protected, meaning that they can only be written when the corresponding LUT is
disabled (ENABLE=0 in CCL.LUT0CTRLA):
•
LUT n Control x register, except ENABLE bit (CCL.LUTnCTRLx)
Enable-protected bits in the CCL.LUTnCTRLx registers can be written at the same time as ENABLE in
CCL.LUTnCTRLx is written to '1', but not at the same time as ENABLE is written to '0'.
Enable-protection is denoted by the Enable-Protected property in the register description.
28.3.2
Operation
28.3.2.1 Enabling, Disabling, and Resetting
The CCL is enabled by writing a '1' to the ENABLE bit in the Control register (CCL.CTRLA). The CCL is disabled by
writing a '0' to that ENABLE bit.
Each LUT is enabled by writing a '1' to the LUT Enable bit (ENABLE) in the LUT n Control A register
(CCL.LUTnCTRLA). Each LUT is disabled by writing a '0' to the ENABLE bit in CCL.LUTnCTRLA.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 362
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.3.2.2 Look-Up Table Logic
The look-up table in each LUT unit can generate a combinational logic output as a function of up to three inputs
IN[2:0]. Unused inputs can be masked (tied low). The truth table for the combinational logic expression is defined by
the bits in the CCL.TRUTHn registers. Each combination of the input bits (IN[2:0]) corresponds to one bit in the
TRUTHn register, as shown in the table below.
Table 28-2. Truth Table of LUT
IN[2]
IN[1]
IN[0]
OUT
0
0
0
TRUTH[0]
0
0
1
TRUTH[1]
0
1
0
TRUTH[2]
0
1
1
TRUTH[3]
1
0
0
TRUTH[4]
1
0
1
TRUTH[5]
1
1
0
TRUTH[6]
1
1
1
TRUTH[7]
28.3.2.3 Truth Table Inputs Selection
Input Overview
The inputs can be individually:
•
•
•
•
Masked
Driven by peripherals:
– Analog comparator output (AC)
– Timer/Counters waveform outputs (TC)
Driven by internal events from Event System
Driven by other CCL sub-modules
The Input Selection for each input y of LUT n is configured by writing the Input y Source Selection bit in the LUT n
Control x=[B,C] registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC
Internal Feedback Inputs (FEEDBACK)
When selected (INSELy=FEEDBACK in CCL.LUTnCTRLx), the Sequential (SEQ) output is used as input for the
corresponding LUT.
The output from an internal sequential module can be used as input source for the LUT, see the figure below for an
example for LUT0 and LUT1. The sequential selection for each LUT follows the formula:
IN 2N � = SEQ �
IN 2N+1 � = SEQ �
With N representing the sequencer number and i=0,1 representing the LUT input index.
For details, refer to 28.3.2.6 Sequential Logic.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 363
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
Figure 28-2. Feedback Input Selection
Linked LUT (LINK)
When selecting the LINK input option, the next LUT's direct output is used as the LUT input. In general, LUT[n+1] is
linked to the input of LUT[n]. As example, LUT1 is the input for LUT0.
Figure 28-3. Linked LUT Input Selection
LUT0
SEQ 0
CTRL
(ENABLE)
LUT1
Internal Events Inputs Selection (EVENT)
Asynchronous events from the Event System can be used as input to the LUT. Two event input lines (EVENT0 and
EVENT1) are available, and can be selected as LUT input. Before selecting the EVENT input option by writing to the
LUT CONTROL A or B register (CCL.LUTnCTRLB or LUTnCTRLC), the Event System must be configured.
I/O Pin Inputs (I/O)
When selecting the I/O option, the LUT input will be connected to its corresponding I/O pin. Refer to the I/O
Multiplexing section for more details about where the LUTnINy is located.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 364
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
Figure 28-4. I/O Pin Input Selection
Peripherals
The different peripherals on the three input lines of each LUT are selected by writing to the respective LUT n Input y
bit fields in the LUT n Control B and C registers:
• INSEL0 in CCL.LUTnCTRLB
• INSEL1 in CCL.LUTnCTRLB
• INSEL2 in CCL.LUTnCTRLC
Related Links
5. I/O Multiplexing and Considerations
17. I/O Pin Configuration (PORT)
11. Clock Controller (CLKCTRL)
29. Analog Comparator (AC)
21. 16-bit Timer/Counter Type A (TCA)
24. Universal Synchronous and Asynchronous Receiver and Transmitter (USART)
25. Serial Peripheral Interface (SPI)
26. Two-Wire Interface (TWI)
5. I/O Multiplexing and Considerations
28.3.2.4 Filter
By default, the LUT output is a combinational function of the LUT inputs. This may cause some short glitches when
the inputs change the value. These glitches can be removed by clocking through filters if demanded by application
needs.
The Filter Selection bits (FILTSEL) in the LUT Control registers (CCL.LUTnCTRLA) define the digital filter options.
When a filter is enabled, the output will be delayed by two to five CLK cycles (peripheral clock or alternative clock).
One clock cycle after the corresponding LUT is disabled, all internal filter logic is cleared.
Figure 28-5. Filter
FILTSEL
Input
OUT
Q
D
R
Q
D
R
Q
D
R
D
G
Q
R
CLK_MUX_OUT
CLR
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 365
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.3.2.5 Edge Detector
The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a falling edge,
the TRUTH table should be programmed to provide inverted output.
The edge detector is enabled by writing '1' to the Edge Selection bit (EDGEDET) in the LUT n Control A register
(CCL.LUTnCTRLA). In order to avoid unpredictable behavior, a valid filter option must be enabled as well.
Edge detection is disabled by writing a '0' to EDGEDET in CCL.LUTnCTRLA. After disabling an LUT, the
corresponding internal Edge Detector logic is cleared one clock cycle later.
Figure 28-6. Edge Detector
CLK_MUX_OUT
28.3.2.6 Sequential Logic
Each LUT pair can be connected to an internal Sequential block. A Sequential block can function as either D flip-flop,
JK flip-flop, gated D-latch, or RS-latch. The function is selected by writing the Sequential Selection bits (SEQSEL) in
the Sequential Control register (CCL.SEQCTRLn).
The Sequential block receives its input from either LUT, filter, or edge detector, depending on the configuration.
The Sequential block is clocked by the same clock as the corresponding LUT, which is either the peripheral clock or
input line 2 (IN[2]). This is configured by the Clock Source bit (CLKSRC) in the LUT n Control A register
(CCL.LUTnCTRLA).
When the even LUT (LUT0) is disabled, the latch is asynchronously cleared, during which the flip-flop Reset signal
(R) is kept enabled for one clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on the rising edge of
the clock, as shown in the respective Characteristics tables.
Gated D Flip-Flop (DFF)
The D-input is driven by the even LUT output (LUT0), and the G-input is driven by the odd LUT output (LUT1).
Figure 28-7. D Flip-Flop
even LUT
CLK_MUX_OUT
odd LUT
Table 28-3. DFF Characteristics
R
G
D
OUT
1
X
X
Clear
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 366
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
...........continued
R
G
D
OUT
0
1
1
Set
0
Clear
X
Hold state (no change)
0
JK Flip-Flop (JK)
The J-input is driven by the even LUT output (LUT0), and the K-input is driven by the odd LUT output (LUT1).
Figure 28-8. JK Flip-Flop
even LUT
CLK_MUX_OUT
odd LUT
Table 28-4. JK Characteristics
R
J
K
OUT
1
X
X
Clear
0
0
0
Hold state (no change)
0
0
1
Clear
0
1
0
Set
0
1
1
Toggle
Gated D-Latch (DLATCH)
The D-input is driven by the even LUT output (LUT0), and the G-input is driven by the odd LUT output (LUT1).
Figure 28-9. D-Latch
even LUT
D
odd LUT
G
Q
OUT
Table 28-5. D-Latch Characteristics
G
D
OUT
0
X
Hold state (no change)
1
0
Clear
1
1
Set
RS-Latch (RS)
The S-input is driven by the even LUT output (LUT0), and the R-input is driven by the odd LUT output (LUT1).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 367
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
Figure 28-10. RS-Latch
even LUT
S
odd LUT
R
Q
OUT
Table 28-6. RS-Latch Characteristics
S
R
OUT
0
0
Hold state (no change)
0
1
Clear
1
0
Set
1
1
Forbidden state
28.3.2.7 Clock Source Settings
The Filter, Edge Detector, and Sequential logic are by default clocked by the system clock (CLK_PER). It is also
possible to use the LUT input 2 (IN[2]) to clock these blocks (CLK_MUX_OUT in Figure 28-11). This is configured by
writing the Clock Source bit (CLKSRC) in the LUT Control A register (CCL.LUTnCTRLA) to '1'.
Figure 28-11. Clock Source Settings
Edge
Detector
IN[2]
Filter
CLK_MUX_OUT
CLK_CCL
CLKSRC
LUT0
Edge
Detector
IN[2]
Sequential
logic
Filter
CLK_MUX_OUT
CLK_CCL
CLKSRC
LUT1
When the Clock Source bit (CLKSRC) is '1', IN[2] is used to clock the corresponding Filter and Edge Detector
(CLK_MUX_OUT). The Sequential logic is clocked by CLK_MUX_OUT of the even LUT in the pair. When CLKSRC
bit is '1', IN[2] is treated as MASKed (low) in the TRUTH table.
The CCL peripheral must be disabled while changing the clock source to avoid undetermined outputs from the
peripheral.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 368
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.3.3
Events
The CCL can generate the following output events:
•
LUTnOUT: Look-Up Table Output Value
The CCL can take the following actions on an input event:
•
INx: The event is used as input for the TRUTH table
Related Links
15. Event System (EVSYS)
28.3.4
Sleep Mode Operation
Writing the Run In Standby bit (RUNSTDBY) in the Control A register (CCL.CTRLA) to '1' will allow the system clock
to be enabled in Standby Sleep mode.
If RUNSTDBY is '0' the system clock will be disabled in Standby Sleep mode. If the Filter, Edge Detector, or
Sequential logic is enabled, the LUT output will be forced to zero in Standby Sleep mode. In Idle sleep mode, the
TRUTH table decoder will continue operation and the LUT output will be refreshed accordingly, regardless of the
RUNSTDBY bit.
If the Clock Source bit (CLKSRC) in the LUT n Control A register (CCL.LUTnCTRLA) is written to '1', the LUT input 2
(IN[2]) will always clock the Filter, Edge Detector, and Sequential block. The availability of the IN[2] clock in sleep
modes will depend on the sleep settings of the peripheral employed.
28.3.5
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 369
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.4
Register Summary - CCL
Offset
Name
Bit Pos.
0x00
0x01
0x02
...
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
CTRLA
SEQCTRL0
7:0
7:0
28.5
RUNSTDBY
ENABLE
SEQSEL[3:0]
Reserved
LUT0CTRLA
LUT0CTRLB
LUT0CTRLC
TRUTH0
LUT1CTRLA
LUT1CTRLB
LUT1CTRLC
TRUTH1
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
EDGEDET
EDGEDET
CLKSRC
INSEL1[3:0]
FILTSEL[1:0]
CLKSRC
INSEL1[3:0]
FILTSEL[1:0]
OUTEN
ENABLE
INSEL0[3:0]
INSEL2[3:0]
TRUTH[7:0]
OUTEN
ENABLE
INSEL0[3:0]
INSEL2[3:0]
TRUTH[7:0]
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 370
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
-
6
RUNSTDBY
R/W
0
5
4
3
2
1
0
ENABLE
R/W
0
Bit 6 – RUNSTDBY Run in Standby
This bit indicates if the peripheral clock (CLK_PER) is kept running in Standby Sleep mode. The setting is ignored for
configurations where the CLK_PER is not required.
Value
Description
0
System clock is not required in Standby Sleep mode
1
System clock is required in Standby Sleep mode
Bit 0 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 371
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.5.2
Sequential Control 0
Name:
Offset:
Reset:
Property:
Bit
7
SEQCTRL0
0x01 [ID-00000485]
0x00
Enable-Protected
6
Access
Reset
5
4
3
R/W
0
2
1
SEQSEL[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – SEQSEL[3:0] Sequential Selection
These bits select the sequential configuration.
Value
Name
Description
0x0
DISABLE
Sequential logic is disabled
0x1
DFF
D flip-flop
0x2
JK
JK flip-flop
0x3
LATCH
D latch
0x4
RS
RS latch
Other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 372
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.5.3
LUT n Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
EDGEDET
R/W
0
LUTCTRLA
0x05 + n*0x04 [n=0..1]
0x00
Enable-Protected
6
CLKSRC
R/W
0
5
4
FILTSEL[1:0]
R/W
R/W
0
0
3
OUTEN
R/W
0
2
1
0
ENABLE
R/W
0
Bit 7 – EDGEDET Edge Detection
Value
Description
0
Edge detector is disabled
1
Edge detector is enabled
Bit 6 – CLKSRC Clock Source Selection
This bit selects whether the peripheral clock (CLK_PER) or any input present on input line 2 (IN[2]) is used as clock
(CLK_MUX_OUT) for an LUT.
The CLK_MUX_OUT of the even LUT is used for clocking the Sequential block of an LUT pair.
Value
Description
0
CLK_PER is clocking the LUT
1
IN[2] is clocking the LUT
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
Value
Name
0x0
DISABLE
0x1
SYNCH
0x2
FILTER
0x3
-
Description
Filter disabled
Synchronizer enabled
Filter enabled
Reserved
Bit 3 – OUTEN Output Enable
This bit enables the LUT output to the LUTnOUT pin. When written to '1', the pin configuration of the PORT I/O
Controller is overridden.
Value
Description
0
Output to pin disabled
1
Output to pin enabled
Bit 0 – ENABLE LUT Enable
Value
Description
0
The LUT is disabled
1
The LUT is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 373
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.5.4
LUT n Control B
Name:
Offset:
Reset:
Property:
LUTCTRLB
0x06 + n*0x04 [n=0..1]
0x00
Enable-Protected
SPI connections to the CCL work only in master SPI mode.
USART connections to the CCL work only in asynchronous/synchronous USART Master mode.
Bit
Access
Reset
7
R/W
0
6
5
INSEL1[3:0]
R/W
R/W
0
0
4
3
R/W
0
R/W
0
2
1
INSEL0[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 7:4 – INSEL1[3:0] LUT n Input 1 Source Selection
These bits select the source for input 1 of LUT n:
Value
Name
Description
0x0
MASK
Masked input
0x1
FEEDBACK
Feedback input
0x2
LINK
Linked other LUT as input source
0x3
EVENT0
Event input source 0
0x4
EVENT1
Event input source 1
0x5
IO
I/O pin LUTn-IN1 input source
0x6
AC0
AC0 OUT input source
0x7
TCB0
TCB WO input source
0x8
TCA0
TCA WO1 input source
0x9
Reserved
0xA
USART0
USART TXD input source
0xB
SPI0
SPI MOSI input source
Bits 3:0 – INSEL0[3:0] LUT n Input 0 Source Selection
These bits select the source for input 0 of LUT n:
Value
Name
Description
0x0
MASK
Masked input
0x1
FEEDBACK
Feedback input
0x2
LINK
Linked other LUT as input source
0x3
EVENT0
Event input source 0
0x4
EVENT1
Event input source 1
0x5
IO
I/O pin LUTn-IN0 input source
0x6
AC0
AC0 OUT input source
0x7
TCB0
TCB WO input source
0x8
TCA0
TCA WO0 input source
0x9
Reserved
0xA
USART0
USART XCK input source
0xB
SPI0
SPI SCK input source
Other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 374
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.5.5
LUT n Control C
Name:
Offset:
Reset:
Property:
Bit
7
LUTCTRLC
0x07 + n*0x04 [n=0..1]
0x00
Enable-Protected
6
Access
Reset
5
4
3
R/W
0
2
1
INSEL2[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – INSEL2[3:0] LUT n Input 2 Source Selection
These bits select the source for input 2 of LUT n:
Value
Name
Description
0x0
MASK
Masked input
0x1
FEEDBACK
Feedback input
0x2
LINK
Linked other LUT as input source
0x3
EVENT0
Event input source 0
0x4
EVENT1
Event input source 1
0x5
IO
I/O pin LUTn-IN2 input source
0x6
AC0
AC0 OUT input source
0x7
TCB0
TCB WO input source
0x8
TCA0
TCA WO2 input source
0x9
Reserved
0xA
Reserved
0xB
SPI0
SPI MISO input source
other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 375
ATtiny202/204/402/404/406 Automotiv...
Configurable Custom Logic (CCL)
28.5.6
TRUTHn
Name:
Offset:
Reset:
Property:
Bit
7
TRUTH
0x08 + n*0x04 [n=0..1]
0x00
Enable-Protected
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TRUTH[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TRUTH[7:0] Truth Table
These bits define the value of truth logic as a function of inputs IN[2:0].
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 376
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.
Analog Comparator (AC)
29.1
Features
•
•
•
•
•
•
•
•
29.2
One Instance of the AC Controller, AC0
Zero-Cross Detection
Selectable Hysteresis:
– None
– 10 mV
– 25 mV
– 50 mV
Analog Comparator Output Available on Pin
Comparator Output Inversion Available
Flexible Input Selection:
– Up to two positive pins
– Up to two negative pins
– Internal reference voltage
Interrupt Generation On:
– Rising edge
– Falling edge
– Both edges
Event Generation:
– Comparator output
Overview
The Analog Comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The AC can be configured to generate interrupt requests and/or events upon several different
combinations of input change.
The dynamic behavior of the AC can be adjusted by a hysteresis feature. The hysteresis can be customized to
optimize the operation for each application.
The input selection includes analog port pins and internal references. The analog comparator output state can also
be output on a pin for use by external devices.
The AC has one positive input and one negative input. The positive input source is one of a selection of two analog
input pins. The negative inputs are chosen either from analog input pins or from internal inputs, such as an internal
voltage reference.
The digital output from the comparator is '1' when the difference between the positive and the negative input voltage
is positive and '0' otherwise.
This device provides one instance of the AC controller, AC0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 377
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.2.1
Block Diagram
Figure 29-1. Analog Comparator
AC Controller
AINP0
MUXCTRLA
:
Invert
+
AINPn
Controller
Logic
AC
AINN0
OUT
-
:
AINNn
Hysteresis
Enable
VREF
Event
System
CTRLA
Note: Refer to 29.2.2 Signal Description for the number of AINN and AINP.
29.2.2
29.2.3
Signal Description
Signal
Description
Type
AINN0
Negative Input 0
Analog
AINN1
Negative Input 1
Analog
AINP0
Positive Input 0
Analog
AINP1
Positive Input 1
Analog
OUT
Comparator Output for AC
Digital
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 29-1. AC System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
29.2.3.1 Clocks
This peripheral depends on the peripheral clock.
29.2.3.2 I/O Lines and Connections
I/O pins AINN0-AINN1 and AINP0- AINP1 are all analog inputs to the AC.
For correct operation, the pins must be configured in the port and port multiplexing peripherals.
It is recommended to disable the GPIO input when using the AC.
29.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 378
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.2.3.4 Events
The events of this peripheral are connected to the Event System.
29.2.3.5 Debug Operation
This peripheral is unaffected by entering Debug mode.
If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper
operation or data loss may result during halted debugging.
29.3
29.3.1
Functional Description
Initialization
For basic operation, follow these steps:
• Configure the desired input pins in the port peripheral
• Select the positive and negative input sources by writing the Positive and Negative Input MUX Selection bit
fields (MUXPOS and MUXNEG) in the MUX Control A register (AC.MUXCTRLA)
• Optional: Enable the output to pin by writing a '1' to the Output Pad Enable bit (OUTEN) in the Control A register
(AC.CTRLA)
• Enable the AC by writing a '1' to the ENABLE bit in AC.CTRLA
During the start-up time after enabling the AC, the output of the AC may be invalid.
The start-up time of the AC by itself is at most 2.5 µs. If an internal reference is used, the reference start-up time is
normally longer than the AC start-up time. The VREF start-up time is 60 µs at most.
29.3.2
Operation
29.3.2.1 Input Hysteresis
Applying an input hysteresis helps to prevent constant toggling of the output when the noise-afflicted input signals are
close to each other.
The input hysteresis can either be disabled or have one of three levels. The hysteresis is configured by writing to the
Hysteresis Mode Select bit field (HYSMODE) in the Control A register (ACn.CTRLA).
29.3.2.2 Input Sources
The AC has one positive and one negative input. The inputs can be pins and internal sources, such as a voltage
reference.
Each input is selected by writing to the Positive and Negative Input MUX Selection bit field (MUXPOS and MUXNEG)
in the MUX Control A register (AC.MUXTRLA).
29.3.2.2.1 Pin Inputs
The following Analog input pins on the port can be selected as input to the analog comparator
•
•
•
•
AINN0
AINN1
AINP0
AINP1
29.3.2.2.2 Internal Inputs
One internal input is available for the analog comparator:
•
29.3.3
AC voltage reference
Events
The AC will generate the following event automatically when the AC is enabled:
•
The digital output from the AC (OUT in the block diagram) is available as an Event System source. The events
from the AC are asynchronous to any clocks in the device.
The AC has no event inputs.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 379
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.3.4
Interrupts
Table 29-2. Available Interrupt Vectors and Sources
Offset Name
0x00
Vector Description
COMP0 Analog comparator interrupt
Conditions
AC output is toggling as configured by INTMODE in AC.CTRLA
When an interrupt condition occurs, the corresponding interrupt flag is set in the STATUS register (AC.STATUS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt Control
register (AC.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the AC.STATUS register description for details
on how to clear interrupt flags.
29.3.5
Sleep Mode Operation
In Idle Sleep mode, the AC will continue to operate as normal.
In Standby Sleep mode, the AC is disabled by default. If the Run in Standby Sleep mode bit (RUNSTDBY) in the
Control A register (AC.CTRLA) is written to '1', the AC will continue to operate, but the Status register will not be
updated, and no Interrupts are generated if no other modules request the CLK_PER, but events and the pad output
will be updated.
In Power-Down Sleep mode, the AC and the output to the pad are disabled.
29.3.6
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 380
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.4
Register Summary - AC
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
...
0x05
0x06
0x07
CTRLA
Reserved
MUXCTRLA
7:0
RUNSTDBY
7:0
INVERT
29.5
OUTEN
INTMODE[1:0]
HYSMODE[1:0]
MUXPOS
ENABLE
MUXNEG[1:0]
Reserved
INTCTRL
STATUS
7:0
7:0
STATE
CMP
CMP
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 381
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RUNSTDBY
R/W
0
CTRLA
0x00
0x00
-
6
OUTEN
R/W
0
5
4
INTMODE[1:0]
R/W
R/W
0
0
3
2
1
HYSMODE[1:0]
R/W
R/W
0
0
0
ENABLE
R/W
0
Bit 7 – RUNSTDBY Run in Standby Mode
Writing a '1' to this bit allows the AC to continue operation in Standby Sleep mode. Since the clock is stopped,
interrupts and status flags are not updated.
Value
Description
0
In Standby Sleep mode, the peripheral is halted
1
In Standby Sleep mode, the peripheral continues operation
Bit 6 – OUTEN Analog Comparator Output Pad Enable
Writing this bit to '1' makes the OUT signal available on the pin.
Bits 5:4 – INTMODE[1:0] Interrupt Modes
Writing to these bits selects what edges of the AC output triggers an interrupt request.
Value
Name
Description
0x0
BOTHEDGE
Both negative and positive edge
0x1
Reserved
0x2
NEGEDGE
Negative edge
0x3
POSEDGE
Positive edge
Bits 2:1 – HYSMODE[1:0] Hysteresis Mode Select
Writing these bits selects the Hysteresis mode for the AC input.
Value
Name
Description
0x0
OFF
OFF
0x1
10
±10 mV
0x2
25
±25 mV
0x3
50
±50 mV
Bit 0 – ENABLE Enable AC
Writing this bit to '1' enables the AC.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 382
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.5.2
Mux Control A
Name:
Offset:
Reset:
Property:
MUXCTRLA
0x02
0x00
-
AC.MUXCTRLA controls analog comparator muxes
Bit
Access
Reset
7
INVERT
R/W
0
6
5
4
3
MUXPOS
R/W
0
2
1
0
MUXNEG[1:0]
R/W
R/W
0
0
Bit 7 – INVERT Invert AC Output
Writing a '1' to this bit enables inversion of the output of the AC. This effectively inverts the input to all the peripherals
connected to the signal, and affects the internal status signals.
Bit 3 – MUXPOS Positive Input MUX Selection
Writing to this bit field selects the input signal to the positive input of the AC.
Value
Name
Description
0x0
AINP0
Positive Pin 0
0x1
AINP1
Positive Pin 1
Bits 1:0 – MUXNEG[1:0] Negative Input MUX Selection
Writing to this bit field selects the input signal to the negative input of the AC.
Value
Name
Description
0x0
AINN0
Negative Pin 0
0x1
AINN1
Negative Pin 1
0x2
VREF
Voltage Reference
0x3
Reserved
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 383
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.5.3
Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x06
0x00
-
6
5
4
3
Access
Reset
2
1
0
CMP
R/W
0
Bit 0 – CMP Analog Comparator Interrupt Enable
Writing this bit to '1' enables analog comparator interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 384
ATtiny202/204/402/404/406 Automotiv...
Analog Comparator (AC)
29.5.4
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x07
0x00
-
6
Access
Reset
5
4
STATE
R
0
3
2
1
0
CMP
R/W
0
Bit 4 – STATE Analog Comparator State
This shows the current status of the OUT signal from the AC. This will have a synchronizer delay to get updated in
the I/O register (three cycles).
Bit 0 – CMP Analog Comparator Interrupt Flag
This is the interrupt flag for AC. Writing a '1' to this bit will clear the Interrupt Flag.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 385
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.
Analog-to-Digital Converter (ADC)
30.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
30.2
10-Bit Resolution
±2 LSB Absolute Accuracy
6.5 - 260 μs Conversion Time
Up to 115 ksps at 10-Bit Resolution (150 ksps at 8-bit)
Up to Twelve Multiplexed Single-ended Input Channels
Temperature Sensor Input Channel
0V to VDD ADC Input Voltage Range
Multiple Internal ADC Reference Voltages Between 0.55V and VDD
Free-running or Single Conversion mode
Interrupt Available on ADC Conversion Complete
Optional Event Triggered Conversion
Optional Interrupt on Conversion Results
Compare Function for Accurate Monitoring or User-Defined Thresholds (Window Comparator mode)
Accumulation up to 64 Samples per Conversion
Overview
The Analog-to-Digital Converter (ADC) peripheral features a 10-bit Successive Approximation ADC (SAR), with a
sampling rate up to 115 ksps at 10-bit resolution (150 ksps at 8-bit). The ADC is connected to a 12-channel analog
multiplexer, which allows twelve single-ended voltage inputs. The single-ended voltage inputs refer to 0V (GND). The
ADC input channel can either be internal (e.g. a voltage reference) or external through the analog input pins.
An ADC conversion can be started by software or by using the Event System (EVSYS) to route an event from other
peripherals, making it possible to do a periodic sampling of input signals, trigger an ADC conversion on a special
condition, or trigger an ADC conversion in Standby Sleep mode. A window compare feature is available for
monitoring the input signal and can be configured to only trigger an interrupt on user-defined thresholds for under,
over, inside, or outside a window, with minimum software intervention required.
The ADC input signal is fed through a sample-and-hold circuit that ensures that the input voltage to the ADC is held
at a constant level during sampling.
The ADC supports sampling in bursts where a configurable number of conversion results are accumulated into a
single ADC result (Sample Accumulation). Further, a sample delay can be configured to tune the ADC sampling
frequency associated with a single burst. This is to tune the sampling frequency away from any harmonic noise
aliased with the ADC sampling frequency (within the burst) from the sampled signal. An automatic sampling delay
variation feature can be used to randomize this delay to slightly change the time between samples.
Internal reference voltages from Voltage Reference (VREF) or VDD are provided on-chip.
This device has one instance of the ADC peripheral; ADC0.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 386
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.2.1
Block Diagram
Figure 30-1. Block Diagram
Internal reference
VREF
VDD
ADC
"accumulate"
"enable"
VREF
RES
"convert"
AINn
..
.
"sample"
AIN0
AIN1
>
<
Control Logic
MUXPOS
WCOMP
(IRQ)
RESRDY
(IRQ)
CTRLA
EVCTRL
COMMAND
WINLT
WINHT
The analog input channel is selected by writing to the MUXPOS bits in the MUXPOS register (ADC.MUXPOS). Any
of the ADC input pins, GND, can be selected as single-ended input to the ADC. The ADC is enabled by writing a ‘1’
to the ADC ENABLE bit in the Control A register (ADC.CTRLA). Voltage reference and input channel selections will
not go into effect before the ADC is enabled. The ADC does not consume power when the ENABLE bit in
ADC.CTRLA is ‘0’.
The ADC generates a 10-bit result that can be read from the Result Register (ADC.RES). The result is presented
right adjusted.
30.2.2
Signal Description
Pin Name
Type
Description
AIN[11:0]
Analog input
Analog input to be converted
Related Links
2.1 Configuration Summary
5. I/O Multiplexing and Considerations
30.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 30-1. ADC System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
Yes
CPUINT
Events
Yes
EVSYS
Debug
Yes
UPDI
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 387
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.2.3.1 Clocks
The ADC uses the peripheral clock CLK_PER and has an internal prescaler to generate the ADC clock source
CLK_ADC.
Related Links
11. Clock Controller (CLKCTRL)
30.3.2.2 Clock Generation
30.2.3.2 I/O Lines and Connections
The I/O pins (AINx) are configured by the port - I/O Pin Controller.
The digital input buffer should be disabled on the pin used as input for the ADC to disconnect the digital domain from
the analog domain to obtain the best possible ADC results. This is configured by the port - I/O Pin Controller.
Related Links
17. I/O Pin Configuration (PORT)
30.2.3.3 Interrupts
Using the interrupts of this peripheral requires the interrupt controller to be configured first.
Related Links
14. CPU Interrupt Controller (CPUINT)
9.7.3 SREG
30.3.4 Interrupts
30.2.3.4 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
30.2.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging mode will
halt normal operation of the peripheral.
This peripheral can be forced to operate with halted CPU by writing a '1' to the Debug Run bit (DBGRUN) in the
Debug Control register of the peripheral (peripheral.DBGCTRL).
30.2.4
Definitions
An ideal n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest
code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal
behavior:
Offset Error
The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5
LSB). Ideal value: 0 LSB.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 388
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
Figure 30-2. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
Gain Error
VREF Input Voltage
After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE
to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB.
Figure 30-3. Gain Error
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF
Integral NonLinearity (INL)
Input Voltage
After adjusting for offset and gain error, the INL is the maximum deviation of an actual
transition compared to an ideal transition for any code. Ideal value: 0 LSB.
Figure 30-4. Integral Non-Linearity
Output Code
INL
Ideal ADC
Actual ADC
VREF
© 2019 Microchip Technology Inc.
Complete Datasheet
Input Voltage
DS40002159A-page 389
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
Differential NonLinearity (DNL)
The maximum deviation of the actual code width (the interval between two adjacent
transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
Figure 30-5. Differential Non-Linearity
Output Code
0x3FF
1 LSB
DNL
0x000
0
VREF
Input Voltage
Quantization Error
Due to the quantization of the input voltage into a finite number of codes, a range of input
voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
Absolute Accuracy
The maximum deviation of an actual (unadjusted) transition compared to an ideal transition
for any code. This is the compound effect of all aforementioned errors. Ideal value: ±0.5 LSB.
30.3
Functional Description
30.3.1
Initialization
The following steps are recommended in order to initialize ADC operation:
1. Configure the resolution by writing to the Resolution Selection bit (RESSEL) in the Control A register
(ADC.CTRLA).
2. Optional: Enable the Free-Running mode by writing a '1' to the Free-Running bit (FREERUN) in ADC.CTRLA.
3. Optional: Configure the number of samples to be accumulated per conversion by writing the Sample
Accumulation Number Select bits (SAMPNUM) in the Control B register (ADC.CTRLB).
4. Configure a voltage reference by writing to the Reference Selection bit (REFSEL) in the Control C register
(ADC.CTRLC). Default is the internal voltage reference of the device (VREF, as configured there).
5. Configure the CLK_ADC by writing to the Prescaler bit field (PRESC) in the Control C register (ADC.CTRLC).
6. Configure an input by writing to the MUXPOS bit field in the MUXPOS register (ADC.MUXPOS).
7. Optional: Enable Start Event input by writing a '1' to the Start Event Input bit (STARTEI) in the Event Control
register (ADC.EVCTRL). Configure the Event System accordingly.
8. Enable the ADC by writing a '1' to the ENABLE bit in ADC.CTRLA.
Following these steps will initialize the ADC for basic measurements, which can be triggered by an event (if
configured) or by writing a '1' to the Start Conversion bit (STCONV) in the Command register (ADC.COMMAND).
30.3.2
Operation
30.3.2.1 Starting a Conversion
Once the input channel is selected by writing to the MUXPOS register (ADCn.MUXPOS), a conversion is triggered by
writing a '1' to the ADC Start Conversion bit (STCONV) in the Command register (ADCn.COMMAND). This bit is one
as long as the conversion is in progress. In Single Conversion mode, STCONV is cleared by hardware when the
conversion is completed.
If a different input channel is selected while a conversion is in progress, the ADC will finish the current conversion
before changing the channel.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 390
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
Depending on the accumulator setting, the conversion result is from a single sensing operation, or from a sequence
of accumulated samples. Once the triggered operation is finished, the Result Ready flag (RESRDY) in the Interrupt
Flag register (ADCn.INTFLAG) is set. The corresponding interrupt vector is executed if the Result Ready Interrupt
Enable bit (RESRDY) in the Interrupt Control register (ADCn.INTCTRL) is one and the Global Interrupt Enable bit is
one.
A single conversion can be started by writing a '1' to the STCONV bit in ADCn.COMMAND. The STCONV bit can be
used to determine if a conversion is in progress. The STCONV bit will be set during a conversion and cleared once
the conversion is complete.
The RESRDY interrupt flag in ADCn.INTFLAG will be set even if the specific interrupt is disabled, allowing software
to check for finished conversion by polling the flag. A conversion can thus be triggered without causing an interrupt.
Alternatively, a conversion can be triggered by an event. This is enabled by writing a '1' to the Start Event Input bit
(STARTEI) in the Event Control register (ADCn.EVCTRL). Any incoming event routed to the ADC through the Event
System (EVSYS) will trigger an ADC conversion. This provides a method to start conversions at predictable intervals
or at specific conditions.
The event trigger input is edge sensitive. When an event occurs, STCONV in ADCn.COMMAND is set. STCONV will
be cleared when the conversion is complete.
In Free-Running mode, the first conversion is started by writing the STCONV bit to '1' in ADCn.COMMAND. A new
conversion cycle is started immediately after the previous conversion cycle has completed. A conversion complete
will set the RESRDY flag in ADCn.INTFLAGS.
30.3.2.2 Clock Generation
Figure 30-6. ADC Prescaler
ENABLE
"START"
Reset
8-bit PRESCALER
CTRLC
CLK_PER/256
CLK_PER/128
CLK_PER/64
CLK_PER/32
CLK_PER/16
CLK_PER/8
CLK_PER/4
CLK_PER/2
CLK_PER
PRESC
ADC clock source
(CLK_ADC)
The ADC requires an input clock frequency between 50 kHz and 1.5 MHz for maximum resolution. If a lower
resolution than 10 bits is selected, the input clock frequency to the ADC can be higher than 1.5 MHz to get a higher
sample rate.
The ADC module contains a prescaler which generates the ADC clock (CLK_ADC) from any CPU clock (CLK_PER)
above 100 kHz. The prescaling is selected by writing to the Prescaler bits (PRESC) in the Control C register
(ADCn.CTRLC). The prescaler starts counting from the moment the ADC is switched on by writing a '1' to the
ENABLE bit in ADCn.CTRLA. The prescaler keeps running as long as the ENABLE bit is one. The prescaler counter
is reset to zero when the ENABLE bit is zero.
When initiating a conversion by writing a '1' to the Start Conversion bit (STCONV) in the Command register
(ADCn.COMMAND) or from event, the conversion starts at the following rising edge of the CLK_ADC clock cycle.
The prescaler is kept reset as long as there is no ongoing conversion. This assures a fixed delay from the trigger to
the actual start of a conversion in CLK_PER cycles as:
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 391
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
StartDelay =
PRESCfactor
+2
2
Figure 30-7. Start Conversion and Clock Generation
CLK_PER
STCONV
CLK_PER/2
CLK_PER/4
CLK_PER/8
30.3.2.3 Conversion Timing
A normal conversion takes 13 CLK_ADC cycles. The actual sample-and-hold takes place two CLK_ADC cycles after
the start of a conversion. Start of conversion is initiated by writing a '1' to the STCONV bit in ADC.COMMAND. When
a conversion is complete, the result is available in the Result register (ADC.RES), and the Result Ready interrupt flag
is set (RESRDY in ADC.INTFLAG). The interrupt flag will be cleared when the result is read from the Result registers,
or by writing a '1' to the RESRDY bit in ADC.INTFLAG.
Figure 30-8. ADC Timing Diagram - Single Conversion
Cycle Number
1
2
3
4
5
6
7
9
8
10
11
13
12
ADC clock
ADC enable
STCONV
RESRDY IF
RESH
RESL
Result MSB
Result LSB
conversion
sample
complete
Both sampling time and sampling length can be adjusted using Sample Delay bit field in Control D (ADC.CTRLD) and
sampling Sample Length bit field in the Sample Control register (ADC.SAMPCTRL). Both of these control the ADC
sampling time in a number of CLK_ADC cycles. This allows sampling high-impedance sources without relaxing
conversion speed. See register description for further information. Total sampling time is given by:
SampleTime =
2 + SAMPDLY + SAMPLEN
�CLK_ADC
Figure 30-9. ADC Timing Diagram - Single Conversion With Delays
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK_ADC
ENABLE
STCONV
RES
Result
INITDLY
(0 – 256
CLK_ADC cycles)
SAMPDLY
(0 – 15
CLK_ADC cycles)
SAMPLEN
(0 – 31
CLK_ADC cycles)
In Free-Running mode, a new conversion will be started immediately after the conversion completes, while the
STCONV bit is one. The sampling rate RS in free-running mode is calculated by:
�S =
�CLK_ADC
13 + SAMPDLY + SAMPLEN
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 392
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
Figure 30-10. ADC Timing Diagram - Free-Running Conversion
2
3
4
6
5
7
1
Cycle Number
8
9
10
11
12
13
1
2
ADC clock
ADC enable
Input event
STCONV
RESRDY IF
RESH
RESL
Result MSB
Result LSB
sample
conversion
complete
30.3.2.4 Changing Channel or Reference Selection
The MUXPOS bits the ADCn.MUXPOS register and the REFSEL bits in the ADCn.CTRLC register are buffered
through a temporary register to which the CPU has random access. This ensures that the channel and reference
selections only take place at a safe point during the conversion. The channel and reference selections are
continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selections are locked to ensure sufficient sampling time for the
ADC. Continuous updating resumes in the last CLK_ADC clock cycle before the conversion completes (RESRDY in
ADCn.INTFLAGS is set). The conversion starts on the following rising CLK_ADC clock edge after the STCONV bit is
written to '1'.
30.3.2.4.1 ADC Input Channels
When changing channel selection, the user should observe the following guidelines to ensure that the correct
channel is selected:
In Single Conversion mode: The channel should be selected before starting the conversion. The channel selection
may be changed one ADC clock cycle after writing '1' to the STCONV bit.
In Free-Running mode: The channel should be selected before starting the first conversion. The channel selection
may be changed one ADC clock cycle after writing '1' to the STCONV bit. Since the next conversion has already
started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect
the new channel selection.
The ADC requires a settling time after switching the input channel - refer to the Electrical Characteristics section for
details.
Related Links
32. Electrical Characteristics
30.3.2.4.2 ADC Voltage Reference
The reference voltage for the ADC (VREF) controls the conversion range of the ADC. Input voltages that exceed the
selected VREF will be converted to the maximum result value of the ADC, for an ideal 10-bit ADC this is 0x3FF. VREF
can be selected by writing the Reference Selection bits (REFSEL) in the Control C register (ADC.CTRLC) as either
VDD or an internal reference from the VREF peripheral. VDD is connected to the ADC through a passive switch.
The internal reference is generated from an internal bandgap reference through an internal amplifier, and is controlled
by the Voltage Reference (VREF) peripheral.
Related Links
19. Voltage Reference (VREF)
30.3.2.4.3 Analog Input Circuitry
The analog input circuitry is illustrated in Figure 30-11. An analog source applied to ADCn is subjected to the pin
capacitance and input leakage of that pin (represented by IH and IL), regardless of whether that channel is selected
as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series
resistance (combined resistance in the input path).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 393
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such source is
used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend
on how long the source needs to charge the S/H capacitor, which can vary substantially.
Figure 30-11. Analog Input Schematic
IIH
ADCn
Rin
Cin
IIL
VDD/2
30.3.2.5 ADC Conversion Result
After the conversion is complete (RESRDY is '1'), the conversion result RES is available in the ADC Result Register
(ADCn.RES). The result for a 10-bit conversion is given as:
1023 × �IN
�REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see description for
REFSEL in ADCn.CTRLC and ADCn.MUXPOS).
RES =
30.3.2.6 Window Comparator Mode
The ADC can raise the WCOMP flag in the Interrupt and Flag register (ADCn.INTFLAG) and request an interrupt
(WCOMP) when the result of a conversion is above and/or below certain thresholds. The available modes are:
• The result is under a threshold
• The result is over a threshold
• The result is inside a window (above a lower threshold, but below the upper one)
• The result is outside a window (either under the lower or above the upper threshold)
The thresholds are defined by writing to the Window Comparator Threshold registers (ADCn.WINLT and
ADCn.WINHT). Writing to the Window Comparator mode bit field (WINCM) in the Control E register (ADCn.CTRLE)
selects the conditions when the flag is raised and/or the interrupt is requested.
Assuming the ADC is already configured to run, follow these steps to use the Window Comparator mode:
1. Choose which Window Comparator to use (see WINCM description in ADCn.CTRLE), and set the required
threshold(s) by writing to ADCn.WINLT and/or ADCn.WINHT.
2. Optional: enable the interrupt request by writing a '1' to the Window Comparator Interrupt Enable bit (WCOMP)
in the Interrupt Control register (ADCn.INTCTRL).
3. Enable the Window Comparator and select a mode by writing a non-zero value to the WINCM bit field in
ADCn.CTRLE.
When accumulating multiple samples, the comparison between the result and the threshold will happen after the last
sample was acquired. Consequently, the flag is only raised once, after taking the last sample of the accumulation.
30.3.3
Events
An ADC conversion can be triggered automatically by an event input if the Start Event Input bit (STARTEI) in the
Event Control register (ADCn.EVCTRL) is written to '1'.
See also the description of the Asynchronous User Channel n Input Selection in the Event System
(EVSYS.ASYNCUSERn).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 394
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.3.4
Interrupts
Table 30-2. Available Interrupt Vectors and Sources
Offset Name
Vector Description
Conditions
0x00
RESRDY Result Ready interrupt
The conversion result is available in the Result register
(ADC.RES).
0x02
WCOMP Window Comparator interrupt As defined by WINCM in ADC.CTRLE.
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of the
peripheral (peripheral.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheral's Interrupt
Control register (peripheral.INTCTRL).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt flag is set. The
interrupt request remains active until the interrupt flag is cleared. See the peripheral's INTFLAGS register for details
on how to clear interrupt flags.
30.3.5
Sleep Mode Operation
The ADC is by default disabled in Standby Sleep mode.
The ADC can stay fully operational in Standby Sleep mode if the Run in Standby bit (RUNSTDBY) in the Control A
register (ADC.CTRLA) is written to '1'.
When the device is entering Standby Sleep mode when RUNSTDBY is one, the ADC will stay active, hence any
ongoing conversions will be completed and interrupts will be executed as configured.
In Standby Sleep mode an ADC conversion must be triggered via the Event System (EVSYS), or the ADC must be in
free-running mode with the first conversion triggered by software before entering sleep. The peripheral clock is
requested if needed and is turned off after the conversion is completed.
When an input event trigger occurs, the positive edge will be detected, the Start Conversion bit (STCONV) in the
Command register (ADC.COMMAND) set, and the conversion will start. When the conversion is completed, the
Result Ready Flag (RESRDY) in the Interrupt Flags register (ADC.INTFLAGS) is set and the STCONV bit in
ADC.COMMAND is cleared.
The reference source and supply infrastructure need time to stabilize when activated in Standby Sleep mode.
Configure a delay for the start of the first conversion by writing a non-zero value to the Initial Delay bits (INITDLY) in
the Control D register (ADC.CTRLD).
In Power-Down Sleep mode, no conversions are possible. Any ongoing conversions are halted and will be resumed
when going out of sleep. At end of conversion, the Result Ready Flag (RESRDY) will be set, but the content of the
result registers (ADC.RES) is invalid since the ADC was halted in the middle of a conversion.
Related Links
12. Sleep Controller (SLPCTRL)
30.3.6
Synchronization
Not applicable.
30.3.7
Configuration Change Protection
Not applicable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 395
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.4
Register Summary - ADCn
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
...
0x0F
CTRLA
CTRLB
CTRLC
CTRLD
CTRLE
SAMPCTRL
MUXPOS
Reserved
COMMAND
EVCTRL
INTCTRL
INTFLAGS
DBGCTRL
TEMP
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0x10
RES
0x12
WINLT
0x14
WINHT
0x16
CALIB
30.5
RUNSTBY
7:0
7:0
7:0
7:0
7:0
7:0
RESSEL
SAMPCAP
INITDLY[2:0]
REFSEL[1:0]
ASDV
FREERUN
SAMPNUM[2:0]
PRESC[2:0]
SAMPDLY[3:0]
WINCM[2:0]
SAMPLEN[4:0]
MUXPOS[4:0]
WCOMP
WCOMP
ENABLE
STCONV
STARTEI
RESRDY
RESRDY
DBGRUN
TEMP[7:0]
Reserved
7:0
15:8
7:0
15:8
7:0
15:8
7:0
RES[7:0]
RES[15:8]
WINLT[7:0]
WINLT[15:8]
WINHT[7:0]
WINHT[15:8]
DUTYCYC
Register Description
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 396
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
RUNSTBY
R/W
0
CTRLA
0x00
0x00
-
6
5
4
3
R
0
R
0
R
0
R
0
2
RESSEL
R/W
0
1
FREERUN
R/W
0
0
ENABLE
R/W
0
Bit 7 – RUNSTBY Run in Standby
This bit determines whether the ADC needs to run when the chip is in Standby Sleep mode.
Bit 2 – RESSEL Resolution Selection
This bit selects the ADC resolution.
Value
Description
0
Full 10-bit resolution. The 10-bit ADC results are accumulated or stored to the ADC Result register
(ADC.RES).
1
8-bit resolution. The conversion results are truncated to eight bits (MSBs) before they are accumulated
or stored to the ADC Result register (ADC.RES). The two Least Significant bits are discarded.
Bit 1 – FREERUN Free-Running
Writing a '1' to this bit will enable the Free-Running mode for the data acquisition. The first conversion is started by
writing COMMAND.STCONV bit high. In the Free-Running mode, a new conversion cycle is started immediately after
or as soon as the previous conversion cycle has completed. This is signaled by INTFLAGS.RESRDY.
Bit 0 – ENABLE ADC Enable
Value
Description
0
ADC is disabled
1
ADC is enabled
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 397
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
-
6
5
4
3
Access
Reset
2
R/W
0
1
SAMPNUM[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SAMPNUM[2:0] Sample Accumulation Number Select
These bits select how many consecutive ADC sampling results are accumulated automatically. When this bit is
written to a value greater than 0x0, the according number of consecutive ADC sampling results are accumulated into
the ADC Result register (ADC.RES) in one complete conversion.
Value
Name
Description
0x0
NONE
No accumulation.
0x1
ACC2
2 results accumulated.
0x2
ACC4
4 results accumulated.
0x3
ACC8
8 results accumulated.
0x4
ACC16
16 results accumulated.
0x5
ACC32
32 results accumulated.
0x6
ACC64
64 results accumulated.
0x7
Reserved.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 398
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.3
Control C
Name:
Offset:
Reset:
Property:
Bit
7
Access
Reset
R
0
CTRLC
0x02
0x00
-
6
SAMPCAP
R/W
0
5
4
REFSEL[1:0]
R/W
R/W
0
0
3
2
R
0
R/W
0
1
PRESC[2:0]
R/W
0
0
R/W
0
Bit 6 – SAMPCAP Sample Capacitance Selection
This bit selects the sample capacitance, and hence, the input impedance. The best value is dependent on the
reference voltage and the application's electrical properties.
Value
Description
0
Recommended for reference voltage values below 1V.
1
Reduced size of sampling capacitance. Recommended for higher reference voltages.
Bits 5:4 – REFSEL[1:0] Reference Selection
These bits select the voltage reference for the ADC.
Value
Name
0x0
INTERNAL
0x1
VDD
Other
-
Description
Internal reference
VDD
Reserved.
Bits 2:0 – PRESC[2:0] Prescaler
These bits define the division factor from the peripheral clock (CLK_PER) to the ADC clock (CLK_ADC).
Value
Name
Description
0x0
DIV2
CLK_PER divided by 2
0x1
DIV4
CLK_PER divided by 4
0x2
DIV8
CLK_PER divided by 8
0x3
DIV16
CLK_PER divided by 16
0x4
DIV32
CLK_PER divided by 32
0x5
DIV64
CLK_PER divided by 64
0x6
DIV128
CLK_PER divided by 128
0x7
DIV256
CLK_PER divided by 256
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 399
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.4
Control D
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
R/W
0
CTRLD
0x03
0x00
-
6
INITDLY[2:0]
R/W
0
5
R/W
0
4
ASDV
R/W
0
3
R/W
0
2
1
SAMPDLY[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 7:5 – INITDLY[2:0] Initialization Delay
These bits define the initialization/start-up delay before the first sample when enabling the ADC or changing to an
internal reference voltage. Setting this delay will ensure that the reference, MUXes, etc. are ready before starting the
first conversion. The initialization delay will also take place when waking up from deep sleep to do a measurement.
The delay is expressed as a number of CLK_ADC cycles.
Value
Name
Description
0x0
DLY0
Delay 0 CLK_ADC cycles.
0x1
DLY16
Delay 16 CLK_ADC cycles.
0x2
DLY32
Delay 32 CLK_ADC cycles.
0x3
DLY64
Delay 64 CLK_ADC cycles.
0x4
DLY128
Delay 128 CLK_ADC cycles.
0x5
DLY256
Delay 256 CLK_ADC cycles.
Other
Reserved
Bit 4 – ASDV Automatic Sampling Delay Variation
Writing this bit to '1' enables automatic sampling delay variation between ADC conversions. The purpose of varying
sampling instant is to randomize the sampling instant and thus avoid standing frequency components in the
frequency spectrum. The value of the SAMPDLY bits are automatically incremented by one after each sample.
When the Automatic Sampling Delay Variation is enabled and the SAMPDLY value reaches 0xF, it wraps around to
0x0.
Value
Name
Description
0
ASVOFF
The Automatic Sampling Delay Variation is disabled.
1
ASVON
The Automatic Sampling Delay Variation is enabled.
Bits 3:0 – SAMPDLY[3:0] Sampling Delay Selection
These bits define the delay between consecutive ADC samples. The programmable Sampling Delay allows modifying
the sampling frequency during hardware accumulation, to suppress periodic noise sources that may otherwise disturb
the sampling. The SAMPDLY field can be also modified automatically from one sampling cycle to another, by setting
the ASDV bit. The delay is expressed as CLK_ADC cycles and is given directly by the bitfield setting. The sampling
cap is kept open during the delay.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 400
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.5
Control E
Name:
Offset:
Reset:
Property:
Bit
7
CTRLE
0x4
0x00
-
6
5
4
3
Access
Reset
2
R/W
0
1
WINCM[2:0]
R/W
0
0
R/W
0
Bits 2:0 – WINCM[2:0] Window Comparator Mode
This field enables and defines when the interrupt flag is set in Window Comparator mode. RESULT is the 16-bit
accumulator result. WINLT and WINHT are 16-bit lower threshold value and 16-bit higher threshold value,
respectively.
Value
Name
Description
0x0
NONE
No Window Comparison (default)
0x1
BELOW
RESULT < WINLT
0x2
ABOVE
RESULT > WINHT
0x3
INSIDE
WINLT < RESULT < WINHT
0x4
OUTSIDE
RESULT < WINLT or RESULT >WINHT)
Other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 401
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.6
Sample Control
Name:
Offset:
Reset:
Property:
Bit
7
SAMPCTRL
0x5
0x00
-
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
SAMPLEN[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – SAMPLEN[4:0] Sample Length
These bits extend the ADC sampling length in a number of CLK_ADC cycles. By default, the sampling time is two
CLK_ADC cycles. Increasing the sampling length allows sampling sources with higher impedance. The total
conversion time increases with the selected sampling length.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 402
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.7
MUXPOS
Name:
Offset:
Reset:
Property:
MUXPOS
0x06
0x00
-
Bit
7
6
5
4
3
Access
Reset
R
0
R
0
R
0
R/W
0
R/W
0
2
MUXPOS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – MUXPOS[4:0] MUXPOS
This bit field selects which single-ended analog input is connected to the ADC. If these bits are changed during a
conversion, the change will not take effect until this conversion is complete.
Value
Name
Description
0x00
AIN0
ADC input pin 0
0x01
AIN1
ADC input pin 1
0x02
AIN2
ADC input pin 2
0x03
AIN3
ADC input pin 3
0x04
AIN4
ADC input pin 4
0x05
AIN5
ADC input pin 5
0x06
AIN6
ADC input pin 6
0x07
AIN7
ADC input pin 7
0x08
AIN8
ADC input pin 8
0x09
AIN9
ADC input pin 9
0x0A
AIN10
ADC input pin 10
0x0B
AIN11
ADC input pin 11
0x1C
Reserved
0x1D
INTREF
Internal reference (from VREF peripheral)
0x1E
Reserved
0x1F
GND
0V (GND)
Other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 403
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.8
Command
Name:
Offset:
Reset:
Property:
COMMAND
0x08
0x00
-
Bit
7
6
5
4
3
2
1
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
STCONV
R/W
0
Bit 0 – STCONV Start Conversion
Writing a '1' to this bit will start a single measurement. If in Free-Running mode this will start the first conversion.
STCONV will read as '1' as long as a conversion is in progress. When the conversion is complete, this bit is
automatically cleared.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 404
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x09
0x00
-
6
5
4
3
Access
Reset
2
1
0
STARTEI
R/W
0
Bit 0 – STARTEI Start Event Input
This bit enables event input as source for conversion start.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 405
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.10 Interrupt Control
Name:
Offset:
Reset:
Property:
Bit
7
INTCTRL
0x0A
0x00
-
6
5
4
3
Access
Reset
2
1
WCOMP
R/W
0
0
RESRDY
R/W
0
Bit 1 – WCOMP Window Comparator Interrupt Enable
Writing a '1' to this bit enables window comparator interrupt.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a '1' to this bit enables result ready interrupt.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 406
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.11 Interrupt Flags
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAGS
0x0B
0x00
-
6
5
4
3
Access
Reset
2
1
WCOMP
R/W
0
0
RESRDY
R/W
0
Bit 1 – WCOMP Window Comparator Interrupt Flag
This window comparator flag is set when the measurement is complete and if the result matches the selected
Window Comparator mode defined by WINCM (ADCn.CTRLE). The comparison is done at the end of the conversion.
The flag is cleared by either writing a '1' to the bit position or by reading the Result register (ADCn.RES). Writing a '0'
to this bit has no effect.
Bit 0 – RESRDY Result Ready Interrupt Flag
The result ready interrupt flag is set when a measurement is complete and a new result is ready. The flag is cleared
by either writing a '1' to the bit location or by reading the Result register (ADCn.RES). Writing a '0' to this bit has no
effect.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 407
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.12 Debug Run
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x0C
0x00
-
6
5
4
3
2
Access
Reset
1
0
DBGRUN
R/W
0
Bit 0 – DBGRUN Debug Run
Value
Description
0
The peripheral is halted in Break Debug mode and ignores events
1
The peripheral will continue to run in Break Debug mode when the CPU is halted
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 408
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.13 Temporary
Name:
Offset:
Reset:
Property:
TEMP
0x0D
0x00
-
The Temporary register is used by the CPU for single-cycle, 16-bit access to the 16-bit registers of this peripheral. It
can be read and written by software. There is one common Temporary register for all the 16-bit registers of this
peripheral.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TEMP[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TEMP[7:0] Temporary
Temporary register for read/write operations in 16-bit registers.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 409
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.14 Result
Name:
Offset:
Reset:
Property:
RES
0x10
0x00
-
The ADCn.RESL and ADCn.RESH register pair represent the 16-bit value, ADCn.RES. The low byte [7:0] (suffix L) is
accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
If the analog input is higher than the reference level of the ADC, the 10-bit ADC result will be equal the maximum
value of 0x3FF. Likewise, if the input is below 0V, the ADC result will be 0x000. As the ADC cannot produce a result
above 0x3FF values, the accumulated value will never exceed 0xFFC0 even after the maximum allowed 64
accumulations.
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
RES[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
RES[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:8 – RES[15:8] Result high byte
These bits constitute the MSB of ADCn.RES register, where the MSb is RES[15]. The ADC itself has 10-bit output,
ADC[9:0], where the MSb is ADC[9]. The data format in ADC and Digital Accumulation is 1’s complement, where
0x0000 represents the zero and 0xFFFF represents the largest number (full scale).
Bits 7:0 – RES[7:0] Result low byte
These bits constitute the LSB of ADC/Accumulator Result, (ADCn.RES) register. The data format in ADC and Digital
Accumulation is 1’s complement, where 0x0000 represents the zero and 0xFFFF represents the largest number (full
scale).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 410
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.15 Window Comparator Low Threshold
Name:
Offset:
Reset:
Property:
WINLT
0x12
0x00
-
This register is the 16-bit low threshold for the digital comparator monitoring the ADCn.RES register. The ADC itself
has 10-bit output, RES[9:0], where the MSb is RES[9]. The data format in ADC and Digital Accumulation is one’s
complement, where 0x0000 represents the zero and 0xFFFF represents the largest number (full scale).
The ADCn.WINLTH and ADCn.WINLTL register pair represent the 16-bit value, ADCn.WINLT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
When accumulating samples, the window comparator thresholds are applied on the accumulated value and not on
each sample.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINLT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – WINLT[15:8] Window Comparator Low Threshold High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – WINLT[7:0] Window Comparator Low Threshold Low Byte
These bits hold the LSB of the 16-bit register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 411
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.16 Window Comparator High Threshold
Name:
Offset:
Reset:
Property:
WINHT
0x14
0x00
-
This register is the 16-bit high threshold for the digital comparator monitoring the ADCn.RES register. The ADC itself
has 10-bit output, RES[9:0], where the MSb is RES[9]. The data format in ADC and Digital Accumulation is one’s
complement, where 0x0000 represents the zero and 0xFFFF represents the largest number (full scale).
The ADCn.WINHTH and ADCn.WINHTL register pair represents the 16-bit value, ADCn.WINHT. The low byte [7:0]
(suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01.
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINHT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINHT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:8 – WINHT[15:8] Window Comparator High Threshold High Byte
These bits hold the MSB of the 16-bit register.
Bits 7:0 – WINHT[7:0] Window Comparator High Threshold Low Byte
These bits hold the LSB of the 16-bit register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 412
ATtiny202/204/402/404/406 Automotiv...
Analog-to-Digital Converter (ADC)
30.5.17 Calibration
Name:
Offset:
Reset:
Property:
Bit
7
CALIB
0x16
0x01
-
6
5
4
3
Access
Reset
2
1
0
DUTYCYC
R/W
1
Bit 0 – DUTYCYC Duty Cycle
This bit determines the duty cycle of the ADC clock.
Value
Description
0
50% Duty Cycle
1
25% Duty Cycle (high 25% and low 75%)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 413
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.
Unified Program and Debug Interface (UPDI)
31.1
Features
•
•
•
31.2
Programming:
– External programming through UPDI 1-wire (1W) interface
• Enable programming by 12V or fuse
• Uses the RESET pin of the device for programming
• No GPIO pins occupied during operation
• Asynchronous Half-Duplex UART protocol towards the programmer
Debugging:
– Memory mapped access to device address space (NVM, RAM, I/O)
– No limitation on device clock frequency
– Unlimited number of user program breakpoints
– Two hardware breakpoints
– Run-time readout of CPU Program Counter (PC), Stack Pointer (SP), and Status register (SREG) for code
profiling
– Program flow control
• Go, Stop, Reset, Step Into
– Non-intrusive run-time chip monitoring without accessing system registers
• Monitor CRC status and sleep status
Unified Programming and Debug Interface (UPDI):
– Built-in error detection with error signature readout
– Frequency measurement of internal oscillators using the Event System
Overview
The Unified Program and Debug Interface (UPDI) is a proprietary interface for external programming and on-chip
debugging of a device.
The UPDI supports programming of nonvolatile memory (NVM) space; FLASH, EEPROM, fuses, lockbits, and the
user row. In addition, the UPDI can access the entire I/O and data space of the device. See the NVM controller
documentation for programming via the NVM controller and executing NVM controller commands.
Programming and debugging are done through the UPDI Physical interface (UPDI PHY), which is a 1-wire UARTbased half duplex interface using the RESET pin for data reception and transmission. Clocking of UPDI PHY is done
by an internal oscillator. Enabling of the 1-wire interface, by disabling the Reset functionality, is either done by 12V
programming or by fusing the RESET pin to UPDI by setting the RESET Pin Configuration (RSTPINCFG) bits in
FUSE.SYSCFG0. The UPDI access layer grants access to the bus matrix, with memory mapped access to system
blocks such as memories, NVM, and peripherals.
The Asynchronous System Interface (ASI) provides direct interface access to On-Chip Debugging (OCD), NVM and
System Management features. This gives the debugger direct access to system information, without requesting bus
access.
Related Links
10. Nonvolatile Memory Controller (NVMCTRL)
31.3.7 Enabling of KEY Protected Interfaces
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 414
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.2.1
Block Diagram
Figure 31-1. UPDI Block Diagram
ASI
Memories
UPDI PAD
(RX/TX Data)
UPDI
Physical
layer
Bus Matrix
UPDI Controller
UPDI
Access
layer
NVM
Peripherals
ASI Access
ASI Internal Interfaces
OCD
NVM
Controller
System
Management
31.2.2
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 31-1. UPDI System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORT
Interrupts
No
-
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
31.2.2.2 I/O Lines and Connections
31.2.2.4 Power Management
31.2.2.1 Clocks
The UPDI Physical (UPDI PHY) layer and UPDI Access (UPDI ACC) layer can operate on different clock domains.
The UPDI PHY layer clock is derived from an internal oscillator, and the UPDI ACC layer clock is the same as the
system clock. There is a synchronization boundary between the UPDI PHY layer and the UPDI ACC layer, which
ensures correct operation between the clock domains. The UPDI clock output frequency is selected through the ASI,
and the default UPDI clock start-up frequency is 4 MHz after enabling the UPDI. The UPDI clock frequency is
changed by writing the UPDICLKSEL bits in the ASI_CTRLA register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 415
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-2. UPDI Clock Domains
ASI
SYNCH
UPDI Controller
UPDI
Physical
layer
Clock
Controller
UPDI clk
source
~
UPDI
Access
layer
Clock
Controller
Clk_UPDI
Clk_sys
Clk_sys
UPDI
CLKSEL
~
Related Links
11. Clock Controller (CLKCTRL)
31.2.2.2 I/O Lines and Connections
To operate the UPDI, the RESET pin must be set to UPDI mode. This is not done through the port I/O pin
configuration as regular I/O pins, but through setting the RESET Pin Configuration (RSTPINCFG) bits in
FUSE.SYSCFG0 as described in 31.3.2.1 UPDI Enable with Fuse Override of RESET Pin, or by following the UPDI
12V enable sequence from 31.3.2.2 UPDI Enable with 12V Override of RESET Pin. Pull enable, input enable and
output enable settings are automatically controlled by the UPDI when active.
31.2.2.3 Events
The events of this peripheral are connected to the Event System.
Related Links
15. Event System (EVSYS)
31.2.2.4 Power Management
The UPDI physical layer continues to operate in any Sleep mode and is always accessible for a connected debugger,
but read/write access to the system bus is restricted in Sleep modes where the CPU clock is switched off. The UPDI
can be enabled at any time, independent of the system Sleep state. See 31.3.9 Sleep Mode Operation for details on
UPDI operation during Sleep modes.
31.3
31.3.1
Functional Description
Principle of Operation
Communication through the UPDI is based on standard UART communication, using a fixed frame format, and
automatic baud rate detection for clock and data recovery. In addition to the data frame, there are several control
frames which are important to the communication. The supported frame formats are presented in Figure 31-3.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 416
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-3. Supported UPDI Frame Formats
DATA
St
0
1
2
3
4
5
6
7
P
S1 S2
P
S1 S2
P
S1 S2
IDLE
BREAK
SYNCH (0x55)
St
Synch Part
End_synch
ACK (0x40)
St
Data
Frame
IDLE
Frame
BREAK
SYNCH
ACK
Data frame consist of one Start bit (always low), eight data bits, one parity bit (even parity), and two Stop
bits (always high). If the Start bit, parity bit, or Stop bits have an incorrect value, an error will be detected
and signalized by the UPDI. The parity bit-check in the UPDI can be disabled by writing the PARD bit in
UPDI.CTRLA, in which case the parity generation from the debugger can be ignored.
Special frame that consists of 12 high bits. This is the same as keeping the transmission line in an Idle
state.
Special frame that consists of 12 low bits. The BREAK frame is used to reset the UPDI back to its default
state and is typically used for error recovery.
The SYNCH frame (0x55) is used by the Baud Rate Generator to set the baud rate for the coming
transmission. A SYNCH character is always expected by the UPDI in front of every new instruction, and
after a successful BREAK has been transmitted.
The Acknowledge (ACK) character is transmitted from the UPDI whenever an ST or STS instruction has
successfully crossed the synchronization boundary and have gained bus access. When an ACK is
received by the debugger, the next transmission can start.
31.3.1.1 UPDI UART
All transmission and reception of serial data on the UPDI is achieved using the UPDI frames presented in Figure
31-3. Communication is initiated from the master (debugger) side, and every transmission must start with a SYNCH
character upon which the UPDI can recover the transmission baud rate, and store this setting for the coming data.
The baud rate set by the SYNCH character will be used for both reception and transmission for the instruction byte
received after the SYNCH. See 31.3.3 UPDI Instruction Set for details on when the next SYNCH character is
expected in the instruction stream.
There is no writable baud rate register in the UPDI, so the baud rate sampled from the SYNCH character is used for
data recovery by sampling the Start bit, and performing a majority vote on the middle samples. This process is
repeated for all bits in the frame, including the parity bit and two Stop bits. The baud generator uses 16 samples, and
the majority voting is done on sample 7, 8, and 9.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 417
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-4. UPDI UART Start Bit and Data/Parity/Stop Bit Sampling
RxD
IDLE
Sample
0 0
START
1
2
3
4
5
6
7
RxD
BIT 0
8 9 10 11 12 13 14 15 16 1
2
3
BIT n
Sample
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 1
The transmission baud rate must be set up in relation to the selected UPDI clock, which can be adjusted by
UPDICLKSEL in UPDI.ASI_CTRLA. See Table 31-2 for recommended maximum and minimum baud rate settings.
Table 31-2. Recommended UART Baud Rate Based on UPDICLKSEL Setting
UPDICLKSEL[1:0]
MAX Recommended Baud Rate
MIN Recommended Baud Rate
0x1 (16 MHz)
0.9 Mbps
0.300 kbps
0x2 (8 MHz)
450 kbps
0.150 kbps
0x3 (4 MHz) - Default
225 kbps
0.075 kbps
The UPDI Baud Rate Generator utilizes fractional baud counting to minimize the transmission error. With the fixed
frame format used by the UPDI, the maximum and recommended receiver transmission error limits can be seen in
the following table:
Table 31-3. Receiver Baud Rate Error
Data + Parity Bits
Rslow
Rfast
Max. Total Error [%]
Recommended
Max. RX Error [%]
9
96.39
104.76
+4.76/-3.61
+1.5/-1.5
31.3.1.2 BREAK Character
The BREAK character is used to reset the internal state of the UPDI to the default setting. This is useful if the UPDI
enters an error state due to a communication error, or when synchronization between the debugger and the UPDI is
lost.
A single BREAK character is enough to reset the UPDI, but in some special cases where the BREAK character is
sent when the UPDI has not yet entered the error state, a double BREAK character might be needed. A double
BREAK is ensured to reset the UPDI from any state. When sending a double BREAK it is required to have at least
one Stop bit between the BREAK characters.
No SYNCH character is required before the BREAK because the BREAK is used to reset the UPDI from any state.
This means that the UPDI will sample the BREAK based on the last stored baud rate setting, derived from the last
received valid SYNCH character. If the communication error was due to an incorrect sampling of the SYNCH
character, the baud rate is unknown to the connected debugger. For this reason, the BREAK character should be
transmitted at the slowest recommended baud rate setting for the selected UPDI clock according to Table 31-4:
Table 31-4. Recommended BREAK Character Duration
UPDICLKSEL[1:0]
Recommended BREAK Character Duration
0x1 (16 MHz)
6.15 ms
0x2 (8 MHz)
12.30 ms
0x3 (4 MHz) - Default
24.60 ms
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 418
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.3.2
Operation
The UPDI must be enabled before the UART communication can start:
• 31.3.2.2 UPDI Enable with 12V Override of RESET Pin
• 31.3.2.1 UPDI Enable with Fuse Override of RESET Pin
31.3.2.1 UPDI Enable with Fuse Override of RESET Pin
When the RESET Pin Configuration (RSTPINCFG) bits in FUSE.SYSCFG0 are 0x1, the RESET pin will be
overridden, and the UPDI will take control of the pin and configure it as input with pull-up. When the pull-up is
detected by a connected debugger, the UPDI enable sequence, as depicted below, is started.
Figure 31-5. UPDI Enable Sequence with UPDI PAD Enabled By Fuse
1
Fuse read in. Pull-up enabled. Ready to receive init.
2
Drive low from debugger to request UPDI clock
3
UPDI clock ready; Communication channel ready.
RESET
1
2
Hi-Z
St
D0
D1
D2
Handshake / BREAK
TRES
UPDI.rxd
UPDI.txd
D3
D4
D5
D6
D7
Sp
SYNC (0x55)
(Autobaud)
(Ignore)
3
Hi-Z
Hi-Z
UPDI.txd = 0
TUPDI
debugger.
UPDI.txd
Hi-Z
Hi-Z
Debugger.txd = 0
TDeb0
Debugger.txd = z
TDebZ
When the pull-up is detected, the debugger initiates the enable sequence by driving the line low for a duration of
TDeb0 to ensure that the line is released from the debugger before the UPDI enable sequence is done.
The negative edge is detected by the UPDI, which requests the UPDI clock. The UPDI will continue to drive the line
low until the clock is stable and ready for the UPDI to use. The duration of this TUPDI will vary, depending on the
status of the oscillator when the UPDI is enabled. After this duration, the data line will be released by the UPDI, and
pulled high.
When the debugger detects that the line is high, the initial SYNCH character (0x55) must be sent to properly enable
the UPDI for communication. If the Start bit of the SYNCH character is not sent well within maximum TDebZ, the UPDI
will disable itself, and the enable sequence must be repeated. This time is based on counted cycles on the 4 MHz
UPDI clock, which is the default when enabling the UPDI. The disable is performed to avoid the UPDI being enabled
unintentionally.
After successful SYNCH character transmission, the first instruction frame can be transmitted.
Related Links
32.17 UPDI Timing
31.3.2.2 UPDI Enable with 12V Override of RESET Pin
GPIO or Reset functionality on the RESET pin can be overridden by the UPDI by using 12V programming. By
applying a 12V pulse to the RESET pin, the pin functionality is switched to UPDI, independent of RSTPINCFG in
FUSE.SYSCFG0. It is recommended to always reset the device before starting the 12V enable sequence.
During power-up, the Power-on Reset (POR) must be released before the 12V pulse can be applied. The duration of
the pulse is recommended in the range from 100 μs to 1 ms, before tri-stating. When applying the rising edge of the
12V pulse, the UPDI will be reset. After tri-stating, the UPDI will remain in Reset until the RESET pin is driven low by
the debugger. This will release the UPDI Reset and initiate the same enable sequence as explained in 31.3.2.1 UPDI
Enable with Fuse Override of RESET Pin.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 419
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
The following figure shows the 12V enable sequence.
Figure 31-6. UPDI Enable Sequence by 12V Programming
1 Fused pin Function disabled; UPDI pin function enabled.
2
UPDI interface enabled with pull-up.
1
(Ignore)
St
Hi-Z
D0
D1
D2
D3
D4
D5
D6
D7
Sp
UPDIPAD
12V ramp
Tmin10ns
Tmax4ms
Handshake / BREAK
Debugger.txd = z
Tmin10us
Tmin1us
Tmax200us
Tmax10us
SYNC (0x55)
(Autobaud)
(Ignore)
UPDI.rxd
Hi-Z
UPDI.txd
Hi-Z
2
UPDI.txd = 0
Tmin10us,
Tmax200us
debugger.
UPDI.txd
debugger.
UPDI.o12v
Hi-Z
12V
Hi-Z
Debugger.txd = 0
Tmin200ns
Tmax1us
Debugger.txd = z.
Tmin200us,
Tmax14ms
Vdd
When enabled by 12V, only a POR will disable the UPDI configuration on the RESET pin, and restore the default
setting. If issuing a UPDI Disable command through the UPDIDIS bit in UPDI.CTRLB, the UPDI will be reset and the
clock request will be canceled, but the RESET pin will remain in UPDI configuration.
Note: If insufficient external protection is added to the UPDI Pin, an ESD pulse can be interpreted as a 12V override
by the microcontroller and enables the UPDI.
31.3.2.3 UPDI Disable
Any programming or debug session should be terminated by writing the UPDIDIS bit in UPDI.CTRLB. Writing this bit
will reset the UPDI including any decoded KEYs and disable the oscillator request for the module. If the disable
operation is not performed the UPDI will stay enabled and request its oscillator, causing increased power
consumption for the application.
During the enable sequence the UPDI can disable itself in case of a faulty enable sequence. There are two cases
that will cause an automatic disable:
• A SYNCH character is not sent within 13.5 ms after the initial enable pulse described in 31.3.2.1 UPDI Enable
with Fuse Override of RESET Pin.
• The first SYNCH character after an initiated enable is too short or too long to register as a valid SYNCH
character. See Table 31-2 for recommended baud rate operating ranges.
31.3.2.4 Output Enable Timer Protection for GPIO Configuration
When the RESET Pin Configuration (RSTPINCFG) bits in FUSE.SYSCFG0 are 0x0, the RESET pin is configured as
GPIO. To avoid a potential conflict between the GPIO actively driving the output and a 12V UPDI enable sequence
initiation, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for
this pin only after this period.
It is always recommended to issue a System Reset before entering the 12V programming sequence.
31.3.2.5 UPDI Communication Error Handling
The UPDI contains a comprehensive error detection system that provides information to the debugger when
recovering from an error scenario. The error detection consists of detecting physical transmission errors like start bit
error, parity error, contention error, and frame error, to more high-level errors like access timeout error. See the
PESIG bits in UPDI_STATUSB for an overview of the available error signatures.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 420
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Whenever the UPDI detects an error, it will immediately transfer to an internal error state to avoid unwanted system
communication. In the error state the UPDI will ignore all incoming data requests, except if a BREAK character is
transmitted. The following procedure should always be applied when recovering from an error condition.
• Send a BREAK character. See 31.3.1.2 BREAK Character for recommended BREAK character handling.
• Send a SYNCH character at the desired baud rate for the next data transfer. Upon receiving a BREAK the UPDI
oscillator setting in UPDI.ASI_CTRLA is reset to the 4 MHz default UPDI clock selection. This affects the baud
rate range of the UPDI according to Table 31-2.
• Do a Load Control Status (LDCS) to UPDI.STATUSB register to read the PESIG field. PESIG gives information
about the occurred error, and the error signature will be cleared when read.
• The UPDI is now recovered from the error state and ready to receive the next SYNCH character and instruction.
31.3.2.6 Direction Change
In order to ensure correct timing for half duplex UART operation, the UPDI has a built-in Guard Time mechanism to
relax the timing when changing direction from RX mode to TX mode. The Guard Time is a number of IDLE bits
inserted before the next Start bit is transmitted. The number of IDLE bits can be configured through GTVAL in
UPDI.CTRLA. The duration of each IDLE bit is given by the baud rate used by the current transmission.
It is not recommended to use GTVAL setting 0x7, with no additional IDLE bits.
Figure 31-7. UPDI Direction Change by Inserting IDLE Bits
RX Data Frame
St
R X D a ta F ra m e
Dir Change
P
Data from
debugger to UPDI
S1
S2
I D L E b it s
TX Data Frame
St
T X D a ta F r a m e
G uard Tim e #
IDLE bits inserted
P
S1
S2
Data from UPDI to
debugger
The UPDI Guard Time is the minimum IDLE time that the connected debugger will experience when waiting for data
from the UPDI. Because of the asynchronous interface to the system, as presented in 31.2.2.1 Clocks, the ratio
between the UPDI clock and the system clock will affect the synchronization time, and how long it takes before the
UPDI can transmit data. In the cases where the synchronization delay is shorter than the current Guard Time setting,
the Guard Time will be given by GTVAL directly.
31.3.3
UPDI Instruction Set
Communication through the UPDI is based on a small instruction set. The instructions are used to access the internal
UPDI and ASI Control and Status (CS) space, as well as the memory mapped system space. All instructions are byte
instructions and must be preceded by a SYNCH character to determine the baud rate for the communication. See
31.3.1.1 UPDI UART for information about setting the baud rate for the transmission. The following figure gives an
overview of the UPDI instruction set.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 421
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-8. UPDI Instruction Set Overview
Opcode
L DS
STS
0
0
0
1
Size A
0
0
0
0
Opcode
LD
ST
0
0
0
1
Ptr
1
1
Size B
Size A/B
0
STCS
1
1
0
1
0
0
0
0
0
LD S
0
0
1
LD
0
1
0
STS
0
1
1
ST
1
0
0
L D C S ( L D S C o n t r o l/ S ta t u s )
1
0
1
REPEAT
1
1
0
S T C S ( S T S C o n tr o l/ S ta t u s )
1
1
1
KEY
S ize A - A d d re s s s ize
0
CS Address
L DCS
OPCODE
0
0
B y te
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
1
R e s e rv e d
P tr - P o in ter a c c es s
0
0
0
0
* (p tr)
0
1
* (p tr+ + )
1
0
p tr
1
1
R e s e rv e d
S ize B - D ata s ize
Size B
REPEA T
1
0
1
0
0
0
SIB
K EY
1
1
1
0
0
Size C
0
0
B y te
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
1
R e s e rv e d
C S A d d r e s s (C S - C o n t r o l /S t a t u s r e g .)
0
0
0
0
R eg 0
0
0
0
1
R eg 1
0
0
1
0
R eg 2
0
0
1
1
R eg 3
0
1
0
0
R e g 4 (A S I C S s p a c e )
......
1
1
1
1
R e s e rv e d
S ize C - K ey s ize
0
0
0
1
6 4 b it s ( 8 B y t e s )
1 2 8 b it s ( 1 6 B y t e s )
1
0
R e s e rv e d
1
1
R e s e rv e d
S IB – S y s t e m I n f o r m a t i o n B l o c k s e l .
© 2019 Microchip Technology Inc.
0
R e c e iv e K E Y
1
S e n d S IB
Complete Datasheet
DS40002159A-page 422
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.3.3.1 LDS - Load Data from Data Space Using Direct Addressing
The LDS instruction is used to load data from the bus matrix and into the serial shift register for serial readout. The
LDS instruction is based on direct addressing, and the address must be given as an operand to the instruction for the
data transfer to start. Maximum supported size for address and data is 16 bits. LDS instruction supports repeated
memory access when combined with the REPEAT instruction.
As shown in Figure 31-9, after issuing the SYNCH character followed by the LDS instruction, the number of desired
address bytes, as indicated by the SizeA field in the instruction, must be transmitted. The output data size is selected
by the SizeB field and is issued after the specified Guard Time. When combined with the REPEAT instruction, the
address must be sent in for each iteration of the repeat, meaning after each time the output data sampling is done.
There is no automatic address increment when using REPEAT with LDS, as it uses a direct addressing protocol.
Figure 31-9. LDS Instruction Operation
OPCODE
Size A
Size B
S ize A - A d d re s s s ize
0
L DS
0
0
0
0
0
B y te
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
1
R e s e rv e d
S ize B - D ata s ize
0
0
B y te
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
1
R e s e rv e d
ADR SIZE
Synch
(0x55)
LDS
A d r_ 0
Rx
A d r_ n
D a ta _ 0
D a ta _ n
Tx
ΔGT
31.3.3.2 STS - Store Data to Data Space Using Direct Addressing
The STS instruction is used to store data that is shifted serially into the PHY layer to the bus matrix address space.
The STS instruction is based on direct addressing, where the address is the first set of operands, and data is the
second set. The size of the address and data operands are given by the size fields presented in the figure below. The
maximum size for both address and data is 16 bits.
STS supports repeated memory access when combined with the REPEAT instruction.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 423
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-10. STS Instruction Operation
OPCODE
Size A
Size B
S ize A - A d d re s s s ize
0
STS
1
0
0
0
0
B y te
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
1
R e s e rv e d
S ize B - D ata s ize
0
0
B y te
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
1
R e s e rv e d
ADR SIZE
Synch
(0x55)
STS
A d r_ 0
DATA SIZE
A d r_ n
D a ta _ 0
Rx
D a ta _ n
ACK
ΔGT
ACK
Tx
ΔGT
The transfer protocol for an STS instruction is depicted in the figure as well, following this sequence:
1.
2.
3.
The address is sent.
An Acknowledge (ACK) is sent back from the UPDI if the transfer was successful.
The number of bytes as specified in the STS instruction is sent.
4.
A new ACK is received after the data has been successfully transferred.
31.3.3.3 LD - Load Data from Data Space Using Indirect Addressing
The LD instruction is used to load data from the bus matrix and into the serial shift register for serial readout. The LD
instruction is based on indirect addressing, which means that the Address Pointer in the UPDI needs to be written
prior to bus matrix access. Automatic pointer post-increment operation is supported and is useful when the LD
instruction is used with REPEAT. It is also possible to do an LD of the UPDI Pointer register. The maximum supported
size for address and data load is 16 bits.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 424
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-11. LD Instruction Operation
OPCODE
LD
Synch
(0x55)
0
0
Ptr
1
Size A/B
P tr - P o in ter a c c es s
0
0
0
* (p tr)
0
1
* (p tr+ + )
1
0
p tr
1
1
R e s e rv e d
S ize A - A d d re s s s ize
S ize B - D ata s ize
0
0
B y te
0
0
B y te
0
1
W o rd (2 B y te s )
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
0
R e s e rv e d
1
1
R e s e rv e d
1
1
R e s e rv e d
LD
DATA SIZE
D a ta _ 0
Rx
D a ta _ n
Tx
ΔGT
The figure above shows an example of a typical LD sequence, where data is received after the Guard Time period.
Loading data from the UPDI Pointer register follows the same transmission protocol.
31.3.3.4 ST - Store Data from Data Space Using Indirect Addressing
The ST instruction is used to store data that is shifted serially into the PHY layer to the bus matrix address space.
The ST instruction is based on indirect addressing, which means that the Address Pointer in the UPDI needs to be
written prior to bus matrix access. Automatic pointer post-increment operation is supported, and is useful when the
ST instruction is used with REPEAT. ST is also used to store the UPDI Address Pointer into the Pointer register. The
maximum supported size for storing address and data is 16 bits.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 425
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-12. ST Instruction Operation
OPCODE
ST
0
1
Ptr
1
Size A/B
P tr - P o in ter a c c es s
0
0
0
* (p tr)
0
1
* (p tr+ + )
1
0
p tr
1
1
R e s e rv e d
S ize A - A d d re s s s ize
S ize B - D ata s ize
0
0
B y te
0
0
B y te
0
1
W o rd (2 B y te s )
0
1
W o rd (2 B y te s )
1
0
R e s e rv e d
1
0
R e s e rv e d
1
1
R e s e rv e d
1
1
R e s e rv e d
ADDRESS_SIZE
Synch
(0x55)
ST
ADR _0
ADR _n
Rx
ACK
Tx
ΔGT
Block SIZE
Synch
(0x55)
ST
D a ta _ 0
Rx
D a ta _ n
ACK
Tx
ΔGT
The figure above gives an example of ST to the UPDI Pointer register and store of regular data. In both cases an
Acknowledge (ACK) is sent back by the UPDI if the store was successful and a SYNCH character is sent before each
instruction. To write the UPDI Pointer register, the following procedure should be followed.
• Set the PTR field in the ST instruction to the signature 0x2
•
•
Set the address size field SizeA to the desired address size
After issuing the ST instruction, send SizeA bytes of address data
•
Wait for the ACK character, which signifies a successful write to the Address register
After the Address register is written, sending data is done in a similar fashion.
• Set the PTR field in the ST instruction to the signature 0x0 to write to the address specified by the UPDI Pointer
register. If the PTR field is set to 0x1, the UPDI pointer is automatically updated to the next address according to
the data size SizeD field of the instruction after the write is executed
• Set the SizeD field in the instruction to the desired data size
• After sending the ST instruction, send SizeD bytes of address data
•
Wait for the ACK character which signifies a successful write to the bus matrix
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 426
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
When used with the REPEAT, it is recommended to set up the address register with the start address for the block to
be written and use the Pointer Post Increment register to automatically increase the address for each repeat cycle.
When using REPEAT, the data frame of SizeD data bytes can be sent after each received ACK.
31.3.3.5 LCDS - Load Data from Control and Status Register Space
The LCDS instruction is used to load data from the UPDI and ASI CS-space. LCDS is based on direct addressing,
where the address is part of the instruction opcode. The total address space for LCDS is 16 bytes and can only
access the internal UPDI register space. This instruction only supports byte access and the data size is not
configurable.
Figure 31-13. LCDS Instruction Operation
OPCODE
L DCS
1
0
CS Address
0
CS Address (CS - Control/Status reg.)
0 0 0 0 Reg 0
0 0 0 1 Reg 1
0 0 1 0 Reg 2
0 0 1 1 Reg 3
0 1 0 0 Reg 4 (ASI CS Space)
......
1 1 1 1 Reserved
0
Synch
(0x55)
LDCS
Rx
Data
Tx
Δgt
The figure above shows a typical example of LCDS data transmission. A data byte from the LCDS space is transmitted
from the UPDI after the Guard Time is completed.
31.3.3.6 STCS (Store Data to Control and Status Register Space)
The STCS instruction is used to store data to the UPDI and ASI CS-space. STCS is based on direct addressing,
where the address is part of the instruction opcode. The total address space for STCS is 16 bytes, and can only
access the internal UPDI register space. This instruction only supports byte access, and data size is not configurable.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 427
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-14. STCS Instruction Operation
OPCODE
STCS
1
1
CS Address
0
C S A d d r e s s (C S - C o n t r o l /S t a t u s r e g .)
0
Synch
(0x55)
STCS
0
0
0
0
R eg 0
0
0
0
1
R eg 1
0
0
1
0
R eg 2
0
0
1
1
R eg 3
0
1
0
0
R e g 4 (A S I C S S p a c e )
......
1
1
1
1
R e s e rv e d
D a ta
Rx
Tx
Figure 31-14 shows the data frame transmitted after the SYNCH and instruction frames. There is no response
generated from the STCS instruction, as is the case for ST and STS.
31.3.3.7 REPEAT - Set Instruction Repeat Counter
The REPEAT instruction is used to store the repeat count value into the UPDI Repeat Counter register. When
instructions are used with REPEAT, protocol overhead for SYNCH and Instruction Frame can be omitted on all
instructions except the first instruction after the REPEAT is issued. REPEAT is most useful for memory instructions
(LD,ST,LDS,STS), but all instructions can be repeated, except the REPEAT instruction itself.
The DATA_SIZE opcode field refers to the size of the repeat value. Only byte size (up to 255 repeats) is supported.
The instruction that is loaded directly after the REPEAT instruction will be repeated RPT_0 times. The instruction will
be issued a total of RPT_0 + 1 times. An ongoing repeat can only be aborted by sending a BREAK character.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 428
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-15. REPEAT Instruction Operation
OPCODE
REPEA T
1
0
Size B
1
0
0
0
S ize B - D ata s ize
0
0
B y te
0
1
R e s e rv e d
1
0
R e s e rv e d
1
1
R e s e rv e d
REPEAT SIZE
Synch
(0x55)
REPEA T
RPT_0
Rpt nr of Blocks of DATA_SIZE
DATA_SIZE
Synch
(0x55)
ST
(p t r + + )
D a ta _ 0
D a ta _ n
DATA_SIZE
DATA_SIZE
D a ta B _ 1
D a ta B _ n
Rx
ACK
Δd
ACK
Δd
Δd
Δd
Tx
Δd
The figure above gives an example of repeat operation with an ST instruction using pointer post-increment operation.
After the REPEAT instruction is sent with RPT_0 = n, the first ST instruction is issued with SYNCH and Instruction
frame, while the next n ST instructions are executed by only sending in data bytes according to the ST operand
DATA_SIZE, and maintaining the Acknowledge (ACK) handshake protocol.
If using indirect addressing instructions (LD/ST) it is recommended to always use the pointer post increment option
when combined with REPEAT. Otherwise, the same address will be accessed in all repeated access operations. For
direct addressing instructions (LDS/STS), the address must always be transmitted as specified in the instruction
protocol, before data can be received (LDS) or sent (STS).
31.3.3.8 KEY - Set Activation KEY
The KEY instruction is used for communicating KEY bytes to the UPDI, opening up for executing protected features
on the device. See Table 31-5 for an overview of functions that are activated by KEYs. For the KEY instruction, only
64-bit KEY size is supported. If the System Information Block (SIB) field of the KEY instruction is set, the KEY
instruction returns the SIB instead of expecting incoming KEY bytes. Maximum supported size for SIB is 128 bits.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 429
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-16. KEY Instruction Operation
SIB
K EY
1
1
1
0
Size C
0
S ize C - K ey s ize
0
0
6 4 b it s ( 8 B y t e s )
0
1
1 2 8 b it s ( 1 6 B y t e s ) ( S IB o n ly )
1
0
R e s e rv e d
1
1
R e s e rv e d
S IB – S y s t e m I n f o r m a t i o n B l o c k s e l .
0
Send KEY
1
R e c e iv e S I B
KEY SIZE
Synch
(0x55)
K EY
KEY_0
KEY_n
Rx
Tx
Synch
(0x55)
Rx
K EY
S IB _ 0
Δgt
S IB _ n
Tx
SIB SIZE
The figure above shows the transmission of a KEY and the reception of a SIB. In both cases, the SIZE_C field in the
opcode determines the number of frames being sent or received. There is no response after sending a KEY to the
UPDI. When requesting the SIB, data will be transmitted from the UPDI according to the current Guard Time setting.
31.3.4
System Clock Measurement with UPDI
It is possible to use the UPDI to get an accurate measurement of the system clock frequency, by using the UPDI
event connected to TCB with Input Capture capabilities. A recommended setup flow for this feature is given by the
following steps:
• Set up TCBn.CTRLB with setting CNTMODE=0x3, Input Capture Frequency Measurement mode.
• Write CAPTEI=1 in TCBn.EVCTRL to enable Event Interrupt. Keep EDGE = 0 in TCBn.EVCTRL.
• Configure the Event System as described in 31.3.8 Events.
• For the SYNCH character used to generate the UPDI events, it is recommended to use a slow baud rate in the
range of 10 kbps - 50 kbps to get a more accurate measurement on the value captured by the timer between
each UPDI event. One particular thing is that if the capture is set up to trigger an interrupt, the first captured
value should be ignored. The second captured value based on the input event should be used for the
measurement. See the figure below for an example using 10 kbps UPDI SYNCH character pulses, giving a
capture window of 200 µs for the timer.
• It is possible to readout the captured value directly after the SYNCH character, by reading the TCBn.CCMP
register or the value can be written to memory by the CPU once the capture is done.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 430
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-17. UPDI System Clock Measurement Events
Ignore first
capture event
200us
UPDI_
Input
TCB_CCMP
31.3.5
CAPT_1
CAPT_2
CAPT_3
Interbyte Delay
When loading data with the UPDI, or reading out the System Information Block, the output data will normally come
out with two IDLE bits between each transmitted byte for a multibyte transfer. Depending on the application on the
receiver side, data might be coming out too fast when there are no extra IDLE bits between each byte. By enabling
the IBDLY feature in UPDI.CTRLB, two extra Stop bits will be inserted between each byte to relax the sampling time
for the debugger. Interbyte delay works in the same way as a guard time, by inserting extra IDLE bits, but only a fixed
number of IDLE bits and only for multibyte transfers. The first transmitted byte after a direction change will be subject
to the regular Guard Time before it is transmitted, and the interbyte delay is not added to this time.
Figure 31-18. Interbyte Delay Example with LD and RPT
Too fast transm ission, no interbyte delay
RX
Debugger
Data
TX
RPT
CNT
LD*(ptr)
S
D0
GT
Debugger
Processing
B
D1
S
B
D1lots
D0
D2
S
B
D3
S
B
D4
D1lost
D2
S
B
D5
S
B
D4
Data sam pling ok with interbyte delay
RX
Debugger
Data
TX
RPT
CNT
Debugger
Processing
LD*(ptr)
GT
S IB
B
D0
D0
S IB
B
D1
D1
D2
D2
S IB
B
D3
S
B
D3
In Figure 31-18, GT denotes the Guard Time insertion, SB are Stop bits and IB is the inserted interbyte delay. The
rest of the frames are data and instructions.
31.3.6
System Information Block
The System Information Block (SIB) can be read out at any time by setting the SIB bit in the KEY instruction from
31.3.3.8 KEY - Set Activation KEY. The SIB provides a compact form of providing information for the debugger,
which is vital in identifying and setting up the proper communication channel with the part. The output of the SIB
should be interpreted as ASCII symbols. The KEY size field should be set to 16 bytes when reading out the complete
SIB, and an 8-byte size can be used to read out only the Family_ID. See Figure 31-19 for SIB format description, and
which data is available at different readout sizes.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 431
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
Figure 31-19. System Information Block Format
16 8
31.3.7
[Byte][Bits]
[6:0] [55:0]
[7][7:0]
[10:8][23:0]
[13:11][23:0]
[14][7:0]
[15][7:0]
Field Name
Family_ID
Reserved
NVM_VERSION
OCD_VERSION
RESERVED
DBG_OSC_FREQ
Enabling of KEY Protected Interfaces
Access to some internal interfaces and features are protected by the UPDI KEY mechanism. To activate a KEY, the
correct KEY data must be transmitted by using the KEY instruction as described in KEY instruction. Table 31-5
describes the available KEYs, and the condition required when doing the operation with the KEY active. There is no
requirement when shifting in the KEY, but you would, for instance, normally run a Chip Erase before enabling the
NVMPROG KEY to unlock the device for debugging. But if the NVMPROGKEY is shifted in first, it will not be reset by
shifting in the Chip Erase KEY afterwards.
Table 31-5. KEY Activation Overview
KEY Name
Description
Requirements for
Operation
Reset
Chip Erase
Start NVM Chip erase.
Clear Lockbits
None
UPDI Disable/UPDI Reset
NVMPROG
Activate NVM
Programming
Lockbits Cleared.
ASI_SYS_STATUS.NVMP
ROG set.
Programming Done/UPDI
Reset
USERROW-Write
Program User Row on
Locked part
Lockbits Set.
ASI_SYS_STATUS.UROW
PROG set.
Write to KEY status bit/
UPDI Reset
Table 31-6 gives an overview of the available KEY signatures that must be shifted in to activate the interfaces.
Table 31-6. KEY Activation Signatures
KEY Name
KEY Signature (LSB Written First)
Size
Chip Erase
0x4E564D4572617365
64 bits
NVMPROG
0x4E564D50726F6720
64 bits
USERROW-Write
0x4E564D5573267465
64 bits
31.3.7.1 Chip Erase
The following steps should be followed to issue a Chip Erase.
1. Enter the CHIPERASE KEY by using the KEY instruction. See Table 31-6 for the CHIPERASE signature.
2.
3.
4.
5.
6.
Optional: Read the Chip Erase bit in the AS Key Status register (CHIPERASE in UPDI.ASI_KEY_STATUS) to
see that the KEY is successfully activated.
Write the Reset signature into the UPDI.ASI_RESET_REQ register. This will issue a System Reset.
Write 0x00 to the ASI Reset Request register (UPDI.ASI_RESET_REQ) to clear the System Reset.
Read the Lock Status bit in the ASI System Status register (LOCKSTATUS in UPDI.ASI_SYS_STATUS).
Chip Erase is done when LOCKSTATUS == 0 in UPDI.ASI_SYS_STATUS. If LOCKSTATUS == 1, go to point
5 again.
After a successful Chip Erase, the Lockbits will be cleared, and the UPDI will have full access to the system. Until
Lockbits are cleared, the UPDI cannot access the system bus, and only CS-space operations can be performed.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 432
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
CAUTION
During Chip Erase, the BOD is forced ON (ACTIVE=0x1 in BOD.CTRLA) and uses the BOD Level from
the BOD Configuration fuse (LVL in BOD.CTRLB = LVL in FUSE.BODCFG). If the supply voltage VDD is
below that threshold level, the device is unserviceable until VDD is increased adequately.
31.3.7.2 NVM Programming
If the device is unlocked, it is possible to write directly to the NVM Controller using the UPDI. This will lead to
unpredictable code execution if the CPU is active during the NVM programming. To avoid this, the following NVM
Programming sequence should be executed.
1.
2.
Follow the Chip erase procedure as described in Chip Erase. If the part is already unlocked, this point can be
skipped.
Enter the NVMPROG KEY by using the KEY instruction. See Table 31-6 for the NVMPROG signature.
3.
4.
5.
6.
7.
Optional: Read the NVMPROG field in the KEY_STATUS register to see that the KEY has been activated.
Write the Reset signature into the ASI_RESET_REQ register. This will issue a System Reset.
Write 0x00 to the Reset signature in the ASI_RESET_REQ register to clear the System Reset.
Read NVMPROG in ASI_SYS_STATUS.
NVM Programming can start when NVMPROG == 1 in the ASI_SYS_STATUS register. If NVMPROG == 0, go
to point 6 again.
8. Write data to NVM through the UPDI.
9. Write the Reset signature into the ASI_RESET_REQ register. This will issue a System Reset.
10. Write 0x00 to the Reset signature in ASI_RESET_REQ register to clear the System Reset.
11. Programming is complete.
31.3.7.3 User Row Programming
The User Row Programming feature allows the user to program new values to the User Row (USERROW) on a
locked device. To program with this functionality enabled, the following sequence should be followed.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Enter the USERROW-Write KEY located in Table 31-6 by using the KEY instruction. See Table 31-6 for the
UROWWRITE signature.
Optional: Read the UROWWRITE bit field in UPDI.ASI_KEY_STATUS to see that the KEY has been
activated.
Write the Reset signature into the UPDI.ASI_RESET_REQ register. This will issue a System Reset.
Write 0x00 to the Reset signature in the UPDI.ASI_RESET_REQ register to clear the System Reset.
Read the UROWPROG bit in UPDI.ASI_SYS_STATUS.
User Row Programming can start when UROWPROG == 1. If UROWPROG == 0, go to point 5 again.
The writable area has a size of one EEPROM page, 32 bytes, and it is only possible to write User Row data to
the first 32 byte addresses of the RAM. Addressing outside this memory range will result in a non-executed
write. The data will map 1:1 with the User Row space when the data is copied into the User Row upon
completion of the Programming sequence.
When all User Row data has been written to the RAM, write the UROWWRITEFINAL bit in
UPDI.ASI_SYS_CTRLA.
Read the UROWPROG bit in UPDI.ASI_SYS_STATUS.
The User Row Programming is completed when UROWPROG == 0. If UROWPROG == 1, go to point 9 again.
Write the UROWWRITE bit in UPDI.ASI_KEY_STATUS.
Write the Reset signature into the UPDI.ASI_RESET_REQ register. This will issue a System Reset.
Write 0x00 to the Reset signature in the UPDI.ASI_RESET_REQ register to clear the System Reset.
User Row Programming is complete.
It is not possible to read back data from the SRAM in this mode. Only writing to the first 32 bytes of the SRAM is
allowed.
31.3.8
Events
The UPDI is connected to the Event System (EVSYS) as described in the register Asynchronous Channel n
Generator Selection.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 433
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
The UPDI can generate the following output events:
•
SYNCH Character Positive Edge Event
This event is set on the UPDI clock for each detected positive edge in the SYNCH character, and it is not possible to
disable this event from the UPDI. The recommended application for this event is system clock frequency
measurement through the UPDI. Section 31.3.4 System Clock Measurement with UPDI provides the details on how
to set up the system for this operation.
Related Links
15. Event System (EVSYS)
31.3.9
Sleep Mode Operation
The UPDI physical layer runs independently of all Sleep modes and the UPDI is always accessible for a connected
debugger independent of the device Sleep mode. If the system enters a Sleep mode that turns the CPU clock OFF,
the UPDI will not be able to access the system bus and read memories and peripherals. The UPDI physical layer
clock is unaffected by the Sleep mode settings, as long as the UPDI is enabled. By reading the INSLEEP bit in
UPDI.ASI_SYS_STATUS it is possible to monitor if the system domain is in Sleep mode. The INSLEEP bit is set if the
system is in IDLE Sleep mode or deeper.
It is possible to prevent the system clock from stopping when going into Sleep mode, by writing the CLKREQ bit in
UPDI.ASI_SYS_CTRL to '1'. If this bit is set, the system Sleep mode state is emulated, and it is possible for the UPDI
to access the system bus and read the peripheral registers even in the deepest Sleep modes.
CLKREQ in UPDI.ASI_SYS_CTRL is by default '1', which means that the default operation is keeping the system
clock on during Sleep modes.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 434
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.4
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
...
0x06
0x07
0x08
0x09
STATUSA
STATUSB
CTRLA
CTRLB
7:0
7:0
7:0
7:0
ASI_KEY_STATUS
ASI_RESET_REQ
ASI_CTRLA
7:0
7:0
7:0
0x0A
ASI_SYS_CTRLA
7:0
0x0B
0x0C
ASI_SYS_STATUS
ASI_CRC_STATUS
7:0
7:0
31.5
UPDIREV[3:0]
IBDLY
PARD
DTD
NACKDIS
RSD
CCDETDIS
PESIG[2:0]
GTVAL[2:0]
UPDIDIS
Reserved
UROWWRITE NVMPROG CHIPERASE
RSTREQ[7:0]
RSTSYS
INSLEEP
UPDICLKSEL[1:0]
UROWWRITE
CLKREQ
_FINAL
NVMPROG UROWPROG
LOCKSTATUS
CRC_STATUS[2:0]
Register Description
These registers are readable only through the UPDI with special instructions and are NOT readable through the CPU.
Registers at offset addresses 0x0-0x3 are the UPDI Physical configuration registers.
Registers at offset addresses 0x4-0xC are the ASI level registers.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 435
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.1
Status A
Name:
Offset:
Reset:
Property:
Bit
7
STATUSA
0x00
0x10
-
6
5
4
R
0
R
1
3
2
1
0
UPDIREV[3:0]
Access
Reset
R
0
R
0
Bits 7:4 – UPDIREV[3:0] UPDI Revision
These bits are read-only and contain the revision of the current UPDI implementation.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 436
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.2
Status B
Name:
Offset:
Reset:
Property:
Bit
STATUSB
0x01
0x00
-
7
6
5
4
3
Access
Reset
2
R
0
1
PESIG[2:0]
R
0
0
R
0
Bits 2:0 – PESIG[2:0] UPDI Error Signature
These bits describe the UPDI Error Signature and are set when an internal UPDI error condition occurs. The PESIG
field is cleared on a read from the debugger.
Table 31-7. Valid Error Signatures
PESIG[2:0] Error Type
Error Description
0x0
No error
No error detected (Default)
0x1
Parity error
Wrong sampling of the parity bit
0x2
Frame error
Wrong sampling of frame Stop bits
0x3
Access Layer Time-out Error UPDI can get no data or response from the Access layer. Examples of
error cases are system domain in Sleep or system domain Reset.
0x4
Clock Recovery error
Wrong sampling of frame Start bit
0x5
-
Reserved
0x6
Reserved
Reserved
0x7
Contention error
Signalize Driving Contention on the UPDI RXD/TXD line
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 437
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.3
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
IBDLY
R/W
0
CTRLA
0x02
0x00
-
6
5
PARD
R/W
0
4
DTD
R/W
0
3
RSD
R/W
0
2
R/W
0
1
GTVAL[2:0]
R/W
0
0
R/W
0
Bit 7 – IBDLY Inter-Byte Delay Enable
Writing a '1' to this bit enables a fixed inter-byte delay between each data byte transmitted from the UPDI when doing
multi-byte LD(S). The fixed length is two IDLE characters. Before the first transmitted byte,the regular GT delay used
for direction change will be used.
Bit 5 – PARD Parity Disable
Writing this bit to '1' will disable parity detection in the UPDI by ignoring the Parity bit. This feature is recommended
only during testing.
Bit 4 – DTD Disable Time-out Detection
Setting this bit disables the time-out detection on the PHY layer, which requests a response from the ACC layer
within a specified time (65536 UPDI clock cycles).
Bit 3 – RSD Response Signature Disable
Writing a '1' to this bit will disable any response signatures generated by the UPDI. This is to reduce the protocol
overhead to a minimum when writing large blocks of data to the NVM space. Disabling the Response Signature
should be used with caution, and only when the delay experienced by the UPDI when accessing the system bus is
predictable, otherwise loss of data may occur.
Bits 2:0 – GTVAL[2:0] Guard Time Value
This bit field selects the Guard Time Value that will be used by the UPDI when the transmission mode switches from
RX to TX. The guard time is equal to the baud rate used in 1-Wire mode.
Value
Description
0x0
UPDI Guard Time: 128 cycles (default)
0x1
UPDI Guard Time: 64 cycles
0x2
UPDI Guard Time: 32 cycles
0x3
UPDI Guard Time: 16 cycles
0x4
UPDI Guard Time: 8 cycles
0x5
UPDI Guard Time: 4 cycles
0x6
UPDI Guard Time: 2 cycles
0x7
GT off (no extra Idle bits inserted)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 438
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.4
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x03
0x00
-
6
Access
Reset
5
4
NACKDIS
R
0
3
CCDETDIS
R
0
2
UPDIDIS
R
0
1
0
Bit 4 – NACKDIS Disable NACK Response
Writing this bit to '1' disables the NACK signature sent by the UPDI if a System Reset is issued during an ongoing
LD(S) and ST(S) operation.
Bit 3 – CCDETDIS Collision and Contention Detection Disable
If this bit is written to '0', contention detection is enabled for the 1W mode. This means that the UPDI can detect a
collision in an ongoing 1-Wire transmission.
Bit 2 – UPDIDIS UPDI Disable
Writing a '1' to this bit disables the UPDI PHY interface. The clock request from the UPDI is lowered, and the UPDI is
reset. All UPDI PHY configurations and KEYs will be reset when the UPDI is disabled.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 439
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.5
ASI Key Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_KEY_STATUS
0x07
0x00
-
6
Access
Reset
5
UROWWRITE
R
0
4
NVMPROG
R
0
3
CHIPERASE
R
0
2
1
0
Bit 5 – UROWWRITE User Row Write Key Status
This bit is set to '1' if the UROWWRITE KEY is active. Otherwise, this bit reads as zero.
Bit 4 – NVMPROG NVM Programming
This bit is set to '1' if the NVMPROG KEY is active. This bit is automatically reset after the programming sequence is
done. Otherwise, this bit reads as zero.
Bit 3 – CHIPERASE Chip Erase
This bit is set to '1' if the CHIPERASE KEY is active. This bit will automatically be reset when the Chip Erase
sequence is completed. Otherwise, this bit reads as zero.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 440
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.6
ASI Reset Request
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
ASI_RESET_REQ
0x08
0x00
-
7
6
5
R/W
0
R/W
0
R/W
0
4
3
RSTREQ[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – RSTREQ[7:0] Reset Request
A Reset is signalized to the System when writing the Reset signature 0x59h to this address.
Writing any other signature to this register will clear the Reset.
When reading this register, reading bit RSTREQ[0] will tell if the UPDI is holding an active Reset on the system. If this
bit is '1', the UPDI has an active Reset request to the system. All other bits will read as '0'.
The UPDI will not be reset when issuing a System Reset from this register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 441
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.7
ASI Control A
Name:
Offset:
Reset:
Property:
Bit
7
ASI_CTRLA
0x09
0x02
-
6
5
4
3
Access
Reset
2
1
0
UPDICLKSEL[1:0]
R/W
R/W
1
1
Bits 1:0 – UPDICLKSEL[1:0] UPDI Clock Select
Writing these bits select the UPDI clock output frequency. Default setting after Reset and enable is 4 MHz. Any other
clock output selection is only recommended when the BOD is at the highest level. For all other BOD settings, the
default 4 MHz selection is recommended.
Value
Description
0x0
Reserved
0x1
16 MHz UPDI clock
0x2
8 MHz UPDI clock
0x3
4 MHz UPDI clock (Default Setting)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 442
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.8
ASI System Control A
Name:
Offset:
Reset:
Property:
ASI_SYS_CTRLA
0x0A
0x00
-
Bit
7
6
5
4
3
2
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
1
UROWWRITE_
FINAL
R/W
0
0
CLKREQ
R/W
0
Bit 1 – UROWWRITE_FINAL User Row Programming Done
This bit should be written through the UPDI when the user row data has been written to the RAM. Writing this bit will
start the process of programming the user row data to the Flash.
If this bit is written before the User Row code is written to RAM by the UPDI, the CPU will progress without the written
data.
This bit is only writable if the Userrow-write KEY is successfully decoded.
Bit 0 – CLKREQ Request System Clock
If this bit is written to '1', the ASI is requesting the system clock, independent of system Sleep modes. This makes it
possible for the UPDI to access the ACC layer, also if the system is in Sleep mode.
Writing a zero to this bit will lower the clock request.
This bit will be reset when the UPDI is disabled.
This bit is set by default when the UPDI is enabled in any mode (Fuse, 12V).
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 443
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.9
ASI System Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_SYS_STATUS
0x0B
0x01
-
6
Access
Reset
5
RSTSYS
R
0
4
INSLEEP
R
0
3
NVMPROG
R
0
2
UROWPROG
R
0
1
0
LOCKSTATUS
R
1
Bit 5 – RSTSYS System Reset Active
If this bit is set, there is an active Reset on the system domain. If this bit is cleared, the system is not in Reset.
This bit is cleared on read.
A Reset held from the ASI_RESET_REQ register will also affect this bit.
Bit 4 – INSLEEP System Domain in Sleep
If this bit is set, the system domain is in IDLE or deeper Sleep mode. If this bit is cleared, the system is not in Sleep.
Bit 3 – NVMPROG Start NVM Programming
If this bit is set, NVM Programming can start from the UPDI.
When the UPDI is done, it must reset the system through the UPDI Reset register.
Bit 2 – UROWPROG Start User Row Programming
If this bit is set, User Row Programming can start from the UPDI.
When the UPDI is done, it must write the UROWWRITE_FINAL bit in ASI_SYS_CTRLA.
Bit 0 – LOCKSTATUS NVM Lock Status
If this bit is set, the device is locked. If a Chip Erase is done, and the Lockbits are cleared, this bit will read as zero.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 444
ATtiny202/204/402/404/406 Automotiv...
Unified Program and Debug Interface (UPDI)
31.5.10 ASI CRC Status
Name:
Offset:
Reset:
Property:
Bit
7
ASI_CRC_STATUS
0x0C
0x00
-
6
5
4
3
Access
Reset
2
R
0
1
CRC_STATUS[2:0]
R
0
0
R
0
Bits 2:0 – CRC_STATUS[2:0] CRC Execution Status
These bits signalize the status of the CRC conversion. The bits are one-hot encoded.
Value
Description
0x0
Not enabled
0x1
CRC enabled, busy
0x2
CRC enabled, done with OK signature
0x4
CRC enabled, done with FAILED signature
Other
Reserved
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 445
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
32.
Electrical Characteristics
32.1
Disclaimer
All typical values are measured at T = 25°C and VDD = 3V unless otherwise specified. All minimum and maximum
values are valid across operating temperature and voltage unless otherwise specified.
32.2
Absolute Maximum Ratings
Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 32-1. Absolute Maximum Ratings
Symbol Description
VDD
Power supply voltage
IVDD
Current into a VDD pin
IGND
Conditions
Current out of a GND pin
Min. Max.
Unit
-0.5 6
V
T = [-40, 85]°C
-
200
mA
T = [85, 125]°C
-
100
mA
T = [-40, 85]°C
-
200
mA
T = [85, 125]°C
-
100
mA
VRST
RESET pin voltage with respect to GND
-0.5 13
V
VPIN
Pin voltage with respect to GND
-0.5 VDD+0.5 V
IPIN
I/O pin sink/source current
-40
40
mA
Ic1
(1)
I/O pin injection current except RESET pin
Vpin < GND-0.6V or 5.5V < Vpin ≤
6.1V
4.9V < VDD ≤ 5.5V
-1
1
mA
Ic2(1)
I/O pin injection current except RESET pin
Vpin < GND-0.6V or Vpin ≤ 5.5V
VDD ≤ 4.9V
-15
15
mA
Ictot
Sum of I/O pin injection current except RESET
pin
-45
45
mA
Tstorage
Storage temperature
-65
150
°C
Note:
1.
– If VPIN is lower than GND-0.6V, then a current limiting resistor is required. The negative DC injection
current limiting resistor is calculated as R = (GND-0.6V – VPIN)/ICn.
– If VPIN is greater than VDD+0.6V, then a current limiting resistor is required. The positive DC injection
current limiting resistor is calculated as R = (VPIN-(VDD+0.6))/ICn.
CAUTION
VRSTMAX = 13V
Care should be taken to avoid overshoot (overvoltage) when connecting the RESET pin to a 12V source.
Exposing the pin to a voltage above the rated absolute maximum can activate the pin’s ESD protection
circuitry, which will remain activated until the voltage has been brought below approximately 10V. A 12V
driver can keep the ESD protection in an activated state (if activated by an overvoltage condition) while
driving currents through it, potentially causing permanent damage to the part.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 446
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
32.3
General Operating Ratings
The device must operate within the ratings listed in this section for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 32-2. General Operating Conditions
Symbol
Description
VDD
Operating supply voltage
T
Operating temperature
Condition
range(1)
Min.
Max.
Unit
2.7(2)
5.5
V
-40
125
°C
Note:
1. Refer to the device ordering codes for the device temperature range.
2. Operation is ensured down to 2.7V or BOD triggering level, VBOD. VBOD may be below minimum Operating
Supply Voltage for some devices. Where this is the case, the device is tested down to VDD = VBOD during
production.
– During Chip Erase, the BOD is forced ON. If the supply voltage VDD is below the configured VBOD, the
Chip Erase will fail. See 31.3.7.1 Chip Erase.
Table 32-3. Operating Voltage and Frequency
Symbol
Description
Condition
Min.
Max.
Unit
CLK_CPU
Operating system clock frequency
VDD = [2.7, 5.5]V
T = [-40, 125]°C(1)
0
8
MHz
VDD = [4.5, 5.5]V
T = [-40, 125]°C(2)
0
16
Note:
1. Operation ensured down to BOD triggering level, VBOD with BODLEVEL2.
2. Operation ensured down to BOD triggering level, VBOD with BODLEVEL7.
The maximum CPU clock frequency depends on VDD. As shown in the following figure, the Maximum Frequency vs.
VDD is linear between 2.7V < VDD < 4.5V.
Figure 32-1. Maximum Frequency vs. VDD for [-40, 125]°C
16 MHz
8 MHz
Safe Operating Area
2.7V
32.4
4.5V
5.5V
Power Consumption
The values are measured power consumption under the following conditions, except where noted:
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 447
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
•
•
•
•
VDD = 3V
T = 25°C
OSC20M (16 MHz setting) used as the system clock source, except where otherwise specified
System power consumption measured with peripherals disabled and without I/O drive
Table 32-4. Power Consumption in Active and Idle Mode
Mode
Description
Condition
Typ. Max.
Unit
Active
Active power consumption
CLK_CPU = 16 MHz
VDD = 5V
7.9
10
mA
CLK_CPU = 8 MHz (div2)
VDD = 5V
4.0
5.5
mA
VDD = 3V
2.2
3.5
mA
VDD = 5V
19
35
µA
VDD = 3V
11
25
µA
CLK_CPU = 16 MHz
VDD = 5V
3.4
5
mA
CLK_CPU = 8 MHz (div2)
VDD = 5V
1.7
2.5
mA
VDD = 3V
0.9
1.5
mA
VDD = 5V
8.0
20
µA
VDD = 3V
4.0
15
µA
CLK_CPU = 32.768 kHz (OSCULP32K)
Idle
Idle power consumption
CLK_CPU = 32.768 kHz (OSCULP32K)
Table 32-5. Power consumption in Power-down, Standby and Reset mode
32.5
Mode
Description
Condition
Standby
Standby power
consumption
RTC running at 1.024
kHz from internal
OSCULP32K
Power
Down/
Standby
Power down/Standby
power consumption are
the same when all
peripherals are stopped
Reset
Reset power
consumption
Typ.
25°C
Max.
85°C
Max.
125°C
Unit
VDD = 3V 0.71
6.0
8.0
µA
All peripherals stopped
VDD = 3V 0.1
5.0
7.0
µA
Reset line pulled down
VDD = 3V 100
-
-
µA
Wake-Up Time
Wake-up time from Sleep mode is measured from the edge of the wake-up signal to the first instruction executed.
Operating conditions:
• VDD = 3V
• T = 25°C
• OSC20M as the system clock source, unless otherwise specified
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 448
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
Table 32-6. Start-Up, Reset, and Wake-Up Time from OSC20M
Symbol Description
twakeup
Condition
Start-up time from any Reset release
Wake-up from Idle mode
-
200
-
OSC20M @ 16 MHz; VDD = 5V -
1.2
-
OSC20M @ 8 MHz; VDD = 3V
-
2.4
-
-
10
-
Wake-up from Standby and Power-down mode
32.6
Min. Typ. Max. Unit
µs
Peripherals Power Consumption
The table below can be used to calculate the additional current consumption for the different I/O peripherals in the
various operating modes.
Operating conditions:
• VDD=3V
• T=25°C
• OSC20M at 1 MHz used as the system clock source, except where otherwise specified.
Table 32-7. Peripherals Power Consumption
Peripheral
Conditions
Typ.(1)
Unit
BOD
Continuous
19
µA
Sampling @ 1 kHz
1
TCA
16-bit count @ 1 MHz
13
µA
TCB
16-bit count @ 1 MHz
7.5
µA
RTC
16-bit count @ OSCULP32K
1
µA
WDT (including OSCULP32K)
1
µA
OSC20M
125
µA
AC
45
µA
50 ksps
325
µA
100 ksps
340
µA
0.5
µA
ADC
OSCULP32K
USART
Enable @ 9600 Baud
13
µA
SPI (Master)
Enable @ 100 kHz
2
µA
TWI (Master)
Enable @ 100 kHz
24
µA
TWI (Slave)
Enable @ 100 kHz
17
µA
Flash programming
Erase Operation
1.5
mA
Write Operation
3.0
Note:
1. Current consumption of the module only. To calculate the total power consumption of the system, add this
value to the base power consumption as listed in Power Consumption.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 449
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
32.7
BOD and POR Characteristics
Table 32-8. Power Supply Characteristics
Symbol
Description
SRON
Power-on Slope
Condition
Min.
Typ.
Max.
Unit
-
-
100
V/ms
Table 32-9. Power-on Reset (POR) Characteristics
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
VPOR
POR threshold voltage on VDD falling
VDD falls/rises at 0.5 V/ms or slower
0.8
-
1.6
V
1.4
-
1.8
POR threshold voltage on VDD rising
Table 32-10. Brown-out Detection (BOD) Characteristics
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
VBOD
BOD triggering level (falling/rising)
BODLEVEL7
3.9
4.2
4.5
V
BODLEVEL2
2.4
2.6
2.9
Percentage above the selected BOD level
-
4
-
Interrupt level 1
-
13
-
Interrupt level 2
-
25
-
BODLEVEL7
-
80
-
BODLEVEL2
-
40
-
Continuous
-
7
-
µs
Sampled, 1 kHz
-
1
-
ms
Sampled, 125 Hz
-
8
-
Time from enable to ready
-
40
-
VINT
VHYS
TBOD
Tstart
32.8
Interrupt level 0
Hysteresis
Detection time
Start-up time
%
mV
µs
External Reset Characteristics
Table 32-11. External Reset Characteristics
32.9
Symbol
Description
VHVRST
Condition
Min.
Typ.
Max.
Unit
Ensured detection for a high-voltage Reset
11.5
-
12.5
V
VRST_VIH
Input high-voltage for RESET
0.8×VDD
-
VDD+0.2
VRST_VIL
Input low-voltage for RESET
-0.2
-
0.2×VDD
tRST
Minimum pulse-width on RESET pin
-
-
2.5
µs
RRST
RESET pull-up resistor
20
-
60
kΩ
VReset = 0V
Oscillators and Clocks
Operating conditions:
• VDD = 3V, except where specified otherwise
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 450
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
Table 32-12. Internal Oscillator (OSC20M) Characteristics
Symbol
Description
Condition
fOSC20M
Accuracy with 16 MHz frequency selection
Factory calibrated
Min.
Typ.
Max.
Unit
T = 25°C, 3.0V
-3.0
-
3.0
%
T = [0, 70]°C,
VDD = [2.7, 3.6]V(2)
-4.0
-
4.0
Full operation range(2)
-5.0
-
5.0
14.5
-
17.5
MHz
OSC20M(1) = 16 MHz
fCAL
User calibration range
%CAL
Calibration step size
-
1.5
-
%
DC
Duty cycle
-
50
-
%
Tstart
Start-up time
-
8
-
µs
Within 2% accuracy
Note:
1. Oscillator frequencies above speed specification must be divided so that the CPU clock always is within
specification.
2. These values are based on characterization and not covered by production test limits.
Table 32-13. 32.768 kHz Internal Oscillator (OSCULP32K) Characteristics
Symbol
Description
Condition
Condition
Min.
Typ.
Max.
Unit
fOSCULP32K
Accuracy
Factory calibrated
T = 25°C, 3.0V
-3
-
3
%
T = [0, 70]°C,
VDD = [2.7, 3.6]V(1)
-10
-
10
Full operation range(1)
-30
-
30
-
50
-
%
-
250
-
µs
DC
Duty cycle
Tstart
Start-up time
Note:
1. These values are based on characterization and not covered by production test limits.
Figure 32-2. External Clock Waveform Characteristics
V IH1
V IL1
Table 32-14. External Clock Characteristics
Symbol
Description
Condition
VDD = [2.7, 5.5]V
VDD = [4.5, 5.5]V
Min.
Max.
Min.
Max.
Unit
fCLCL
Frequency
0.0
8.0
0.0
16.0
MHz
tCLCL
Clock period
125
-
62.5
-
ns
tCHCX
High time
50
-
25
-
ns
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 451
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
...........continued
Symbol
tCLCX
Description
Condition
Low time
VDD = [2.7, 5.5]V
VDD = [4.5, 5.5]V
Min.
Max.
Min.
Max.
50
-
25
-
Unit
ns
Related Links
11.3.4.1.1 16 MHz Oscillator (OSC20M)
32.10
I/O Pin Characteristics
Table 32-15. I/O Pin Characteristics (TA = [-40, 105]°C, VDD = [2.7, 5.5]V Unless Otherwise Stated)
Symbol
Description
VIL
Min.
Typ.
Max.
Unit
Input low-voltage, except RESET pin as I/O
-0.2
-
0.3×VDD
V
VIH
Input high-voltage, except RESET pin as I/O
0.7×VDD
-
VDD+0.2V
V
IIH / IIL
I/O pin Input leakage current, except RESET pin as I/O
VDD = 5.5V, Pin high
-
< 0.05
-
µA
VDD = 5.5V, Pin low
-
< 0.05
-
VDD = 3.0V, IOL = 7.5 mA
-
-
0.6
VDD = 5.0V, IOL = 15 mA
-
-
1
VDD = 3.0V, IOH = 7.5 mA
2.4
-
-
VDD = 5.0V, IOH = 15 mA
4
-
-
Maximum combined I/O sink current per pin group(1)
-
-
100
Maximum combined I/O source current per pin group(1)
-
-
100
VIL2
Input low-voltage on RESET pin as I/O
-0.2
-
0.3×VDD
V
VIH2
Input high-voltage on RESET pin as I/O
0.7×VDD
-
VDD+0.2V
V
VOL2
I/O pin drive strength on RESET pin as I/O
VDD = 3.0V, IOL = 0.25 mA
-
-
0.6
V
VDD = 5.0V, IOL = 0.5 mA
-
-
1
VDD = 3.0V, IOH = 0.25 mA
2.4
-
-
VDD = 5.0V, IOH = 0.5 mA
4
-
-
VDD = 3.0V, load = 20 pF
-
2.5
-
VDD = 5.0V, load = 20 pF
-
1.5
-
VDD = 3.0V, load = 20 pF
-
2.0
-
VDD = 5.0V, load = 20 pF
-
1.3
-
VOL
VOH
Itotal
VOH2
tRISE
tFALL
I/O pin drive strength
I/O pin drive strength
I/O pin drive strength on RESET pin as I/O
Rise time
Fall time
Condition
V
V
mA
V
ns
ns
Cpin
I/O pin capacitance except TWI pins
-
3
-
pF
Cpin
I/O pin capacitance on TWI pins
-
10
-
pF
Rp
Pull-up resistor
20
35
50
kΩ
Note:
1. Pin group A (PA[7:0]), pin group B (PB[7:0]). The combined continuous sink/source current for all I/O ports
should not exceed the limits.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 452
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
32.11
USART
Figure 32-3. USART in SPI Mode - Timing Requirements in Master Mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Table 32-16. USART in SPI Master Mode - Timing Characteristics
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
fSCK
SCK clock frequency
Master
-
-
10
MHz
tSCK
SCK period
Master
100
-
-
ns
tSCKW
SCK high/low width
Master
-
0.5×tSCK
-
ns
tSCKR
SCK rise time
Master
-
2.7
-
ns
tSCKF
SCK fall time
Master
-
2.7
-
ns
tMIS
MISO setup to SCK
Master
-
10
-
ns
tMIH
MISO hold after SCK
Master
-
10
-
ns
tMOS
MOSI setup to SCK
Master
-
0.5×tSCK
-
ns
tMOH
MOSI hold after SCK
Master
-
1.0
-
ns
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 453
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
32.12
SPI
Figure 32-4. SPI - Timing Requirements in Master Mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSb
LSb
tMOH
tMOH
MOSI
(Data Output)
MSb
LSb
Figure 32-5. SPI - Timing Requirements in Slave Mode
SS
tSSCKR
tSSS
tSSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
MSb
tSOSS
MISO
(Data Output)
tSSCK
LSb
tSOS
tSOSH
MSb
LSb
Table 32-17. SPI - Timing Characteristics
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
fSCK
SCK clock frequency
Master
-
-
10
MHz
tSCK
SCK period
Master
100
-
-
ns
tSCKW
SCK high/low width
Master
-
0.5×tSCK
-
ns
tSCKR
SCK rise time
Master
-
2.7
-
ns
tSCKF
SCK fall time
Master
-
2.7
-
ns
tMIS
MISO setup to SCK
Master
-
10
-
ns
tMIH
MISO hold after SCK
Master
-
10
-
ns
tMOS
MOSI setup to SCK
Master
-
0.5×tSCK
-
ns
tMOH
MOSI hold after SCK
Master
-
1.0
-
ns
fSSCK
Slave SCK clock frequency
Slave
-
-
5
MHz
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 454
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
...........continued
32.13
Symbol
Description
Condition
Min.
Typ.
Max.
Unit
tSSCK
Slave SCK Period
Slave
4×tCLK_PER
-
-
ns
tSSCKW
SCK high/low width
Slave
2×tCLK_PER
-
-
ns
tSSCKR
SCK rise time
Slave
-
-
1600
ns
tSSCKF
SCK fall time
Slave
-
-
1600
ns
tSIS
MOSI setup to SCK
Slave
3.0
-
-
ns
tSIH
MOSI hold after SCK
Slave
tCLK_PER
-
-
ns
tSSS
SS setup to SCK
Slave
21
-
-
ns
tSSH
SS hold after SCK
Slave
20
-
-
ns
tSOS
MISO setup to SCK
Slave
-
8.0
-
ns
tSOH
MISO hold after SCK
Slave
-
13
-
ns
tSOSS
MISO setup after SS low
Slave
-
11
-
ns
tSOSH
MISO hold after SS low
Slave
-
8.0
-
ns
TWI
Figure 32-6. TWI - Timing Requirements
t of
t HIGH
tr
t LOW
t LOW
SCL
t SU;STA
t HD;STA
t HD;DAT
t SU;DAT
t SU;STO
SDA
t BUF
Table 32-18. TWI - Timing Characteristics
Symbol Description
Condition
Min.
Typ. Max.
Unit
fSCL
SCL clock frequency
Max. frequency requires system
clock at 10 MHz, which, in turn,
requires VDD = [2.7, 5.5]V and T =
[-40, 105]°C
0
-
1000
kHz
VIH
Input high voltage
0.7×VDD
-
-
V
VIL
Input low voltage
-
-
0.3×VDD
V
VHYS
Hysteresis of Schmitt
trigger inputs
0.1×VDD
0.4×VDD
V
VOL
Output low voltage
V
IOL
Low-level output
current
© 2019 Microchip Technology Inc.
Iload = 20 mA, Fast mode+
-
-
0.2×VDD
Iload = 3 mA, Normal mode, VDD >
2.7V
-
-
0.4
fSCL ≤ 400 kHz, VOL = 0.4V
3
-
-
fSCL ≤ 1 MHz, VOL = 0.4V
20
-
-
Complete Datasheet
mA
DS40002159A-page 455
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
...........continued
Symbol Description
Condition
Min.
Typ. Max.
Unit
CB
fSCL ≤ 100 kHz
-
-
400
pF
fSCL ≤ 400 kHz
-
-
400
fSCL ≤ 1 MHz
-
-
550
fSCL ≤ 100 kHz
-
-
1000
fSCL ≤ 400 kHz
20
-
300
fSCL ≤ 1 MHz
-
-
120
fSCL ≤ 400
kHz
20×(VDD/
5.5V)
-
250
fSCL ≤ 1 MHz
20×(VDD/
5.5V)
-
120
tR
tOF
Capacitive load for
each bus line
Rise time for both
SDA and SCL
Output fall time from
VIHmin to VILmax
10 pF < Capacitance
of bus line < 400 pF
ns
ns
tSP
Spikes suppressed
by Input filter
0
-
50
ns
IL
Input current for each 0.1×VDD < VI < 0.9×VDD
I/O pin
-
-
1
µA
CI
Capacitance for each
I/O pin
-
-
10
pF
RP
Value of pull-up
resistor
(VDDVOL(max)) /IO
-
1000 ns/
(0.8473×CB)
Ω
fSCL ≤ 100 kHz
L
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
Hold time (repeated)
Start condition
Low period of SCL
Clock
High period of SCL
Clock
Setup time for a
repeated Start
condition
Data hold time
© 2019 Microchip Technology Inc.
fSCL ≤ 400 kHz
-
-
300 ns/
(0.8473×CB)
fSCL ≤ 1 MHz
-
-
120 ns/
(0.8473×CB)
fSCL ≤ 100 kHz
4.0
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
fSCL ≤ 100 kHz
4.7
-
-
fSCL ≤ 400 kHz
1.3
-
-
fSCL ≤ 1 MHz
0.5
-
-
fSCL ≤ 100 kHz
4.0
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
fSCL ≤ 100 kHz
4.7
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
fSCL ≤ 100 kHz
0
-
3.45
fSCL ≤ 400 kHz
0
-
0.9
fSCL ≤ 1 MHz
0
-
0.45
Complete Datasheet
µs
µs
µs
µs
µs
DS40002159A-page 456
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
...........continued
Symbol Description
Condition
Min.
Typ. Max.
Unit
tSU;DAT
fSCL ≤ 100 kHz
250
-
-
ns
fSCL ≤ 400 kHz
100
-
-
fSCL ≤ 1 MHz
50
-
-
fSCL ≤ 100 kHz
4
-
-
fSCL ≤ 400 kHz
0.6
-
-
fSCL ≤ 1 MHz
0.26
-
-
fSCL ≤ 100 kHz
4.7
-
-
fSCL ≤ 400 kHz
1.3
-
-
fSCL ≤ 1 MHz
0.5
-
-
tSU;STO
tBUF
32.14
Data setup time
Setup time for Stop
condition
Bus free time
between a Stop and
Start condition
µs
µs
VREF
Table 32-19. Internal Voltage Reference Characteristics
Symbol
Description
Min.
Typ.
Max.
Unit
tstart
Start-up time
-
25
-
µs
VDDINT055V
Power supply voltage range for INT055V
2.7
-
5.5
V
VDDINT11V
Power supply voltage range for INT11V
2.7
-
5.5
VDDINT15V
Power supply voltage range for INT15V
2.7
-
5.5
VDDINT25V
Power supply voltage range for INT25V
2.9
-
5.5
VDDINT43V
Power supply voltage range for INT43V
4.75
-
5.5
Table 32-20. ADC Internal Voltage Reference Characteristics(1)
Symbol(2)
Description
Condition
Min.
INT11V
Internal reference voltage
VDD = [2.7V, 3.6V]
T = [0, 105]°C
INT055V
INT15V
INT25V
Internal reference voltage
INT055V
INT11V
INT15V
INT25V
INT43V
Internal reference voltage
Typ.
Max.
Unit
-2.0
2.0
%
VDD = [2.7V, 3.6V]
T = [0, 105]°C
-3.0
3.0
VDD = [2.7V, 5.5V]
T = [-40, 125]°C
-5.0
5.0
Note:
1. These values are based on characterization and not covered by production test limits.
2. The symbols INTxxV refer to the respective values of the ADC0REFSEL and DAC0REFSEL bit fields in the
VREF.CTRLA register.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 457
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
Table 32-21. AC Internal Voltage Reference Characteristics(1)
Symbol(2)
Description
Condition
Min.
INT055V
INT11V
INT15V
INT25V
Internal reference voltage
VDD = [2.7V, 3.6V]
T = [0, 105]°C
INT055V
INT11V
INT15V
INT25V
INT43V
Internal reference voltage
VDD = [2.7V, 5.5V]
T = [-40, 125]°C
Typ.
Max.
Unit
-3.0
3.0
%
-5.0
5.0
Note:
1. These values are based on characterization and not covered by production test limits.
2. The symbols INTxxV refer to the respective values of the ADC0REFSEL and DAC0REFSEL bit fields in the
VREF.CTRLA register.
32.15
ADC
Operating conditions:
• VDD = 2.7V to 5.5V
• Temperature = -40°C to 125°C
• DUTYCYC = 25%
• CLKADC = 13 × fADC
• SAMPCAP is 10 pF for 0.55V reference, while it is set to 5 pF for VREF ≥ 1.1V
• Applies for all allowed combinations of VREF selections and Sample Rates unless otherwise stated
Table 32-22. Power Supply, Reference, and Input Range
Symbol
Description
VDD
Supply voltage
VREF
Reference voltage
CIN
Input capacitance
VIN
Input voltage range
IBAND
Input bandwidth
Conditions
Min.
Typ.
Max.
Unit
2.7
-
5.5
V
REFSEL = Internal reference
0.55
-
VDD-0.4
V
REFSEL = VDD
2.7
-
5.5
SAMPCAP = 5 pF
-
5
-
SAMPCAP = 10 pF
-
10
-
0
-
VREF
V
-
-
57.5
kHz
1.1V ≤ VREF
pF
Table 32-23. Clock and Timing Characteristics
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
fADC
Sample rate
1.1V ≤ VREF
15
-
115
ksps
1.1V ≤ VREF (8-bit resolution)
15
-
150
VREF = 0.55V (10 bits)
7.5
-
20
VREF = 0.55V (10 bits)
100
-
260
1.1V ≤ VREF (10 bits)
200
-
1500
1.1V ≤ VREF (8-bit resolution)
200
-
2000(1)
CLKADC
Clock frequency
© 2019 Microchip Technology Inc.
Complete Datasheet
kHz
DS40002159A-page 458
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
...........continued
Symbol
Description
Conditions
Ts
Sampling time
TCONV
Conversion time (latency)
TSTART
Start-up time
Min.
Typ.
Max.
Unit
2
2
33
CLKADC cycles
Sampling time = 2 CLKADC
8.7
-
50
µs
Internal VREF
-
22
-
µs
Note:
1. 50% duty cycle is required for clock frequencies above 1500 kHz.
Table 32-24. Accuracy Characteristics Internal Reference(2)
Symbol
Description
Res
Resolution
INL
Integral Nonlinearity
Conditions
Min.
Typ.
Max.
Unit
-
10
-
bit
fADC = 7.7 ksps
-
1.0
3.0
LSB
REFSEL =
INTERNAL or VDD
fADC = 15 ksps
-
1.0
3.0
REFSEL =
INTERNAL or VDD
fADC = 77 ksps
-
1.0
3.0
fADC = 115 ksps
-
1.2
3.0
fADC = 7.7 ksps
-
0.6
1.3
fADC = 15 ksps
-
0.4
1.2
fADC = 15 ksps
-
0.4
1.0
fADC = 77 ksps
-
0.4
1.0
fADC = 115 ksps
-
0.5
1.6
fADC = 115 ksps
-
0.9
2.0
T = [0, 105]°C
-
3
30
-
3
40
REFSEL = VDD
-
2
5
REFSEL =
INTERNAL
-
-
65
REFSEL =
INTERNAL
VREF = 0.55V
1.1V ≤ VREF
DNL(1)
Differential Nonlinearity
REFSEL =
INTERNAL
LSB
VREF = 0.55V
REFSEL =
INTERNAL
VREF = 1.1V
REFSEL =
INTERNAL or VDD
1.5V ≤ VREF
REFSEL =
INTERNAL or VDD
1.1V ≤ VREF
REFSEL =
INTERNAL
1.1V ≤ VREF
REFSEL = VDD
1.8V ≤ VREF
EABS
Absolute
accuracy
REFSEL =
INTERNAL
VREF = 1.1V
© 2019 Microchip Technology Inc.
LSB
VDD = [2.7V, 3.6V]
VDD = [2.7V, 3.6V]
Complete Datasheet
DS40002159A-page 459
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
...........continued
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
EGAIN
Gain error
REFSEL =
INTERNAL
-25
3
25
LSB
-35
3
35
REFSEL = VDD
-1
2
4
REFSEL =
INTERNAL
-60
-
60
REFSEL =
INTERNAL
-5
-0.5
2
LSB
-4
-0.5
2
LSB
T = [0, 105]°C
VDD = [2.7V, 3.6V]
VREF = 1.1V
EOFF
Offset error
VDD = [2.7V, 3.6V]
VREF = 0.55V
REFSEL =
INTERNAL
1.1V ≤ VREF
Note:
1. A DNL error of less than or equal to 1 LSB ensures a monotonic transfer function with no missing codes.
2. These values are based on characterization and not covered by production test limits.
Related Links
30.2.4 Definitions
32.16
AC
Table 32-25. Analog Comparator Characteristics
Symbol
Description
VIN
Input voltage
CIN
Input pin capacitance
VOFF
Min.
Typ.
Max.
Unit
0
-
VDD
V
PA6
-
9
-
pF
PA7, PB5, PB4
-
5
-
VIN = VDD/2
-30
±10
30
VIN = [0V, VDD]
-50
±30
50
mV
IL
Input leakage current
-
5
-
nA
TSTART
Start-up time
-
1.3
-
µs
VHYS
Hysteresis
HYSMODE = 0x0
0
0
10
mV
HYSMODE = 0x1
0
10
30
HYSMODE = 0x2
5
30
90
HYSMODE = 0x3
12
55
190
25 mV Overdrive, VDD ≥ 2.7V
-
150
-
tPD
32.17
Input offset voltage
Condition
Propagation delay
ns
UPDI Timing
UPDI Enable Sequence with UPDI PAD Enabled by Fuse(1)
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 460
ATtiny202/204/402/404/406 Automotiv...
Electrical Characteristics
1
Fuse read in. Pull-up enabled. Ready to receive init.
2
Drive low from debugger to request UPDI clock
3
UPDI clock ready; Communication channel ready.
RESET
1
2
Hi-Z
St
D0
D1
D2
D3
Handshake / BREAK
TRES
UPDI.rxd
D4
D5
D6
D7
Sp
SYNC (0x55)
(Autobaud)
(Ignore)
UPDI.txd
3
Hi-Z
Hi-Z
UPDI.txd = 0
TUPDI
debugger.
UPDI.txd
Hi-Z
Hi-Z
Debugger.txd = 0
TDeb0
Symbol
Debugger.txd = z
TDebZ
Description
Min.
Max.
Unit
TRES
Duration of Handshake/Break on RESET
10
200
µs
TUPDI
Duration of UPDI.txd = 0
10
200
µs
TDeb0
Duration of Debugger.txd = 0
0.2
1
µs
TDebZ
Duration of Debugger.txd = z
200
14000
µs
Note:
1. These parameters are for design guidance only and are not production tested.
Related Links
31.3.2.1 UPDI Enable with Fuse Override of RESET Pin
32.18
Programming Time
See the following table for typical programming times for Flash and EEPROM.
Table 32-26. Programming Times
Symbol
Typical Programming Time
Page Buffer Clear
Seven CLK_CPU cycles
Page Write
2 ms
Page Erase
2 ms
Page Erase-Write
4 ms
Chip Erase
4 ms
EEPROM Erase
4 ms
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 461
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
33.
Typical Characteristics
33.1
Power Consumption
33.1.1
Supply Currents in Active Mode for ATtiny202/204/402/404/406 Automotive
Figure 33-1. Active Supply Current vs. Frequency (1-16 MHz) at T=25°C
VDD [V]
10.0
2.7
3
3.6
4.2
5
5.5
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0
2
4
6
8
Frequency [MHz]
10
12
14
16
Figure 33-2. Active Supply Current vs. Frequency [0.1, 1.0] MHz at T=25°C
VDD [V]
600
2.7
3
3.6
4.2
5
5.5
550
500
450
400
350
300
250
200
150
100
50
0
0.0
0.1
0.2
© 2019 Microchip Technology Inc.
0.3
0.4
0.5
0.6
Frequency [MHz]
0.7
0.8
Complete Datasheet
0.9
1.0
DS40002159A-page 462
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-3. Active Supply Current vs. Temperature (f=16 MHz OSC20M)
VDD [V]
10.0
4.5
5
5.5
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-40
-20
0
20
40
Temperature [°C]
60
80
100
120
Figure 33-4. Active Supply Current vs. VDD (f=[1, 16] MHz OSC20M) at T=25°C
Frequency [MHz]
10.0
1
2
4
8
16
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
© 2019 Microchip Technology Inc.
3.5
4.0
Vdd [V]
4.5
Complete Datasheet
5.0
5.5
DS40002159A-page 463
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-5. Active Supply Current vs. VDD (f=32 KHz OSCULP32K)
Temperature [°C]
32
-40
-20
0
25
70
85
105
125
28
24
20
16
12
8
4
0
33.1.2
2.5
3.0
3.5
4.0
4.5
Vdd [V]
5.0
5.5
Supply Currents in Idle Mode for ATtiny202/204/402/404/406 Automotive
Figure 33-6. Idle Supply Current vs. Frequency (1-16 MHz) at T=25°C
VDD [V]
5.0
2.7
3
3.6
4.2
5
5.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
© 2019 Microchip Technology Inc.
6
8
Frequency [MHz]
10
12
Complete Datasheet
14
16
DS40002159A-page 464
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-7. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz) at T=25°C
VDD [V]
250
2.7
3
3.6
4.2
5
5.5
225
200
175
150
125
100
75
50
25
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency [MHz]
0.7
0.8
0.9
1.0
Figure 33-8. Idle Supply Current vs. Temperature (f=16 MHz OSC20M)
VDD [V]
5.0
4.5
5
5.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
© 2019 Microchip Technology Inc.
20
40
Temperature [°C]
60
80
Complete Datasheet
100
120
DS40002159A-page 465
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-9. Idle Supply Current vs. VDD (f=32 KHz OSCULP32K)
Temperature [°C]
20
-40
-20
0
25
70
85
105
125
18
16
14
12
10
8
6
4
2
0
33.1.3
2.5
3.0
3.5
4.0
4.5
Vdd [V]
5.0
5.5
Supply Currents in Power-Down Mode for ATtiny202/204/402/404/406 Automotive
Figure 33-10. Power-Down Mode Supply Current vs. Temperature (all functions disabled)
VDD [V]
5.0
2.7
3
3.6
4.2
5
5.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40
-20
0
© 2019 Microchip Technology Inc.
20
40
Temperature [°C]
60
80
Complete Datasheet
100
120
DS40002159A-page 466
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-11. Power-Down Mode Supply Current vs. VDD (all functions disabled)
Temperature [°C]
5.0
-40
-20
0
25
70
85
105
125
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
33.1.4
2.5
3.0
3.5
4.0
Vdd [V]
4.5
5.0
5.5
Supply Currents in Standby Mode for ATtiny202/204/402/404/406 Automotive
Figure 33-12. Standby Mode Supply Current vs. VDD (RTC Running with Internal OSCULP32K)
Temperature [°C]
10.0
-40
-20
0
25
70
85
105
125
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
© 2019 Microchip Technology Inc.
3.5
4.0
Vdd [V]
4.5
Complete Datasheet
5.0
5.5
DS40002159A-page 467
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-13. Standby Mode Supply Current vs. VDD (Sampled BOD Running at 125 Hz)
Temperature [°C]
10.0
-40
-20
0
25
70
85
105
125
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
Vdd [V]
4.5
5.0
5.5
Figure 33-14. Standby Mode Supply Current vs. VDD (Sampled BOD Running at 1 kHz)
Temperature [°C]
10.0
-40
-20
0
25
70
85
105
125
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
© 2019 Microchip Technology Inc.
3.5
4.0
Vdd [V]
4.5
Complete Datasheet
5.0
5.5
DS40002159A-page 468
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
33.2
GPIO
GPIO Input Characteristics
Figure 33-15. I/O Pin Input Hysteresis vs. VDD
Temperature [°C]
2.0
-40
0
25
70
85
105
125
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
Figure 33-16. I/O Pin Input Threshold Voltage vs. VDD (T=25°C)
Threshold
75
Vih
Vil
70
65
60
55
50
45
40
35
30
25
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 469
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-17. I/O Pin Input Threshold Voltage vs. VDD (VIH)
Temperature [°C]
75
-40
0
25
70
85
105
125
70
65
60
55
50
45
40
35
30
25
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
Figure 33-18. I/O Pin Input Threshold Voltage vs. VDD (VIL)
Temperature [°C]
75
-40
0
25
70
85
105
125
70
65
60
55
50
45
40
35
30
25
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 470
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
GPIO Output Characteristics
Figure 33-19. I/O Pin Output Voltage vs. Sink Current (VDD=3.0V)
Temperature [°C]
0.50
-40
-20
0
25
70
85
105
125
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
1
2
3
4
5
6
7
8
9
10
Sink current [mA]
Figure 33-20. I/O Pin Output Voltage vs. Sink Current (VDD=5.0V)
Temperature [°C]
1.0
-40
-20
0
25
70
85
105
125
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
Sink current [mA]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 471
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-21. I/O Pin Output Voltage vs. Sink Current (T=25°C)
Vdd [V]
1.0
3
4
5
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
Sink current [mA]
Figure 33-22. I/O Pin Output Voltage vs. Source Current (VDD=3.0V)
Temperature [°C]
3.0
-40
-20
0
25
70
85
105
125
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
0
1
2
3
4
5
6
7
8
9
10
Source current [mA]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 472
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-23. I/O Pin Output Voltage vs. Source Current (VDD=5.0V)
Temperature [°C]
5.0
-40
-20
0
25
70
85
105
125
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
0
2
4
6
8
10
12
14
16
18
20
Source current [mA]
Figure 33-24. I/O Pin Output Voltage vs. Source Current (T=25°C)
Vdd [V]
5.0
3
4
5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
12
14
16
18
20
Source current [mA]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 473
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
GPIO Pull-Up Characteristics
Figure 33-25. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD=3.0V)
Temperature [°C]
3.0
-40
-20
0
25
70
85
105
125
2.8
2.5
2.3
2.0
1.8
1.5
1.3
1.0
0
5
10
15
20
25
30
35
40
45
50
Pull-up resistor current [µA]
Figure 33-26. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VDD=5.0V)
Temperature [°C]
5.0
-40
-20
0
25
70
85
105
125
4.8
4.5
4.3
4.0
3.8
3.5
3.3
3.0
0
5
10
15
20
25
30
35
40
45
50
Pull-up resistor current [µA]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 474
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
33.3
VREF Characteristics
Figure 33-27. Internal 0.55V Reference vs. Temperature
Vdd [V]
1.0
3
5
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 33-28. Internal 1.1V Reference vs. Temperature
Vdd [V]
1.0
3
5
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 475
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-29. Internal 2.5V Reference vs. Temperature
Vdd [V]
1.0
3
5
0.8
0.6
Vref error [%]
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 33-30. Internal 4.3V Reference vs. Temperature
Vdd [V]
1.0
5
0.8
0.6
Vref error [%]
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 476
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
33.4
BOD Characteristics
BOD Current vs. VDD
Figure 33-31. BOD Current vs. VDD (Continuous Mode Enabled)
Temperature [°C]
50
-40
0
25
70
85
105
125
45
40
35
30
25
20
15
10
5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
Figure 33-32. BOD Current vs. VDD (Sampled BOD at 125 Hz)
Temperature [°C]
5.0
-40
0
25
70
85
105
125
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 477
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-33. BOD Current vs. VDD (Sampled BOD at 1 kHz)
Temperature [°C]
5.0
-40
0
25
70
85
105
125
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
BOD Threshold vs. Temperature
Figure 33-34. BOD Threshold vs. Temperature (Level 2.6V)
Falling VDD
Rising VDD
2.74
2.72
2.70
BOD level [V]
2.68
2.66
2.64
2.62
2.60
2.58
2.56
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 478
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-35. BOD Threshold vs. Temperature (Level 4.3V)
Falling VDD
Rising VDD
4.34
4.32
4.30
BOD level [V]
4.28
4.26
4.24
4.22
4.20
4.18
4.16
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
33.5
ADC Characteristics
Figure 33-36. Absolute Accuracy vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
Vref [V]
10.0
1.1
1.5
2.5
4.34
VDD
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 479
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-37. Absolute Accuracy vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
Temperature [°C]
10.0
-40
25
85
105
9.0
Absolute Accuracy [LSB]
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1.1
1.5
2.5
4.3
VDD
Vref [V]
Figure 33-38. DNL Error vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
Vref [V]
2.0
1.1
1.5
2.5
4.34
VDD
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 480
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-39. DNL vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
Temperature [°C]
2.0
-40
25
85
105
1.8
1.6
DNL [LSB]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.1
1.5
2.5
4.3
VDD
Vref [V]
Figure 33-40. Gain Error vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
Vref [V]
8.0
1.1
1.5
2.5
4.34
VDD
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-1.0
-2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 481
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-41. Gain Error vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
Temperature [°C]
8.0
-40
25
85
105
7.0
6.0
Gain [LSB]
5.0
4.0
3.0
2.0
1.0
0.0
1.1
1.5
2.5
4.3
VDD
Vref [V]
Figure 33-42. INL vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
Vref [V]
2.0
1.1
1.5
2.5
4.34
VDD
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 482
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-43. INL vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
Temperature [°C]
2.0
-40
25
85
105
1.8
1.6
INL [LSB]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.1
1.5
2.5
4.3
VDD
Vref [V]
Figure 33-44. Offset Error vs. VDD (fADC=115 ksps) at T=25°C, REFSEL = Internal Reference
Vref [V]
2.0
1.1
1.5
2.5
4.34
VDD
1.6
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 483
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-45. Offset Error vs. Vref (VDD=5.0V, fADC=115 ksps), REFSEL = Internal Reference
Temperature [°C]
2.0
-40
25
85
105
1.6
1.2
Offset [LSB]
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
1.1
1.5
2.5
4.3
VDD
Vref [V]
AC Characteristics
Figure 33-46. Hysteresis vs. VCM - 10 mV (VDD=5V)
Temperature [°C]
20
-40
-20
0
25
55
85
105
125
18
16
14
Hysteresis [mV]
33.6
12
10
8
6
4
2
0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcommon mode [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 484
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-47. Hysteresis vs. VCM - 10 mV to 50 mV (VDD=5V, T=25°C)
HYSMODE
80
10mV
25mV
50mV
72
64
Hysteresis [mV]
56
48
40
32
24
16
8
0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcommon mode [V]
Figure 33-48. Offset vs. VCM - 10 mV (VDD=5V)
Temperature [°C]
10.0
-40
-20
0
25
55
85
105
125
9.0
8.0
Offset [mV]
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcommon mode [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 485
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-49. Offset vs. VCM - 10 mV to 50 mV (VDD=5V, T=25°C)
HYSMODE
10
10mV
25mV
50mV
9
8
Offset [mV]
7
6
5
4
3
2
1
0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vcommon mode [V]
Figure 33-50. Propagation Delay vs. VCM Falling Positive Input, VOD = 25 mV (T=25°C)
Vdd [V]
500
3
5
400
300
200
100
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V common mode [V]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 486
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-51. Propagation Delay vs. VCM Rising Positive Input, VOD = 30 mV (T=25°C)
Vdd [V]
500
3
5
400
300
200
100
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V common mode [V]
OSC20M Characteristics
Figure 33-52. OSC20M Internal Oscillator: Calibration Stepsize vs. Calibration Value (VDD=3V)
Temperature [°C]
2.5
-40
-20
0
25
70
85
105
125
2.3
2.0
Step size from 20MHz [%]
33.7
1.8
1.5
1.3
1.0
0.8
0.5
0.3
0.0
0
8
16
24
32
40
48
56
64
OSCCAL [x1]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 487
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-53. OSC20M Internal Oscillator: Frequency vs. Calibration Value (VDD=3V)
Temperature [°C]
30
-40
-20
0
25
70
85
105
125
28
26
Frequency [MHz]
24
22
20
18
16
14
12
10
0
8
16
24
32
40
48
56
64
OSCCAL [x1]
Figure 33-54. OSC20M Internal Oscillator: Frequency vs. Temperature
Vdd [V]
16.5
2.7
3
3.6
5
5.5
16.4
16.3
16.2
16.1
16.0
15.9
15.8
15.7
15.6
15.5
-40
-20
0
© 2019 Microchip Technology Inc.
20
40
Temperature [°C]
60
80
100
Complete Datasheet
120
DS40002159A-page 488
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-55. OSC20M Internal Oscillator: Frequency vs. VDD
Temperature [°C]
16.5
-40
-20
0
25
70
85
105
125
16.4
16.3
16.2
16.1
16.0
15.9
15.8
15.7
15.6
15.5
33.8
2.5
3.0
3.5
4.0
4.5
Vdd [V]
5.0
5.5
OSCULP32K Characteristics
Figure 33-56. OSCULP32K Internal Oscillator Frequency vs. Temperature
Vdd [V]
40.0
2.7
3
3.6
5
5.5
39.0
38.0
37.0
36.0
35.0
34.0
33.0
32.0
31.0
30.0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 489
ATtiny202/204/402/404/406 Automotiv...
Typical Characteristics
Figure 33-57. OSCULP32K Internal Oscillator Frequency vs. VDD
Temperature [°C]
40.0
-40
-20
0
25
70
85
105
125
39.0
38.0
37.0
36.0
35.0
34.0
33.0
32.0
31.0
30.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Vdd [V]
33.9
TWI SDA Hold timing
Figure 33-58. TWI SDA Holdtime vs temperature (Slave mode) VDD = 3V, CLKCPU = 10 MHz
SDA Hold
1000
300ns
500ns
50ns
OFF
900
800
700
600
500
400
300
200
100
0
-40
-20
0
20
40
60
80
100
120
Temperature [°C]
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 490
ATtiny202/204/402/404/406 Automotiv...
Ordering Information
34.
Ordering Information
•
34.1
Available ordering options can be found by:
– Clicking on one of the following product page links:
• ATtiny202 Product Page
• ATtiny204 Product Page
• ATtiny402 Product Page
• ATtiny404 Product Page
• ATtiny406 Product Page
– Searching by product name at microchipdirect.com
– Contacting your local sales representative
Product Information
Note: For the latest information on available ordering codes, refer to the ATtiny202/204/402/404/406 Automotive
Silicon Errata and Data Sheet Clarification Document found at the product page.
Ordering Code(1)
Flash/SRAM
Pin Count
Max CPU Speed
Supply Voltage
Package Type(2,3)
Temperature Range
ATtiny202-SSBT-VAO
2 KB/128B
8
16 MHz
2.7V to 5.5V
SOIC
-40°C +105°C
ATtiny202-SSZT-VAO
2 KB/128B
8
16 MHz
2.7V to 5.5V
SOIC
-40°C +125°C
ATtiny204-SSBT-VAO
2 KB/128B
14
16 MHz
2.7V to 5.5V
SOIC
-40°C +105°C
ATtiny204-SSZT-VAO
2 KB/128B
14
16 MHz
2.7V to 5.5V
SOIC
-40°C +125°C
ATtiny402-SSBT-VAO
4 KB/256B
8
16 MHz
2.7V to 5.5V
SOIC
-40°C +105°C
ATtiny402-SSZT-VAO
4 KB/256B
8
16 MHz
2.7V to 5.5V
SOIC
-40°C +125°C
ATtiny404-SSBT-VAO
4 KB/256B
14
16 MHz
2.7V to 5.5V
SOIC
-40°C +105°C
ATtiny404-SSZT-VAO
4 KB/256B
14
16 MHz
2.7V to 5.5V
SOIC
-40°C +125°C
ATtiny406-SBT-VAO
4 KB/256B
20
16 MHz
2.7V to 5.5V
SOIC
-40°C +105°C
ATtiny406-SZT-VAO
4 KB/256B
20
16 MHz
2.7V to 5.5V
SOIC
-40°C +125°C
ATtiny406-MBT-VAO
4 KB/256B
20
16 MHz
2.7V to 5.5V
VQFN
-40°C +105°C
ATtiny406-MZT-VAO
4 KB/256B
20
16 MHz
2.7V to 5.5V
VQFN
-40°C +125°C
Note:
1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS
directive). Also Halide free and fully Green.
2. Available in Tape & Reel, Tube or Tray packing media.
3. Package outline drawings can be found in the Package Drawings chapter.
34.2
Product Identification System
To order or obtain information, for example, on pricing or delivery, refer to the factory or the listed sales office.
AT tiny 406 - MBT
Carrier Type
Package up to 24 pins
Flash size in KB
tinyAVR series
Pin count
T=Tape & Reel
Blank=Tube or Tray
Temperature Range
B=-40°C to +105°C
Z=-40°C to +125°C
Package Type
6=20 pins
4=14 pins
2= 8 pins
© 2019 Microchip Technology Inc.
M=VQFN
S=SOIC300
SS=SOIC150
Complete Datasheet
DS40002159A-page 491
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
35.
Package Drawings
35.1
Online Package Drawings
For the most recent package drawings:
1. Go to http://www.microchip.com/packaging.
2. Go to the package type specific page, for example VQFN.
3. Search for either Drawing Number, Style or GPC to find updated drawing.
Table 35-1. Drawing Numbers
Package Type
Drawing Number(1)
Style
Atmel Legacy GPC
Comment
SOIC8
C04-00057
C2X
SWB
-
SOIC14
C04-00065
D3X
SVQ
-
SOIC20
C04-21323
MDB
SRJ
-
VQFN20
C04-00476
2LX
ZCJ
Wettable Flanks
Note:
1. If the drawing number is not found online, the drawing present in the data sheet is the newest one.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 492
ATtiny202/204/402/404/406 Automotiv...
R
Package Drawings
35.2
8-Pin SOIC150
8-Lead Plastic Small Outline - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Atmel Legacy Global Package Code SWB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NOTE 5
NX b
0.25
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SWB Rev E Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 493
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
8-Lead Plastic Small Outline - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Atmel Legacy Global Package Code SWB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SWB Rev E Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 494
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
8-Lead Plastic Small Outline - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Atmel Legacy Global Package Code SWB
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SWB Rev E
Table 35-2. Device and Package Maximum Weight
© 2017 Microchip Technology Inc.
Maximum Weight
© 2019 Microchip Technology Inc.
78 mg
Complete Datasheet
DS40002159A-page 495
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
Table 35-3. Package Reference
JEDEC Drawing Reference
N/A
JESD97 Classification
E3
Table 35-4. Package Code
C2X
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 496
R
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
35.3
14-Pin SOIC150
14-Lead Plastic Small Outline (D3X, UEB, M5B, UEB) - Narrow, 3.90 mm Body [SOIC]
Atmel Legacy Global Package Code SVQ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
NOTE 5
D
N
E
2
E2
2
E1
E
2X
0.10 C D
NOTE 1
1
2
2X N/2 TIPS
0.20 C
3
e
NX b
B
0.25
NOTE 5
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
14X
0.10 C
SIDE VIEW
A1
h
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-D3X Rev D
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 497
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
14-Lead Plastic Small Outline (D3X, UEB, M5B, UEB) - Narrow, 3.90 mm Body [SOIC]
Atmel Legacy Global Package Code SVQ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
§
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Lead Angle
Foot Angle
c
Lead Thickness
Lead Width
b
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0°
0.10
0.31
5°
5°
MILLIMETERS
NOM
14
1.27 BSC
6.00 BSC
3.90 BSC
8.65 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-D3X Rev D Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 498
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
14-Lead Plastic Small Outline (D3X, UEB, M5B, UEB) - Narrow, 3.90 mm Body [SOIC]
Atmel Legacy Global Package Code SVQ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X14)
X
Contact Pad Length (X14)
Y
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-D3X Rev D
Table
35-5. Device
and Package
© 2017
Microchip Technology
Inc. Maximum Weight
Maximum Weight
© 2019 Microchip Technology Inc.
143.2 mg
Complete Datasheet
DS40002159A-page 499
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
Table 35-6. Package Reference
JEDEC Drawing Reference
N/A
JESD97 Classification
E3
Table 35-7. Package Code
D3X
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 500
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
35.4
20-Pin SOIC300
20-Lead Small Outline Integrated Circuit (MDB) - 7.50 mm (.300 In.) Body [SOIC]
Atmel Legacy Global Package Code SRJ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C
D
NOTE 5
A
D
DETAIL A
E
2
E1
2
E1
E
h
2X
0.10 C D
NOTE 1
2X 10 TIPS
0.30 C
e
h
NOTE 5
B
END VIEW
TOP VIEW
0.10 C
C SEATING
PLANE
A
20X
A1
0.10 C
SIDE VIEW
Microchip Technology Drawing C04-21323-MDB Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 501
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
20-Lead Small Outline Integrated Circuit (MDB) - 7.50 mm (.300 In.) Body [SOIC]
Atmel Legacy Global Package Code SRJ
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
ϴ1
ϴ2
R1
H
R
c
ϴ1
ϴ
L
(L1)
DETAIL A
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Lead Angle
ϴ2
Foot Angle
ϴ
c
Lead Thickness
Lead Width
b
Mold Draft Angle
ϴ1
MIN
2.35
0.10
0.25
0.40
0°
0°
0.20
0.31
5°
MILLIMETERS
NOM
20
1.27 BSC
2.50
10.30 BSC
7.50 BSC
12.80 BSC
1.40 REF
-
MAX
2.65
0.30
0.75
1.27
8°
0.33
0.51
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing C04-21323-MDB Rev A Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 502
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
20-Lead Small Outline Integrated Circuit (MDB) - 7.50 mm (.300 In.) Body [SOIC]
Atmel Legacy Global Package Code SRJ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
20
SILK SCREEN
C
Y
1
2
E
X
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (Xnn)
X
Contact Pad Length (Xnn)
Y
MIN
MILLIMETERS
NOM
1.27
9.30
MAX
0.60
2.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23323-MDB Rev A
Table 35-8. Device and Package Maximum Weight
© 2018 Microchip Technology Inc.
Maximum Weight
© 2019 Microchip Technology Inc.
542 mg
Complete Datasheet
DS40002159A-page 503
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
Table 35-9. Package Reference
JEDEC Drawing Reference
N/A
JESD97 Classification
E3
Table 35-10. Package Code
MDB
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 504
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
35.5
20-Pin VQFN
20-Lead Very Thin Plastic Quad Flat, No Lead Package (2LX) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
20X
0.08 C
D
NOTE 1
A
0.10 C
B
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.05 C
2X
A1
TOP VIEW
0.05 C
(A3)
0.10
C A B
A
SEATING
C
PLANE
D2
SIDE VIEW
0.10
DETAIL A
A
C A B
A
E2
A4
2
1
STEPPED
WETTABLE
FLANK
K
D3
NOTE 1
N
L
e
BOTTOM VIEW
20X b
0.10
0.05
SECTION A-A
C A B
C
Microchip Technology Drawing C04-476-2LX Rev C Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 505
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
20-Lead Very Thin Plastic Quad Flat, No Lead Package (2LX) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DETAIL 1
ALTERNATE TERMINAL
CONFIGURATIONS
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
Terminal Length
L
Terminal-to-Exposed-Pad
K
D3
Wettable Flank Step Length
Wettable Flank Step Height
A4
MIN
0.80
0.00
1.60
1.60
0.15
0.35
0.20
0.10
MILLIMETERS
NOM
MAX
20
0.40 BSC
0.90
1.00
0.02
0.05
0.203 REF
3.00 BSC
1.70
1.80
3.00 BSC
1.70
1.80
0.20
0.25
0.40
0.45
0.085
0.19
Dimensions D3 and A4 above apply to all new products released after
November 1, and all products shipped after January 1, 2019, and supersede
dimensions D3 and A4 below.
No physical changes are being made to any package; this update is to align
cosmetic and tolerance variations from existing suppliers.
Notes:
Wettable Flank Step Length
Wettable Flank Step Height
D3
A4
0.035
0.10
0.06
-
0.085
0.19
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-476-2LX Rev C Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 506
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
20-Lead Very Thin Plastic Quad Flat, No Lead Package (2LX) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad and Stepped Wettable Flanks
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
20
ØV
1
G2
2
C2
Y2
EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X20)
X1
Contact Pad Length (X20)
Y1
Contact Pad to Center Pad (X20)
G1
Contact Pad to Contact Pad (X16)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.40 BSC
MAX
1.80
1.80
3.00
3.00
0.20
0.80
0.20
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2476-2LX Rev C
Table 35-11. Device and Package Maximum Weight
© 2018 Microchip Technology Inc.
Maximum Weight
© 2019 Microchip Technology Inc.
14 mg
Complete Datasheet
DS40002159A-page 507
ATtiny202/204/402/404/406 Automotiv...
Package Drawings
Table 35-12. Package Reference
JEDEC Drawing Reference
N/A
JESD97 Classification
E3
Table 35-13. Package Code
2LX
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 508
ATtiny202/204/402/404/406 Automotiv...
Thermal Considerations
36.
Thermal Considerations
36.1
Thermal Resistance Data
The following table summarizes the thermal resistance data depending on the package.
Table 36-1. Thermal Resistance Data
Package Type
θJA [°C/W]
θJC [°C/W]
8-pin SOIC150 (SWB)
91.8
21.5
14-pin SOIC150 (SVQ)
58
26
20-pin SOIC300 (SRJ)
44
21
20-pin VQFN (ZCL)
79.7
36
Related Links
36.2 Junction Temperature
36.2
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device has to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
Related Links
36.1 Thermal Resistance Data
© 2019 Microchip Technology Inc.
Complete Datasheet
DS40002159A-page 509
ATtiny202/204/402/404/406 Automotiv...
Instruction Set Summary
37.
Instruction Set Summary
Table 37-1. Arithmetic and Logic Instructions
Mnemonic
Operands
Description
Op
Flags
#Clocks
ADD
Rd, Rr
Add without Carry
Rd
←
Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd
←
Rd + Rr + C
Z,C,N,V,S,H
1
ADIW
Rd, K
Add Immediate to Word
Rd + 1:Rd
←
Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd
←
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
←
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
←
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
←
Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd
←
Rd + 1:Rd - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND
Rd
←
Rd • Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
←
Rd • K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
←
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
←
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
←
Rd ⊕ Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
←
$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
←
$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
←
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
←
Rd • ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
←
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
←
Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
←
Rd • Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
←
Rd ⊕ Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
←
$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0
←
Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0
←
Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0
←
Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0
←
Rd x Rr
工商网监
湘ICP备2023018690号
