ATtiny24/44/84
8-bit AVR Microcontroller with 2/4/8K Bytes In-System
Programmable Flash
DATASHEET
Features
● High performance, low power AVR® 8-bit microcontroller
● Advanced RISC architecture
● 120 powerful instructions – most single clock cycle execution
● 32 x 8 general purpose working registers
● Fully static operation
● Non-volatile program and data memories
● 2/4/8K byte of in-system programmable program memory flash (Atmel®
ATtiny24/44/84)
● Endurance: 10,000 write/erase cycles
● 128/256/512 bytes in-system programmable EEPROM (Atmel ATtiny24/44/84)
● Endurance: 100,000 write/erase cycles
● 128/256/512 bytes internal SRAM (Atmel ATtiny24/44/84)
● Programming lock for self-programming flash program and EEPROM data
security
● Peripheral features
● Two Timer/Counters, 8- and 16-bit counters with two PWM channels on both
● 10-bit ADC
● Eight single-ended channels
● 12 differential ADC channel pairs with programmable gain (1x, 20x)
● Temperature measurement
● Programmable watchdog timer with separate on-chip oscillator
● On-chip analog comparator
● Universal serial interface
● Special microcontroller features
●
●
●
●
●
●
●
●
●
debugWIRE on-chip debug system
In-system programmable via SPI port
External and internal interrupt sources
Pin change interrupt on 12 pins
Low power idle, ADC noise reduction, standby and power-down modes
Enhanced power-on reset circuit
Programmable brown-out detection circuit
Internal calibrated oscillator
On-chip temperature sensor
● I/O and packages
● 14-pin SOIC, 20-pin QFN/MLF: Twelve programmable I/O lines
7701G-AVR-02/15
● Operating voltage:
● 2.7 - 5.5V for Atmel ATtiny24/44/84
● Speed grade
● Atmel ATtiny24/44/84: 0 - 8MHz at 2.7 - 5.5V, 0 - 16MHz at 4.5 - 5.5V
● Automotive temperature range
● Low power consumption
● Active mode:
● 1MHz, 2.7V: 800µA
● Power-down mode:
● 2.7V: 2.0µA
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ATtiny24/44/84 [DATASHEET]
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1.
Pin Configurations
Figure 1-1. Pinout Atmel ATtiny24/44/84
SOIC
VCC
1
14
GND
(PCINT8/XTAL1) PB0
2
13
PA0 (ADC0/AREF/PCINT0)
(PCINT9/XTAL2) PB1
3
12
PA1 (ADC1/AIN0/PCINT1)
(PCINT11/RESET/dW) PB3
4
11
PA2 (ADC2/AIN1/PCINT2)
(PCINT10/INT0/OC0A/CKOUT) PB2
5
10
PA3 (ADC3/T0/PCINT3)
(PCINT7/ICP/OC0B/ADC7) PA7
6
9
PA4 (ADC4/USCK/SCL/T1/PCINT4)
(PCINT6/OC1A/SDA/MOSI/ADC6/) PA6
7
8
PA5 (ADC5/DO/MISO/OC1B/PCINT5)
DNC
DNC
DNC
PA6
20
19
18
17
16
Pin16: PA6 (PCINT6/OC1A/SDA/MOSI/ADC6)
Pin20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)
2
14
PB2 (PCINT10/INT0/OC0A/CKOUT)
(ADCV2/AIN1/PCINT2) PA2
3
13
PB3 (PCINT11/RESET/dW)
(ADC1/AIN0/PCINT1) PA1
4
12
PB1 (PCINT9/XTAL2)
(ADC0/AREF/PCINT0) PA0
5
11
PB0 (PCINT8/XTAL1)
Bottom pad should be
soldered to ground
DNC: Do Not Connect
6
7
8
9
10
DNC
(ADC3//AT0/PCINT3) PA3
VCC
PA7 (PCINT7/ICP/OC0B/ADC7)
GND
15
DNC
1
DNC
(ADC4/USCK/SCL/PCINT4) PA4
Note
1.1
PA5
QFN/MLF
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of actual Atmel® ATtiny24/44/84
AVR® microcontrollers manufactured on the typical process technology. Applicable automotive min. and max. values will be
available after devices representative of the whole process excursion (corner run) have been characterized.
ATtiny24/44/84 [DATASHEET]
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3
2.
Overview
The Atmel® ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the Atmel ATtiny24/44/84 achieves throughputs approaching 1MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.
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Block Diagram
Figure 2-1. Block Diagram
VCC
8-bit Databus
GND
Internal
Oscillator
Internal
Calibrated
Oscillator
Timing and
Control
Program
Counter
Stack
Pointer
Watchdog
Timer
Program
Flash
SRAM
MCU Control
Register
Instruction
Register
MCU Status
Register
General
Purpose
Registers
Timer/
Counter 0
X
Y
Z
Instruction
Decoder
Timer/
Counter 1
Control
Lines
ALU
Status
Register
Interrupt
Unit
Programming
Logic
+ -
Analog
Comparator
2.1
ISP
Interface
Data Register
Port A
Data Dir. Register
Port A
EEPROM
ADC
Oscillators
Data Register
Port B
Data Dir. Register
Port B
Port A Drivers
Port B Drivers
PA7-PA0
PB3-PB0
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5
The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The Atmel ATtiny24/44/84 provides the following features: 2/4/8K bytes of in-system programmable flash, 128/256/512 bytes
EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit
Timer/Counter with two PWM channels, a 16-bit Timer/Counter with two PWM channels, internal and external interrupts, an
8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable watchdog
timer with internal oscillator, internal calibrated oscillator, and three software selectable power saving modes. The idle mode
stops the CPU while allowing the SRAM, Timer/Counter, ADC, analog comparator, and interrupt system to continue
functioning. The power-down mode saves the register contents, disabling all chip functions until the next interrupt or
hardware reset. The ADC noise reduction mode stops the CPU and all I/O modules except ADC to minimize switching noise
during ADC conversions. In standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping.
This allows very fast start-up combined with low power consumption.
The device is manufactured using Atmel's high-density non-volatile memory technology. The on-chip ISP flash allows the
program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory
programmer or by an on-chip boot code running on the AVR core.
The Atmel ATtiny24/44/84 AVR is supported with a full suite of program and system development tools including: C
compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
2.2
Automotive Quality Grade
The Atmel ATtiny24/44/84 has been developed and manufactured according to the most stringent requirements of the
international standard ISO-TS-16949 grade 1. This data sheet contains limit values extracted from the results of extensive
characterization (temperature and voltage). The quality and reliability of the Atmel ATtiny24/44/84 have been verified during
regular product qualification as per AEC-Q100.
As indicated in the ordering information paragraph, the product is available in only one temperature grade.
Table 2-1.
Temperature Grade Identification for Automotive Products
Temperature
Temperature Identifier
Comments
–40; +125
Z
Full automotive temperature range
2.3
Pin Descriptions
2.3.1
VCC
Supply voltage.
2.3.2
GND
Ground.
2.3.3
Port B (PB3...PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have
symmetrical drive characteristics with both high sink and source capability except PB3, which has the RESET capability. To
use pin PB3 as an I/O pin instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the Atmel ATtiny24/44/84 as listed on Section 12.3
“Alternate Port Functions” on page 54.
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2.3.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running. The minimum pulse length is given in Table 9-1 on page 37. Shorter pulses are not guaranteed to generate a reset.
2.3.5
Port A (PA7...PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The port A output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled
low will source current if the pull-up resistors are activated. The port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Port A has an alternate function as analog input for the ADC, analog comparator, Timer/Counter, SPI and pin change
interrupt as described in Section 12.3 “Alternate Port Functions” on page 54.
ATtiny24/44/84 [DATASHEET]
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7
3.
Resources
A comprehensive set of development tools, driver and application notes, and datasheets are available for download on
http://www.atmel.com/avr.
4.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code
examples assume that the part-specific header file is included before compilation. Be aware that not all C compiler vendors
include bit definitions in the header files, and interrupt handling in C is compiler dependent. Please confirm with the C
compiler documentation for more details.
For I/O registers located in the extended I/O map, IN, OUT, SBIS, SBIC, CBI, and SBI instructions must be replaced with
instructions that allow access to extended I/O, typically LDS and STS combined with SBRS, SBRC, SBR, and CBR.
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ATtiny24/44/84 [DATASHEET]
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5.
CPU Core
5.1
Overview
This section discusses the Atmel® AVR® core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must, therefore, be able to access memories, perform calculations, control peripherals, and
handle interrupts.
Architectural Overview
Figure 5-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status and
Control
32 x 8
General
Purpose
Registers
Instruction
Decoder
Control Lines
Indirect Addressing
Instruction
Register
Direct Addressing
5.2
ALU
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
Data
SRAM
Timer/Counter 1
EEPROM
Universal
Serial Interface
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture, with separate memories and buses
for program and data. Instructions in the program memory are executed with a single-level pipelining. While one instruction
is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be
executed in every clock cycle. The program memory is in-system reprogrammable flash memory.
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9
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This
allows single-cycle arithmetic logic unit (ALU) operation. In a typical ALU operation, two operands are output from the
register file, the operation is executed, and the result is stored back in the register file, all in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling
efficient address calculations. One of the address pointers can also be used as an address pointer for look up tables in flash
program memory. These added function registers are the 16-bit X-, Y-, and Z-registers, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single-register
operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect
information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions able to directly address the whole
address space. Most AVR® instructions have a single 16-bit word format. Every program memory address contains a 16- or
32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and
the usage of the SRAM. All user programs must initialize the stack pointer (SP) in the reset routine (before subroutines or
interrupts are executed). The SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through
the five different addressing modes supported in the AVR architecture.
The memory spaces in the Atmel® AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All interrupts have a separate interrupt vector in the interrupt vector table. The interrupts have priority in accordance
with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions such as control registers, SPI, and other I/O
functions. The I/O memory can be accessed directly or as the data space locations following those of the register file,
0x20 - 0x5F.
5.3
ALU – Arithmetic Logic Unit
The high-performance Atmel AVR ALU operates in direct connection with all 32 general purpose working registers. Within a
single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are
executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit functions. Some
implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and
fractional format. See the “Instruction Set” section for a detailed description.
5.4
Status Register
The status register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the status register is
updated after all ALU operations, as specified in the instruction set summary. This will in many cases remove the need for
using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored when returning from an
interrupt. This must be handled by software.
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5.4.1
SREG – AVR Status Register
Bit
7
6
5
4
3
2
1
0
0x3F (0x5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then
performed in separate control registers. If the global interrupt enable register is cleared, none of the interrupts are enabled
independently of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and
is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with
the SEI and CLI instructions, as described in the instruction set summary.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit
from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The half carry flag H indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic. See the
instruction set reference for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive OR between the negative flag N and the two's complement overflow flag V. See the
“Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two's complement overflow flag V supports two's complement arithmetic. See the instruction set summary for detailed
information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result in an arithmetic or logic operation. See the instruction set summary for
detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result in an arithmetic or logic operation. See the instruction set summary for detailed
information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetic or logic operation. See the instruction set summary for detailed
information.
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11
5.5
General Purpose Register File
The register file is optimized for the Atmel® AVR® Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
●
●
●
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Figure 5-2 on page 12 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5-2. AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in Figure 5-2, each register is also assigned a data memory address, mapping them directly into the first 32
locations of the user data space. Although not physically implemented as SRAM locations, this memory organization
provides great flexibility in access of the registers, as the X-, Y- and Z-registers can be set to index any register in the file.
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5.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in Figure 5-3 on page 13.
Figure 5-3. The X-, Y-, and Z-registers
15
XH
XL
0
7
0
7
0
X-register
R27 (0x1B)
R26 (0x1A)
15
YH
YL
0
7
0
7
0
Y-register
R29 (0x1D)
R28 (0x1C)
15
ZH
ZL
0
7
0
7
0
Z-register
R31 (0x1F)
R30 (0x1E)
In the different addressing modes, these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set summary for details).
5.6
Stack Pointer
The stack is mainly used for storing temporary data, for storing local variables, and for storing return addresses after
interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is
implemented as growing from higher memory locations to lower memory locations. This implies that a stack PUSH
instruction decreases the stack pointer.
The stack pointer points to the data SRAM stack area where the subroutine and interrupt stacks are located. This stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The stack pointer must be set to point above 0x60. The stack pointer is decremented by one when data are pushed onto the
stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the stack with a
subroutine call or interrupt. The stack pointer is incremented by one when data are popped from the stack with the POP
instruction, and it is incremented by two when data are popped from the stack with a return from subroutine RET instruction
or return from interrupt RETI instruction.
The Atmel AVR® stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only
the SPL register is needed. In this case, the SPH register will not be present.
5.6.1
SPH and SPL – Stack Pointer High and Low
Bit
15
14
13
12
11
10
9
8
0x3E (0x5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D (0x5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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13
5.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel® AVR® CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 5-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast
access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 5-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 5-5 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 5-5. Single-cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
5.8
Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a
separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be
written with a logical one together with the global interrupt enable bit in the status register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. The complete
list of vectors is shown in Section 10. “Interrupts” on page 44. The list also determines the priority levels of the different
interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0, the external
interrupt request 0.
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can
write a logical one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt
routine. The I-bit is automatically set when a return from interrupt instruction, RETI, is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these
interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine,
and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt
flag will be set and remembered until the interrupt is enabled or the flag is cleared by software. Similarly, if one or more
interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and
remembered until the global interrupt enable bit is set, and will then be executed by order of priority.
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The second type of interrupt will trigger as long as the interrupt condition is present. These interrupts do not necessarily have
interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the Atmel® AVR® exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from
an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed
after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can
be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in
cli
sbi
sbi
out
r16, SREG
; store SREG value
; disable interrupts during timed sequence
EECR, EEMPE ; start EEPROM write
EECR, EEPE
SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1