ATTINY24A-CCUR

ATtiny24A/44A/84A tinyAVR® Data Sheet Introduction ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation • High Endurance, Non-volatile Memory Segments – 2K/4K/8K Bytes of In-System, Self-programmable Flash Program Memory • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes of Internal SRAM – Data Retention: 20 years at 85°C / 100 years at 25°C – Programming Lock for Self-programming Flash & EEPROM Data Security • Peripheral Features – One 8-bit and One 16-bit Timer/Counter with Two PWM Channels, Each – 10-bit ADC • 8 Single-ended Channels • 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Universal Serial Interface • Special Microcontroller Features – debugWIRE On-chip Debug System  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 1 ATtiny24A/44A/84A – In-System Programmable via SPI Port – Internal and External Interrupt Sources • Pin Change Interrupt on 12 Pins – Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit with Software Disable Function – Internal Calibrated Oscillator – On-chip Temperature Sensor • I/O and Packages – Available in 20-pin WQFN/VQFN, 14-pin SOIC, 14-pin PDIP and 15-ball UFBGA – Twelve Programmable I/O Lines • Operating Voltage: – 1.8 – 5.5V • Speed Grade: – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 10 MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Industrial Temperature Range: -40°C to +85°C • Low Power Consumption – Active Mode: • 210 µA at 1.8V and 1 MHz – Idle Mode: • 33 µA at 1.8V and 1 MHz – Power-down Mode: • 0.1 µA at 1.8V and 25°C  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 2 ATtiny24A/44A/84A Table of Contents 1 Pin Configurations ................................................................................... 8 1.1 Pin Descriptions................................................................................................. 9 2 Overview ................................................................................................. 10 3 General Information ............................................................................... 12 4 5 6 7 3.1 Resources ....................................................................................................... 12 3.2 Code Examples ............................................................................................... 12 3.3 Capacitive Touch Sensing ............................................................................... 12 3.4 Data Retention................................................................................................. 12 3.5 Disclaimer........................................................................................................ 12 CPU Core ................................................................................................ 13 4.1 Architectural Overview..................................................................................... 13 4.2 ALU – Arithmetic Logic Unit............................................................................. 14 4.3 Status Register ................................................................................................ 14 4.4 General Purpose Register File ........................................................................ 14 4.5 Stack Pointer ................................................................................................... 16 4.6 Instruction Execution Timing ........................................................................... 16 4.7 Reset and Interrupt Handling........................................................................... 17 4.8 Register Description ........................................................................................ 19 Memories ................................................................................................ 21 5.1 In-System Re-programmable Flash Program Memory .................................... 21 5.2 SRAM Data Memory........................................................................................ 21 5.3 EEPROM Data Memory .................................................................................. 22 5.4 I/O Memory...................................................................................................... 26 5.5 Register Description ........................................................................................ 26 Clock System .......................................................................................... 29 6.1 Clock Subsystems ........................................................................................... 29 6.2 Clock Sources ................................................................................................. 30 6.3 System Clock Prescaler .................................................................................. 34 6.4 Clock Output Buffer ......................................................................................... 35 6.5 Register Description ........................................................................................ 36 Power Management and Sleep Modes ................................................. 38 7.1 Sleep Modes.................................................................................................... 38 7.2 Software BOD Disable..................................................................................... 39  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 3 ATtiny24A/44A/84A 8 9 7.3 Power Reduction Register ............................................................................... 39 7.4 Minimizing Power Consumption ...................................................................... 40 7.5 Register Description ........................................................................................ 41 System Control and Reset .................................................................... 43 8.1 Resetting the AVR ........................................................................................... 43 8.2 Reset Sources ................................................................................................. 44 8.3 Internal Voltage Reference.............................................................................. 46 8.4 Watchdog Timer .............................................................................................. 46 8.5 Register Description ........................................................................................ 49 Interrupts ................................................................................................ 52 9.1 Interrupt Vectors .............................................................................................. 52 9.2 External Interrupts ........................................................................................... 53 9.3 Register Description ........................................................................................ 55 10 I/O Ports .................................................................................................. 58 10.1 Ports as General Digital I/O ............................................................................. 58 10.2 Alternate Port Functions .................................................................................. 62 10.3 Register Description ........................................................................................ 71 11 8-bit Timer/Counter0 with PWM ............................................................ 73 11.1 Features .......................................................................................................... 73 11.2 Overview.......................................................................................................... 73 11.3 Clock Sources ................................................................................................. 74 11.4 Counter Unit .................................................................................................... 74 11.5 Output Compare Unit....................................................................................... 75 11.6 Compare Match Output Unit ............................................................................ 77 11.7 Modes of Operation ......................................................................................... 78 11.8 Timer/Counter Timing Diagrams ..................................................................... 82 11.9 Register Description ........................................................................................ 83 12 16-bit Timer/Counter1 ............................................................................ 89 12.1 Features .......................................................................................................... 89 12.2 Overview.......................................................................................................... 89 12.3 Timer/Counter Clock Sources ......................................................................... 91 12.4 Counter Unit .................................................................................................... 91 12.5 Input Capture Unit ........................................................................................... 92 12.6 Output Compare Units..................................................................................... 94 12.7 Compare Match Output Unit ............................................................................ 96  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 4 ATtiny24A/44A/84A 12.8 Modes of Operation ......................................................................................... 97 12.9 Timer/Counter Timing Diagrams ................................................................... 104 12.10 Accessing 16-bit Registers ............................................................................ 105 12.11 Register Description ...................................................................................... 108 13 Timer/Counter Prescaler ..................................................................... 116 13.1 Prescaler Reset ............................................................................................. 116 13.2 External Clock Source ................................................................................... 116 13.3 Register Description ...................................................................................... 117 14 USI – Universal Serial Interface .......................................................... 119 14.1 Features ........................................................................................................ 119 14.2 Overview........................................................................................................ 119 14.3 Functional Descriptions ................................................................................. 120 14.4 Alternative USI Usage ................................................................................... 126 14.5 Register Descriptions .................................................................................... 126 15 Analog Comparator .............................................................................. 131 15.1 Analog Comparator Multiplexed Input ........................................................... 131 15.2 Register Description ...................................................................................... 132 16 Analog to Digital Converter ................................................................. 135 16.1 Features ........................................................................................................ 135 16.2 Overview........................................................................................................ 135 16.3 Operation....................................................................................................... 136 16.4 Starting a Conversion .................................................................................... 137 16.5 Prescaling and Conversion Timing ................................................................ 138 16.6 Changing Channel or Reference Selection ................................................... 141 16.7 ADC Noise Canceler ..................................................................................... 142 16.8 Analog Input Circuitry .................................................................................... 142 16.9 Noise Canceling Techniques......................................................................... 143 16.10 ADC Accuracy Definitions ............................................................................. 143 16.11 ADC Conversion Result................................................................................. 145 16.12 Temperature Measurement ........................................................................... 146 16.13 Register Description ...................................................................................... 146 17 debugWIRE On-chip Debug System .................................................. 153 17.1 Features ........................................................................................................ 153 17.2 Overview........................................................................................................ 153 17.3 Physical Interface .......................................................................................... 153  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 5 ATtiny24A/44A/84A 17.4 Software Break Points ................................................................................... 154 17.5 Limitations of debugWIRE ............................................................................. 154 17.6 Register Description ...................................................................................... 154 18 Self-Programming the Flash ............................................................... 155 18.1 Performing Page Erase by SPM.................................................................... 155 18.2 Filling the Temporary Buffer (Page Loading)................................................. 155 18.3 Performing a Page Write ............................................................................... 156 18.4 Addressing the Flash During Self-Programming ........................................... 156 18.5 EEPROM Write Prevents Writing to SPMCSR .............................................. 156 18.6 Reading Lock, Fuse and Signature Data from Software ............................... 157 18.7 Preventing Flash Corruption .......................................................................... 158 18.8 Programming Time for Flash when Using SPM ............................................ 159 18.9 Register Description ...................................................................................... 159 19 Memory Programming ......................................................................... 161 19.1 Program And Data Memory Lock Bits ........................................................... 161 19.2 Fuse Bytes..................................................................................................... 162 19.3 Device Signature Imprint Table ..................................................................... 163 19.4 Page Size ...................................................................................................... 164 19.5 Serial Programming ....................................................................................... 165 19.6 High-voltage Serial Programming.................................................................. 168 19.7 High-Voltage Serial Programming Algorithm ................................................. 169 20 Electrical Characteristics .................................................................... 176 20.1 Absolute Maximum Ratings* ......................................................................... 176 20.2 DC Characteristics......................................................................................... 176 20.3 Speed ............................................................................................................ 177 20.4 Clock Characteristics..................................................................................... 178 20.5 System and Reset Characteristics ................................................................ 179 20.6 ADC Characteristics ...................................................................................... 180 20.7 Analog Comparator Characteristics............................................................... 182 20.8 Serial Programming Characteristics .............................................................. 183 20.9 High-Voltage Serial Programming Characteristics ........................................ 184 21 Typical Characteristics ........................................................................ 185 21.1 Supply Current of I/O Modules ...................................................................... 185 21.2 ATtiny24A ...................................................................................................... 186 21.3 ATtiny44A ...................................................................................................... 214  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 6 ATtiny24A/44A/84A 21.4 ATtiny84A ...................................................................................................... 242 22 Register Summary ............................................................................... 269 23 Instruction Set Summary ..................................................................... 271 24 Ordering Information ........................................................................... 273 24.1 ATtiny24A ...................................................................................................... 273 24.2 ATtiny44A ...................................................................................................... 274 24.3 ATtiny84A ...................................................................................................... 275 25 Packaging Information ........................................................................ 276 25.1 14S1 .............................................................................................................. 276 25.2 14P3 .............................................................................................................. 279 25.3 15CC1 ........................................................................................................... 280 25.4 20M1.............................................................................................................. 283 25.5 20M2.............................................................................................................. 286 26 Errata ..................................................................................................... 289 27 Datasheet Revision History ................................................................. 290 27.1 Rev. A – 10/20............................................................................................... 290 27.2 Rev. 8183F – 06/12 ....................................................................................... 290 27.3 Rev. 8183E – 01/12....................................................................................... 290 27.4 Rev. 8183D – 04/11....................................................................................... 290 27.5 Rev. 8183C – 03/11....................................................................................... 290 27.6 Rev. 8183B – 03/10....................................................................................... 291 27.7 Rev. 8183A – 12/08....................................................................................... 291  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 7 ATtiny24A/44A/84A 1. Pin Configurations Figure 1-1. Pinout of ATtiny24A/44A/84A PDIP/SOIC VCC (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5) PA7 (PCINT7/ICP/OC0B/ADC7) PB2 (PCINT10/INT0/OC0A/CKOUT) PB3 (PCINT11/RESET/dW) PB1 (PCINT9/XTAL2) PB0 (PCINT8/XTAL1/CLKI) DNC DNC GND VCC DNC NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect Table 1-1. 15 14 13 12 11 6 7 8 9 10 1 2 3 4 5 (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0 20 19 18 17 16 PA5 DNC DNC DNC PA6 WQFN/VQFN UFBGA - Pinout ATtiny24A/44A/84A (top view) 1 A 2 3 4 PA5 PA6 PB2 B PA4 PA7 PB1 PB3 C PA3 PA2 PA1 PB0 D PA0 GND GND VCC  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 8 ATtiny24A/44A/84A 1.1 1.1.1 Pin Descriptions VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed in Section 10.2 “Alternate Port Functions” on page 64. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 182. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.5 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 64.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 9 ATtiny24A/44A/84A 2. Overview ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram VCC 8-BIT DATABUS INTERNAL OSCILLATOR INTERNAL CALIBRATED OSCILLATOR TIMING AND CONTROL GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER PROGRAM FLASH SRAM MCU CONTROL REGISTER INSTRUCTION REGISTER MCU STATUS REGISTER GENERAL PURPOSE REGISTERS TIMER/ COUNTER0 X Y Z INSTRUCTION DECODER TIMER/ COUNTER1 CONTROL LINES ALU STATUS REGISTER INTERRUPT UNIT ANALOG COMPARATOR + _ PROGRAMMING LOGIC EEPROM ISP INTERFACE DATA REGISTER PORT A DATA DIR. REG.PORT A ADC OSCILLATORS DATA REGISTER PORT B DATA DIR. REG.PORT B PORT A DRIVERS PORT B DRIVERS PA[7:0] PB[3:0] The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 10 ATtiny24A/44A/84A The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Microchip’s high density non-volatile memory technology. The on-chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The ATtiny24A/44A/84A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 11 ATtiny24A/44A/84A 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.microchip.com. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Capacitive Touch Sensing Microchip QTouch® Library provides a simple to use solution for touch sensitive interfaces on Microchip AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Microchip website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Microchip website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 12 ATtiny24A/44A/84A 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4-1. Block Diagram of the AVR® Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registrers Instruction Decoder Control Lines Indirect Addressing Instruction Register Direct Addressing 4.1 Interrupt Unit Watchdog Timer ADC ALU Analog Comparator Timer/Counter 0 Data SRAM Timer/Counter 1 Universal Serial Interface EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 13 ATtiny24A/44A/84A The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 14 ATtiny24A/44A/84A The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR® CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 below. Figure 4-3. The X-, Y-, and Z-registers 15  2020 Microchip Technology Inc. XH Data Sheet Complete XL 0 DS40002269A-page 15 ATtiny24A/44A/84A X-register 7 0 R27 (0x1B) 15 Y-register 0 R26 (0x1A) YH 7 YL 0 R29 (0x1D) Z-register 7 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 16 ATtiny24A/44A/84A Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 53. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)  2020 Microchip Technology Inc. Data Sheet Complete DS40002269A-page 17 ATtiny24A/44A/84A to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1