Atmel 8-bit AVR Microcontroller with 2/4/8K
Bytes In-System Programmable Flash
ATtiny25/V / ATtiny45/V / ATtiny85/V
Summary
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data Security
Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
Operating Voltage
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
Speed Grade
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 300 µA
Rev. 2586QS–AVR–08/2013
– Power-down Mode:
• 0.1 µA at 1.8V
2586QS–AVR–08/2013
1. Pin Configurations
Figure 1-1.
Pinout ATtiny25/45/85
PDIP/SOIC/TSSOP
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
NOTE: TSSOP only for ATtiny45/V
15
14
13
12
11
6
7
8
9
10
1
2
3
4
5
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
DNC
DNC
GND
DNC
DNC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
20
19
18
17
16
DNC
DNC
DNC
DNC
DNC
QFN/MLF
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
1.1
Pin Descriptions
1.1.1
VCC
Supply voltage.
1.1.2
GND
Ground.
1.1.3
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
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Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions
of Port B” on page 60.
On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility
Mode for supporting the backward compatibility with ATtiny15.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4
on page 165. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
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2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1
MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
GND
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
TIMER/
COUNTER0
X
Y
Z
TIMER/
COUNTER1
ALU
UNIVERSAL
SERIAL
INTERFACE
STATUS
REGISTER
INTERRUPT
UNIT
PROGRAMMING
LOGIC
DATA
EEPROM
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
OSCILLATORS
ADC /
ANALOG COMPARATOR
PORT B DRIVERS
RESET
PB[0:5]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny25/45/85 [DATASHEET]
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The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512
bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one
8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal
and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and
three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the
CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash
allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional
non-volatile memory programmer or by an On-chip boot code running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
ATtiny25/45/85 [DATASHEET]
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3. About
3.1
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined
with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.
3.3
Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
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4. Register Summary
Address
Note:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
SREG
I
T
H
S
V
N
Z
C
page 8
0x3E
SPH
–
–
–
–
–
–
SP9
SP8
page 11
0x3D
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
page 11
0x3C
Reserved
page 51
–
0x3B
GIMSK
–
INT0
PCIE
–
–
–
–
–
0x3A
GIFR
–
INTF0
PCIF
–
–
–
–
–
page 52
0x39
TIMSK
–
OCIE1A
OCIE1B
OCIE0A
OCIE0B
TOIE1
TOIE0
–
pages 81, 102
0x38
TIFR
–
OCF1A
OCF1B
OCF0A
OCF0B
TOV1
TOV0
–
page 81
0x37
SPMCSR
–
–
RSIG
CTPB
RFLB
PGWRT
PGERS
SPMEN
page 145
0x36
Reserved
0x35
MCUCR
BODS
PUD
SE
SM1
–
SM0
BODSE
ISC01
ISC00
pages 37, 51, 64
0x34
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
page 44,
0x33
TCCR0B
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
page 79
0x32
TCNT0
0x31
OSCCAL
0x30
TCCR1
0x2F
TCNT1
Timer/Counter1
pages 91, 102
0x2E
OCR1A
Timer/Counter1 Output Compare Register A
pages 91, 102
Timer/Counter0
CTC1
PWM1A
0x2D
OCR1C
0x2C
GTCCR
0x2B
OCR1B
0x2A
TCCR0A
0x29
OCR0A
0x28
OCR0B
0x27
PLLCSR
LSM
0x26
CLKPR
CLKPCE
–
0x25
DT1A
DT1AH3
DT1AH2
DT1BH3
DT1BH2
-
-
0x24
DT1B
0x23
DTPS1
0x22
DWDR
0x21
WDTCR
0x20
PRR
0x1F
EEARH
0x1E
EEARL
0x1D
EEDR
0x1C
EECR
page 80
Oscillator Calibration Register
COM1A1
COM1A0
CS13
page 31
CS12
CS11
CS10
Timer/Counter1 Output Compare Register C
TSM
PWM1B
COM1B1
COM0A1
COM0A0
COM0B1
COM1B0
FOC1B
pages 91, 102
FOC1A
PSR1
PSR0
WGM01
WGM00
Timer/Counter1 Output Compare Register B
Timer/Counter0 – Output Compare Register A
–
page 81
–
–
PCKE
PLLE
PLOCK
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
page 32
DT1AH1
DT1AH0
DT1AL3
DT1AL2
DT1AL1
DT1AL0
page 107
DT1BH1
DT1BH0
DT1BL3
DT1BL2
DT1BL1
DT1BL0
page 107
-
-
-
-
DTPS11
DTPS10
page 106
WDE
WDP2
WDP1
WDP0
page 45
PRTIM1
PRTIM0
PRUSI
PRADC
page 36
EEAR8
page 20
DWDR[7:0]
WDIF
WDIE
WDP3
WDCE
–
EEAR7
EEAR6
EEAR5
EEAR4
–
EEPM1
EEAR3
EEPM0
pages 94, 103
page 140
EEAR2
EEAR1
EEAR0
page 21
EERIE
EEMPE
EEPE
EERE
page 21
EEPROM Data Register
–
page 77
page 80
Timer/Counter0 – Output Compare Register B
–
pages 77, 90, 101
page 92
–
COM0B0
pages 89, 100
page 21
0x1B
Reserved
–
0x1A
Reserved
–
0x19
Reserved
0x18
PORTB
–
–
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
page 64
0x17
DDRB
–
–
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
page 64
0x16
PINB
–
–
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 64
0x15
PCMSK
–
–
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
page 52
0x14
DIDR0
–
–
ADC0D
ADC2D
ADC3D
ADC1D
AIN1D
AIN0D
pages 121, 138
–
0x13
GPIOR2
General Purpose I/O Register 2
page 10
0x12
GPIOR1
General Purpose I/O Register 1
page 10
0x11
GPIOR0
General Purpose I/O Register 0
page 10
0x10
USIBR
USI Buffer Register
page 115
0x0F
USIDR
0x0E
USISR
USISIF
USIOIF
USIPF
USIDC
USI Data Register
USICNT3
USICNT2
USICNT1
USICNT0
page 115
page 115
0x0D
USICR
USISIE
USIOIE
USIWM1
USIWM0
USICS1
USICS0
USICLK
USITC
page 116
0x0C
Reserved
–
0x0B
Reserved
–
0x0A
Reserved
–
0x09
Reserved
0x08
ACSR
0x07
–
ACD
ACBG
ACO
ACI
ACIE
–
ACIS1
ACIS0
page 120
ADMUX
REFS1
REFS0
ADLAR
REFS2
MUX3
MUX2
MUX1
MUX0
page 134
0x06
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
page 136
0x05
ADCH
ADC Data Register High Byte
0x04
ADCL
ADC Data Register Low Byte
0x03
ADCSRB
0x02
Reserved
–
0x01
Reserved
–
0x00
Reserved
–
BIN
ACME
IPR
–
–
page 137
page 137
ADTS2
ADTS1
ADTS0
pages 120, 137
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
ATtiny25/45/85 [DATASHEET]
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should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
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5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd Rd - Rr - C
Z,C,N,V,H
1
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl Rdh:Rdl - K
Z,C,N,V,S
2
1
AND
Rd, Rr
Logical AND Registers
Rd Rd Rr
Z,N,V
ANDI
Rd, K
Logical AND Register and Constant
Rd Rd K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd Rd Rr
Z,N,V
1
COM
Rd
One’s Complement
Rd 0xFF Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd 0x00 Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd Rd (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd Rd 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd Rd Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd Rd Rd
Z,N,V
1
SER
Rd
Set Register
Rd 0xFF
None
1
Relative Jump
PC PC + k + 1
None
2
Indirect Jump to (Z)
PC Z
None
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
Relative Subroutine Call
PC PC + k + 1
None
3
ICALL
Indirect Call to (Z)
PC Z
None
3
RET
Subroutine Return
PC STACK
None
4
RETI
Interrupt Return
PC STACK
I
if (Rd = Rr) PC PC + 2 or 3
None
RCALL
k
4
CPSE
Rd,Rr
Compare, Skip if Equal
1/2/3
CP
Rd,Rr
Compare
Rd Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd Rr C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC PC + 2 or 3
None
1
1/2/3
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PCPC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PCPC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N V= 0) then PC PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N V= 1) then PC PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) Rd(n), Rd(0) 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) Rd(n+1), Rd(7) 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)C,Rd(n+1) Rd(n),CRd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)C,Rd(n) Rd(n+1),CRd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n) Rd(n+1), n=0..6
Z,C,N,V
1
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Mnemonics
Operands
Description
Operation
Flags
#Clocks
SWAP
Rd
Swap Nibbles
Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0)
None
BSET
s
Flag Set
SREG(s) 1
SREG(s)
1
1
BCLR
s
Flag Clear
SREG(s) 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) T
None
1
1
SEC
Set Carry
C1
C
CLC
Clear Carry
C0
C
1
SEN
Set Negative Flag
N1
N
1
CLN
Clear Negative Flag
N0
N
1
SEZ
Set Zero Flag
Z1
Z
1
CLZ
Clear Zero Flag
Z0
Z
1
SEI
Global Interrupt Enable
I1
I
1
CLI
Global Interrupt Disable
I 0
I
1
1
SES
Set Signed Test Flag
S1
S
CLS
Clear Signed Test Flag
S0
S
1
SEV
Set Twos Complement Overflow.
V1
V
1
CLV
Clear Twos Complement Overflow
V0
V
1
SET
Set T in SREG
T1
T
1
CLT
Clear T in SREG
T0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H1
H0
H
H
1
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
Rd Rr
Rd+1:Rd Rr+1:Rr
LDI
Rd, K
Load Immediate
Rd K
None
1
LD
Rd, X
Load Indirect
Rd (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd (X), X X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X X - 1, Rd (X)
None
2
2
LD
Rd, Y
Load Indirect
Rd (Y)
None
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd (Y), Y Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y Y - 1, Rd (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd (Z), Z Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z Z - 1, Rd (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd (Z + q)
None
2
2
LDS
Rd, k
Load Direct from SRAM
Rd (k)
None
ST
X, Rr
Store Indirect
(X) Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) Rr, X X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X X - 1, (X) Rr
None
2
ST
Y, Rr
Store Indirect
(Y) Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) Rr, Y Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y Y - 1, (Y) Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) Rr
None
2
ST
Z, Rr
Store Indirect
(Z) Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) Rr, Z Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z Z - 1, (Z) Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) Rr
None
2
Load Program Memory
R0 (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd (Z), Z Z+1
None
3
Store Program Memory
(z) R1:R0
None
SPM
IN
Rd, P
In Port
Rd P
None
OUT
P, Rr
Out Port
P Rr
None
1
PUSH
Rr
Push Register on Stack
STACK Rr
None
2
POP
Rd
Pop Register from Stack
Rd STACK
None
2
1
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/Timer)
For On-chip Debug Only
None
None
1
N/A
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
10
6. Ordering Information
6.1
ATtiny25
Speed (MHz) (1)
Supply Voltage (V)
Temperature Range
Package (2)
Ordering Code (3)
8P3
ATtiny25V-10PU
8S2
ATtiny25V-10SU
ATtiny25V-10SUR
ATtiny25V-10SH
ATtiny25V-10SHR
S8S1
ATtiny25V-10SSU
ATtiny25V-10SSUR
ATtiny25V-10SSH
ATtiny25V-10SSHR
20M1
ATtiny25V-10MU
ATtiny25V-10MUR
8S2
ATtiny25V-10SN
ATtiny25V-10SNR
S8S1
ATtiny25V-10SSN
ATtiny25V-10SSNR
20M1
ATtiny25V-10MF
ATtiny25V-10MFR
8P3
ATtiny25-20PU
8S2
ATtiny25-20SU
ATtiny25-20SUR
ATtiny25-20SH
ATtiny25-20SHR
S8S1
ATtiny25-20SSU
ATtiny25-20SSUR
ATtiny25-20SSH
ATtiny25-20SSHR
20M1
ATtiny25-20MU
ATtiny25-20MUR
8S2
ATtiny25-20SN
ATtiny25-20SNR
S8S1
ATtiny25-20SSN
ATtiny25-20SSNR
20M1
ATtiny25-20MF
ATtiny25-20MFR
Industrial
(-40C to +85C) (4)
10
1.8 – 5.5
Industrial
(-40C to +105C) (5)
Industrial (-40C to +125C) (6)
Industrial
(-40C to +85C) (4)
20
2.7 – 5.5
Industrial
(-40C to +105C) (5)
Industrial (-40C to +125C) (6)
Notes:
1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163.
2. All Pb-free, halide-free, fully green, and comply with European directive for Restriction of Hazardous Substances (RoHS).
3. Code indicators: H = NiPdAu lead finish, U/N = matte tin, R = tape & reel.
4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.
5. For characteristics, see “Appendix A – Specification at 105C”.
6. For characteristics, see “Appendix B – Specification at 125C”.
Package Types
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
S8S1
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
11
6.2
ATtiny45
Speed (MHz) (1)
10
1.8 – 5.5
20
Notes:
Supply Voltage (V)
2.7 – 5.5
Temperature Range
Package (2)
Ordering Code (3)
8P3
ATtiny45V-10PU
8S2
ATtiny45V-10SU
ATtiny45V-10SUR
ATtiny45V-10SH
ATtiny45V-10SHR
8X
ATtiny45V-10XU
ATtiny45V-10XUR
20M1
ATtiny45V-10MU
ATtiny45V-10MUR
8P3
ATtiny45-20PU
8S2
ATtiny45-20SU
ATtiny45-20SUR
ATtiny45-20SH
ATtiny45-20SHR
8X
ATtiny45-20XU
ATtiny45-20XUR
20M1
ATtiny45-20MU
ATtiny45-20MUR
Industrial
(-40C to +85C) (4)
Industrial
(-40C to +85C) (4)
1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Package Types
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
8X
8-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
12
6.3
ATtiny85
Speed (MHz) (1)
10
1.8 – 5.5
20
Notes:
Supply Voltage (V)
2.7 – 5.5
Temperature Range
Industrial
(-40C to +85C) (4)
Industrial
(-40C to +85C) (4)
Package (2)
Ordering Code (3)
8P3
ATtiny85V-10PU
8S2
ATtiny85V-10SU
ATtiny85V-10SUR
ATtiny85V-10SH
ATtiny85V-10SHR
20M1
ATtiny85V-10MU
ATtiny85V-10MUR
8P3
ATtiny85-20PU
8S2
ATtiny85-20SU
ATtiny85-20SUR
ATtiny85-20SH
ATtiny85-20SHR
20M1
ATtiny85-20MU
ATtiny85-20MUR
1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Package Types
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20M1
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
13
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
MIN
MAX
NOM
A
b2
b3
b
4 PLCS
Side View
L
NOTE
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
0.100 BSC
eA
0.300 BSC
0.115
3
3
e
L
Notes:
0.210
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
14
7.2
8S2
C
1
E
E1
L
N
θ
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
SIDE VIEW
MAX
NOM
NOTE
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
4
C
0.15
0.35
4
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
θ
0°
8°
e
Notes: 1.
2.
3.
4.
MIN
A
1.27 BSC
2
3
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs aren't included.
Determines the true geometric position.
Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
GPC
STN
4/15/08
DRAWING NO. REV.
8S2
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
F
15
7.3
S8S1
1
E1
E
N
Top View
e
b
A
A1
D
Side View
C
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
MAX
NOM
E
5.79
6.20
E1
3.81
3.99
A
1.35
1.75
A1
0.1
0.25
D
4.80
4.98
C
0.17
0.25
b
0.31
0.51
L
0.4
1.27
e
NOTE
1.27 BSC
0o
8o
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
7/28/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small
Outline (JEDEC SOIC)
DRAWING NO.
S8S1
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
REV.
A
16
7.4
8X
C
1
E1
End View
E
L
Top View
e
Ø
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
MAX
1.05
1.10
1.20
A1
0.05
0.10
0.15
b
0.25
–
0.30
C
–
0.127
–
D
2.90
3.05
3.10
E1
4.30
4.40
4.50
E
6.20
6.40
6.60
A
D
Side View
MIN
NOM
SYMBOL
e
NOTE
0.65 TYP
L
0.50
0.60
0.70
Ø
0o
–
8o
Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC.
4/14/05
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8X, 8-lead, 4.4 mm Body Width, Plastic Thin Shrink
Small Outline Package (TSSOP)
DRAWING NO.
8X
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
REV.
A
17
7.5
20M1
D
1
Pin 1 ID
2
SIDE VIEW
E
3
TOP VIEW
A2
D2
A1
A
0.08
1
2
Pin #1
Notch
(0.20 R)
3
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
b
L
e
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
–
0.01
0.05
A2
b
0.18
D
D2
E2
L
0.23
0.30
4.00 BSC
2.45
2.60
2.75
4.00 BSC
2.45
e
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
NOTE
0.20 REF
E
Note:
C
2.60
2.75
0.50 BSC
0.35
0.40
0.55
10/27/04
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
20M1
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
REV.
B
18
8. Errata
8.1
Errata ATtiny25
The revision letter in this section refers to the revision of the ATtiny25 device.
8.1.1
Rev D – F
No known errata.
8.1.2
Rev B – C
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.
8.1.3
Rev A
Not sampled.
8.2
Errata ATtiny45
The revision letter in this section refers to the revision of the ATtiny45 device.
8.2.1
Rev F – G
No known errata
8.2.2
Rev D – E
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
19
8.2.3
Rev B – C
•
•
•
•
PLL not locking
EEPROM read from application code does not work in Lock Bit Mode 3
EEPROM read may fail at low supply voltage / low clock frequency
Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly
1. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
2. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the
application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
3. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.
4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly
Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when the control bits,
COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0, respectively, the OC1B-XOC1B output works correctly.
Problem Fix/Work around
The only workaround is to use same control setting on COM1A[1:0] and COM1B[1:0] control bits, see table 144 in the data sheet. The problem has been fixed for Tiny45 rev D.
8.2.4
Rev A
•
•
•
•
•
Too high power down power consumption
DebugWIRE looses communication when single stepping into interrupts
PLL not locking
EEPROM read from application code does not work in Lock Bit Mode 3
EEPROM read may fail at low supply voltage / low clock frequency
1. Too high power down power consumption
Three situations will lead to a too high power down power consumption. These are:
– An external clock is selected by fuses, but the I/O PORT is still enabled as an output.
– The EEPROM is read before entering power down.
– VCC is 4.5 volts or higher.
Problem fix / Workaround
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
20
– When using external clock, avoid setting the clock pin as Output.
– Do not read the EEPROM if power down power consumption is important.
– Use VCC lower than 4.5 Volts.
2. DebugWIRE looses communication when single stepping into interrupts
When receiving an interrupt during single stepping, debugwire will loose
communication.
Problem fix / Workaround
– When singlestepping, disable interrupts.
– When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt.
3. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
4. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the
application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
5. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterized. Guidelines are given for
room temperature, only.
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
21
8.3
Errata ATtiny85
The revision letter in this section refers to the revision of the ATtiny85 device.
8.3.1
Rev B – C
No known errata.
8.3.2
Rev A
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.
ATtiny25/45/85 [DATASHEET]
2586QS–AVR–08/2013
22
9. Datasheet Revision History
9.1
Rev. 2586Q-08/13
1.
9.2
Rev. 2586P-06/13
1.
9.3
“Bit 3 – FOC1B: Force Output Compare Match 1B” description in “GTCCR – General Timer/Counter1 Control
Register” on page 90 updated: PB3 in “compare match output pin PB3 (OC1B)” corrected to PB4.
Updated description of “EEARH – EEPROM Address Register” and “EEARL – EEPROM Address Register” on page
20.
Rev. 2586O-02/13
Updated ordering codes on page 11, page 12, and page 13.
9.4
Rev. 2586N-04/11
1. Added:
– Section “Capacitive Touch Sensing” on page 6.
2. Updated:
– Document template.
– Removed “Preliminary” on front page. All devices now final and in production.
– Section “Limitations” on page 36.
– Program example on page 49.
– Section “Overview” on page 122.
– Table 17-4 on page 135.
– Section “Limitations of debugWIRE” on page 140.
– Section “Serial Programming Algorithm” on page 151.
– Table 21-7 on page 166.
– EEPROM errata on pages 19, 19, 20, 21, and 22
– Ordering information on pages 11, 12, and 13.
9.5
Rev. 2586M-07/10
1. Clarified Section 6.4 “Clock Output Buffer” on page 31.
2. Added Ordering Codes -SN and -SNR for ATtiny25 extended temperature.
9.6
Rev. 2586L-06/10
1. Added:
– TSSOP for ATtiny45 in “Features” on page 1, Pinout Figure 1-1 on page 2, Ordering Information in
Section 6.2 “ATtiny45” on page 12, and Packaging Information in Section 7.4 “8X” on page 17
– Table 6-11, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29
– Figure 22-36 on page 191 and Figure 22-37 on page 191, Typical Characteristics plots for Bandgap
Voltage vs. VCC and Temperature
– Extended temperature in Section 6.1 “ATtiny25” on page 11, Ordering Information
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– Tape & reel part numbers in Ordering Information, in Section 6.1 “ATtiny25” on page 11 and Section
6.2 “ATtiny45” on page 12
2. Updated:
– “Features” on page 1, removed Preliminary from ATtiny25
– Section 8.4.2 “Code Example” on page 44
– “PCMSK – Pin Change Mask Register” on page 52, Bit Descriptions
– “TCCR1 – Timer/Counter1 Control Register” on page 89 and “GTCCR – General Timer/Counter1
Control Register” on page 90, COM bit descriptions clarified
– Section 20.3.2 “Calibration Bytes” on page 150, frequencies (8 MHz, 6.4 MHz)
– Table 20-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM Location,” on page 153,
value for tWD_ERASE
– Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,” on page 158
– Table 21-1, “DC Characteristics. TA = -40C to +85C,” on page 161, notes adjusted
– Table 21-11, “Serial Programming Characteristics, TA = -40C to +85C, VCC = 1.8 - 5.5V (Unless
Otherwise Noted),” on page 170, added tSLIV
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0].
9.7
Rev. 2586K-01/08
1. Updated Document Template.
2. Added Sections:
– “Data Retention” on page 6
– “Low Level Interrupt” on page 49
– “Device Signature Imprint Table” on page 149
3. Updated Sections:
– “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24
– “System Clock and Clock Options” on page 23
– “Internal PLL in ATtiny15 Compatibility Mode” on page 24
– “Sleep Modes” on page 34
– “Software BOD Disable” on page 35
– “External Interrupts” on page 49
– “Timer/Counter1 in PWM Mode” on page 97
– “USI – Universal Serial Interface” on page 108
– “Temperature Measurement” on page 133
– “Reading Lock, Fuse and Signature Data from Software” on page 143
– “Program And Data Memory Lock Bits” on page 147
– “Fuse Bytes” on page 148
– “Signature Bytes” on page 150
– “Calibration Bytes” on page 150
– “System and Reset Characteristics” on page 165
4. Added Figures:
– “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 184
– “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 185
– “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 185
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– “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 186
5. Updated Figure:
– “Reset Logic” on page 39
6. Updated Tables:
– “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28
– “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on page 28
– “Start-up Times for the 128 kHz Internal Oscillator” on page 28
– “Compare Mode Select in PWM Mode” on page 86
– “Compare Mode Select in PWM Mode” on page 98
– “DC Characteristics. TA = -40C to +85C” on page 161
– “Calibration Accuracy of Internal RC Oscillator” on page 164
– “ADC Characteristics” on page 167
7. Updated Code Example in Section:
– “Write” on page 17
8. Updated Bit Descriptions in:
– “MCUCR – MCU Control Register” on page 37
– “Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode” on page 77
– “Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode” on page 77
– “Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source” on page 138
– “SPMCSR – Store Program Memory Control and Status Register” on page 145.
9. Updated description of feature “EEPROM read may fail at low supply voltage / low clock frequency” in
Sections:
– “Errata ATtiny25” on page 19
– “Errata ATtiny45” on page 19
– “Errata ATtiny85” on page 22
10. Updated Package Description in Sections:
– “ATtiny25” on page 11
– “ATtiny45” on page 12
– “ATtiny85” on page 13
11. Updated Package Drawing:
– “S8S1” on page 16
12. Updated Order Codes for:
– “ATtiny25” on page 11
9.8
Rev. 2586J-12/06
1.
2.
3.
4.
5.
Updated “Low Power Consumption” on page 1.
Updated description of instruction length in “Architectural Overview” .
Updated Flash size in “In-System Re-programmable Flash Program Memory” on
page 15.
Updated cross-references in sections “Atomic Byte Programming” , “Erase” and
“Write” , starting on page 17.
Updated “Atomic Byte Programming” on page 17.
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6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
Replaced single clocking system figure with two: Figure 6-2 and Figure 6-3.
Updated Table 6-1 on page 25, Table 6-13 on page 30 and Table 6-6 on page 27.
Updated “Calibrated Internal Oscillator” on page 27.
Updated Table 6-5 on page 26.
Updated “OSCCAL – Oscillator Calibration Register” on page 31.
Updated “CLKPR – Clock Prescale Register” on page 32.
Updated “Power-down Mode” on page 35.
Updated “Bit 0” in “PRR – Power Reduction Register” on page 38.
Added footnote to Table 8-3 on page 46.
Updated Table 10-5 on page 63.
Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 64.
Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now
located on page 66.
Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 86.
Updated bit description in “PLLCSR – PLL Control and Status Register” on page 94
and “PLLCSR – PLL Control and Status Register” on page 103.
Added recommended maximum frequency in“Prescaling and Conversion Timing” on
page 125.
Updated Figure 17-8 on page 129 .
Updated “Temperature Measurement” on page 133.
Updated Table 17-3 on page 134.
Updated bit R/W descriptions in:
“TIMSK – Timer/Counter Interrupt Mask Register” on page 81,
“TIFR – Timer/Counter Interrupt Flag Register” on page 81,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 92,
“TIFR – Timer/Counter Interrupt Flag Register” on page 93,
“PLLCSR – PLL Control and Status Register” on page 94,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 102,
“TIFR – Timer/Counter Interrupt Flag Register” on page 103,
“PLLCSR – PLL Control and Status Register” on page 103 and
“DIDR0 – Digital Input Disable Register 0” on page 138.
Added limitation to “Limitations of debugWIRE” on page 140.
Updated “DC Characteristics” on page 161.
Updated Table 21-7 on page 166.
Updated Figure 21-6 on page 171.
Updated Table 21-12 on page 171.
Updated Table 22-1 on page 177.
Updated Table 22-2 on page 177.
Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 188.
Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 189.
Updated Table 22-39 on page 192.
Updated Table 22-46, Table 22-47, Table 22-48 and Table 22-49.
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9.9
Rev. 2586I-09/06
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
9.10
Rev. 2586H-06/06
1.
2.
3.
9.11
Updated “Calibrated Internal Oscillator” on page 27.
Updated Table 6.5.1 on page 31.
Added Table 21-2 on page 164.
Rev. 2586G-05/06
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
9.12
All Characterization data moved to “Electrical Characteristics” on page 161.
All Register Descriptions are gathered up in seperate sections in the end of each
chapter.
Updated Table 11-3 on page 78, Table 11-5 on page 79, Table 11-6 on page 80 and
Table 20-4 on page 148.
Updated “Calibrated Internal Oscillator” on page 27.
Updated Note in Table 7-1 on page 34.
Updated “System Control and Reset” on page 39.
Updated Register Description in “I/O Ports” on page 53.
Updated Features in “USI – Universal Serial Interface” on page 108.
Updated Code Example in “SPI Master Operation Example” on page 110 and “SPI
Slave Operation Example” on page 111.
Updated “Analog Comparator Multiplexed Input” on page 119.
Updated Figure 17-1 on page 123.
Updated “Signature Bytes” on page 150.
Updated “Electrical Characteristics” on page 161.
Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
Updated “Default Clock Source” on page 30.
Updated “Low-Frequency Crystal Oscillator” on page 29.
Updated “Calibrated Internal Oscillator” on page 27.
Updated “Clock Output Buffer” on page 31.
Updated “Power Management and Sleep Modes” on page 34.
Added “Software BOD Disable” on page 35.
Updated Figure 16-1 on page 119.
Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 120.
Added note for Table 17-2 on page 125.
Updated “Register Summary” on page 7.
Rev. 2586F-04/06
1.
2.
3.
Updated “Digital Input Enable and Sleep Modes” on page 57.
Updated Table 20-16 on page 158.
Updated “Ordering Information” on page 11.
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9.13
Rev. 2586E-03/06
1.
2.
3.
4.
5.
9.14
Rev. 2586D-02/06
1.
2.
3.
4.
5.
6.
7.
8.
9.
9.15
Updated “Features” on page 1.
Updated Figure 1-1 on page 2.
Updated Code Examples on page 18 and page 19.
Moved “Temperature Measurement” to Section 17.12 page 133.
Updated “Register Summary” on page 7.
Updated “Ordering Information” on page 11.
Rev. 2586B-05/05
1.
2.
3.
4.
5.
6.
7.
8.
9.
9.17
Updated Table 6-13 on page 30, Table 6-10 on page 29, Table 6-3 on page 26,
Table 6-9 on page 28, Table 6-5 on page 26, Table 9-1 on page 48,Table 17-4 on
page 135, Table 20-16 on page 158, Table 21-8 on page 167.
Updated “Timer/Counter1 in PWM Mode” on page 86.
Updated text “Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page 93.
Updated values in “DC Characteristics” on page 161.
Updated “Register Summary” on page 7.
Updated “Ordering Information” on page 11.
Updated Rev B and C in “Errata ATtiny45” on page 19.
All references to power-save mode are removed.
Updated Register Adresses.
Rev. 2586C-06/05
1.
2.
3.
4.
5.
6.
9.16
Updated Features in “Analog to Digital Converter” on page 122.
Updated Operation in “Analog to Digital Converter” on page 122.
Updated Table 17-2 on page 133.
Updated Table 17-3 on page 134.
Updated “Errata” on page 19.
CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some
TBD.
Removed “Preliminary Description” from “Temperature Measurement” on page 133.
Updated “Features” on page 1.
Updated Figure 1-1 on page 2 and Figure 8-1 on page 39.
Updated Table 7-2 on page 38, Table 10-4 on page 63, Table 10-5 on page 63
Updated “Serial Programming Instruction set” on page 153.
Updated SPH register in “Instruction Set Summary” on page 9.
Updated “DC Characteristics” on page 161.
Updated “Ordering Information” on page 11.
Updated “Errata” on page 19.
Rev. 2586A-02/05
Initial revision.
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