ATTINY828-AUR

ATtiny828 8-bit AVR Microcontroller with 8K Bytes In-System Programmable Flash DATASHEET Features z High Performance, Low Power Atmel® AVR® 8-bit Microcontroller z Advanced RISC Architecture z 123 Powerful Instructions – Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers z Fully Static Operation z Up to 20 MIPS Throughput at 20 MHz z z Non-volatile Program and Data Memories z z z z z 8K Bytes of In-System Programmable Flash Program Memory z Endurance: 10,000 Write/Erase Cycles 256 Bytes of In-System Programmable EEPROM z Endurance: 100,000 Write/Erase Cycles 512 Bytes Internal SRAM Optional Boot Code Section with Independent Lock Bits Data Retention: 20 Years at 85oC / 100 Years at 25oC z Peripheral Features z z z z z z z One 8-bit and one 16-bit Timer/Counter with Two PWM Channels, Each Programmable Ultra Low Power Watchdog Timer On-chip Analog Comparator 10-bit Analog to Digital Converter z 28 External and 4 Internal, Single-ended Input Channels Full Duplex USART with Start Frame Detection Master/Slave SPI Serial Interface Slave I2C Serial Interface z Special Microcontroller Features z z z z z z z Low Power Idle, ADC Noise Reduction, and Power-down Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit with Supply Voltage Sampling External and Internal Interrupt Sources z Pin Change Interrupt on 28 Pins Calibrated 8MHz Oscillator with Temperature Calibration Option Calibrated 32kHz Ultra Low Power Oscillator High-Current Drive Capability on 8 I/O Pins z I/O and Packages z 32-lead TQFP, and 32-pad QFN/MLF: 28 Programmable I/O Lines z Speed Grade z 0 – 2 MHz @ 1.7 – 1.8V 0 – 4 MHz @ 1.8 – 5.5V z 0 – 10 MHz @ 2.7 – 5.5V z 0 – 20 MHz @ 4.5 – 5.5V z 8371A–AVR–08/12 z Low Power Consumption z Active Mode: 0.2 mA at 1.8V and 1MHz Idle Mode: 30 µA at 1.8V and 1MHz z Power-Down Mode (WDT Enabled): 1 µA at 1.8V z Power-Down Mode (WDT Disabled): 100 nA at 1.8V z Pin Configurations ATtiny828 Pinout in MLF32. 32 31 30 29 28 27 26 25 PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO) PC0 (PCINT16/ADC16/TOCC0/SS/XCK) PD3 (PCINT27/ADC27/SCL/SCK) PD2 (PCINT26/ADC26/RESET/DW) PD1 (PCINT25/ADC25/MISO) PD0 (PCINT24/ADC24/SDA/MOSI) PB7 (PCINT15/ADC15) PB6 (PCINT14/ADC14) Figure 1. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 PB5 (PCINT13/ADC13) PB4 (PCINT12/ADC12) PB3 (PCINT11/ADC11) GND PB2 (PCINT10/ADC10) PB1 (PCINT9/ADC9) AVCC PB0 (PCINT8/ADC8) 24 23 22 21 20 19 18 17 PB5 (PCINT13/ADC13) PB4 (PCINT12/ADC12) PB3 (PCINT11/ADC11) GND PB2 (PCINT10/ADC10) PB1 (PCINT9/ADC9) AVCC PB0 (PCINT8/ADC8) (PCINT0/ADC0) PA0 (PCINT1/ADC1/AIN0) PA1 (PCINT2/ADC2/AIN1) PA2 (PCINT3/ADC3) PA3 (PCINT4/ADC4) PA4 (PCINT5/ADC5) PA5 (PCINT6/ADC6) PA6 (PCINT7/ADC7) PA7 9 10 11 12 13 14 15 16 (PCINT18/ADC18/TOCC2/RXD/INT1) PC2 (PCINT19/ADC19/TOCC3/TXD) PC3 (PCINT20/ADC20/TOCC4) PC4 VCC GND (PCINT21/ADC21/TOCC5/ICP1/T0) PC5 (PCINT22/ADC22/CLKI/TOCC6) PC6 (PCINT23/ADC23/TOCC7/T1) PC7 NOTE: Bottom pad should be soldered to ground 32 31 30 29 28 27 26 25 PC1 (PCINT17/ADC17/TOCC1/INT0/CLKO) PC0 (PCINT16/ADC16/TOCC0/SS/XCK) PD3 (PCINT27/ADC27/SCL/SCK) PD2 (PCINT26/ADC26/RESET/DW) PD1 (PCINT25/ADC25/MISO) PD0 (PCINT24/ADC24/SDA/MOSI) PB7 (PCINT15/ADC15) PB6 (PCINT14/ADC14) ATtiny828 Pinout in TQFP32. (PCINT18/ADC18/TOCC2/RXD/INT1) PC2 (PCINT19/ADC19/TOCC3/TXD) PC3 (PCINT20/ADC20/TOCC4) PC4 VCC GND (PCINT21/ADC21/TOCC5/ICP1/T0) PC5 (PCINT22/ADC22/CLKI/TOCC6) PC6 (PCINT23/ADC23/TOCC7/T1) PC7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 2. (PCINT0/ADC0) PA0 (PCINT1/ADC1/AIN0) PA1 (PCINT2/ADC2/AIN1) PA2 (PCINT3/ADC3) PA3 (PCINT4/ADC4) PA4 (PCINT5/ADC5) PA5 (PCINT6/ADC6) PA6 (PCINT7/ADC7) PA7 1. ATtiny828 [DATASHEET] 8371A–AVR–08/12 2 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 AVCC AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected to VCC even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to VCC through a low-pass filter, as described in “Noise Canceling Techniques” on page 145. All pins of Port A and Port B are powered by AVCC. All other I/O pins take their supply voltage from VCC. 1.1.3 GND Ground. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 107 on page 250. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.5 Port A (PA7:PA0) This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink and standard source capability. See Table 107 on page 250 for port drive strength. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, the analog comparator, and ADC. See “Alternative Port Functions” on page 63. 1.1.6 Port B (PB7:PB0) This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink and standard source capability. See Table 103 on page 247 for port drive strength. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, and ADC. See “Alternative Port Functions” on page 63. 1.1.7 Port C (PC7:PC0) This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have high sink and standard source capability. Optionally, extra high sink capability can be enabled. See Table 103 on page 247 for port drive strength. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, ADC, timer/counter, external interrupts, and serial interfaces. See “Alternative Port Functions” on page 63. 1.1.8 Port D (PD3:PD0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers of PD0 and PD3 have symmetrical drive characteristics, with both sink and source capability. Output buffer PD1 has high sink and ATtiny828 [DATASHEET] 8371A–AVR–08/12 3 standard source capability, while PD2 only has weak drive characteristics due to its use as a reset pin. See Table 103 on page 247 for port drive strength. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, ADC, serial interfaces, and debugWire. See “Alternative Port Functions” on page 63. ATtiny828 [DATASHEET] 8371A–AVR–08/12 4 2. Overview ATtiny828 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny828 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 3. VCC Block Diagram RESET GND ON-CHIP DEBUGGER POWER SUPERVISION: POR BOD RESET EEPROM CALIBRATED ULP OSCILLATOR CALIBRATED OSCILLATOR WATCHDOG TIMER ISP INTERFACE DEBUG INTERFACE 8-BIT TIMER/COUNTER 16-BIT TIMER/COUNTER TWO-WIRE INTERFACE USART TIMING AND CONTROL PROGRAM MEMORY DATA MEMORY (FLASH) (SRAM) TEMPERATURE SENSOR CPU CORE ANALOG COMPARATOR MULTIPLEXER VOLTAGE REFERENCE ADC 8-BIT DATA BUS PORT A PORT B PORT C PORT D PA[7:0] PB[7:0] PC[7:0] PD[3:0] The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. ATtiny828 [DATASHEET] 8371A–AVR–08/12 5 ATtiny828 provides the following features: z 8K bytes of in-system programmable Flash z 512 bytes of SRAM data memory z 256 bytes of EEPROM data memory z 28 general purpose I/O lines z 32 general purpose working registers z An 8-bit timer/counter with two PWM channels z A16-bit timer/counter with two PWM channels z Internal and external interrupts z A 10-bit ADC with 4 internal and 28 external chanels z An ultra-low power, programmable watchdog timer with internal oscillator z A programmable USART with start frame detection z A slave, I2C compliant Two-Wire Interface (TWI) z A master/slave Serial Peripheral Interface (SPI) z A calibrated 8MHz oscillator z A calibrated 32kHz, ultra low power oscillator z Three software selectable power saving modes. The device includes the following modes for saving power: z Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt system to continue functioning z ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC z Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program memory can be re-programmed in-system through a serial interface, by a conventional non-volatile memory programmer or by an onchip boot code, running on the AVR core. The boot program can use any interface to download the application program to the Flash memory. Software in the boot section of the Flash executes while the application section of the Flash is updated, providing true read-while-write operation. The ATtiny828 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. ATtiny828 [DATASHEET] 8371A–AVR–08/12 6 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATtiny828 [DATASHEET] 8371A–AVR–08/12 7 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4. Block Diagram of the AVR Architecture 8-BIT DATA BUS INDIRECT ADDRESSING DATA MEMORY (SRAM) PROGRAM COUNTER PROGRAM MEMORY (FLASH) INSTRUCTION REGISTER INTERRUPT UNIT STATUS AND CONTROL GENERAL PURPOSE REGISTERS DIRECT ADDRESSING 4.1 X Y Z ALU INSTRUCTION DECODER CONTROL LINES In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. ATtiny828 [DATASHEET] 8371A–AVR–08/12 8 Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. Program Flash memory is divided in two sections; the boot program section and the application program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction, which is used to write the application memory section, must reside in the boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATtiny828 has Extended I/O Space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See external document “AVR Instruction Set” and “Instruction Set Summary” on page 301 section for more information. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. See external document “AVR Instruction Set” and “Instruction Set Summary” on page 301 section for more information. The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: z One 8-bit output operand and one 8-bit result input z Two 8-bit output operands and one 8-bit result input z Two 8-bit output operands and one 16-bit result input z One 16-bit output operand and one 16-bit result input Figure 5 below shows the structure of the 32 general purpose working registers in the CPU. ATtiny828 [DATASHEET] 8371A–AVR–08/12 9 Figure 5. General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 R3 0x03 … ... R12 0x0C R13 0x0D R14 0x0E R15 0x0F R16 0x10 R17 0x11 Special Function … ... R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File are single cycle instructions with direct access to all registers. As shown in Figure 5, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6 below. Figure 6. The X-, Y-, and Z-registers 15 X-register 7 0 XH 0 7 R27 XL R26 15 Y-register 7 0 YH 0 7 R29 YL 7 0 R28 15 Z-register 0 0 ZH R31 0 7 ZL 0 R30 ATtiny828 [DATASHEET] 8371A–AVR–08/12 10 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack grows from higher memory locations to lower memory locations. This means that the PUSH instructions decreases and the POP instruction increases the stack pointer value. The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space must be defined by the program before any subroutine calls are executed or interrupts are enabled. The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction). The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer and the number of bits implemented is device dependent. In some AVR devices all data memory can be addressed using SPL, only. In this case, the SPH register is not implemented. The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of SRAM. See Table 3 on page 17. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 8 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. ATtiny828 [DATASHEET] 8371A–AVR–08/12 11 Figure 8. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the value of the program counter, interrupts may be automatically disabled when Boot Lock Bits (BLB02 or BLB12) are programmed. This feature improves software security. See section “Lock Bits” on page 225 for details. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 48. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The interrupt vector table can be moved to the start of Flash boot section by setting the IVSEL bit. For more information, see “MCUCR – MCU Control Register” on page 53 and “Interrupts” on page 48. The reset vector can also be moved to the start of Flash boot section by programming the BOOTRST fuse. See “Entering the Boot Loader Program” on page 216. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. ATtiny828 [DATASHEET] 8371A–AVR–08/12 12 When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in cli sbi sbi out r16, SREG ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write EECR, EEMPE EECR, EEPE SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; _CLI(); EECR |= (1