ATTINY841-SSUR

ATtiny441/ATtiny841 8-bit AVR Microcontroller with 4/8K Bytes In-System Programmable Flash SUMMARY DATASHEET Features  High Performance, Low Power Atmel® AVR® 8-bit Microcontroller  Advanced RISC Architecture     120 Powerful Instructions – Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz  Non-volatile Program and Data Memories      4/8K Bytes of In-System Programmable Flash Program Memory  Endurance: 10,000 Write/Erase Cycles 256/512 Bytes of In-System Programmable EEPROM  Endurance: 100,000 Write/Erase Cycles 256/512 Bytes Internal SRAM Data Retention: 20 Years at 85oC / 100 Years at 25oC Programming Lock for Self-Programming Flash & EEPROM Data Security  Peripheral Features        One 8-bit and Two 16-bit Timer/Counters with Two PWM Channels, Each Programmable Ultra Low Power Watchdog Timer 10-bit Analog to Digital Converter  12 External and 5 Internal, Single-ended Input Channels  46 Differential ADC Channel Pairs with Programmable Gain (1x / 20x / 100x) Two On-chip Analog Comparators Two Full Duplex USARTs with Start Frame Detection Master/Slave SPI Serial Interface Slave I2C Serial Interface  Special Microcontroller Features     Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes Enhanced Power-on Reset Circuit Programmable Brown-out Detection Circuit with Supply Voltage Sampling External and Internal Interrupt Sources  Pin Change Interrupt on 12 Pins  Calibrated 8MHz Oscillator with Temperature Calibration Option  Calibrated 32kHz Ultra Low Power Oscillator  High-Current Drive Capability on 2 I/O Pins  I/O and Packages   14-pin SOIC, 20-pad MLF/QFN and 20-pad VQFN 12 Programmable I/O Lines  Speed Grade     0 – 2 MHz @ 1.7 – 1.8V 0 – 4 MHz @ 1.8 – 5.5V 0 – 10 MHz @ 2.7 – 5.5V 0 – 16 MHz @ 4.5 – 5.5V  Low Power Consumption     Active Mode: 0.2 mA at 1.8V and 1MHz Idle Mode: 30 µA at 1.8V and 1MHz Power-Down Mode (WDT Enabled): 1.3µA at 1.8V Power-Down Mode (WDT Disabled): 150nA at 1.8V 8495HS–AVR–05/2014 1. Pin Configurations Figure 1-1. Pinout in 14-pin SOIC. (PCINT8/ADC11/XTAL1/CLKI) (PCINT9/ADC10/XTAL2/INT0) (PCINT11/ADC9/RESET/dW) (PCINT10/ADC8/CLKO/TOCC7/ICP2/RXD0) (PCINT7/ADC7/TOCC6/ICP1/TXD0/SS) (PCINT6/ADC6/ACO1/TOCC5/XCK1/SDA/MOSI) VCC PB0 PB1 PB3 PB2 PA7 PA6 1 14 2 13 3 12 4 11 5 10 6 9 7 8 GND PA0 (PCINT0/ADC0/AREF/MISO) PA1 (PCINT1/ADC1/AIN00/TOCC0/TXD0/MOSI) PA2 (PCINT2/ADC2/AIN01/TOCC1/RXD0/SS) PA3 (PCINT3/ADC3/AIN10/TOCC2/T0/XCK0/SCK) PA4 (PCINT4/ADC4/AIN11/TOCC3/T1/RXD1/SCL/SCK) PA5 (PCINT5/ADC5/ACO0/TOCC4/T2/TXD1/MISO) Bottom pad should be 16 17 18 13 4 12 5 11 10 3 9 14 8 15 2 PA7 PB2 PB3 PB1 PB0 (PCINT7/ADC7/TOCC6/ICP1/TXD0/SS) (PCINT10/ADC8/CLKO/TOCC7/ICP2/RXD0) (PCINT11/ADC9/RESET/dW) (PCINT9/ADC10/XTAL2/INT0) (PCINT8/ADC11/XTAL1/CLKI) DNC DNC GND VCC DNC NOTE 19 1 7 PA4 PA3 PA2 PA1 PA0 6 (PCINT4/ADC4/AIN11/TOCC3/T1/RXD1/SCL/SCK) (PCINT3/ADC3/AIN10/TOCC2/T0/XCK0/SCK) (PCINT2/ADC2/AIN01/TOCC1/RXD0/SS) (PCINT1/ADC1/AIN00/TOCC0/TXD0/MOSI) (PCINT0/ADC0/AREF/MISO) 20 PA5 (PCINT5/ADC5/ACO0/TOCC4/T2/TXD1/MISO) DNC DNC DNC PA6 (PCINT6/ADC6/ACO1/TOCC5/XCK1/SDA/MOSI) Figure 1-2. Pinout in 20-pad VQFN/WQFN. soldered to ground. DNC: Do Not Connect 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 2 1.1.3 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.4 Port A (PA7:PA0) This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have standard sink and source capability, except ports PA7 and PA5, which have high sink capability. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, the analog comparator, and ADC. 1.1.5 Port B (PB3:PB0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have standard sink and source capability. As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. This port has alternative pin functions for pin change interrupts, and ADC. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 3 2. Overview ATtiny441/841 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny441/841 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram VCC RESET GND DEBUG INTERFACE ON-CHIP DEBUGGER POWER SUPERVISION: POR BOD RESET EEPROM CALIBRATED ULP OSCILLATOR CALIBRATED OSCILLATOR WATCHDOG TIMER ISP INTERFACE TWO-WIRE INTERFACE USART USART 8-BIT TIMER/COUNTER 16-BIT TIMER/COUNTER TIMING AND CONTROL 16-BIT TIMER/COUNTER PROGRAM MEMORY DATA MEMORY (FLASH) (SRAM) CPU CORE TEMPERATURE SENSOR VOLTAGE REFERENCE ANALOG COMPARATOR MULTIPLEXER ANALOG COMPARATOR ADC 8-BIT DATA BUS PORT A PORT B PA[7:0] PB[3:0] ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 4 The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. ATtiny441/841 provides the following features:  4K/8K bytes of in-system programmable Flash  256/512 bytes of SRAM data memory  256/512 bytes of EEPROM data memory  12 general purpose I/O lines  32 general purpose working registers  One 8-bit timer/counter with two PWM channels  Two 16-bit timer/counters with two PWM channels  Internal and external interrupts  One 10-bit ADC with 5 internal and 12 external channels  One ultra-low power, programmable watchdog timer with internal oscillator  Two programmable USARTs with start frame detection  Slave Two-Wire Interface (TWI)  Master/slave Serial Peripheral Interface (SPI)  Calibrated 8MHz oscillator  Calibrated 32kHz, ultra low power oscillator  Four software selectable power saving modes. The device includes the following modes for saving power:  Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt system to continue functioning  ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC  Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset  Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program memory can be re-programmed in-system through a serial interface, by a conventional non-volatile memory programmer or by an onchip boot code, running on the AVR core. The ATtiny441/841 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 5 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 6 4. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved – – – – – – – – (0xFE) Reserved – – – – – – – – (0xFD) Reserved – – – – – – – – (0xFC) Reserved – – – – – – – – (0xFB) Reserved – – – – – – – – (0xFA) Reserved – – – – – – – – (0xF9) Reserved – – – – – – – – (0xF8) Reserved – – – – – – – – (0xF7) Reserved – – – – – – – – (0xF6) Reserved – – – – – – – – (0xF5) Reserved – – – – – – – – (0xF4) Reserved – – – – – – – – (0xF3) Reserved – – – – – – – – (0xF2) Reserved – – – – – – – – (0xF1) Reserved – – – – – – – – (0xF0) Reserved – – – – – – – – (0xEF) Reserved – – – – – – – – Page(s) (0xEE) Reserved – – – – – – – – (0xED) Reserved – – – – – – – – (0xEC) Reserved – – – – – – – – (0xEB) Reserved – – – – – – – – (0xEA) Reserved – – – – – – – – (0xE9) Reserved – – – – – – – – (0xE8) Reserved – – – – – – – – (0xE7) Reserved – – – – – – – – (0xE6) Reserved – – – – – – – – (0xE5) Reserved – – – – – – – – (0xE4) Reserved – – – – – – – – (0xE3) Reserved – – – – – – – – (0xE2) Reserved – – – – – – – – (0xE1) Reserved – – – – – – – – (0xE0) Reserved – – – – – – – – (0xDF) Reserved – – – – – – – – (0xDE) Reserved – – – – – – – – (0xDD) Reserved – – – – – – – – (0xDC) Reserved – – – – – – – – (0xDB) Reserved – – – – – – – – (0xDA) Reserved – – – – – – – – (0xD9) Reserved – – – – – – – – (0xD8) Reserved – – – – – – – – (0xD7) Reserved – – – – – – – – (0xD6) Reserved – – – – – – – – (0xD5) Reserved – – – – – – – – (0xD4) Reserved – – – – – – – – (0xD3) Reserved – – – – – – – – (0xD2) Reserved – – – – – – – – (0xD1) Reserved – – – – – – – – (0xD0) Reserved – – – – – – – – (0xCF) Reserved – – – – – – – – (0xCE) Reserved – – – – – – – – (0xCD) Reserved – – – – – – – – (0xCC) Reserved – – – – – – – – (0xCB) Reserved – – – – – – – – (0xCA) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Page 111 (0xC9) TCCR2B ICNC2 ICES2 – WGM23 WGM22 CS22 CS21 CS20 Page 114 (0xC8) TCCR2C FOC2A FOC2B – – – – – – (0xC7) TCNT2H Timer/Counter2 – Counter Register High Byte Page 115 Page 116 (0xC6) TCNT2L Timer/Counter2 – Counter Register Low Byte Page 116 (0xC5) OCR2AH Timer/Counter2 – Output Compare Register A High Byte Page 117 (0xC4) OCR2AL Timer/Counter2 – Output Compare Register A Low Byte Page 117 (0xC3) OCR2BH Timer/Counter2 – Output Compare Register B High Byte Page 117 (0xC2) OCR2BL Timer/Counter2 – Output Compare Register B Low Byte Page 117 (0xC1) ICR2H Timer/Counter1 – Input Capture Register High Byte Page 118 (0xC0) ICR2L (0xBF) Reserved Timer/Counter1 – Input Capture Register Low Byte – – – – – – Page 118 – – ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 7 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xBE) Reserved – – – – – – – – (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) Reserved – – – – – – – – (0xB9) Reserved – – – – – – – – (0xB8) Reserved – – – – – – – – (0xB7) Reserved – – – – – – – – (0xB6) Reserved – – – – – – – – (0xB5) Reserved – – – – – – – – (0xB4) Reserved – – – – – – – – (0xB3) Reserved – – – – – – – – (0xB2) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Page 157 (0xB1) SPSR SPIF WCOL – – – – – SPI2X Page 158 (0xB0) SPDR (0xAF) Reserved – – – SPI Data Register – – – – Page(s) Page 159 – (0xAE) Reserved – – – – – – – – (0xAD) Reserved – – – – – – – – (0xAC) Reserved – – – – – – – – (0xAB) Reserved – – – – – – – – (0xAA) Reserved – – – – – – – – (0xA9) Reserved – – – – – – – – (0xA8) Reserved – – – – – – – – (0xA7) Reserved – – – – – – – – (0xA6) Reserved – – – – – – – – (0xA5) TWSCRA TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME Page 205 (0xA4) TWSCRB – – – – TWHNM TWAA TWCMD1 TWCMD0 Page 205 (0xA3) TWSSRA TWDIF TWASIF TWCH TWRA TWC TWBE TWDIR TWAS Page 207 (0xA2) TWSA (0xA1) TWSAM (0xA0) TWSD (0x9F) Reserved (0x9E) Reserved – – – – – – – – (0x9D) Reserved – – – – – – – – (0x9C) Reserved – – – – – – – – (0x9B) Reserved – – – – – – – – (0x9A) Reserved – – – – – – – – (0x99) Reserved – – – – – – – – (0x98) Reserved – – – – – – – – (0x97) Reserved – – – – – – – – (0x96) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 (0x95) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 Page 182, 194 (0x94) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 Page 183, 195 (0x93) UCSR1D RXSIE1 RXS1 SFDE1 – – – – – (0x92) UBRR1H USART1 Baud Register High Byte (0x91) UBRR1L USART1 Baud Rate Register Low Byte Page 186, 196 (0x90) UDR1 USART1 Data Register Pages 180, 192 TWI Slave Address Register Page 208 TWI Slave Address Mask Register TWAE TWI Slave Data Register – – – – Page 208 Page 209 – – – – Page 181, 193 Page 185 Page 186, 196 (0x8F) Reserved – – – – – – – – (0x8E) Reserved – – – – – – – – (0x8D) Reserved – – – – – – – – (0x8C) Reserved – – – – – – – – (0x8B) Reserved – – – – – – – – (0x8A) Reserved – – – – – – – – (0x89) Reserved – – – – – – – – (0x88) Reserved – – – – – – – – (0x87) Reserved – – – – – – – – (0x86) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 (0x85) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 Page 182, 194 (0x84) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 Page 183, 195 (0x83) UCSR0D RXSIE0 RXS0 SFDE0 – – – – – (0x82) UBRR0H USART0 Baud Register High Byte (0x81) UBRR0L USART0 Baud Rate Register Low Byte Page 186, 196 (0x80) UDR0 USART0 Data Register Pages 180, 192 Page 181, 193 Page 185 Page 186, 196 (0x7F) Reserved – – – – – – – – (0x7E) Reserved – – – – – – – – (0x7D) Reserved – – – – – – – – (0x7C) Reserved – – – – – – – – (0x7B) Reserved – – – – – – – – ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 8 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7A) Reserved – – – – – – – – (0x79) Reserved – – – – – – – – (0x78) Reserved – – – – – – – – (0x77) OSCCAL1 – – – – – – CAL11 CAL10 (0x76) OSCTCAL0B Oscillator Temperature Compensation Register B (0x75) OSCTCAL0A Oscillator Temperature Compensation Register A (0x74) OSCCAL0 CAL07 CAL06 CAL05 CAL04 CAL03 CAL02 Page(s) Page 34 Page 34 Page 33 CAL01 CAL00 Page 33 (0x73) CLKPR – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Page 32 (0x72) CLKCR OSCRDY CSTR CKOUTC SUT CKSEL3 CKSEL2 CKSEL1 CKSEL0 Page 31 PRTWI PRUSART1 PRUSART0 PRTIM1 PRTIM0 PRADC Page 38 (0x71) CCP (0x70) PRR CPU Change Protection Register PRSPI Page 13 PRTIM2 (0x6F) Reserved – – – – – – – – (0x6E) Reserved – – – – – – – – (0x6D) Reserved – – – – – – – – (0x6C) Reserved – – – – – – – – (0x6B) Reserved – – – – – – – – (0x6A) PHDE – – – – – – PHDEA1 PHDEA0 (0x69) Reserved – – – – – – – – (0x68) TOCPMSA1 TOCC7S1 TOCC7S0 TOCC6S1 TOCC6S0 TOCC5S1 TOCC5S0 TOCC4S1 TOCC4S0 Page 115 (0x67) TOCPMSA0 TOCC3S1 TOCC3S0 TOCC2S1 TOCC2S0 TOCC1S1 TOCC1S0 TOCC0S1 TOCC0S0 Page 115 (0x66) TOCPMCOE TOCC7OE TOCC6OE TOCC5OE TOCC4OE TOCC3OE TOCC2OE TOCC1OE TOCC0OE Page 116 (0x65) REMAP – – – – – – SPIMAP U0MAP Pages 159, 186 (0x64) PORTCR – – – – – – BBMB BBMA Page 71 (0x63) PUEA PUEA7 PUEA6 PUEA5 PUEA4 PUEA3 PUEA2 PUEA1 PUEA0 Page 73 Page 71 (0x62) PUEB – – – – PUEB3 PUEB2 PUEB1 PUEB0 Page 71 (0x61) DIDR1 – – – – ADC9D ADC8D ADC10D ADC11D Page 150 Pages 127, 131, 149 (0x60) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 0x3F (0x5F) SREG I T H S V N Z C Page 14 0x3E (0x5E) SPH – – – – – – SP9 SP8 Page 13 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Page 13 0x3C (0x5C) OCR0B 0x3B (0x5B) GIMSK – INT0 PCIE1 PCIE0 – – – Page 52 0x3A (0x5A) GIFR – INTF0 PCIF1 PCIF0 – – – – Page 53 0x39 (0x59) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 Page 90 0x38 (0x58) TIFR0 – – – – – OCF0B OCF0A TOV0 Page 90 0x37 (0x57) SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN Page 217 0x36 (0x56) OCR0A 0x35 (0x55) MCUCR Page 38, 52 Timer/Counter0 – Output Compare Register B – Page 89 Timer/Counter0 – Output Compare Register A – – SE SM1 Page 89 SM0 – ISC01 ISC00 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF Page 46 0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Page 88 – – – – – – 0x32 (0x52) TCNT0 0x31 (0x51) Reserved Timer/Counter0 – Counter Register – Page 89 – 0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Page 85 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Page 111 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Page 114 0x2E (0x4E) TCCR1B 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte Page 116 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte Page 116 0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte Page 117 0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte Page 117 0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte Page 117 0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte Page 117 0x27 (0x47) DWDR debugWire Data Register Page 211 0x26 (0x46) Reserved 0x25 (0x45) ICR1H Timer/Counter1 – Input Capture Register High Byte Page 118 0x24 (0x44) ICR1L Timer/Counter1 – Input Capture Register Low Byte Page 118 – – – – – – – – 0x23 (0x43) GTCCR TSM – – – – – – PSR Page 122 0x22 (0x42) TCCR1C FOC1A FOC1B – – – – – – Page 115 0x21 (0x41) WDTCSR WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 Page 47 0x20 (0x40) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 Page 54 0x1F (0x3F) EEARH EEPROM Address Register High Byte Page 21 0x1E (0x3E) EEARL EEPROM Address Register Low Byte Page 22 0x1D (0x3D) EEDR 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 73 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Page 73 0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 73 0x18 (0x38) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 Page 72 0x17 (0x37) DDRB – – – – DDB3 DDB2 DDB1 DDB0 Page 72 EEPROM Data Register Page 22 Page 22 ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 9 Note: Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s) 0x16 (0x36) PINB – – – – PINB3 PINB2 PINB1 PINB0 Page 72 0x15 (0x35) GPIOR2 General Purpose I/O Register 2 Page 24 0x14 (0x34) GPIOR1 General Purpose I/O Register 1 Page 24 0x13 (0x33) GPIOR0 General Purpose I/O register 0 0x12 (0x32) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 Page 24 PCINT3 PCINT2 PCINT1 PCINT0 Page 54 0x11 (0x31) TIMSK2 – – ICIE2 – – OCIE2B OCIE2A TOIE2 Page 118 0x10 (0x30) TIFR2 – – ICF2 – – OCF2B OCF2A TOV2 Page 119 0x0F (0x2F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 Page 118 0x0E (0x2E) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 Page 119 0x0D (0x2D) ACSR1B HSEL1 HLEV1 – ACOE1 – ACME1 – – Page 130 0x0C (0x2C) ACSR1A ACD1 ACBG1 ACO1 ACI1 ACIE1 ACIC1 ACIS11 ACIS10 Page 129 0x0B (0x2B) ACSR0B HSEL0 HLEV0 – ACOE0 ACNMUX01 ACNMUX00 ACPMUX01 ACPMUX00 Page 126 0x0A (0x2A) ACSR0A ACD0 ACPMUX02 ACO0 ACI0 ACIE0 ACIC0 ACIS01 ACIS00 Page 125 0x09 (0x29) ADMUXA – – MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 Page 143 0x08 (0x28) ADMUXB REFS2 REFS1 REFS0 – – – GSEL1 GSEL0 0x07 (0x27) ADCH ADC – Conversion Result High Byte Page 146 Page 147 0x06 (0x26) ADCL 0x05 (0x25) ADCSRA ADEN ADSC ADATE ADC – Conversion Result Low Byte ADIF ADIE ADPS2 ADPS1 ADPS0 Page 148 Page 147 0x04 (0x24) ADCSRB – – – – ADLAR ADTS2 ADT1 ADTS0 Page 149 0x03 (0x23) Reserved – – – – – – – – 0x02 (0x22) Reserved – – – – – – – – 0x01 (0x21) Reserved – – – – – – – – 0x00 (0x20) Reserved – – – – – – – – 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 10 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks 1 ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd  Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl  Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd  Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd  Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl  Rdh:Rdl - K Z,C,N,V,S 2 1 AND Rd, Rr Logical AND Registers Rd Rd  Rr Z,N,V ANDI Rd, K Logical AND Register and Constant Rd  Rd K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd  Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd  Rd  Rr Z,N,V 1 COM Rd One’s Complement Rd  0xFF  Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd  0x00  Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd  Rd  (0xFF - K) Z,N,V 1 INC Rd Increment Rd  Rd + 1 Z,N,V 1 DEC Rd Decrement Rd  Rd  1 Z,N,V 1 1 TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V CLR Rd Clear Register Rd  Rd  Rd Z,N,V 1 SER Rd Set Register Rd  0xFF None 1 Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC  Z None 2 Relative Subroutine Call PC  PC + k + 1 None 3 ICALL Indirect Call to (Z) PC  Z None 3 RET Subroutine Return PC  STACK None 4 BRANCH INSTRUCTIONS RJMP k IJMP RCALL k Interrupt Return PC  STACK I 4 Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd  Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd  Rr  C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd  K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC  PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC  PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC  PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC  PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N  V= 1) then PC  PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1/2 RETI CPSE BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b)  1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)  0 None 2 LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Rd(0)  0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Rd(7)  0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 11 Mnemonics Operands Description Operation Flags ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V #Clocks 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s)  1 SREG(s) 1 BCLR s Flag Clear SREG(s)  0 SREG(s) 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV Clear Twos Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set Half Carry Flag in SREG H1 H 1 CLH Clear Half Carry Flag in SREG H0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd  Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd  Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd  K None 1 LD Rd, X Load Indirect Rd  (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd  (X), X  X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X  X - 1, Rd  (X) None 2 2 LD Rd, Y Load Indirect Rd  (Y) None LD Rd, Y+ Load Indirect and Post-Inc. Rd  (Y), Y  Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y  Y - 1, Rd  (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd  (Y + q) None 2 LD Rd, Z Load Indirect Rd  (Z) None 2 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd  (Z), Z  Z+1 None LD Rd, -Z Load Indirect and Pre-Dec. Z  Z - 1, Rd  (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd  (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X  X + 1 None 2 2 ST - X, Rr Store Indirect and Pre-Dec. X  X - 1, (X)  Rr None ST Y, Rr Store Indirect (Y)  Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y)  Rr, Y  Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y  Y - 1, (Y)  Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q)  Rr None 2 ST Z, Rr Store Indirect (Z)  Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z)  Rr, Z  Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z  Z - 1, (Z)  Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2 STS k, Rr LPM Store Direct to SRAM (k)  Rr None 2 Load Program Memory R0  (Z) None 3 3 LPM Rd, Z Load Program Memory Rd  (Z) None LPM Rd, Z+ Load Program Memory and Post-Inc Rd  (Z), Z  Z+1 None 3 Store Program Memory (Z)  R1:R0 None 1 SPM IN Rd, P In Port Rd  P None OUT P, Rr Out Port P  Rr None 1 PUSH Rr Push Register on Stack STACK  Rr None 2 POP Rd Pop Register from Stack Rd  STACK None 2 None 1 MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 12 6. Ordering Information 6.1 ATtiny441 Speed Supply Voltage Temperature Range Package(1) Ordering Code ATtiny441-SSU 14S1 ATtiny441-SSUR 16 MHz 1.7 – 5.5V Industrial (-40C to +85C)(2) ATtiny441-MU 20M1 ATtiny441-MUR ATtiny441-MMH 20M2 ATtiny441-MMHR Notes: 1. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Package Type 14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (QFN/MLF) 20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN) ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 13 6.2 ATtiny841 Speed Supply Voltage Temperature Range Package(1) Ordering Code ATtiny841-SSU 14S1 ATtiny841-SSUR 16 MHz 1.7 – 5.5V Industrial (-40C to +85C)(2) ATtiny841-MU 20M1 ATtiny841-MUR ATtiny841-MMH 20M2 ATtiny841-MMHR Notes: 1. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Package Type 14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (QFN/MLF) 20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN) ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 14 7. Packaging Information 7.1 14S1 1 E H E N L Top View End View e COMMON DIMENSIONS (Unit of Measure = mm/inches) b SYMBOL A1 A D Side View NOM MAX NOTE A 1.35/0.0532 – 1.75/0.0688 A1 0.1/.0040 – 0.25/0.0098 b 0.33/0.0130 – 0.5/0.0200 5 D 8.55/0.3367 – 8.74/0.3444 2 E 3.8/0.1497 – 3.99/0.1574 3 H 5.8/0.2284 – 6.19/0.2440 L 0.41/0.0160 – 1.27/0.0500 e Notes: MIN 4 1.27/0.050 BSC 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. L is the length of the terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2/5/02 TITLE R 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14S1 ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 REV. A 15 7.2 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.55 12/02/2014 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 REV. B 16 7.3 20M2 D C y Pin 1 ID E SIDE VIEW TOP VIEW A1 A D2 16 17 18 19 20 COMMON DIMENSIONS (Unit of Measure = mm) C0.18 (8X) 15 Pin #1 Chamfer (C 0.3) 14 2 e E2 13 MIN NOM MAX A 0.75 0.80 0.85 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 SYMBOL 1 3 C 12 4 11 5 D b 10 9 8 7 6 K L BOTTOM VIEW 0.3 Ref (4x) NOTE 0.152 2.90 3.00 3.10 D2 1.40 1.55 1.70 E 2.90 3.00 3.10 E2 1.40 1.55 1.70 e – 0.45 – L 0.35 0.40 0.45 K 0.20 – – y 0.00 – 0.08 10/24/08 Package Drawing Contact: packagedrawings@atmel.com GPC TITLE 20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, ZFC 1.55 x 1.55 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) DRAWING NO. REV. 20M2 B ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 17 8. Errata 8.1 ATtiny441 8.1.1 Rev. D No known erratas. 8.1.2 Rev. C Not sampled 8.1.3 Rev. B Not sampled. 8.1.4 Rev. A Not sampled 8.2 ATtiny841 8.2.1 Rev. C No known erratas. 8.2.2 Rev. B Issue: Non-volatile Memories Should Not Be Written at High Temperatures And Low Voltages Reliability issues have been detected when Flash, EEPROM or Fuse Bytes are programmed at voltages below 3V AND temperatures above 55°C. Workaround: 8.2.3 Do not write to Flash, EEPROM or Fuse bytes when supply voltage is below 3V AND device temperature is above 55°C. Rev. A Issue: Non-volatile Memories Should Not Be Written at High Temperatures And Low Voltages Reliability issues have been detected when Flash, EEPROM or Fuse Bytes are programmed at voltages below 3V AND temperatures above 55C. Workaround: Do not write to Flash, EEPROM or Fuse bytes when supply voltage is below 3V AND device temperature is above 55C. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 18 9. Datasheet Revision History Doc. Rev. Date Comments 8495A 09/2012 Initial revision 8495B 12/2012 Updated Figure 1-1 on page 2, Figure 1-2 on page 2, and REMAP register on pages 159, 186 and 7. Added ATtiny241. 8495C 03/2013 Updated “Ordering Information” : All -SU and SUR updated to -SSU and -SSUR. 8495D 07/2013 Removed references to ATtiny241 which will not be offered. 8495E 08/2013 Updated “Device Signature Imprint Table” on page 220. 8495F 10/2013 Added Typical Characterization plots. 8495G 01/2014 System and Reset Characteristics: Updated min and max limits of Internal bandgap voltage (VBG) in: Section 25.1.5 on page 240 Section 25.2.5 on page 249 8495H 05/2014 Updated WDT code example: RSTFLR register replaced with MCUSR. ATtiny441/841 [SUMMARY DATASHEET] 8495HS–AVR–05/2014 19 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2014 Atmel Corporation. All rights reserved. / Rev.: 8495HS–AVR–05/2014 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 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