Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
– Data retention: 20 years at 85°C / 100 years at 25C
– Programming Lock for Self-Programming Flash Program & EEPROM Data Security
Peripheral Features
– 8/16-bit Timer/Counter with Prescaler
– 8/10-bit High Speed Timer/Counter with Separate Prescaler
• 3 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– 10-bit ADC
• 11 Single-Ended Channels
• 16 Differential ADC Channel Pairs
• 15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator
– Universal Serial Interface with Start Condition Detector
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– On-chip Temperature Sensor
I/O and Packages
– 16 Programmable I/O Lines
– Available in 20-pin PDIP, 20-pin SOIC and 32-pad MLF
Operating Voltage:
– 1.8 – 5.5V for ATtiny261V/461V/861V
– 2.7 – 5.5V for ATtiny261/461/861
Speed Grade:
– ATtiny261V/461V/861V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
– ATtiny261/461/861: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode (1 MHz System Clock): 300 µA @ 1.8V
– Power-Down Mode: 0.1 µA at 1.8V
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny261/V*
ATtiny461/V
ATtiny861/V
*Mature
2588F–AVR–06/2013
1. Pin Configurations
Figure 1-1.
Pinout ATtiny261/461/861 and ATtiny261V/461V/861V
PDIP/SOIC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
AVCC
PA4 (ADC3/ICP0/PCINT4)
PA5 (ADC4/AIN2/PCINT5)
PA6 (ADC5/AIN0/PCINT6)
PA7 (ADC6/AIN1/PCINT7)
32
31
30
29
28
27
26
25
PB2 (SCK/USCK/SCL/OC1B/PCINT10)
PB1 (MISO/DO/OC1A/PCINT9)
PB0 (MOSI/DI/SDA/OC1A/PCINT8)
NC
NC
NC
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
(MOSI/DI/SDA/OC1A/PCINT8) PB0
(MISO/DO/OC1A/PCINT9) PB1
(SCK/USCK/SCL/OC1B/PCINT10) PB2
(OC1B/PCINT11) PB3
VCC
GND
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
1
2
3
4
5
6
7
8
QFN/MLF
24
23
22
21
20
19
18
17
NC
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
AGND
NC
NC
AVCC
PA4 (ADC3/ICP0/PCINT4)
NC
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
NC
(ADC6/AIN1/PCINT7) PA7
(ADC5/AIN0/PCINT6) PA6
(ADC4/AIN2/PCINT5) PA5
NC
9
10
11
12
13
14
15
16
NC
(OC1B/PCINT11) PB3
NC
VCC
GND
NC
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
Note:
2
To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board.
ATtiny261/461/861
2588F–AVR–06/2013
ATtiny261/461/861
1.1
1.1.1
Pin Descriptions
VCC
Supply voltage.
1.1.2
GND
Ground.
1.1.3
AVCC
Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC),
the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port
A. It should be externally connected to VCC, even if some peripherals such as the ADC are not
used. If the ADC is used AVCC should be connected to VCC through a low-pass filter.
1.1.4
AGND
Analog ground.
1.1.5
Port A (PA7:PA0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port A also serves the functions of various special features of the device, as listed on page 63.
1.1.6
Port B (PB7:PB0)
An 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
Output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, port pins that are externally pulled low will source current if pull-up resistors have
been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port B also serves the functions of various special features of the device, as listed on page 66.
1.1.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 19-4 on page 190. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
2588F–AVR–06/2013
2. Overview
ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Block Diagram
Block Diagram
GND
Figure 2-1.
VCC
2.1
Watchdog
Timer
Watchdog
Oscillator
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
debugWIRE
Flash
SRAM
PROGRAM
LOGIC
CPU
EEPROM
AVCC
AGND
AREF
Timer/Counter1
A/D Conv.
USI
Analog Comp.
Internal
Bandgap
DATABUS
Timer/Counter0
3
PORT B (8)
11
PORT A (8)
RESET
XTAL[1..2]
PB[0..7]
PA[0..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
4
ATtiny261/461/861
2588F–AVR–06/2013
ATtiny261/461/861
The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O lines, 32
general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8-bit high
speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an 11-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four software
selectable power saving modes. Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Powerdown mode saves the register contents, disabling all chip functions until the next Interrupt or
Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny261/461/861 AVR is supported by a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation
kits.
5
2588F–AVR–06/2013
3. About
3.1
Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
3.4
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology.
6
ATtiny261/461/861
2588F–AVR–06/2013
ATtiny261/461/861
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
4.1
Architectural Overview
Figure 4-1.
Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
7
2588F–AVR–06/2013
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
directly addressing the whole address space. Most AVR instructions have a single 16-bit word
format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices
only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
4.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
4.3
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
8
ATtiny261/461/861
2588F–AVR–06/2013
ATtiny261/461/861
The Status Register is neither automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt. This must be handled by software.
4.3.1
SREG – AVR Status Register
Bit
7
6
5
4
3
2
1
0
0x3F (0x5F)
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
9
2588F–AVR–06/2013
4.4
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2.
AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
R27
0x1B
X-register Low Byte
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
4.4.1
The X-register, Y-register, and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3.
Figure 4-3.
The X-, Y-, and Z-registers
15
X-register
7
R27 (0x1B)
10
XH
XL
0
7
0
0
R26 (0x1A)
ATtiny261/461/861
2588F–AVR–06/2013
ATtiny261/461/861
15
Y-register
YH
YL
7
0
R29 (0x1D)
Z-register
0
7
0
R28 (0x1C)
15
ZH
7
0
ZL
7
R31 (0x1F)
0
0
R30 (0x1E)
In different addressing modes these address registers function as automatic increment and
automatic decrement (see the instruction set reference for details).
4.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present
4.5.1
SPH and SPL — Stack Pointer Register
Bit
15
14
13
12
11
10
9
8
0x3E (0x5E)
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
0x3D (0x5D)
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
Read/Write
Initial Value
4.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
11
2588F–AVR–06/2013
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination register.
Figure 4-5.
Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
4.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 50. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
12
ATtiny261/461/861
2588F–AVR–06/2013
ATtiny261/461/861
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG
cli
; store SREG value
; disable interrupts during timed sequence
sbi EECR, EEMPE
; start EEPROM write
sbi EECR, EEPE
out SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1