ATUC128L3U-AUR

Feature Summary • • • • • • • • • • • • • • • 32-bit load/store RISC architecture Up to 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter, and Link Register reside in register file Fully orthogonal instruction set Pipelined architecture allows one instruction per clock cycle for most instructions Byte, half-word, word and double word memory access Fast interrupts and multiple interrupt priority levels Optional branch prediction for minimum delay branches Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density Optional DSP extention with saturated arithmetic, and a wide variety of multiply instructions Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors Architectural support for efficient On-Chip Debug solutions Optional MPU or MMU allows for advanced operating systems FlashVault™ support through Secure State for executing trusted code alongside nontrusted code on the same CPU AVR32 Architecture Document 32000D–04/2011 1. Introduction AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow for a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. 1.1 The AVR family The AVR family was launched by Atmel in 1996 and has had remarkable success in the 8-and 16-bit flash microcontroller market. AVR32 is complements the current AVR microcontrollers. Through the AVR32 family, the AVR is extended into a new range of higher performance applications that is currently served by 32- and 64-bit processors To truly exploit the power of a 32-bit architecture, the new AVR32 architecture is not binary compatible with earlier AVR architectures. In order to achieve high code density, the instruction format is flexible providing both compact instructions with 16 bits length and extended 32-bit instructions. While the instruction length is only 16 bits for most instructions, powerful 32-bit instructions are implemented to further increase performance. Compact and extended instructions can be freely mixed in the instruction stream. 1.2 The AVR32 Microprocessor Architecture The AVR32 is a new innovative microprocessor architecture. It is a fully synchronous synthesisable RTL design with industry standard interfaces, ensuring easy integration into SoC designs with legacy intellectual property (IP). Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class of microprocessor architectures. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and half-word data types without penalty in code size and performance. Memory load and store operations are provided for byte, half-word, word and double word data with automatic sign- or zero extension of half-word and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution: • Load/store to an address specified by a pointer register • Load/store to an address specified by a pointer register with postincrement 2 AVR32 32000D–04/2011 AVR32 • Load/store to an address specified by a pointer register with predecrement • Load/store to an address specified by a pointer register with displacement • Load/store to an address specified by a small immediate (direct addressing within a small page) • Load/store to an address specified by a pointer register and an index register. The register file is organized as 16 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, one register is designed to hold return values from function calls and is used implicitly by some instructions. The AVR32 core defines several micro architectures in order to capture the entire range of applications. The microarchitectures are named AVR32A, AVR32B and so on. Different microarchitectures are suited to different end applications, allowing the designer to select a microarchitecture with the optimum set of parameters for a specific application. 1.2.1 Exceptions and Interrupts The AVR32 incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. Each priority class has dedicated registers to keep the return address and status register thereby removing the need to perform time-consuming memory operations to save this information. There are four levels of external interrupt requests, all executing in their own context. The contexts can provide a number of dedicated registers for the interrupts to use directly ensuring low latency. High priority interrupts may have a larger number of shadow registers available than low priority interrupts. An interrupt controller does the priority handling of the external interrupts and provides the prioritized interrupt vector to the processor core. 1.2.2 Java Support Java hardware acceleration is available as an option, in the form of a Java Card or Java Virtual Machine hardware implementation. 1.2.3 FlashVault Revision 3 of the AVR32 architecture introduced a new CPU state called Secure State. This state is instrumental in the new security technology named FlashVault. This innovation allows the on-chip flash and other memories to be partially programmed and locked, creating a safe onchip storage for secret code and valuable software intellectual property. Code stored in the FlashVault will execute as normal, but reading, copying or debugging the code is not possible. This allows a device with FlashVault code protection to carry a piece of valuable software such as a math library or an encryption algorithm from a trusted location to a potentially untrustworthy partner where the rest of the source code can be developed, debugged and programmed. 3 32000D–04/2011 1.3 Microarchitectures The AVR32 architecture defines different microarchitectures. This enables implementations that are tailored to specific needs and applications. The microarchitectures provide different performance levels at the expense of area and power consumption. The following microarchitectures are defined: 1.3.1 AVR32A The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 1.3.2 AVR32B The AVR32B microarchitecture is targeted at applications where interrupt latency is important. The AVR32B therefore implements dedicated registers to hold the status register and return address for interrupts, exceptions and supervisor calls. This information does not need to be written to the stack, and latency is therefore reduced. Additionally, AVR32B allows hardware shadowing of the registers in the register file. The INT0 to INT3 contexts may have dedicated versions of the registers in the register file, allowing the interrupt routine to start executing immediately. The scall, rete and rets instructions use the dedicated status register and return address registers in their operation. No stack accesses are performed. 4 AVR32 32000D–04/2011 AVR32 2. Programming Model This chapter describes the programming model and the set of registers accessible to the user. 2.1 Data Formats The AVR32 processor supports the data types shown in Table 2-1 on page 5: Table 2-1. Overview of execution modes, their priorities and privilege levels. Type Data Width Byte 8 bits Halfword 16 bits Word 32 bits Double Word 64 bits When any of these types are described as unsigned, the N bit data value represents a non-negative integer in the range 0 to + 2N-1. When any of these types are described as signed, the N bit data value represents an integer in the range of -2N-1 to +2N-1-1, using two’s complement format. Some instructions operate on fractional numbers. For these numbers, the data value represents a fraction in the range of -1 to +1-2-(N-1), using two’s complement format. 2.2 Data Organization Data is usually stored in a big-endian way, see Figure 2-1 on page 5. This means that when multi-byte data is stored in memory, the most significant byte is stored at the lowest address. All instructions are interpreted as being big-endian. However, in order to support data transfers that are little-endian, special endian-translating load and store instructions are defined. The register file can hold data of different formats. Both byte, halfword (16-bit) and word (32-bit) formats can be represented, and byte and halfword formats are supported in both unsigned and signed 2’s complement formats. Some instructions also use doubleword operands. Doubleword data are placed in two consecutive registers. The most significant word is in the uppermost register. Valid register pairs are R1:R0, R3:R2, R5:R4, R7:R6, R9:R8, R11:R10 and R13:R12. Load and store operations that transfer bytes or halfwords, automatically zero-extends or signextends the bytes or half-words as they are loaded. Figure 2-1. Data representation in the register file 31 8 7 S SSSSSSSSSSSSSSSSSSSSSSSS 31 0 8 7 000000000000000000000000 31 16 SSSSSSSSSSSSSSSS 31 16 S ig n e x te n d e d b y te B y te 0 U n s ig n e d b y te B y te 15 S 0 S ig n e x te n d e d h a lfw o rd H a lfw o rd 15 0 0000000000000000 U n s ig n e d h a lfw o rd H a lfw o rd 31 0 to p upper lo w e r b o tto m W o rd 5 32000D–04/2011 AVR32 can access data of size byte, halfword, word and doubleword using dedicated instructions. The memory system can support unaligned accesses for selected load/store instructions in some implementations. Any other unaligned access will cause an address exception. For performance reasons, the user should make sure that the stack always is word aligned. This means that only word instructions can be used to access the stack. When manipulating the stack pointer, the user has to ensure that the result is word aligned before trying to load and store data on the stack. Failing to do so will result in performance penalties. Code will execute correctly if the stack is unaligned but with a significant performance penalty. 2.3 Instruction Organization The AVR32 instruction set has both compact and extended instructions. Compact instructions denotes the instructions which have a length of 16 bits while extended instructions have a length of 32 bits. All instructions must be placed on halfword boundaries, see Table 2-2 on page 6. Extended instructions can be both aligned and unaligned to halfword boundaries. In normal instruction flow, the instruction buffer will always contain enough entries to ensure that compact, aligned extended and unaligned extended instructions can be issued in a single cycle. Change-of-flow operations such as branches, jumps, calls and returns may in some implementations require the instruction buffer to be flushed. The user should consult the Technical Reference Manual for the specific implementation in order to determine how alignment of the branch target address affects performance. Table 2-2. Instructions are stored in memory in a big endian fashion and must be aligned on half word boundaries Word Address 6 I J N+24 H1 H2 N+20 F2 G N+16 E2 F1 N+12 D E1 N+8 C1 C2 N+4 A B N Byte Address 0 1 2 3 Byte Address 0 1 2 3 AVR32 32000D–04/2011 AVR32 2.4 2.4.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 2-3 on page 7. Table 2-3. Overview of execution modes, their priorities and privilege levels. Priority Mode Security Description 1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode 2 Exception Privileged Execute exceptions 3 Interrupt 3 Privileged General purpose interrupt mode 4 Interrupt 2 Privileged General purpose interrupt mode 5 Interrupt 1 Privileged General purpose interrupt mode 6 Interrupt 0 Privileged General purpose interrupt mode N/A Supervisor Privileged Runs supervisor calls N/A Application Unprivileged Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 2.4.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the Technical Reference Manual. Debug state is exited by the retd instruction. 2.4.3 Java State Some versions of the AVR32 processor core comes with a Java Extension Module (JEM). The processor can be set in a Java State where normal RISC operations are suspended. The Java state is described in chapter 3. 2.4.4 Secure State The secure state added in the AVR32 Architecture revision 3 allows executing secure or trusted software in alongside nonsecure or untrusted software on the same processor. Hardware mech- 7 32000D–04/2011 anisms are in place to make sure the nonsecure software can not read or modify instruction or data belonging to the secure software. The secure state is described in chapter 4. 2.5 Entry and Exit Mechanism Table 2-4 on page 8 illustrates how the different states and modes are entered and exited. Table 2-4. 2.6 Entry and exit from states, modes and functions Entry method Exit method Non-maskable Interrupt Signal on NMI line rete Exception Mode Internal error signal generated rete Interrupt3 Signal on INT3 line rete Interrupt2 Signal on INT2 line rete Interrupt1 Signal on INT1 line rete Interrupt0 Signal on INT0 line rete Supervisor Mode scall instruction rets Application Mode Returned to from any of the above modes Can not be exited from Subprogram Function call ret{cond}, ldm, popm, mov PC, LR Secure state sscall retss Register File Each of AVR32’s normal operation modes described in Section 2.4.1 “Normal RISC State” on page 7 has a dedicated context. Note that the Stack Pointer (SP), Program Counter (PC) and the Link Register (LR) are mapped into the register file, making the effective register count for each context 13 general purpose registers. The mapping of SP, PC and LR allows ordinary instructions, like additions or subtractions, to use these registers. This results in efficient addressing of memory. Register R12 is designed to hold return values from function calls, and the conditional return with move and test instruction use this register as an implicit return value operand. The load multiple and pop multiple instructions have the same functionality, which enables them to be used as return instructions. The AVR32 core’s orthogonal instruction set allows all registers in the register file to be used as pointers. 2.6.1 Register file in AVR32A The AVR32A is targeted for cost-sensitive applications. Therefore, no hardware-shadowing of registers is provided, see Figure 2-2 on page 9. All data that must be saved between execution states are placed on the system stack, not in dedicated registers as done in AVR32B. A shadowed stack pointer is still provided for the privileged modes, facilitating a dedicated system stack. When an exception occurs in an AVR32A-compliant implementation, the status register and return address are pushed by hardware onto the system stack. When an INT0, INT1, INT2 or INT3 occurs, the status register, return address, R8-R12 and LR are pushed on the system stack. The corresponding registers are popped from stack by the rete instruction. The scall and rets instructions also use the system stack to store the return address and status register. 8 AVR32 32000D–04/2011 AVR32 Figure 2-2. 2.6.2 Register File in AVR32A Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Bit 31 Bit 0 Exception NMI Bit 31 Bit 31 Bit 0 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SR SR SR SR SR SR SR Register File in AVR32B The AVR32B allows separate register files for the interrupt and exception modes, see Figure 2-3 on page 9. These modes have a number of implementation defined shadowed registers in order to speed up interrupt handling. The shadowed registers are automatically mapped in depending on the current execution mode. All contexts, except Application, have a dedicated Return Status Register (RSR) and Return Address Register (RAR). The RSR registers are used for storing the Status Register value in the context to return to. The RAR registers are used for storing the address in the context to return to. The RSR and RAR registers eliminates the need to temporarily store the Status Register and return address to stack when entering a new context. Figure 2-3. Register File in AVR32B Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 Bit 31 INT2 Bit 0 Bit 31 INT3 Bit 0 Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR / LR_INT0 SP_SYS PC LR / LR_INT1 SP_SYS PC LR / LR_INT2 SP_SYS PC LR / LR_INT3 SP_SYS banked registers banked registers banked registers banked registers (implementation defined) (implementation defined) (implementation defined) (implementation defined) SR SR RSR_SUP RAR_SUP SR RSR_INT0 RAR_INT0 SR RSR_INT1 RAR_INT1 SR RSR_INT2 RAR_INT2 SR RSR_INT3 RAR_INT3 Exception NMI Bit 31 Bit 31 Bit 0 Bit 0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_EX RAR_EX SR RSR_NMI RAR_NMI The register file is designed with an implementation specific part and an architectural defined part. Depending on the implementation, each of the interrupt modes can have different configu- 9 32000D–04/2011 rations of shadowed registers. This allows for maximum flexibility in targeting the processor for different application, see Figure 2-4 on page 10. Figure 2-4. A typical AVR32B register file implementation Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 Bit 31 INT2 Bit 0 Bit 31 INT3 Bit 0 Bit 31 Bit 0 Exception NMI Bit 31 Bit 31 Bit 0 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR_INT2 SP_SYS R12_INT2 R11_INT2 R10_INT2 R9_INT2 R8_INT2 R7 R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR_INT3 SP_SYS R12_INT3 R11_INT3 R10_INT3 R9_INT3 R8_INT3 R7_INT3 INT0PC R6_INT3 INT1PC R5_INT3 FINTPC R4_INT3 SMPC R3_INT3 R2_INT3 R1_INT3 R0_INT3 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SR RSR_SUP RAR_SUP SR RSR_INT0 RAR_INT0 SR RSR_INT1 RAR_INT1 SR RSR_INT2 RAR_INT2 SR RSR_INT3 RAR_INT3 SR RSR_EX RAR_EX SR RSR_NMI RAR_NMI Three different shadowing schemes are offered, small, half and full, ranging from no general registers shadowed to all general registers shadowed, see Figure 2-5 on page 10. Figure 2-5. AVR32 offers three different models for shadowed registers. Small Bit 31 Half Bit 0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 2.7 Bit 31 Full Bit 0 PC LR_INTx SP_SYS R12_INTx R11_INTx R10_INTx R9_INTx R8_INTx R7 R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 Bit 31 Bit 0 PC LR_INTx SP_SYS R12_INTx R11_INTx R10_INTx R9_INTx R8_INTx R7_INTx INT0PC R6_INTx INT1PC R5_INTx FINTPC R4_INTx SMPC R3_INTx R2_INTx R1_INTx R0_INTx The Stack Pointer Since the Stack Pointer (SP) is located in the register file, it can be addressed as an ordinary register. This simplifies allocation and access of local variables and parameters. The Stack Pointer is also used implicitly by several instructions. The system modes have a shadowed stack pointer different from the application mode stack pointer. This allows having a separate system stack. 10 AVR32 32000D–04/2011 AVR32 2.8 The Program Counter The Program Counter (PC) contains the address of the instruction being executed. The memory space is byte addressed. With the exception of Java state, the instruction size is a multiple of 2 bytes and the LSB of the Program Counter is fixed to zero. The PC is automatically incremented in normal program flow, depending on the size of the current instruction. The PC is mapped into the register file and it can be used as a source or destination operand in all instructions using register operands. This includes arithmetical or logical instructions and load/store instructions. Instructions using PC as destination register are treated the same way as jump instructions. This implies that the pipeline is flushed, and execution resumed at the address specified by the new PC value. 2.9 The Link Register The general purpose register R14 is used as a Link Register in all modes. The Link Register holds subroutine return addresses. When a subroutine call is performed by a variant of the call instruction, LR is set to hold the subroutine return address. The subroutine return is performed by copying LR back to the program counter, either explicitly by a mov instruction, by using a ldm or popm instruction or a ret instruction. The Link Register R14 can be used as a general-purpose register at all other times. 2.10 The Status Register The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 2-6 on page 11 and Figure 2-7 on page 12. The lower halfword contains the C, Z, N, V and Q flags, while the upper halfword contains information about the mode and state the processor executes in. The upper halfword can only be accessed from a privileged mode. Figure 2-6. The Status Register high halfword B it 3 1 B it 1 6 SS LC 1 H J DM D - M2 M1 M0 EM I3 M I2 FE M I1 M I0 M GM 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 B it n a m e In itia l v a lu e G lo b a l In te rru p t M a s k In te r ru p t L e v e l 0 M a s k In te r ru p t L e v e l 1 M a s k In te r ru p t L e v e l 2 M a s k In te r ru p t L e v e l 3 M a s k E x c e p tio n M a s k M o d e B it 0 M o d e B it 1 M o d e B it 2 R e s e rv e d D e b u g S ta te D e b u g S ta te M a s k J a v a S ta te J a v a H a n d le R e s e rv e d S e c u re S ta te 11 32000D–04/2011 Figure 2-7. The Status Register low halfword B it 1 5 B it 0 R T - - - - - - - - L Q V N Z C B it n a m e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 In itia l v a lu e C a rry Z e ro S ig n O v e r f lo w S a tu r a tio n Lock R e s e rv e d S c r a tc h R e g is te r R e m a p E n a b le SS - Secure State This bit is indicates if the processor is executing in the secure state. For more details, see chapter 4. The bit is initialized in an IMPLEMENTATION DEFINED way at reset. H - Java Handle This bit is included to support different heap types in the Java Virtual Machine. For more details, see chapter 3. The bit is cleared at reset. J - Java State The processor is in Java state when this bit is set. The incoming instruction stream will be decoded as a stream of Java bytecodes, not RISC opcodes. The bit is cleared at reset. This bit should not be modified by the user as undefined behaviour may result. DM - Debug State Mask If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset, and can both be read and written by software. D - Debug State The processor is in debug state when this bit is set. The bit is cleared at reset and should only be modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behaviour may result if the user tries to modify this bit manually. M2, M1, M0 - Execution Mode These bits show the active execution mode. The settings for the different modes are shown in Table 2-5 on page 13. M2 and M1 are cleared by reset while M0 is set so that the processor is in supervisor mode after reset. These bits are modified by hardware, or execution of certain instructions like scall, rets and rete. Undefined behaviour may result if the user tries to modify these bits manually. 12 AVR32 32000D–04/2011 AVR32 Table 2-5. Mode bit settings M2 M1 M0 Mode 1 1 1 Non Maskable Interrupt 1 1 0 Exception 1 0 1 Interrupt level 3 1 0 0 Interrupt level 2 0 1 1 Interrupt level 1 0 1 0 Interrupt level 0 0 0 1 Supervisor 0 0 0 Application EM - Exception mask When this bit is set, exceptions are masked. Exceptions are enabled otherwise. The bit is automatically set when exception processing is initiated or Debug Mode is entered. Software may clear this bit after performing the necessary measures if nested exceptions should be supported. This bit is set at reset. I3M - Interrupt level 3 mask When this bit is set, level 3 interrupts are masked. If I3M and GM are cleared, INT3 interrupts are enabled. The bit is automatically set when INT3 processing is initiated. Software may clear this bit after performing the necessary measures if nested INT3s should be supported. This bit is cleared at reset. I2M - Interrupt level 2 mask When this bit is set, level 2 interrupts are masked. If I2M and GM are cleared, INT2 interrupts are enabled. The bit is automatically set when INT3 or INT2 processing is initiated. Software may clear this bit after performing the necessary measures if nested INT2s should be supported. This bit is cleared at reset. I1M - Interrupt level 1 mask When this bit is set, level 1 interrupts are masked. If I1M and GM are cleared, INT1 interrupts are enabled. The bit is automatically set when INT3, INT2 or INT1 processing is initiated. Software may clear this bit after performing the necessary measures if nested INT1s should be supported. This bit is cleared at reset. I0M - Interrupt level 0 mask When this bit is set, level 0 interrupts are masked. If I0M and GM are cleared, INT0 interrupts are enabled. The bit is automatically set when INT3, INT2, INT1 or INT0 processing is initiated. Software may clear this bit after performing the necessary measures if nested INT0s should be supported. This bit is cleared at reset. GM - Global Interrupt Mask When this bit is set, all interrupts are disabled. This bit overrides I0M, I1M, I2M and I3M. The bit is automatically set when exception processing is initiated, Debug Mode is entered, or a Java trap is taken. This bit is automatically cleared when returning from a Java trap. This bit is set after reset. 13 32000D–04/2011 R - Java register remap When this bit is set, the addresses of the registers in the register file is dynamically changed. This allows efficient use of the register file registers as a stack. For more details, see chapter 3.. The R bit is cleared at reset. Undefined behaviour may result if this bit is modified by the user. T - Scratch bit This bit is not set or cleared implicit by any instruction and the programmer can therefore use this bit as a custom flag to for example signal events in the program. This bit is cleared at reset. L - Lock flag Used by the conditional store instruction. Used to support atomical memory access. Automatically cleared by rete. This bit is cleared after reset. Q - Saturation flag The saturation flag indicates that a saturating arithmetic operation overflowed. The flag is sticky and once set it has to be manually cleared by a csrf instruction after the desired action has been taken. See the Instruction set description for details. V - Overflow flag The overflow flag indicates that an arithmetic operation overflowed. See the Instruction set description for details. N - Negative flag The negative flag is modified by arithmetical and logical operations. See the Instruction set description for details. Z - Zero flag The zero flag indicates a zero result after an arithmetic or logic operation. See the Instruction set description for details. C - Carry flag The carry flag indicates a carry after an arithmetic or logic operation. See the Instruction set description for details. 2.11 System registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions, see Table 2-7 on page 15. The number of physical locations is IMPLEMENTATION DEFINED, but a maximum of 256 locations can be addressed with the dedicated instructions. Some of the System Registers are altered automatically by hardware. The reset value of the System Registers are IMPLEMENTATION DEFINED. 14 AVR32 32000D–04/2011 AVR32 The Compliance column describes if the register is Required, Optional or Unused in AVR32A and AVR32B, see Table 2-6 on page 15 for legend. Table 2-6. Table 2-7. Legend for the Compliance column Abbreviation Meaning RA Required in AVR32A OA Optional in AVR32A UA Unused in AVR32A RB Required in AVR32B OB Optional in AVR32B UB Unused in AVR32B System Registers Reg # Address Name Function Compliance 0 0 SR Status Register RA RB 1 4 EVBA Exception Vector Base Address RA RB 2 8 ACBA Application Call Base Address RA RB 3 12 CPUCR CPU Control Register RA RB 4 16 ECR Exception Cause Register OA OB 5 20 RSR_SUP Return Status Register for Supervisor context UA RB 6 24 RSR_INT0 Return Status Register for INT 0 context UA RB 7 28 RSR_INT1 Return Status Register for INT 1 context UA RB 8 32 RSR_INT2 Return Status Register for INT 2 context UA RB 9 36 RSR_INT3 Return Status Register for INT 3 context UA RB 10 40 RSR_EX Return Status Register for Exception context UA RB 11 44 RSR_NMI Return Status Register for NMI context UA RB 12 48 RSR_DBG Return Status Register for Debug Mode OA OB 13 52 RAR_SUP Return Address Register for Supervisor context UA RB 14 56 RAR_INT0 Return Address Register for INT 0 context UA RB 15 60 RAR_INT1 Return Address Register for INT 1 context UA RB 16 64 RAR_INT2 Return Address Register for INT 2 context UA RB 17 68 RAR_INT3 Return Address Register for INT 3 context UA RB 18 72 RAR_EX Return Address Register for Exception context UA RB 19 76 RAR_NMI Return Address Register for NMI context UA RB 20 80 RAR_DBG Return Address Register for Debug Mode OA OB 21 84 JECR Java Exception Cause Register OA OB 22 88 JOSP Java Operand Stack Pointer OA OB 23 92 JAVA_LV0 Java Local Variable 0 OA OB 15 32000D–04/2011 Table 2-7. System Registers (Continued) Reg # Address Name Function Compliance 24 96 JAVA_LV1 Java Local Variable 1 OA OB 25 100 JAVA_LV2 Java Local Variable 2 OA OB 26 104 JAVA_LV3 Java Local Variable 3 OA OB 27 108 JAVA_LV4 Java Local Variable 4 OA OB 28 112 JAVA_LV5 Java Local Variable 5 OA OB 29 116 JAVA_LV6 Java Local Variable 6 OA OB 30 120 JAVA_LV7 Java Local Variable 7 OA OB 31 124 JTBA Java Trap Base Address OA OB 32 128 JBCR Java Write Barrier Control Register OA OB 33-63 132-252 Reserved Reserved for future use - - 64 256 CONFIG0 Configuration register 0 RA RB 65 260 CONFIG1 Configuration register 1 RA RB 66 264 COUNT Cycle Counter register RA RB 67 268 COMPARE Compare register RA RB 68 272 TLBEHI MMU TLB Entry High OA OB 69 276 TLBELO MMU TLB Entry Low OA OB 70 280 PTBR MMU Page Table Base Register OA OB 71 284 TLBEAR MMU TLB Exception Address Register OA OB 72 288 MMUCR MMU Control Register OA OB 73 292 TLBARLO MMU TLB Accessed Register Low OA OB 74 296 TLBARHI MMU TLB Accessed Register High OA OB 75 300 PCCNT Performance Clock Counter OA OB 76 304 PCNT0 Performance Counter 0 OA OB 77 308 PCNT1 Performance Counter 1 OA OB 78 312 PCCR Performance Counter Control Register OA OB 79 316 BEAR Bus Error Address Register OA OB 80 320 MPUAR0 MPU Address Register region 0 OA OB 81 324 MPUAR1 MPU Address Register region 1 OA OB 82 328 MPUAR2 MPU Address Register region 2 OA OB 83 332 MPUAR3 MPU Address Register region 3 OA OB 84 336 MPUAR4 MPU Address Register region 4 OA OB 85 340 MPUAR5 MPU Address Register region 5 OA OB 86 344 MPUAR6 MPU Address Register region 6 OA OB 87 348 MPUAR7 MPU Address Register region 7 OA OB 88 352 MPUPSR0 MPU Privilege Select Register region 0 OA OB 89 356 MPUPSR1 MPU Privilege Select Register region 1 OA OB 16 AVR32 32000D–04/2011 AVR32 Table 2-7. System Registers (Continued) Reg # Address Name Function Compliance 90 360 MPUPSR2 MPU Privilege Select Register region 2 OA OB 91 364 MPUPSR3 MPU Privilege Select Register region 3 OA OB 92 368 MPUPSR4 MPU Privilege Select Register region 4 OA OB 93 372 MPUPSR5 MPU Privilege Select Register region 5 OA OB 94 376 MPUPSR6 MPU Privilege Select Register region 6 OA OB 95 380 MPUPSR7 MPU Privilege Select Register region 7 OA OB 96 384 MPUCRA MPU Cacheable Register A OA OB 97 388 MPUCRB MPU Cacheable Register B OA OB 98 392 MPUBRA MPU Bufferable Register A OA OB 99 396 MPUBRB MPU Bufferable Register B OA OB 100 400 MPUAPRA MPU Access Permission Register A OA OB 101 404 MPUAPRB MPU Access Permission Register B OA OB 102 408 MPUCR MPU Control Register OA OB 103 412 SS_STATUS Secure State Status Register OA OB 104 416 SS_ADRF Secure State Address Flash Register OA OB 105 420 SS_ADRR Secure State Address RAM Register OA OB 106 424 SS_ADR0 Secure State Address 0 Register OA OB 107 428 SS_ADR1 Secure State Address 1 Register OA OB 108 432 SS_SP_SYS Secure State Stack Pointer System Register OA OB 109 436 SS_SP_APP Secure State Stack Pointer Application Register OA OB 110 440 SS_RAR Secure State Return Address Register OA OB 111 444 SS_RSR Secure State Return Status Register OA OB 112-191 448-764 Reserved Reserved for future use - - 192-255 768-1020 IMPL IMPLEMENTATION DEFINED - - SR- Status Register The Status Register is mapped into the system register space. This allows it to be loaded into the register file to be modified, or to be stored to memory. The Status Register is described in detail in Section 2.10 “The Status Register” on page 11. EVBA - Exception Vector Base Address This register contains a pointer to the exception routines. All exception routines start at this address, or at a defined offset relative to the address. Special alignment requirements may apply for EVBA, depending on the implementation of the interrupt controller. Exceptions are described in detail in Section 8. “Event Processing” on page 63. ACBA - Application Call Base Address Pointer to the start of a table of function pointers. Subroutines can thereby be called by the compact acall instruction. This facilitates efficient reuse of code. Keeping this pointer as a register facilitates multiple function pointer tables. ACBA is a full 32 bit register, but the lowest two bits 17 32000D–04/2011 should be written to zero, making ACBA word aligned. Failing to do so may result in erroneous behaviour. CPUCR - CPU Control Register Register controlling the configuration and behaviour of the CPU. The behaviour of this register is IMPLEMENTATION DEFINED. An example of a typical control bit in the CPUCR is an enable bit for branch prediction. ECR - Exception Cause Register This register identifies the cause of the most recently executed exception. This information may be used to handle exceptions more efficiently in certain operating systems. The register is updated with a value equal to the EVBA offset of the exception, shifted 2 bit positions to the right. Only the 9 lowest bits of the EVBA offset are considered. As an example, an ITLB miss jumps to EVBA+0x50. The ECR will then be loaded with 0x50>>2 == 0x14. The ECR register is not loaded when an scall, Breakpoint or OCD Stop CPU exception is taken. Note that for interrupts, the offset is given by the autovector provided by the interrupt controller. The resulting ECR value may therefore overlap with an ECR value used by a regular exception. This can be avoided by choosing the autovector offsets so that no such overlaps occur. RSR_SUP, RSR_INT0, RSR_INT1, RSR_INT2, RSR_INT3, RSR_EX, RSR_NMI - Return Status Registers If a request for a mode change, for instance an interrupt request, is accepted when executing in a context C, the Status Register values in context C are automatically stored in the Return Status Register (RSR) associated with the interrupt context I. When the execution in the interrupt state I is finished and the rets / rete instruction is encountered, the RSR associated with I is copied to SR, and the execution continues in the original context C. RSR_DBG - Return Status Register for Debug Mode When Debug mode is entered, the status register contents of the original mode is automatically saved in this register. When the debug routine is finished, the retd instruction copies the contents of RSR_DBG into SR. RAR_SUP, RAR_INT0, RAR_INT1, RAR_INT2, RAR_INT3, RAR_EX, RAR_NMI - Return Address Registers If a request for a mode change, for instance an interrupt request, is accepted when executing in a context C, the re-entry address of context C is automatically stored in the Return Address Register (RAR) associated with the interrupt context I. When the execution in the interrupt state I is finished and the rets / rete instruction is encountered, a change-of-flow to the address in the RAR associated with I, and the execution continues in the original context C. The calculation of the re-entry addresses is described in Section 8. “Event Processing” on page 63. RAR_DBG - Return Address Register for Debug Mode When Debug mode is entered, the Program Counter contents of the original mode is automatically saved in this register. When the debug routine is finished, the retd instruction copies the contents of RAR_DBG into PC. JECR - Java Exception Cause Register This register contains information needed for Java traps, see AVR32 Java Technical Reference Manual for details. JOSP - Java Operand Stack Pointer This register holds the Java Operand Stack Pointer. The register is initialized to 0 at reset. 18 AVR32 32000D–04/2011 AVR32 JAVA_LVx - Java Local Variable Registers The Java Extension Module uses these registers to store local variables temporary. JTBA - Java Trap Base Address This register contains the base address to the program code for the trapped Java instructions. JBCR - Java Write Barrier Control Register This register is used by the garbage collector in the Java Virtual Machine. CONFIG0 / 1 - Configuration Register 0 / 1 Used to describe the processor, its configuration and capabilities. The contents and functionality of these registers is described in detail in Section 2.11.1 “Configuration Registers” on page 21. COUNT - Cycle Counter Register The COUNT register increments once every clock cycle, regardless of pipeline stalls and flushes. The COUNT register can both be read and written. The count register can be used together with the COMPARE register to create a timer with interrupt functionality. The COUNT register is written to zero upon reset and compare match. Revision 3 of the AVR32 Architecture allows some implementations to disable this automatic clearing of COUNT upon COMPARE match, usually by programming a bit in CPUCR. Refer to the Technical Reference Manual for the device for details. Incrementation of the COUNT register can not be disabled. The COUNT register will increment even though a compare interrupt is pending. COMPARE - Cycle Counter Compare Register The COMPARE register holds a value that the COUNT register is compared against. The COMPARE register can both be read and written. When the COMPARE and COUNT registers match, a compare interrupt request is generated and COUNT is reset to 0. This interrupt request is routed out to the interrupt controller, which may forward the request back to the processor as a normal interrupt request at a priority level determined by the interrupt controller. Writing a value to the COMPARE register clears any pending compare interrupt requests. The compare and exception generation feature is disabled if the COMPARE register contains the value zero. The COMPARE register is written to zero upon reset. TLBEHI - MMU TLB Entry Register High Part Used to interface the CPU to the TLB. The contents and functionality of the register is described in detail in Section 5. “Memory Management Unit” on page 35. TLBELO - MMU TLB Entry Register Low Part Used to interface the CPU to the TLB. The contents and functionality of the register is described in detail in Section 5. “Memory Management Unit” on page 35. PTBR - MMU Page Table Base Register Contains a pointer to the start of the Page Table. The contents and functionality of the register is described in detail in Section 5. “Memory Management Unit” on page 35. TLBEAR - MMU TLB Exception Address Register Contains the virtual address that caused the most recent MMU error. The contents and functionality of the register is described in detail in Section 5. “Memory Management Unit” on page 35. 19 32000D–04/2011 MMUCR - MMU Control Register Used to control the MMU and the TLB. The contents and functionality of the register is described in detail in Section 5. “Memory Management Unit” on page 35. TLBARLO / TLBARHI - MMU TLB Accessed Register Low / High Contains the Accessed bits for the TLB. The contents and functionality of the register is described in detail in Section 5. “Memory Management Unit” on page 35. PCCNT - Performance Clock Counter Clock cycle counter for performance counters. The contents and functionality of the register is described in detail in Section 7. “Performance counters” on page 57. PCNT0 / PCNT1 - Performance Counter 0 / 1 Counts the events specified by the Performance Counter Control Register. The contents and functionality of the register is described in detail in Section 7. “Performance counters” on page 57. PCCR - Performance Counter Control Register Controls and configures the setup of the performance counters. The contents and functionality of the register is described in detail in Section 7. “Performance counters” on page 57. BEAR - Bus Error Address Register Physical address that caused a Data Bus Error. This register is Read Only. Writes are allowed, but are ignored. MPUARn - MPU Address Register n Registers that define the base address and size of the protection regions. Refer to Section 6. “Memory Protection Unit” on page 51 for details. MPUPSRn - MPU Privilege Select Register n Registers that define which privilege register set to use for the different subregions in each protection region. Refer to Section 6. “Memory Protection Unit” on page 51 for details. MPUCRA / MPUCRB - MPU Cacheable Register A / B Registers that define if the different protection regions are cacheable. Refer to Section 6. “Memory Protection Unit” on page 51 for details. MPUBRA / MPUBRB - MPU Bufferable Register A / B Registers that define if the different protection regions are bufferable. Refer to Section 6. “Memory Protection Unit” on page 51 for details. MPUAPRA / MPUAPRB - MPU Access Permission Register A / B Registers that define the access permissions for the different protection regions. Refer to Section 6. “Memory Protection Unit” on page 51 for details. MPUCR - MPU Control Register Register that control the operation of the MPU. Refer to Section 6. “Memory Protection Unit” on page 51 for details. 20 AVR32 32000D–04/2011 AVR32 SS_STATUS - Secure State Status Register Register that can be used to pass status or other information from the secure state to the nonsecure state. Refer to Section 4. “Secure state” on page 31 for details. SS_ADRF, SS_ADRR, SS_ADR0, SS_ADR1 - Secure State Address Registers Registers used to partition memories into a secure and a nonsecure section. Refer to Section 4. “Secure state” on page 31 for details. SS_SP_SYS, SS_SP_APP - Secure State SP_SYS and SP_APP Registers Read-only registers containing the SP_SYS and SP_APP values. Refer to Section 4. “Secure state” on page 31 for details. SS_RAR, SS_RSR - Secure State Return Address and Return Status Registers Contains the address and status register of the sscall instruction that called secure state. Also used when returning to nonsecure state with the retss instruction. Refer to Section 4. “Secure state” on page 31 for details. 2.11.1 Configuration Registers Configuration registers are used to inform applications and operating systems about the setup and configuration of the processor on which it is running, see Figure 2-8 on page 21. The AVR32 implements the following read-only configuration registers. Figure 2-8. Configuration Registers CONFIG0 31 24 23 Processor ID 20 19 16 15 Processor Revision - 13 12 AT 10 9 AR 7 6 5 4 3 2 1 0 MMUT F J P O S D R CONFIG1 31 26 25 IMMU SZ 20 19 DMMU SZ 16 15 ISET 13 12 ILSZ 10 9 IASS 6 5 DSET 3 2 DLSZ 0 DASS Table 2-8 on page 21 shows the CONFIG0 fields. Table 2-8. CONFIG0 Fields Name Bit Description Processor ID 31:24 Specifies the type of processor. This allows the application to distinguish between different processor implementations. RESERVED 23:20 Reserved for future use. Processor revision 19:16 Specifies the revision of the processor implementation. 21 32000D–04/2011 Table 2-8. Name CONFIG0 Fields (Continued) Bit Description Architecture type AT AR 15:13 12:10 Value Semantic 0 AVR32A 1 AVR32B Other Reserved Architecture Revision. Specifies which revision of the AVR32 architecture the processor implements. Value Semantic 0 Revision 0 1 Revision 1 2 Revision 2 3 Revision 3 Other Reserved MMU type MMUT 9:7 Value Semantic 0 None, using direct mapping and no segmentation 1 ITLB and DTLB 2 Shared TLB 3 Memory Protection Unit Other Reserved Floating-point unit implemented F Value Semantic 0 No FPU implemented 1 FPU implemented 6 Java extension implemented J Value Semantic 0 No Java extension implemented 1 Java extension implemented 5 Performance counters implemented P Value Semantic 0 No Performance Counters implemented 1 Performance Counters implemented 4 On-Chip Debug implemented O 22 Value Semantic 0 No OCD implemented 1 OCD implemented 3 AVR32 32000D–04/2011 AVR32 Table 2-8. Name CONFIG0 Fields (Continued) Bit Description SIMD instructions implemented S Value Semantic 0 No SIMD instructions 1 SIMD instructions implemented 2 DSP instructions implemented D Value Semantic 0 No DSP instructions 1 DSP instructions implemented 1 Memory Read-Modify-Write instructions implemented R Value Semantic 0 No RMW instructions 1 RMW instructions implemented 0 Table 2-9 on page 23 shows the CONFIG1 fields. Table 2-9. CONFIG1 Fields Name Bit Description IMMU SZ 31:26 The number of entries in the IMMU equals (IMMU SZ) + 1. Not used in single-MMU or MPU systems. 25:20 Specifies the number of entries in the DMMU or in the shared MMU in single-MMU systems. The number of entries in the DMMU or shared MMU equals (DMMU SZ + 1). In systems with MPU, DMMU SZ equals the number of MPUAR entries. DMMU SZ 23 32000D–04/2011 Table 2-9. Name CONFIG1 Fields (Continued) Bit Description Number of sets in ICACHE ISET Value Semantic 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 8 256 9 512 10 1024 11 2048 12 4096 13 8192 14 16384 15 32768 19:16 Line size in ICACHE ILSZ 24 Value Semantic 0 No ICACHE present 1 4 bytes 2 8 bytes 3 16 bytes 4 32 bytes 5 64 bytes 6 128 bytes 7 256 bytes 15:13 AVR32 32000D–04/2011 AVR32 Table 2-9. Name CONFIG1 Fields (Continued) Bit Description Associativity of ICACHE IASS Value Semantic 0 Direct mapped 1 2-way 2 4-way 3 8-way 4 16-way 5 32-way 6 64-way 7 128-way 12:10 Number of sets in DCACHE DSET Value Semantic 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 8 256 9 512 10 1024 11 2048 12 4096 13 8192 14 16384 15 32768 9:6 25 32000D–04/2011 Table 2-9. Name CONFIG1 Fields (Continued) Bit Description Line size in DCACHE DLSZ Value Semantic 0 No DCACHE present 1 4 bytes 2 8 bytes 3 16 bytes 4 32 bytes 5 64 bytes 6 128 bytes 7 256 bytes 5:3 Associativity of DCACHE DASS 2.12 Value Semantic 0 Direct mapped 1 2-way 2 4-way 3 8-way 4 16-way 5 32-way 6 64-way 7 128-way 2:0 Recommended Call Convention The compiler vendor is free to define a call convention, but seen from a hardware point of view, there are some recommendations on how the call convention should be defined. Register R12 is intended as return value register in connection with function calls. Some instructions will use this register implicitly. For instance, the conditional ret instruction will move its argument into R12. 26 AVR32 32000D–04/2011 AVR32 3. Java Extension Module The AVR32 architecture can optionally support execution of Java bytecodes by including a Java Extension Module (JEM). This support is included with minimal hardware overhead. Comparing Java bytecode instructions with native AVR32 instructions, we see that a large part of the instructions overlap as illustrated in Figure 3-1 on page 27. The idea is thus to reuse the hardware resources by adding a separate Java instruction decoder and control module that executes in Java state. The processor keeps track of its execution state through the status register and changes execution mode seamlessly. In a larger runtime system, an operating system keeps track of and dispatches different processes. A Java program will typically be one, or several, of these processes. The Java state is not to be confused with the security modes “system” and “application”, as the JEM can execute in both modes. When the processor switches instruction decoder and enters Java state, it does not affect the security level set by the system. A Java program could also be executed from the different interrupt levels without interfering with the mode settings of the processor, although it is not recommended that interrupt routines are written in Java due to latency. The Java binary instructions are called bytecodes. These bytecodes are one or more bytes long. A bytecode consists of an opcode and optional arguments. The bytecodes include some instructions with a high semantic content. In order to reduce the hardware overhead, these instructions are trapped and executed as small RISC programs. These programs are stored in the program memory and can be changed by the programmer (part of the Java VM implementation). This gives full flexibility with regards to future extensions of the Java instruction set. Performance is ensured through an efficient trapping mechanism and “Java tailored” RISC instructions. Figure 3-1. A large part of the instruction set is shared between the AVR RISC and the Java Virtual Machine. The Java instruction set includes instructions with high semantic contents while the AVR RISC instruction set complements Java’s set with traditional hardware near RISC instructions Java Java additions High level instructions 3.1 AVR Common AVR RIS C additions Low level instructions The AVR32 Java Virtual Machine The AVR32 Java Virtual machine consists of two parts, the Java Extension Module in hardware and the AVR32 specific Java Virtual Machine software, see Figure 3-2 on page 28. Together, the two modules comply with the Java Virtual Machine specification. 27 32000D–04/2011 The AVR32 Java Virtual Machine software loads and controls the execution of the Java classes. The bytecodes are executed in hardware, except for some instructions, for example the instructions that create or manipulate objects. These are trapped and executed in software within the Java Virtual Machine. Figure 3-2. Overview of the AVR32 Java Virtual Machine and the Java Extension Module. The grey area represent the software parts of the virtual machine, while the white box to the right represents the hardware module. AVR32 Java Virtual Machine Heap Garbage Collector Objects Header Data Method Area Trapped Object Bytecodes Classes Class Variables Attributes Methods Meta Data AVR32 Java Extension Module Constant Pool Other Trapped Bytecodes Threads Frames Stack PC, SP Local Variables Const. Pool Pointer Scheduler Figure 3-3 on page 29 shows one example on how a Java program is executed. The processor boots in AVR32 (RISC) state and it executes applications as a normal RISC processor. To invoke a Java program, the Java Virtual Machine is called like any other application. The Java Virtual Machine will execute an init routine followed by a class loader that parses the class and initializes all registers necessary to start executing the Java program. The last instruction in the 28 AVR32 32000D–04/2011 AVR32 class loader is the “RETJ” instruction that sets the processor in the Java state. This means that the instruction decoder now decodes Java opcodes instead of the normal AVR32 opcodes. Figure 3-3. Example of running a Java program void main() { function1 (); application (); Java Extension Module ajvm(arguments) void ajvm() { init(); classloader(); retj; AVR32 Java Virtual Machine iconst_1 istore_0 iconst_2 getfield mfsr R12, JECR cp R12, 0x8 retj iconst_1 istore_0 iconst_2 Trap routines return mfsr R12, JECR cp R12, 0x8 cleanup() void cleanup() { } ret } application 29 32000D–04/2011 During execution of the Java program, the Java Extension Module will encounter some bytecodes that are not supported in hardware. The instruction decoder will automatically recognize these bytecodes and switch the processor back into RISC state and at the same time jump to a predefined location where it will execute a software routine that performs the semantic of the trapped bytecode. When finished, the routine ends with a “RETJ” instruction. This instruction will make the AVR32 core return to Java state and the Java program will continue at the correct location. Detailed technical information about the Java Extension module is available in a separate Java Technical Reference document. 30 AVR32 32000D–04/2011 AVR32 4. Secure state Revision 3 of the AVR32 architecture introduces a secure execution state. This state is intended to allow execution of a proprietary secret code alongside code of unknown origin and intent on the same processor. For example, a company with a proprietary algorithm can program this algorithm into the secure memory sections of the device, and resell the device with the programmed algorithm to an end customer. The end customer will not be able to read or modify the preprogrammed code in any way. Examples of such preprogrammed code can be multimedia codecs, digital signal processing algorithms or telecom software stacks. Whereas previous approaches to this problem required the proprietary code and the end user application to execute on separate devices, the secure state allows integration of the two codes on the same device, saving cost and increasing performance since inter-IC communication is no longer required. In order to keep the proprietary code secret, this code will execute in a “secure world”. The end user application will execute in a “nonsecure world”. Code in the nonsecure world can request services from the secure world by executing a special instruction, sscall. This instruction is executed in the context of an API specified by the provider of the proprietary code. The sscall instruction can be associated with arguments passed in registers or memory, and after execution of the requested algorithm, the secure world returns results to the requesting nonsecure application in registers or in memory. Hardware is implemented to divide the memory resources into two sections, one secure and one non-secure section. The secure section of the memories can only be accessed (read, written or executed) from code running in the secure world. The nonsecure section of the memories can be read, written or executed from the nonsecure world, and read or written from the secure world. The customer can choose if his application will enable the secure state support or not. An IMPLEMENTATION DEFINED mechanism, usually a Flash fuse, is used to enable or disable secure state support. If this mechanism is programmed so as to disable the secure state, the system will boot in nonsecure world, and its behavior will be identical to previous devices implementing older revisions of the AVR32 architecture. If the system is set up to enable secure state support, the system will boot in the secure state. This allows configuration and startup of the secure world application before execution is passed to the nonsecure world. 4.1 Mechanisms implementing the Secure State The following architectural mechanisms are used to implement the secure state: • The sscall and retss instructions are used for passing between the secure and nonsecure worlds. • The secure world has a dedicated stack pointer, SP_SEC, which is automatically banked into the register file whenever executing in the secure world. • The SS bit is set in the status register whenever the system is in the secure state. Only sscall and retss can alter this bit. • Interrupts and exceptions have special handler addresses used when receiving interrupts or exceptions in the secure world. This allows executing the interrupt or exception handler in the secure world, or jumping back into the nonsecure world to execute the handler there. • A set of secure system registers are used to configure the secure world behavior, and to aid in communication between the secure and nonsecure worlds. These registers can be written when in the secure world, but only read when in the nonsecure world. 31 32000D–04/2011 • When trying to access secure world memories from the nonsecure world, a bus error exception will be raised, and the access will be aborted. Writes to secure system registers from within the nonsecure world will simply be disregarded without any error indication. • The On-Chip Debug (OCD) system is modified to prevent any leak of proprietary code or data to the nonsecure world. This prevents hacking through the use of the OCD system. 4.2 Secure state programming model The programming model in the secure state is similar to in normal RISC state, except that SP_SEC has been banked in, and the secure system registers are available in all privileged modes. Figure 4-1. Register File in AVR32A with secure context Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Bit 31 Bit 0 Exception NMI Bit 31 Bit 31 Bit 0 Secure Bit 0 Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SR SR SR SR SR SR SR SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 32 AVR32 32000D–04/2011 AVR32 Figure 4-2. Register File in AVR32B with secure context Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 Bit 31 INT2 Bit 0 Bit 31 INT3 Bit 0 Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR / LR_INT0 SP_SYS banked registers banked registers banked registers banked registers (implementation defined) (implementation defined) (implementation defined) (implementation defined) SR SR RSR_SUP RAR_SUP SR RSR_INT0 RAR_INT0 SR RSR_INT1 RAR_INT1 SR RSR_INT2 RAR_INT2 SR RSR_INT3 RAR_INT3 PC LR / LR_INT1 SP_SYS PC LR / LR_INT2 SP_SYS PC LR / LR_INT3 SP_SYS Exception NMI Bit 31 Bit 31 Bit 0 Secure Bit 0 Bit 31 Bit 0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_EX RAR_EX SR RSR_NMI RAR_NMI SR SS_RSR SS_RAR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 4.3 Details on Secure State implementation Refer to the Technical Reference manual for the CPU core you are using for details on the Secure State implementation. 33 32000D–04/2011 34 AVR32 32000D–04/2011 AVR32 5. Memory Management Unit The AVR32 architecture defines an optional Memory Management Unit (MMU). This allows efficient implementation of virtual memory and large memory spaces. Virtual memory simplifies execution of multiple processes and allows allocation of privileges to different sections of the memory space. 5.1 Memory map in systems with MMU The AVR32 architecture specifies a 32-bit virtual memory space. This virtual space is mapped into a 32-bit physical space by a MMU. It should also be noted that not all implementations will use caches. The cacheability information specified in the figure will therefore not apply for all implementations. Refer to the implementation-specific Hardware Manual for details. The virtual memory map is specified in Figure 5-1. Figure 5-1. The AVR32 virtual memory space 0xFFFFFFFF 0xE0000000 0xC0000000 0xA0000000 0x80000000 512MB system space, non-cacheable 0xFFFFFFFF P4 512MB translated space, P3 cacheable 512MB non-translated space, non-cacheable P2 512MB non-translated space, cacheable P1 2GB translated space Cacheable P0 0x00000000 Unaccessible space Access error 0x80000000 2GB translated space Cacheable U0 0x00000000 Privileged Modes Unprivileged Mode The memory map has six different segments, named P0 through P4, and U0. The P-segments are accessible in the privileged modes, while the U-segment is accessible in the unprivileged mode. Both the P1 and P2 segments are default segment translated to the physical address range 0x00000000 to 0x1FFFFFFF. The mapping between virtual addresses and physical addresses is therefore implemented by clearing of MSBs in the virtual address. The difference between P1 and P2 is that P1 may be cached, depending on the cache configuration, while P2 is always uncached. Because P1 and P2 are segment translated and not page translated, code for initialization of MMUs and exception vectors are located in these segments. P1, being cacheable, may offer higher performance than P2. 35 32000D–04/2011 The P3 space is also by default segment translated to the physical address range 0x00000000 to 0x1FFFFFFF. By enabling and setting up the MMU, the P3 space becomes page translated. Page translation will override segment translation. The P4 space is intended for memory mapping special system resources like the memory arrays in caches. This segment is non-cacheable, non-translated. The U0 segment is accessible in the unprivileged user mode. This segment is cacheable and translated, depending upon the configuration of the cache and the memory management unit. If accesses to other memory addresses than the ones within U0 is made in application mode, an access error exception is issued. The virtual address map is summarized in Table 5-1 on page 36. Table 5-1. The virtual address map Virtual address [31:29] Segment name Virtual Address Range Segment size Accessible from Default segment translated 111 P4 0xFFFF_FFFF to 0xE000_0000 512 MB Privileged No System space Unmapped, Uncacheable 110 P3 0xDFFF_FFFF to 0xC000_0000 512 MB Privileged Yes Mapped, Cacheable 101 P2 0xBFFF_FFFF to 0xA000_0000 512 MB Privileged Yes Unmapped, Uncacheable 100 P1 0x9FFF_FFFF to 0x8000_0000 512 MB Privileged Yes Unmapped, Cacheable 0xx P0 / U0 0x7FFF_FFFF to 0x0000_0000 2 Gb Unprivileged Privileged No Mapped, Cacheable Characteristics The segment translation can be disabled by clearing the S bit in the MMUCR. This will place all the virtual memory space into a single 4 GB mapped memory space. Doing this will give all access permission control to the AP bits in the TLB entry matching the virtual address, and allow all virtual addresses to be translated. Segment translation is enabled by default. The AVR32 architecture has two translations of addresses. 1. Segment translation (enabled by the MMUCR[S] bit) 2. Page translation (enabled by the MMUCR[E] bit) Both these translations are performed by the MMU and they can be applied independent of each other. This means that you can enable: 1. No translation. Virtual and physical addresses are the same. 2. Segment translation only. The virtual and physical addresses are the same for addresses residing in the P0, P4 and U0 segments. P1, P2 and P3 are mapped to the physical address range 0x00000000 to 0x1FFFFFFF. 3. Page translation only. All addresses are mapped as described by the TLB entries. 4. Both segment and page translations. P1 and P2 are mapped to the physical address range 0x00000000 to 0x1FFFFFFF. U0, P0 and P3 are mapped as described by the TLB entries. The virtual and physical addresses are the same for addresses residing in the P4 segment. The segment translation is by default turned on and the page translation is by default turned off after reset. The segment translation is summarized in Figure 5-2 on page 37. 36 AVR32 32000D–04/2011 AVR32 Figure 5-2. The AVR32 segment translation map Virtual address space 0xFFFFFFFF P4 512MB system space, non-cacheable Physical address space Segment translation 512MB physical address space 0xE0000000 0xE0000000 512MB translated space, P3 cacheable 0xC0000000 512MB non-translated P2 space, non-cacheable 0xA0000000 512MB non-translated P1 space, cacheable 0x80000000 P0 / U0 0xFFFFFFFF 2GB translated space cacheable 0x80000000 2GB physical address space 0x20000000 0x00000000 5.2 0x00000000 Understanding the MMU The AVR32 Memory Management Unit (MMU) is responsible for mapping virtual to physical addresses. When a memory access is performed, the MMU translates the virtual address specified into a physical address, while checking the access permissions. If an error occurs in the translation process, or Operating System intervention is needed for some reason, the MMU will issue an exception, allowing the problem to be resolved by software. The MMU architecture uses paging to map memory pages from the 32-bit virtual address space to a 32-bit physical address space. Page sizes of 1, 4, 64 kilobytes and 1 megabyte are supported. Each page has individual access rights, providing fine protection granularity. The information needed in order to perform the virtual-to-physical mapping resides in a page table. Each page has its own entry in the page table. The page table also contains protection information and other data needed in the translation process. Conceptually, the page table is accessed for every memory access, in order to read the mapping information for each page. In order to speed up the translation process, a special page table cache is used. This cache is called a Translation Lookaside Buffer (TLB). The TLB contains the n most recently used page table entries. The number n of entries in the TLB is IMPLEMENTATION DEFINED. It is also IMPLEMENTATION DEFINED whether a single unified TLB should be used for both instruction and memory accesses, or if two separate TLBs are implemented. The architecture supports one or two TLBs with up to 64 entries in each. TLB entries can also be locked in the TLB, guaranteeing high-speed memory accesses. 37 32000D–04/2011 5.2.1 Virtual Memory Models The MMU provides two different virtual memory models, selected by the Mode (M) bit in the MMU Control Register: • Shared virtual memory, where the same virtual address space is shared between all processes • Private virtual memory, where each process has its own virtual address space In shared virtual memory, the virtual address uniquely identifies which physical address it should be mapped to. Two different processes addressing the same virtual address will always access the same physical address. In other words, the Virtual Page Number (VPN) section of the virtual address uniquely specifies the Physical Frame Number (PFN) section in the physical address. In private virtual memory, each process has its own virtual memory space. This is implemented by using both the VPN and the Application Space Identifier (ASID) of the current process when searching the TLB for a match. Each process has a unique ASID. Therefore, two different processes accessing the same VPN won’t hit the same TLB entry, since their ASID is different. Pages can be shared between processes in private virtual mode by setting the Global (G) bit in the page table entry. This will disable the ASID check in the TLB search, causing the VPN section uniquely to identify the PFN for the particular page. 5.2.2 MMU interface registers The following registers are used to control the MMU, and provide the interface between the MMU and the operating system. Most registers can be altered both by the application software (by writing to them) and by hardware when an exception occurs. All the registers are mapped into the System Register space, their addresses are presented in Section 2.11 “System registers” on page 14. The MMU interface registers are shown in Figure 5-3. Figure 5-3. The MMU interface registers TLBEH I 31 10 VPN 9 8 V I 7 0 A S ID TLBELO 31 10 PFN 9 8 C G B 7 6 4 AP 3 2 SZ 1 0 D W PTBR 31 0 PTBR TLBEAR 31 0 TLBEAR MMUCR 31 26 25 IR P 20 IL A 19 14 13 DRP 8 D LA 7 5 - 4 3 2 1 S N I M E 0 TLBAR LO / TLBARH I 31 0 TLBAR LO / TLBARHI 38 AVR32 32000D–04/2011 AVR32 5.2.2.1 TLB Entry Register High Part - TLBEHI The contents of the TLBEHI and TLBELO registers is loaded into the TLB when the tlbw instruction is executed. The TLBEHI register consists of the following fields: • VPN - Virtual Page Number in the TLB entry. This field contains 22 bits, but the number of bits used depends on the page size. A page size of 1 kB requires 22 bits, while larger page sizes require fewer bits. When preparing to write an entry into the TLB, the virtual page number of the entry to write should be written into VPN. When an MMU-related exception has occurred, the virtual page number of the failing address is written to VPN by hardware. • V - Valid. Set if the TLB entry is valid, cleared otherwise. This bit is written to 0 by a reset. If an access to a page which is marked as invalid is attempted, an TLB Miss exception is raised. Valid is set automatically by hardware whenever an MMU exception occurs. • I - Instruction TLB. If set, the current TLBEHI and TLBELO entries should be written into the Instruction TLB. If cleared, the Data or Unified TLB should be addressed. The I bit is set by hardware when an MMU-related exception occurs, indicating whether the error occurred in the ITLB or the UTLB/DTLB. • ASID - Application Space Identifier. The operating system allocates a unique ASID to each process. This ASID is written into TLBEHI by the OS, and used in the TLB address match if the MMU is running in Private Virtual Memory mode and the G bit of the TLB entry is cleared. ASID is never changed by hardware. 5.2.2.2 TLB Entry Register Low Part - TLBELO The contents of the TLBEHI and TLBELO registers is loaded into the TLB when the tlbw instruction is executed. None of the fields in TLBELO are altered by hardware. The TLBELO register consists of the following fields: • PFN - Physical Frame Number to which the VPN is mapped. This field contains 22 bits, but the number of bits used depends on the page size. A page size of 1 kB requires 22 bits, while larger page sizes require fewer bits. When preparing to write an entry into the TLB, the physical frame number of the entry to write should be written into PFN. • C - Cacheable. Set if the page is cacheable, cleared otherwise. • G - Global bit used in the address comparison in the TLB lookup. If the MMU is operating in the Private Virtual Memory mode and the G bit is set, the ASID won’t be used in the TLB lookup. • B - Bufferable. Set if the page is bufferable, cleared otherwise. • AP - Access permissions specifying the privilege requirements to access the page. The following permissions can be set, see Table 5-2 on page 40. 39 32000D–04/2011 Table 5-2. Access permissions implied by the AP bits AP Privileged mode Unprivileged mode 000 Read None 001 Read / Execute None 010 Read / Write None 011 Read / Write / Execute None 100 Read Read 101 Read / Execute Read / Execute 110 Read / Write Read / Write 111 Read / Write / Execute Read / Write / Execute • SZ - Size of the page. The following page sizes are provided, see Table 5-3: Table 5-3. Page sizes implied by the SZ bits SZ Page size Bits used in VPN Bits used in PFN 00 1 kB TLBEHI[31:10] TLBELO[31:10] 01 4 kB TLBEHI[31:12] TLBELO[31:12] 10 64 kB TLBEHI[31:16] TLBELO[31:16] 11 1 MB TLBEHI[31:20] TLBELO[31:20] • D - Dirty bit. Set if the page has been written to, cleared otherwise. If the memory access is a store and the D bit is cleared, an Initial Page Write exception is raised. • W - Write through. If set, a write-through cache update policy should be used. Write-back should be used otherwise. The bit is ignored if the cache only supports write-through or writeback. 5.2.2.3 Page Table Base Register - PTBR This register points to the start of the page table structure. The register is not used by hardware, and can only be modified by software. The register is meant to be used by the MMU-related exception routines. 5.2.2.4 TLB Exception Address Register - TLBEAR This register contains the virtual address that caused the most recent MMU-related exception. The register is updated by hardware when such an exception occurs. 5.2.2.5 MMU Control Register - MMUCR The MMUCR controls the operation of the MMU. The MMUCR has the following fields: • IRP - Instruction TLB Replacement Pointer. Points to the ITLB entry to overwrite when a new entry is loaded by the tlbw instruction. The IRP field may be updated automatically in an IMPLEMENTATION DEFINED manner in order to optimize the replacement algorithm. The IRP field can also be written by software, allowing the exception routine to implement a replacement algorithm in software. The IRP field is 6 bits wide, allowing a maximum of 64 40 AVR32 32000D–04/2011 AVR32 entries in the ITLB. It is IMPLEMENTATION DEFINED whether to use fewer entries. Impementations with a single unified TLB does not use the IRP field. • ILA - Instruction TLB Lockdown Amount. Specified the number of locked down ITLB entries. All ITLB entries from entry 0 to entry (ILA-1) are locked down. If ILA equals zero, no entries are locked down. Implementations with a single unified TLB does not use the ILA field. • DRP - Data TLB Replacement Pointer. Points to the DTLB entry to overwrite when a new entry is loaded by the tlbw instruction. The DRP field may be updated automatically in an IMPLEMENTATION DEFINED manner in order to optimize the replacement algorithm. The DRP field can also be written by software, allowing the exception routine to implement a replacement algorithm in software. The DRP field is 6 bits wide, allowing a maximum of 64 entries in the DTLB. It is IMPLEMENTATION DEFINED whether to use fewer entries. Implementations with a single unified TLB use the DRP field to point into the unified TLB. • DLA - Data TLB Lockdown Amount. Specified the number of locked down DTLB or UTLB entries. All DTLB entries from entry 0 to entry (DLA-1) are locked down. If DLA equals zero, no entries are locked down. • S - Segmentation Enable. If set, the segmented memory model is used in the translation process. If cleared, the memory is regarded as unsegmented. The S bit is set after reset. • N - Not Found. Set if the entry searched for by the TLB Search instruction (tlbs) was not found in the TLB. • I - Invalidate. Writing this bit to one invalidates all TLB entries. The bit is automatically cleared by the MMU when the invalidate operation is finished. • M - Mode. Selects whether the shared virtual memory mode or the private virtual memory mode should be used. The M bit determines how the TLB address comparison should be performed, see Table 5-4 on page 41. Table 5-4. MMU mode implied by the M bit M Mode 0 Private Virtual Memory 1 Shared Virtual Memory • E - Enable. If set, the MMU translation is enabled. If cleared, the MMU translation is disabled and the physical address is identical to the virtual address. Access permissions are not checked and no MMU-related exceptions are issued if the MMU is disabled. If the MMU is disabled, the segmented memory model is used. 5.2.2.6 TLB Accessed Register HI / LO - TLBARHI / TLBARLO The TLBARHI and TLBARLO register form one 64-bit register with 64 1-bit fields. Each of these fields contain the Accessed bit for the corresponding TLB entry. The I bit in TLBEHI determines whether the ITLB or DTLB Accessed bits are read. The Accessed bit is 0 if the page has been accessed, and 1 if it has not been accessed. Bit 31-0 in TLBARLO correspond to TLB entry 031, bit 31-0 in TLBARHI correspond to TLB entry 32-63. If the TLB implementation contains less than 64 entries then nonimplemented entries are read as 0. Note: The contents of TLBARHI/TLBARLO are reversed to let the Count Leading Zero (CLZ) instruction be used directly on the contents of the registers. E.g. if CLZ returns the value four on the contents of TLBARLO, then item four is the first unused item in the TLB. 41 32000D–04/2011 5.2.3 Page Table Organization The MMU leaves the page table organization up to the OS software. Since the page table handling and TLB handling is done in software, the OS is free to implement different page table organizations. It is recommended, however, that the page table entries (PTEs) are of the format shown in Figure 5-4. This allows the loaded PTE to be written directly into TLBELO, without the need for reformatting. How the PTEs are indexed and organized in memory is left to the OS. Figure 5-4. Recommended Page Table Entry format 31 10 9 8 7 6 PFN 5.2.4 C G B 4 3 2 1 0 AP SZ D W TLB organization The TLB is used as a cache for the page table, in order to speed up the virtual memory translation process. Up to two TLBs can be implemented, each with up to 64 entries. Each TLB is configured as shown in Figure 5-5 on page 42. Figure 5-5. TLB organization Address section Data section Entry 0 VPN[21:0] ASID[7:0] V PFN[21:0] C G B AP[2:0] SZ[1:0] D W A Entry 1 VPN[21:0] ASID[7:0] V PFN[21:0] C G B AP[2:0] SZ[1:0] D W A Entry 2 VPN[21:0] ASID[7:0] V PFN[21:0] C G B AP[2:0] SZ[1:0] D W A Entry 3 VPN[21:0] ASID[7:0] V PFN[21:0] C G B AP[2:0] SZ[1:0] D W A Entry 63 VPN[21:0] ASID[7:0] V PFN[21:0] C G B AP[2:0] SZ[1:0] D W A The D, W and AP[1] bits are not implemented in ITLBs, since they have no meaning there. The AP[0] bits are not implemented in DTLBs, since they have no meaning there. The A bit is the Accessed bit. This bit is set when the TLB entry is loaded with a new value using the tlbw instruction. It is cleared whenever the TLB matching process finds a match in the specific TLB entry. The A bit is used to implement pseudo-LRU replacement algorithms. When an address look-up is performed by the TLB, the address section is searched for an entry matching the virtual address to be accessed. The matching process is described in chapter 5.2.5. 42 AVR32 32000D–04/2011 AVR32 5.2.5 Translation process The translation process maps addresses from the virtual address space to the physical address space. The addresses are generated as shown in Table 5-5, depending on the page size chosen: Table 5-5. Physical address generation Page size Physical address 1 kB PFN[31:10], VA[9:0] 4 kB PFN[31:12], VA[11:0] 64 kB PFN[31:16], VA[15:0] 1 MB PFN[31:20], VA[19:0] A data memory access can be described as shown in Table 5-6. Table 5-6. Data memory access pseudo-code example If (Segmentation disabled) If (! PagingEnabled) PerformAccess(cached, write-back); else PerformPagedAccess(VA); else if (VA in Privileged space) if (InApplicationMode) SignalException(DTLB Protection, accesstype); endif; if (VA in P4 space) PerformAccess(non-cached); else if (VA in P2 space) PerformAccess(non-cached); else if (VA in P1 space) PerformAccess(cached, writeback); else // VA in P0, U0 or P3 space if ( ! PagingEnabled) PerformAccess(cached, writeback); else PerformPagedAccess(VA); endif; endif; endif; 43 32000D–04/2011 The translation process performed by PerformTranslatedAccess( ) can be described as shown in Table 5-7. Table 5-7. PerformTranslatedAccess( ) pseudo-code example match ← 0; for (i=0; i n Number of bits in operand x x >> n x (2n-1-1)) then (2n-1-1); elseif (x < -2n-1) then -2n-1; else x; Signed to Unsigned Saturation ( x is treated as a signed value ): If (x > (2n-1)) then (2n-1-1); elseif ( x < 0 ) then 0; else x; Unsigned Saturation ( x is treated as an unsigned value ): If (x > (2n-1)) then (2n-1-1); else x; Sign Extend x to an n-bit value Identical to SE(x, 32) Zero Extend x to an n-bit value Identical to ZE(x, 32) Operations SATSU(x, n) SATU(x, n) SE(x, n) SE(x) ZE(x, n) ZE(x) 9.1.4 Status Register Flags C: Z: N: V: Q: instructions. M0: 94 Carry / Borrow flag. Zero flag, set if the result of the operation is zero. Bit 31 of the result. Set if 2’s complement overflow occurred. Saturated flag, set if saturation and/or overflow has occurred after some Mode bit 0 AVR32 32000D–04/2011 AVR32 M1: M2: 9.1.5 9.1.6 9.1.7 9.1.8 Mode bit 1 Mode bit 2 Data Type Extensions .d .w .h .b Double (64-bit) operation. Word (32-bit) operation. Halfword (16-bit) operation. Byte operation (8-bit) operation. t b Top halfword, bits 31-16. Bottom halfword, bits 15-0. t u l b Top byte, bits 31-24. Upper byte, bits 23-16. Lower byte, bits 15-8. Bottom byte, bits 7-0. Halfword selectors Byte selectors CPU System Registers RSR_INT0: RSR_INT1: RSR_INT2: RSR_INT3: RSR_EX: RSR_NMI: RSR_SUP: Interrupt level 0 Return Status Register. Interrupt level 1 Return Status Register. Interrupt level 2 Return Status Register. Interrupt level 3 Return Status Register. Exception Return Status Register. Non maskable interrupt Return Status Register. Supervisor Return Status Register. RAR_INT0: RAR_INT1: RAR_INT2: RAR_INT3: RAR_EX: RAR_NMI: RAR_SUP: Interrupt level 0 Return Address Register. Interrupt level 1 Return Address Register. Interrupt level 2 Return Address Register. Interrupt level 3 Return Address Register. Exception Return Address Register. Non maskable interrupt Return Address Register. Supervisor Return Address Register. ACBA: EVBA: Application Call Base Address register. Exception Vector Base Address register. 95 32000D–04/2011 9.1.9 Branch conditions Table 9-1. Branch conditions Coding in cond3 Coding in cond4 Condition mnemonic Evaluated expression B’000 B’0000 eq Z Equal B’001 B’0001 ne ¬Z Not equal B’010 B’0010 cc / hs ¬C Unsigned Higher or same B’011 B’0011 cs / lo C Unsigned Lower B’100 B’0100 ge N == V Signed Greater than or equal B’101 B’0101 lt N⊕V Signed Less than B’110 B’0110 mi N Signed Minus / negative B’111 B’0111 pl ¬N Signed Plus / positive N/A B’1000 ls C∨Z Unsigned Lower or same N/A B’1001 gt ¬Z ∧ (N==V) Signed Greater than N/A B’1010 le Z ∨ (N ⊕ V) Signed Less than or equal N/A B’1011 hi ¬C ∧ ¬Z Unsigned Higher N/A B’1100 vs V Overflow N/A B’1101 vc ¬V No overflow N/A B’1110 qs Q N/A B’1111 al True 96 Numerical format Fractional Meaning Saturation Always AVR32 32000D–04/2011 AVR32 9.2 Instruction Formats This is an overview of the different instruction formats. 9.2.1 Two Register Instructions 15 13 12 Opcod 9.2.2 1 0 0 Rd/Rs 12 0 1 13 12 0 1 9 1 1 8 4 0 3 Opcode 0 Rd 1 1 9 8 7 1 Opc 4 3 cond4 0 Rs/Rd 13 12 1 Opc 11 4 3 k8 0 Rd SP / PC relative load / store 15 0 1 13 12 11 10 0 Opcode 4 3 k7 0 Rd/Rs K5 immediate and single register 15 0 1 13 12 0 1 10 9 0 Opc 1 8 4 3 k5 0 Rd Displacement load with k5 immediate 15 0 9.2.8 Opcode 0 K8 immediate and single register 15 9.2.7 3 Return and test 0 9.2.6 13 1 15 9.2.5 4 Single Register Instructions 0 9.2.4 8 Rs/Rp 15 9.2.3 9 13 1 12 1 9 8 4 Rp 3 k5 0 Rd Displacement load / store with k3 immediate 15 14 13 1 0 0 12 9 Rp 8 7 Opcode 6 4 k3 3 0 Rd/Rs 97 32000D–04/2011 9.2.9 One register and a register pair 15 1 9.2.10 13 0 1 1 0 12 0 1 0 13 0 1 1 0 5 0 Opcode 1 11 8 0 4 1 Opc 20 1 0 1 Opc 19 16 1 Rd 7 0 k8 9 8 Bit[4:1] 5 Opcode 4 3 0 Bit[0] 13 12 0 0 11 4 k8 Rd 3 2 0 1 13 12 0 0 11 4 K10[7:0] 3 1 12 1 0 11 4 1 k8/Label 0 cond3 2 1 0 Opc K10[9:8] 3 0 0 3 2 k 0 1 0 0 Opc Multiple registers (POPM) 15 1 1 0 1 PC LR 12 11 10 9-8 7-4 3-0 0 1 0 Multiple registers (PUSHM) 15 1 1 13 12 11 0 1 PC 4 LR 12 11 10 9 8 10 9-8 7-4 3-0 3 0 0 0 1 1 Status register bit specification 15 1 98 0 K8 and no register 1 9.2.17 1 Rd/Rs cond4 12 1 15 9.2.16 3 Relative jump and call 15 9.2.15 1 6 Short branch 15 9.2.14 8 One register with bit addressing 15 9.2.13 Rp 1 15 9.2.12 9 One register with k8 immediate and cond4 31 29 28 25 24 1 9.2.11 12 11 1 0 1 0 Opcode 4 Bit No 3 0 0 1 0 0 AVR32 32000D–04/2011 AVR32 9.2.18 Only Opcode 15 1 9.2.19 9 1 0 1 29 1 0 3 Opcode 0 0 1 0 0 0 25 0 24 0 11 8 0 Opcode 20 0 7 0 0 6 0 0 5 19 0 16 Ry/Ri 4 3 Shift Amount 0 Rd/Rs 3 registers unshifted 1 29 1 0 28 Rx 12 0 25 1 15 0 24 0 20 0 0 0 11 0 16 Ry 4 0 19 3 Opcode 0 Rd DSP Halfword Multiply 31 1 29 1 0 28 Rx 12 0 25 1 15 0 24 0 11 8 0 Opcode 20 0 7 0 0 0 19 0 6 5 4 0 X Y 16 Ry 3 0 Rd DSP Word and Halfword Multiply 31 1 29 1 0 28 Rx 12 0 25 1 15 9.2.23 1 Rb/Rx 12 31 9.2.22 1 28 1 15 9.2.21 0 4 3 registers shifted 31 9.2.20 1 8 0 0 11 8 0 Opcode 2 register operands with k8 immediate 31 29 28 25 1 1 1 15 0 Rs 12 0 0 1 24 0 7 0 0 0 5 4 0 Y 24 8 Opcode 0 1 0 11 20 0 0 16 Ry 3 0 Rd 20 0 19 0 19 16 Rd 7 0 k8 99 32000D–04/2011 9.2.24 2 register operands with k5 immediate 31 1 29 1 9.2.25 Rs 12 0 25 1 15 0 28 0 11 8 1 1 20 0 0 1 25 Rd 15 0 1 1 15 Rd 4 0 0 k5 20 1 1 16 0 0 1 5 4 19 16 Rs 0 o5 29 28 26 1 1 Opc 13 12 25 11 k12 [11:8] w5 24 20 1 1 0 8 7 6 1 19 16 0 Rp 0 CRd/CRs k12[7:0] 2 register operands 31 1 29 1 0 28 Rs 12 0 25 1 15 9.2.28 0 19 Coprocessor 0 load and store 31 9.2.27 5 9 Opcode 9.2.26 0 24 1 10 0 7 Opcode 2 Registers with w5 and o5 31 29 28 1 24 0 0 11 1 24 8 20 0 0 0 1 Opcode 1 16 0 Rd 7 0 0 0 0 Register operand with K16 31 29 28 1 19 0 0 20 19 Opcode 0 0 0 16 Rd/Rp 15 0 k16 9.2.29 Cache operation 31 1 20 1 1 1 0 1 0 0 0 0 0 15 16 Rp 0 Op5 100 1 19 k11 AVR32 32000D–04/2011 AVR32 9.2.30 Register or condition code and K21 31 29 28 25 1 1 1 24 K21[20:17] 21 20 19 K21 [16] Opcode 16 Rd/cond 15 0 k21[15:0] 9.2.31 No register and k21 31 29 28 1 1 1 25 24 K[20:17] 21 20 19 K21 [16] Opcode 16 Opcode 15 0 k21[15:0] 9.2.32 Two registers and K16 31 29 28 1 1 1 25 24 20 Rs/Rp 19 Opcode 16 Rd/Rs 15 0 k16 9.2.33 Register, doubleword register and K16 31 1 29 1 28 25 1 24 20 Rs/Rp 19 Opcode 16 Rd/Rs 15 Opc 0 k16 9.2.34 K16 and bit address 31 29 28 1 1 1 0 26 0 25 0 Bit[4] 24 1 20 1 0 0 19 1 16 Bit[3:0] 15 0 k16 9.2.35 Coprocessor Operation 31 1 1 29 28 1 0 25 0 Op[5:4] 24 1 20 1 0 1 0 19 16 Op[3:0] 15 0 CP# Op[6] CRd CRx CRy 101 32000D–04/2011 9.2.36 Coprocessor load and store 31 1 1 15 29 28 1 0 1 13 12 11 CP # 9.2.37 Opc 1 15 0 Opc 1 1 0 8 7 6 1 15 1 1 0 1 13 12 11 10 9 8 ++/-- 0 1 0 1 Opcode 13 12 11 Opc 1 1 25 24 1 1 8 CRs/CRd 15 1 0 1 13 12 11 CP# Opc 1 1 1 0 1 0 1 0 Sleep and sync 31 29 1 1 0 0 0 28 1 0 CR CR CR CR CR CR CR 14- 13- 11- 9-8 7-6 5-4 3-2 1-0 20 1 7 0 1 6 4 0 0 0 20 0 1 0 9 8 7 6 5 4 k k Opc 1 0 0 25 24 Opcode 0 Rd/Rs/Rp Opc Opc 1 0 0 0 1 0 1 16 3 1 8 0 19 0 1 15 0 Rp 0 0 0 19 17 0 16 Rp 3 20 0 16 7 0 8 0 19 CR CRs/CRd 0 Rp 0 1 15 0 0 20 Register and system register 31 1 16 0 Coprocessor load and store with indexed addressing 31 29 28 25 24 1 102 1 19 k8 0 CP# 9.2.41 20 CRd/CRs Coprocessor load, store and move 31 29 28 1 9.2.40 24 1 CP # 9.2.39 25 Coprocessor load and store multiple registers 31 29 28 25 24 1 9.2.38 26 0 i3 19 1 16 Rd/Rs 7 0 System Register Ad- 1 0 1 20 19 1 0 7 16 0 0 0 0 Op8 AVR32 32000D–04/2011 AVR32 9.2.42 Register and bit address 31 1 29 1 28 1 25 Opcode 24 20 1 1 0 1 15 0 9.2.43 5 0 0 0 0 0 0 0 0 25 24 ++/-- 1 0 19 1 16 Rd 4 0 0 Bit Number Load and store multiple registers 31 1 29 1 28 1 26 Opcode 20 1 1 0 19 0 16 Rp 15 0 R15 R14 R13 R12 R11 R10 R9 9.2.44 29 28 1 1 1 15 14 13 12 0 0 0 Part R6 29 1 1 1 15 14 13 0 1 25 Rp 24 1 1 1 R4 R3 20 19 R2 R1 R0 0 1 16 Rd 11 0 k12 1 28 25 Rp 12 24 1 20 1 1 1 16 Rd 0 k12 28 25 1 15 0 19 11 Part 2 Register and k12 31 29 1 Rp 12 24 1 20 1 1 0 19 1 16 Rd/Rs 11 0 Opcode 9.2.47 R5 Register, k12 and byte select 31 9.2.46 R7 Register, k12 and halfword select 31 9.2.45 R8 k12 ANDL / ANDH 31 1 1 29 28 1 0 26 0 25 Opc COH 24 0 20 0 15 0 0 1 19 16 Rd 0 k16 103 32000D–04/2011 9.2.48 Saturate 31 1 29 1 28 1 Opcode 15 0 9.2.49 0 25 0 12 11 10 0 0 0 24 1 20 1 9 1 29 1 28 25 1 Rx 1 9 1 13 0 12 9 0 1 Rp k5 20 1 1 1 19 16 0 8 4 0 Rs 12 0 0 8 Ry 3 0 Rd 7 3 0 k4 Rs 24 0 11 20 0 8 1 4 1 25 1 15 0 0 16 0 7 Opcode 19 4 cond4 Rd 3 0 0 0 0 0 4 Registers with k2 31 29 28 1 1 1 15 14 13 12 Opcode X Y 25 Rx 1 1 1 15 14 13 12 Opcode X Y 13 12 0 1 24 1 11 20 1 8 7 Ri 3 Registers with k8 and sa 31 29 28 0 25 Rx 1 1 0 6 5 4 0 1 Ry 3 0 Rb 20 1 16 k2 24 1 19 1 11 19 16 0 4 Ry 3 0 k8 Rp k3 immediate 15 1 104 0 k5 2 Registers with cond4 31 29 28 1 9.2.54 4 Rd 2 Registers with k4 15 9.2.53 5 24 Opcode 9.2.52 1 s5 15 9.2.51 1 16 3 Registers with k5 31 9.2.50 0 19 1 7 0 1 1 0 1 6 4 k3 3 0 0 1 0 0 AVR32 32000D–04/2011 AVR32 9.2.55 Address and b5 31 29 1 1 15 14 28 1 25 Opcode 24 0 0 1 b5[4:1] 2 register operands 1 1 29 28 1 0 0 12 11 0 0 15 0 0 1 20 0 0 0 8 0 1 1 25 24 0 0 0 7 1 0 4 1 1 19 16 Rs 3 Opc 0 Rd 2 register operands and k3 31 1 29 1 0 0 28 1 15 9.2.58 0 16 k15 31 9.2.57 0 19 0 b5[0] 9.2.56 20 1 Rs 12 11 0 0 0 8 0 1 1 25 24 19 0 0 0 7 1 0 4 1 1 18 0 k3 3 Opc 16 0 Rd 2 register operands and k4 31 1 29 1 1 15 0 0 28 1 Rs 12 11 0 0 0 8 0 1 1 20 0 0 0 7 1 0 4 1 1 19 Opc 16 k4 3 0 Rd 105 32000D–04/2011 9.3 9.3.1 Instruction Set Summary Architecture revision Unless otherwise noted, all instructions are part of revision 1 of the AVR32 architecture. The following instructions were added in revision 2, none were removed: • movh Rd, imm • {add, sub, and, or, eor}{cond4}, Rd, Rx, Ry • ld.{sb, ub, sh, uh, w}{cond4} Rd, Rp[disp] • st.{b, h, w}{cond4} Rp[disp], Rs • rsub{cond4} Rd, imm 9.3.2 Arithmetic Operations Table 9-2. Arithmetic Operations Mnemonics Operands / Syntax Description Operation Rev abs C Rd Absolute value. Rd ← |Rd| 1 acr C Rd Add carry to register. Rd ← Rd + C 1 adc E Rd, Rx, Ry Add with carry. Rd ← Rx + Ry + C 1 C Rd, Rs Add. Rd ← Rd + Rs 1 E Rd, Rx, Ry > sa, bp Unsigned saturate from bit given by sa5 after a right shift of bp5 bit positions. Rd ← Sat((Rd >> sa5),bp5) 1 subhh.w E Rd, Rx:, Ry: Subtract signed halfwords. (32 ← 16 -16) Rd ← SE(Rx:) SE(Ry:) 1 108 AVR32 32000D–04/2011 AVR32 Table 9-4. DSP Operations (Continued) mulsathh.h E Rd, Rx:, Ry: Fractional signed multiply with saturation. Return halfword. (16 ← 16 x 16) Rd ← SE(Sat(Rx: *Ry: > 16) 1 mulsathh.w E Rd, Rx:, Ry: Fractional signed multiply with saturation. Return word. (32 ← 16 x 16) Rd ← Sat( Rx:*Ry: 16) 1 mulsatrndwh. w E Rd, Rx, Ry: Fractional signed multiply with rounding. Return word. (32 ← 32 x 16) Rd ← SE(( Sat(Rx*Ry: > 16) 1 mulsatwh.w E Rd, Rx, Ry: Fractional signed multiply with saturation. Return word. (32 ← 32 x 16) Rd ← Sat(Rx*Ry: >16 1 macsathh.w E Rd, Rx:, Ry: Fractional signed multiply accumulate with saturation. Return word. (32 ← 16 x 16 + 32) Rd ← Sat (Sat(Rx: *Ry: sa5) 1 C Rd, Rs E Rd, Rx, Ry > sa and{cond4} E Rd, Rx, Ry Logical AND if condition satisfied. if (cond4) Rd ← Rx ∧ Ry 2 andn C Rd, Rs Logical AND NOT. Rd ← Rd ∧ ¬Rs 1 E Rd, imm Logical AND High Halfword, low halfword is unchanged. Rd[31:16] ← Rd[31:16] ∧ imm16 1 E Rd, imm, COH Logical AND High Halfword, clear other halfword. Rd[31:16] ← Rd[31:16] ∧ imm16 Rd[15:0] ← 0 1 E Rd, imm Logical AND Low Halfword, high halfword is unchanged. Rd[15:0] ← Rd[15:0] ∧ imm16 1 E Rd, imm, COH Logical AND Low Halfword, clear other halfword. Rd[15:0] ← Rd[15:0] ∧ imm16 Rd[31:16] ← 0 1 C Rd One’s Complement (NOT). Rd ← ¬Rd 1 C Rd, Rs Rd ← Rd ⊕ Rs 1 E Rd, Rx, Ry sa Rd ← Rd ⊕ (Rs >> sa5) 1 eor{cond4} E Rd, Rx, Ry Logical EOR if condition satisfied. if (cond4) Rd ← Rx ⊕ Ry 2 eorh E Rd, imm Logical Exclusive OR (High Halfword). Rd[31:16] ← Rd[31:16] ⊕ imm16 1 eorl E Rd, imm Logical Exclusive OR (Low Halfword). Rd[15:0] ← Rd[15:0] ⊕ imm16 1 C Rd, Rs Rd ← Rd ∨ Rs 1 E Rd, Rx, Ry sa Rd ← Rd ∨ (Rs >> sa5) 1 or{cond4} E Rd, Rx, Ry Logical OR if condition satisfied. if (cond4) Rd ← Rx ∨ Ry 2 orh E Rd, imm Logical OR (High Halfword). Rd[31:16] ← Rd[31:16] ∨ imm16 1 orl E Rd, imm Logical OR (Low Halfword). Rd[15:0] ← Rd[15:0] ∨ imm16 1 tst C Rd, Rs Test register for zero. Rd ∧ Rs 1 110 AVR32 and Logical AND. andh andl com eor or Logical Exclusive OR. Logical (Inclusive) OR. 32000D–04/2011 AVR32 9.3.6 Bit Operations Table 9-6. Bit Operations Mnemonics Operands / Syntax Description Operation Rev bfexts E Rd, Rs, o5, w5 Extract and sign-extend the w5 bits in Rs starting at bit-offset o5 to Rd. See Instruction Set Reference 1 bfextu E Rd, Rs, o5, w5 Extract and zero-extend the w5 bits in Rs starting at bit-offset o5 to Rd. See Instruction Set Reference 1 bfins E Rd, Rs, o5, w5 Insert the lower w5 bits of Rs in Rd at bitoffset o5. See Instruction Set Reference 1 bld E Rd, bp Bit load. C ← Rd[bp5] Z ← Rd[bp5] 1 brev C Rd Bit reverse. Rd[0:31] ← Rd[31:0] 1 bst E Rd, bp Bit store. Rd[bp5] ← C 1 casts.b C Rd Typecast byte to signed word. Rd ← SE(Rd[7:0]) 1 casts.h C Rd Typecast halfword to signed word. Rd ← SE(Rd[15:0]) 1 castu.b C Rd Typecast byte to unsigned word. Rd ← ZE(Rd[7:0]) 1 castu.h C Rd Typecast halfword to unsigned word. Rd ← ZE(Rd[15:0]) 1 cbr C Rd, bp Clear bit in register. Rd[bp5] ← 0 1 clz E Rd, Rs Count leading zeros. See Instruction Set Reference 1 sbr C Rd, bp Set bit in register. Rd[bp5] ← 1 1 Swap bytes in register. Rd[31:24] ← Rd[7:0], Rd[23:16] ← Rd[15:8], Rd[15:8] ← Rd[23:16], Rd[7:0] ← Rd[31:24] 1 1 1 swap.b C Rd swap.bh C Rd Swap bytes in each halfword. Rd[31:24] ← Rd[23:16], Rd[23:16] ← Rd[31:24], Rd[15:8] ← Rd[7:0], Rd[7:0] ← Rd[15:8] swap.h C Rd Swap halfwords in register. Rd[31:16] ← Rd[15:0], Rd[15:0] ← Rd[31:16] 111 32000D–04/2011 9.3.7 Shift Operations Table 9-7. Operations Mnemonics Operands / Syntax Description Operation Rev E Rd, Rx, Ry E Rd, Rs, sa C Rd, sa 1 E Rd, Rx, Ry 1 E Rd, Rs, sa C Rd, sa 1 E Rd, Rx, Ry 1 E Rd, Rs, sa C Rd, sa rol C Rd Rotate left through carry. See Instruction Set Reference 1 ror C Rd Rotate right through carry. See Instruction Set Reference 1 112 AVR32 asr lsl lsr 1 Arithmetic shift right (signed) . Logical shift left. Logical shift right. See Instruction Set Reference See Instruction Set Reference See Instruction Set Reference 1 1 1 1 32000D–04/2011 AVR32 9.3.8 Instruction Flow Table 9-8. Instruction Flow Mnemonics Operands / Syntax Description Operation Rev if (cond3) PC ← PC + (SE(disp8)