ATWINC15x0
ATWINC15x0-MR210xB IEEE® 802.11 b/g/n SmartConnect
IoT Module
Introduction
The ATWINC15x0-MR210xB is a low power consumption 802.11 b/g/n IoT (Internet of Things)
module,specifically optimized for low power IoT applications. The module integrates Power Amplifier (PA),
Low-Noise Amplifier (LNA), Switch, Power Management, and a printed antenna or a micro co-ax (u.FL)
connector for an external antenna resulting in a small form factor (21.7 x 14.7 x 2.1 mm) design. It is
interoperable with various vendors’ 802.11 b/g/n access points. This module provides SPI ports to
interface with a host controller.
The references to the ATWINC15x0-MR210xB module include the module devices listed in the following:
•
ATWINC1500-MR210PB
•
ATWINC1500-MR210UB
•
ATWINC1510-MR210PB
•
ATWINC1510-MR210UB
Features
•
•
•
•
•
•
•
•
•
IEEE® 802.11 b/g/n 20 MHz (1x1) solution
Single spatial stream in 2.4 GHz ISM band
Integrated Transmit/Receive switch
Integrated PCB antenna or u.FL micro co-ax connector for external antenna
Superior sensitivity and range via advanced PHY signal processing
Advanced equalization and channel estimation
Advanced carrier and timing synchronization
Wi-Fi® Direct (supported till firmware release 19.5.2)
Soft-AP support
•
•
Supports IEEE 802.11 WEP, WPA, WPA2 security
Support Enterprise security with WPA/WPA2 (802.1X)(1)
– EAP-TLS
– EAP-PEAPv0/1 with TLS
– EAP-TTLSv0 with MSCHAPv2
– EAP-PEAPv0/1 with MSCHAPv2
Superior MAC throughput via hardware accelerated two-level A-MSDU/A-MPDU frame aggregation
and block acknowledgment
On-chip memory management engine to reduce host load
SPI host interface
•
•
•
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 1
ATWINC15x0
•
•
•
•
•
•
•
•
•
•
•
Operating temperature range from -40°C to +85°C. RF performance at room temperature of 25oC with
a 2-3 db change at boundary conditions
I/O operating voltage of 2.7V to 3.6V
Built-in 26 MHz crystal
Integrated Flash memory for system software
Power Save modes
– 4 µA Power-Down mode typical at 3.3V I/O
– 380 µA Doze mode with chip settings preserved (used for beacon monitoring)(2)
– On-chip low power sleep oscillator
– Fast host wake-up from Doze mode by a pin or SPI transaction
Fast Boot options
– On-chip boot ROM (Firmware instant boot)
– SPI flash boot
– Low-leakage on-chip memory for state variables
– Fast AP re-association (150 ms)
On-chip Network stack to offload MCU
– Integrated Network IP stack to minimize host CPU requirements
– Network features TCP, UDP, DHCP, ARP, HTTP, TLS, and DNS
– Hardware accelerators for Wi-Fi and TLS security to improve connection time
Hardware accelerator for IP checksum
Hardware accelerators for OTA security
Small footprint host driver
Wi-Fi Alliance® certifications for Connectivity and Optimizations
– ID: WFA61069
Note:
1. For more information on software feature, refer to Wi-Fi Network Controller Software Design Guide
(DS00002389).
2. For information on module power modes, refer to Power Consumption.
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 2
Table of Contents
1. Ordering Information and Module Marking................................................................ 5
2. Block Diagram........................................................................................................... 7
3. Pin Description.......................................................................................................... 8
4. Electrical Specifications...........................................................................................10
4.1.
4.2.
Absolute Maximum Ratings........................................................................................................10
Recommended Operating Conditions........................................................................................ 10
5. CPU and Memory Subsystems................................................................................11
5.1.
5.2.
5.3.
Processor................................................................................................................................... 11
Memory Subsystem....................................................................................................................11
Non-volatile Memory (eFuse)..................................................................................................... 11
6. WLAN Subsystem................................................................................................... 13
6.1.
6.2.
6.3.
MAC........................................................................................................................................... 13
PHY............................................................................................................................................ 14
Radio.......................................................................................................................................... 14
7. External Interfaces...................................................................................................18
7.1.
7.2.
7.3.
Interfacing with the Host Microcontroller.................................................................................... 18
SPI Interface...............................................................................................................................19
UART Interface...........................................................................................................................21
8. Power Consumption................................................................................................ 23
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
Description of Device States...................................................................................................... 23
Current Consumption in Various Device States......................................................................... 23
Restrictions for Power States..................................................................................................... 24
Power-up/down Sequence......................................................................................................... 24
Digital I/O Pin Behavior During Power-up Sequences............................................................... 25
Module Reset............................................................................................................................. 26
9. Notes On Interfacing to the ATWINC15x0-MR210xB.............................................. 27
9.1.
Programmable Pull Up Resistors............................................................................................... 27
10. Schematic Design Information.................................................................................28
10.1. Application Schematic................................................................................................................ 28
11. Module Drawing.......................................................................................................29
11.1. Module Footprint........................................................................................................................ 30
12. Design Considerations............................................................................................ 32
12.1. ATWINC15x0-MR210PB Placement and Routing Guidelines....................................................32
12.2. Printed PCB Antenna Performance of ATWINC15x0-MR210PB............................................... 32
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 3
ATWINC15x0
12.3. ATWINC15x0-MR210UB Placement and Routing Guidelines................................................... 35
12.4. Module Assembly Considerations.............................................................................................. 36
13. Reflow Profile Information....................................................................................... 37
13.1.
13.2.
13.3.
13.4.
Storage Condition.......................................................................................................................37
Printing Process......................................................................................................................... 37
Baking Conditions...................................................................................................................... 37
Soldering and Reflow Condition................................................................................................. 37
14. Regulatory Approval................................................................................................ 40
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
14.8.
United States..............................................................................................................................41
Canada.......................................................................................................................................43
Europe........................................................................................................................................45
Japan..........................................................................................................................................47
Korea..........................................................................................................................................48
Taiwan........................................................................................................................................ 48
China.......................................................................................................................................... 49
Other Regulatory Information..................................................................................................... 50
15. Reference Documentation and Support.................................................................. 51
15.1. Reference Documents................................................................................................................51
16. Document Revision History..................................................................................... 52
The Microchip Web Site................................................................................................ 56
Customer Change Notification Service..........................................................................56
Customer Support......................................................................................................... 56
Microchip Devices Code Protection Feature................................................................. 56
Legal Notice...................................................................................................................57
Trademarks................................................................................................................... 57
Quality Management System Certified by DNV.............................................................58
Worldwide Sales and Service........................................................................................59
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 4
ATWINC15x0
Ordering Information and Module Marking
1.
Ordering Information and Module Marking
Following table describes the ordering details for the ATWINC15x0-MR210xB modules.
Table 1-1. Ordering Details
Model Number
Ordering
Code1
Package
Dimension
No. Description
of
Pins
Regulatory
Certification
ATWINC1500MR210PB
ATWINC1500MR210PBXXXX
21.7 x 14.7 x 2.1
mm
28
Certified Module with
ATWINC1500B chip
(4Mb Flash) and PCB
printed antenna
FCC, ISED,
CE, MIC,
KCC, NCC,
SRRC
ATWINC1500MR210UB
ATWINC1500MR210UBXXXX
21.7 x 14.7 x 2.1
mm
28
Certified Module with
ATWINC1500B chip
(4Mb Flash) and u.FL
connector
FCC, ISED,
CE
ATWINC1510MR210PB
ATWINC1510MR210PBXXXX
21.7 x 14.7 x 2.1
mm
28
Certified Module with
ATWINC1510B chip
(8Mb Flash) and PCB
printed antenna
FCC, ISED,
CE, MIC,
KCC, NCC,
SRRC
ATWINC1510MR210UB
ATWINC1510MR210UBXXXX
21.7 x 14.7 x 2.1
mm
28
Certified Module with
ATWINC1510B chip
(8Mb Flash) and u.FL
connector
FCC, ISED,
CE
Note:
1. XXXX in the Ordering code represents the Firmware version of the product. For more details, refer
to the Software Release Notes available on the Microchip web page.
Following figure illustrates the ATWINC15x0-MR210xB modules’ marking information.
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 5
ATWINC15x0
Ordering Information and Module Marking
Figure 1-1. Marking Information
ATWINC15x0 -
MR
ATWINC1500: 4Mb Flash
ATWINC1510: 8Mb Flash
2
1
0
Software Version
Reserved
1 0
MR Industrial
Module Revision Letter
P: PCB Antenna
U: uFL Connector
1: No OTA / with shield
2: OTA with shield
© 2018 Microchip Technology Inc.
P
Datasheet
DS70005304C-page 6
ATWINC15x0
Block Diagram
2.
Block Diagram
Figure 2-1. ATWINC15x0-MR210xB Module Block Diagram
Printed 2.4 GHz Antenna
or
u.FL 2.4 GHz External
Antenna Connector
VBAT
VDDIO
SPI_CFG
SPI
RX/TX
BAL UN
Wi-Fi ®
ATWINC15x0
SoC
GPIO 3
GPIO 4
GPIO 5
GPIO 6
IRQN
Chip_EN
WAKE
26 MHz crystal
RESET
GN D
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 7
ATWINC15x0
Pin Description
Pin Description
Figure 3-1. Pin Diagram
ATWINC15x0-MR210
9
8
GND_2
IRQN
12
UART_TXD
14
15
7
NC
NC
6
NC
5
NC
4
RESET_N
3
2
1
I2C_SCL
I2C_SDA
GPIO_6
GND_3
27
GND_1
28
23
VDDIO
1P3V_TP
GPIO_5
22
CHIP_EN
UART_RXD
18
19
21
SPI_SCK
16
17
GPIO_1
SPI_SSN
SPI_MISO
13
20
SPI_MOSI
29
PADDLE
GND
(Bottom)
GPIO_3
GPIO_4
WAKE
10
11
24
25
26
SPI_CFG
VBAT
3.
Table 3-1. ATWINC15x0-MR210xB Pin Description
Pin
#
Name
Type
Description
1
GPIO_6
I/O
General purpose I/O.
Yes
2
I2C_SCL
I/O
I2C Slave Clock. Currently used only for development
debug. Leave unconnected.
Yes
3
I2C_SDA
I/O
I2C Slave Data. Currently used only for development
debug. Leave unconnected.
Yes
4
RESET_N
I
Active-Low Hard Reset. When this pin is asserted
low, the module will be placed in the reset state.
When this pin is asserted high, the module will be out
of reset and will function normally. Connect to a host
output that defaults low at power up. If the host output
is tri-stated, add a 1 MΩ pull down resistor to ensure
a low level at power-up.
No
5
NC
-
No connect.
© 2018 Microchip Technology Inc.
Programmable
Pull Up Resistor
-
Datasheet
DS70005304C-page 8
ATWINC15x0
Pin Description
Pin
#
Name
Type
Description
Programmable
Pull Up Resistor
6
NC
-
No connect.
-
7
NC
-
No connect.
-
8
NC
-
No connect.
-
9
GND_1
-
GND.
-
10
SPI_CFG
I
Tie to VDDIO through a 1 MΩ resistor to enable the
SPI interface.
No
11
WAKE
I
Host Wake control. Can be used to wake-up the
module from Doze mode. Connect to a host GPIO.
Yes
12
GND_2
-
GND.
13
IRQN
O
ATWINC15x0-MR210xB Device Interrupt output.
Connect to host interrupt input pin.
Yes
14
UART_TXD
O
UART Transmit Output from ATWINC15x0-MR210xB
Added debug.
Yes
15
SPI_RXD
I
SPI MOSI (Master Out, Slave In) pin.
Yes
16
SPI_SSN
I
SPI Slave Select. Active-low.
Yes
17
SPI_TXD
O
SPI MISO (Master In, Slave Out) pin.
Yes
18
SPI_SCK
I
SPI Clock.
Yes
19
UART_RXD
I
UART Receive input to ATWINC15x0-MR210xB.
Added debug.
Yes
20
VBATT
-
Battery power supply.
21
GPIO_1/RTC
I
General Purpose I/O / RTC.
Yes
22
CHIP_EN
I
Module enable. High level enables the module; low
level places module in Power-Down mode. Connect
to a host output that defaults low at power-up. If the
host output is tri-stated, add a 1 MΩ pull down
resistor to ensure a low level at power-up.
No
23
VDDIO
-
I/O Power Supply. Must match host I/O voltage.
-
24
1P3V_TP
-
1.3V VDD Core Test Point. Decouple with 10 µF, and
0.01 µF to GND.
-
25
GPIO_3
I/O
General purpose I/O.
Yes
26
GPIO_4
I/O
General purpose I/O.
Yes
27
GPIO_5
I/O
General purpose I/O.
Yes
28
GND_3
-
GND.
-
29
PADDLE GND -
GND.
-
© 2018 Microchip Technology Inc.
-
Datasheet
-
DS70005304C-page 9
ATWINC15x0
Electrical Specifications
4.
Electrical Specifications
4.1
Absolute Maximum Ratings
Absolute maximum ratings for the ATWINC15x0-MR210xB modules are listed below.
Table 4-1. Conditions
Symbol
Description
Min.
Max.
Unit
VBATT
Input supply voltage
-0.3
5.0
V
VDDIO
I/O voltage
-0.3
4.2
V
-40
+85
oC
Operating Temperature
CAUTION
4.2
Stresses listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only. The functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect the device reliability.
Recommended Operating Conditions
Table 4-2. Recommended Operating Conditions
Symbol
Min.
Typ.
Max.
Unit
VBATT
3.0
3.3
4.2
V
VDDIO
2.7
3.3
3.6
V
Note: 1. Test Conditions: -40oC - +85oC
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 10
ATWINC15x0
CPU and Memory Subsystems
5.
CPU and Memory Subsystems
5.1
Processor
The ATWINC15x0-MR210xB modules have a Cortus APS3 32-bit processor. This processor performs
many of the MAC functions, including but not limited to the association, authentication, power
management, security key management, and MSDU aggregation/de-aggregation. In addition, the
processor provides flexibility for various modes of operation, such as STA and AP modes.
5.2
Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 160KB instruction RAM and a 64KB
data RAM. The ATWINC15x0-MR210xB modules come populated with either 4Mb or 8Mb of Flash
memory depending on the module model that is ordered. This memory can be used for system software.
See Table 1-1 for more information. In addition, the device uses a 128KB shared RAM, accessible by the
processor and MAC, which allows the APS3 core to perform various data management tasks on the TX
and RX data packets.
5.3
Non-volatile Memory (eFuse)
The ATWINC15x0-MR210xB modules have 768 bits of non-volatile eFuse memory that can be read by
the CPU after device reset. This non-volatile one-time-programmable (OTP) memory can be used to store
customer-specific parameters, such as MAC address; various calibration information, such as TX power,
crystal frequency offset, etc.; and other software-specific configuration parameters. The eFuse is
partitioned into six 128-bit banks. Each bank has the same bitmap (see following figure). The purpose of
the first 80 bits in each bank is fixed, and the remaining 48 bits are general-purpose software dependent
bits, or reserved for future use. Since each bank can be programmed independently, this allows for
several updates of the device parameters following the initial programming; for example, if the MAC
address has to be changed, Bank 1 has to be programmed with the new MAC address along with the
values of TX gain correction and frequency offset if they are used and programmed in Bank 0. The
contents of Bank 0 have to be invalidated in this case by programming the invalid bit in the Bank 0. This
will allow the firmware to use the MAC address. By default, all the ATWINC15x0-MR210xB modules are
programmed with the MAC address and the frequency offset bits of Bank 0.
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 11
ATWINC15x0
CPU and Memory Subsystems
Figure 5-1. eFuse Bitmap
Flags
8
Bank 0
F
48
MAC ADDR
TX
Gain
Correc
tion
8
G
1
15
Freq.
Offset
7
Used
1
Used
1
MAC ADDR
Used
4
Reserved
3
Version
1
Invalid
Used
1
16
FO
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
128 Bits
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 12
ATWINC15x0
WLAN Subsystem
6.
WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY).
The following two subsections describe the MAC and PHY in detail.
6.1
MAC
6.1.1
Description
The ATWINC15x0-MR210xB MAC is designed to operate at low power while providing high data
throughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath
engines, hardwired control logic, and a low-power, high-efficiency microprocessor. The combination of
dedicated logic with a programmable processor provides optimal power efficiency and real-time response
while providing the flexibility to accommodate evolving standards and future feature enhancements.
Dedicated datapath engines are used to implement datapath functions with heavy computational
requirements. For example, an FCS engine checks the CRC of the transmitting and receiving packets,
and a cipher engine performs all the required encryption and decryption operations for the WEP, WPATKIP, and WPA2 CCMP-AES.
Control functions which have real-time requirements are implemented using hardwired control logic
modules. These logic modules offer real-time response while maintaining configurability via the
processor. Examples of hardwired control logic modules are the channel access control module
(implements EDCA/HCCA, Beacon TX control, interframe spacing, etc.), protocol timer module
(responsible for the Network Access Vector, back-off timing, timing synchronization function, and slot
management), MPDU handling module, aggregation/de-aggregation module, block ACK controller
(implements the protocol requirements for burst block communication), and TX/RX control FSMs
(coordinate data movement between PHY-MAC interface, cipher engine, and the DMA interface to the
TX/RX FIFOs).
The MAC functions implemented solely in software on the microprocessor have the following
characteristics:
•
•
•
6.1.2
Functions with high memory requirements or complex data structures. Examples are association
table management and power save queuing.
Functions with low computational load or without critical real-time requirements. Examples are
authentication and association.
Functions which need flexibility and upgradeability. Examples are beacon frame processing and
QoS scheduling.
Features
The ATWINC15x0-MR210xB IEEE802.11 MAC supports the following functions:
•
•
•
IEEE 802.11b/g/n
IEEE 802.11e WMM QoS EDCA/PCF multiple access categories traffic scheduling
Advanced IEEE 802.11n features:
– Transmission and reception of aggregated MPDUs (A-MPDU)
– Transmission and reception of aggregated MSDUs (A-MSDU)
– Immediate Block Acknowledgment
– Reduced Interframe Spacing (RIFS)
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 13
ATWINC15x0
WLAN Subsystem
•
•
•
•
Support for IEEE802.11i and WFA security with key management:
– WEP 64/128
– WPA-TKIP
– 128-bit WPA2 CCMP (AES)
Advanced power management:
– Standard 802.11 Power Save Mode
RTS-CTS and CTS-self support
Supports either STA or AP mode in the infrastructure basic service set mode
6.2
PHY
6.2.1
Description
The ATWINC1500B WLAN PHY is designed to achieve reliable and power-efficient physical layer
communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced
algorithms have been employed to achieve maximum throughput in a real world communication
environment with impairments and interference. The PHY implements all the required functions that
include FFT, filtering, FEC (Viterbi decoder), frequency, timing acquisition and tracking, channel
estimation and equalization, carrier sensing, clear channel assessment, and automatic gain control.
6.2.2
Features
The ATWINC1500B IEEE802.11 PHY supports the following functions:
•
•
•
•
•
•
•
6.3
Single antenna 1x1 stream in 20MHz channels
Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps
Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2,
13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps
IEEE 802.11n mixed mode operation
Per packet TX power control
Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery,
and frame detection
Radio
This section presents information describing the properties and characteristics of the ATWINC15x0MR210xB and Wi-Fi radio transmit and receive performance capabilities of the device.
The performance measurements are taken at the RF pin assuming 50Ω impedance; the RF performance
is guaranteed for room temperature of 25oC with a derating of 2-3dB at boundary conditions.
Measurements were taken under typical conditions: VBATT=3.3V; VDDIO=3.3V; temperature: +25ºC
Table 6-1. Features and Properties
Feature
Description
Part Number
ATWINC15x0-MR210xB
WLAN Standard
IEEE 802.11 b/g/n, Wi-Fi compliant
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 14
ATWINC15x0
WLAN Subsystem
Feature
Description
Host Interface
SPI
Dimension
21.7 x 14.7 x 2.1 mm
Frequency Range
2.412GHz ~ 2.472GHz (2.4GHz ISM Band)
Number of Channels
11 for North America, and 13 for Europe
Modulation
802.11b: DQPSK, DBPSK, CCK
802.11g/n: OFDM /64-QAM,16-QAM, QPSK, BPSK
Data Rate
802.11b: 1, 2, 5.5, 11Mbps
802.11g: 6, 9, 12, 18, 24, 36, 48, 54Mbps
6.3.1
Data Rate
(20MHz, normal GI, 800ns)
802.11n: 6.5, 13, 19.5, 26, 39, 52, 58.5, 65Mbps
Data Rate
(20MHz, short GI, 400ns)
802.11n: 7.2, 14.4, 21.7, 28.9, 43.3, 57.8,
65,72.2Mbps
Operating temperature
-40 to +85oC
Storage temperature
-40 to +125 oC
Humidity
Operating Humidity 10% to 95% Non-Condensing
Storage Humidity 5% to 95% Non-Condensing
Receiver Performance
Table 6-2. Receiver Performance
Parameter
Description
Minimum
Frequency
© 2018 Microchip Technology Inc.
2,412
Datasheet
Typical
Maximum
Unit
2,472
MHz
DS70005304C-page 15
ATWINC15x0
WLAN Subsystem
Parameter
Sensitivity
802.11b
Sensitivity
802.11g
Sensitivity
802.11n
(BW=20MHz)
Maximum Receive
Signal Level
Adjacent Channel
Rejection
Description
Minimum
Typical
1Mbps DSS
-95
2Mbps DSS
-90
5.5Mbps DSS
-92
11Mbps DSS
-86
6Mbps OFDM
-90
9Mbps OFDM
-89
12Mbps OFDM
-88
18Mbps OFDM
-85
24Mbps OFDM
-83
36Mbps OFDM
-80
48Mbps OFDM
-76
54Mbps OFDM
-74
MCS 0
-89
MCS 1
-87
MCS 2
-85
MCS 3
-82
MCS 4
-77
MCS 5
-74
MCS 6
-72
MCS 7
-70.5
1-11Mbps DSS
0
6-54Mbps OFDM
0
MCS 0 – 7
0
1Mbps DSS (30MHz offset)
50
11Mbps DSS (25MHz offset)
43
6Mbps OFDM (25MHz offset)
40
54Mbps OFDM (25MHz offset)
25
MCS 0 – 20MHz BW (25MHz offset)
40
MCS 7 – 20MHz BW (25MHz offset)
20
© 2018 Microchip Technology Inc.
Datasheet
Maximum
Unit
dBm
dB
DS70005304C-page 16
ATWINC15x0
WLAN Subsystem
Parameter
Cellular Blocker
Immunity
6.3.2
Description
Minimum
Typical
776-794MHz CDMA
-14
824-849MHz GSM
-10
880-915MHz GSM
-10
1710-1785MHz GSM
-15
1850-1910MHz GSM
-15
1850-1910MHz WCDMA
-24
1920-1980MHz WCDMA
-24
Maximum
Unit
dBm
Transmitter Performance
Table 6-3. Transmitter Performance
Parameter
Description
Minimum
Typical
Maximum
Unit
Frequency
—
2,412
—
2,472
MHz
802.11b 1Mbps
—
17.5
—
802.11b 11Mbps
—
18.5
—
802.11g 6Mbps
—
17.5
—
802.11g 54Mbps
—
16
—
802.11n MCS 0
—
17.0
—
802.11n MCS 7
—
14.5
—
TX Power Accuracy
—
—
±1.5 2
—
dB
Carrier Suppression
—
—
30.0
—
dBc
2nd
—
3rd
—
Output Power1-2
ON_Transmit
Harmonic Output Power
-41
—
-41
dBm
dBm/MHz
Note:
1. Measured at 802.11 spec compliant EVM/Spectral Mask.
2. Measured after RF matching network.
3. Operating temperature range is -40°C to +85°C. RF performance guaranteed at room temperature
of 25°C with a 2-3dB change at boundary conditions.
4. With respect to TX power, different (higher/lower) RF output power settings may be used for
specific antennas and/or enclosures, in which case recertification may be required.
5. The availability of some specific channels and/or operational frequency bands are country
dependent and should be programmed at the Host product factory to match the intended
destination. Regulatory bodies prohibit exposing the settings to the end user. This requirement
needs to be taken care of via Host implementation.
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 17
ATWINC15x0
External Interfaces
7.
External Interfaces
7.1
Interfacing with the Host Microcontroller
This section describes interfacing the ATWINC15x0-MR210xB module with the host microcontroller. The
interface is comprised of a slave SPI and additional control signals, as shown in the following figure. For
more information on SPI interface specification and timing, refer to the SPI Interface. Additional control
signals are connected to the GPIO/IRQ interface of the microcontroller.
Figure 7-1. Interfacing with Host Microcontroller
CHIP_EN
RESET
WAKE
Host
Microcontroller
Wi-Fi Controller
Module
SPI
IRQN
Table 7-1. Host Microcontroller Interface Pins
Pin Number
Function
4
RESET_N
11
WAKE
13
IRQ_N
22
CHIP_EN
16
SPI_SSN
15
SPI_MOSI
17
SPI_MISO
18
SPI_SCK
Related Links
7.2 SPI Interface
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 18
ATWINC15x0
External Interfaces
7.2
SPI Interface
7.2.1
Overview
The ATWINC15x0-MR210xB has a Serial Peripheral Interface (SPI) that operates as an SPI slave. The
SPI interface can be used for control and for serial I/O of 802.11 data. The SPI pins are mapped as
shown in the following table. The SPI is a full-duplex slave-synchronous serial interface that is available
immediately following reset when pin 10 (SPI_CFG) is tied to VDDIO.
Table 7-2. SPI Interface Pin Mapping
Pin #
SPI function
10
CFG: Must be tied to VDDIO
16
SSN: Active-Low Slave Select
15
MOSI(RXD): Serial Data Receive
18
SCK: Serial Clock
17
MISO(TXD): Serial Data Transmit
When the SPI is not selected, that is, when SSN is high, the SPI interface will not interfere with data
transfers between the serial-master and other serial-slave devices. When the serial slave is not selected,
its transmitted data output is buffered, resulting in a high impedance drive onto the MISO line.
The SPI interface responds to a protocol that allows an external host to read or write any register in the
chip as well as initiate DMA transfers.
The SPI SSN, MOSI, MISO, and SCK pins of the ATWINC15x0-MR210xB have internal programmable
pull-up resistors. These resistors should be programmed to be disabled; otherwise, if any of the SPI pins
are driven to a low level while the ATWINC15x0-MR210xB is in the low power sleep state, the current will
flow from the VDDIO supply through the pull-up resistors, increasing the current consumption of the
module.
Related Links
9.1 Programmable Pull Up Resistors
7.2.2
SPI Timing
The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and
Clock Phase (CPHA) settings. These modes are illustrated in the following table and figure.
Table 7-3. SPI Slave Modes
Mode
CPOL
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
Note: The ATWINC15x0 firmware uses “SPI MODE 0” to communicate with the host.
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 19
ATWINC15x0
External Interfaces
The red lines in the following figure correspond to Clock Phase = 0 and the blue lines correspond to Clock
Phase = 1.
Figure 7-2. SPI Slave Clock Polarity and Clock Phase Timing
CPOL = 0
SCK
CPOL = 1
SSN
RXD/TXD
(MOSI/MISO)
z
CPHA = 0
1
2
z
CPHA = 1
1
3
2
4
5
3
4
6
5
7
6
8
7
z
8
z
The SPI timing is provided in the following figure and table.
Figure 7-3. SPI Timing Diagram (SPI Mode CPOL=0, CPHA=0)
f SCK
t LH
t WH
SCK
t WL
t HL
TXD
t ODLY
RXD
t ISU
t IHD
SSN
t SUSSN
Table 7-4. SPI Slave Timing
Parameter
Symbol
Clock Input Frequency2
fSCK
© 2018 Microchip Technology Inc.
t HDSSN
Parameters1
Min.
Max.
—
Datasheet
Units
48
MHz
DS70005304C-page 20
ATWINC15x0
External Interfaces
Parameter
Symbol
Min.
Max.
Units
Clock Low Pulse Width
tWL
4
—
Clock High Pulse Width
tWH
5
—
Clock Rise Time
tLH
0
7
Clock Fall Time
tHL
0
7
TXD Output Delay3
tODLY
4
9 from SCK fall
12.5 from SCK
rise
RXD Input Setup Time
tISU
1
—
RXD Input Hold Time
tIHD
5
—
SSN Input Setup Time
tSUSSN
3
—
SSN Input Hold Time
tHDSSN
5.5
—
ns
Note:
1. Timing is applicable to all SPI modes
2. Maximum clock frequency specified is limited by the SPI Slave interface internal design, actual
maximum clock frequency can be lower and depends on the specific PCB layout
3. Timing based on 15pF output loading
7.3
UART Interface
The ATWINC15x0-MR210xB supports the Universal Asynchronous Receiver/Transmitter (UART)
interface. This interface should be used for debug purposes only. The UART is available on pins 14 and
19. The UART is compatible with the RS-232 standard, and the ATWINC15x0-MR210xB operates as
Data Terminal Equipment (DTE). It has a two-pin RXD/TXD interface.
The default configuration for accessing the UART interface of ATWINC15x0-MR210xB is mentioned
below:
•
Baud rate: 115200
•
Data: 8 bit
•
Parity: None
•
Stop bit: 1 bit
•
Flow control: None
It also has RX and TX FIFOs, which ensure reliable high-speed reception and low software overhead
transmission. FIFO size is 4 x 8 for both RX and TX direction. The UART also has status registers
showing the number of received characters available in the FIFO and various error conditions, as well the
ability to generate interrupts based on these status bits.
An example of the UART receiving or transmitting a single packet is shown in the following figure. This
example shows 7-bit data (0x45), odd parity, and two stop bits.
© 2018 Microchip Technology Inc.
Datasheet
DS70005304C-page 21
ATWINC15x0
External Interfaces
Important: UART2 supports RTS and CTS flow control. The UART RTS and UART CTS
MUST be connected to the host MCU UART and enabled for the UART interface to be
functional.
Figure 7-4. Example of UART RX of TX Packet
Previous
Packets or
Leading
Idle Bits
© 2018 Microchip Technology Inc.
Current Packet
Next
Packet
Data
Parity
Bit
Start
Bit
Datasheet
Stop Bits
DS70005304C-page 22
ATWINC15x0
Power Consumption
8.
Power Consumption
8.1
Description of Device States
The ATWINC15x0-MR210xB has several device states:
•
•
•
•
•
ON_Transmit – Device is actively transmitting an 802.11 signal. Highest output power and nominal
current consumption.
ON_Receive – Device is actively receiving an 802.11 signal. Lowest sensitivity and nominal current
consumption.
ON_Doze – Device is ON but is neither transmitting nor receiving
Power_Down – Device core supply off (Leakage)
IDLE connect – Device is connected with 1 DTIM beacon interval
The following pins are used to switch between the ON and Power_Down states:
•
•
8.2
CHIP_EN – Device pin (pin #22) used to enable DC/DC Converter
VDDIO – I/O supply voltage from external supply
In the ON states, VDDIO is on and CHIP_EN is high (at VDDIO voltage level). To switch between
the ON states and Power_Down state CHIP_EN has to change between high and low (GND)
voltage. When VDDIO is off and CHIP_EN is low, the chip is powered off with no leakage (also see
Restrictions for Power States).
Current Consumption in Various Device States
Table 8-1. Current Consumption
Device State
ON_Transmit
ON_Receive
© 2018 Microchip Technology Inc.
Code Rate
Output
power, dBm
Current Consumption 1
802.11b 1Mbps
17.5
268mA
22mA
802.11b 11Mbps
18.5
264mA
22mA
802.11g 6Mbps
17.5
269mA
22mA
802.11g 54Mbps
16.0
266mA
22mA
802.11n MCS 0
17.0
268mA
22mA
802.11n MCS 7
14.5
265mA
22mA
802.11b 1Mbps
N/A
61mA
22mA
802.11b 11Mbps
N/A
61mA
22mA
802.11g 6Mbps
N/A
61mA
22mA
802.11g 54Mbps
N/A
61mA
22mA
802.11n MCS 0
N/A
61mA
22mA
802.11n MCS 7
N/A
61mA
22mA
Datasheet
IVBATT
IVDDIO
DS70005304C-page 23
ATWINC15x0
Power Consumption
Device State
Code Rate
Output
power, dBm
Current Consumption 1
ON_Doze
N/A
N/A
380µA
工商网监
湘ICP备2023018690号
