ATxmega128/64/32/16A4U
AVR® XMEGA® Data Sheet
Introduction
The Microchip AVR® XMEGA® is a family of low power, high performance, and peripheral rich 8/16-bit
microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single
clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per
second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus
processing speed.
Features
• High-performance, low-power Microchip AVR® XMEGA® 8/16-bit Microcontroller
• Nonvolatile program and data memories
- 16K - 128KB of in-system self-programmable flash
- 4K - 8KB boot section
- 1K - 2KB EEPROM
- 2K - 8KB internal SRAM
• Peripheral Features
- Four-channel DMA controller
- Eight-channel event system
- Five 16-bit timer/counters
• Three timer/counters with 4 output compare or input capture channels
• Two timer/counters with 2 output compare or input capture channels
• High-resolution extensions on all timer/counters
• Advanced waveform extension (AWeX) on one timer/counter
- One USB device interface
• USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
• 32 Endpoints with full configuration flexibility
- Five USARTs with IrDA support for one USART
- Two Two-wire interfaces with dual address match (I2C and SMBus compatible)
- Two serial peripheral interfaces (SPIs)
- AES and DES crypto engine
- CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
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ATxmega128/64/32/16A4U
- 16-bit real time counter (RTC) with separate oscillator
- One twelve-channel, 12-bit, 2msps Analog to Digital Converter
- One two-channel, 12-bit, 1msps Digital to Analog Converter
- Two Analog Comparators with window compare function, and current sources
- External interrupts on all general purpose I/O pins
- Programmable watchdog timer with separate on-chip ultra low power oscillator
- QTouch® library support
• Capacitive touch buttons, sliders and wheels
• Special microcontroller features
- Power-on reset and programmable brown-out detection
- Internal and external clock options with PLL and prescaler
- Programmable multilevel interrupt controller
- Five sleep modes
- Programming and debug interfaces
• PDI (program and debug interface)
• I/O and packages
- 34 Programmable I/O pins
- 44 - lead TQFP
- 44 - pad VQFN
- 49 - ball VFBGA
• Operating voltage
- 1.6 – 3.6V
• Operating frequency
- 0 – 12MHz from 1.6V
- 0 – 32MHz from 2.7V
2011-2020 Microchip Technology Inc.
Data Sheet Complete
DS40002166A-page 2
ATxmega128/64/32/16A4U
Table of Contents
1
Ordering Information ............................................................................... 8
2
Pinout/Block Diagram ............................................................................ 10
3
Overview ................................................................................................. 12
3.1
4
Block Diagram ................................................................................................. 13
Resources ............................................................................................... 14
4.1
Recommended reading ................................................................................... 14
5
Capacitive touch sensing ...................................................................... 14
6
AVR CPU ................................................................................................. 15
7
8
6.1
Features .......................................................................................................... 15
6.2
Overview.......................................................................................................... 15
6.3
Architectural Overview..................................................................................... 15
6.4
ALU - Arithmetic Logic Unit ............................................................................. 16
6.5
Program Flow .................................................................................................. 17
6.6
Status Register ................................................................................................ 17
6.7
Stack and Stack Pointer .................................................................................. 17
6.8
Register File .................................................................................................... 18
Memories ................................................................................................ 19
7.1
Features .......................................................................................................... 19
7.2
Overview.......................................................................................................... 19
7.3
Flash Program Memory ................................................................................... 20
7.4
Fuses and Lock bits......................................................................................... 21
7.5
Data Memory ................................................................................................... 21
7.6
EEPROM ......................................................................................................... 22
7.7
I/O Memory...................................................................................................... 22
7.8
Data Memory and Bus Arbitration ................................................................... 23
7.9
Memory Timing ................................................................................................ 23
7.10
Device ID and Revision ................................................................................... 23
7.11
I/O Memory Protection..................................................................................... 23
7.12
Flash and EEPROM Page Size....................................................................... 23
DMAC – Direct Memory Access Controller .......................................... 25
8.1
Features .......................................................................................................... 25
8.2
Overview.......................................................................................................... 25
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ATxmega128/64/32/16A4U
9
Event System .......................................................................................... 26
9.1
Features .......................................................................................................... 26
9.2
Overview.......................................................................................................... 26
10 System Clock and Clock options ......................................................... 27
10.1
Features .......................................................................................................... 27
10.2
Overview.......................................................................................................... 27
10.3
Clock Sources ................................................................................................. 28
11 Power Management and Sleep Modes ................................................. 30
11.1
Features .......................................................................................................... 30
11.2
Overview.......................................................................................................... 30
11.3
Sleep Modes.................................................................................................... 30
12 System Control and Reset .................................................................... 32
12.1
Features .......................................................................................................... 32
12.2
Overview.......................................................................................................... 32
12.3
Reset Sequence .............................................................................................. 32
12.4
Reset Sources ................................................................................................. 32
13 WDT – Watchdog Timer ......................................................................... 34
13.1
Features .......................................................................................................... 34
13.2
Overview.......................................................................................................... 34
14 Interrupts and Programmable Multilevel Interrupt Controller ........... 35
14.1
Features .......................................................................................................... 35
14.2
Overview.......................................................................................................... 35
14.3
Interrupt vectors............................................................................................... 35
15 I/O Ports .................................................................................................. 37
15.1
Features .......................................................................................................... 37
15.2
Overview.......................................................................................................... 37
15.3
Output Driver ................................................................................................... 37
15.4
Input sensing ................................................................................................... 40
15.5
Alternate Port Functions .................................................................................. 40
16 TC0/1 – 16-bit Timer/Counter Type 0 and 1 ......................................... 41
16.1
Features .......................................................................................................... 41
16.2
Overview.......................................................................................................... 41
17 TC2 - Timer/Counter Type 2 .................................................................. 43
17.1
Features .......................................................................................................... 43
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ATxmega128/64/32/16A4U
17.2
Overview.......................................................................................................... 43
18 AWeX – Advanced Waveform Extension ............................................. 44
18.1
Features .......................................................................................................... 44
18.2
Overview.......................................................................................................... 44
19 Hi-Res – High Resolution Extension .................................................... 45
19.1
Features .......................................................................................................... 45
19.2
Overview.......................................................................................................... 45
20 RTC – 16-bit Real-Time Counter ........................................................... 46
20.1
Features .......................................................................................................... 46
20.2
Overview.......................................................................................................... 46
21 USB – Universal Serial Bus Interface ................................................... 47
21.1
Features .......................................................................................................... 47
21.2
Overview.......................................................................................................... 47
22 TWI – Two-Wire Interface ...................................................................... 49
22.1
Features .......................................................................................................... 49
22.2
Overview.......................................................................................................... 49
23 SPI – Serial Peripheral Interface ........................................................... 50
23.1
Features .......................................................................................................... 50
23.2
Overview.......................................................................................................... 50
24 USART ..................................................................................................... 51
24.1
Features .......................................................................................................... 51
24.2
Overview.......................................................................................................... 51
25 IRCOM – IR Communication Module .................................................... 52
25.1
Features .......................................................................................................... 52
25.2
Overview.......................................................................................................... 52
26 AES and DES Crypto Engine ................................................................ 53
26.1
Features .......................................................................................................... 53
26.2
Overview.......................................................................................................... 53
27 CRC – Cyclic Redundancy Check Generator ...................................... 54
27.1
Features .......................................................................................................... 54
27.2
Overview.......................................................................................................... 54
28 ADC – 12-bit Analog to Digital Converter ............................................ 55
28.1
Features .......................................................................................................... 55
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28.2
Overview.......................................................................................................... 55
29 DAC – 12-bit Digital to Analog Converter ............................................ 57
29.1
Features .......................................................................................................... 57
29.2
Overview.......................................................................................................... 57
30 AC – Analog Comparator ...................................................................... 59
30.1
Features .......................................................................................................... 59
30.2
Overview.......................................................................................................... 59
31 Programming and Debugging ............................................................... 61
31.1
Features .......................................................................................................... 61
31.2
Overview.......................................................................................................... 61
32 Pinout and Pin Functions ...................................................................... 61
32.1
Alternate Pin Function Description .................................................................. 61
32.2
Alternate Pin Functions ................................................................................... 64
33 Peripheral Module Address Map .......................................................... 67
34 Instruction Set Summary ....................................................................... 69
35 Packaging information .......................................................................... 74
35.1
44A .................................................................................................................. 74
35.2
PW................................................................................................................... 76
35.3
44M1................................................................................................................ 79
35.4
49C2 ................................................................................................................ 82
36 Electrical Characteristics ...................................................................... 85
36.1
ATxmega16A4U .............................................................................................. 85
36.2
ATxmega32A4U ............................................................................................ 106
36.3
ATxmega64A4U ............................................................................................ 128
36.4
ATxmega128A4U .......................................................................................... 150
37 Typical Characteristics ........................................................................ 172
37.1
ATxmega16A4U ............................................................................................ 172
37.2
ATxmega32A4U ............................................................................................ 214
37.3
ATxmega64A4U ............................................................................................ 256
37.4
ATxmega128A4U .......................................................................................... 298
38 Errata ..................................................................................................... 340
39 Datasheet Revision History ................................................................. 341
39.1
Rev. A – 04/2020 ........................................................................................... 341
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ATxmega128/64/32/16A4U
39.2
8387H –09/2014 ............................................................................................ 341
39.3
8387G – 03/2014........................................................................................... 341
39.4
8387F – 01/2014 ........................................................................................... 342
39.5
8387E – 11/2013 ........................................................................................... 342
39.6
8387D – 02/2013 ........................................................................................... 342
39.7
8387C – 03/2012 ........................................................................................... 343
39.8
8387B – 12/2011 ........................................................................................... 343
39.9
8387A – 07/2011 ........................................................................................... 344
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ATxmega128/64/32/16A4U
1.
Ordering Information
Ordering code
Flash (bytes)
EEPROM (bytes)
SRAM (bytes)
128K + 8K
2K
8K
128K + 8K
2K
8K
64K + 4K
2K
4K
ATxmega64A4U-AUR
64K + 4K
2K
4K
ATxmega32A4U-AU
32K + 4K
1K
4K
ATxmega32A4U-AUR(4)
32K + 4K
1K
4K
ATxmega16A4U-AU
16K + 4K
1K
2K
16K + 4K
1K
2K
128K + 8K
2K
8K
128K + 8K
2K
8K
ATxmega64A4U-MH
64K + 4K
2K
4K
ATxmega64A4U-MHR(4)
64K + 4K
2K
4K
ATxmega32A4U-MH
32K + 4K
1K
4K
ATxmega32A4U-MHR(4)
32K + 4K
1K
4K
ATxmega16A4U-MH
16K + 4K
1K
2K
ATxmega16A4U-MHR(4)
16K + 4K
1K
2K
ATxmega128A4U-CU
128K + 8K
2K
8K
128K + 8K
2K
8K
64K + 4K
2K
4K
ATxmega64A4U-CUR
64K + 4K
2K
4K
ATxmega32A4U-CU
32K + 4K
1K
4K
ATxmega32A4U-CUR(4)
32K + 4K
1K
4K
ATxmega16A4U-CU
16K + 4K
1K
2K
ATxmega16A4U-CUR
16K + 4K
1K
2K
ATxmega32A4U-AN
32K + 4K
1K
4K
ATxmega32A4U-ANR
32K + 4K
1K
4K
ATxmega16A4U-AN
16K + 4K
1K
2K
ATxmega16A4U-ANR(4)
16K + 4K
1K
2K
ATxmega128A4U-AU
ATxmega128A4U-AUR
(4)
ATxmega64A4U-AU
(4)
Speed (MHz)
Power supply
Package (1)(2)(3)
Temp.
44A
(4)
ATxmega16A4U-AUR
ATxmega128A4U-MH
ATxmega128A4U-MHR
(4)
PW
32
1.6 - 3.6V
-40C - 85C
44M1
ATxmega128A4U-CUR
(4)
ATxmega64A4U-CU
(4)
49C2
(4)
(4)
44A
32
Notes:
1.
2.
3.
4.
1.6 - 3.6V
0C - 105C
PW
This device can also be supplied in wafer form. Please contact your local Microchip sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see “Instruction Set Summary” on page 69.
Tape and Reel
Package Type
44A
44-Lead, 10 x 10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
44M1
44-Lead, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)
PW
44-Lead, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)
49C2
49-Ball (7 x 7 Array), 0.65mm Pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA)
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DS40002166A-page 8
ATxmega128/64/32/16A4U
Typical Applications
Industrial control
Climate control
Low power battery applications
Factory automation
RF and ZigBee®
Power tools
Building control
USB connectivity
HVAC
Board control
Sensor control
Utility metering
White goods
Optical
Medical applications
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DS40002166A-page 9
ATxmega128/64/32/16A4U
2.
Pinout/Block Diagram
Figure 2-1. Block Diagram and VQFN/TQFP pinout
Power
Ground
Programming, debug, test
AVCC
GND
PR1
PR0
RESET/PDI
PDI
38
37
36
35
34
PA1
41
39
PA2
42
PA0
PA3
43
40
PA4
External clock / Crystal pins
General Purpose I /O
44
Digital function
Analog function / Oscillators
Port R
XOSC
PA6
2
PA7
3
PB0
4
PB1
5
PB2
6
PB3
7
GND
8
VCC
9
DATA BUS
Port A
1
33
PE3
OSC/CLK
Control
Internal
oscillators
Watchdog
Power
Supervision
32
PE2
Sleep
Controller
Real Time
Counter
Watchdog
Timer
Reset
Controller
31
VCC
Event System
Controller
Crypto /
CRC
OCD
Prog/Debug
Interface
30
GND
29
PE1
28
PE0
27
PD7
26
PD6
25
PD5
24
PD4
23
PD3
AREF
ADC
AC0:1
Port B
PA5
TOSC
Interrupt
Controller
AREF
BUS
matrix
Internal
references
DAC
DMA
Controller
CPU
FLASH
EEPROM
SRAM
DATA BUS
Notes:
1.
2.
TWI
USART0
TC0
USB
SPI
13
14
15
16
17
18
19
20
21
22
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
PD1
PD2
Port E
12
Port D
PC2
Port C
USART0:1
TC0:1
TWI
11
SPI
PC1
USART0:1
10
TC0:1
PC0
IRCOM
EVENT ROUTING NETWORK
For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 61.
The large center pad underneath the VQFN packages should be soldered to ground on the board to ensure good mechanical stability.
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DS40002166A-page 10
ATxmega128/64/32/16A4U
Figure 2-2. VFBGA pinout
Top view
1
Table 2-1.
2
3
4
5
6
7
7
Bottom view
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
VFBGA pinout
1
2
3
4
5
6
7
A
PA3
AVCC
GND
PR1
PR0
PDI_DATA
PE3
B
PA4
PA1
PA0
GND
PE2
VCC
C
PA5
PA2
PA6
PA7
GND
PE1
GND
D
PB1
PB2
PB3
PB0
GND
PD7
PE0
E
GND
GND
PC3
GND
PD4
PD5
PD6
F
VCC
PC0
PC4
PC6
PD0
PD1
PD3
G
PC1
PC2
PC5
PC7
GND
VCC
PD2
2011-2020 Microchip Technology Inc.
RESET/
PDI_CLK
DS40002166A-page 11
ATxmega128/64/32/16A4U
3.
Overview
The Microchip AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers
based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA
devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the
system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA® A4U devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable
multilevel interrupt controller, 34 general purpose I/O lines, 16-bit real-time counter (RTC); five flexible, 16-bit
timer/counters with compare and PWM channels; five USARTs; two two-wire serial interfaces (TWIs); one full speed
USB 2.0 interface; two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; one twelve-channel, 12bit ADC with programmable gain; one 2-channel 12-bit DAC; two analog comparators (ACs) with window mode;
programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and
programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the
SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,
USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to
run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the
external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the
external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
Microchip offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Microchip high-density, nonvolatile memory technology. The program flash memory
can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download
the application program to the flash memory. The boot loader software in the boot flash section will continue to run while
the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU
with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly
flexible and cost effective solution for many embedded applications.
All Microchip AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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DS40002166A-page 12
ATxmega128/64/32/16A4U
3.1
Block Diagram
Figure 3-1. XMEGA® A4U Block Diagram
PR[0..1]
Digital function
Programming, debug, test
Analog function
Oscillator/Crystal/Clock
XTAL1/
TOSC1
General Purpose I/O
XTAL2/
TOSC2
Oscillator
Circuits/
Clock
Generation
PORT R (2)
Real Time
Counter
DATA BUS
PA[0..7]
PORT A (8)
Watchdog
Timer
Event System
Controller
Oscillator
Control
SRAM
ACA
DMA
Controller
ADCA
AREFA
Watchdog
Oscillator
Sleep
Controller
Prog/Debug
Controller
BUS Matrix
Power
Supervision
POR/BOD &
RESET
PDI
VCC
GND
RESET/
PDI_CLK
PDI_DATA
Int. Refs.
AES
Tempref
AREFB
®
DES
OCD
Interrupt
Controller
CPU
PB[0..7]
CRC
PORT B (8)
DACB
NVM Controller
Flash
IRCOM
EEPROM
DATA BUS
PORT D (8)
TWIE
TCE0
USARTE0
USB
SPID
TCD0:1
USARTD0:1
SPIC
PORT C (8)
TWIC
TCC0:1
USARTC0:1
EVENT ROUTING NETWORK
PORT E (4)
TOSC1 (optional)
TOSC2
(optional)
PC[0..7]
2011-2020 Microchip Technology Inc.
PD[0..7]
PE[0..3]
DS40002166A-page 13
ATxmega128/64/32/16A4U
4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.microchip.com.
4.1
Recommended reading
Microchip AVR XMEGA AU manual
XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain example
code and show applied use of the modules and peripherals.
All documentation are available from http://www.microchip.com.
5.
Capacitive touch sensing
The Microchip QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Microchip
AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully
debounced reporting of touch keys and includes Adjacent Key Suppression™ (AKS™) technology for unambiguous
detection of key events. The QTouch library includes support for the QTouch and QMatrix™ acquisition methods.
Touch sensing can be added to any application by linking the appropriate Microchip QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Microchip website at the following location:
http://www.microchip.com. For implementation details and other information, refer to the QTouch library user guide - also
available for download from the Microchip website.
2011-2020 Microchip Technology Inc.
DS40002166A-page 14
ATxmega128/64/32/16A4U
®
6.
AVR CPU
6.1
Features
8/16-bit, high-performance Microchip AVR RISC CPU
142 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
6.2
Overview
All Microchip AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 35.
6.3
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.microchip.com.
2011-2020 Microchip Technology Inc.
DS40002166A-page 15
ATxmega128/64/32/16A4U
Figure 6-1. Block diagram of the AVR® CPU architecture.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for safe storing of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
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purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
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During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-1 on page 22.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
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7.
Memories
7.1
Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
Bus arbitration
Deterministic priority handling between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM and I/O memory
Simultaneous bus access for CPU and DMA controller
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The Microchip AVR architecture has two main memory spaces, the program memory and the data memory. Executable
code can reside only in the program memory, while data can be stored in the program memory and the data memory.
The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear
and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 8. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
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7.3
Flash Program Memory
The Microchip AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Table 7-1.
Flash Program Memory (Hexadecimal address).
Word Address
ATxmega128A4U
ATxmega64A4U
0
ATxmega32A4U
0
ATxmega16A4U
0
0
Application Section
(128K/64K/32K/16K)
...
7.3.1
EFFF
/
77FF
/
37FF
/
17FF
F000
/
7800
/
3800
/
1800
FFFF
/
7FFF
/
3FFF
/
1FFF
10000
/
8000
/
4000
/
2000
10FFF
/
87FF
/
47FF
/
27FF
Application Table Section
(8K/4K/4K/4K)
Boot Section
(8K/4K/4K/4K)
Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2
Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3
Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
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7.3.4
Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 85.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-2.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-2.
Device ID bytes for Microchip AVR® XMEGA® A4U devices.
Device
7.3.5
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega16A4U
41
94
1E
ATxmega32A4U
41
95
1E
ATxmega64A4U
46
96
1E
ATxmega128A4U
46
97
1E
User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, and startup configuration.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory
if available. The data memory is organized as one continuous memory section, see Figure 7-1. To simplify development,
I/O Memory, EEPROM and SRAM will always have the same start addresses for all Microchip AVR XMEGA devices.
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Figure 7-1. Data memory map (Hexadecimal address).
Byte Address
ATxmega64A4U
0
FFF
I/O Registers (4K)
1000
EEPROM (2K)
17FF
Byte Address
ATxmega32A4U
0
FFF
1000
13FF
RESERVED
2000
2FFF
Byte Address
Internal SRAM (4K)
I/O Registers (4K)
EEPROM (1K)
Byte Address
ATxmega16A4U
0
FFF
1000
13FF
RESERVED
2000
2FFF
Internal SRAM (4K)
I/O Registers (4K)
EEPROM (1K)
RESERVED
2000
27FF
Internal SRAM (2K)
ATxmega128A4U
0
FFF
I/O Registers (4K)
1000
EEPROM (2K)
17FF
RESERVED
2000
3FFF
7.6
Internal SRAM (8K)
EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or
memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
7.7
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA® A4U is shown in the “Peripheral Module Address
Map” on page 67.
7.7.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
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7.8
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
7.9
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
7.10
Device ID and Revision
Each device has a three-byte device ID. This ID identifies Microchip as the manufacturer of the device and the device
type. A separate register contains the revision number of the device.
7.11
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.12
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-3 on page 23 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and
erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash
access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page
number and the least significant address bits (FWORD) give the word in the page.
Table 7-3.
Devices
Number of words and pages in the flash.
PC size
bits
Flash size
Page Size
bytes
words
FWORD
FPAGE
Application
Size
No of
pages
Boot
Size
No of
pages
ATxmega16A4U
14
16K + 4K
128
Z[6:0]
Z[13:7]
16K
64
4K
16
ATxmega32A4U
15
32K + 4K
128
Z[6:0]
Z[14:7]
32K
128
4K
16
ATxmega64A4U
16
64K + 4K
128
Z[6:0]
Z[15:7]
64K
256
4K
16
ATxmega128A4U
17
128K + 8K
128
Z[6:0]
Z[16:7]
128K
512
8K
32
Table 7-4 shows EEPROM memory organization for the Microchip AVR XMEGA® A4U devices. EEEPROM write and
erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a
time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in
the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
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Table 7-4.
Number of bytes and pages in the EEPROM.
Devices
EEPROM
Size
Page Size
E2BYTE
E2PAGE
No of Pages
bytes
ATxmega16A4U
1K
32
ADDR[4:0]
ADDR[10:5]
32
ATxmega32A4U
1K
32
ADDR[4:0]
ADDR[10:5]
32
ATxmega64A4U
2K
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega128A4U
2K
32
ADDR[4:0]
ADDR[10:5]
64
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8.
DMAC – Direct Memory Access Controller
8.1
Features
Allows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
from peripheral to data memory
from peripheral to peripheral
Four DMA channels with separate
transfer triggers
interrupt vectors
addressing modes
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Multiple addressing modes
Static
Incremental
Decremental
Optional reload of source and destination addresses at the end of each
Burst
Block
Transaction
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
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9.
Event System
9.1
Features
System for direct peripheral-to-peripheral communication and signaling
Peripherals can directly send, receive, and react to peripheral events
CPU and DMA controller independent operation
100% predictable signal timing
Short and guaranteed response time
Eight event channels for up to eight different and parallel signal routing configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders
Digital filtering of I/O pin state
Works in active mode and idle sleep mode
9.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It also allows for synchronized timing of actions in several peripheral
modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 26 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller).
Events can also be generated from software and the peripheral clock.
Figure 9-1. Event system overview and connected peripherals.
CPU /
Software
DMA
Controller
Event Routing Network
ADC
AC
clkPER
Prescaler
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
USB
Port pins
IRCOM
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
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10.
System Clock and Clock options
10.1
Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated and tuneable oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1x to 31x multiplication
Lock detector
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at two and four times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2
Overview
Microchip AVR XMEGA® A4U devices have a flexible clock system supporting a large number of clock sources. It
incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency
phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration
feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove
frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable
interrupt and switch to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 10-1 on page 28 presents the principal clock system in the XMEGA® A4U family of devices. Not all of the clocks
need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 30.
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Figure 10-1. The clock system, clock sources and clock distribution.
Real Time
Counter
AVR® CPU
RAM
Peripherals
Non-Volatile
Memory
clkPER
clkCPU
clkPER2
clkPER4
USB
clkUSB
Brown-out
Detector
System Clock Prescalers
Watchdog
Timer
Prescaler
AVR®
System Clock Multiplexer
clkSYS
clkRTC
(SCLKSEL)
RTCSRC
USBSRC
DIV32
DIV32
DIV32
PLL
PLLSRC
DIV4
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
32 MHz
Int. Osc
2 MHz
Int. Osc
XTAL2
XTAL1
TOSC2
TOSC1
10.3
0.4 – 16 MHz
XTAL
Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
10.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The
production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB
clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
10.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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11.
Power Management and Sleep Modes
11.1
Features
Power management for adjusting power consumption and functions
Five sleep modes
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2
Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Microchip AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
11.3
Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
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11.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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12.
System Control and Reset
12.1
Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
12.2
Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
12.3
Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4
Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 34.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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13.
WDT – Watchdog Timer
13.1
Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
13.2
Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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14.
Interrupts and Programmable Multilevel Interrupt Controller
14.1
Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
14.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3
Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Microchip AVR XMEGA® A4U devices are shown in Table 14-1 on page 36.
Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU
manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page 36.
The program address is the word address.
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Table 14-1. Reset and interrupt vectors
Program address
(base address)
Source
0x000
RESET
0x002
OSCF_INT_vect
Crystal oscillator failure interrupt vector (NMI)
0x004
PORTC_INT_base
Port C interrupt base
0x008
PORTR_INT_base
Port R interrupt base
0x00C
DMA_INT_base
DMA controller interrupt base
0x014
RTC_INT_base
Real time counter interrupt base
0x018
TWIC_INT_base
Two-Wire Interface on Port C interrupt base
0x01C
TCC0_INT_base
Timer/counter 0 on port C interrupt base
0x028
TCC1_INT_base
Timer/counter 1 on port C interrupt base
0x030
SPIC_INT_vect
SPI on port C interrupt vector
0x032
USARTC0_INT_base
USART 0 on port C interrupt base
0x038
USARTC1_INT_base
USART 1 on port C interrupt base
0x03E
AES_INT_vect
AES interrupt vector
0x040
NVM_INT_base
Nonvolatile Memory interrupt base
0x044
PORTB_INT_base
Port B interrupt base
0x056
PORTE_INT_base
Port E interrupt base
0x05A
TWIE_INT_base
Two-wire Interface on Port E interrupt base
0x05E
TCE0_INT_base
Timer/counter 0 on port E interrupt base
0x06A
TCE1_INT_base
Timer/counter 1 on port E interrupt base
0x074
USARTE0_INT_base
USART 0 on port E interrupt base
0x080
PORTD_INT_base
Port D interrupt base
0x084
PORTA_INT_base
Port A interrupt base
0x088
ACA_INT_base
Analog Comparator on Port A interrupt base
0x08E
ADCA_INT_base
Analog to Digital Converter on Port A interrupt base
0x09A
TCD0_INT_base
Timer/counter 0 on port D interrupt base
0x0A6
TCD1_INT_base
Timer/counter 1 on port D interrupt base
0x0AE
SPID_INT_vector
SPI on port D interrupt vector
0x0B0
USARTD0_INT_base
USART 0 on port D interrupt base
0x0B6
USARTD1_INT_base
USART 1 on port D interrupt base
0x0FA
USB_INT_base
USB on port D interrupt base
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15.
I/O Ports
15.1
Features
34 general purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
Optional slew rate control
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
15.2
Selectable USART, SPI, and timer/counter input/output pin locations
Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.
15.3
Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
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15.3.1 Push-pull
Figure 15-1. I/O configuration - Totem-pole.
DIRn
OUTn
Pn
INn
15.3.2 Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input).
DIRn
OUTn
Pn
INn
15.3.3 Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).
DIRn
OUTn
Pn
INn
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper.
DIRn
OUTn
Pn
INn
15.3.5 Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down.
OUTn
Pn
INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
INn
Pn
OUTn
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15.4
Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7.
Figure 15-7. Input sensing system overview.
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
D Q D Q
INVERTED I/O
R
EDGE
DETECT
Event
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5
Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 61 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
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16.
TC0/1 – 16-bit Timer/Counter Type 0 and 1
16.1
Features
Five 16-bit timer/counters
Three timer/counters of type 0
Two timer/counters of type 1
Split-mode enabling two 8-bit timer/counter from each timer/counter type 0
32-bit timer/counter support by cascading two timer/counters
Up to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
Double buffered timer period setting
Double buffered capture or compare channels
Waveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
Input capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
Timer overflow and error interrupts/events
One compare match or input capture interrupt/event per CC channel
Can be used with event system for:
Quadrature decoding
Count and direction control
Capture
Can be used with DMA and to trigger DMA transactions
High-resolution extension
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
Advanced waveform extension:
Low- and high-side output with programmable dead-time insertion (DTI)
Event controlled fault protection for safe disabling of drivers
16.2
Overview
Microchip AVR XMEGA devices have a set of five flexible 16-bit Timer/Counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
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Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 44 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 45 for more details.
Figure 16-1. Overview of a Timer/Counter and closely related peripherals.
Timer/Counter
Base Counter
Timer Period
Counter
Prescaler
Control Logic
clkPER
Event
System
clkPER4
Buffer
Capture
Control
Waveform
Generation
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORT
Comparator
AWeX
Hi-Res
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
PORTC and PORTD each has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Conter0. Notation
of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1 and TCE0, respectively.
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17.
TC2 - Timer/Counter Type 2
17.1
Features
Six eight-bit timer/counters
Three Low-byte timer/counter
Three High-byte timer/counter
Up to eight compare channels in each Timer/Counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
Can be used to trigger DMA transactions
17.2
Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock source and separate
period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from
the event system. The counters are always counting down.
PORTC, and PORTD each has one Timer/Counter 2.
Notation of these are TCC2 (Time/Counter C2) and TCD2, respectively.
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18.
AWeX – Advanced Waveform Extension
18.1
Features
Waveform output with complementary output from each compare channel
Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
Pattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
Event controlled fault protection for instant and predictable fault triggering
18.2
Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
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19.
Hi-Res – High Resolution Extension
19.1
Features
Increases waveform generator resolution up to 8x (three bits)
Supports frequency, single-slope PWM, and dual-slope PWM generation
Supports the AWeX when this is used for the same timer/counter
19.2
Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There are three hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD and
PORTE. The notation of these are HIRESC, HIRESD and HIRESE, respectively.
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20.
RTC – 16-bit Real-Time Counter
20.1
Features
16-bit resolution
Selectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
Programmable 10-bit clock prescaling
One compare register
One period register
Clear counter on period overflow
Optional interrupt/event on overflow and compare match
20.2
Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 20-1. Real-time counter overview.
External Clock
TOSC1
TOSC2
32.768kHz Crystal Osc
32.768kHz Int. Osc
DIV32
DIV32
32kHz int ULP (DIV32)
PER
RTCSRC
clkRTC
10-bit
prescaler
=
TOP/
Overflow
=
”match”/
Compare
CNT
COMP
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21.
USB – Universal Serial Bus Interface
21.1
Features
One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
One input endpoint per endpoint address
One output endpoint per endpoint address
Endpoint address transfer type selectable to
Control transfers
Interrupt transfers
Bulk transfers
Isochronous transfers
Configurable data payload size per endpoint, up to 1023 bytes
Endpoint configuration and data buffers located in internal SRAM
Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
Built-in direct memory access (DMA) to internal SRAM for:
Endpoint configurations
Reading and writing endpoint data
Ping-pong operation for higher throughput and double buffered operation
Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
Multipacket transfer for reduced interrupt load and software intervention
Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
Transaction complete FIFO for workflow management when using multiple endpoints
Tracks all completed transactions in a first-come, first-served work queue
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
21.2
Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and
a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep
mode.
PORTD has one USB. Notation of this is USB.
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22.
TWI – Two-Wire Interface
22.1
Features
Two Identical two-wire interface peripherals
Bidirectional, two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start/repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2
Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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23.
SPI – Serial Peripheral Interface
23.1
Features
Two Identical SPI peripherals
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
23.2
Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Microchip AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.
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24.
USART
24.1
Features
Five identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
Transmit complete
Transmit data register empty
Receive complete
Multiprocessor communication mode
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
Master SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
24.2
Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2Kbps.
PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these peripherals are USARTC0,
USARTC1, USARTD0, USARTD1 and USARTE0, respectively.
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25.
IRCOM – IR Communication Module
25.1
Features
Pulse modulation/demodulation for infrared communication
IrDA compatible for baud rates up to 115.2Kbps
Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
Built-in filtering
Can be connected to and used by any USART
25.2
Overview
Microchip AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud
rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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26.
AES and DES Crypto Engine
26.1
Features
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
Encryption and decryption
DES supported
Encryption/decryption in 16 CPU clock cycles per 8-byte block
AES crypto module
Encryption and decryption
Supports 128-bit keys
Supports XOR data load mode to the state memory
Encryption/decryption in 375 clock cycles per 16-byte block
26.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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27.
CRC – Cyclic Redundancy Check Generator
27.1
Features
Cyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
Data in SRAM and I/O memory space
Integrated with flash memory, DMA controller and CPU
Continuous CRC on data going through a DMA channel
Automatic CRC of the complete or a selectable range of the flash memory
CPU can load data to the CRC generator through the I/O interface
CRC polynomial software selectable to
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
Zero remainder detection
27.2
Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in Microchip AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16
(CRC-CCITT) and CRC-32 (IEEE 802.3).
CRC-16:
Polynomial:
x16+x12+x5+1
Hex value:
0x1021
CRC-32:
Polynomial:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value:
0x04C11DB7
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28.
ADC – 12-bit Analog to Digital Converter
28.1
Features
One Analog to Digital Converter (ADC)
12-bit resolution
Up to two million samples per second
Two inputs can be sampled simultaneously using ADC and 1x gain stage
Four inputs can be sampled within 1.5µs
Down to 2.5µs conversion time with 8-bit resolution
Down to 3.5µs conversion time with 12-bit resolution
Differential and single-ended input
Up to 12 single-ended inputs
12x4 differential inputs without gain
8x4 differential inputs with gain
Built-in differential gain stage
1/2x,
1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
Single, continuous and scan conversion options
Four internal inputs
Internal temperature sensor
DAC output
AVCC voltage divided by 10
1.1V bandgap voltage
Four conversion channels with individual input control and result registers
Enable four parallel configurations and results
Internal and external reference options
Compare function for accurate monitoring of user defined thresholds
Optional event triggered conversion for accurate timing
Optional DMA transfer of conversion results
Optional interrupt/event on compare result
28.2
Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to two
million samples per second (msps). The input selection is flexible, and both single-ended and differential measurements
can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In
addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at a
low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started while
other ADC conversions are still ongoing. This removes dependencies between sample rate and propagation delay.
The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start control.
The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with high
data throughput or for multiple modules using the ADC independently. It is possible to use DMA to move ADC results
directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The output from the DAC, AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
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Figure 28-1. ADC overview.
ADC0
Compare
•
••
ADC11
ADC0
Internal
signals
VINP
CH0 Result
••
•
ADC7
ADC4
CH1 Result
Threshold
(Int Req)
½x - 64x
CH2 Result
•
••
ADC7
Int. signals
<
>
Internal
signals
CH3 Result
VINN
ADC0
•
••
ADC3
Int. signals
Internal 1.00V
Internal AVCC/1.6V
Internal AVCC/2
AREFA
AREFB
Reference
Voltage
Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the
gain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any intervention by the application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs
for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
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29.
DAC – 12-bit Digital to Analog Converter
29.1
Features
One Digital to Analog Converter (DAC)
12-bit resolution
Two independent, continuous-drive output channels
Up to one million samples per second conversion rate per DAC channel
Built-in calibration that removes:
29.2
Offset error
Gain error
Multiple conversion trigger sources
On new available data
Events from the event system
High drive capabilities and support for
Resistive loads
Capacitive loads
Combined resistive and capacitive loads
Internal and external reference options
DAC output available as input to analog comparator and ADC
Low-power mode, with reduced drive strength
Optional DMA transfer of data
Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit
resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in
calibration system can remove offset and gain error when loaded with calibration values from software.
Figure 29-1. DAC overview.
DMA req
(Data Empty)
CH0DATA
12
D
A
T
A
DAC0
Output
Driver
Int.
driver
AVCC
Internal 1.00V
AREFA
AREFB
Reference
selection
Trigger
CTRLB
Trigger
CH1DATA
12
DMA req
(Data Empty)
2011-2020 Microchip Technology Inc.
Select
D
A
T
A
Enable
CTRLA
Select
DAC1
Enable
To
AC/ADC
Internal Output
enable
Output
Driver
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A DAC conversion is automatically started when new data to be converted are available. Events from the event system
can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and
other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.
The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which
combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external
voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or
ADC.
PORTB has one DAC. Notation of this peripheral is DACB.
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30.
AC – Analog Comparator
30.1
Features
Two Analog Comparators (ACs)
Selectable propagation delay versus current consumption
Selectable hysteresis
No
Small
Large
Analog comparator output available on pin
Flexible input selection
All pins on the port
Output from the DAC
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal AVCC voltage
Interrupt and event generation on:
Rising edge
Falling edge
Toggle
Window function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
Constant current source with configurable output pin selection
30.2
Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of
these parameters may be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA has one AC pair. Notation is ACA.
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Figure 30-1. Analog comparator overview.
Pin Input
AC0OUT
Pin Input
Hysteresis
Enable
DAC
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
Interrupt
Mode
WINCTRL
Enable
Bandgap
Interrupt
Sensititivity
Control
&
Window
Function
Interrupts
Events
Hysteresis
Pin Input
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 30-2.
Figure 30-2. Analog comparator window function.
+
AC0
Upper limit of window
Interrupt
sensitivity
control
Input signal
Interrupts
Events
+
AC1
Lower limit of window
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31.
Programming and Debugging
31.1
Features
Programming
External programming through PDI interface
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
Debugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
No limitation on device clock frequency
Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
31.2
Overview
The Program and Debug Interface (PDI) is an Microchip proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Microchip tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset
pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external
programmer or on-chip debugger/emulator can be directly connected to this interface.
32.
Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 10. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
32.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
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32.1.1 Operation/Power Supply
VCC
Digital supply voltage
AVCC
Analog supply voltage
GND
Ground
32.1.2 Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
32.1.3 Analog functions
ACn
Analog Comparator input pin n
ACnOUT
Analog Comparator n Output
ADCn
Analog to Digital Converter input pin n
DACn
Digital to Analog Converter output pin n
AREF
Analog Reference input pin
32.1.4 Timer/Counter and AWEX functions
OCnxLS
Output Compare Channel x Low Side for Timer/Counter n
OCnxHS
Output Compare Channel x High Side for Timer/Counter n
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32.1.5 Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
Serial Clock In for TWI when external driver interface is enabled
SCLOUT
Serial Clock Out for TWI when external driver interface is enabled
SDAIN
Serial Data In for TWI when external driver interface is enabled
SDAOUT
Serial Data Out for TWI when external driver interface is enabled
XCKn
Transfer Clock for USART n
RXDn
Receiver Data for USART n
TXDn
Transmitter Data for USART n
SS
Slave Select for SPI
MOSI
Master Out Slave In for SPI
MISO
Master In Slave Out for SPI
SCK
Serial Clock for SPI
D-
Data- for USB
D+
Data+ for USB
32.1.6 Oscillators, Clock and Event
TOSCn
Timer Oscillator pin n
XTALn
Input/Output for Oscillator pin n
CLKOUT
Peripheral Clock Output
EVOUT
Event Channel Output
RTCOUT
RTC Clock Source Output
32.1.7 Debug/System functions
RESET
Reset pin
PDI_CLK
Program and Debug Interface Clock pin
PDI_DATA
Program and Debug Interface Data pin
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32.2
Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
first table where this apply.
Table 32-1. Port A - alternate functions.
PORT A
PIN #
INTERRUPT
ADCA POS/
GAINPOS
ADCA NEG
ADCA
GAINNEG
ACA POS
ACA NEG
GND
38
AVCC
39
PA0
40
SYNC
ADC0
ADC0
AC0
AC0
PA1
41
SYNC
ADC1
ADC1
AC1
AC1
PA2
42
SYNC/ASYNC
ADC2
ADC2
AC2
PA3
43
SYNC
ADC3
ADC3
AC3
PA4
44
SYNC
ADC4
ADC4
AC4
PA5
1
SYNC
ADC5
ADC5
AC5
PA6
2
SYNC
ADC6
ADC6
AC6
PA7
3
SYNC
ADC7
ADC7
ACAOUT
REFA
AREF
AC3
AC5
AC1OUT
AC7
AC0OUT
Table 32-2. Port B - alternate functions.
PORT B
PIN #
INTERRUPT
ADCA POS
PB0
4
SYNC
ADC8
PB1
5
SYNC
ADC9
PB2
6
SYNC/ASYNC
ADC10
DAC0
PB3
7
SYNC
ADC11
DAC1
2011-2020 Microchip Technology Inc.
DACB
REFB
AREF
DS40002166A-page 64
ATxmega128/64/32/16A4U
Table 32-3. Port C - alternate functions.
PORT C
PIN #
INTERRUPT
TCC0
AWEXC
TCC1
(1)(2)
USART
C0(3)
USART
C1
SPIC(4)
TWIC
TWIC
w/ext
driver
GND
8
VCC
9
PC0
10
SYNC
OC0A
OC0ALS
PC1
11
SYNC
OC0B
OC0AHS
XCK0
PC2
12
SYNC/
ASYNC
OC0C
OC0BLS
RXD0
SDAOUT
PC3
13
SYNC
OC0D
OC0BHS
TXD0
SCLOUT
PC4
14
SYNC
OC0CLS
OC1A
PC5
15
SYNC
OC0CHS
OC1B
PC6
16
SYNC
PC7
17
SYNC
Notes:
1.
2.
3.
4.
5.
6.
SDAIN
SCL
SCLIN
EVENTOUT
(5)
(6)
SS
XCK1
MOSI
OC0DLS
RXD1
MISO
clkRTC
OC0DHS
TXD1
SCK
clkPER
EVOUT
Pin mapping of all TC0 can optionally be moved to high nibble of port
If TC0 is configured as TC2 all eight pins can be used for PWM output.
Pin mapping of all USART0 can optionally be moved to high nibble of port.
Pins MOSI and SCK for all SPI can optionally be swapped.
CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.
EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.
Table 32-4.
PORT D
SDA
CLOCKOUT
PIN #
Port D - alternate functions.
INTERRUPT
TCD0
TCD1
USB
USARTD0
GND
18
VCC
19
PD0
20
SYNC
OC0A
PD1
21
SYNC
OC0B
XCK0
PD2
22
SYNC/ASYNC
OC0C
RXD0
PD3
23
SYNC
OC0D
TXD0
PD4
24
SYNC
OC1A
PD5
25
SYNC
OC1B
PD6
26
SYNC
PD7
27
SYNC
2011-2020 Microchip Technology Inc.
USARTD1
SPID
CLOCKOUT
EVENTOUT
clkPER
EVOUT
SS
XCK1
MOSI
D-
RXD1
MISO
D+
TXD1
SCK
DS40002166A-page 65
ATxmega128/64/32/16A4U
Table 32-5. Port E - alternate functions.
PORT E
PIN #
INTERRUPT
TCE0
USARTE0
PE0
28
SYNC
OC0A
PE1
29
SYNC
OC0B
XCK0
GND
30
VCC
31
PE2
32
SYNC/ASYNC
OC0C
RXD0
PE3
33
SYNC
OC0D
TXD0
TWIE
SDA
SCL
Table 32-6. Port R - alternate functions.
PORT R
PIN #
INTERRUPT
PDI
XTAL
TOSC(1)
PDI
34
PDI_DATA
RESET
35
PDI_CLOCK
PR0
36
SYNC
XTAL2
TOSC2
PR1
37
SYNC
XTAL1
TOSC1
Note:
1.
TOSC pins can optionally be moved to PE2/PE3.
2011-2020 Microchip Technology Inc.
DS40002166A-page 66
ATxmega128/64/32/16A4U
33.
Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Microchip AVR XMEGA® A4U. For
complete register description and summary for each peripheral module, refer to the XMEGA AU manual.
Table 33-1. Peripheral module address map.
Base address
Name
Description
0x0000
GPIO
General Purpose IO Registers
0x0010
VPORT0
Virtual Port 0
0x0014
VPORT1
Virtual Port 1
0x0018
VPORT2
Virtual Port 2
0x001C
VPORT3
Virtual Port 2
0x0030
CPU
CPU
0x0040
CLK
Clock Control
0x0048
SLEEP
Sleep Controller
0x0050
OSC
Oscillator Control
0x0060
DFLLRC32M
DFLL for the 32MHz Internal RC Oscillator
0x0068
DFLLRC2M
DFLL for the 2MHz RC Oscillator
0x0070
PR
Power Reduction
0x0078
RST
Reset Controller
0x0080
WDT
Watch-Dog Timer
0x0090
MCU
MCU Control
0x00A0
PMIC
Programmable MUltilevel Interrupt Controller
0x00B0
PORTCFG
0x00C0
AES
AES Module
0x00D0
CRC
CRC Module
0x0100
DMA
DMA Module
0x0180
EVSYS
Event System
0x01C0
NVM
Non Volatile Memory (NVM) Controller
0x0200
ADCA
Analog to Digital Converter on port A
0x0380
ACA
Analog Comparator pair on port A
0x0400
RTC
Real Time Counter
0x0480
TWIC
Two Wire Interface on port C
0x04A0
TWIE
Two Wire Interface on port E
0x04C0
USB
Universal Serial Bus Interface
0x0600
PORTA
2011-2020 Microchip Technology Inc.
Port Configuration
Port A
DS40002166A-page 67
ATxmega128/64/32/16A4U
Base address
Name
Description
0x0620
PORTB
Port B
0x0640
PORTC
Port C
0x0660
PORTD
Port D
0x0680
PORTE
Port E
0x07E0
PORTR
Port R
0x0800
TCC0
Timer/Counter 0 on port C
0x0840
TCC1
Timer/Counter 1 on port C
0x0880
AWEXC
Advanced Waveform Extension on port C
0x0890
HIRESC
High Resolution Extension on port C
0x08A0
USARTC0
USART 0 on port C
0x08B0
USARTC1
USART 1 on port C
0x08C0
SPIC
0x08F8
IRCOM
0x0900
TCD0
Timer/Counter 0 on port D
0x0940
TCD1
Timer/Counter 1 on port D
0x0990
HIRESD
0x09A0
USARTD0
USART 0 on port D
0x09B0
USARTD1
USART 1 on port D
0x09C0
SPID
Serial Peripheral Interface on port D
0x0A00
TCE0
Timer/Counter 0 on port E
0x0A80
AWEXE
Advanced Waveform Extensionon port E
0x0A90
HIRESE
High Resolution Extension on port E
0x0AA0
USARTE0
2011-2020 Microchip Technology Inc.
Serial Peripheral Interface on port C
Infrared Communication Module
High Resolution Extension on port D
USART 0 on port E
DS40002166A-page 68
ATxmega128/64/32/16A4U
34.
Instruction Set Summary
Mnemonic
s
Operand
s
Description
Operation
Flags
#Clock
s
Arithmetic and Logic Instructions
ADD
Rd, Rr
Add without Carry
Rd
Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd
Rd + Rr + C
Z,C,N,V,S,H
1
ADIW
Rd, K
Add Immediate to Word
Rd
Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd
Rd + 1:Rd - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND
Rd
Rd Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
Rd K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
Rd Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
Rd ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
Rd Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
Rd Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0
Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0
Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0
Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0
Rd x Rr
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