Features
• High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller
• Non-volatile Program and Data Memories
•
•
•
•
•
– 64 KB - 256 KB of In-System Self-Programmable Flash
– 4 KB - 8 KB Boot Code Section with Independent Lock Bits
– 2 KB - 4 KB EEPROM
– 4 KB - 16 KB Internal SRAM
Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Seven USARTs
IrDA Extension on 1 USART
– AES and DES Crypto Engine
– Two Two-wire Interfaces with dual address match (I2C and SMBus compatible)
– Three SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming, test and debugging
I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
8/16-bit
XMEGA A3
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
Not recommended for
new designs - Use
XMEGA A3U series
Typical Applications
•
•
•
•
•
Industrial control
Factory automation
Building control
Board control
White Goods
•
•
•
•
•
Climate control
ZigBee
Motor control
Networking
Optical
•
•
•
•
•
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
8068U–AVR–06/2013
Not recommended for new designs
Use XMEGA A3U series
XMEGA A3
1. Ordering Information
Flash
E2
SRAM
Speed (MHz)
Power Supply
ATxmega256A3-AU
256 KB + 8 KB
4 KB
16 KB
32
1.6 - 3.6V
ATxmega192A3-AU
192 KB + 8 KB
2 KB
16 KB
32
1.6 - 3.6V
ATxmega128A3-AU
128 KB + 8 KB
2 KB
8 KB
32
1.6 - 3.6V
ATxmega64A3-AU
64 KB + 4 KB
2 KB
4 KB
32
1.6 - 3.6V
ATxmega256A3-MH
256 KB + 8 KB
4 KB
16 KB
32
1.6 - 3.6V
ATxmega192A3-MH
192 KB + 8 KB
2 KB
16 KB
32
1.6 - 3.6V
ATxmega128A3-MH
128 KB + 8 KB
2 KB
8 KB
32
1.6 - 3.6V
ATxmega64A3-MH
64 KB + 4 KB
2 KB
4 KB
32
1.6 - 3.6V
Ordering Code
Notes:
1.
2.
3.
Package(1)(2)(3)
Temp
64A
-40C - 85C
64M2
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see ”Packaging information” on page 61.
Package Type
64A
64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64M2
64-Pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
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XMEGA A3
2. Pinout/Block Diagram
ADC A
OSC/CLK
Control
PF5
PF4
PF3
BOD
VREF
POR
TEMP
RTC
OCD
AC A0
Power
Control
AC A1
FLASH
CPU
ADC B
Reset
Control
DAC B
RAM
DMA
AC B0
E2PROM
Interrupt Controller
Watchdog
AC B1
Event System ctrl
DATA BU S
USART0
SPI
TWI
T/C0
Port F
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PF2
PF1
PF0
VCC
GND
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
GND
PD7
PD2
PD3
PD4
PD5
PD6
27
28
29
30
31
32
Port E
PD0
PD1
GND
VCC
USART0:1
T/C0:1
SPI
USART0:1
Port D
25
26
Port C
T/C0:1
SPI
TWI
USART0:1
EVENT ROUTING NETWORK
PC1
PC2
PC3
PC4
PC5
PC6
PC7
Notes:
VCC
GND
PF7
PF6
55
54
53
52
51
50
49
57
56
DATA BU S
T/C0:1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Port R
17
18
19
20
21
22
23
24
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
48
1
2
Port A
PA3
PA4
PA2
PA1
PA0
AVCC
GND
PR1
PR0
RESET/PDI
PDI
INDEX CORNER
64
63
62
61
60
59
58
Block diagram and pinout.
Port B
Figure 2-1.
1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 49.
2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good
mechanical stability.
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XMEGA A3
3. Overview
The Atmel® AVR® XMEGA™ A3 is a family of low power, high performance and peripheral rich
CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching
1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA A3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose
I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare
modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional
differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock for each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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XMEGA A3
3.1
Block Diagram
Figure 3-1.
XMEGA A3 Block Diagram
PR[0..1]
XTAL1
PORT R (2)
XTAL2
Oscillator
Circuits/
Clock
Generation
Watchdog
Oscillator
Real Time
Counter
Watchdog
Timer
DATA BUS
PA[0..7]
PORT A (8)
Event System
Controller
ACA
SRAM
DMA
Controller
ADCA
VCC
Power
Supervision
POR/BOD &
RESET
Oscillator
Control
GND
Sleep
Controller
RESET/
PDI_CLK
PDI
PDI_DATA
AREFA
BUS
Controller
VCC/10
Prog/Debug
Controller
JTAG
Int. Ref.
Tempref
DES
PORT B
OCD
AREFB
CPU
Interrupt
Controller
AES
ADCB
NVM Controller
PB[0..7]/
JTAG
USARTF0
PORT B (8)
TCF0
Flash
EEPROM
PORT F (8)
ACB
PF[0..7]
DACB
IRCOM
DATA BUS
PORT C (8)
PORT D (8)
TWIE
SPIE
TCE0:1
USARTE0:1
SPID
USARTD0:1
TCD0:1
TWIC
SPIC
TCC0:1
USARTC0:1
EVENT ROUTING NETWORK
PORT E (8)
To Clock
Generato
r
TOSC1
TOSC2
PC[0..7]
PD[0..7]
PE[0..7]
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8068U–AVR–06/2013
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XMEGA A3
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1
Recommended reading
• XMEGA Manual
• XMEGA Application Notes
This device data sheet only contains part specific information and a short description of each
peripheral and module. The XMEGA Manual describes the modules and peripherals in depth.
The XMEGA application notes contain example code and show applied use of the modules and
peripherals.
The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
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XMEGA A3
6. AVR CPU
6.1
Features
• 8/16-bit high performance AVR RISC Architecture
•
•
•
•
•
•
•
6.2
– 138 instructions
– Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
Overview
The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations and control peripherals. Interrupt handling is described in a separate section. Figure
6-1 on page 7 shows the CPU block diagram.
Figure 6-1.
CPU block diagram
DATA BUS
Flash
Program
Memory
Program
Counter
OCD
Instruction
Register
STATUS/
CONTROL
Instruction
Decode
32 x 8 General
Purpose
Registers
ALU
Multiplier/
DES
DATA BUS
Peripheral
Module 1
Peripheral
Module 2
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
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XMEGA A3
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3
Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4
ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5
Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
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XMEGA A3
7. Memories
7.1
Features
• Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
– Built in fast CRC check of a selectable flash program memory section
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
16 bit-accessible General Purpose Register for global variables or flags
– Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access
Simultaneous bus access for CPU and DMA Controller
• Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC, DAC and temperature sensor calibration data
• User Signature Row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configurations are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.
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XMEGA A3
7.3
In-System Programmable Flash Program Memory
The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each
Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.
Figure 7-1.
Flash Program Memory (Hexadecimal address)
Word Address
0
Application Section
(256 KB/192 KB/128 KB/64 KB)
...
1EFFF
/
16FFF
/
EFFF
/
77FF
1F000
/
17000
/
F000
/
7800
1FFFF
/
17FFF
/
FFFF
/
7FFF
20000
/
18000
/
10000
/
8000
20FFF
/
18FFF
/
10FFF
/
87FF
Application Table Section
(8 KB/8 KB/8 KB/4 KB)
Boot Section
(8 KB/8 KB/8 KB/4 KB)
The Application Table Section and Boot Section can also be used for general application
software.
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XMEGA A3
7.4
Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2.
Data Memory Map (Hexadecimal address)
Byte Address
0
FFF
1000
17FF
ATxmega192A3
I/O Registers
(4 KB)
EEPROM
(2 KB)
Byte Address
0
FFF
1000
17FF
RESERVED
2000
5FFF
Internal SRAM
(16 KB)
ATxmega128A3
I/O Registers
(4 KB)
EEPROM
(2 KB)
Byte Address
ATxmega64A3
0
I/O Registers
(4 KB)
FFF
1000
EEPROM
(2 KB)
17FF
RESERVED
2000
3FFF
Internal SRAM
(8 KB)
RESERVED
2000
2FFF
Byte Address
0
FFF
Internal SRAM
(4 KB)
ATxmega256A3
I/O Registers
(4 KB)
1000
EEPROM
(4 KB)
1FFF
2000
5FFF
Internal SRAM
(16 KB)
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XMEGA A3
7.4.1
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the ”Peripheral Module Address Map” on page 56.
7.4.2
SRAM Data Memory
The XMEGA A3 devices have internal SRAM memory for data storage.
7.4.3
EEPROM Data Memory
The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
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7.5
Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA A3 devices is shown in Table 7-1 on page 13. The serial number consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both application software and external programming.
Table 7-1.
Device ID bytes for XMEGA A3 devices.
Device
7.6
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega64A3
42
96
1E
ATxmega128A3
42
97
1E
ATxmega192A3
44
97
1E
ATxmega256A3
42
98
1E
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or identification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase session and on-chip debug sessions.
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7.7
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) gives the page number and the least significant address bits (FWORD)
gives the word in the page.
Table 7-2.
Devices
Flash
Page Size
Number of words and Pages in the Flash.
FWORD
FPAGE
Application
Boot
Size
(words)
Size
No of Pages
Size
No of Pages
ATxmega64A3
64 KB + 4 KB
128
Z[7:1]
Z[16:8]
64K
256
4 KB
16
ATxmega128A3
128 KB + 8 KB
256
Z[8:1]
Z[17:9]
128K
256
8 KB
16
ATxmega192A3
192 KB + 8 KB
256
Z[8:1]
Z[18:9]
192K
384
8 KB
16
ATxmega256A3
256 KB + 8 KB
256
Z[8:1]
Z[18:9]
256K
512
8 KB
16
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A3 devices. EEEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives
the page number and the least significant address bits (E2BYTE) gives the byte in the page.
Table 7-3.
Devices
Number of bytes and Pages in the EEPROM.
EEPROM
Page Size
E2BYTE
E2PAGE
No of Pages
Size
(Bytes)
ATxmega64A3
2 KB
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega128A3
2 KB
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega192A3
2 KB
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega256A3
4 KB
32
ADDR[4:0]
ADDR[11:5]
128
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8. DMAC - Direct Memory Access Controller
8.1
Features
• Allows High-speed data transfer
•
•
•
•
•
8.2
– From memory to peripheral
– From memory to memory
– From peripheral to memory
– From peripheral to peripheral
4 Channels
From 1 byte and up to 16 M bytes transfers in a single transaction
Multiple addressing modes for source and destination address
– Increment
– Decrement
– Static
1, 2, 4, or 8 bytes Burst Transfers
Programmable priority between channels
Overview
The XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories
and peripherals in the data space. The DMA controller uses the same data bus as the CPU to
transfer data.
It has 4 channels that can be configured independently. Each DMA channel can perform data
transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to
repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be
configured to access the source and destination memory address with incrementing, decrementing or static addressing. The addressing is independent for source and destination address.
When the transaction is complete the original source and destination address can automatically
be reloaded to be ready for the next transaction.
The DMAC can access all the peripherals through their I/O memory registers, and the DMA may
be used for automatic transfer of data to/from communication modules, as well as automatic
data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or
from port pins. A wide range of transfer triggers is available from the peripherals, Event System
and software. Each DMA channel has different transfer triggers.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
The DMA controller can read from memory mapped EEPROM, but it cannot write to the
EEPROM or access the Flash.
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9. Event System
9.1
Features
•
•
•
•
•
•
•
•
9.2
Inter-peripheral communication and signalling with minimum latency
CPU and DMA independent operation
8 Event Channels allows for up to 8 signals to be routed at the same time
Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (ClkSYS)
– Software (CPU)
Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
The same event can be used by multiple peripherals for synchronized timing
Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
Functions in Active and Idle mode
Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
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Figure 9-1.
Event system block diagram.
PORTx
ClkSYS
CPU
ADCx
RTC
Event Routing
Network
DACx
IRCOM
ACx
T/Cxn
DMAC
The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators
(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always routed into the Event Routing Network. This consist of
eight multiplexers where each can be configured in software to select which event to be routed
into that event channel. All eight event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
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10. System Clock and Clock options
10.1
Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
•
•
•
•
•
•
10.2
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32.768 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32.768 kHz Crystal Oscillator
– External clock
PLL with internal and external clock options with 2 to 31x multiplication
Clock Prescalers with 2 to 2048x division
Fast peripheral clock running at 2 and 4 times the CPU clock speed
Automatic Run-Time Calibration of internal oscillators
Crystal Oscillator failure detection
Overview
XMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 19 shows the principal clock system in XMEGA A3.
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Figure 10-1. Clock system overview
clkULP
WDT/BOD
32 kHz ULP
Internal Oscillator
clkRTC
RTC
32.768 kHz
Calibrated Internal
Oscillator
PERIPHERALS
ADC
2 MHz
Run-Time Calibrated
Internal Oscillator
32 MHz
Run-time Calibrated
Internal Oscillator
DAC
CLOCK CONTROL
clkPER
UNIT
with PLL and
Prescaler
PORTS
...
DMA
INTERRUPT
32.768 KHz
Crystal Oscillator
EVSYS
RAM
0.4 - 16 MHz
Crystal Oscillator
CPU
clkCPU NVM MEMORY
FLASH
External
Clock Input
EEPROM
Each clock source is briefly described in the following sub-sections.
10.3
10.3.1
Clock Options
32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
10.3.2
32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during production to provide a default frequency which is close to its nominal
frequency.
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10.3.3
32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
10.3.4
0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
10.3.5
2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
10.3.6
32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
10.3.7
External Clock input
The external clock input gives the possibility to connect a clock from an external source.
10.3.8
PLL with Multiplication factor 1 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1
Features
• 5 sleep modes
– Idle
– Power-down
– Power-save
– Standby
– Extended standby
• Power Reduction registers to disable clocks to unused peripherals
11.2
Overview
The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the
CPU is executing application code. The application code decides when and which sleep mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
11.3
Sleep Modes
11.3.1
Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from
all enabled interrupts will wake the device.
11.3.2
Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
11.3.3
Power-save Mode
Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will
keep running during sleep and the device can also wake up from RTC interrupts.
11.3.4
Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
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11.3.5
Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
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12. System Control and Reset
12.1
Features
• Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– PDI reset
– Software reset
• Asynchronous reset
– No running clock in the device is required for reset
• Reset status register
12.2
Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector
address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active. The reset
functionality is asynchronous, so no running clock is required to reset the device. After the
device is reset, the reset source can be determined by the application by reading the Reset Status Register.
12.3
12.3.1
Reset Sources
Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.3.2
External Reset
The MCU is reset when a low level is present on the RESET pin.
12.3.3
Watchdog Reset
The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.
The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For
more details see ”WDT - Watchdog Timer” on page 24.
12.3.4
Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
12.3.5
PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
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12.3.6
Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
13. WDT - Watchdog Timer
13.1
Features
• 11 selectable timeout periods, from 8 ms to 8s.
• Two operation modes
– Standard mode
– Window mode
• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
• Configuration lock to prevent unwanted changes
13.2
Overview
The XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable the WDT.
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14. PMIC - Programmable Multi-level Interrupt Controller
14.1
Features
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
14.2
Overview
XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
14.3
Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown
in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for
each peripheral in the XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address.
Table 14-1.
Reset and Interrupt Vectors
Program Address
(Base Address)
Source
0x000
RESET
0x002
OSCF_INT_vect
Crystal Oscillator Failure Interrupt vector (NMI)
0x004
PORTC_INT_base
Port C Interrupt base
0x008
PORTR_INT_base
Port R Interrupt base
0x00C
DMA_INT_base
DMA Controller Interrupt base
0x014
RTC_INT_base
Real Time Counter Interrupt base
0x018
TWIC_INT_base
Two-Wire Interface on Port C Interrupt base
0x01C
TCC0_INT_base
Timer/Counter 0 on port C Interrupt base
0x028
TCC1_INT_base
Timer/Counter 1 on port C Interrupt base
0x030
SPIC_INT_vect
SPI on port C Interrupt vector
0x032
USARTC0_INT_base
USART 0 on port C Interrupt base
0x03D
USARTC1_INT_base
USART 1 on port C Interrupt base
0x03E
AES_INT_vect
AES Interrupt vector
Interrupt Description
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Table 14-1.
Reset and Interrupt Vectors (Continued)
Program Address
(Base Address)
Source
Interrupt Description
0x040
NVM_INT_base
Non-Volatile Memory Interrupt base
0x044
PORTB_INT_base
Port B Interrupt base
0x048
ACB_INT_base
Analog Comparator on Port B Interrupt base
0x04E
ADCB_INT_base
Analog to Digital Converter on Port B Interrupt base
0x056
PORTE_INT_base
Port E INT base
0x05A
TWIE_INT_base
Two-Wire Interface on Port E Interrupt base
0x05E
TCE0_INT_base
Timer/Counter 0 on port E Interrupt base
0x06A
TCE1_INT_base
Timer/Counter 1 on port E Interrupt base
0x072
SPIE_INT_vect
SPI on port E Interrupt vector
0x074
USARTE0_INT_base
USART 0 on port E Interrupt base
0x07A
USARTE1_INT_base
USART 1 on port E Interrupt base
0x080
PORTD_INT_base
Port D Interrupt base
0x084
PORTA_INT_base
Port A Interrupt base
0x088
ACA_INT_base
Analog Comparator on Port A Interrupt base
0x08E
ADCA_INT_base
Analog to Digital Converter on Port A Interrupt base
0x09A
TCD0_INT_base
Timer/Counter 0 on port D Interrupt base
0x0A6
TCD1_INT_base
Timer/Counter 1 on port D Interrupt base
0x0AE
SPID_INT_vector
SPI D Interrupt vector
0x0B0
USARTD0_INT_base
USART 0 on port D Interrupt base
0x0B6
USARTD1_INT_base
USART 1 on port D Interrupt base
0x0D0
PORTF_INT_base
Port F Interrupt base
0x0D8
TCF0_INT_base
Timer/Counter 0 on port F Interrupt base
0x0EE
USARTF0_INT_base
USART 0 on port F Interrupt base
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15. I/O Ports
15.1
Features
• Selectable input and output configuration for each pin individually
• Flexible pin configuration through dedicated Pin Configuration Register
• Synchronous and/or asynchronous input sensing with port interrupts and events
•
•
•
•
•
•
•
•
•
15.2
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
Asynchronous wake-up from all input sensing configurations
Two port interrupts with flexible pin masking
Highly configurable output driver and pull settings:
–
Totem-pole
–
Pull-up/-down
–
Wired-AND
–
Wired-OR
–
Bus-keeper
–
Inverted I/O
Configuration of multiple pins in a single operation
Read-Modify-Write (RMW) support
Toggle/clear/set registers for Output and Direction registers
Clock output on port pin
Event Channel 0 output on port pin 7
Mapping of port registers (virtual ports) into bit accessible I/O memory space
Overview
The XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asynchronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
15.3
I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate
functions.
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15.3.1
Push-pull
Figure 15-1. I/O configuration - Totem-pole
DIRn
OUTn
Pn
INn
15.3.2
Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn
OUTn
Pn
INn
15.3.3
Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn
Pn
INn
15.3.4
Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper
DIRn
OUTn
Pn
INn
15.3.5
Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down
OUTn
Pn
INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up
INn
Pn
OUTn
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15.4
Input sensing
•
•
•
•
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 15-7 on page 30.
Figure 15-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
D Q D Q
INVERTED I/O
R
EDGE
DETECT
Event
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5
Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can
be individually selected as source for each of the interrupts. The interrupts are then triggered
according to the input sense configuration for each pin configured as source for the interrupt.
15.6
Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 49 shows which modules on peripherals that enable alternate functions on a pin, and
which alternate functions that are available on a pin.
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16. T/C - 16-bits Timer/Counter with PWM
16.1
Features
• Seven 16-bit Timer/Counters
•
•
•
•
•
•
•
•
•
•
•
•
16.2
– Four Timer/Counters of type 0
– Three Timer/Counters of type 1
Four Compare or Capture (CC) Channels in Timer/Counter 0
Two Compare or Capture (CC) Channels in Timer/Counter 1
Double Buffered Timer Period Setting
Double Buffered Compare or Capture Channels
Waveform Generation:
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
– Frequency Generation
Input Capture:
– Input Capture with Noise Cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
Event Counter with Direction Control
Timer Overflow and Timer Error Interrupts and Events
One Compare Match or Capture Interrupt and Event per CC Channel
Supports DMA Operation
Hi-Resolution Extension (Hi-Res)
Advanced Waveform Extension (AWEX)
Overview
XMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The
difference between them is that Timer/Counter 0 has four Compare/Capture channels, while
Timer/Counter 1 has two Compare/Capture channels.
The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the
microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of
Timer and Compare registers are double buffered to ensure glitch free operation. Single slope
PWM, dual slope PWM and frequency generation waveforms can be generated using the Compare Channels.
Through the Event System, any input pin or event in the microcontroller can be used to trigger
input capture, hence no dedicated pins is required for this. The input capture has a noise canceller to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width
measurements.
A wide range of interrupt or event sources are available, including T/C Overflow, Compare
match and Capture for each Compare/Capture channel in the T/C.
PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF
has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1,
TCE0, TCE1 and TCF0, respectively.
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Control Logic
Counter
Event
System
clkPER4
Buffer
Capture
Control
Waveform
Generation
DTI
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORT
Comparator
AWeX
Hi-Res
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by
2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on
page 34 for more details.
The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See ”AWEX - Advanced
Waveform Extension” on page 33 for more details.
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17. AWEX - Advanced Waveform Extension
17.1
Features
•
•
•
•
•
•
•
•
17.2
Output with complementary output from each Capture channel
Four Dead Time Insertion (DTI) Units, one for each Capture channel
8-bit DTI Resolution
Separate High and Low Side Dead-Time Setting
Double Buffered Dead-Time
Event Controlled Fault Protection
Single Channel Multiple Output Operation (for BLDC motor control)
Double Buffered Pattern Generation
Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in
Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for
example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.
Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any
AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that
enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG
output with dead time insertion between LS and HS switching. The DTI output will override the
normal port value according to the port override setting. Optionally the final output can be
inverted by using the invert I/O setting for the port pin.
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from Compare Channel A can be distributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is
bypassed.
The Fault Protection unit is connected to the Event System. This enables any event to trigger a
fault condition that will disable the AWEX output. Several event channels can be used to trigger
fault on several different conditions.
The AWEX is available for TCC0. The notation of this is AWEXC.
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18. Hi-Res - High Resolution Extension
18.1
Features
• Increases Waveform Generator resolution by 2-bits (4x)
• Supports Frequency, single- and dual-slope PWM operation
• Supports the AWEX when this is enabled and used for the same Timer/Counter
18.2
Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running
at four times the CPU clock speed will be as input to the Timer/Counter.
The High Resolution Extension can also be used when an AWEX is enabled and used with a
Timer/Counter.
XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each
Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are
HIRESC, HIRESD, HIRESE and HIRESF, respectively.
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19. RTC - Real-Time Counter
19.1
Features
•
•
•
•
•
•
19.2
16-bit Timer
Flexible Tick resolution ranging from 1 Hz to 32.768 kHz
One Compare register
One Period register
Clear timer on Overflow or Compare Match
Overflow or Compare Match event and interrupt generation
Overview
The XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an
accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the
32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare
register. For details, see Figure 19-1.
A wide range of Resolution and Time-out periods can be configured using the RTC. With a maximum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1
second, the maximum time-out period is over 18 hours (65536 seconds).
Figure 19-1. Real-time Counter overview
Period
Overflow
32.768 kHz
=
10-bit
prescaler
1.024 kHz
Counter
=
Compare Match
Compare
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20. TWI - Two Wire Interface
20.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
20.2
Two Identical TWI peripherals
Simple yet Powerful and Flexible Communication Interface
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when in Sleep Mode
I2C and System Management Bus (SMBus) compatible
Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 individually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
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21. SPI - Serial Peripheral Interface
21.1
Features
•
•
•
•
•
•
•
•
•
21.2
Three Identical SPI peripherals
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer
between different devices. Devices can communicate using a master-slave scheme, and data is
transferred both to and from the devices simultaneously.
PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID,
and SPIE respectively.
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22. USART
22.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
22.2
Seven Identical USART peripherals
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High-resolution Arithmetic Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
Master SPI mode for SPI communication
IrDA support through the IRCOM module
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only.
Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0,
USARTE1 and USARTF0, respectively.
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23. IRCOM - IR Communication Module
23.1
Features
• Pulse modulation/demodulation for infrared communication
• Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps
• Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
• Built in filtering
• Can be connected to and used by one USART at a time
23.2
Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with
baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,
fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation disabled. There is one IRCOM available which can be connected to any USART to enable infrared
pulse coding/decoding for that USART.
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24. Crypto Engine
24.1
Features
• Data Encryption Standard (DES) CPU instruction
• Advanced Encryption Standard (AES) Crypto module
• DES Instruction
– Encryption and Decryption
– Single-cycle DES instruction
– Encryption/Decryption in 16 clock cycles per 8-byte block
• AES Crypto Module
– Encryption and Decryption
– Support 128-bit keys
– Support XOR data load mode to the State memory for Cipher Block Chaining
– Encryption/Decryption in 375 clock cycles per 16-byte block
24.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used encryption standards. These are supported through an AES peripheral module and
a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and
DES encrypted communication and data storage.
DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte
data blocks must be loaded into the Register file, and then DES must be executed 16 times to
encrypt/decrypt the data block.
The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.
The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is
done and decrypted/encrypted data can be read out, and an optional interrupt can be generated.
The AES Crypto Module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully
loaded.
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25. ADC - 12-bit Analog to Digital Converter
25.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
25.2
Two ADCs with 12-bit resolution
2 Msps sample rate for each ADC
Signed and Unsigned conversions
4 result registers with individual input channel control for each ADC
8 single ended inputs for each ADC
8x4 differential inputs for each ADC
4 internal inputs:
–
Integrated Temperature Sensor
–
DAC Output
–
VCC voltage divided by 10
–
Bandgap voltage
Software selectable gain of 2, 4, 8, 16, 32 or 64
Software selectable resolution of 8- or 12-bit.
Internal or External Reference selection
Event triggered conversion for accurate timing
DMA transfer of conversion results
Interrupt/Event on compare result
Overview
XMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 25-1 on page 42.
The two ADC modules can be operated simultaneously, individually or synchronized.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 million samples per second. The input selection is flexible, and both
single-ended and differential measurements can be done. For differential measurements an
optional gain stage is available to increase the dynamic range. In addition several internal signal
inputs are available. The ADC can provide both signed and unsigned results.
This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each
stage convert one part of the result. The pipeline design enables high sample rate at low clock
speeds, and remove limitations on samples speed versus propagation delay. This also means
that a new analog voltage can be sampled and a new ADC measurement started while other
ADC measurements are ongoing.
ADC measurements can either be started by application software or an incoming event from
another peripheral in the device. Four different result registers with individual input selection
(MUX selection) are provided to make it easier for the application to keep track of the data. Each
result register and MUX selection pair is referred to as an ADC Channel. It is possible to use
DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external analog reference voltages can be used. An accurate internal 1.0V
reference is available.
An integrated temperature sensor is available and the output from this can be measured with the
ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the
ADC.
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Figure 25-1. ADC overview
Channel A MUX selection
Channel C MUX selection
Channel D MUX selection
Configuration
Reference selection
Pin inputs
Channel A
Register
Channel B
Register
Pin inputs
Internal inputs
Channel B MUX selection
ADC
Channel C
Register
1-64 X
Event
Trigger
Channel D
Register
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB,
respectively.
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26. DAC - 12-bit Digital to Analog Converter
26.1
Features
•
•
•
•
•
•
•
•
26.2
One DAC with 12-bit resolution
Up to 1 Msps conversion rate for each DAC
Flexible conversion range
Multiple trigger sources
1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC
Built-in offset and gain calibration
High drive capabilities
Low Power Mode
Overview
The XMEGA A3 features one two-channel, 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 26-1 on page 43.
A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage
as the upper limit for conversion, but it is also possible to use the supply voltage or any applied
voltage in-between. The external reference input is shared with the ADC reference input.
Figure 26-1. DAC overview
Configuration
Reference selection
Channel A
Register
Channel A
DAC
Channel B
Channel B
Register
Event
Trigger
The DAC has one continuous output with high drive capabilities for both resistive and capacitive
loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H)
channels, each with separate data conversion registers.
A DAC conversion may be started from the application software by writing the data conversion
registers. The DAC can also be configured to do conversions triggered by the Event System to
have regular timing, independent of the application software. DMA may be used for transferring
data from memory locations to DAC data registers.
The DAC has a built-in calibration system to reduce offset and gain error when loading with a
calibration value from software.
PORTB each has one DAC. Notation of this peripheral is DACB.
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27. AC - Analog Comparator
27.1
Features
• Four Analog Comparators
• Selectable Power vs. Speed
• Selectable hysteresis
– 0, 20 mV, 50 mV
• Analog Comparator output available on pin
• Flexible Input Selection
– All pins on the port
– Output from the DAC
– Bandgap reference voltage.
– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
• Interrupt and event generation on
– Rising edge
– Falling edge
– Toggle
• Window function interrupt and event generation on
– Signal above window
– Signal inside window
– Signal below window
27.2
Overview
XMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two voltages, and the output indicates which input is largest. The Analog Comparator may be configured
to give interrupt requests and/or events upon several different combinations of input change.
Both hysteresis and propagation delays may be adjusted in order to find the optimal operation
for each application.
A wide range of input selection is available, both external pins and several internal signals can
be used.
The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They
have identical behavior but separate control registers.
Optionally, the state of the comparator is directly available on a pin.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 27-1. Analog comparator overview
Pin inputs
Internal inputs
+
Pin 0 output
AC0
Pin inputs
-
Internal inputs
VCC scaled
Interrupt
sensitivity
control
Pin inputs
Interrupts
Events
Internal inputs
+
AC1
Pin inputs
-
Internal inputs
VCC scaled
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27.3
Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped
in a pair may be used to realize a window function. One pair of analog comparators is shown in
Figure 27-1 on page 45.
• Input selection from pin
– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator
– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator
• Internal signals available on positive analog comparator inputs
– Output from 12-bit DAC
• Internal signals available on negative analog comparator inputs
– 64-level scaler of the VCC, available on negative analog comparator input
– Bandgap voltage reference
• Output from 12-bit DAC
27.4
Window Function
The window function is realized by connecting the external inputs of the two analog comparators
in a pair as shown in Figure 27-2.
Figure 27-2. Analog comparator window function
+
AC0
Upper limit of window
Interrupt
sensitivity
control
Input signal
Interrupts
Events
+
AC1
Lower limit of window
-
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28. OCD - On-chip Debug
28.1
Features
• Complete Program Flow Control
– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
Debugging on C and high-level language source code level
Debugging on Assembler and disassembler level
1 dedicated program address or source level breakpoint for AVR Studio / debugger
4 Hardware Breakpoints
Unlimited Number of User Program Breakpoints
Unlimited Number of User Data Breakpoints, with break on:
– Data location read, write or both read and write
– Data location content equal or not equal to a value
– Data location content is greater or less than a value
– Data location content is within or outside a range
– Bits of a data location are equal or not equal to a value
• Non-Intrusive Operation
– No hardware or software resources in the device are used
• High Speed Operation
– No limitation on debug/programming clock frequency versus system clock frequency
•
•
•
•
•
•
28.2
Overview
The XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s
development tools - provides all the necessary functions to debug an application. It has support
for program and data breakpoints, and can debug an application from C and high level language
source code level, as well as assembler and disassembler level. It has full Non-Intrusive Operation and no hardware or software resources in the device are used. The ODC system is
accessed through an external debugging tool which connects to the JTAG or PDI physical interfaces. Refer to ”Program and Debug Interfaces” on page 48.
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29. Program and Debug Interfaces
29.1
Features
•
•
•
•
•
29.2
PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
JTAG Interface (IEEE std. 1149.1 compliant)
Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)
Access to the OCD system
Programming of Flash, EEPROM, Fuses and Lock Bits
Overview
The programming and debug facilities are accessed through the JTAG and PDI physical interfaces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no
general purpose pins are used. JTAG uses four general purpose pins on PORTB.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
29.3
IEEE 1149.1 (JTAG) Boundary-scan
The JTAG physical layer handles the basic low-level serial communication over four I/O lines
named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and
boundary scan.
29.3.1
Boundary-scan Order
Table 30-8 on page 53 shows the Scan order between TDI and TDO when the Boundary-scan
chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned
out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain,
since these pins constitute the TAP pins when the JTAG is enabled.
29.3.2
Boundary-scan Description Language Files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
ATxmega256/192/128/64A3 devices.
See Table 30-8 on page 53 for ATxmega256/192/128/64A3 Boundary Scan Order.
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30. Pinout and Pin Functions
The pinout of XMEGA A3 is shown ”” on page 2. In addition to general I/O functionality, each pin
may have several function. This will depend on which peripheral is enabled and connected to
the actual pin. Only one of the alternate pin functions can be used at time.
30.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
30.1.1
30.1.2
30.1.3
30.1.4
Operation/Power Supply
VCC
Digital supply voltage
AVCC
Analog supply voltage
GND
Ground
Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
Analog functions
ACn
Analog Comparator input pin n
AC0OUT
Analog Comparator 0 Output
ADCn
Analog to Digital Converter input pin n
DACn
Digital to Analog Converter output pin n
AREF
Analog Reference input pin
Timer/Counter and AWEX functions
OCnx
Output Compare Channel x for Timer/Counter n
OCnx
Inverted Output Compare Channel x for Timer/Counter n
OCnxLS
Output Compare Channel x Low Side for Timer/Counter n
OCnxHS
Output Compare Channel x High Side for Timer/Counter n
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30.1.5
30.1.6
30.1.7
Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
Serial Clock In for TWI when external driver interface is enabled
SCLOUT
Serial Clock Out for TWI when external driver interface is enabled
SDAIN
Serial Data In for TWI when external driver interface is enabled
SDAOUT
Serial Data Out for TWI when external driver interface is enabled
XCKn
Transfer Clock for USART n
RXDn
Receiver Data for USART n
TXDn
Transmitter Data for USART n
SS
Slave Select for SPI
MOSI
Master Out Slave In for SPI
MISO
Master In Slave Out for SPI
SCK
Serial Clock for SPI
Oscillators, Clock and Event
TOSCn
Timer Oscillator pin n
XTALn
Input/Output for inverting Oscillator pin n
CLKOUT
Peripheral Clock Output
EVOUT
Event Channel 0 Output
Debug/System functions
RESET
Reset pin
PDI_CLK
Program and Debug Interface Clock pin
PDI_DATA
Program and Debug Interface Data pin
TCK
JTAG Test Clock
TDI
JTAG Test Data In
TDO
JTAG Test Data Out
TMS
JTAG Test Mode Select
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30.2
Alternate Pin Functions
The tables below show the main and alternate pin functions for all pins on each port. They also
show which peripheral that makes use of or enables the alternate pin function.
Table 30-1.
PORT A
Port A - Alternate functions
PIN #
INTERRUPT
ADCA POS
ADCA NEG
ADCA
GAINPOS
SYNC
ADC0
ADC0
ADC0
ADCA
GAINNEG
ACA POS
ACA NEG
AC0
AC0
ADC1
AC1
AC1
ADC2
AC2
GND
60
AVCC
61
PA0
62
PA1
63
SYNC
ADC1
ADC1
PA2
64
SYNC/ASYNC
ADC2
ADC2
PA3
1
SYNC
ADC3
ADC3
PA4
2
SYNC
ADC4
PA5
3
SYNC
ADC5
ADC5
ADC5
AC5
PA6
4
SYNC
ADC6
ADC6
ADC6
AC6
PA7
5
SYNC
ADC7
ADC7
ADC7
Table 30-2.
ADC3
ADC4
AC3
ADC4
REFA
AREF
AC3
AC4
AC5
AC7
AC0 OUT
Port B - Alternate functions
PIN #
INTERRUPT
ADCB
POS
ADCB
NEG
ADCB
GAINPOS
PB0
6
SYNC
ADC0
ADC0
ADC0
PB1
7
SYNC
ADC1
ADC1
PB2
8
SYNC/ASYNC
ADC2
ADC2
PB3
9
SYNC
ADC3
ADC3
ADC3
AC3
PB4
10
SYNC
ADC4
ADC4
PB5
11
SYNC
ADC5
ADC5
ADC5
AC5
PB6
12
SYNC
ADC6
ADC6
ADC6
AC6
PB7
13
SYNC
ADC7
ADC7
ADC7
GND
14
VCC
15
PORT B
ACA OUT
ADCB
GAINNEG
ACB POS
ACB NEG
AC0
AC0
ADC1
AC1
AC1
ADC2
AC2
ADC4
ACB OUT
DACB
REFB
JTAG
AREF
DAC0
AC3
DAC1
AC4
TMS
AC5
TDI
TCK
AC7
AC0 OUT
TDO
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Table 30-3.
PORT C
Port C - Alternate functions
PIN #
INTERRUPT
TCC0
AWEXC
PC0
16
SYNC
OC0A
OC0ALS
PC1
17
SYNC
OC0B
OC0AHS
XCK0
PC2
18
SYNC/ASYNC
OC0C
OC0BLS
RXD0
PC3
19
SYNC
OC0D
OC0BHS
PC4
20
SYNC
OC0CLS
OC1A
PC5
21
SYNC
OC0CHS
OC1B
PC6
22
SYNC
PC7
23
SYNC
GND
24
VCC
25
Table 30-4.
PORT D
TCC1
USARTC0
USARTC1
SPIC
TWIC
CLKOUT
EVOUT
SCL
TXD0
SS
XCK1
MOSI
OC0DLS
RXD1
MISO
OC0DHS
TXD1
SCK
Port D - Alternate functions
PIN #
INTERRUPT
TCD0
26
SYNC
OC0A
PD1
27
SYNC
OC0B
XCK0
PD2
28
SYNC/ASYNC
OC0C
RXD0
PD3
29
SYNC
OC0D
PD4
30
SYNC
OC1A
PD5
31
SYNC
OC1B
XCK1
MOSI
PD6
32
SYNC
RXD1
MISO
PD7
33
SYNC
TXD1
SCK
GND
34
VCC
35
PORT E
EVENTOUT
SDA
PD0
Table 30-5.
CLOCKOUT
TCD1
USARTD0
USARTD1
SPID
CLOCKOUT
EVENTOUT
CLKOUT
EVOUT
TXD0
SS
Port E - Alternate functions
PIN #
INTERRUPT
TCE0
TCE1
USARTE0
USARTE1
SPIE
PE0
36
SYNC
OC0A
PE1
37
SYNC
OC0B
XCK0
PE2
38
SYNC/ASYNC
OC0C
RXD0
PE3
39
SYNC
OC0D
TXD0
PE4
40
SYNC
OC1A
PE5
41
SYNC
OC1B
XCK1
MOSI
PE6
42
SYNC
RXD1
MISO
PE7
43
SYNC
TXD1
SCK
GND
44
VCC
45
TWIE
CLOCKOUT
EVENTOUT
TOSC
SDA
SCL
SS
TOSC2
CLKOUT
EVOUT
TOSC1
52
8068U–AVR–06/2013
Not recommended for new designs Use XMEGA A3U series
XMEGA A3
Port F - Alternate functions
Table 30-6.
PORT F
PIN #
INTERRUPT
TCF0
PF0
46
SYNC
OC0A
PF1
47
SYNC
OC0B
XCK0
PF2
48
SYNC/ASYNC
OC0C
RXD0
PF3
49
SYNC
OC0D
TXD0
PF4
50
SYNC
PF5
51
SYNC
PF6
54
SYNC
PF7
55
SYNC
GND
52
VCC
53
Table 30-7.
PORT R
USARTF0
Port R- Alternate functions
PIN #
INTERRUPT
PROGR
XTAL
PDI
56
PDI_DATA
RESET
57
PDI_CLOCK
PRO
58
SYNC
XTAL2
PR1
59
SYNC
XTAL1
Table 30-8.
Bit Number
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
ATxmega256/192/128/64A3 Boundary Scan Order
Signal Name
PQ3.Bidir
PQ3.Control
PQ2.Bidir
PQ2.Control
PQ1.Bidir
PQ1.Control
PQ0.Bidir
PQ0.Control
PK7.Bidir
PK7.Control
PK6.Bidir
PK6.Control
PK5.Bidir
PK5.Control
PK4.Bidir
PK4.Control
PK3.Bidir
PK3.Control
PK2.Bidir
PK2.Control
PK1.Bidir
PK1.Control
PK0.Bidir
PK0.Control
Module
PORT Q
PORT K
53
8068U–AVR–06/2013
Not recommended for new designs Use XMEGA A3U series
XMEGA A3
Bit Number
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
Signal Name
PJ7.Bidir
PJ7.Control
PJ6.Bidir
PJ6.Control
PJ5.Bidir
PJ5.Control
PJ4.Bidir
PJ4.Control
PJ3.Bidir
PJ3.Control
PJ2.Bidir
PJ2.Control
PJ1.Bidir
PJ1.Control
PJ0.Bidir
PJ0.Control
PH7.Bidir
PH7.Control
PH6.Bidir
PH6.Control
PH5.Bidir
PH5.Control
PH4.Bidir
PH4.Control
PH3.Bidir
PH3.Control
PH2.Bidir
PH2.Control
PH1.Bidir
PH1.Control
PH0.Bidir
PH0.Control
PF7.Bidir
PF7.Control
PF6.Bidir
PF6.Control
PF5.Bidir
PF5.Control
PF4.Bidir
PF4.Control
PF3.Bidir
PF3.Control
PF2.Bidir
PF2.Control
PF1.Bidir
PF1.Control
PF0.Bidir
PF0.Control
PE7.Bidir
PE7.Control
PE6.Bidir
PE6.Control
PE5.Bidir
PE5.Control
PE4.Bidir
PE4.Control
PE3.Bidir
PE3.Control
PE2.Bidir
PE2.Control
PE1.Bidir
PE1.Control
PE0.Bidir
PE0.Control
Module
PORT J
PORT H
PORT F
PORT E
54
8068U–AVR–06/2013
Not recommended for new designs Use XMEGA A3U series
XMEGA A3
Bit Number
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Signal Name
PD7.Bidir
PD7.Control
PD6.Bidir
PD6.Control
PD5.Bidir
PD5.Control
PD4.Bidir
PD4.Control
PD3.Bidir
PD3.Control
PD2.Bidir
PD2.Control
PD1.Bidir
PD1.Control
PD0.Bidir
PD0.Control
PC7.Bidir
PC7.Control
PC6.Bidir
PC6.Control
PC5.Bidir
PC5.Control
PC4.Bidir
PC4.Control
PC3.Bidir
PC3.Control
PC2.Bidir
PC2.Control
PC1.Bidir
PC1.Control
PC0.Bidir
PC0.Control
PB3.Bidir
PB3.Control
PB2.Bidir
PB2.Control
PB1.Bidir
PB1.Control
PB0.Bidir
PB0.Control
PA7.Bidir
PA7.Control
PA6.Bidir
PA6.Control
PA5.Bidir
PA5.Control
PA4.Bidir
PA4.Control
PA3.Bidir
PA3.Control
PA2.Bidir
PA2.Control
PA1.Bidir
PA1.Control
PA0.Bidir
PA0.Control
PR1.Bidir
PR1.Control
PR0.Bidir
PR0.Control
RESET.Observe_Only
PDI_DATA.Observe_Only
Module
PORT D
PORT C
PORT B
PORT A
PORT R
RESET
PDI Data
55
8068U–AVR–06/2013
Not recommended for new designs Use XMEGA A3U series
XMEGA A3
31. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA A3. For
complete register description and summary for each peripheral module, refer to the XMEGA A
Manual.
Base Address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x00C0
0x0100
0x0180
0x01C0
0x0200
0x0240
0x0320
0x0380
0x0390
0x0400
0x0480
0x04A0
0x0600
0x0620
0x0640
0x0660
0x0680
0x06A0
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08B0
0x08C0
0x08F8
0x0900
0x0940
0x0990
0x09A0
0x09B0
0x09C0
0x0A00
0x0A40
0x0A80
0x0A90
0x0AA0
0x0AB0
0x0AC0
0x0B00
0x0B90
0x0BA0
Name
Description
GPIO
VPORT0
VPORT1
VPORT2
VPORT3
CPU
CLK
SLEEP
OSC
DFLLRC32M
DFLLRC2M
PR
RST
WDT
MCU
PMIC
PORTCFG
AES
DMA
EVSYS
NVM
ADCA
ADCB
DACB
ACA
ACB
RTC
TWIC
TWIE
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTR
TCC0
TCC1
AWEXC
HIRESC
USARTC0
USARTC1
SPIC
IRCOM
TCD0
TCD1
HIRESD
USARTD0
USARTD1
SPID
TCE0
TCE1
AWEXE
HIRESE
USARTE0
USARTE1
SPIE
TCF0
HIRESF
USARTF0
General Purpose IO Registers
Virtual Port 0
Virtual Port 1
Virtual Port 2
Virtual Port 2
CPU
Clock Control
Sleep Controller
Oscillator Control
DFLL for the 32 MHz Internal RC Oscillator
DFLL for the 2 MHz RC Oscillator
Power Reduction
Reset Controller
Watch-Dog Timer
MCU Control
Programmable MUltilevel Interrupt Controller
Port Configuration
AES Module
DMA Controller
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog to Digital Converter on port B
Digital to Analog Converter on port B
Analog Comparator pair on port A
Analog Comparator pair on port B
Real Time Counter
Two Wire Interface on port C
Two Wire Interfaceon port E
Port A
Port B
Port C
Port D
Port E
Port F
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
USART 1 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port D
Timer/Counter 1 on port D
High Resolution Extension on port D
USART 0 on port D
USART 1 on port D
Serial Peripheral Interface on port D
Timer/Counter 0 on port E
Timer/Counter 1 on port E
Advanced Waveform Extensionon port E
High Resolution Extension on port E
USART 0 on port E
USART 1 on oirt E
Serial Peripheral Interface on port E
Timer/Counter 0 on port F
High Resolution Extension on port F
USART 0 on port F
56
8068U–AVR–06/2013
Not recommended for new designs Use XMEGA A3U series
XMEGA A3
32. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
Rd, Rr
Add without Carry
Rd
Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd
Rd + Rr + C
Z,C,N,V,S,H
1
ADIW
Rd, K
Add Immediate to Word
Rd
Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd
Rd + 1:Rd - K
Z,C,N,V,S
2
ADD
AND
Rd, Rr
Logical AND
Rd
Rd Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
Rd K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
Rd Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
Rd ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
Rd Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
Rd Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0
Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0
Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0
Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0
Rd x Rr
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