8-bit Atmel XMEGA AU Microcontroller
XMEGA AU MANUAL
This document contains complete and detailed description of all modules included in
the Atmel®AVR®XMEGA®AU microcontroller family. The Atmel AVR XMEGA AU is a
family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit
microcontrollers based on the AVR enhanced RISC architecture. The available Atmel
AVR XMEGA AU modules described in this manual are:
Atmel AVR CPU
Memories
DMAC - Direct memory access controller
Event system
System clock and clock options
Power management and sleep modes
System control and reset
Battery backup system
WDT - Watchdog timer
Interrupts and programmable multilevel interrupt controller
PORT - I/O ports
TC - 16-bit timer/counters
AWeX - Advanced waveform extension
Hi-Res - High resolution extension
RTC - Real-time counter
RTC32 - 32-bit real-time counter
USB - Universal serial bus interface
TWI - Two-wire serial interface
SPI - Serial peripheral interface
USART - Universal synchronous and asynchronous serial receiver and transmitter
IRCOM - Infrared communication module
AES and DES cryptographic engine
CRC - Cyclic redundancy check
EBI - External bus interface
ADC - Analog-to-digital converter
DAC - Digital-to-analog converter
AC - Analog comparator
IEEE 1149.1 JTAG interface
PDI - Program and debug interface
Memory programming
Peripheral address map
Register summary
Interrupt vector summary
Instruction set summary
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1.
About the Manual
This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA AU
microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals
and modules described in this manual may not be present in all Atmel AVR XMEGA AU devices.
For all device-specific information such as characterization data, memory sizes, modules, peripherals available and their
absolute memory addresses, refer to the device datasheets. When several instances of a peripheral exists in one device,
each instance will have a unique name. For example each port module (PORT) have unique name, such as PORTA,
PORTB, etc. Register and bit names are unique within one module instance.
For more details on applied use and code examples for peripherals and modules, refer to the Atmel AVR XMEGA
specific application notes available from http://www.atmel.com/avr.
1.1
Reading the Manual
The main sections describe the various modules and peripherals. Each section contains a short feature list and overview
describing the module. The remaining section describes the features and functions in more detail.
The register description sections list all registers and describe each register, bit and flag with their function. This includes
details on how to set up and enable various features in the module. When multiple bits are needed for a configuration
setting, these are grouped together in a bit group. The possible bit group configurations are listed for all bit groups
together with their associated Group Configuration and a short description. The Group Configuration refers to the defined
configuration name used in the Atmel AVR XMEGA assembler header files and application note source code.
The register summary sections list the internal register map for each module type.
The interrupt vector summary sections list the interrupt vectors and offset address for each module type.
1.2
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download from
http://www.atmel.com/avr.
1.3
Recommended Reading
Atmel AVR XMEGA AU device datasheets
XMEGA application notes
This manual contains general modules and peripheral descriptions. The AVR XMEGA AU device datasheets contains the device-specific information. The XMEGA application notes and AVR Software Framework contain example code and show applied use of the modules and peripherals.
For new users, it is recommended to read the AVR1000 - Getting Started Writing C Code for Atmel XMEGA, and
AVR1900 - Getting Started with Atmel ATxmega128A1 application notes.
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2.
Overview
The AVR XMEGA AU microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit
microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the Atmel AVR XMEGA AU devices achieve throughputs approaching one million instructions per second (MIPS)
per megahertz, allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The Atmel AVR XMEGA AU devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller; eight-channel event system and programmable
multilevel interrupt controller; up to 78 general purpose I/O lines; 16- or 32-bit real-time counter (RTC); up to eight
flexible, 16-bit timer/counters with capture, compare and PWM modes; up to eight USARTs; up to four I2C and SMBUS
compatible two-wire serial interfaces (TWIs); one full-speed USB 2.0 interface; up to four serial peripheral interfaces
(SPIs); CRC module; AES and DES cryptographic engine; up to two 16-channel, 12-bit ADCs with programmable gain;
up to two 2-channel, 12-bit DACs; up to four analog comparators with window mode; programmable watchdog timer with
separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. Selected
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug and
programming.
The Atmel AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while
allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The
power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the
next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter
continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby
mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup
from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and
the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with In-system, self-programmable flash, the Atmel AVR XMEGA is a powerful microcontroller family
that provides a highly flexible and cost effective solution for many embedded applications.
The Atmel AVR XMEGA AU devices are supported with a full suite of program and system development tools, including
C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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2.1
Block Diagram
Figure 2-1. Atmel AVR XMEGA AU block diagram.
Oscillator / Crystal / Clock
General Purpose I/O
VBAT
Power
Supervision
32.768 kHz
XOSC
Battery Backup
Controller
Real Time
Counter
PORT Q (8)
EBI
PORT R (2)
Digital function
Analog function
Bus masters / Programming / Debug
Oscillator
Circuits/
Clock
Generation
Watchdog
Oscillator
Real Time
Counter
EVENT ROUTING NETWORK
Watchdog
Timer
DATA BUS
DACA
Event System
Controller
PORT A (8)
Power
Supervision
POR/BOD &
RESET
Oscillator
Control
SRAM
DMA
Controller
ACA
Sleep
Controller
PDI
ADCA
BUS
Matrix
AREFA
Prog/Debug
Controller
JTAG
Int. Refs.
PORT P (8)
AES
Tempref
PORT N (8)
OCD
AREFB
DES
PORT M (8)
Interrupt
Controller
CPU
ADCB
CRC
PORT L (8)
ACB
PORT K (8)
NVM Controller
PORT B (8)
PORT J (8)
Flash
E E P RO M
EBI
DACB
PORT H (8)
PORT G (8)
DATA BUS
PORT D (8)
SPIF
TWIF
TCF0:1
USARTF0:1
SPIE
PORT E (8)
TWIE
TCE0:1
USARTE0:1
USB
TWID
SPID
TCD0:1
USARTD0:1
SPIC
PORT C (8)
TWIC
TCC0:1
USARTC0:1
IRCOM
EVENT ROUTING NETWORK
PORT F (8)
In Table 2-1 on page 5 a feature summary for the XMEGA AU family is shown, split into one feature summary column for
each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet
for ordering codes and memory options.
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Table 2-1.
XMEGA AU feature summary overview.
Feature
Pins, I/O
Memory
Details / sub-family
A1U
A3U
A3BU
A4U
Total
100
64
64
44
Programmable I/O pins
78
50
47
34
Program memory (KB)
64 - 128
64 - 256
256
16 - 128
Boot memory (KB)
4-8
4-8
8
4-8
SRAM (KB)
4-8
4 - 16
16
2-8
EEPROM
2
2-4
4
1 -2
General purpose registers
16
16
16
16
100A
64A
64A
44A
–
64M2
64M2
44M1
100C1/100C2
–
–
49C2
TQFP
Package
QFN /VQFN
BGA
QTouch
Sense channels
56
56
56
56
DMA Controller
Channels
4
4
4
4
Channels
8
8
8
8
QDEC
3
3
3
3
0.4 - 16MHz XOSC
Yes
Yes
Yes
Yes
32.768 kHz TOSC
Yes
Yes
Yes
Yes
2MHz calibrated
Yes
Yes
Yes
Yes
32MHz calibrated
Yes
Yes
Yes
Yes
128MHz PLL
Yes
Yes
Yes
Yes
32.768kHz calibrated
Yes
Yes
Yes
Yes
32kHz ULP
Yes
Yes
Yes
Yes
TC0 - 16-bit, 4 CC
4
4
4
3
TC1 - 16-bit, 2 CC
4
3
2
2
TC2 - 2x 8-bit
4
4
4
2
Hi-Res
4
4
4
3
AWeX
4
2
2
1
RTC
1
1
Event System
Crystal Oscillator
Internal Oscillator
Timer / Counter
RTC32
1
Battery Backup System
Serial Communication
1
Yes
USB full-speed device
1
1
1
1
USART
8
7
6
5
SPI
4
3
3
2
TWI
4
2
2
2
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Feature
Crypto /CRC
Details / sub-family
A1U
A3U
A3BU
A4U
AES-128
Yes
Yes
Yes
Yes
DES
Yes
Yes
Yes
Yes
CRC-16
Yes
Yes
Yes
Yes
CRC-32
Yes
Yes
Yes
Yes
4
–
–
–
2
2
2
1
12
12
12
12
Sampling speed (kbps)
2000
2000
2000
2000
Input channels per ADC
16
16
16
12
Conversion channels
4
4
4
4
2
1
1
1
12
12
12
12
1000
1000
1000
1000
2
2
2
2
4
4
4
2
PDI
Yes
Yes
Yes
Yes
JTAG
Yes
Yes
Yes
Boundary scan
Yes
Yes
Yes
Chip selects
External Memory (EBI)
SRAM
Yes
SDRAM
Yes
Resolution (bits)
Analog to Digital
Converter (ADC)
Digital to Analog
Converter (DAC)
Resolution (bits)
Sampling speed (kbps)
Output channels per DAC
Analog Comparator (AC)
Program and Debug
Interface
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3.
3.1
AVR CPU
Features
8/16-bit, high-performance Atmel AVR RISC CPU
142 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
3.2
Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, “Interrupts and Programmable
Multilevel Interrupt Controller” on page 131.
3.3
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For a summary of all AVR instructions, refer to “Instruction Set Summary” on page
429. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 3-1. Block diagram of the AVR CPU architecture.
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The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for save storing of nonvolatile data in the program memory.
3.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit supports arithmetic and logic operations between registers or between a constant and a register.
Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose
registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status
register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
3.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
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3.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
3.6
Instruction Execution Timing
The AVR CPU is clocked by the CPU clock, clkCPU. No internal clock division is used. Figure 3-2 on page 9 shows the
parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register
file concept. This is the basic pipelining concept used to obtain up to 1MIPS/MHz performance with high power efficiency.
Figure 3-2. The parallel instruction fetches and instruction executions.
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 3-3 on page 9 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation
using two register operands is executed and the result is stored back to the destination register.
Figure 3-3. Single Cycle ALU Operation.
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
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3.7
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 429. This
will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact
code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
3.8
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
3.9
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
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Figure 3-4. AVR CPU general purpose working registers.
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
R26
The register file is located in a separate address space, and so the registers are not accessible as data memory.
3.9.1
The X-, Y-, and Z- Registers
Registers R26..R31 have added functions besides their general-purpose usage.
These registers can form 16-bit address pointers for addressing data memory. These three address registers are called
the X-register, Y-register, and Z-register. The Z-register can also be used as an address pointer to read from and/or write
to the flash program memory, signature rows, fuses, and lock bits.
Figure 3-5. The X-, Y- and Z-registers.
Bit (individually)
7
X-register
0
7
8
7
0
7
XH
Bit (X-register)
15
Bit (individually)
7
Y-register
R29
15
Bit (individually)
7
Z-register
R31
0
0
R28
YL
8
7
0
7
ZH
15
0
R26
XL
YH
Bit (Y-register)
Bit (Z-register)
R27
0
0
R30
ZL
8
7
0
The lowest register address holds the least-significant byte (LSB), and the highest register address holds the mostsignificant byte (MSB). In the different addressing modes, these address registers function as fixed displacement,
automatic increment, and automatic decrement (see “Instruction Set Summary” on page 429 for details).
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3.10
RAMP and Extended Indirect Registers
In order to access program memory or data memory above 64KB, the address pointer must be larger than 16 bits. This is
done by concatenating one register to one of the X-, Y-, or Z-registers. This register then holds the most-significant byte
(MSB) in a 24-bit address or address pointer.
These registers are available only on devices with external bus interface and/or more than 64KB of program or data
memory space. For these devices, only the number of bits required to address the whole program and data memory
space in the device is implemented in the registers.
3.10.1
RAMPX, RAMPY and RAMPZ Registers
The RAMPX, RAMPY and RAMPZ registers are concatenated with the X-, Y-, and Z-registers, respectively, to enable
indirect addressing of the whole data memory space above 64KB and up to 16MB.
Figure 3-6. The combined RAMPX + X, RAMPY + Y and RAMPZ + Z registers.
Bit (Individually)
7
0
7
0
RAMPX
Bit (X-pointer)
23
Bit (Individually)
7
XH
16
15
0
7
RAMPY
Bit (Y-pointer)
23
Bit (Individually)
7
16
15
0
7
8
7
0
7
16
0
0
YL
8
7
0
7
ZH
23
0
XL
YH
RAMPZ
Bit (Z-pointer)
7
0
0
ZL
15
8
7
0
When reading (ELPM) and writing (SPM) program memory locations above the first 128KB of the program memory,
RAMPZ is concatenated with the Z-register to form the 24-bit address. LPM is not affected by the RAMPZ setting.
3.10.2 RAMPD Register
This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB.
Together, RAMPD and the operand will form a 24-bit address.
Figure 3-7. The combined RAMPD + K register.
Bit (Individually)
7
Bit (D-pointer)
23
0
15
16
15
0
RAMPD
K
0
3.10.3 EIND - Extended Indirect Register
EIND is concatenated with the Z-register to enable indirect jump and call to locations above the first 128KB (64K words)
of the program memory.
Figure 3-8. The combined EIND + Z register.
Bit (Individually)
7
0
7
EIND
Bit (D-pointer)
23
0
7
ZH
16
15
0
ZL
8
7
0
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3.11
Accessing 16-bit Registers
The AVR data bus is 8 bits wide, and so accessing 16-bit registers requires atomic operations. These registers must be
byte-accessed using two read or write operations. 16-bit registers are connected to the 8-bit bus and a temporary register
using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte is then written
into the temporary register. When the high byte of the 16-bit register is written, the temporary register is copied into the
low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low byte register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the
low byte is read. When the high byte is read, it is then read from the temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when reading or writing
the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit register during an
atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when writing or reading 16-bit registers.
The temporary registers can also be read and written directly from user software.
3.11.1 Accessing 24- and 32-bit Registers
For 24- and 32-bit registers, the read and write access is done in the same way as described for 16-bit registers, except
there are two temporary registers for 24-bit registers and three for 32-bit registers. The least-significant byte must be
written first when doing a write, and read first when doing a read.
3.12
Configuration Change Protection
System critical I/O register settings are protected from accidental modification. The SPM instruction is protected from
accidental execution, and the LPM instruction is protected when reading the fuses and signature row. This is handled
globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or
execution of protected instructions, are only possible after the CPU writes a signature to the CCP register. The different
signatures are described in the register description.
There are two modes of operation: one for protected I/O registers, and one for the protected instructions, SPM/LPM.
3.12.1 Sequence for write operation to protected I/O registers
1.
The application code writes the signature that enable change of protected I/O registers to the CCP register.
2.
Within four instruction cycles, the application code must write the appropriate data to the protected register. Most
protected registers also contain a write enable/change enable bit. This bit must be written to one in the same operation as the data are written. The protected change is immediately disabled if the CPU performs write operations to
the I/O register or data memory or if the SPM, LPM, or SLEEP instruction is executed.
3.12.2 Sequence for execution of protected SPM/LPM
1.
The application code writes the signature for the execution of protected SPM/LPM to the CCP register.
2.
Within four instruction cycles, the application code must execute the appropriate instruction. The protected change
is immediately disabled if the CPU performs write operations to the data memory or if the SLEEP instruction is
executed.
Once the correct signature is written by the CPU, interrupts will be ignored for the duration of the configuration change
enable period. Any interrupt request (including non-maskable interrupts) during the CCP period will set the
corresponding interrupt flag as normal, and the request is kept pending. After the CCP period is completed, any pending
interrupts are executed according to their level and priority. DMA requests are still handled, but do not influence the
protected configuration change enable period. A signature written by DMA is ignored.
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3.13
Fuse Lock
For some system-critical features, it is possible to program a fuse to disable all changes to the associated I/O control
registers. If this is done, it will not be possible to change the registers from the user software, and the fuse can only be
reprogrammed using an external programmer. Details on this are described in the datasheet module where this feature is
available.
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3.14
Register Descriptions
3.14.1 CCP – Configuration Change Protection register
Bit
7
6
5
4
3
2
1
0
Read/Write
W
W
W
W
W
W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x04
CCP[7:0]
Bit 7:0 – CCP[7:0]: Configuration Change Protection
The CCP register must be written with the correct signature to enable change of the protected I/O register or execution of the protected instruction for a maximum period of four CPU instruction cycles. All interrupts are ignored
during these cycles. After these cycles, interrupts will automatically be handled again by the CPU, and any pending interrupts will be executed according to their level and priority. When the protected I/O register signature is
written, CCP[0] will read as one as long as the protected feature is enabled. Similarly when the protected
SPM/LPM signature is written, CCP[1] will read as one as long as the protected feature is enabled. CCP[7:2] will
always read as zero. Table 3-1 on page 15 shows the signature for the various modes.
Table 3-1.
Modes of CPU change protection.
Signature
Group configuration
Description
0x9D
SPM
Protected SPM/LPM
0xD8
IOREG
Protected IO register
3.14.2 RAMPD – Extended Direct Addressing register
This register is concatenated with the operand for direct addressing (LDS/STS) of the whole data memory space on
devices with more than 64KB of data memory. This register is not available if the data memory, including external
memory, is less than 64KB.
Bit
7
6
5
4
3
+0x08
2
1
0
RAMPD[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing Bits
These bits hold the MSB of the 24-bit address created by RAMPD and the 16-bit operand. Only the number of bits
required to address the available data memory is implemented for each device. Unused bits will always read as
zero.
3.14.3 RAMPX – Extended X-Pointer register
This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. This register is not available if the data memory, including
external memory, is less than 64KB.
Bit
7
6
5
4
+0x09
3
2
1
0
RAMPX[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
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Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of
bits required to address the available data memory is implemented for each device. Unused bits will always read
as zero.
3.14.4 RAMPY – Extended Y-Pointer register
This register is concatenated with the Y-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. This register is not available if the data memory, including
external memory, is less than 64KB.
Bit
7
6
5
4
+0x0A
3
2
1
0
RAMPY[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit 7:0 – RAMPY[7:0]: Extended Y-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPY and the 16-bit Y-register. Only the number of
bits required to address the available data memory is implemented for each device. Unused bits will always read
as zero.
3.14.5 RAMPZ – Extended Z-Pointer register
This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory
space on devices with more than 64KB of data memory. RAMPZ is concatenated with the Z-register when reading
(ELPM) program memory locations above the first 64KB and writing (SPM) program memory locations above the first
128KB of the program memory.
This register is not available if the data memory, including external memory and program memory in the device, is less
than 64KB.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
+0x0B
RAMPZ[7:0]
Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address Bits
These bits hold the MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register. Only the number of
bits required to address the available data and program memory is implemented for each device. Unused bits will
always read as zero.
3.14.6 EIND – Extended Indirect register
This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP) and call (EICALL) to the
whole program memory space on devices with more than 128KB of program memory. The register should be used for
jumps to addresses below 128KB if ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are
used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program
memory in the device is less than 128KB.
Bit
7
6
5
4
3
+0x0C
2
1
0
EIND[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
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Bit 7:0 – EIND[7:0]: Extended Indirect Address Bits
These bits hold the MSB of the 24-bit address created by EIND and the 16-bit Z-register. Only the number of bits
required to access the available program memory is implemented for each device. Unused bits will always read as
zero.
3.14.7 SPL – Stack Pointer register Low
The SPH and SPL stack pointer pair represent the 16-bit SP value. The SP holds the stack pointer that points to the top
of the stack. After reset, the stack pointer points to the highest internal SRAM address. To prevent corruption when
updating the stack pointer from software, a write to SPL will automatically disable interrupts for the next four instructions
or until the next I/O memory write.
Only the number of bits required to address the available data memory, including external memory, up to 64KB is
implemented for each device. Unused bits will always read as zero.
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
3
2
1
0
+0x0D
SP[7:0]
Read/Write
(1)
Initial Value
Note:
1.
Refer to specific device datasheets for exact size.
Bit 7:0 – SP[7:0]: Stack Pointer Low Byte
These bits hold the LSB of the 16-bit stack pointer (SP).
3.14.8 SPH – Stack Pointer register High
Bit
7
6
5
4
+0x0E
SP[15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value(1)
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Note:
1.
Refer to specific device datasheets for the exact size.
Bit 7:0 – SP[15:8]: Stack Pointer High Byte
These bits hold the MSB of the 16-bit stack pointer (SP).
3.14.9 SREG – Status register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. For details information about the bits in this register and how they are affected by the different instructions
see “Instruction Set Summary” on page 429.
Bit
7
+0x0F
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set for interrupts to be enabled. If the global interrupt enable register is
cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. This bit is not
cleared by hardware after an interrupt has occurred. This bit can be set and cleared by the application with the SEI
and CLI instructions, as described in “Instruction Set Summary” on page 429. Changing the I flag through the I/Oregister result in a one-cycle wait state on the access.
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Bit 6 – T: Bit Copy Storage
The bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for the operated
bit. A bit from a register in the register file can be copied into this bit by the BST instruction, and this bit can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 – H: Half Carry Flag
The half carry flag (H) indicates a half carry in some arithmetic operations. Half carry is useful in BCD arithmetic.
Bit 4 – S: Sign Bit, S = N V
The sign bit is always an exclusive or between the negative flag, N, and the two’s complement overflow flag, V.
Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag (V) supports two’s complement arithmetic.
Bit 2 – N: Negative Flag
The negative flag (N) indicates a negative result in an arithmetic or logic operation.
Bit 1 – Z: Zero Flag
The zero flag (Z) indicates a zero result in an arithmetic or logic operation.
Bit 0 – C: Carry Flag
The carry flag (C) indicates a carry in an arithmetic or logic operation.
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3.15
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
+0x00
Reserved
–
–
–
–
–
–
–
–
+0x01
Reserved
–
–
–
–
–
–
–
–
+0x02
Reserved
–
–
–
–
–
–
–
–
+0x03
Reserved
–
–
–
–
–
–
–
–
+0x04
CCP
+0x05
Reserved
–
–
–
–
–
–
–
–
+0x06
Reserved
–
–
–
–
–
–
–
–
+0x07
Reserved
–
–
–
–
–
–
–
–
+0x08
RAMPD
RAMPD[7:0]
15
+0x09
RAMPX
RAMPX[7:0]
15
+0x0A
RAMPY
RAMPY[7:0]
16
+0x0B
RAMPZ
RAMPZ[7:0]
16
+0x0C
EIND
EIND[7:0]
16
+0x0D
SPL
SPL[7:0]
17
+0x0E
SPH
SPH[7:0]
17
+0x0F
SREG
CCP[7:0]
I
T
H
S
Page
15
V
N
Z
C
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19
4.
Memories
4.1
Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or bootloader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose registers for global variables or flags
External memory support
SRAM
SDRAM
Memory mapped external hardware
Bus arbitration
Deterministic handling of priority between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM, I/O memory, and external memory access
Simultaneous bus access for CPU and DMA controller
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
4.2
Overview
This section describes the different memory sections. The AVR architecture has two main memory spaces, the program
memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the
program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile
data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces
can be locked for further write and read/write operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
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4.3
Flash Program Memory
All XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory
can be accessed for read and write from an external programmer through the PDI or from application software running in
the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section, as shown in Figure 4-1 on page 21. The sizes
of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have
different levels of protection. The store program memory (SPM) instruction, used to write to the flash from the application
software, will only operate when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 4-1. Flash memory sections.
0x000000
Application Flash
Section
Application Table
Flash Section
End Application
Start Boot Loader
Boot Loader Flash
Section
Flashend
4.3.1
Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
4.3.2
Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
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4.3.3
Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
4.3.4
Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions such as temperature, voltage
references, etc., refer to the device datasheet.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
4.3.5
User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
4.4
Fuses and Lockbits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
4.5
Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory,
if available. The data memory is organized as one continuous memory section, as shown in Figure 4-2 on page 23.
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Figure 4-2. Data memory map.
Start/End
Address
Data Memory
0x000000
I/O Memory
(Up to 4 KB)
0x001000
EEPROM
(Up to 4 KB)
0x002000
Internal SRAM
External Memory
(0 to 16 MB)
0xFFFFFF
I/O memory, EEPROM, and SRAM will always have the same start addresses for all XMEGA devices. The address
space for external memory will always start at the end of internal SRAM and end at address 0xFFFFFF.
4.6
Internal SRAM
The internal SRAM always starts at hexadecimal address 0x2000. SRAM is accessed by the CPU using the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions.
4.7
EEPROM
All XMEGA devices have EEPROM for nonvolatile data storage. It is addressable in a separate data space (default) or
memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000. However, flushing the buffer and erasing and writing pages must still be done through the NVM controller as for
I/O-mapped access.
4.8
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
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4.8.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
4.9
External Memory
Up to four ports are dedicated to external memory, supporting external SRAM, SDRAM, and memory mapped
peripherals such as LCD displays. For details, refer to “EBI – External Bus Interface” on page 319. The external memory
address space will always start at the end of internal SRAM.
4.10
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time. See Figure 4-3 on page 24.
The USB module acts as a bus master, and is connected directly to internal SRAM through a pseudo-dual-port (PDP)
interface.
Figure 4-3. Bus access.
DMA
CH0
CH1
CH2
CH3
CPU
External
Programming
AVR core
OCD
PDI
Bus matrix
Flash
EEPROM
Non-Volatile
Memory
Interrupt
Controller
USB
EBI
NVM
Controller
Power
Management
USART
External
Memory
AC
Event System
Controller
SPI
SRAM
ADC
Oscillator
Control
TWI
RAM
DAC
I/O
Timer /
Counter
Battery
Backup
Crypto
modules
Real Time
Counter
CRC
Peripherals and system modules
4.10.1 Bus Priority
When several masters request access to the same bus, the bus priority is in the following order (from higher to lower
priority):
1.
2.
3.
4.
Bus Master with ongoing access.
Bus Master with ongoing burst.
1. Alternating DMA controller read and DMA controller write when they access the same data memory section.
Bus Master requesting burst access.
1. CPU has priority.
Bus Master requesting bus access.
1.
CPU has priority.
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4.11
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External
memory has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the
external bus interface. Refer to the instruction summary for more details on instructions and instruction timing.
4.12
Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
4.13
JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
4.14
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism. For details, refer to “Configuration Change
Protection” on page 13.
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4.15
Register Description – NVM Controller
4.15.1 ADDR0 – Address register 0
The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value, ADDR. This is used for addressing all NVM
sections for read, write, and CRC operations.
Bit
7
6
5
4
+0x00
3
2
1
0
ADDR[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
3
2
1
0
Bit 7:0 – ADDR[7:0]: Address Byte 0
This register gives the address low byte when accessing NVM locations.
4.15.2 ADDR1 – Address register 1
Bit
7
6
5
4
+0x01
ADDR[15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7:0 – ADDR[15:8]: Address Byte 1
This register gives the address high byte when accessing NVM locations.
4.15.3 ADDR2 – Address register 2
Bit
7
6
5
4
+0x02
ADDR[23:16]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – ADDR[23:16]: Address Byte 2
This register gives the address extended byte when accessing NVM locations.
4.15.4 DATA0 – Data register 0
The DATA0, DATA1, and DATA registers represent the 24-bit value, DATA. This holds data during NVM read, write, and
CRC access.
Bit
7
6
5
4
+0x04
3
2
1
0
DATA[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DATA[7:0]: Data Byte 0
This register gives the data value byte 0 when accessing NVM locations.
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4.15.5 DATA1 – Data register 1
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
+0x05
DATA[15:8]
Bit 7:0 – DATA[15:8]: Data Byte 1
This register gives the data value byte 1 when accessing NVM locations.
4.15.6 DATA2 – Data register 2
Bit
7
6
5
4
+0x06
DATA[23:16]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
2
1
0
Bit 7:0 – DATA[23:16]: Data Byte 2
This register gives the data value byte 2 when accessing NVM locations.
4.15.7 CMD – Command Register
Bit
7
+0x0A
–
6
5
4
3
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
CMD[6:0]
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6:0 – CMD[6:0]: Command
These bits define the programming commands for the flash. Bit 6 is only set for external programming commands.
See “Memory Programming” on page 407” for programming commands.
4.15.8 CTRLA – Control register A
Bit
7
6
5
4
3
2
1
0
+0x0B
–
–
–
–
–
–
–
CMDEX
Read/Write
R
R
R
R
R
R
R
S
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – CMDEX: Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the configuration change
protection (CCP) mechanism. Refer to “Configuration Change Protection” on page 13 for details on the CCP.
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4.15.9 CTRLB – Control register B
Bit
7
6
5
4
3
2
1
0
+0x0C
–
–
–
–
EEMAPEN
FPRM
EPRM
SPMLOCK
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3 – EEMAPEN: EEPROM Data Memory Mapping Enable
Setting this bit enables data memory mapping of the EEPROM section. The EEPROM can then be accessed using
load and store instructions.
Bit 2 – FPRM: Flash Power Reduction Mode
Setting this bit enables power saving for the flash memory. If code is running from the application section, the boot
loader section will be turned off, and vice versa. If access to the section that is turned off is required, the CPU will
be halted for a time equal to the start-up time from the idle sleep mode.
Bit 1 – EPRM: EEPROM Power Reduction Mode
Setting this bit enables power saving for the EEPROM. The EEPROM will then be turned off in a manner equivalent to entering sleep mode. If access is required, the bus master will be halted for a time equal to the start-up time
from idle sleep mode.
Bit 0 – SPMLOCK: SPM Locked
This bit can be written to prevent all further self-programming. The bit is cleared at reset, and cannot be cleared
from software. This bit is protected by the configuration change protection (CCP) mechanism. Refer to “Configuration Change Protection” on page 13 for details on the CCP.
4.15.10 INTCTRL – Interrupt Control register
Bit
7
6
5
4
+0x0D
–
–
–
–
3
2
1
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPMLVL[1:0]
0
EELVL[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level
These bits enable the interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131. This is a level interrupt that will be triggered only when the NVMBUSY flag
in the STATUS register is set to zero. Thus, the interrupt should not be enabled before triggering an NVM command, as the NVMBUSY flag will not be set before the NVM command is triggered. The interrupt should be
disabled in the interrupt handler.
Bit 1:0 – EELVL[1:0]: EEPROM Ready Interrupt Level
These bits enable the EEPROM ready interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131. This is a level interrupt that will be triggered only when the
NVMBUSY flag in the STATUS register is set to zero. Thus, the interrupt should not be enabled before triggering
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an NVM command, as the NVMNVMBUSY flag will not be set before the NVM command is triggered. The interrupt
should be disabled in the interrupt handler.
4.15.11 STATUS – Status register
Bit
+0x04
7
6
5
4
3
2
1
0
NVMBUSY
FBUSY
–
–
–
–
EELOAD
FLOAD
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – NVMBUSY: Nonvolatile Memory Busy
The NVMBUSY flag indicates if the NVM (Flash, EEPROM, lock bit) is being programmed. Once an operation is
started, this flag is set and remains set until the operation is completed. The NVMBUSY flag is automatically
cleared when the operation is finished.
Bit 6 – FBUSY: Flash Busy
The FBUSY flag indicates if a flash programming operation is initiated. Once an operation is started, the FBUSY
flag is set and the application section cannot be accessed. The FBUSY flag is automatically cleared when the
operation is finished.
Bit 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – EELOAD: EEPROM Page Buffer Active Loading
The EELOAD flag indicates that the temporary EEPROM page buffer has been loaded with one or more data
bytes. It remains set until an EEPROM page write or a page buffer flush operation is executed. For more details,
see “Flash and EEPROM Programming Sequences” on page 409.
Bit 0 – FLOAD: Flash Page Buffer Active Loading
The FLOAD flag indicates that the temporary flash page buffer has been loaded with one or more data bytes. It
remains set until an application page write, boot page write, or page buffer flush operation is executed. For more
details, see “Flash and EEPROM Programming Sequences” on page 409.
4.15.12 LOCKBITS – Lock Bit register
Bit
7
+0x07
6
5
4
3
BLBA[1:0]
BLBB[1:0]
2
1
BLBAT[1:0]
0
LB[1:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
1
1
1
1
1
1
1
1
This register is a mapping of the NVM lock bits into the I/O memory space, which enables direct read access from the
application software. Refer to “LOCKBITS – Lock Bit register” on page 33 for a description.
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4.16
Register Descriptions – Fuses and Lock bits
4.16.1 FUSEBYTE0 – Fuse Byte 0
Bit
7
6
5
4
+0x00
3
2
1
0
JTAGUID[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
Bit 7 – JTAGUID[7:0]: JTAG USER ID
These fuses can be used to set the default JTAG user ID for the device. During reset, the JTAGUID fuse bits will
be loaded into the MCU JTAG user ID register.
4.16.2 FUSEBYTE1 – Fuse Byte1
Bit
7
6
+0x01
5
4
3
2
WDWPER[3:0]
1
0
WDPER[3:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – WDWPER[3:0]: Watchdog Window Timeout Period
These fuse bits are used to set initial value of the closed window for the Watchdog Timer in Window Mode. During
reset these fuse bits are automatically written to the WPER bits Watchdog Window Mode Control Register. Refer
to “WINCTRL – Window Mode Control register” on page 128 for details.
Bit 3:0 – WDPER[3:0]: Watchdog Timeout Period
These fuse bits are used to set the initial value of the watchdog timeout period. During reset, these fuse bits are
automatically written to the PER bits in the watchdog control register. Refer to “CTRL – Control register” on page
127 for details.
4.16.3 FUSEBYTE2 – Fuse Byte2
Bit
7
6
5
4
3
2
1
0
+0x02
–
BOOTRST
TOSCSEL
–
–
–
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
BODPD[1:0]
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to one
when this register is written.
Bit 6 – BOOTRST: Boot Loader Section Reset Vector
This fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash section.
The device will then start executing from the boot loader flash section after reset.
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Table 4-1.
Boot reset fuse.
BOOTRST
Reset address
0
Reset vector = Boot loader reset
1
Reset vector = Application reset (address 0x0000)
Bit 5 – TOSCSEL: 32.768kHz Timer Oscillator Pin Selection
This fuse is used to select the pin location for the 32.768kHz timer oscillator (TOSC). This fuse is available only on
devices where XTAL and TOSC pins by default are shared.
Table 4-2.
TOSCSEL fuse.
TOSCSEL
Note:
Group configuration
Description
0
ALTERNATE(1)
TOSC1/2 on separate pins
1
XTAL
TOSC1/2 shared with XTAL
1.
See the device datasheet for alternate TOSC position.
Bit 4:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
one when this register is written.
Bit 1:0 – BODPD[1:0]: BOD Operation in Power-down Mode
These fuse bits set the BOD operation mode in all sleep modes except idle mode.
For details on the BOD and BOD operation modes, refer to “Brownout Detection” on page 112.
Table 4-3.
BOD operation modes in sleep modes.
BODPD[1:0]
Description
00
Reserved
01
BOD enabled in sampled mode
10
BOD enabled continuously
11
BOD disabled
4.16.4 FUSEBYTE4 – Fuse Byte4
Bit
7
6
5
4
+0x04
–
–
–
RSTDISBL
3
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
2
1
0
WDLOCK
JTAGEN
R/W
R/W
R/W
1
1
0
STARTUPTIME[1:0]
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
one when this register is written.
Bit: 4 – RSTDISBL: External Reset Disable
This fuse can be programmed to disable the external reset pin functionality. When this is done, pulling the reset pin
low will not cause an external reset. A reset is required before this bit will be read correctly after it is changed.
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Bit 3:2 – STARTUPTIME[1:0]: Start-up time
These fuse bits can be used to set at a programmable timeout period from when all reset sources are released
until the internal reset is released from the delay counter. A reset is required before these bits will be read correctly
after they are changed.
The delay is timed from the 1kHz output of the ULP oscillator. Refer to “Reset Sequence” on page 111 for details.
Table 4-4.
Start-up time.
STARTUPTIME[1:0]
00
64
01
4
10
Reserved
11
0
Bit 1 – WDLOCK: Watchdog Timer Lock
The WDLOCK fuse can be programmed to lock the watchdog timer configuration. When this fuse is programmed,
the watchdog timer configuration cannot be changed, and the ENABLE bit in the watchdog CTRL register is automatically set at reset and cannot be cleared from the application software. The WEN bit in the watchdog WINCTRL
register is not set automatically, and needs to be set from software. A reset is required before this bit will be read
correctly after it is changed.
Table 4-5.
Watchdog timer lock.
WDLOCK
1kHz ULP oscillator cycles
Description
0
Watchdog timer locked for modifications
1
Watchdog timer not locked
Bit 0 – JTAGEN: JTAG Enabled
This fuse controls whether or not the JTAG interface is enabled.
When the JTAG interface is disabled, all access through JTAG is prohibited, and the device can be accessed
using only the program and debug interface (PDI). The JTAGEN fuse is available only on devices with JTAG interface. A reset is required before this bit will be read correctly after it is changed.
Table 4-6.
JTAG Enable.
JTAGEN
Description
0
JTAG enabled
1
JTAG disabled
4.16.5 FUSEBYTE5 – Fuse Byte 5
Bit
7
6
5
4
3
2
1
0
+0x05
–
–
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
–
–
–
–
–
–
BODACT[1:0]
EESAVE
BODLEVEL[2:0]
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Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
one when this register is written.
Bit 5:4 – BODACT[1:0]: BOD Operation in Active Mode
These fuse bits set the BOD operation mode when the device is in active and idle modes. For details on the BOD
and BOD operation modes, refer to “Brownout Detection” on page 112.
Table 4-7.
BOD operation modes in active and idle modes.
BODACT[1:0]
Description
00
Reserved
01
BOD enabled in sampled mode
10
BOD enabled continuously
11
BOD disabled
Bit 3 – EESAVE: EEPROM is Preserved through the Chip Erase
A chip erase command will normally erase the flash, EEPROM, and internal SRAM. If this fuse is programmed, the
EEPROM is not erased during chip erase. This is useful if EEPROM is used to store data independently of the
software revision.
Table 4-8.
EEPROM preserved through chip erase.
EESAVE
Description
0
EEPROM is preserved during chip erase
1
EEPROM is erased during chip erase
Changes to the EESAVE fuse bit take effect immediately after the write timeout elapses. Hence, it is possible to
update EESAVE and perform a chip erase according to the new setting of EESAVE without leaving and reentering
programming mode.
Bit 2:0 – BODLEVEL[2:0]: Brownout Detection Voltage Level
These fuse bits sets the BOD voltage level. Refer to “Reset System” on page 110 for details. For BOD level nominal values, see Table 9-2 on page 113.
4.16.6 LOCKBITS – Lock Bit register
Bit
7
+0x07
6
5
4
3
BLBA[1:0]
BLBB[1:0]
2
1
BLBAT[1:0]
0
LB[1:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section
These lock bits control the software security level for accessing the boot loader section. The BLBB bits can only be
written to a more strict locking. Resetting the BLBB bits is possible only by executing a chip erase command.
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Table 4-9.
Boot lock bit for the boot loader section.
BLBB[1:0]
Group configuration
11
NOLOCK
No lock – no restrictions for SPM and (E)LPM accessing the boot loader
section.
10
WLOCK
Write lock – SPM is not allowed to write the boot loader section.
01
00
RLOCK
RWLOCK
Description
Read lock – (E)LPM executing from the application section is not allowed to
read from the boot loader section.
If the interrupt vectors are placed in the application section, interrupts are
disabled while executing from the boot loader section.
Read and write lock – SPM is not allowed to write to the boot loader section,
and (E)LPM executing from the application section is not allowed to read
from the boot loader section.
If the interrupt vectors are placed in the application section, interrupts are
disabled while executing from the boot loader section.
Bit 5:4 – BLBA[1:0]: Boot Lock Bit Application Section
These lock bits control the software security level for accessing the application section. The BLBA bits can only be
written to a more strict locking. Resetting the BLBA bits is possible only by executing a chip erase command.
Table 4-10. Boot lock bit for the application section.
BLBA[1:0]
Group configuration
11
NOLOCK
No Lock - no restrictions for SPM and (E)LPM accessing the application
section.
10
WLOCK
Write lock – SPM is not allowed to write the application section.
01
00
RLOCK
RWLOCK
Description
Read lock – (E)LPM executing from the boot loader section is not allowed to
read from the application section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
Read and write lock – SPM is not allowed to write to the application section,
and (E)LPM executing from the boot loader section is not allowed to read
from the application section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
Bit 3:2 – BLBAT[1:0]: Boot Lock Bit Application Table Section
These lock bits control the software security level for accessing the application table section for software access.
The BLBAT bits can only be written to a more strict locking. Resetting the BLBAT bits is possible only by executing
a chip erase command
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Table 4-11. Boot lock bit for the application table section.
BLBAT[1:0]
Group configuration
11
NOLOCK
No lock – no restrictions for SPM and (E)LPM accessing the application
table section.
10
WLOCK
Write lock – SPM is not allowed to write the application table
01
RLOCK
00
RWLOCK
Description
Read lock – (E)LPM executing from the boot loader section is not allowed to
read from the application table section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
Read and write lock – SPM is not allowed to write to the application table
section, and (E)LPM executing from the boot loader section is not allowed to
read from the application table section.
If the interrupt vectors are placed in the boot loader section, interrupts are
disabled while executing from the application section.
Bit 1:0 – LB[1:0]: Lock Bits(1)
These lock bits control the security level for the flash and EEPROM during external programming. These bits are
writable only through an external programming interface. Resetting the lock bits is possible only by executing a
chip erase command. All other access; using the TIF and OCD, is blocked if any of the Lock Bits are written to 0.
These bits do not block any software access to the memory
Table 4-12. Lock bit protection mode.
Note:
LB[1:0]
Group configuration
11
NOLOCK3
10
WLOCK
00
RWLOCK
1.
Description
No lock – no memory locks enabled.
Write lock – programming of the flash and EEPROM is disabled for the
programming interface. Fuse bits are locked for write from the programming
interface.
Read and write lock – programming and read/verification of the flash and
EEPROM are disabled for the programming interface. The lock bits and
fuses are locked for read and write from the programming interface.
Program the Fuse Bits and Boot Lock Bits before programming the Lock Bits.
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4.17
Register Description – Production Signature Row
4.17.1 RCOSC2M – Internal 2MHz Oscillator Calibration register
Bit
7
6
5
4
+0x00
3
2
1
0
RCOSC2M[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – RCOSC2M[7:0]: Internal 2MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 2MHz oscillator. Calibration of the oscillator is performed during production testing of the device. During reset, this value is automatically loaded into calibration
register B for the 2MHz DFLL. R.Refer to “CALB – DFLL Calibration register B” on page 99 for more details.
4.17.2 RCOSC2MA – Internal 2MHz Oscillator Calibration register
Bit
7
6
5
4
+0x01
3
2
1
0
RCOSC2MA[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – RCOSC2MA[7:0]: Internal 2MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 2MHz oscillator. Calibration of the oscillator is performed during production testing of the device. During reset, this value is automatically loaded into calibration
register A for the 2MHz DFLL. Refer to “CALA – DFLL Calibration Register A” on page 98 for more details.
4.17.3 RCOSC32K – Internal 32.768kHz Oscillator Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x02
3
2
1
0
R
R
R
R
x
x
x
x
RCOSC32K[7:0]
Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibration of the oscillator
is performed during production testing of the device. During reset, this value is automatically loaded into the calibration register for the 32.768kHz oscillator. Refer to “RC32KCAL – 32kHz Oscillator Calibration register” on page
97 for more details.
4.17.4 RCOSC32M – Internal 32MHz Oscillator Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x03
3
2
1
0
R
R
R
R
x
x
x
x
RCOSC32M[7:0]
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Bit 7:0 – RCOSC32M[7:0]: Internal 32MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is
performed during production testing of the device. During reset, this value is automatically loaded into calibration
register B for the 32MHz DFLL. R.Refer to “CALB – DFLL Calibration register B” on page 99 for more details.
4.17.5 RCOSC32MA – Internal 32MHz RC Oscillator Calibration register
Bit
7
6
5
4
+0x04
3
2
1
0
RCOSC32MA[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – RCOSC32MA[7:0]: Internal 32MHz Oscillator Calibration Value
This byte contains the oscillator calibration value for the internal 32MHz oscillator. Calibration of the oscillator is
performed during production testing of the device. During reset, this value is automatically loaded into calibration
register A for the 32MHz DFLL. R.Refer to “CALA – DFLL Calibration Register A” on page 98 for more details.
4.17.6 LOTNUM0 – Lot Number register 0
LOTNUM0, LOTNUM1, LOTNUM2, LOTNUM3, LOTNUM4, and LOTNUM5 contain the lot number for each device.
Together with the wafer number and wafer coordinates, this gives a serial number for the device.
Bit
7
6
5
4
+0x08
3
2
1
0
LOTNUM0[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
3
2
1
0
Bit 7:0 – LOTNUM0[7:0]: Lot Number Byte 0
This byte contains byte 0 of the lot number for the device.
4.17.7 LOTNUM1 – Lot Number register 1
Bit
7
6
5
4
+0x09
LOTNUM1[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
3
2
1
0
Bit 7:0 – LOTNUM1[7:0]: Lot Number Byte 1
This byte contains byte 1 of the lot number for the device.
4.17.8 LOTNUM2 – Lot Number register 2
Bit
7
6
5
4
+0x0A
LOTNUM2[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – LOTNUM2[7:0]: Lot Number Byte 2
This byte contains byte 2 of the lot number for the device.
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4.17.9 LOTNUM3- Lot Number register 3
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x0B
3
2
1
0
R
R
R
R
x
x
x
x
3
2
1
0
LOTNUM3[7:0]
Bit 7:0 – LOTNUM3[7:0]: Lot Number Byte 3
This byte contains byte 3 of the lot number for the device.
4.17.10 LOTNUM4 – Lot Number register 4
Bit
7
6
5
4
+0x0C
LOTNUM4[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
3
2
1
0
Bit 7:0 – LOTNUM4[7:0]: Lot Number Byte 4
This byte contains byte 4 of the lot number for the device.
4.17.11 LOTNUM5 – Lot Number register 5
Bit
7
6
5
4
+0x0D
LOTNUM5[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
3
2
1
0
Bit 7:0 – LOTNUM5[7:0]: Lot Number Byte 5
This byte contains byte 5 of the lot number for the device.
4.17.12 WAFNUM – Wafer Number register
Bit
7
6
5
4
+0x10
WAFNUM[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
x
x
x
x
x
Bit 7:0 – WAFNUM[7:0]: Wafer Number
This byte contains the wafer number for each device. Together with the lot number and wafer coordinates, this
gives a serial number for the device.
4.17.13 COORDX0 – Wafer Coordinate X register 0
COORDX0, COORDX1, COORDY0, and COORDY1 contain the wafer X and Y coordinates for each device. Together
with the lot number and wafer number, this gives a serial number for each device.
Bit
7
6
5
4
+0x12
3
2
1
0
COORDX0[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
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Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 0
This byte contains byte 0 of wafer coordinate X for the device.
4.17.14 COORDX1 – Wafer Coordinate X register 1
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x13
3
2
1
0
R
R
R
R
x
x
x
x
2
1
0
COORDX1[7:0]
Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1
This byte contains byte 1 of wafer coordinate X for the device.
4.17.15 COORDY0 – Wafer Coordinate Y register 0
Bit
7
6
5
4
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
2
1
0
+0x14
3
COORDY0[7:0]
Bit 7:0 – COORDY0[7:0]: Wafer Coordinate Y Byte 0
This byte contains byte 0 of wafer coordinate Y for the device.
4.17.16 COORDY1 – Wafer Coordinate Y register 1
Bit
7
6
5
4
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
+0x15
3
COORDY1[7:0]
Bit 7:0 – COORDY1[7:0]: Wafer Coordinate Y Byte 1
This byte contains byte 1 of wafer coordinate Y for the device
4.17.17 USBCAL0 – USB Calibration register 0
USBCAL0 and USBCAL1 contain the calibration value for the USB pins. Calibration is done during production to enable
operation without requiring external components on the USB lines for the device. The calibration bytes are not loaded
automatically into the USB calibration registers, and so this must be done from software.
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x1A
3
2
1
0
R
R
R
R
x
x
x
x
USBCAL0[7:0]
Bit 7:0 – USBCAL0[7:0]: USB Pad Calibration Byte 0
This byte contains byte 0 of the USB pin calibration data, and must be loaded into the USB CALL register.
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4.17.18 USBCAL1 – USB Pad Calibration register 1
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x1B
3
2
1
0
R
R
R
R
x
x
x
x
USBCAL1[7:0]
Bit 7:0 – USBCAL1[7:0]: USB Pad Calibration Byte 1
This byte contains byte 1 of the USB pin calibration data, and must be loaded into the USB CALH register.
4.17.19 RCOSC48M – USB RCOSC Calibration
Bit
7
6
5
4
+0x1C
3
2
1
0
RCOSC48M[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – RCOSC48M[7:0]: 48MHz RSCOSC Calibration
This byte contains a 48MHz calibration value for the internal 32MHz oscillator. When this calibration value is written to calibration register B for the 32MHz DFLL, the oscillator is calibrated to 48MHz to enable full-speed USB
operation from internal oscillator.
Note:
The COMP2 and COMP1 registers inside the DFLL32M must be set to B71B.
4.17.20 ADCACAL0 – ADCA Calibration register 0
ADCACAL0 and ADCACAL1 contain the calibration value for the analog- to -digital converter A (ADCA). Calibration is
done during production testing of the device. The calibration bytes are not loaded automatically into the ADC calibration
registers, and so this must be done from software.
Bit
7
6
5
4
+0x20
3
2
1
0
ADCACAL0[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – ADCACAL0[7:0]: ADCA Calibration Byte 0
This byte contains byte 0 of the ADCA calibration data, and must be loaded into the ADCA CALL register.
4.17.21 ADCACAL1 – ADCA Calibration register 1
Bit
7
6
5
4
+0x21
3
2
1
0
ADCACAL1[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1
This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH register.
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4.17.22 ADCBCAL0 – ADCB Calibration register 0
ADCBCAL0 and ADCBCAL1 contains the calibration value for the analog -to -digital converter B (ADCB). Calibration is
done during production testing of the device. The calibration bytes are not loaded automatically into the ADC calibration
registers, so this must be done from software.
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x24
3
2
1
0
R
R
R
R
x
x
x
x
ADCBCAL0[7:0]
Bit 7:0 – ADCBCAL0[7:0]: ADCB Calibration Byte 0
This byte contains byte 0 of the ADCB calibration data, and must be loaded into the ADCB CALL register.
4.17.23 ADCBCAL1 – ADCB Calibration register 1
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
x
x
x
x
+0x25
3
2
1
0
R
R
R
R
x
x
x
x
ADCBCAL1[7:0]
Bit 7:0 – ADCBCAL0[7:0]: ADCB Calibration Byte 1
This byte contains byte 1 of the ADCB calibration data, and must be loaded into the ADCB CALH register.
4.17.24 TEMPSENSE0 – Temperature Sensor Calibration register 0
TEMPSENSE0 and TEMPSENSE1 contain the 12-bit ADCA value from a temperature measurement done with the
internal temperature sensor. The measurement is done in production testing at 85C, and can be used for single- or
multi-point temperature sensor calibration.
Bit
7
6
5
4
+0x2E
3
2
1
0
TEMPSENSE0[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
x
x
x
x
x
x
x
x
2
1
0
Bit 7:0 – TEMPSENSE0[7:0]: Temperature Sensor Calibration Byte 0
This byte contains the byte 0 of the temperature measurement.
4.17.25 TEMPSENSE1 – Temperature Sensor Calibration register 1
Bit
7
6
5
4
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
x
x
x
x
+0x2F
3
TEMPSENSE1[7:0]
Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1
This byte contains byte 1 of the temperature measurement.
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4.17.26 DACA0OFFCAL – DACA Offset Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
0
0
0
0
3
+0x30
2
1
0
R
R
R
R
x
x
x
x
DACA0OFFCAL[7:0]
Bit 7:0 – DACA0OFFCAL[7:0]: DACA0 Offset Calibration Byte
This byte contains the offset calibration value for channel 0 in the digital -to -analog converter A (DACA). Calibration is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 0 offset calibration register, so this must be done from software.
4.17.27 DACA0GAINCAL – DACA Gain Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
0
0
0
0
+0x31
3
2
1
0
R
R
R
R
x
x
x
x
DACA0GAINCAL[7:0]
Bit 7:0 – DACA0GAINCAL[7:0]: DACA0 Gain Calibration Byte
This byte contains the gain calibration value for channel 0 in the digital -to -analog converter A (DACA). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC gain
calibration register, so this must be done from software.
4.17.28 DACB0OFFCAL – DACB Offset Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
0
0
0
0
3
+0x32
2
1
0
R
R
R
R
x
x
x
x
DACB0OFFCAL[7:0]
Bit 7:0 – DACB0OFFCAL[7:0]: DACB0 Offset Calibration Byte
This byte contains the offset calibration value for channel 0 in the digital- to -analog converter B (DACB). Calibration is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 0 offset calibration register, so this must be done from software.
4.17.29 DACB0GAINCAL – DACB Gain Calibration register
Bit
7
6
5
4
+0x33
3
2
1
0
DACB0GAINCAL[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
x
x
x
x
Bit 7:0 – DACB0GAINCAL[7:0]: DACB0 Gain Calibration Byte
This byte contains the gain calibration value for channel 0 in the digital- to- analog converter B (DACB). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC channel 0 gain calibration register, so this must be done from software.
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4.17.30 DACA1OFFCAL – DACA Offset Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
0
0
0
0
3
+0x34
2
1
0
R
R
R
R
x
x
x
x
DACA1OFFCAL[7:0]
Bit 7:0 – DACA1OFFCAL[7:0]: DACA1 Offset Calibration Byte
This byte contains the offset calibration value for channel 1 in the digital- to -analog converter A (DACA). Calibration is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 1 offset calibration register, so this must be done from software.
4.17.31 DACA1GAINCAL – DACA Gain Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
0
0
0
0
3
+0x35
2
1
0
R
R
R
R
x
x
x
x
DACA1GAINCAL[7:0]
Bit 7:0 – DACA1GAINCAL[7:0]: DACA1 Gain Calibration Byte
This byte contains the gain calibration value for channel 1 in the digital -to- analog converter A (DACA). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC channel 1 gain calibration register, so this must be done from software.
4.17.32 DACB1OFFCAL – DACB Offset Calibration register
Bit
7
6
5
4
Read/Write
R
R
R
R
Initial Value
0
0
0
0
3
+0x36
2
1
0
R
R
R
R
x
x
x
x
DACB1OFFCAL[7:0]
Bit 7:0 – DACB1OFFCAL[7:0]: DACB1 Offset Calibration Byte
This byte contains the offset calibration value for channel 1 in the digital- to -analog converter B (DACB). Calibration is done during production testing of the device. The calibration byte is not loaded automatically into the DAC
channel 1 offset calibration register, so this must be done from software.
4.17.33 DACB1GAINCAL – DACB Gain Calibration register
Bit
7
6
5
4
+0x37
3
2
1
0
DACB1GAINCAL[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
x
x
x
x
Bit 7:0 – DACB1GAINCAL[7:0]: DACB1 Gain Calibration Byte
This byte contains the gain calibration value for channel 1 in the digital- to -analog converter B (DACB). Calibration
is done during production testing of the device. The calibration byte is not loaded automatically into the DAC channel 1 gain calibration register, so this must be done from software.
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4.18
Register Description – General Purpose I/O Memory
4.18.1 GPIORn – General Purpose I/O register n
Bit
7
6
5
4
+n
3
2
1
0
GPIORn[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
These are general purpose registers that can be used to store data, such as global variables and flags, in the bitaccessible I/O memory space.
4.19
Register Description – External Memory
Refer to “EBI – External Bus Interface” on page 319.
4.20
Register Descriptions – MCU Control
4.20.1 DEVID0 – Device ID register 0
DEVID0, DEVID1, and DEVID2 contain the byte identification that identifies each microcontroller device type. For details
on the actual ID,, refer to the device datasheet.
Bit
7
6
5
4
+0x00
3
2
1
0
DEVID0[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
1
1
1
1
0
Bit 7:0 – DEVID0[7:0]: Device ID Byte 0
Byte 0 of the device ID. This byte will always be read as 0x1E. This indicates that the device is manufactured by
Atmel.
4.20.2 DEVID1 – Device ID register 1
Bit
7
6
5
4
+0x01
3
2
1
0
DEVID1[7:0]
Read/Write
R
R
R
R
R
R
R
R
Initial Value
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
3
2
1
0
Bit 7:0 – DEVID[7:0]: Device ID Byte 1
Byte 1 of the device ID indicates the flash size of the device.
4.20.3 DEVID2 – Device ID register 2
Bit
7
6
5
4
Read/Write
R
R
R
R
R
R
R
R
Initial Value
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
+0x02
DEVID2[7:0]
Bit 7:0 – DEVID2[7:0]: Device ID Byte 2
Byte 2 of the device ID indicates the device number.
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4.20.4 REVID – Revision ID
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
–
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
1/0
1/0
1/0
1/0
3
2
1
0
Bit 7:4 – Reserved
These bits are unused and reserved for future use.
Bit 3:0 – REVID[3:0]: Revision ID
These bits contains the device revision. 0 = A, 1 = B, and so on.
REVID[3:0]
4.20.5 JTAGUID – JTAG User ID register
Bit
7
6
5
4
Read/Write
R
R
R
R
R
R
R
R
Initial Value
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
+0x04
JTAGUID[7:0]
Bit 7:0 – JTAGUID[7:0]: JTAG User ID
The JTAGUID can be used to identify two devices with identical device IDs in a JTAG scan chain. The JTAGUID
will automatically be loaded from flash during reset and placed in these registers.
4.20.6 MCUCR – Control register
Bit
7
6
5
4
3
2
1
0
+0x06
–
–
–
–
–
–
–
JTAGD
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – JTAGD: JTAG Disable
Setting this bit will disable the JTAG interface. This bit is protected by the configuration change protection mechanism. F.For details, refer to “Configuration Change Protection” on page 13.
4.20.7 ANAINIT – Analog Initialization register
Bit
7
6
5
4
+0x07
–
–
–
–
STARTUPDLYB[1:0]
STARTUPDLYA[1:0]
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
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Bit 3:2 / 1:0 – STARTUPDLYx
Setting these bits enables sequential start of the internal components used for the ADC, DAC, and analog comparator with the main input/output connected to that port. When this is done, the internal components, such as voltage
reference and bias currents, are started sequentially when the module is enabled. This reduces the peak current
consumption during startup of the module. For maximum effect, the start-up delay should be set so that it is larger
than 0.5µs.
Table 4-13. Analog startup delay.
STARTUPDLYx
Group configuration
Description
00
NONE
Direct startup
11
2CLK
2 * ClkPER
10
8CLK
8 * ClkPER
11
32CLK
32 * ClkPER
4.20.8 EVSYSLOCK – Event System Lock register
Bit
7
6
5
4
3
2
1
0
+0x08
–
–
–
EVSYS1LOCK
–
–
–
EVSYS0LOCK
Read/Write
R
R
R
R/W
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – EVSYS1LOCK
Setting this bit will lock all registers in the event system related to event channels 4 to 7against for further modification. The following registers in the event system are locked: CH4MUX, CH4CTRL, CH5MUX, CH5CTRL,
CH6MUX, CH6CTRL, CH7MUX, and CH7CTRL. This bit is protected by the configuration change protection
mechanism. For details, refer to “Configuration Change Protection” on page 13.
Bit 3:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – EVSYS0LOCK
Setting this bit will lock all registers in the event system related to event channels 0 to 3 for against further modification. The following registers in the event system are locked: CH0MUX, CH0CTRL, CH1MUX, CH1CTRL,
CH2MUX, CH2CTRL, CH3MUX, and CH3CTRL. This bit is protected by the configuration change protection
mechanism. F.For details, refer to “Configuration Change Protection” on page 13.
4.20.9 AWEXLOCK – Advanced Waveform Extension Lock register
Bit
7
6
5
4
3
2
1
0
+0x09
–
–
–
–
–
AWEXELOCK
–
AWEXCLOCK
Read/Write
R
R
R
R
R
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
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Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – AWEXELOCK: Advanced Waveform Extension Lock for TCE0
Setting this bit will lock all registers in the AWEXE module for timer/counter E0 for against further modification.
This bit is protected by the configuration change protection mechanism.For details, refer to “Configuration Change
Protection” on page 13.
Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 0 – AWEXCLOCK: Advanced Waveform Extension Lock for TCC0
Setting this bit will lock all registers in the AWEXC module for timer/counter C0 for against further modification.
This bit is protected by the configuration change protection mechanism. For details, refer to “Configuration Change
Protection” on page 13.
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4.21
Register summary – NVM controller
Address
Name
+0x00
ADDR0
Address Byte 0
26
+0x01
ADDR1
Address Byte 1
26
+0x02
ADDR2
Address Byte 2
26
+0x03
Reserved
+0x04
DATA0
Data Byte 0
26
+0x05
DATA1
Data Byte 1
27
+0x06
DATA2
Data Byte 2
27
+0x07
Reserved
–
–
–
–
–
–
–
–
+0x08
Reserved
–
–
–
–
–
–
–
–
+0x09
Reserved
–
–
–
–
–
–
–
–
+0x0A
CMD
–
+0x0B
CTRLA
–
–
–
–
–
–
–
CMDEX
27
+0x0C
CTRLB
–
–
–
–
EEMAPEN
FPRM
EPRM
SPMLOCK
28
+0x0D
INTCTRL
–
–
–
–
+0x0E
Reserved
–
–
–
–
–
–
–
–
+0x0F
STATUS
NVMBUSY
FBUSY
–
–
–
–
EELOAD
FLOAD
+0x10
LOCKBITS
4.22
Bit 7
Bit 6
–
–
Bit 5
Bit 4
–
Bit 3
–
Bit 2
–
–
Bit 1
Bit 0
–
–
CMD[6:0]
BLBB[1:0]
27
SPMLVL[1:0]
BLBA[1:0]
Page
EELVL[1:0]
BLBAT[1:0]
28
LB[1:0]
29
29
Register summary – Fuses and Lock Bits
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
+0x00
FUSEBYTE0
+0x01
FUSEBYTE1
+0x02
FUSEBYTE2
–
BOOTRST
TOSCSEL
–
–
–
+0x03
Reserved
–
–
–
–
–
–
+0x04
FUSEBYTE4
–
–
–
RSTDISBL
+0x05
FUSEBYTE5
–
–
+0x06
Reserved
–
–
+0x07
LOCKBITS
Bit 1
Bit 0
JTAGUID
30
WDWPER3:0]
BLBB[1:0]
WDPER[3:0]
BODACT[1:0]
–
–
BLBA[1:0]
Page
STARTUPTIME[1:0]
EESAVE
–
BODPD[1:0]
30
–
–
WDLOCK
JTAGEN
BODLEVEL[2:0]
–
BLBAT[1:0]
30
–
31
32
–
LB[1:0]
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48
4.23
Register summary – Production Signature Row
Address
Auto load
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
+0x00
YES
RCOSC2M
RCOSC2M[7:0]
36
+0x01
YES
RCOSC2MA
RCOSC2MA[7:0]
36
+0x02
YES
RCOSC32K
RCOSC32K[7:0]
36
+0x03
YES
RCOSC32M
RCOSC32M[7:0]
36
+0x04
YES
RCOSC32MA
RCOSC32MA[7:0]
36
+0x05
Reserved
–
–
–
–
–
–
–
–
+0x06
Reserved
–
–
–
–
–
–
–
–
+0x07
Reserved
–
–
–
–
–
–
–
–
Page
+0x08
NO
LOTNUM0
LOTNUM0[7:0]
37
+0x09
NO
LOTNUM1
LOTNUM1[7:0]
37
+0x0A
NO
LOTNUM2
LOTNUM2[7:0]
37
+0x0B
NO
LOTNUM3
LOTNUM3[7:0]
38
+0x0C
NO
LOTNUM4
LOTNUM4[7:0]
38
+0x0D
NO
LOTNUM5
LOTNUM5[7:0]
38
+0x0E
Reserved
–
–
–
–
–
–
–
–
+0x0F
Reserved
–
–
–
–
–
–
–
–
+0x10
NO
+0x11
WAFNUM
Reserved
WAFNUM[7:0]
–
–
–
–
–
38
–
–
–
+0x12
NO
COORDX0
COORDX0[7:0]
38
+0x13
NO
COORDX1
COORDX1[7:0]
39
+0x14
NO
COORDY0
COORDY0[7:0]
39
+0x15
NO
COORDY1
COORDY1[7:0]
39
+0x16
Reserved
–
–
–
–
–
–
–
–
+0x17
Reserved
–
–
–
–
–
–
–
–
+0x18
Reserved
–
–
–
–
–
–
–
–
+0x19
Reserved
–
–
–
–
–
–
–
–
+0x1A
USBCAL0
USBCAL0[7:0]
39
+0x1B
USBCAL1
USBCAL1[7:0]
40
+0x1C
RCOSC48M
RCOSC48M[7:0]
40
+0x1D
Reserved
–
–
–
–
–
–
–
–
+0x1E
Reserved
–
–
–
–
–
–
–
–
+0x1F
Reserved
–
–
–
–
–
–
–
–
+0x20
NO
ADCACAL0
ADCACAL0[7:0]
40
+0x21
NO
ADCACAL1
ADCACAL1[7:0]
40
+0x22
Reserved
–
–
–
–
–
–
–
–
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Address
Auto load
+0x23
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
–
–
–
–
–
–
–
–
Page
+0x24
NO
ADCBCAL0
ADCBCAL0[7:0]
41
+0x25
NO
ADCBCAL1
ADCBCAL0[7:0]
41
+0x26
Reserved
–
–
–
–
–
–
–
–
+0x27
Reserved
–
–
–
–
–
–
–
–
+0x28
Reserved
–
–
–
–
–
–
–
–
+0x29
Reserved
–
–
–
–
–
–
–
–
+0x2A
Reserved
–
–
–
–
–
–
–
–
+0x2B
Reserved
–
–
–
–
–
–
–
–
+0x2C
Reserved
–
–
–
–
–
–
–
–
+0x2D
Reserved
–
–
–
–
–
–
–
–
+0x2E
NO
TEMPSENSE0
TEMPSENSE0[7:0]
+0x2F
NO
TEMPSENSE1
+0x30
NO
DACA0OFFCAL
DACA0OFFCAL[7:0]
42
+0x31
NO
DACA0GAINCAL
DACA0GAINCAL[7:0]
42
+0x32
NO
DACB0OFFCAL
DACB0OFFCAL[7:0]
42
+0x33
NO
DACB0GAINCAL
DACB0GAINCAL[7:0]
42
+0x34
NO
DACA1OFFCAL
DACA1OFFCAL[7:0]
43
+0x35
NO
DACA1GAINCAL
DACA1GAINCAL[7:0]
43
+0x36
NO
DACB1OFFCAL
DACB1OFFCAL[7:0]
43
+0x37
NO
DACB1GAINCAL
DACB1GAINCAL[7:0]
43
–
–
–
41
TEMPSENSE1[11:8]
–
41
+0x38
Reserved
–
–
–
–
–
–
–
–
+0x39
Reserved
–
–
–
–
–
–
–
–
0x3A
Reserved
–
–
–
–
–
–
–
–
+0x3B
Reserved
–
–
–
–
–
–
–
–
+0x3C
Reserved
–
–
–
–
–
–
–
–
+0x3D
Reserved
–
–
–
–
–
–
–
–
+0x3E
Reserved
–
–
–
–
–
–
–
–
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4.24
Register summary – General Purpose I/O registers
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
+0x00
GPIOR0
GPIOR[7:0]
44
+0x01
GPIOR1
GPIOR[7:0]
44
+0x02
GPIOR2
GPIOR[7:0]
44
+0x03
GPIOR3
GPIOR[7:0]
44
+0x04
GPIOR4
GPIOR[7:0]
44
+0x05
GPIOR5
GPIOR[7:0]
44
+0x06
GPIOR6
GPIOR[7:0]
44
+0x07
GPIOR7
GPIOR[7:0]
44
+0x08
GPIOR8
GPIOR[7:0]
44
+0x09
GPIOR9
GPIOR[7:0]
44
+0x0A
GPIOR10
GPIOR[7:0]
44
+0x0B
GPIOR11
GPIOR[7:0]
44
+0x0C
GPIOR12
GPIOR[7:0]
44
+0x0D
GPIOR13
GPIOR[7:0]
44
+0x0E
GPIOR14
GPIOR[7:0]
44
+0x0F
GPIOR15
GPIOR[7:0]
44
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4.25
Register summary – MCU control
Address
Name
+0x00
DEVID0
DEVID0[7:0]
44
+0x01
DEVID1
DEVID1[7:0]
44
+0x02
DEVID2
DEVID2[7:0]
44
+0x03
REVID
+0x04
JTAGUID
+0x05
Reserved
–
–
–
–
–
–
–
–
+0x06
MCUCR
–
–
–
–
–
–
–
JTAGD
45
+0x07
ANAINIT
–
–
–
–
STARTUPDLYB[1:0]
STARTUPDLYA[1:0]
45
+0x08
EVSYSLOCK
–
–
–
EVSYS1LOCK
–
–
–
EVSYS0LOCK
46
+0x09
AWEXLOCK
–
–
–
–
–
AWEXELOCK
–
AWEXCLOCK
46
+0x0A
Reserved
–
–
–
–
–
–
–
–
+0x0B
Reserved
–
–
–
–
–
–
–
–
4.26
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
Bit 3
Bit 2
Bit 1
bit 0
REVID[3:0]
–
Page
45
JTAGUID[7:0]
45
Interrupt vector summary – NVM Controller
Table 4-14. NVM interrupt vectors and their word offset address from the NVM controller interrupt base.
Offset
Source
Interrupt description
0x00
EE_vect
Nonvolatile memory EEPROM interrupt vector
0x02
SPM_vect
Nonvolatile memory SPM interrupt vector
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5.
DMAC - Direct Memory Access Controller
5.1
Features
Allows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
from peripheral to data memory
from peripheral to peripheral
Four DMA channels with separate
transfer triggers
interrupt vectors
addressing modes
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Multiple addressing modes
Static
Incremental
Decremental
Optional reload of source and destination addresses at the end of each
Burst
Block
Transaction
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
5.2
Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
off load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
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Figure 5-1. DMA Overview.
DMA Channel 0
DMA trigger /
Event
CTRLA
CTRLB
TRIGSRC
Enable
Burst
Arbitration
Control Logic
TRFCNT
REPCNT
R/W Master port
Arbiter
DESTADDR
SRCADDR
Read
BUF
Write
DMA Channel 1
DMA Channel 2
Bus
matrix
CTRL
DMA Channel 3
Slave port
Read /
Write
5.3
DMA Transaction
A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction. A
transaction is done in data blocks, and the size of the transaction (number of bytes to transfer) is selectable from
software and controlled by the block size and repeat counter settings. Each block transfer is divided into smaller bursts.
5.3.1
Block Transfer and Repeat
The size of the block transfer is set by the block transfer count register, and can be anything from 1 byte to 64KB.
A repeat counter can be enabled to set a number of repeated block transfers before a transaction is complete. The
repeat is from 1 to 255, and an unlimited repeat count can be achieved by setting the repeat count to zero.
5.3.2
Burst Transfer
Since the AVR CPU and DMA controller use the same data buses, a block transfer is divided into smaller burst transfers.
The burst transfer is selectable to 1, 2, 4, or 8 bytes. This means that if the DMA acquires the data bus and a transfer
request is pending, it will occupy the bus until all bytes in the burst are transferred.
A bus arbiter controls when the DMA controller and the AVR CPU can use the bus. The CPU always has priority, and so
as long as the CPU requests access to the bus, any pending burst transfer must wait. The CPU requests bus access
when it executes an instruction that writes or reads data to SRAM, I/O memory, EEPROM or the external bus interface.
For more details on memory access bus arbitration, refer to “Data Memory” on page 22.
Figure 5-2. DMA transaction.
Four-byte burst mode
Block size: 12 bytes
Repeat count: 2
Burst transfer
Block transfer
DMA transaction
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5.4
Transfer Triggers
DMA transfers can be started only when a DMA transfer request is detected. A transfer request can be triggered from
software, from an external trigger source (peripheral), or from an event. There are dedicated source trigger selections for
each DMA channel. The available trigger sources may vary from device to device, depending on the modules or
peripherals that exist in the device. Using a transfer trigger for a module or peripherals that does not exist will have no
effect. For a list of all transfer triggers, refer to “TRIGSRC – Trigger Source” on page 62.
By default, a trigger starts a block transfer operation. When the block transfer is complete, the channel is automatically
disabled. When enabled again, the channel will wait for the next block transfer trigger. It is possible to select the trigger to
start a burst transfer instead of a block transfer. This is called a single-shot transfer, and for each trigger only one burst is
transferred. When repeat mode is enabled, the next block transfer does not require a transfer trigger. It will start as soon
as the previous block is done.
If the trigger source generates a transfer request during an ongoing transfer, this will be kept pending, and the transfer
can start when the ongoing one is done. Only one pending transfer can be kept, and so if the trigger source generates
more transfer requests when one is already pending, these will be lost.
5.5
Addressing
The source and destination address for a DMA transfer can either be static or automatically incremented or
decremented, with individual selections for source and destination. When address increment or decrement is used, the
default behaviour is to update the address after each access. The original source and destination addresses are stored
by the DMA controller, and so the source and destination addresses can be individually configured to be reloaded at the
following points:
5.6
End of each burst transfer
End of each block transfer
End of transaction
Never reloaded
Priority Between Channels
If several channels request a data transfer at the same time, a priority scheme is available to determine which channel is
allowed to transfer data. Application software can decide whether one or more channels should have a fixed priority or if
a round robin scheme should be used. A round robin scheme means that the channel that last transferred data will have
the lowest priority.
5.7
Double Buffering
To allow for continuous transfer, two channels can be interlinked so that the second takes over the transfer when the first
is finished, and vice versa. This leaves time for the application to process the data transferred by the first channel,
prepare fresh data buffers, and set up the channel registers again while the second channel is working. This is referred to
as double buffering or chained transfers.
When double buffering is enabled for a channel pair, it is important that the two channels are configured with the same
repeat count. The block sizes need not be equal, but for most applications they should be, along with the rest of the
channel’s operation mode settings.
Note that the double buffering channel pairs are limited to channels 0 and 1 as the first pair and channels 2 and 3 as the
second pair. However, it is possible to have one pair operate in double buffered mode while the other is left unused or
operating independently.
5.8
Transfer Buffers
To avoid unnecessary bus loading when doing data transfer between memories with different access timing (for
example, I/O register and external memory), the DMA controller has a four-byte buffer. Two bytes will be read from the
source address and written to this buffer before a write to the destination is started.
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5.9
Error detection
The DMA controller can detect erroneous operation. Error conditions are detected individually for each DMA channel,
and the error conditions are:
5.10
Write to memory mapped EEPROM locations
Reading EEPROM when the EEPROM is off (sleep entered)
DMA controller or a busy channel is disabled in software during a transfer
Software Reset
Both the DMA controller and a DMA channel can be reset from the user software. When the DMA controller is reset, all
registers associated with the DMA controller, including channels, are cleared. A software reset can be done only when
the DMA controller is disabled.
When a DMA channel is reset, all registers associated with the DMA channel are cleared. A software reset can be done
only when the DMA channel is disabled.
5.11
Protection
In order to ensure safe operation, some of the channel registers are protected during a transaction. When the DMA
channel busy flag (CHnBUSY) is set for a channel, the user can modify only the following registers and bits:
5.12
CTRL register
INTFLAGS register
TEMP registers
CHEN, CHRST, TRFREQ, and REPEAT bits of the channel CTRL register
TRIGSRC register
Interrupts
The DMA controller can generate interrupts when an error is detected on a DMA channel or when a transaction is
complete for a DMA channel. Each DMA channel has a separate interrupt vector, and there are different interrupt flags
for error and transaction complete.
If repeat is not enabled, the transaction complete flag is set at the end of the block transfer. If unlimited repeat is enabled,
the transaction complete flag is also set at the end of each block transfer.
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5.13
Register Description – DMA Controller
5.13.1 CTRL – Control register
Bit
7
6
5
4
3
ENABLE
RESET
–
–
DBUFMODE[1:0]
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x00
2
1
0
PRIMODE[1:0]
Bit 7 – ENABLE: Enable
Setting this bit enables the DMA controller. If the DMA controller is enabled and this bit is written to zero, the
ENABLE bit is not cleared before the internal transfer buffer is empty, and the DMA data transfer is aborted.
Bit 6 – RESET: Software Reset
Writing a one to RESET will be ignored as long as DMA is enabled (ENABLE = 1). This bit can be set only when
the DMA controller is disabled (ENABLE = 0).
Bit 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – DBUFMODE[1:0]: Double Buffer Mode
These bits enable the double buffer on the different channels according to Table 5-1.
Table 5-1.
DMA double buffer settings.
DBUFMODE[1:0]
Group configuration
Description
00
DISABLED
01
CH01
Double buffer enabled on channel0/1
10
CH23
Double buffer enabled on channel2/3
11
CH01CH23
No double buffer enabled
Double buffer enabled on channel0/1 and channel2/3
Bit 1:0 – PRIMODE[1:0]: Channel Priority Mode
These bits determine the internal channel priority according to Table 5-2
Table 5-2.
DMA channel priority settings.
PRIMODE[1:0]
Group configuration
Description
00
RR0123
Round robin
01
CH0RR123
Channel0 > Round robin (channel 1, 2 and 3)
10
CH01RR23
Channel0 > Channel1 > Round robin (channel 2 and 3)
11
CH0123
Channel0 > Channel1 > Channel2 > Channel3
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5.13.2 INTFLAGS – Interrupt Status register
Bit
+0x03
7
6
5
4
3
2
1
0
CH3ERRIF
CH2ERRIF
CH1ERRIF
CH0ERRIF
CH3TRNFIF
CH2TRNFIF
CH1TRNFIF
CH0TRNFIF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – CHnERRIF[3:0]: Channel n Error Interrupt Flag
If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one to this bit location
will clear the flag.
Bit 3:0 – CHnTRNFIF[3:0]: Channel n Transaction Complete Interrupt Flag
When a transaction on channel n has been completed, the CHnTRFIF flag will be set. If unlimited repeat count is
enabled, this flag is read as one after each block transfer. Writing a one to this bit location will clear the flag.
5.13.3 STATUS – Status register
Bit
+0x04
7
6
5
4
3
2
1
0
CH3BUSY
CH2BUSY
CH1BUSY
CH0BUSY
CH3PEND
CH2PEND
CH1PEND
CH0PEND
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – CHnBUSY[3:0]: Channel Busy
When channel n starts a DMA transaction, the CHnBUSY flag will be read as one. This flag is automatically
cleared when the DMA channel is disabled, when the channel n transaction complete interrupt flag is set, or if the
DMA channel n error interrupt flag is set.
Bit 3:0 – CHnPEND[3:0]: Channel Pending
If a block transfer is pending on DMA channel n, the CHnPEND flag will be read as one. This flag is automatically
cleared when the block transfer starts or if the transfer is aborted.
5.13.4 TEMPL – Temporary register Low
Bit
7
6
5
4
+0x06
3
2
1
0
TEMP[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – TEMP[7:0]: Temporary register 0
This register is used when reading 16- and 24-bit registers in the DMA controller. Byte 1 of the 16/24-bit register is
stored here when it is written by the CPU. Byte 1 of the 16/24-bit register is stored when byte 0 is read by the CPU.
This register can also be read and written from the user software.
Reading and writing 16- and 24-bit registers requires special attention. For details, refer to “The combined EIND +
Z register.” on page 12.
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5.13.5 TEMPH – Temporary Register High
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x07
TEMP[15:8]
Bit 7:0 – TEMP[15:8]: Temporary Register
This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register is
stored when it is written by the CPU. Byte 2 of the 24-bit register is stored here when byte 1 is read by the CPU.
This register can also be read and written from the user software.
Reading and writing 24-bit registers requires special attention. For details, refer to “The combined EIND + Z register.” on page 12.
5.14
Register Description – DMA Channel
5.14.1 CTRLA – Control register A
Bit
+0x00
7
6
5
4
3
2
1
0
ENABLE
RESET
REPEAT
TRFREQ
–
SINGLE
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
BURSTLEN[1:0]
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – ENABLE: Channel Enable
Setting this bit enables the DMA channel. This bit is automatically cleared when the transaction is completed. If the
DMA channel is enabled and this bit is written to zero, the CHEN bit is not cleared until the internal transfer buffer
is empty and the DMA transfer is aborted.
Bit 6 – RESET: Software Reset
Setting this bit will reset the DMA channel. It can only be set when the DMA channel is disabled (CHEN = 0). Writing a one to this bit will be ignored as long as the channel is enabled (CHEN=1). This bit is automatically cleared
when reset is completed.
Bit 5 – REPEAT: Repeat Mode
Setting this bit enables the repeat mode. In repeat mode, this bit is cleared by hardware at the beginning of the last
block transfer. The REPCNT register should be configured before setting the REPEAT bit.
Bit 4 – TRFREQ: Transfer Request
Setting this bit requests a data transfer on the DMA channel. This bit is automatically cleared at the beginning of
the data transfer. Writing this bit does not have any effect unless the channel is enabled.
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2 – SINGLE: Single-Shot Data transfer
Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the
transfer trigger. A write to this bit will be ignored while the channel is enabled.
Bit 1:0 – BURSTLEN[1:0]: Burst Mode
These bits decide the DMA channel burst mode according to Table 5-3 on page 60. These bits cannot be changed
if the channel is busy.
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Table 5-3.
DMA channel burst mode.
BURSTLEN[1:0]
Group configuration
00
1BYTE
1 byte burst mode
01
2BYTE
2 bytes burst mode
10
4BYTE
4 bytes burst mode
11
8BYTE
8 bytes burst mode
Table 5-4.
Description
Summary of triggers, transaction complete flag and channel disable according to DMA channel
configuration.
REPEAT
SINGLE
REPCNT
Trigger
Flag set after
Channel disabled after
0
0
0
Block
1 block
1 block
0
0
1
Block
1 block
1 block
0
0
n>1
Block
1 block
1 block
0
1
0
BURSTLEN
1 block
1 block
0
1
1
BURSTLEN
1 block
1 block
0
1
n>1
BURSTLEN
1 block
1 block
1
0
0
Block
Each block
Each block
1
0
1
Transaction
1 block
1 block
1
0
n>1
Transaction
n blocks
n blocks
1
1
0
BURSTLEN
Each block
Never
1
1
1
BURSTLEN
1 block
1 block
1
1
n>1
BURSTLEN
n blocks
n blocks
5.14.2 CTRLB – Control register B
Bit
7
6
5
4
CHBUSY
CHPEND
ERRIF
TRNIF
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x01
3
2
ERRINTLVL[1:0]
1
0
TRNINTLVL[1:0]
Bit 7 – CHBUSY: Channel Busy
When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one. This flag is automatically
cleared when the DMA channel is disabled, when the channel transaction complete interrupt flag is set or when the
channel error interrupt flag is set.
Bit 6 – CHPEND: Channel Pending
If a block transfer is pending on the DMA channel, the CHPEND flag will be read as one. This flag is automatically
cleared when the transfer starts or if the transfer is aborted.
Bit 5 – ERRIF: Error Interrupt Flag
If an error condition is detected on the DMA channel, the ERRIF flag will be set and the optional interrupt is generated. Since the DMA channel error interrupt shares the interrupt address with the DMA channel n transaction
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complete interrupt, ERRIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing
a one to this location.
Bit 4 – TRNIF: Channel n Transaction Complete Interrupt Flag
When a transaction on the DMA channel has been completed, the TRNIF flag will be set and the optional interrupt
is generated. When repeat is not enabled, the transaction is complete and TRNIFR is set after the block transfer.
When unlimited repeat is enabled, TRNIF is also set after each block transfer.
Since the DMA channel transaction n complete interrupt shares the interrupt address with the DMA channel error
interrupt, TRNIF will not be cleared when the interrupt vector is executed. This flag is cleared by writing a one to
this location.
Bit 3:2 – ERRINTLVL[1:0]: Channel Error Interrupt Level
These bits enable the interrupt for DMA channel transfer errors and select the interrupt level, as described in
“Interrupts and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will trigger for the
conditions when ERRIF is set.
Bit 1:0 – TRNINTLVL[1:0]: Channel Transaction Complete Interrupt Level
These bits enable the interrupt for DMA channel transaction completes and select the interrupt level, as described
in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will trigger for
the conditions when TRNIF is set.
5.14.3 ADDRCTRL – Address Control register
Bit
7
6
5
4
3
2
1
0
+0x02
SRCRELOAD[1:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DESTRELOAD[1:0]
DESTDIR[1:0]
Bit 7:6 – SRCRELOAD[1:0]: Channel Source Address Reload
These bits decide the DMA channel source address reload according to Table 5-5 on page 61. A write to these bits
is ignored while the channel is busy.
Table 5-5.
DMA channel source address reload settings.
SRCRELOAD[1:0]
SRCDIR[1:0]
Group configuration
Description
00
NONE
No reload performed.
01
BLOCK
DMA source address register is reloaded with initial value at end of each
block transfer.
10
BURST
DMA source address register is reloaded with initial value at end of each
burst transfer.
11
TRANSACTION
DMA source address register is reloaded with initial value at end of each
transaction.
Bit 5:4 – SRCDIR[1:0]: Channel Source Address Mode
These bits decide the DMA channel source address mode according to Table 5-6. These bits cannot be changed if
the channel is busy.
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Table 5-6.
DMA channel source address mode settings.
SRCDIR[1:0]
Group configuration
00
FIXED
01
INC
Increment
10
DEC
Decrement
11
–
Fixed
Reserved
Bit 3:2 – DESTRELOAD[1:0]: Channel Destination Address Reload
These bits decide the DMA channel destination address reload according to Table 5-7 on page 62. These bits cannot be changed if the channel is busy.
Table 5-7.
DMA channel destination address reload settings.
DESTRELOAD[1:0]
Description
Group configuration
Description
00
NONE
No reload performed.
01
BLOCK
DMA channel destination address register is reloaded with initial value
at end of each block transfer.
10
BURST
DMA channel destination address register is reloaded with initial value
at end of each burst transfer.
11
TRANSACTION
DMA channel destination address register is reloaded with initial value
at end of each transaction.
Bit 1:0 – DESTDIR[1:0]: Channel Destination Address Mode
These bits decide the DMA channel destination address mode according to Table 5-8 on page 62. These bits cannot be changed if the channel is busy.
Table 5-8.
DMA channel destination address mode settings.
DESTDIR[1:0]
Group configuration
Description
00
FIXED
Fixed
01
INC
Increment
10
DEC
Decrement
11
–
Reserved
5.14.4 TRIGSRC – Trigger Source
7
Bit
6
5
+0x03
4
3
2
1
0
TRIGSRC[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – TRIGSRC[7:0]: Channel Trigger Source Select
These bits select which trigger source is used for triggering a transfer on the DMA channel. A zero value means
that the trigger source is disabled. For each trigger source, the value to put in the TRIGSRC register is the sum of
the module’s or peripheral’s base value and the offset value for the trigger source in the module or peripheral.
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Table 5-9 on page 63 shows the base value for all modules and peripherals. Table 5-10 on page 64 to Table 5-13
on page 64 shows the offset value for the trigger sources in the different modules and peripheral types. For modules or peripherals which do not exist for a device, the transfer trigger does not exist. Refer to the device datasheet
for the list of peripherals available.
If the interrupt flag related to the trigger source is cleared or the interrupt level enabled so that an interrupt is triggered, the DMA request will be lost. Since a DMA request can clear the interrupt flag, interrupts can be lost.
Note:
For most trigger sources, the request is cleared by accessing a register belonging to the peripheral with the request. Refer to the different peripheral
chapters for how requests are generated and cleared.
Table 5-9.
DMA trigger source base values for all modules and peripherals.
TRIGSRC base value
Group configuration
Description
0x00
OFF
Software triggers only
0x01
SYS
Event system DMA triggers base value
0x04
AES
AES DMA trigger value
0x10
ADCA
ADCA DMA triggers base value
0x15
DACA
DACA DMA trigger bas
0x20
ADCB
ADCB DMA triggers base value
0x25
DACB
DACB DMA triggers base value
0x40
TCC0
Timer/counter C0 DMA triggers base value
0x46
TCC1
Timer/counter C1 triggers base value
0x4A
SPIC
SPI C DMA triggers value
0x4B
USARTC0
USART C0 DMA triggers base value
0x4E
USARTC1
USART C1 DMA triggers base value
0x60
TCD0
Timer/counter D0 DMA triggers base value
0x66
TCD1
Timer/counter D1 triggers base value
0x6A
SPID
SPI D DMA triggers value
0x6B
USARTD0
USART D0 DMA triggers base value
0x6E
USARTD1
USART D1 DMA triggers base value
0x80
TCE0
Timer/counter E0 DMA triggers base value
0x86
TCE1
Timer/counter E1 triggers base value
0x8A
SPIE
SPI E DMA triggers value
0x8B
USARTE0
USART E0 DMA triggers base value
0x8E
USARTE1
USART E1 DMA triggers base value
0xA0
TCF0
Timer/counter F0 DMA triggers base value
0xA6
TCF1
Timer/counter F1 triggers base value
0xAA
SPIF
SPI F DMA trigger value
0xAB
USARTF0
USART F0 DMA triggers base value
0xAE
USARTF1
USART F1 DMA triggers base value
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Table 5-10. DMA trigger source offset values for event system triggers.
TRGSRC offset value
Group configuration
Description
+0x00
CH0
Event channel 0
+0x01
CH1
Event channel 1
+0x02
CH2
Event channel 2
Table 5-11. DMA trigger source offset values for DAC and ADC triggers.
TRGSRC offset value
1.
2.
Description
+0x00
CH0
ADC/DAC channel 0
+0x01
CH1
ADC/DAC channel 1
+0x02
CH2(1)
ADC channel 2
+0x03
CH3
ADC channel 3
+0x04
Notes:
Group configuration
(2)
CH4
ADC channel 0, 1, 2, 3
For DAC only, channel 0 and 1 exists and can be used as triggers.
Channel 4 equals ADC channel 0 to 3 all together.
Table 5-12. DMA trigger source offset values for timer/ counter triggers.
TRGSRC offset value
Note:
1.
Group configuration
Description
+0x00
OVF
Overflow/underflow
+0x01
ERR
Error
+0x02
CCA
Compare or capture channel A
+0x03
CCB
Compare or capture channel B
+0x04
CCC(1)
Compare or capture channel C
+0x05
CCD(1)
Compare or capture channel D
CC channel C and D triggers are available only for timer/counters 0.
Table 5-13. DMA trigger source offset values for USART triggers.
TRGSRC offset value
Group configuration
Description
0x00
RXC
Receive complete
0x01
DRE
Data register empty
The group configuration is the “base_offset;” for example, TCC1_CCA for the timer/counter C1 CC channel A the transfer
trigger.
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5.14.5 TRFCNTL – Channel Block Transfer Count register Low
The TRFCNTH and TRFCNTL register pair represents the 16-bit value TRFCNT. TRFCNT defines the number of bytes
in a block transfer. The value of TRFCNT is decremented after each byte read by the DMA channel. When TRFCNT
reaches zero, the register is reloaded with the last value written to it.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x04
TRFCNT[7:0]
Bit 7:0 – TRFCNT[7:0]: Channel n Block Transfer Count low byte
These bits hold the LSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trigger, DMA will be
doing 0xFFFF transfers.
5.14.6 TRFCNTH – Channel Block Transfer Count register High
Reading and writing 16-bit values requires special attention. For details, refer to “The combined EIND + Z register.” on
page 12.
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
+0x05
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
TRFCNT[15:8]
Bit 7:0 – TRFCNT[15:8]: Channel n Block Transfer Count high byte
These bits hold the MSB of the 16-bit block transfer count.
The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trigger, DMA will be
doing 0xFFFF transfers.
5.14.7 REPCNT – Repeat Counter register
Bit
7
6
5
4
+0x06
3
2
1
0
REPCNT[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
REPCNT counts how many times a block transfer is performed. For each block transfer, this register will be
decremented.
When repeat mode is enabled (see REPEAT bit in “ADDRCTRL – Address Control register” on page 61), this register is
used to control when the transaction is complete. The counter is decremented after each block transfer if the DMA has to
serve a limited number of repeated block transfers. When repeat mode is enabled, the channel is disabled when
REPCNT reaches zero and the last block transfer is completed. Unlimited repeat is achieved by setting this register to
zero.
5.14.8 SRCADDR0 – Source Address 0
SRCADDR0, SRCADDR1, and SRCADDR2 represent the 24-bit value SRCADDR, which is the DMA channel source
address. SRCADDR2 is the most significant byte in the register. SRCADDR may be automatically incremented or
decremented based on settings in the SRCDIR bits in “ADDRCTRL – Address Control register” on page 61.
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Bit
7
6
5
4
+0x08
3
2
1
0
SRCADDR[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – SRCADDR[7:0]: Channel Source Address Byte 0
These bits hold byte 0 of the 24-bit source address.
5.14.9 SRCADDR1 – Channel Source Address 1
Bit
7
6
5
4
+0x09
3
2
1
0
SRCADDR[15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – SRCADDR[15:8]: Channel Source Address Byte 1
These bits hold byte 1 of the 24-bit source address.
5.14.10 SRCADDR2 – Channel Source Address 2
Reading and writing 24-bit values require special attention. For details, refer to “Accessing 24- and 32-bit Registers” on
page 13.
Bit
7
6
5
4
+0x0A
3
2
1
0
SRCADDR[23:16]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – SRCADDR[23:16]: Channel Source Address Byte 2
These bits hold byte 2 of the 24-bit source address.
5.14.11 DESTADDR0 – Channel Destination Address 0
DESTADDR0, DESTADDR1, and DESTADDR2 represent the 24-bit value DESTADDR, which is the DMA channel
destination address. DESTADDR2 holds the most significant byte in the register. DESTADDR may be automatically
incremented or decremented based on settings in the DESTDIR bits in “ADDRCTRL – Address Control register” on page
61.
Bit
7
6
5
4
+0x0C
3
2
1
0
DESTADDR[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DESTADDR[7:0]: Channel Destination Address Byte 0
These bits hold byte 0 of the 24-bit source address.
5.14.12 DESTADDR1 – Channel Destination Address 1
Bit
7
6
5
4
+0x0D
3
2
1
0
DESTADDR[15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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Bit 7:0 – DESTADDR[15:8]: Channel Destination Address Byte 1
These bits hold byte 1 of the 24-bit source address.
5.14.13 DESTADDR2 – Channel Destination Address 2
Reading and writing 24-bit values require special attention. For details, refer to “Accessing 24- and 32-bit Registers” on
page 13.
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
+0x0E
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
DESTADDR[23:16]
Bit 7:0 – DESTADDR[23:16]: Channel Destination Address Byte 2
These bits hold byte 2 of the 24-bit source address.
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5.15
Register Summary – DMA Controller
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
+0x00
CTRL
ENABLE
RESET
–
–
+0x01
Reserved
–
–
–
–
–
–
–
–
+0x02
Reserved
–
–
–
–
–
–
–
–
+0x03
INTFLAGS
CH3ERRIF
CH2ERRIF
CH1ERRIF
CH0ERRIF
CH3TRNFIF
CH2TRNFIF
CH1TRNFIF
CH0TRNFIF
58
+0x04
STATUS
CH3BUSY
CH2BUSY
CH1BUSY
CH0BUSY
CH3PEND
CH2PEND
CH1PEND
CH0PEND
58
+0x05
Reserved
–
–
–
–
–
–
–
–
+0x06
TEMPL
TEMP[7:0]
58
+0x07
TEMPH
TEMP[15:8]
59
+0x10
CH0 Offset
Offset address for DMA Channel 0
+0x20
CH1 Offset
Offset address for DMA Channel 1
+0x30
CH2 Offset
Offset address for DMA Channel 2
+0x40
CH3 Offset
Offset address for DMA Channel 3
5.16
Bit 3
Bit 2
Bit 1
DBUFMODE[1:0]
Bit 0
Page
PRIMODE[1:0]
57
Register Summary – DMA Channel
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
+0x00
CTRLA
ENABLE
RESET
REPEAT
TRFREQ
–
SINGLE
+0x01
CTRLB
CHBUSY
CHPEND
ERRIF
TRNIF
+0x02
ADDCTRL
+0x03
TRIGSRC
TRIGSRC[7:0]
62
+0x04
TRFCNTL
TRFCNT[7:0]
65
+0x05
TRFCNTH
TRFCNT[15:8]
65
+0x06
REPCNT
REPCNT[7:0]
65
+0x07
Reserved
+0x08
SRCADDR0
SRCADDR[7:0]
65
+0x09
SRCADDR1
SRCADDR[15:8]
66
+0x0A
SRCADDR2
SRCADDR[23:16]
66
+0x0B
Reserved
+0x0C
DESTADDR0
DESTADDR[7:0]
66
+0x0D
DESTADDR1
DESTADDR[15:8]
66
+0x0E
DESTADDR2
DESTADDR[23:16]
67
+0x0F
Reserved
SRCRELOAD[1:0]
–
–
–
–
–
–
SRCDIR[1:0]
–
–
–
–
–
–
Bit 1
Bit 0
Page
BURSTLEN[1:0]
59
ERRINTLVL[1:0]
TRNINTLVL[1:0]
60
DESTRELOAD[1:0]
DESTDIR[1:0]
61
–
–
–
–
–
–
–
–
–
–
–
–
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5.17
Interrupt vector summary
Table 5-14. DMA interrupt vectors and their word offset addresses from the DMA controller interrupt base.
Offset
Source
Interrupt description
0x00
CH0_vect
DMA controller channel 0 interrupt vector
0x02
CH1_vect
DMA controller channel 1 interrupt vector
0x04
CH2_vect
DMA controller channel 2 interrupt vector
0x06
CH3_vect
DMA controller channel 3 interrupt vector
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6.
Event System
6.1
Features
System for direct peripheral-to-peripheral communication and signaling
Peripherals can directly send, receive, and react to peripheral events
CPU and DMA controller independent operation
100% predictable signal timing
Short and guaranteed response time
Eight event channels for up to eight different and parallel signal routing and configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders
Digital filtering of I/O pin state
Works in active mode and idle sleep mode
6.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It also allows for synchronized timing of actions in several peripheral
modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 6-1 on page 71 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller).
Events can also be generated from software and the peripheral clock.
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Figure 6-1. Event system overview and connected peripherals.
CPU /
Software
DMA
Controller
Event Routing Network
ADC
AC
clkPER
Prescaler
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
USB
Port pins
IRCOM
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to eight parallel event configurations and routings. The
maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep
mode.
6.3
Events
In the context of the event system, an indication that a change of state within a peripheral has occurred is called an
event. There are two main types of events: signaling events and data events. Signaling events only indicate a change of
state while data events contain additional information about the event.
The peripheral from which the event originates is called the event generator. Within each peripheral (for example, a
timer/counter), there can be several event sources, such as a timer compare match or timer overflow. The peripheral
using the event is called the event user, and the action that is triggered is called the event action.
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Figure 6-2. Example of event source, generator, user, and action.
Event Generator
Event User
Timer/Counter
ADC
Compare Match
Over-/Underflow
|
Error
Event
Routing
Network
Channel Sweep
Single
Conversion
Event Action Selection
Event Source
Event Action
Events can also be generated manually in software.
6.3.1
Signaling Events
Signaling events are the most basic type of event. A signaling event does not contain any information apart from the
indication of a change in a peripheral. Most peripherals can only generate and use signaling events. Unless otherwise
stated, all occurrences of the word ”event” are to be understood as meaning signaling events.
6.3.2
Data Events
Data events differ from signaling events in that they contain information that event users can decode to decide event
actions based on the receiver information.
Although the event routing network can route all events to all event users, those that are only meant to use signaling
events do not have decoding capabilities needed to utilize data events. How event users decode data events is shown in
Table 6-1 on page 73.
Event users that can utilize data events can also use signaling events. This is configurable, and is described in the
datasheet module for each peripheral.
6.3.3
Peripheral Clock Events
Each event channel includes a peripheral clock prescaler with a range from 1 (no prescaling) to 32768. This enables
configurable periodic event generation based on the peripheral clock. It is possible to periodically trigger events in a
peripheral or to periodically trigger synchronized events in several peripherals. Since each event channel include a
prescaler, different peripherals can receive triggers with different intervals.
6.3.4
Software Events
Events can be generated from software by writing the DATA and STROBE registers. The DATA register must be written
first, since writing the STROBE register triggers the operation. The DATA and STROBE registers contain one bit for each
event channel. Bit n corresponds to event channel n. It is possible to generate events on several channels at the same
time by writing to several bit locations at once.
Software-generated events last for one clock cycle and will overwrite events from other event generators on that event
channel during that clock cycle.
Table 6-1 on page 73 shows the different events, how they can be manually generated, and how they are decoded.
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Table 6-1.
6.4
Quadrature decoder data events.
STROBE
DATA
Data event user
Signaling event user
0
0
No event
No event
0
1
Data event 01
No event
1
0
Data event 02
Signaling event
1
1
Data event 03
Signaling event
Event Routing Network
The event routing network routes the events between peripherals. It consists of eight multiplexers (CHnMUX), which can
each be configured to route any event source to any event users. The output from a multiplexer is referred to as an event
channel. For each peripheral, it is selectable if and how incoming events should trigger event actions. Details on
configurations can be found in the datasheet for each peripheral. The event routing network is shown in Figure 6-3 on
page 74.
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Figure 6-3. Event routing network.
Event
Event
Event
Event
Event
Event
Event
Event
(8)
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
7
6
5
4
3
2
1
0
(10)
TCC0
(6)
TCC1
(4)
CH0CTRL[7:0]
(8)
(10)
TCD0
(6)
TCD1
(4)
CH0MUX[7:0]
CH1CTRL[7:0]
(10)
TCE0
(6)
TCE1
(4)
TCF0
(6)
TCF1
(4)
(8)
ADCA
(4)
(8)
ADCB
(4)
(8)
DACA
(8)
DACB
(8)
(8)
USB
CH1MUX[7:0]
CH2CTRL[7:0]
(10)
CH2MUX[7:0]
(36)
CH3CTRL[7:0]
CH3MUX[7:0]
CH4CTRL[7:0]
(4)
CH4MUX[7:0]
ACA
(3)
ACB
(3)
CH5CTRL[7:0]
RTC
(2)
ClkPER
(16)
PORTA
(8)
CH6CTRL[7:0]
PORTB
(8)
CH6MUX[7:0]
CH5MUX[7:0]
(48)
PORTC
(8)
PORTD
(8)
PORTE
(8)
CH7CTRL[7:0]
PORTF
(8)
CH7MUX[7:0]
Eight multiplexers means that it is possible to route up to eight events at the same time. It is also possible to route one
event through several multiplexers.
Not all XMEGA devices contain all peripherals. This only means that a peripheral is not available for generating or using
events. The network configuration itself is compatible between all devices.
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6.5
Event Timing
An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will
generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise
stated, an event lasts for one peripheral clock cycle.
It takes a maximum of two peripheral clock cycles from when an event is generated until the event actions in other
peripherals are triggered. This ensures short and 100% predictable response times, independent of CPU or DMA
controller load or software revisions.
6.6
Filtering
Each event channel includes a digital filter. When this is enabled, an event must be sampled with the same value for a
configurable number of system clock cycles before it is accepted. This is primarily intended for pin change events.
6.7
Quadrature Decoder
The event system includes three quadrature decoders (QDECs), which enable the device to decode quadrature input on
I/O pins and send data events that a timer/counter can decode to count up, count down, or index/reset. Table 6-2 on
page 75 summarizes which quadrature decoder data events are available, how they are decoded, and how they can be
generated. The QDECs and related features and control and status registers are available for event channels 0, 2, and 4.
Table 6-2.
6.7.1
Quadrature decoder data events.
STROBE
DATA
Data event user
Signaling event user
0
0
No event
No event
0
1
Index/reset
No event
1
0
Count down
Signaling event
1
1
Count up
Signaling event
Quadrature Operation
A quadrature signal is characterized by having two square waves that are phase shifted 90 degrees relative to each
other. Rotational movement can be measured by counting the edges of the two waveforms. The phase relationship
between the two square waves determines the direction of rotation.
Figure 6-4. Quadrature signals from a rotary encoder.
1 cycle / 4 states
Forward Direction
QDPH0
QDPH90
QDINDX
00
10
11
01
01
11
10
00
Backward
Direction
QDPH0
QDPH90
QDINDX
Figure 6-4 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and QDPH90 are the two
quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads
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QDPH90, the rotation is defined as negative or reverse. The concatenation of the two phase signals is called the
quadrature state or the phase state.
In order to know the absolute rotary displacement, a third index signal (QINDX) can be used. This gives an indication
once per revolution.
6.7.2
QDEC Setup
For a full QDEC setup, the following is required:
Two or three I/O port pins for quadrature signal input
Two event system channels for quadrature decoding
One timer/counter for up, down, and optional index count
The following procedure should be used for QDEC setup:
1.
Choose two successive pins on a port as QDEC phase inputs.
2.
Set the pin direction for QDPH0 and QDPH90 as input.
3.
Set the pin configuration for QDPH0 and QDPH90 to low level sense.
4.
Select the QDPH0 pin as a multiplexer input for an event channel, n.
5.
Enable quadrature decoding and digital filtering in the event channel.
6.
Optional:
1.
Set up a QDEC index (QINDX).
2.
Select a third pin for QINDX input.
3.
Set the pin direction for QINDX as input.
4.
Set the pin configuration for QINDX to sense both edges.
5.
Select QINDX as a multiplexer input for event channel n+1
6.
Set the quadrature index enable bit in event channel n.
7.
Select the index recognition mode for event channel n.
7.
Set quadrature decoding as the event action for a timer/counter.
8.
Select event channel n as the event source for the timer/counter.
Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the quadrature encoder.
Enable the timer/counter without clock prescaling.
The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read directly from the
timer/counter count register. If the count register is different from BOTTOM when the index is recognized, the
timer/counter error flag is set. Similarly, the error flag is set if the position counter passes BOTTOM without the
recognition of the index.
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6.8
Register Description
6.8.1
CHnMUX – Event Channel n Multiplexer register
Bit
7
6
5
4
3
2
1
0
CHnMUX[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer
These bits select the event source according to Table 6-3. This table is valid for all XMEGA devices regardless of
whether the peripheral is present or not. Selecting event sources from peripherals that are not present will give the
same result as when this register is zero. When this register is zero, no events are routed through. Manually generated events will override CHnMUX and be routed to the event channel even if this register is zero.
Table 6-3.
CHnMUX[7:0] bit settings.
CHnMUX[7:4]
CHnMUX[3:0]
Group configuration
Event source
0000
0
0
0
0
None (manually generated events only)
0000
0
0
0
1
(Reserved)
0000
0
0
1
X
(Reserved)
0000
0
1
X
X
(Reserved)
0000
1
0
0
0
RTC_OVF/RTC32_OVF
RTC overflow / RTC32 overflow
0000
1
0
0
1
RTC_CMP
RTC compare match
0000
1
0
1
0
USB start of frame on CH0 (see Table 6-4 on page 78)
USB error on CH1 (see Table 6-4 on page 78)
USB overflow on CH2 (see Table 6-4 on page 78)
USB setup on CH3 (see Table 6-4 on page 78)
0000
1
0
1
X
(Reserved)
0000
1
1
X
X
(Reserved)
0001
0
0
0
0
ACA_CH0
ACA channel 0
0001
0
0
0
1
ACA_CH1
ACA channel 1
0001
0
0
1
0
ACA_WIN
ACA window
0001
0
0
1
1
ACB_CH0
ACB channel 0
0001
0
1
0
0
ACB_CH1
ACB channel 1
0001
0
1
0
1
ACB_WIN
ACB window
0001
0
1
1
X
(Reserved)
0001
1
X
X
X
(Reserved)
0010
0
0
n
ADCA_CHn
ADCA channel n (n =0, 1, 2 or 3)
0010
0
1
n
ADCB_CHn
ADCB channel n (n=0, 1, 2 or 3)
0010
1
X
X
X
(Reserved)
0011
X
X
X
X
(Reserved)
0100
X
X
X
X
(Reserved)
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CHnMUX[7:4]
CHnMUX[3:0]
Group configuration
PORTA pin n (n= 0, 1, 2 ... or 7)
0101
0
n
PORTA_PINn
0101
1
n
PORTB_PINn(1)
PORTB pin n (n= 0, 1, 2 ... or 7)
(1)
PORTC pin n (n= 0, 1, 2 ... or 7)
0110
0
n
PORTC_PINn
0110
1
n
PORTD_PINn(1)
PORTD pin n (n= 0, 1, 2 ... or 7)
(1)
PORTE pin n (n= 0, 1, 2 ... or 7)
0111
0
n
PORTE_PINn
0111
1
n
PORTF_PINn(1)
PORTF pin n (n= 0, 1, 2 ... or 7)
PRESCALER_M
ClkPER divide by 2M (M=0 to 15)
1000
M
1001
X
X
X
X
(Reserved)
1010
X
X
X
X
(Reserved)
1011
X
X
X
X
(Reserved)
1100
0
E
See Table 6-4
Timer/counter C0 event type E
1100
1
E
See Table 6-4
Timer/counter C1 event type E
1101
0
E
See Table 6-4
Timer/counter D0 event type E
1101
1
E
See Table 6-4
Timer/counter D1 event type E
1110
0
E
See Table 6-4
Timer/counter E0 event type E
1110
1
E
See Table 6-4
Timer/counter E1 event type E
1111
0
E
See Table 6-4
Timer/counter F0 event type E
1111
1
E
See Table 6-4
Timer/counter F1 event type E
Notes: 1.
2.
Table 6-4.
The description of how the ports generate events is described in “Port Event” on page 145.
The different USB events can be selected for only event channel, 0 to 3.
Timer/counter events.
T/C event E
6.8.2
Event source
(1)
Group configuration
Event type
0
0
0
TCxn_OVF
Over/Underflow (x = C, D, E or F) (n= 0 or 1)
0
0
1
TCxn_ERR
Error (x = C, D, E or F) (n= 0 or 1)
0
1
X
1
0
0
TCxn_CCA
Capture or compare A (x = C, D, E or F) (n= 0 or 1)
1
0
1
TCxn_CCB
Capture or compare B (x = C, D, E or F) (n= 0 or 1)
1
1
0
TCxn_CCC
Capture or compare C (x = C, D, E or F) (n= 0)
1
1
1
TCxn_CCD
Capture or compare D (x = C, D, E or F) (n= 0)
(Reserved)
CHnCTRL – Event Channel n Control register
Bit
7
6
5
QDIRM[1:0]
–
4
3
QDIEN
QDEN
2
1
0
DIGFILT[2:0]
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0
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Bit 7 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always write this bit to
zero when this register is written.
Bit 6:5 – QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals, where a valid index signal is recognized and the counter index data event is given according to Table 6-5 on page 79. These bits should only be
set when a quadrature encoder with a connected index signal is used.These bits are available only for CH0CTRL,
CH2CTRL, and CH4CTRL.
Table 6-5.
QDIRM bit settings..
QDIRM[1:0]
Index recognition state
0
0
{QDPH0, QDPH90} = 0b00
0
1
{QDPH0, QDPH90} = 0b01
1
0
{QDPH0, QDPH90} = 0b10
1
1
{QDPH0, QDPH90} = 0b11
Bit 4 – QDIEN: Quadrature Decode Index Enable
When this bit is set, the event channel will be used as a QDEC index source, and the index data event will be
enabled.
This bit is available only for CH0CTRL, CH2CTRL, and CH4CTRL.
Bit 3 – QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
This bit is available only for CH0CTRL, CH2CTRL, and CH4CTRL.
Bit 2:0 – DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event channel only when
the event source has been active and sampled with the same level for the number of peripheral clock cycles
defined by DIGFILT.
Table 6-6.
Digital filter coefficient values .
DIGFILT[2:0]
Group configuration
Description
000
1SAMPLE
One sample
001
2SAMPLES
Two samples
010
3SAMPLES
Three samples
011
4SAMPLES
Four samples
100
5SAMPLES
Five samples
101
6SAMPLES
Six samples
110
7SAMPLES
Seven samples
111
8SAMPLES
Eight samples
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6.8.3
STROBE – Strobe register
If the STROBE register location is written, each event channel will be set according to the STROBE[n] and corresponding
DATA[n] bit settings, if any are unequal to zero.
A single event lasting for one peripheral clock cycle will be generated.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x10
6.8.4
STROBE[7:0]
DATA – Data register
This register contains the data value when manually generating a data event. This register must be written before the
STROBE register. For details, See ”STROBE – Strobe register” on page 80.
Bit
7
6
5
4
+0x11
3
2
1
0
DATA[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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6.9
Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
+0x00
CH0MUX
CH0MUX[7:0]
77
+0x01
CH1MUX
CH1MUX[7:0]
77
+0x02
CH2MUX
CH2MUX[7:0]
77
+0x03
CH3MUX
CH3MUX[7:0]
77
+0x04
CH4MUX
CH4MUX[7:0]
77
+0x05
CH5MUX
CH5MUX[7:0]
77
+0x06
CH6MUX
CH6MUX[7:0]
77
+0x07
CH7MUX
CH7MUX[7:0]
77
+0x08
CH0CTRL
–
+0x09
CH1CTRL
–
+0x0A
CH2CTRL
–
+0x0B
CH3CTRL
–
+0x0C
CH4CTRL
–
+0x0D
CH5CTRL
–
–
+0x0E
CH6CTRL
–
+0x0F
CH7CTRL
–
+0x10
STROBE
STROBE[7:0]
80
+0x11
DATA
DATA[7:0]
80
QDIRM[1:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
QDIEN
QDEN
DIGFILT[2:0]
78
–
–
DIGFILT[2:0]
78
QDIEN
QDEN
DIGFILT[2:0]
78
–
–
DIGFILT[2:0]
78
QDIEN
QDEN
DIGFILT[2:0]
78
–
–
–
DIGFILT[2:0]
78
–
–
–
–
DIGFILT[2:0]
78
–
–
–
–
DIGFILT[2:0]
78
–
–
QDIRM[1:0]
–
–
QDIRM[1:0]
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7.
System Clock and Clock Options
7.1
Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1x to 31x multiplication
Lock detector
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at 2 and 4 times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
7.2
Overview
XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate
internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and
clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available,
and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and
temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal
oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 7-1 on page 83 presents the principal clock system in the XMEGA family of devices. Not all of the clocks need to
be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 103.
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Figure 7-1. The clock system, clock sources, and clock distribution.
Real Time
Counter
RAM
Peripherals
AVR CPU
Non-Volatile
Memory
clkPER
clkCPU
clkPER2
clkPER4
USB
clkUSB
Brown-out
Detector
System Clock Prescalers
Watchdog
Timer
Prescaler
clkSYS
clkRTC
System Clock Multiplexer
(SCLKSEL)
RTCSRC
USBSRC
DIV32
DIV32
DIV32
PLL
PLLSRC
DIV4
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
0.4 – 16 MHz
XTAL
32 MHz
Int. Osc
2 MHz
Int. Osc
XTAL2
XTAL1
TOSC2
TOSC1
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7.3
Clock Distribution
Figure 7-1 on page 83 presents the principal clock distribution system used in XMEGA devices.
7.3.1
System Clock - ClkSYS
The system clock is the output from the main system clock selection. This is fed into the prescalers that are used to
generate all internal clocks except the asynchronous and USB clocks.
7.3.2
CPU Clock - ClkCPU
The CPU clock is routed to the CPU and nonvolatile memory. Halting the CPU clock inhibits the CPU from executing
instructions.
7.3.3
Peripheral Clock - ClkPER
The majority of peripherals and system modules use the peripheral clock. This includes the DMA controller, event
system, interrupt controller, external bus interface and RAM. This clock is always synchronous to the CPU clock, but may
run even when the CPU clock is turned off.
7.3.4
Peripheral 2x/4x Clocks - ClkPER2/ClkPER4
Modules that can run at two or four times the CPU clock frequency can use the peripheral 2x and peripheral 4x clocks.
7.3.5
Asynchronous Clock - ClkRTC
The asynchronous clock allows the real-time counter (RTC) to be clocked directly from an external 32.768kHz crystal
oscillator or the 32 times prescaled output from the internal 32.768kHz oscillator or ULP oscillator. The dedicated clock
domain allows operation of this peripheral even when the device is in sleep mode and the rest of the clocks are stopped.
7.3.6
USB Clock - ClkUSB
The USB device module requires a 12MHz or 48MHz clock. It has a separate clock source selection in order to avoid
system clock source limitations when USB is used.
7.4
Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
7.4.1
Internal Oscillators
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
7.4.1.1 32kHz Ultra Low Power Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy.The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
7.4.1.2 32.768kHz Calibrated Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
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7.4.1.3 32MHz Run-time Calibrated Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The
production signature row contains 48 MHz calibration values intended used when the oscillator is used a full-speed USB
clock source.
7.4.1.4 2MHz Run-time Calibrated Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
7.4.2
External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
7.4.2.1 0.4MHz - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4MHz - 16MHz.
Figure 7-2 shows a typical connection of a crystal oscillator or resonator.
Figure 7-2. Crystal oscillator connection.
C2
XTAL2
C1
XTAL1
GND
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal.
7.4.2.2 External Clock Input
To drive the device from an external clock source, XTAL1 must be driven as shown in Figure 7-3 on page 85. In this
mode, XTAL2 can be used as a general I/O pin.
Figure 7-3. External clock drive configuration.
General
Purpose
I/O
XTAL2
External
Clock
Signal
XTAL1
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7.4.2.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A typical connection is shown in Figure 7-4 on page 86. A low power mode with reduced
voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as
the DFLL reference clock.
Figure 7-4. 32.768kHz crystal oscillator connection.
C2
TOSC2
C1
TOSC1
GND
Two capacitors, C1 and C2, may be added to match the required load capacitance for the connected crystal. For details
on recommended TOSC characteristics and capacitor load, refer to device datasheets.
7.5
System Clock Selection and Prescalers
All the calibrated internal oscillators, the external clock sources (XOSC), and the PLL output can be used as the system
clock source. The system clock source is selectable from software, and can be changed during normal operation. Built-in
hardware protection prevents unsafe clock switching. It is not possible to select a non-stable or disabled oscillator as the
clock source, or to disable the oscillator currently used as the system clock source. Each oscillator option has a status
flag that can be read from software to check that the oscillator is ready.
The system clock is fed into a prescaler block that can divide the clock signal by a factor from 1 to 2048 before it is routed
to the CPU and peripherals. The prescaler settings can be changed from software during normal operation. The first
stage, prescaler A, can divide by a factor of from 1 to 512. Then, prescalers B and C can be individually configured to
either pass the clock through or combine divide it by a factor from 1 to 4. The prescaler guarantees that derived clocks
are always in phase, and that no glitches or intermediate frequencies occur when changing the prescaler setting. The
prescaler settings are updated in accordance with the rising edge of the slowest clock.
Figure 7-5. System clock selection and prescalers.
Clock Selection
Internal 32.768kHz Osc.
ClkPER4
Internal 2MHz Osc.
ClkPER2
ClkCPU
Internal 32MHz Osc.
Internal PLL.
ClkSYS
Prescaler A
1, 2, 4, ... , 512
Prescaler B
1, 2, 4
Prescaler C
1, 2
ClkPER
External Oscillator or Clock.
Prescaler A divides the system clock, and the resulting clock is clkPER4. Prescalers B and C can be enabled to divide the
clock speed further to enable peripheral modules to run at twice or four times the CPU clock frequency. If Prescalers B
and C are not used, all the clocks will run at the same frequency as the output from Prescaler A.
The system clock selection and prescaler registers are protected by the configuration change protection mechanism,
employing a timed write procedure for changing the system clock and prescaler settings. For details, refer to
“Configuration Change Protection” on page 13.
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7.6
PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. The output frequency, fOUT, is given by the input frequency, fIN, multiplied
by the multiplication factor, PLL_FAC.
f OUT = f IN PLL_FAC
Four different clock sources can be chosen as input to the PLL:
2MHz internal oscillator
32MHz internal oscillator divided by 4
0.4MHz - 16MHz crystal oscillator
External clock
To enable the PLL, the following procedure must be followed:
1. Enable reference clock source.
2. Set the multiplication factor and select the clock reference for the PLL.
3. Wait until the clock reference source is stable.
4. Enable the PLL.
Hardware ensures that the PLL configuration cannot be changed when the PLL is in use. The PLL must be disabled
before a new configuration can be written.
It is not possible to use the PLL before the selected clock source is stable and the PLL has locked.
The reference clock source cannot be disabled while the PLL is running.
7.7
DFLL 2MHz and DFLL 32MHz
Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz
internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to do automatic
run-time calibration of the oscillator and compensate for temperature and voltage drift. The choices for the reference
clock sources are:
32.768kHz calibrated internal oscillator
32.768kHz crystal oscillator connected to the TOSC pins
External clock
USB start of frame
The DFLLs divide the oscillator reference clock by 32 to use a 1.024kHz reference. The reference clock is individually
selected for each DFLL, as shown on Figure 7-6 on page 88.
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Figure 7-6. DFLL reference clock selection.
XOSCSEL
TOSC1
TOSC2
XTAL1
32.768 kHz Crystal Osc
External Clock
32.768 kHz Int. Osc
DIV32
DIV32
USB Start of Frame
clkRC2MCREF
clkRC32MCREF
DFLL32M
32 MHz Int. RCOSC
DFLL2M
2 MHz Int. RCOSC
The ideal counter value representing the frequency ratio between the internal oscillator and a 1.024kHz reference clock
is loaded into the DFLL oscillator compare register (COMP) during reset. For the 32MHz oscillator, this register can be
written from software to make the oscillator run at a different frequency or when the ratio between the reference clock
and the oscillator is different (for example when the USB start of frame is used). The 48MHz calibration values must be
read from the production signature row and written to the 32MHz CAL register before the DFLL is enabled with USB SOF
as reference source.
The value that should be written to the COMP register is given by the following formula:
COMP hex (
f OSC
f RCnCREF
)
When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the
internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to
adjust the oscillator frequency. The oscillator is considered running too fast or too slow when the error is more than a half
calibration step size.
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Figure 7-7. Automatic run-time calibration.
clkRCnCREF
DFLL CNT
tRCnCREF
COMP
0
Frequency
OK
RCOSC fast,
CALA decremented
RCOSC slow,
CALA incremented
The DFLL will stop when entering a sleep mode where the oscillators are stopped. After wake up, the DFLL will continue
with the calibration value found before entering sleep. The reset value of the DFLL calibration register can be read from
the production signature row.
When the DFLL is disabled, the DFLL calibration register can be written from software for manual run-time calibration of
the oscillator.
7.8
PLL and External Clock Source Failure Monitor
A built-in failure monitor is available for the PLL and external clock source. If the failure monitor is enabled for the PLL
and/or the external clock source, and this clock source fails (the PLL looses lock or the external clock source stops) while
being used as the system clock, the device will:
Switch to run the system clock from the 2MHz internal oscillator
Reset the oscillator control register and system clock selection register to their default values
Set the failure detection interrupt flag for the failing clock source (PLL or external clock)
Issue a non-maskable interrupt (NMI)
If the PLL or external clock source fails when not being used for the system clock, it is automatically disabled, and the
system clock will continue to operate normally. No NMI is issued. The failure monitor is meant for external clock sources
above 32kHz. It cannot be used for slower external clocks.
When the failure monitor is enabled, it will not be disabled until the next reset.
The failure monitor is stopped in all sleep modes where the PLL or external clock source are stopped. During wake up
from sleep, it is automatically restarted.
The PLL and external clock source failure monitor settings are protected by the configuration change protection
mechanism, employing a timed write procedure for changing the settings. For details, refer to “Configuration Change
Protection” on page 13.
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7.9
Register Description – Clock
7.9.1
CTRL – Control register
Bit
7
6
5
4
3
+0x00
–
–
–
–
–
2
1
0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SCLKSEL[2:0]
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2:0 – SCLKSEL[2:0]: System Clock Selection
These bits are used to select the source for the system clock. See Table 7-1 on page 90 for the different selections. Changing the system clock source will take two clock cycles on the old clock source and two more clock
cycles on the new clock source. These bits are protected by the configuration change protection mechanism. For
details, refer to “Configuration Change Protection” on page 13.
SCLKSEL cannot be changed if the new clock source is not stable. The old clock can not be disabled until the
clock switching is completed.
Table 7-1.
System clock selection.
SCLKSEL[2:0]
7.9.2
Group configuration
Description
000
RC2MHZ
2MHz internal oscillator
001
RC32MHZ
32MHz internal oscillator
010
RC32KHZ
32.768kHz internal oscillator
011
XOSC
External oscillator or clock
100
PLL
Phase locked loop
101
–
Reserved
110
–
Reserved
111
–
Reserved
PSCTRL – Prescaler register
This register is protected by the configuration change protection mechanism. For details, refer to “Configuration Change
Protection” on page 13.
Bit
7
6
5
4
3
2
1
0
+0x01
–
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PSADIV[4:0]
PSBCDIV
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
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Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor
These bits define the division ratio of the clock prescaler A according to Table 7-2 on page 91. These bits can be
written at run-time to change the frequency of the ClkPER4 clock relative to the system clock, ClkSYS.
Table 7-2.
Prescaler A division factor.
PSADIV[4:0]
Group configuration
Description
00000
1
No division
00001
2
Divide by 2
00011
4
Divide by 4
00101
8
Divide by 8
00111
16
Divide by 16
01001
32
Divide by 32
01011
64
Divide by 64
01101
128
Divide by 128
01111
256
Divide by 256
10001
512
Divide by 512
10101
Reserved
10111
Reserved
11001
Reserved
11011
Reserved
11101
Reserved
11111
Reserved
Bit 1:0 – PSBCDIV: Prescaler B and C Division Factors
These bits define the division ratio of the clock prescalers B and C according to Table 7-3 on page 91. Prescaler B
will set the clock frequency for the ClkPER2 clock relative to the ClkPER4 clock. Prescaler C will set the clock frequency for the ClkPER and ClkCPU clocks relative to the ClkPER2 clock. Refer to Figure 7-5 on page 86 fore more
details.
Table 7-3.
Prescaler B and C division factors.
PSBCDIV[1:0]
Group configuration
Prescaler B division
Prescaler C division
00
1_1
No division
No division
01
1_2
No division
Divide by 2
10
4_1
Divide by 4
No division
11
2_2
Divide by 2
Divide by 2
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7.9.3
LOCK – Lock register
Bit
7
6
5
4
3
2
1
0
+0x02
–
–
–
–
–
–
–
LOCK
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – LOCK: Clock System Lock
When this bit is written to one, the CTRL and PSCTRL registers cannot be changed, and the system clock selection and prescaler settings are protected against all further updates until after the next reset. This bit is protected
by the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page
13.
The LOCK bit can be cleared only by a reset.
7.9.4
RTCCTRL – RTC Control register
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
RTCSRC[2:0]
RTCEN
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:1 – RTCSRC[2:0]: RTC Clock Source
These bits select the clock source for the real-time counter according to Table 7-4 on page 92.
Table 7-4.
RTC clock source selection(1).
RTCSRC[2:0]
Notes:
1.
2.
Group configuration
Description
000
ULP
1kHz from 32kHz internal ULP oscillator
001
TOSC
1.024kHz from 32.768kHz crystal oscillator on TOSC
010
RCOSC
1.024kHz from 32.768kHz internal oscillator(2)
011
–
Reserved
100
–
Reserved
101
TOSC32
32.768kHz from 32.768kHz crystal oscillator on TOSC
110
RCOSC32
32.768kHz from 32.768kHz internal oscillator
111
EXTCLK
External clock from TOSC1(2)
This table is not applicable for RTC32
Not available on devices with Battery Backup System
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7.9.5
Bit 0 – RTCEN: RTC Clock Source Enable
Setting the RTCEN bit enables the selected RTC clock source for the real-time counter.
USBCTRL – USB Control register
Bit
7
6
5
4
3
2
1
0
+0x04
–
–
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
USBPSDIV[2:0]
USBSRC[1:0]
USBSEN
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:3 – USBPSDIV[2:0]: USB Prescaler Division Factor
These bits define the division ratio of the USB clock prescaler according to Table 7-5 on page 93. These bits are
locked as long as the USB clock source is enabled.
Table 7-5.
USB prescaler division factor.
USBPSDIV[2:0]
Group configuration
Description
000
1
No division
001
2
Divide by 2
010
4
Divide by 4
011
8
Divide by 8
100
16
Divide by 16
101
32
Divide by 32
110
–
Reserved
111
–
Reserved
Bit 2:1 – USBSRC[1:0]: USB Clock Source
These bits select the clock source for the USB module according to Table 7-6 on page 93.
Table 7-6.
USB clock source.
USBSRC[1:0]
Note:
1.
Group configuration
Description
00
PLL
PLL
01
RC32M
32MHz internal oscillator(1)
The 32MHz internal oscillator must be calibrated to 48MHz before selecting this as source for the USB device module. Refer to “DFLL 2MHz and
DFLL 32MHz” on page 87.
Bit 0 – USBSEN: USB Clock Source Enable
Setting this bit enables the selected clock source for the USB device module.
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7.10
Register Description – Oscillator
7.10.1 CTRL – Oscillator Control register
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
–
PLLEN
XOSCEN
RC32KEN
RC32MEN
RC2MEN
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
1
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – PLLEN: PLL Enable
Setting this bit enables the PLL. Before the PLL is enabled, it must be configured with the desired multiplication
factor and clock source. See ”STATUS – Oscillator Status register” on page 94.
Bit 3 – XOSCEN: External Oscillator Enable
Setting this bit enables the selected external clock source. Refer to “XOSCCTRL – XOSC Control register” on
page 95 for details on how to select the external clock source. The external clock source should be allowed time to
stabilize before it is selected as the source for the system clock. See ”STATUS – Oscillator Status register” on
page 94.
Bit 2 – RC32KEN: 32.768kHz Internal Oscillator Enable
Setting this bit enables the 32.768kHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See ”STATUS – Oscillator Status register” on page 94.
Bit 1 – RC32MEN: 32MHz Internal Oscillator Enable
Setting this bit will enable the 32MHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See ”STATUS – Oscillator Status register” on page 94.
Bit 0 – RC2MEN: 2MHz Internal Oscillator Enable
Setting this bit enables the 2MHz internal oscillator. The oscillator must be stable before it is selected as the
source for the system clock. See ”STATUS – Oscillator Status register” on page 94.
By default, the 2MHz internal oscillator is enabled and this bit is set.
7.10.2 STATUS – Oscillator Status register
Bit
7
6
5
4
3
2
1
0
+0x01
–
–
–
PLLRDY
XOSCRDY
RC32KRDY
RC32MRDY
RC2MRDY
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – PLLRDY: PLL Ready
This flag is set when the PLL has locked on the selected frequency and is ready to be used as the system clock
source.
Bit 3 – XOSCRDY: External Clock Source Ready
This flag is set when the external clock source is stable and is ready to be used as the system clock source.
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7.10.3
Bit 2 – RC32KRDY: 32.768kHz Internal Oscillator Ready
This flag is set when the 32.768kHz internal oscillator is stable and is ready to be used as the system clock source.
Bit 1 – RC32MRDY: 32MHz Internal Oscillator Ready
This flag is set when the 32MHz internal oscillator is stable and is ready to be used as the system clock source.
Bit 0 – RC2MRDY: 2MHz Internal Oscillator Ready
This flag is set when the 2MHz internal oscillator is stable and is ready to be used as the system clock source.
XOSCCTRL – XOSC Control register
Bit
7
+0x02
FRQRANGE[1:0]
6
5
4
X32KLPM
XOSCPWR
3
2
1
0
XOSCSEL[3:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 7-7.
Bit 7:6 – FRQRANGE[1:0]: 0.4 - 16MHz Crystal Oscillator Frequency Range Select
These bits select the frequency range for the connected crystal oscillator according to Table 7-7 on page 95.
16MHz crystal oscillator frequency range selection.
FRQRANGE[1:0]
Group configuration
00
04TO2
0.4MHz - 2MHz
100-300
01
2TO9
2MHz - 9MHz
10-40
10
9TO12
9MHz - 12MHz
10-40
11
12TO16
12MHz - 16MHz
10-30
Note:
Typical frequency range
Recommended range for capacitors C1 and C2 (pF)
Refer to Electrical characteristics section in device datasheet to retrieve the best setting for a given frequency.
Bit 5 – X32KLPM: Crystal Oscillator 32.768kHz Low Power Mode
Setting this bit enables the low power mode for the 32.768kHz crystal oscillator. This will reduce the swing on the
TOSC2 pin.
Bit 4 – XOSCPWR: Crystal Oscillator Drive
Setting this bit will increase the current in the 0.4MHz - 16MHz crystal oscillator and increase the swing on the
XTAL2 pin. This allows for driving crystals with higher load or higher frequency than specified by the FRQRANGE
bits.
Bit 3:0 – XOSCSEL[3:0]: Crystal Oscillator Selection
These bits select the type and start-up time for the crystal or resonator that is connected to the XTAL or TOSC
pins. See Table 7-8 on page 96 for crystal selections. If an external clock or external oscillator is selected as the
source for the system clock, see “CTRL – Oscillator Control register” on page 94. This configuration cannot be
changed.
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Table 7-8.
External oscillator selection and start-up time.
XOSCSEL[3:0]
0000
Notes:
Group configuration
Selected clock source
EXTCLK(3)
External Clock
0010
32KHZ
0011
(3)
Start-up time
6 CLK
32.768kHz TOSC
16K CLK
XTAL_256CLK(1)
0.4MHz - 16MHz XTAL
256 CLK
0111
XTAL_1KCLK(2)
0.4MHz - 16MHz XTAL
1K CLK
1011
XTAL_16KCLK
0.4MHz - 16MHz XTAL
16K CLK
1.
2.
This option should be used only when frequency stability at startup is not important for the application. The option is not suitable for crystals.
This option is intended for use with ceramic resonators. It can also be used when the frequency stability at startup is not important for the
application.
3.
When the external oscillator is used as the reference for a DFLL, only EXTCLK and 32KHZ can be selected.
7.10.4 XOSCFAIL – XOSC Failure Detection register
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
–
PLLFDIF
PLLFDEN
XOSCFDIF
XOSCFDEN
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3 – PLLFDIF: PLL Fault Detection Flag
If PLL failure detection is enabled, PLLFDIF is set when the PLL looses lock. Writing logic one to this location will
clear PLLFDIF.
Bit 2 – PLLFDEN: PLL Fault Detection Enable
Setting this bit will enable PLL failure detection. A non-maskable interrupt will be issued when PLLFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on page 13 for details.
Bit 1 – XOSCFDIF: Failure Detection Interrupt Flag
If the external clock source oscillator failure monitor is enabled, XOSCFDIF is set when a failure is detected. Writing logic one to this location will clear XOSCFDIF.
Bit 0 – XOSCFDEN: Failure Detection Enable
Setting this bit will enable the failure detection monitor, and a non-maskable interrupt will be issued when
XOSCFDIF is set.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on page 13 for details. Once enabled, failure detection can only be disabled by a reset.
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7.10.5 RC32KCAL – 32kHz Oscillator Calibration register
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
x
x
x
x
+0x04
3
2
1
0
R/W
R/W
R/W
R/W
x
x
x
x
RC32KCAL[7:0]
Bit 7:0 – RC32KCAL[7:0]: 32.768kHz Internal Oscillator Calibration bits
This register is used to calibrate the 32.768kHz internal oscillator. A factory-calibrated value is loaded from the signature row of the device and written to this register during reset, giving an oscillator frequency close to 32.768kHz.
The register can also be written from software to calibrate the oscillator frequency during normal operation.
7.10.6 PLLCTRL – PLL Control register
Bit
7
+0x05
6
PLLSRC[1:0]
5
4
3
PLLDIV
2
1
0
PLLFAC[4:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:6 – PLLSRC[1:0]: Clock Source
The PLLSRC bits select the input source for the PLL according to Table 7-9 on page 100.
Table 7-9.
PLL clock source.
PLLSRC[1:0]
Notes:
1.
Group configuration
PLL input source
00
RC2M
2MHz internal oscillator
01
–
Reserved
10
RC32M
32MHz internal oscillator
11
XOSC
External clock source(1)
The 32.768kHz TOSC cannot be selected as the source for the PLL. An external clock must be a minimum 0.4MHz to be used as the source clock.
Bit 5 – PLLDIV: PLL Divided Output Enable
Setting this bit will divide the output from the PLL by 2.
Bit 4:0 – PLLFAC[4:0]: Multiplication Factor
These bits select the multiplication factor for the PLL. The multiplication factor can be in the range of from 1x to
31x.
7.10.7 DFLLCTRL – DFLL Control register
Bit
7
6
5
4
3
2
1
0
+0x06
–
–
–
–
–
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
RC32MCREF[1:0]
RC2MCREF
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
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Bit 2:1 – RC32MCREF[1:0]: 32MHz Oscillator Calibration Reference
These bits are used to select the calibration source for the 32MHz DFLL according to the Table 7-10 on page 101.
These bits will select only which calibration source to use for the DFLL. In addition, the actual clock source that is
selected must enabled and configured for the calibration to function.
Table 7-10. 32MHz oscillator reference selection.
RC32MCREF[1:0]
7.11
Group configuration
Description
00
RC32K
32.768kHz internal oscillator
01
XOSC32
32.768kHz crystal oscillator on TOSC
10
USBSOF
USB start of frame
11
–
Reserved
Bit 0 – RC2MCREF: 2MHz Oscillator Calibration Reference
This bit is used to select the calibration source for the 2MHz DFLL. By default, this bit is zero and the 32.768kHz
internal oscillator is selected. If this bit is set to one, the 32.768kHz crystal oscillator on TOSC is selected as the
reference. This bit will select only which calibration source to use for the DFLL. In addition, the actual clock source
that is selected must enabled and configured for the calibration to function.
Register Description – DFLL32M/DFLL2M
7.11.1 CTRL – DFLL Control register
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
–
–
–
–
–
ENABLE
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – ENABLE: DFLL Enable
Setting this bit enables the DFLL and auto-calibration of the internal oscillator. The reference clock must be
enabled and stable before the DFLL is enabled.
After disabling the DFLL, the reference clock can not be disabled before the ENABLE bit is read as zero.
7.11.2 CALA – DFLL Calibration Register A
The CALA and CALB registers hold the 13-bit DFLL calibration value that is used for automatic run-time calibration of the
internal oscillator. When the DFLL is disabled, the calibration registers can be written by software for manual run-time
calibration of the oscillator. The oscillators will also be calibrated according to the calibration value in these registers
when the DFLL is disabled.
Bit
7
+0x02
–
6
5
4
3
2
1
0
CALA[6:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
x
x
x
x
x
x
x
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Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6:0 – CALA[6:0]: DFLL Calibration Bits
These bits hold the part of the oscillator calibration value that is used for automatic runtime calibration. A factorycalibrated value is loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency approximate to the nominal frequency for the oscillator. The bits cannot be written when the
DFLL is enabled.
7.11.3 CALB – DFLL Calibration register B
Bit
7
+0x03
6
5
4
3
2
1
0
CALB[5:0]
–
–
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
x
x
x
x
x
x
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:0 – CALB[5:0]: DFLL Calibration bits
These bits hold the part of the oscillator calibration value that is used to select the oscillator frequency. A factorycalibrated value is loaded from the signature row of the device and written to this register during reset, giving an
oscillator frequency approximate to the nominal frequency for the oscillator. These bits are not changed during
automatic run-time calibration of the oscillator. The bits cannot be written when the DFLL is enabled. When calibrating to a frequency different from the default, the CALA bits should be set to a middle value to maximize the
range for the DFLL.
7.11.4 COMP1 – DFLL Compare register 1
The COMP1 and COMP2 register pair represent the frequency ratio between the oscillator and the reference clock. The
initial value for these registers is the ratio between the internal oscillator frequency and a 1.024kHz reference.
The initial value for these registers is the ratio between the internal oscillator frequency and a 1.024kHz reference;
0x7A12 for 32 MHz DFLL.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
–
–
–
–
–
–
–
–
3
2
1
0
+0x05
COMP[7:0]
Bit 7:0 – COMP1[7:0]: Compare Byte 1
These bits hold byte 1 of the 16-bit compare register.
7.11.5 COMP2 – DFLL Compare register 2
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
–
–
–
–
–
–
–
–
+0x06
COMP[15:8]
Bit 7:0 – COMP2[15:8]: Compare Byte 2
These bits hold byte 2 of the 16-bit compare register.
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Table 7-11. Nominal DFLL32M COMP values for different output frequencies.
Oscillator frequency (MHz)
COMP value (ClkRCnCREF = 1.024kHz)
30.0
0x7270
32.0
0x7A12
34.0
0x81B3
36.0
0x8954
38.0
0x90F5
40.0
0x9896
42.0
0xA037
44.0
0xA7D8
46.0
0xAF79
48.0
0xB71B
50.0
0xBEBC
52.0
0xC65D
54.0
0xCDFE
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7.12
Register summary – Clock
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
+0x00
CTRL
–
–
–
–
–
+0x01
PSCTRL
–
+0x02
LOCK
–
–
–
–
+0x03
RTCCTRL
–
–
–
–
+0x04
USBSCTRL
–
+0x05
Reserved
–
–
–
–
–
+0x06
Reserved
–
–
–
–
+0x07
Reserved
–
–
–
–
7.13
Bit 2
Bit 1
Bit 0
SCLKSEL[2:0]
PSADIV[4:0]
90
PSBCDIV[1:0]
–
–
–
Page
90
LOCK
92
RTCEN
92
USBSEN
USBPSDIV[2:0]
92
–
–
–
–
–
–
–
–
–
–
–
RTCSRC[2:0]
USBPSDIV[2:0]
USBSRC[1:0]
Register summary – Oscillator
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
CTRL
–
–
–
PLLEN
XOSCEN
RC32KEN
R32MEN
RC2MEN
94
+0x01
STATUS
–
–
–
PLLRDY
XOSCRDY
RC32KRDY
R32MRDY
RC2MRDY
94
+0x02
XOSCCTRL
X32KLPM
XOSCPWR
+0x03
XOSCFAIL
–
–
+0x04
RC32KCAL
+0x05
PLLCTRL
+0x06
DFLLCTRL
–
–
–
–
–
+0x07
Reserved
–
–
–
–
–
7.14
FRQRANGE[1:0]
–
–
XOSCSEL[3:0]
PLLFDIF
PLLFDEN
95
XOSCFDIF
XOSCFDEN
RC32KCAL[7:0]
PLLSRC[1:0]
PLLDIV
96
97
PLLFAC[4:0]
97
RC32MCREF[1:0]
–
–
RC2MCREF
97
–
Register summary – DFLL32M/DFLL2M
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
CTRL
–
–
–
–
–
–
–
ENABLE
98
+0x01
Reserved
–
–
–
–
–
–
–
–
+0x02
CALA
–
+0x03
CALB
–
–
+0x04
Reserved
–
–
+0x05
COMP1
COMP[7:0]
99
+0x06
COMP2
COMP[15:8]
99
+0x07
Reserved
–
CALA[6:0]
–
98
CALB[5:0]
–
–
–
–
–
–
99
–
–
–
–
–
–
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7.15
Oscillator failure interrupt vector summary
Table 7-12. Oscillator failure interrupt vector and its word offset address PLL and external oscillator failure interrupt base.
Offset
Source
Interrupt Description
0x00
OSCF_vect
PLL and external oscillator failure interrupt vector (NMI)
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8.
Power Management and Sleep Modes
8.1
Features
Power management for adjusting power consumption and functions
Five sleep modes
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
8.2
Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
8.3
Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
Table 8-1 on page 104 shows the different sleep modes and the active clock domains, oscillators, and wake-up sources.
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Table 8-1.
Active clock domains and wake-up sources in the different sleep modes.
System Clock Source
RTC Clock Source
USB Resume
Asynchronous Port Interrupts
TWI Address Match Interrupts
Real Time Clock Interrupts
All Interrupts
Idle
X
X
X
X
X
X
X
X
X
Power down
Power save
X
Standby
Extended standby
Wake-up Sources
RTC Clock
CPU Clock
Sleep Modes
Oscillators
Peripheral and USB Clock
Active Clock Domain
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The wake-up time for the device is dependent on the sleep mode and the main clock source. The startup time for the
system clock source must be added to the wake-up time for sleep modes where the system clock source is not kept
running. For details on the startup time for the different oscillator options, refer to “System Clock and Clock Options” on
page 82.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
8.3.1
Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
8.3.2
Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
8.3.3
Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
8.3.4
Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
8.3.5
Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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8.4
Power Reduction Registers
The power reduction (PR) registers provide a method to stop the clock to individual peripherals. When this is done, the
current state of the peripheral is frozen and the associated I/O registers cannot be read or written. Resources used by the
peripheral will remain occupied; hence, the peripheral should be disabled before stopping the clock. Enabling the clock to
a peripheral again puts the peripheral in the same state as before it was stopped. This can be used in idle mode and
active modes to reduce the overall power consumption. In all other sleep modes, the peripheral clock is already stopped.
Not all devices have all the peripherals associated with a bit in the power reduction registers. Setting a power reduction
bit for a peripheral that is not available will have no effect.
8.5
Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in an AVR MCU controlled
system. In general, correct sleep modes should be selected and used to ensure that only the modules required for the
application are operating.
All unneeded functions should be disabled. In particular, the following modules may need special consideration when
trying to achieve the lowest possible power consumption.
8.5.1
Analog-to-Digital Converter - ADC
When entering idle mode, the ADC should be disabled if not used. In other sleep modes, the ADC is automatically
disabled. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and
on again, the next conversion will be an extended conversion. Refer to “ADC – Analog-to-Digital Converter” on page 339
for details on ADC operation.
8.5.2
Analog Comparator - AC
When entering idle mode, the analog comparator should be disabled if not used. In other sleep modes, the analog
comparator is automatically disabled. However, if the analog comparator is set up to use the internal voltage reference as
input, the analog comparator should be disabled in all sleep modes. Otherwise, the internal voltage reference will be
enabled, irrespective of sleep mode. Refer to “AC – Analog Comparator” on page 377 for details on how to configure the
analog comparator.
8.5.3
Brownout Detector
If the brownout detector is not needed by the application, this module should be turned off. If the brownout detector is
enabled by the BODLEVEL fuses, it will be enabled in all sleep modes, and always consume power. In the deeper sleep
modes, it can be turned off and set in sampled mode to reduce current consumption. Refer to “Brownout Detection” on
page 112 for details on how to configure the brownout detector.
8.5.4
Watchdog Timer
If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled,
it will be enabled in all sleep modes and, hence, always consume power. Refer to “WDT – Watchdog Timer” on page 125
for details on how to configure the watchdog timer.
8.5.5
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. Most important is to ensure that
no pins drive resistive loads. In sleep modes where the Peripheral Clock (ClkPER) is stopped, the input buffers of the
device will be disabled. This ensures that no power is consumed by the input logic when not needed.
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8.6
Register Description – Sleep
8.6.1
CTRL – Control register
Bit
7
6
5
4
+0x00
–
–
–
–
3
2
1
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SMODE[2:0]
0
SEN
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:1 – SMODE[2:0]: Sleep Mode Selection
These bits select sleep modes according to Table 8-2 on page 106.
Table 8-2.
Sleep mode.
SMODE[2:0]
Group configuration
Description
000
IDLE
Idle mode
001
–
Reserved
010
PDOWN
Power-down mode
011
PSAVE
Power-save mode
100
–
Reserved
101
–
Reserved
110
STDBY
Standby mode
111
ESTDBY
Extended standby mode
Bit 0 – SEN: Sleep Enable
This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruction is executed. To
avoid unintentional entering of sleep modes, it is recommended to write SEN just before executing the SLEEP
instruction and clear it immediately after waking up.
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8.7
Register Description – Power Reduction
8.7.1
PRGEN – General Power Reduction register
8.7.2
Bit
7
6
5
4
3
2
1
0
+0x00
–
USB
–
AES
EBI
RTC
EVSYS
DMA
Read/Write
R
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6 – USB: USB Module
Setting this bit stops the clock to the USB module. When this bit is cleared, the peripheral should be reinitialized to
ensure proper operation.
Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 4 – AES: AES Module
Setting this bit stops the clock to the AES module. When this bit is cleared, the peripheral should be reinitialized to
ensure proper operation.
Bit 3 – EBI: External Bus Interface
Setting this bit stops the clock to the external bus interface. When this bit is cleared, the peripheral should be reinitialized to ensure proper operation.
Bit 2 – RTC: Real-Time Counter
Setting this bit stops the clock to the real-time counter. When this bit is cleared, the peripheral should be reinitialized to ensure proper operation.
Bit 1 – EVSYS: Event System
Setting this stops the clock to the event system. When this bit is cleared, the module will continue as before it was
stopped.
Bit 0 – DMA: DMA Controller
Setting this bit stops the clock to the DMA controller. This bit can be set only if the DMA controller is disabled.
PRPA/B – Power Reduction Port A/B register
Bit
7
6
5
4
3
2
1
0
+0x01/+0x02
–
–
–
–
–
DAC
ADC
AC
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Note:
Disabling of analog modules stops the clock to the analog blocks themselves and not only the interfaces.
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
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8.7.3
Bit 2 – DAC: Power Reduction DAC
Setting this bit stops the clock to the DAC. The DAC should be disabled before stopped.
Bit 1 – ADC: Power Reduction ADC
Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped.
Bit 0 – AC: Power Reduction Analog Comparator
Setting this bit stops the clock to the analog comparator. The AC should be disabled before shutdown.
PRPC/D/E/F – Power Reduction Port C/D/E/F register
Bit
7
6
5
4
3
2
1
0
+0x03/+0x04/+0x05/+0x06
–
TWI
USART1
USART0
SPI
HIRES
TC1
TC0
Read/Write
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 6 – TWI: Two-Wire Interface
Setting this bit stops the clock to the two-wire interface. When this bit is cleared, the peripheral should be reinitialized to ensure proper operation.
Bit 5 – USART1
Setting this bit stops the clock to USART1. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
Bit 4 – USART0
Setting this bit stops the clock to USART0. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
Bit 3 – SPI: Serial Peripheral Interface
Setting this bit stops the clock to the SPI. When this bit is cleared, the peripheral should be reinitialized to ensure
proper operation.
Bit 2 – HIRES: High-Resolution Extension
Setting this bit stops the clock to the high-resolution extension for the timer/counters. When this bit is cleared, the
peripheral should be reinitialized to ensure proper operation.
Bit 1 – TC1: Timer/Counter 1
Setting this bit stops the clock to timer/counter 1. When this bit is cleared, the peripheral will continue like before
the shut down.
Bit 0 – TC0: Timer/Counter 0
Setting this bit stops the clock to timer/counter 0. When this bit is cleared, the peripheral will continue like before
the shut down.
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8.8
Register summary – Sleep
Address
Name
Bit 7
Bit 6
+0x00
CTRL
–
–
8.9
Bit 5
Bit 4
Bit 3
–
Bit 2
Bit 1
SMODE[2:0]
Bit 0
Page
SEN
106
Register summary – Power reduction
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
PRGEN
–
USB
–
AES
EBI
RTC
EVSYS
DMA
106
+0x01
PRPA
–
–
–
–
–
DAC
ADC
AC
107
+0x02
PRPB
–
–
–
–
–
DAC
ADC
AC
107
+0x03
PRPC
–
TWI
USART1
USART0
SPI
HIRES
TC1
TC0
108
+0x04
PRPD
–
TWI
USART1
USART0
SPI
HIRES
TC1
TC0
108
+0x05
PRPE
–
TWI
USART1
USART0
SPI
HIRES
TC1
TC0
108
+0x06
PRPF
–
TWI
USART1
USART0
SPI
HIRES
TC1
TC0
108
+0x07
Reserved
–
–
–
–
–
–
–
–
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9.
Reset System
9.1
Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
9.2
Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontrollers operates below its power supply rating. If a
reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O
pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to
their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the
content of the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
An overview of the reset system is shown in Figure 9-1 on page 111.
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Figure 9-1. Reset system overview.
Power-on Reset
BODLEVEL [2:0]
PORF
BORF
EXTRF
WDRF
JTRF
MCU Status
Register (MCUSR)
Brown-out
Reset
Pull-up Resistor
SPIKE
FILTER
External
Reset
PDI
Reset
Software
Reset
Watchdog
Reset
ULP
Oscillator
Delay Counters
TIMEOUT
SUT[1:0]
9.3
Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
9.3.1
Reset Counter
The reset counter can delay reset release with a programmable period from when all reset requests are released. The
reset delay is timed from the 1kHz output of the ultra low power (ULP) internal oscillator, and in addition 24 System clock
(clkSYS) cycles are counted before reset is released. The reset delay is set by the STARTUPTIME fuse bits. The
selectable delays are shown in Table 9-1 on page 111.
Table 9-1.
Reset delay.
SUT[1:0]
Number of 1kHz ULP Oscillator Clock Cycles
Recommended Usage
00
64 ClkULP+ 24 ClkSYS
Stable frequency at startup
01
4 ClkULP + 24 ClkSYS
Slowly rising power
10
Reserved
–
11
24 ClkSYS
Fast rising power or BOD enabled
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Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for
ClkSYS.
9.3.2
Oscillator Startup
After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are automatically loaded from
the calibration row to the calibration registers.
9.4
Reset Sources
9.4.1
Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCCthan for rising VCC. Consult the datasheet for POR characteristics data.
Figure 9-2. MCU startup, RESET tied to VCC.
VCC
RESET
VPOT
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 9-3. MCU startup, RESET extended externally,
VCC
RESET
TIME-OUT
VPOT
VRST
tTOUT
INTERNAL
RESET
9.4.2
Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
When the BOD is enabled and VCC decreases to a value below the trigger level (VBOT- in Figure 9-4), the brownout reset
is immediately activated.
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When VCC increases above the trigger level (VBOT+ in Figure 9-4), the reset counter starts the MCU after the timeout
period, tTOUT, has expired.
The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level should
be interpreted as VBOT+= VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
The BOD circuit will detect a drop in VCC only if the voltage stays below the trigger level for longer than tBOD.
Figure 9-4. Brownout detection reset.
tBOD
VCC
VBOT-
VBOT+
tTOUT
TIME-OUT
INTERNAL
RESET
For BOD characterization data consult the device datasheet. The programmable BODLEVEL setting is shown in Table 92 on page 113.
Table 9-2.
Programmable BODLEVEL setting.
BOD level
Fuse BODLEVEL[2:0](2)
BOD level 0
111
1.6
BOD level 1
110
1.8
BOD level 2
101
2.0
BOD level 3
100
2.2
BOD level 4
011
2.4
BOD level 5
010
2.6
BOD level 6
001
2.8
BOD level 7
000
3.0
Notes: 1.
2.
VBOT(1)
Unit
V
The values are nominal values only. For accurate, actual numbers, consult the device datasheet.
Changing these fuse bits will have no effect until leaving programming mode.
The BOD circuit has three modes of operation:
Disabled: In this mode, there is no monitoring of the VCC level.
Enabled: In this mode, the VCC level is continuously monitored, and a drop in VCC below VBOT for a period of tBOD
will give a brownout reset
Sampled: In this mode, the BOD circuit will sample the VCC level with a period identical to that of the 1kHz output
from the ultra low power (ULP) internal oscillator. Between each sample, the BOD is turned off. This mode will
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reduce the power consumption compared to the enabled mode, but a fall in the VCC level between two positive
edges of the 1kHz ULP oscillator output will not be detected. If a brownout is detected in this mode, the BOD circuit
is set in enabled mode to ensure that the device is kept in reset until VCC is above VBOT again
The BODACT fuse determines the BOD setting for active mode and idle mode, while the BODPD fuse determines the
brownout detection setting for all sleep modes, except idle mode.
Table 9-3.
9.4.3
BOD setting fuse decoding.
BODACT[1:0]/ BODPD[1:0]
Mode
00
Reserved
01
Sampled
10
Enabled
11
Disabled
External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
Figure 9-5. External reset characteristics.
CC
tEXT
For external reset characterization data consult the device datasheet.
9.4.4
Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timout period, a watchdog reset will be given. The watchdog reset is active for one to
two clock cycles of the 2MHz internal oscillator.
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Figure 9-6. Watchdog reset.
CC
1-2 2MHz Cycles
For information on configuration and use of the WDT, refer to the “WDT – Watchdog Timer” on page 125.
9.4.5
Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
Figure 9-7. Software reset.
CC
1-2 2MHz Cycles
SOFTWARE
9.4.6
Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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9.5
Register Description
9.5.1
STATUS – Status register
9.5.2
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
SRF
PDIRF
WDRF
BORF
EXTRF
PORF
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
–
–
–
–
–
–
–
–
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5 – SRF: Software Reset Flag
This flag is set if a software reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 4 – PDIRF: Program and Debug Interface Reset Flag
This flag is set if a programming interface reset occurs. The flag will be cleared by a power-on reset or by writing a
one to the bit location.
Bit 3 – WDRF: Watchdog Reset Flag
This flag is set if a watchdog reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 2 – BORF: Brownout Reset Flag
This flag is set if a brownout reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 1 – EXTRF: External Reset Flag
This flag is set if an external reset occurs. The flag will be cleared by a power-on reset or by writing a one to the bit
location.
Bit 0 – PORF: Power On Reset Flag
This flag is set if a power-on reset occurs. Writing a one to the flag will clear the bit location.
CTRL – Control register
Bit
7
6
5
4
3
2
1
0
+0x01
–
–
–
–
–
–
–
SWRST
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – SWRST: Software Reset
When this bit is set, a software reset will occur. The bit is cleared when a reset is issued. This bit is protected by
the configuration change protection mechanism. For details, refer to “Configuration Change Protection” on page
13.
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9.6
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
bit 0
Page
+0x00
STATUS
–
–
SRF
PDIRF
WDRF
BORF
EXTRF
PORF
116
+0x01
CTRL
–
–
–
–
–
–
–
SWRST
116
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10.
Battery Backup System
10.1
Features
Integrated battery backup system ensuring continuos, real-time clock during main power failure
Battery backup power supply from dedicated VBAT pin to power:
One 32-bit real-time counter
One ultra low power 32.768kHz crystal oscillator with failure detection monitor
Two battery backup registers
Automatic power switching between main power and battery backup power:
10.2
Switching from main power to battery backup power at main power loss
Switching from battery backup power to main power at main power return
Overview
Many applications require a real-time clock that keeps running continuously, even in the event of a main power loss or
failure. The battery backup system includes functions for this through automatic power switching between main power
and a battery backup power supply. No external components are required. Figure 10-1 on page 119 shows an overview
of the system.
On devices with a battery backup system, a backup battery can be connected to the dedicated VBAT power pin. If the
main power is lost, the backup battery will continue and power the real-time counter (RTC32), a 32.768kHz crystal
oscillator with failure detection monitor, and two backup registers. The battery backup system does not provide power to
other parts of the volatile memory in the device, such as SRAM and I/O registers outside the system.
The device uses its BOD to detect main power loss and switch to power from the VBAT pin. After main power is restored,
the battery back system will automatically switch back to being powered from the main power again. The backup battery
is drained only when main power is not present, and this ensures maximum battery life.
On devices with the battery backup system, the RTC32 will keep running in all sleep modes.
10.3
Battery Backup System
The battery backup system consists of a VBAT power supervisor, a power switch, a crystal oscillator with failure monitor, a
32-bit real-time counter (RTC32), and two backup registers.
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Figure 10-1. Battery backup system and its power domain implementation.
VBAT
VBAT
power
supervisor
Power
switch
Watchdog w/
Ooscillator
Main
power
supervision
OCD &
Programming
Interface
Oscillator &
sleep
controller
VCC
XTAL1
XTAL2
TOSC1
Crystal
Oscillator
TOSC2
RTC32
Level shifters / Isolation
Failure
monitor
CPU
&
Peripherals
Internal
RAM
GPIO
FLASH,
EEPROM
& Fuses
Backup
Registers
10.3.1 Power Supervisor
The power supervisor monitors the voltage on the VBAT pin. It performs three main functions:
The power-on detection (BBPOD) function detects when power is applied to the VBAT pin, i.e., when the backup battery is
inserted. When this happens the battery backup power-on detection flag (BBPODF) is set and the power switch is
disconnected to prevent the backup battery from being drained before the device is configured.
The brown-out detection (BBBOD) function monitors the VBAT voltage level when the system is powered from the VBAT
pin. If the VBAT voltage drops below a threshold voltage, the battery backup bod flag (BBBODF) is set. The BBBOD
samples the VBAT voltage level at around a 1Hz rate, and is designed for detecting slow voltage changes. The BBBOD is
turned off when the device runs from the main power.
The power detection (BBPWR) function controls the VBAT voltage after a reset. If no voltage is present on the VBAT pin,
the battery backup power flag will be set. This indicates that the backup battery is not present or has been drained.
BBPODF, BBBODF, and the BBPWR flag are later referred to as the power supervision flags.
10.3.2 Power Switch
The power switch switches between main power and the VBAT pin to power the system. This happens automatically, and
is controlled from the main BOD in the device.
10.3.3 Crystal Oscillator with Failure Monitor
The crystal oscillator (XOSC) supports connection of a external 32.768kHz crystal. It provides a prescaled clock output
selectable to 1.024kHz or 1Hz. The crystal oscillator is designed for ultra low power consumption and by default is
configured for low ESR and load capacitance crystals. It is possible to enable a high ESR mode to drive crystals with high
ESR or load capacitance, but this will increase current consumption. The crystal oscillator failure monitor will detect if the
crystal is permanently or temporarily stopped and then set the crystal oscillator failure flag.
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10.3.4 32-bit Real-time Counter
The 32-bit real-time counter (RTC32) will count each clock output from the crystal oscillator. It provides a one-millisecond
or one-second resolution, depending on the crystal oscillator clock output selection. For more details on the 32-bit RTC,
refer to the “RTC32 – 32-bit Real-Time Counter” on page 219.
10.3.5 Backup Registers
The two backup registers can be used to store volatile data parameters when Vcc is not present.
10.4
Configuration
During device initialization, the battery backup system and RTC32 must be configured before they can be used. The
recommended configuration sequence is:
10.5
1.
Apply a reset
2.
Set the access enable bit
3.
Optionally configure the oscillator output and ESR selection
4.
Optionally enable the crystal oscillator failure monitor and the required delay before continuing configuration
5.
Enable the crystal oscillator
6.
Wait until the crystal oscillator ready flag is set
7.
Configure and enable the RTC32
Operation
The main BOD monitors the main voltage (Vcc) level and controls the power switching. This must always be enabled. In
active and idle modes, the BOD must be in continuos mode. In deep sleep modes, the BOD can be in continuos or
sampled mode. The system is designed as a power backup system for the RTC. Reset sources other than the BOD and
power loss (i.e. external reset, watchdog reset, and software reset) must be treated as a system reset. In this case, the
device state should be treated as unknown and lead to complete re-initialization, including battery backup system
configuration.
10.5.1 Main Power Loss
When Vcc drops below the programmed BOD threshold voltage, the device will:
1.
Switch the battery backup system to be powered from the VBAT pin and enable the BBBOD.
2.
Ignore any input signals to the system to prevent accidental or partial configuration.
3.
Stretch the 1Hz / 1.024kHz clock signal to avoid a clock edge when switching is active.
4.
Reset the part of the device not powered from the VBAT pin.
The battery backup system will continue to run as normal during the power switch and afterwards. When main power is
lost, it is not possible to access or read the status from the registers.
10.5.2 Main Power Restore and Start-up Sequence
At every startup after main power is restored, the software should:
1.
Control the main reset source to determine that a POR or BOD took place.
2.
Check for power on the VBAT pin by reading the BBPWR flag.
3.
Read the power supervisor flags to determine further software action:
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1.
If all power supervision flags are cleared, the battery backup system runs as normal. The software should
enable access to the battery backup system and check the crystal oscillator failure flag. If the flag is set, the
software should assume that the RTC32 counter value is invalid and take appropriate action.
2.
If any power supervision flags are set, it indicates the battery backup system has lost power sometime during the period when the rest of the device was unpowererd. Software should assume that the configuration
and RTC32 value are invalid and take appropriate action.
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10.6
Register Description
10.6.1 CTRL: Control register
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
HIGHESR
XOSCSEL
XOSCEN
XOSCFDEN
ACCEN
RESET
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
initial Value
0
0
0
0
0
0
0
0
Bit 7: 6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write this bit to
zero when this register is written.
Bit 5 – HIGHESR: High ESR Mode
Setting this bit will increase the current used to drive the crystal and increase the swing on the TOSC2 pin. This
allows use of crystals with higher load and higher ESR.
Bit 4 – XOSCSEL: Crystal Oscillator Output Selection
This bit selects the prescaled clock output from the 32.768kHz crystal oscillator. After reset, this bit is zero, and the
1Hz clock output is used as input for the RTC32. Setting this bit will select the 1.024kHz clock output as input for
the RTC32. This bit cannot be changed when XOSCEN is set.
Bit 3 – XOSCEN: Crystal Oscillator Enable
Setting this bit will enable the 32.768kHz crystal oscillator. Writing the bit to zero will have no effect, and the oscillator will remain enabled until a battery backup reset is issued. The Crystal oscillator can also be used as
32.768kHz system clock after performing step one to three described in “Configuration” on page 120.
Bit 2 – XOSCFDEN: Crystal Oscillator Failure Detection Enable
Setting this bit will enable the crystal oscillator monitor. The monitor will detect if the crystal is stopped or loses
connection temporarily. At least 64 swings must be lost before the failure detection is triggered. Writing the bit to
zero will have no effect, and the crystal oscillator monitor will remain enabled until a battery backup reset is issued.
Bit 1 – ACCEN: Module Access Enable
Setting this bit will enable access to the battery backup registers. After main reset, this bit must be set in order to
access (read from and write to) the battery backup registers, except for the BBPODF, the BBBODF, and the
BBPWR flags, which are always accessible. Writing this bit to zero will have no effect; only a device reset will clear
this bit.
Bit 0 – RESET: Reset
Setting this bit will force a reset of the battery backup system lasting one peripheral clock cycle. Writing the bit to
zero will have no effect. Writing a one to XOSCEN or XOSCFDEN at the same time will block writing to this bit.
When this bit is set, HIGHESR, XOSCSEL, XOSCEN, and XOSCFDEN in CTRL and XOSCRDY in STATUS will
be cleared.
This bit is protected by the Configuration Change Protection mechanism. For a detailed description, refer to “Configuration Change Protection” on page 13.
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10.6.2 STATUS: Status register
Bit
7
+0x01
6
5
4
3
2
1
0
BBPWR
–
–
–
XOSCRDY
XOSCFAIL
BBBODF
BBPODF
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
x
x
0
0
Bit 7 – BBPWR: Battery Backup Power
This flag is set if no power is detected on the VBAT pin when the device leaves reset. The flag can be cleared by
writing a one to this bit location.
Bit 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3 – XOSCRDY: Crystal Oscillator Ready
This flag is set when the 32.678kHz crystal oscillator has started and is stable and ready. The flag can be cleared
by applying a reset to the battery backup system. The actual start-up time is crystal dependent. Refer to the datasheet for the crystal oscillator used for more information.
Bit 2 – XOSCFAIL: Crystal Oscillator Failure
This flag is set if a crystal oscillator failure is detected. The flag can be cleared by writing a one to this bit location
or by applying a reset to the battery backup system.
Bit 1 – BBBODF: Battery Backup Brown-out Detection Flag
This flag is set if battery backup BOD is detected when the battery backup system is powered from the VBAT pin.
The flag can be cleared by writing a one to this bit location. This flag is not valid when BBPWR is set.
Bit 0 – BBPODF: Battery Backup Power-on Detection Flag
This flag is set if battery backup power-on is detected; i.e., when power is connected to the VBAT pin. The flag is
updated only during device startup when main power is applied. Applying or reapplying power to the VBAT pin while
main power is present will not change this flag until main power is removed and re-applied. The flag can be cleared
by writing a one to this bit location. This flag is not valid when BBPWR is set.
10.6.3 BACKUP0: Backup register 0
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
x
x
x
x
+0x02
3
2
1
0
R/W
R/W
R/W
R/W
x
x
x
x
BACKUP0[7:0]
Bit 7:0 – BACKUP0[7:0]: Backup Value 0
This register can be used to store data in the battery backup system before the main power is lost or removed.
10.6.4 BACKUP1: Backup register 1
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
x
x
x
x
+0x03
3
2
1
0
R/W
R/W
R/W
R/W
x
x
x
x
BACKUP1[7:0]
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10.7
Bit 7:0 – BACKUP1[7:0]: Backup Value 1
This register can be used to store data in the battery backup system before the main power is lost or removed.
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
CTRL
–
–
HIGHESR
XOSCSEL
XOSCEN
XOSCFDEN
ACCEN
RESET
122
+0x01
STATUS
BBPWR
–
–
–
XOSCRDY
OSCFAIL
BBBODF
BBPODF
122
+0x02
BACKUP0
BACKUP0[7:0]
123
+0x03
BACKUP1
BACKUP1[7:0]
123
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11.
WDT – Watchdog Timer
11.1
Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s.
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
11.2
Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
11.3
Normal Mode Operation
In normal mode operation, a single timeout period is set for the WDT. If the WDT is not reset from the application code
before the timeout occurs, then the WDT will issue a system reset. There are 11 possible WDT timeout (TOWDT) periods,
selectable from 8ms to 8s, and the WDT can be reset at any time during the timeout period. A new WDT timeout period
will be started each time the WDT is reset by the WDR instruction. The default timeout period is controlled by fuses.
Normal mode operation is illustrated in Figure 11-1 on page 125.
Figure 11-1. Normal mode operation.
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11.4
Window Mode Operation
In window mode operation, the WDT uses two different timeout periods, a "closed" window timeout period (TOWDTW) and
the normal timeout period (TOWDT). The closed window timeout period defines a duration of from 8ms to 8s where the
WDT cannot be reset. If the WDT is reset during this period, the WDT will issue a system reset. The normal WDT timeout
period, which is also 8ms to 8s, defines the duration of the "open" period during which the WDT can (and should) be
reset. The open period will always follow the closed period, and so the total duration of the timeout period is the sum of
the closed window and the open window timeout periods. The default closed window timeout period is controlled by fuses
(both open and closed periods are controlled by fuses). The window mode operation is illustrated in Figure 11-2.
Figure 11-2. Window mode operation.
11.5
Watchdog Timer Clock
The WDT is clocked from the 1kHz output from the 32kHz ultra low power (ULP) internal oscillator. Due to the ultra low
power design, the oscillator is not very accurate, and so the exact timeout period may vary from device to device. When
designing software which uses the WDT, this device-to-device variation must be kept in mind to ensure that the timeout
periods used are valid for all devices. For more information on ULP oscillator accuracy, consult the device datasheet.
11.6
Configuration Protection and Lock
The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings.
The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing
the WDT control registers. In addition, for the new configuration to be written to the control registers, the register’s
change enable bit must be written at the same time.
The second mechanism locks the configuration by setting the WDT lock fuse. When this fuse is set, the watchdog time
control register cannot be changed; hence, the WDT cannot be disabled from software. After system reset, the WDT will
resume at the configured operation. When the WDT lock fuse is programmed, the window mode timeout period cannot
be changed, but the window mode itself can still be enabled or disabled.
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11.7
Registers Description
11.7.1 CTRL – Control register
Bit
7
6
+0x00
–
–
5
4
3
Read/Write (unlocked)
R
R
R/W
R/W
R/W
Read/Write (locked)
R
R
R
R
R
Initial Value (x = fuse)
0
0
X
X
X
2
1
0
ENABLE
CEN
R/W
R/W
R/W
R
R
R
X
X
0
PER[3:0]
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bits 5:2 – PER[3:0]: Timeout Period
These bits determine the watchdog timeout period as a number of 1kHz ULP oscillator cycles. In window mode
operation, these bits define the open window period. The different typical timeout periods are found in Table 11-1.
The initial values of these bits are set by the watchdog timeout period (WDP) fuses, which are loaded at power-on.
In order to change these bits, the CEN bit must be written to 1 at the same time. These bits are protected by the
configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protection”
on page 13.
Table 11-1. Watchdog timeout periods.
Note:
PER[3:0]
Group configuration
Typical timeout periods
0000
8CLK
8ms
0001
16CLK
16ms
0010
32CLK
32ms
0011
64CLK
64ms
0100
128CLK
0.128s
0101
256CLK
0.256s
0110
512CLK
0.512s
0111
1KCLK
1.0s
1000
2KCLK
2.0s
1001
4KCLK
4.0s
1010
8KCLK
8.0s
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Reserved settings will not give any timeout.
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Bit 1 – ENABLE: Enable
This bit enables the WDT. Clearing this bit disables the watchdog timer.
In order to change this bit, the CEN bit in “CTRL – Control register” on page 127 must be written to one at the
same time. This bit is protected by the configuration change protection mechanism, For a detailed description,
refer to “Configuration Change Protection” on page 13.
Bit 0 – CEN: Change Enable
This bit enables the ability to change the configuration of the “CTRL – Control register” on page 127. When writing
a new value to this register, this bit must be written to one at the same time for the changes to take effect. This bit
is protected by the configuration change protection mechanism. For a detailed description, refer to “Configuration
Change Protection” on page 13.
11.7.2 WINCTRL – Window Mode Control register
Bit
7
6
+0x01
–
–
5
4
3
Read/Write (unlocked)
R
R
R/W
R/W
R/W
Read/Write (locked)
R
R
R
R
R
Initial Value (x = fuse)
0
0
X
X
X
2
1
0
WEN
WCEN
R/W
R/W
R/W
R
R/W
R/W
X
X
0
WPER[3:0]
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5:2 – WPER[3:0]: Window Mode Timeout Period
These bits determine the closed window period as a number of 1kHz ULP oscillator cycles in window mode operation. The typical different closed window periods are found in Table 11-2. The initial values of these bits are set by
the watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are
not in use.
In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by
the configuration change protection mechanism. For a detailed description, refer to “Configuration Change Protection” on page 13.
Table 11-2. Watchdog closed window periods.
WPER[3:0]
Group configuration
Typical closed window periods
0000
8CLK
8ms
0001
16CLK
16ms
0010
32CLK
32ms
0011
64CLK
64ms
0100
128CLK
0.128s
0101
256CLK
0.256s
0110
512CLK
0.512s
0111
1KCLK
1.0s
1000
2KCLK
2.0s
1001
4KCLK
4.0s
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WPER[3:0]
Group configuration
Typical closed window periods
1010
8KCLK
8.0s
Note:
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Reserved settings will not give any timeout for the window.
Bit 1 – WEN: Window Mode Enable
This bit enables the window mode. In order to change this bit, the WCEN bit in “WINCTRL – Window Mode Control
register” on page 128 must be written to one at the same time. This bit is protected by the configuration change
protection mechanism. For a detailed description, refer to “Configuration Change Protection” on page 13.
Bit 0 – WCEN: Window Mode Change Enable
This bit enables the ability to change the configuration of the “WINCTRL – Window Mode Control register” on page
128. When writing a new value to this register, this bit must be written to one at the same time for the changes to
take effect. This bit is protected by the configuration change protection mechanism, but not protected by the WDT
lock fuse.
11.7.3 STATUS – Status register
Bit
7
6
5
4
3
2
1
0
+0x02
–
–
–
–
–
–
–
SYNCBUSY
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set after writing to the CTRL or WINCTRL registers and the data are being synchronized from the system clock to the WDT clock domain. This bit is automatically cleared after the synchronization is finished.
Synchronization will take place only when the ENABLE bit for the Watchdog Timer is set.
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11.8
Register summary
Address
Name
Bit 7
Bit 6
+0x00
CTRL
–
–
+0x01
WINCTRL
–
–
+0x02
STATUS
–
–
Bit 5
–
Bit 4
–
Bit 3
Bit 1
Bit 0
Page
PER[3:0]
ENABLE
CEN
127
WPER[3:0]
WEN
WCEN
128
–
SYNCBUSY
129
–
Bit 2
–
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12.
Interrupts and Programmable Multilevel Interrupt Controller
12.1
Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
12.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
12.3
Operation
Interrupts must be globally enabled for any interrupts to be generated. This is done by setting the global interrupt enable
( I ) bit in the CPU status register. The I bit will not be cleared when an interrupt is acknowledged. Each interrupt level
must also be enabled before interrupts with the corresponding level can be generated.
When an interrupt is enabled and the interrupt condition is present, the PMIC will receive the interrupt request. Based on
the interrupt level and interrupt priority of any ongoing interrupts, the interrupt is either acknowledged or kept pending
until it has priority. When the interrupt request is acknowledged, the program counter is updated to point to the interrupt
vector. The interrupt vector is normally a jump to the interrupt handler; the software routine that handles the interrupt.
After returning from the interrupt handler, program execution continues from where it was before the interrupt occurred.
One instruction is always executed before any pending interrupt is served.
The PMIC status register contains state information that ensures that the PMIC returns to the correct interrupt level when
the RETI (interrupt return) instruction is executed at the end of an interrupt handler. Returning from an interrupt will return
the PMIC to the state it had before entering the interrupt. The status register (SREG) is not saved automatically upon an
interrupt request. The RET (subroutine return) instruction cannot be used when returning from the interrupt handler
routine, as this will not return the PMIC to its correct state.
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Figure 12-1. Interrupt controller overview
Interrupt Controller
Priority
decoder
INT LEVEL
Peripheral 1
INT REQ
INT ACK
CPU ”RETI”
CPU INT ACK
INT LEVEL
Peripheral
n
INT REQ
INT ACK
CPU
INT LEVEL
CPU INT REQ
INT REQ
INT ACK
LEVEL Enable
CTRL
12.4
STATUS
INTPRI
Global
Interrupt
Enable
CPU.SREG
Wake-up
Sleep
Controller
Interrupts
All interrupts and the reset vector each have a separate program vector address in the program memory space. The
lowest address in the program memory space is the reset vector. All interrupts are assigned individual control bits for
enabling and setting the interrupt level, and this is set in the control registers for each peripheral that can generate
interrupts. Details on each interrupt are described in the peripheral where the interrupt is available.
All interrupts have an interrupt flag associated with it. When the interrupt condition is present, the interrupt flag will be set,
even if the corresponding interrupt is not enabled. For most interrupts, the interrupt flag is automatically cleared when
executing the interrupt vector. Writing a logical one to the interrupt flag will also clear the flag. Some interrupt flags are
not cleared when executing the interrupt vector, and some are cleared automatically when an associated register is
accessed (read or written). This is described for each individual interrupt flag.
If an interrupt condition occurs while another, higher priority interrupt is executing or pending, the interrupt flag will be set
and remembered until the interrupt has priority. If an interrupt condition occurs while the corresponding interrupt is not
enabled, the interrupt flag will be set and remembered until the interrupt is enabled or the flag is cleared by software.
Similarly, if one or more interrupt conditions occur while global interrupts are disabled, the corresponding interrupt flag
will be set and remembered until global interrupts are enabled. All pending interrupts are then executed according to their
order of priority.
Interrupts can be blocked when executing code from a locked section; e.g., when the boot lock bits are programmed.
This feature improves software security. Refer to “Memory Programming” on page 407 for details on lock bit settings.
Interrupts are automatically disabled for up to four CPU clock cycles when the configuration change protection register is
written with the correct signature. Refer to “Configuration Change Protection” on page 13 for more details.
12.4.1 NMI – Non-Maskable Interrupts
Which interrupts represent NMI and which represent regular interrupts cannot be selected. Non-maskable interrupts
must be enabled before they can be used. Refer to the device datasheet for NMI present on each device.
An NMI will be executed regardless of the setting of the I bit, and it will never change the I bit. No other interrupts can
interrupt a NMI handler. If more than one NMI is requested at the same time, priority is static according to the interrupt
vector address, where the lowest address has highest priority.
12.4.2 Interrupt Response Time
The interrupt response time for all the enabled interrupts is three CPU clock cycles, minimum; one cycle to finish the
ongoing instruction and two cycles to store the program counter to the stack. After the program counter is pushed on the
stack, the program vector for the interrupt is executed. The jump to the interrupt handler takes three clock cycles.
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If an interrupt occurs during execution of a multicycle instruction, this instruction is completed before the interrupt is
served. See Figure 12-2 on page 133 for more details.
Figure 12-2. Interrupt execution of a multi cycle instruction.
If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock
cycles. In addition, the response time is increased by the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the program counter.
During these clock cycles, the program counter is popped from the stack and the stack pointer is incremented.
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12.5
Interrupt level
The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives
the interrupt level for the interrupt. The interrupt levels and their corresponding bit values for the interrupt level
configuration of all interrupts is shown in Table 12-1.
Table 12-1. Interrupt levels.
Interrupt level configuration
Group configuration
Description
00
OFF
Interrupt disabled.
01
LO
Low-level interrupt
10
MED
11
HI
Medium-level interrupt
High-level interrupt
The interrupt level of an interrupt request is compared against the current level and status of the interrupt controller. An
interrupt request of a higher level will interrupt any ongoing interrupt handler from a lower level interrupt. When returning
from the higher level interrupt handler, the execution of the lower level interrupt handler will continue.
12.6
Interrupt priority
Within each interrupt level, all interrupts have a priority. When several interrupt requests are pending, the order in which
interrupts are acknowledged is decided both by the level and the priority of the interrupt request. Interrupts can be
organized in a static or dynamic (round-robin) priority scheme. High- and medium-level interrupts and the NMI will always
have static priority. For low-level interrupts, static or dynamic priority scheduling can be selected.
12.6.1 Static priority
Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector address decides the priority
within one interrupt level, where the lowest interrupt vector address has the highest priority. Refer to the device datasheet
for the interrupt vector table with the base address for all modules and peripherals with interrupt capability. Refer to the
interrupt vector summary of each module and peripheral in this manual for a list of interrupts and their corresponding
offset address within the different modules and peripherals.
Figure 12-3. Static priority.
Lowes t Addres s
IVEC 0
Highes t Priority
:
:
:
IVEC x
IVEC x+1
:
:
:
Highes t Addres s
IVEC N
Lowes t Priority
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12.6.2 Round-robin Scheduling
To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be
served, the PMIC offers round-robin scheduling for low-level interrupts. When round-robin scheduling is enabled, the
interrupt vector address for the last acknowledged low-level interrupt will have the lowest priority the next time one or
more interrupts from the low level is requested.
Figure 12-4. Round-robin scheduling.
IV EC x las t ack now le dge d
inte rrupt
IV EC 0
IV EC 0
:
:
:
:
:
:
IV EC x
Low est Priority
IV EC x
IV EC x+1
Highest Priority
IV EC x+1
Low est Priority
IV EC x+2
Highest Priority
:
:
:
IV EC N
12.7
IV EC x+1 las t ack now le dge d
inte rrupt
:
:
:
IV EC N
Interrupt vector locations
Table 12-2 on page 135 shows reset and Interrupt vectors placement for the various combinations of BOOTRST and
IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program
code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the
Interrupt Vectors are in the Boot section or vice versa.
Table 12-2. Reset and interrupt vectors placement.
BOOTRST
IVSEL
Reset address
Interrupt vectors start address
1
0
0x0000
0x0002
1
1
0x0000
Boot Reset Address + 0x0002
0
0
Boot Reset Address
0x0002
0
1
Boot Reset Address
Boot Reset Address + 0x0002
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12.8
Register description
12.8.1 STATUS – Status register
Bit
7
6
5
4
3
2
1
0
NMIEX
–
–
–
–
HILVLEX
MEDLVLEX
LOLVLEX
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
+0x00
Bit 7 – NMIEX: Non-Maskable Interrupt Executing
This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the
interrupt handler.
Bit 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – HILVLEX: High-level Interrupt Executing
This flag is set when a high-level interrupt is executing or when the interrupt handler has been interrupted by an
NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
Bit 1 – MEDLVLEX: Medium-level Interrupt Executing
This flag is set when a medium-level interrupt is executing or when the interrupt handler has been interrupted by
an interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
Bit 0 – LOLVLEX: Low-level Interrupt Executing
This flag is set when a low-level interrupt is executing or when the interrupt handler has been interrupted by an
interrupt from higher level or an NMI. The flag will be cleared when returning (RETI) from the interrupt handler.
12.8.2 INTPRI – Interrupt priority register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x01
INTPRI[7:0]
Bit 7:0 – INTPRI: Interrupt Priority
When round-robin scheduling is enabled, this register stores the interrupt vector of the last acknowledged lowlevel interrupt. The stored interrupt vector will have the lowest priority the next time one or more low-level interrupts
are pending. The register is accessible from software to change the priority queue. This register is not reinitialized
to its initial value if round-robing scheduling is disabled, and so if default static priority is needed, the register must
be written to zero.
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12.8.3 CTRL – Control register
Bit
+0x02
7
6
5
4
3
2
1
0
RREN
IVSEL
–
–
–
HILVLEN
MEDLVLEN
LOLVLEN
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7 – RREN: Round-robin Scheduling Enable
When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts. When this bit is
cleared, the priority is static according to interrupt vector address, where the lowest address has the highest
priority.
Bit 6 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the application section in flash.
When this bit is set (one), the interrupt vectors are placed in the beginning of the boot section of the flash. Refer to
the device datasheet for the absolute address.
This bit is protected by the configuration change protection mechanism. Refer to “Configuration Change Protection” on page 13 for details.
Bit 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – HILVLEN: High-level Interrupt Enable(1)
When this bit is set, all high-level interrupts are enabled. If this bit is cleared, high-level interrupt requests will be
ignored.
Bit 1 – MEDLVLEN: Medium-level Interrupt Enable(1)
When this bit is set, all medium-level interrupts are enabled. If this bit is cleared, medium-level interrupt requests
will be ignored.
Bit 0 – LOLVLEN: Low-level Interrupt Enable(1)
When this bit is set, all low-level interrupts are enabled. If this bit is cleared, low-level interrupt requests will be
ignored.
Note:
1.
Ignoring interrupts will be effective one cycle after the bit is cleared.
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12.9
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
STATUS
NMIEX
–
–
–
–
HILVLEX
MEDLVLEX
LOLVLEX
136
+0x01
INTPRI
+0x02
CTRL
INTPRI[7:0]
RREN
IVSEL
–
–
–
136
HILVLEN
MEDLVLEN
LOLVLEN
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138
13.
I/O Ports
13.1
Features
General purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
Optional slew rate control
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
13.2
Selectable USART, SPI, and timer/counter input/output pin locations
Overview
AVR XMEGA microcontrollers have flexible general purpose I/O ports. One port consists of up to eight port pins: pin 0 to
7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement
synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the
modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
Figure 13-1 on page 140 shows the I/O pin functionality and the registers that are available for controlling a pin.
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Figure 13-1. General I/O pin functionality.
Pull Enable
C
o
n
t
r
o
l
PINnCTRL
Q
D
R
L
o
g
i
c
Pull Keep
Pull Direction
Input Disable
Wired AND/OR
Slew Rate Limit
Inverted I/O
OUTn
Pxn
Q
D
R
DIRn
Q
D
R
Synchronizer
INn
Q
D
R
Q
D
R
Digital Input Pin
Analog Input/Output
13.3
I/O Pin Use and Configuration
Each port has one data direction (DIR) register and one data output value (OUT) register that are used for port pin
control. The data input value (IN) register is used for reading the port pins. In addition, each pin has a pin configuration
(PINnCTRL) register for additional pin configuration.
Direction of the pin is decided by the DIRn bit in the DIR register. If DIRn is written to one, pin n is configured as an output
pin. If DIRn is written to zero, pin n is configured as an input pin.
When direction is set as output, the OUTn bit in OUT is used to set the value of the pin. If OUTn is written to one, pin n is
driven high. If OUTn is written to zero, pin n is driven low.
The IN register is used for reading pin values. A pin value can always be read regardless of whether the pin is configured
as input or output, except if digital input is disabled.
The I/O pins are tri-stated when a reset condition becomes active, even if no clocks are running.
The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole,
wired-AND, or wired-OR configuration. It is also possible to enable inverted input and output for a pin.
A totem-pole output has four possible pull configurations: totem-pole (push-pull), pull-down, pull-up, and bus-keeper. The
bus-keeper is active in both directions. This is to avoid oscillation when disabling the output. The totem-pole
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configurations with pull-up and pull-down have active resistors only when the pin is set as input. This feature eliminates
unnecessary power consumption. For wired-AND and wired-OR configuration, the optional pull-up and pull-down
resistors are active in both input and output directions.
Since pull configuration is configured through the pin configuration register, all intermediate port states during switching
of the pin direction and pin values are avoided.
The I/O pin configurations are summarized with simplified schematics in Figure 13-2 on page 141 to Figure 13-7 on page
143.
13.3.1 Totem-pole
In the totem-pole (push-pull) configuration, the pin is driven low or high according to the corresponding bit setting in the
OUT register. In this configuration, there is no current limitation for sink or source other than what the pin is capable of. If
the pin is configured for input, the pin will float if no external pull resistor is connected.
Figure 13-2. I/O pin configuration - Totem-pole (push-pull).
DIRn
OUTn
Pn
INn
13.3.1.1 Totem-pole with Pull-down
In this mode, the configuration is the same as for totem-pole mode, expect the pin is configured with an internal pull-down
resistor when set as input.
Figure 13-3. I/O pin configuration - Totem-pole with pull-down (on input).
DIRn
OUTn
Pn
INn
13.3.1.2 Totem-pole with Pull-up
In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pull-up when set as input.
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Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input).
DIRn
OUTn
Pn
INn
13.3.2 Bus-keeper
In the bus-keeper configuration, it provides a weak bus-keeper that will keep the pin at its logic level when the pin is no
longer driven to high or low. If the last level on the pin/bus was 1, the bus-keeper configuration will use the internal pull
resistor to keep the bus high. If the last logic level on the pin/bus was 0, the bus-keeper will use the internal pull resistor
to keep the bus low.
Figure 13-5. I/O pin configuration - Totem-pole with bus-keeper.
DIRn
OUTn
Pn
INn
13.3.3 Wired-OR
In the wired-OR configuration, the pin will be driven high when the corresponding bits in the OUT and DIR registers are
written to one. When the OUT register is set to zero, the pin is released, allowing the pin to be pulled low with the internal
or an external pull-resistor. If internal pull-down is used, this is also active if the pin is set as input.
Figure 13-6. Output configuration - Wired-OR with optional pull-down.
OUTn
Pn
INn
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13.3.4 Wired-AND
In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are
written to zero. When the OUT register is set to one, the pin is released allowing the pin to be pulled high with the internal
or an external pull-resistor. If internal pull-up is used, this is also active if the pin is set as input.
Figure 13-7. Output configuration - Wired-AND with optional pull-up.
INn
Pn
OUTn
13.4
Reading the Pin Value
Independent of the pin data direction, the pin value can be read from the IN register, as shown in Figure 13-1 on page
140. If the digital input is disabled, the pin value cannot be read. The IN register bit and the preceding flip-flop constitute
a synchronizer. The synchronizer introduces a delay on the internal signal line. Figure 13-8 on page 143 shows a timing
diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation
delays are denoted as tpd,max and tpd,min, respectively.
Figure 13-8. Synchronization when reading a pin value.
PERIPHERAL CLK
INSTRUCTIONS
xxx
xxx
lds r17, PORTx+IN
SYNCHRONIZER FLIPFLOP
IN
r17
0x00
0xFF
tpd, max
tpd, min
13.5
Input Sense Configuration
Input sensing is used to detect an edge or level on the I/O pin input. The different sense configurations that are available
for each pin are detection of a rising edge, falling edge, or any edge or detection of a low level. High level can be
detected by using the inverted input configuration. Input sensing can be used to trigger interrupt requests (IREQ) or
events when there is a change on the pin.
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The I/O pins support synchronous and asynchronous input sensing. Synchronous sensing requires the presence of the
peripheral clock, while asynchronous sensing does not require any clock.
Figure 13-9. Input sensing.
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IRQ
Synchronous sensing
Pxn
Synchronizer
INn
Q D
D
R
Q
EDGE
DETECT
Synchronous
Events
R
INVERTED I/O
Asynchronous
Events
13.6
Port Interrupt
Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts
must be enabled before they can be used. Which sense configurations can be used to generate interrupts is dependent
on whether synchronous or asynchronous input sensing is available for the selected pin.
For synchronous sensing, all sense configurations can be used to generate interrupts. For edge detection, the changed
pin value must be sampled once by the peripheral clock for an interrupt request to be generated.
For asynchronous sensing, only port pin 2 on each port has full asynchronous sense support. This means that for edge
detection, pin 2 will detect and latch any edge and it will always trigger an interrupt request. The other port pins have
limited asynchronous sense support. This means that for edge detection, the changed value must be held until the device
wakes up and a clock is present. If the pin value returns to its initial value before the end of the device wake-up time, the
device will still wake up, but no interrupt request will be generated.
A low level can always be detected by all pins, regardless of a peripheral clock being present or not. If a pin is configured
for low-level sensing, the interrupt will trigger as long as the pin is held low. In active mode, the low level must be held
until the completion of the currently executing instruction for an interrupt to be generated. In all sleep modes, the low level
must be kept until the end of the device wake-up time for an interrupt to be generated. If the low level disappears before
the end of the wake-up time, the device will still wake up, but no interrupt will be generated.
Table 13-1, Table 13-2, and Table 13-3 on page 145 summarize when interrupts can be triggered for the various input
sense configurations.
Table 13-1. Synchronous sense support.
Sense settings
Supported
Interrupt description
Rising edge
Yes
Always triggered
Falling edge
Yes
Always triggered
Any edge
Yes
Always triggered
Low level
Yes
Pin level must be kept unchanged during wake up
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Table 13-2. Full asynchronous sense support.
Sense settings
Supported
Interrupt description
Rising edge
Yes
Always triggered
Falling edge
Yes
Always triggered
Both edges
Yes
Always triggered
Low level
Yes
Pin level must be kept unchanged during wake up
Table 13-3. Limited asynchronous sense support.
Sense settings
13.7
Supported
Interrupt description
Rising edge
No
-
Falling edge
No
-
Any edge
Yes
Pin value must be kept unchanged during wake up
Low level
Yes
Pin level must be kept unchanged during wake up
Port Event
Port pins can generate an event when there is a change on the pin. The sense configurations decide the conditions for
each pin to generate events. Event generation requires the presence of a peripheral clock, and asynchronous event
generation is not possible. For edge sensing, the changed pin value must be sampled once by the peripheral clock for an
event to be generated.
For level sensing, a low-level pin value will not generate events, and a high-level pin value will continuously generate
events. For events to be generated on a low level, the pin configuration must be set to inverted I/O.
Table 13-4. Event sense support.
Sense settings
13.8
Signal event
Data event
Rising edge
Rising edge
Pin value
Falling edge
Falling edge
Pin value
Both edge
Any edge
Pin value
Low level
Pin value
Pin value
Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral.
The port override signals and related logic (grey) are shown in Figure 13-10 on page 146. These signals are not
accessible from software, but are internal signals between the overriding peripheral and the port pin.
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Figure 13-10. Port override signals and related logic.
Pull Enable
PINnCTRL
Q
D
C
o
n
t
r
o
l
Pull Keep
L
o
g
i
c
Digital Input Disable (DID)
Pull Direction
R
DID Override Value
DID Override Enable
Wired AND/OR
Slew Rate Limit
Inverted I/O
OUTn
Pxn
Q
D
OUT Override Value
R
OUT Override Enable
DIRn
Q
D
DIR Override Value
R
DIR Override Enable
Synchronizer
INn
Q
D
R
Q
D
R
Digital Input Pin
Analog Input/Output
13.9
Slew Rate Control
Slew rate control can be enabled for all I/O pins individually. Enabling the slew rate limiter will typically increase the
rise/fall time by 50% to 150%, depending on operating conditions and load. For information about the characteristics of
the slew rate limiter, please refer to the device datasheet.
13.10 Clock and Event Output
It is possible to output the peripheral clock and any of the event channels to the port pins (using EVCTRL register). This
can be used to clock, control, and synchronize external functions and hardware to internal device timing. The output port
pin is selectable. If an event occurs, it remains visible on the port pin as long as the event lasts; normally one peripheral
clock cycle.
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13.11 Multi-pin configuration
The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the
port pin configuration registers. A mask register decides which port pin is configured when one port pin register is written,
while avoiding several pins being written the same way during identical write operations.
13.12 Virtual Ports
Virtual port registers allow the port registers to be mapped virtually in the bit-accessible I/O memory space. When this is
done, writing to the virtual port register will be the same as writing to the real port register. This enables the use of I/O
memory-specific instructions, such as bit-manipulation instructions, on a port register that normally resides in the
extended I/O memory space. There are four virtual ports, and so four ports can be mapped at the same time.
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13.13 Register Descriptions – Ports
13.13.1 DIR – Data Direction register
Bit
7
6
5
4
+0x00
3
2
1
0
DIR[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DIR[7:0]: Data Direction
This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured
as an output pin. If DIRn is written to zero, pin n is configured as an input pin.
13.13.2 DIRSET – Data Direction Set register
Bit
7
6
5
4
+0x01
3
2
1
0
DIRSET[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DIRSET[7:0]: Port Data Direction Set
This register can be used instead of a read-modify-write to set individual pins as output. Writing a one to a bit will
set the corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
13.13.3 DIRCLR – Data Direction Clear register
Bit
7
6
5
4
+0x02
3
2
1
0
DIRCLR[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DIRCLR[7:0]: Port Data Direction Clear
This register can be used instead of a read-modify-write to set individual pins as input. Writing a one to a bit will
clear the corresponding bit in the DIR register. Reading this register will return the value of the DIR register.
13.13.4 DIRTGL – Data Direction Toggle register
Bit
7
6
5
4
+0x03
3
2
1
0
DIRTGL[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle
This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a
bit will toggle the corresponding bit in the DIR register. Reading this register will return the value of the DIR
register.
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13.13.5 OUT – Data Output Value register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x04
OUT[7:0]
Bit 7:0 – OUT[7:0]: Port Data Output value
This register sets the data output value for the individual pins of the port. If OUTn is written to one, pin n is driven
high. If OUTn is written to zero, pin n is driven low. For this setting to have any effect, the pin direction must be set
as output.
13.13.6 OUTSET – Data Output Value Set register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x05
OUTSET[7:0]
Bit 7:0 – OUTSET[7:0]: Data Output Value Set
This register can be used instead of a read-modify-write to set the output value of individual pins to one. Writing a
one to a bit will set the corresponding bit in the OUT register. Reading this register will return the value in the OUT
register.
13.13.7 OUTCLR – Data Output Value Clear Register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x06
OUTCLR[7:0]
Bit 7:0 – OUTCLR[7:0]: Data Output Value Clear
This register can be used instead of a read-modify-write to set the output value of individual pins to zero. Writing a
one to a bit will clear the corresponding bit in the OUT register. Reading this register will return the value in the
OUT register.
13.13.8 OUTTGL – Data Output Value Toggle register
Bit
7
6
5
4
+0x07
3
2
1
0
OUTTGL[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle
This register can be used instead of a read-modify-write to toggle the output value of individual pins. Writing a one
to a bit will toggle the corresponding bit in the OUT register. Reading this register will return the value in the OUT
register.
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13.13.9 IN – Data Input Value register
Bit
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
+0x08
IN[7:0]
Bit 7:0 – IN[7:0]: Data Input Value
This register shows the value present on the pins if the digital input driver is enabled. INn shows the value of pin n
of the port. The input is not sampled and cannot be read if the digital input buffers are disabled.
13.13.10 INTCTRL – Interrupt Control register
Bit
7
6
5
4
3
2
1
0
+0x09
–
–
–
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
INT1LVL[1:0]
INT0LVL[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2/1:0 – INTnLVL[1:0]: Interrupt n Level
These bits enable port interrupt n and select the interrupt level as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131.
13.13.11 INT0MASK – Interrupt 0 Mask register
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
+0x0A
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
INT0MSK[7:0]
Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Bits
These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to
one, pin n is used as source for port interrupt 0.The input sense configuration for each pin is decided by the
PINnCTRL registers.
13.13.12 INT1MASK – Interrupt 1 Mask register
Bit
7
6
5
+0x0B
4
3
2
1
0
INT1MSK[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – INT1MASK[7:0]: Interrupt 1 Mask Bits
These bits are used to mask which pins can be used as sources for port interrupt 1. If INT1MASKn is written to
one, pin n is used as source for port interrupt 1.The input sense configuration for each pin is decided by the
PINnCTRL registers.
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13.13.13 INTFLAGS – Interrupt Flag register
Bit
7
6
5
4
3
2
1
0
+0x0C
–
–
–
–
–
–
INT1IF
INT0IF
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1:0 – INTnIF: Interrupt n Flag
The INTnIF flag is set when a pin change/state matches the pin's input sense configuration, and the pin is set as
source for port interrupt n. Writing a one to this flag's bit location will clear the flag. For enabling and executing the
interrupt, refer to the interrupt level description.
13.13.14 REMAP – Pin Remap register
The pin remap functionality is available for PORTC - PORTF only.
Bit
7
6
5
4
3
2
1
0
+0x0E
–
–
SPI
USART0
TC0D
TC0C
TC0B
TC0A
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5 – SPI: SPI Remap
Setting this bit to one will swap the pin locations of the SCK and MOSI pins to have pin compatibility between SPI
and USART when the USART is operating as a SPI master.
Bit 4 – USART0: USART0 Remap
Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4].
Bit 3 – TC0D: Timer/Counter 0 Output Compare D
Setting this bit will move the location of OC0D from Px3 to Px7.
Bit 2 – TC0C: Timer/Counter 0 Output Compare C
Setting this bit will move the location of OC0C from Px2 to Px6.
Bit 1 – TC0B: Timer/Counter 0 Output Compare B
Setting this bit will move the location of OC0B from Px1 to Px5. If this bit is set and PWM from both timer/counter 0
and timer/counter 1 is enabled, the resulting PWM will be an OR-modulation between the two PWM outputs.
Bit 0 – TC0A: Timer/Counter 0 Output Compare A
Setting this bit will move the location of OC0A from Px0 to Px4. If this bit is set and PWM from both timer/counter 0
and timer/counter 1 is enabled, the resulting PWM will be an OR-modulation between the two PWM outputs. See
Figure 13-11.
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Figure 13-11.I/O timer/counter.
OC4A
OC5A
OCA
13.13.15 PINnCTRL – Pin n Configuration register
Bit
7
6
SRLEN
INVEN
5
4
3
2
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
OPC[2:0]
0
ISC[2:0]
Bit 7 – SRLEN: Slew Rate Limit Enable
Setting this bit will enable slew rate limiting on pin n.
Bit 6 – INVEN: Inverted I/O Enable
Setting this bit will enable inverted output and input data on pin n.
Bit 5:3 – OPC: Output and Pull Configuration
These bits set the output/pull configuration on pin n according to Table 13-5 on page 152.
Table 13-5. Output/pull configuration.
Description
OPC[2:0]
Group configuration
Output configuration
Pull configuration
000
TOTEM
Totem-pole
(N/A)
001
BUSKEEPER
Totem-pole
Bus-keeper
010
PULLDOWN
Totem-pole
Pull-down (on input)
011
PULLUP
Totem-pole
Pull-up (on input)
100
WIREDOR
Wired-OR
(N/A)
101
WIREDAND
Wired-AND
(N/A)
110
WIREDORPULL
Wired-OR
Pull-down
111
WIREDANDPULL
Wired-AND
Pull-up
Bit 2:0 – ISC[2:0]: Input/Sense Configuration
These bits set the input and sense configuration on pin n according to Table 13-6. The sense configuration
decides how the pin can trigger port interrupts and events. If the input buffer is disabled, the input cannot be read
in the IN register.
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Table 13-6. Input/sense configuration.
ISC[2:0]
Group configuration
Description
000
BOTHEDGES
Sense both edges
001
RISING
Sense rising edge
010
FALLING
Sense falling edge
011
LEVEL
Sense low level(1)
100
Reserved
101
Reserved
110
Reserved
111
Notes:
1.
2.
Digital input buffer disabled(2)
INTPUT_DISABLE
A low-level pin value will not generate events, and a high-level pin value will continuously generate events.
Only PORTA - PORTF support the input buffer disable option. If the pin is used for analog functionality, such as AC or ADC, it is recommended to
configure the pin to INPUT_DISABLE.
13.14 Register Descriptions – Port Configuration
13.14.1 MPCMASK – Multi-pin Configuration Mask register
Bit
7
6
5
+0x00
4
3
2
1
0
MPCMASK[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask
The MPCMASK register enables configuration of several pins of a port at the same time. Writing a one to bit n
makes pin n part of the multi-pin configuration. When one or more bits in the MPCMASK register is set, writing any
of the PINnCTRL registers will update only the PINnCTRL registers matching the mask in the MPCMASK register
for that port. The MPCMASK register is automatically cleared after any PINnCTRL register is written.
13.14.2 VPCTRLA – Virtual Port-map Control register A
Bit
7
6
+0x02
5
4
3
2
VP1MAP[3:0]
1
0
VP0MAP[3:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – VP1MAP: Virtual Port 1 Mapping
These bits decide which ports should be mapped to Virtual Port 1. The registers DIR, OUT, IN, and INTFLAGS will
be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 13-7 on
page 154 for configuration.
Bit 3:0 – VP0MAP: Virtual Port 0 Mapping
These bits decide which ports should be mapped to Virtual Port 0. The registers DIR, OUT, IN, and INTFLAGS will
be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 13-7 on
page 154 for configuration.
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13.14.3 VPCTRLB – Virtual Port-map Control register B
Bit
7
6
5
4
3
2
Read/Write
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
+0x03
1
0
R/W
R/W
R/W
0
0
0
VP3MAP[3:0]
VP2MAP[3:0]
Bit 7:4 – VP3MAP: Virtual Port 3 Mapping
These bits decide which ports should be mapped to Virtual Port 3. The registers DIR, OUT, IN, and INTFLAGS will
be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 13-7 on
page 154 for configuration.
Bit 3:0 – VP2MAP: Virtual Port 2 Mapping
These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will
be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 13-7 on
page 154 for configuration.
Table 13-7. Virtual port mapping.
VPnMAP[3:0]
Group configuration
Description
0000
PORTA
PORTA mapped to Virtual Port n
0001
PORTB
PORTB mapped to Virtual Port n
0010
PORTC
PORTC mapped to Virtual Port n
0011
PORTD
PORTD mapped to Virtual Port n
0100
PORTE
PORTE mapped to Virtual Port n
0101
PORTF
PORTF mapped to Virtual Port n
0110
PORTG
PORTG mapped to Virtual Port n
0111
PORTH
PORTH mapped to Virtual Port n
1000
PORTJ
PORTJ mapped to Virtual Port n
1001
PORTK
PORTK mapped to Virtual Port n
1010
PORTL
PORTL mapped to Virtual Port n
1011
PORTM
PORTM mapped to Virtual Port n
1100
PORTN
PORTN mapped to Virtual Port n
1101
PORTP
PORTP mapped to Virtual Port n
1110
PORTQ
PORTQ mapped to Virtual Port n
1111
PORTR
PORTR mapped to Virtual Port n
13.14.4 CLKEVOUT – Clock and Event Out register
Bit
7
6
CLKEVPIN
RTCOUT
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x04
5
4
EVOUT[1:0]
3
2
CLKOUTSEL[1:0]
1
0
CLKOUT[1:0]
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Bit 7 – CLKEVPIN: Clock and Event Output Pin Select
Setting this pin enables output of clock and event pins on port pin 4 instead of port pin 7.
Bit 6 – RTCOUT: RTC Clock Output Enable
Setting this bit enables output of the RTC clock source on PORTC pin 6.
Bit 5:4 – EVOUT[1:0]: Event Output Port
These bits decide which port event channel 0 from the event system will be output to. Pin 7 on the selected port is
the default used, and the CLKOUT bits must be set differently from those of EVOUT. The port pin must be configured as output for the event to be available on the pin.
Table 13-8 on page 155 shows the possible configurations.
Table 13-8. Event output pin selection.
EVOUT[1:0]
Group configuration
Description
00
OFF
Event output disabled
01
PC
Event channel 0 output on PORTC
10
PD
Event channel 0 output on PORTD
11
PE
Event channel 0 output on PORTE
Bits 3:2 – CLKOUTSEL[1:0]: Clock Output Select
These bits are used to select which of the peripheral clocks will be output to the port pin if CLKOUT is configured.
Table 13-9. Event output clock selection.
CLKOUTSEL[1:0]
Group configuration
Description
00
CLK1X
CLKPER output to pin
01
CLK2X
CLKPER2 output to pin
10
CLK4X
CLKPER4 output to pin
Bit 1:0 – CLKOUT[1:0]: Clock Output Port
These bits decide which port the peripheral clock will be output to. Pin 7 on the selected port is the default used.
The CLKOUT setting will override the EVOUT setting. Thus, if both are enabled on the same port pin, the peripheral clock will be visible. The port pin must be configured as output for the clock to be available on the pin.
Table 13-10 on page 155 shows the possible configurations.
Table 13-10. Clock output port configurations.
CLKOUT[1:0]
Group configuration
Description
00
OFF
01
PC
Clock output on PORTC
10
PD
Clock output on PORTD
11
PE
Clock output on PORTE
Clock output disabled
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13.14.5 EBIOUT – EBI Output register
Bit
7
6
5
4
3
2
1
0
+0x05
–
–
–
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EBIADROUT[1:0]
EBICSOUT[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – EBIADROUT[1:0]: EBI Address Output
The maximum configuration of the external bus interface (EBI) requires up to 32 dedicated pins. For devices with
only 24 EBI pins available, eight additional pins can be enabled and placed on alternate pin locations in order to
get a full 32-pin EBI. The port pins must be configured as output for signals to be available on the pins. These bits
are available on devices with only three ports dedicated for the EBI interface. The selections are valid only if the
EBI is configured to operate in four-port mode.
.
Table 13-11. EBI address output port selection.
EBIADROUT[1:0]
Group configuration
Description
00
PF
EBI port 3 address output on PORTF pins 0 to 7
01
PE
EBI port 3 address output on PORTE pins 0 to 7
10
PFH
EBI port 3 address output on PORTF pins 4 to 7
11
PEH
EBI port 3 address output on PORTE pins 4 to 7
Table 13-12. EBI address output
EBIADROUT
SDRAM
SRAM or SRAM LPC
(with SDRAM on CS3)
SRAM
NOALE or ALE1
00 or 01
4’h0, A[11:8]
A[23:16]
A[15:8]
10 or 11
A[11:8]
[19:16]
–
Bit 1:0 – EBICSOUT[1:0]: EBI Chip Select Output
These bits decide which port the EBI chip select signals will be output to. The pins must be configured as output
pins for signals to be available on the pins. Refer to “Register Description – EBI” on page 329 for chip select
configuration.
Table 13-13. EBI chip select port selection.
EBICSOUT[1:0]
Group configuration
Description
00
PH
EBI chip select output to PORTH pin 4 to 7
01
PL
EBI chip select output to PORTL pin 4 to 7
10
PF
EBI chip select output to PORTF pin 4 to 7
11
PE
EBI chip select output to PORTE pin 4 to 7
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13.14.6 EVCTRL – Event Control register
Bit
7
6
5
4
3
2
1
0
+0x06
–
–
–
–
–
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EVOUTSEL[2:0]
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2:0 – EVOUTSEL[2:0]: Event Channel Output Selection
These bits define which channel from the event system is output to the port pin. Table 13-14 on page 157 shows
the available selections.
Table 13-14. Event channel output selection.
EVOUTSEL[2:0]
Group configuration
Description
000
0
Event channel 0 output to pin
001
1
Event channel 1 output to pin
010
2
Event channel 2 output to pin
011
3
Event channel 3 output to pin
100
4
Event channel 4 output to pin
101
5
Event channel 5 output to pin
110
6
Event channel 6 output to pin
111
7
Event channel 7 output to pin
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13.15 Register Descriptions – Virtual Port
13.15.1 DIR – Data Direction register
Bit
7
6
5
4
+0x00
3
2
1
0
DIR[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – DIR[7:0]: Data Direction
This register sets the data direction for the individual pins in the port mapped by VPCTRLA, virtual port-map control register A or VPCTRLB, virtual port-map control register B. When a port is mapped as virtual, accessing this
register is identical to accessing the actual DIR register for the port.
13.15.2 OUT – Data Output Value register
Bit
7
6
5
4
+0x01
3
2
1
0
OUT[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – OUT[7:0]: Data Output value
This register sets the data output value for the individual pins in the port mapped by VPCTRLA, virtual port-map
control register A or VPCTRLB, virtual port-map control register B. When a port is mapped as virtual, accessing
this register is identical to accessing the actual OUT register for the port.
13.15.3 IN – Data Input Value register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x02
IN[7:0]
Bit 7:0 – IN[7:0]: Data Input Value
This register shows the value present on the pins if the digital input buffer is enabled. The configuration of VPCTRLA, virtual port-map control register A or VPCTRLB, virtual port-map control register A, decides the value in the
register. When a port is mapped as virtual, accessing this register is identical to accessing the actual IN register for
the port.
13.15.4 INTFLAGS – Interrupt Flag register
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
–
–
–
INT1IF
INT0IF
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
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Bit 1:0 – INTnIF: Interrupt n Flag
The INTnIF flag is set when a pin change/state matches the pin's input sense configuration, and the pin is set as
source for port interrupt n. Writing a one to this flag's bit location will clear the flag. For enabling and executing the
interrupt, refer to the interrupt level description. The configuration of VPCTRLA, virtual port-map control register A,
or VPCTRLB, Virtual Port-map Control Register B,, decides which flags are mapped. When a port is mapped as
virtual, accessing this register is identical to accessing the actual INTFLAGS register for the port.
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13.16 Register summary – Ports
Address
Name
Bit 7
+0x00
DIR
DIR[7:0]
148
+0x01
DIRSET
DIRSET[7:0]
148
+0x02
DIRCLR
DIRCLR[7:0]
148
+0x03
DIRTGL
DIRTGL[7:0]
148
+0x04
OUT
OUT[7:0]
149
+0x05
OUTSET
OUTSET[7:0]
149
+0x06
OUTCLR
OUTCLR[7:0]
149
+0x07
OUTTGL
OUTTGL[7:0]
149
+0x08
IN
IN[7:0]
150
+0x09
INTCTRL
+0x0A
INT0MASK
INT0MSK[7:0]
150
+0x0B
INT1MASK
INT1MSK[7:0]
150
+0x0C
INTFLAGS
–
–
–
–
–
–
INT1IF
INT0IF
+0x0D
Reserved
–
–
–
–
–
–
–
–
+0x0E
REMAP
–
–
SPI
USART0
TC0D
TC0C
TC0B
TC0A
+0x0F
Reserved
–
–
–
–
–
–
–
–
+0x10
PIN0CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x11
PIN1CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x12
PIN2CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x13
PIN3CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x14
PIN4CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x15
PIN5CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x16
PIN6CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x17
PIN7CTRL
SRLEN
INVEN
OPC[2:0]
ISC[2:0]
152
+0x18
Reserved
–
–
–
–
–
–
–
–
+0x19
Reserved
–
–
–
–
–
–
–
–
+0x1A
Reserved
–
–
–
–
–
–
–
–
+0x1B
Reserved
–
–
–
–
–
–
–
–
+0x1C
Reserved
–
–
–
–
–
–
–
–
+0x1D
Reserved
–
–
–
–
–
–
–
–
+0x1E
Reserved
–
–
–
–
–
–
–
–
+0x1F
Reserved
–
–
–
–
–
–
–
–
–
Bit 6
–
Bit 5
–
Bit 4
Bit 3
–
Bit 2
INT1LVL[1:0]
Bit 1
Bit 0
INT0LVL[1:0]
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151
160
13.17 Register summary – Port Configuration
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
bit 0
+0x00
MPCMASK
+0x01
Reserved
+0x02
VPCTRLA
VP1MAP[3:0]
VP0MAP[3:0]
153
+0x03
VPCTRLB
VP3MAP[3:0]
VP2MAP[3:0]
154
+0x04
CLKEVOUT
CLKEVPIN
RTCOUT
+0x05
EBIOUT
–
–
–
–
+0x06
EVCTRL
–
–
–
–
MPCMASK[7:0]
–
–
–
–
153
–
EVOUT[1:0]
Page
–
–
–
CLKOUTSEL
CLKOUT[1:0]
154
EBIADROUT[1:0]
EBICSOUT[1:0]
156
–
EVCTRL[2:0]
157
13.18 Register summary – Virtual Ports
Address
Name
Bit 7
+0x00
DIR
DIR[7:0]
158
+0x01
OUT
OUT[7:0]
158
+0x02
IN
IN[7:0]
158
+0x03
INTFLAGS
–
Bit 6
–
Bit 5
Bit 4
–
Bit 3
–
–
Bit 2
–
Bit 1
INT1IF
bit 0
INT0IF
Page
158
13.19 Interrupt vector summary – Ports
Table 13-15. Port interrupt vectors and their word offset address.
Offset
Source
Interrupt description
0x00
INT0_vect
Port interrupt vector 0 offset
0x02
INT1_vect
Port interrupt vector 1 offset
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14.
TC0/1 – 16-bit Timer/Counter Type 0 and 1
14.1
Features
16-bit timer/counter
32-bit timer/counter support by cascading two timer/counters
Up to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
Double buffered timer period setting
Double buffered capture or compare channels
Waveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
Input capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
Timer overflow and error interrupts/events
One compare match or input capture interrupt/event per CC channel
Can be used with event system for:
Quadrature decoding
Count and direction control
Capture
Can be used with DMA and to trigger DMA transactions
High-resolution extension
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
Advanced waveform extension:
14.2
Low- and high-side output with programmable dead-time insertion (DTI)
Event controlled fault protection for safe disabling of drivers
Overview
Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program
execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital
signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-
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side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins. The high-resolution (hi-res) extension can be used to
increase the waveform output resolution by four or eight times by using an internal clock source running up to four times
faster than the peripheral clock.
A block diagram of the 16-bit timer/counter with extensions and closely related peripheral modules (in grey) is shown in
Figure 14-1 on page 163.
Figure 14-1. 16-bit timer/counter and closely related peripherals.
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Control Logic
Counter
Event
System
Buffer
Capture
Control
Waveform
Generation
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORTS
Comparator
AWeX
Hi-Res
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
14.2.1 Definitions
The following definitions are used throughout the documentation:
Table 14-1. Timer/counter definitions.
Name
Description
BOTTOM
The counter reaches BOTTOM when it becomes zero.
MAX
The counter reaches MAXimum when it becomes all ones.
TOP
The counter reaches TOP when it becomes equal to the highest value in the count sequence. The TOP value
can be equal to the period (PER) or the compare channel A (CCA) register setting. This is selected by the
waveform generator mode.
UPDATE
The timer/counter signals an update when it reaches BOTTOM or TOP, depending on the waveform generator
mode.
In general, the term “timer” is used when the timer/counter clock control is handled by an internal source, and the term
“counter” is used when the clock control is handled externally (e.g. counting external events). When used for compare
operations, the CC channels are referred to as “compare channels.” When used for capture operations, the CC channels
are referred to as “capture channels.”
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Block Diagram
Figure 14-2 on page 164 shows a detailed block diagram of the timer/counter without the extensions.
Figure 14-2. Timer/counter block diagram.
Base Counter
BV
PERBUF
CTRLA
PER
CTRLD
Clock Select
Event
Select
"count"
"clear"
"load"
"direction"
Counter
CNT
OVF/UNF
(INT/DMA Req.)
Control Logic
ERRIF
(INT Req.)
=
=0
TOP
BOTTOM
"ev"
UPDATE
14.3
Compare/Capture
(Unit x = {A,B,C,D})
BV
CCBUFx
Control Logic
CCx
=
Waveform
Generation
"match"
OCx Out
CCxIF
(INT/DMA
Req.)
The counter register (CNT), period registers with buffer (PER and PERBUF), and compare and capture registers with
buffers (CCx and CCxBUF) are 16-bit registers. All buffer register have a buffer valid (BV) flag that indicates when the
buffer contains a new value.
During normal operation, the counter value is continuously compared to zero and the period (PER) value to determine
whether the counter has reached TOP or BOTTOM.
The counter value is also compared to the CCx registers. These comparisons can be used to generate interrupt
requests, request DMA transactions or generate events for the event system. The waveform generator modes use these
comparisons to set the waveform period or pulse width.
A prescaled peripheral clock and events from the event system can be used to control the counter. The event system is
also used as a source to the input capture. Combined with the quadrature decoding functionality in the event system
(QDEC), the timer/counter can be used for quadrature decoding.
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14.4
Clock and Event Sources
The timer/counter can be clocked from the peripheral clock (clkPER) or the event system, and Figure 14-3 shows the clock
and event selection.
Figure 14-3. Clock and event selection.
clkPER
Common
Prescaler
clkPER /
2{0,...,15}
clkPER /
{1,2,4,8,64,256,1024}
Event System
events
event channels
CKSEL
Control Logic
EVSEL
CNT
EVACT
(Encoding)
The peripheral clock is fed into a common prescaler (common for all timer/counters in a device). Prescaler outputs from 1
to 1/1024 are directly available for selection by the timer/counter. In addition, the whole range of prescaling from 1 to 215
times is available through the event system.
Clock selection (CLKSEL) selects one of the prescaler outputs directly or an event channel as the counter (CNT) input.
This is referred to as normal operation of the counter. For details, refer to “Normal Operation” on page 166. By using the
event system, any event source, such as an external clock signal on any I/O pin, may be used as the clock input.
In addition, the timer/counter can be controlled via the event system. The event selection (EVSEL) and event action
(EVACT) settings are used to trigger an event action from one or more events. This is referred to as event action
controlled operation of the counter. For details, refer to “Event Action Controlled Operation” on page 167. When event
action controlled operation is used, the clock selection must be set to use an event channel as the counter input.
By default, no clock input is selected and the timer/counter is not running.
14.5
Double Buffering
The period register and the CC registers are all double buffered. Each buffer register has a buffer valid (BV) flag, which
indicates that the buffer register contains a valid, i.e. new, value that can be copied into the corresponding period or CC
register. When the period register and CC channels are used for a compare operation, the buffer valid flag is set when
data is written to the buffer register and cleared on an UPDATE condition. This is shown for a compare register in Figure
14-4 on page 166.
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Figure 14-4. Period and compare double buffering.
"write enable"
BV
UPDATE
"data write"
EN
CCxBUF
EN
CCx
CNT
=
"match"
When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case
the buffer valid flag is set on the capture event, as shown in Figure 14-5. For capture, the buffer register and the
corresponding CCx register act like a FIFO. When the CC register is empty or read, any content in the buffer register is
passed to the CC register. The buffer valid flag is passed to set the CCx interrupt flag (IF) and generate the optional
interrupt.
Figure 14-5. Capture double buffering.
"capture"
CNT
BV
EN
CCxBUF
IF
EN
CCx
"INT/DMA
request"
data read
Both the CCx and CCxBUF registers are available as an I/O register. This allows initialization and bypassing of the buffer
register and the double buffering function.
14.6
Counter Operation
Depending on the mode of operation, the counter is cleared, reloaded, incremented, or decremented at each
timer/counter clock input.
14.6.1 Normal Operation
In normal operation, the counter will count in the direction set by the direction (DIR) bit for each clock until it reaches TOP
or BOTTOM. When up-counting and TOP is reached, the counter will be set to zero when the next clock is given. When
down-counting, the counter is reloaded with the period register value when BOTTOM is reached.
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Figure 14-6. Normal operation.
CNT written
MAX
"update"
TOP
CNT
BOTTOM
DIR
As shown in Figure 14-6, it is possible to change the counter value when the counter is running. The write access has
higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed
during normal operation.
Normal operation must be used when using the counter as timer base for the capture channels.
14.6.2 Event Action Controlled Operation
The event selection and event action settings can be used to control the counter from the event system. For the counter,
the following event actions can be selected:
Event system controlled up/down counting
Event n will be used as count enable
Event n+1 will be used to select between up (1) and down (0). The pin configuration must be set to low level
sensing
Event system controlled quadrature decode counting
14.6.3 32-bit Operation
Two timer/counters can be used together to enable 32-bit counter operation. By using two timer/counters, the overflow
event from one timer/counter (least-significant timer) can be routed via the event system and used as the clock input for
another timer/counter (most-significant timer).
14.6.4 Changing the Period
The counter period is changed by writing a new TOP value to the period register. If double buffering is not used, any
period update is immediate, as shown in Figure 14-7 on page 167.
Figure 14-7. Changing the period without buffering.
Counter Wraparound
MAX
"update"
"write"
CNT
BOTTOM
New TOP written to
PER that is higher
than current CNT
New TOP written to
PER that is lower
than current CNT
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A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 14-8.
This due to the fact that CNT and PER are continuously compared, and if a new TOP value that is lower than current
CNT is written to PER, it will wrap before a compare match happen.
Figure 14-8. Unbuffered dual-slope operation.
Counter Wraparound
MAX
"update"
"write"
CNT
BOTTOM
New TOP written to
PER that is higher
than current CNT
New TOP written to
PER that is lower
than current CNT
When double buffering is used, the buffer can be written at any time and still maintain correct operation. The period
register is always updated on the UPDATE condition, as shown for dual-slope operation in Figure 14-9. This prevents
wraparound and the generation of odd waveforms.
Figure 14-9. Changing the period using buffering.
MAX
"update"
"write"
CNT
BOTTOM
New Period written to
PERBUF that is higher
than current CNT
14.7
New Period written to
PERBUF that is lower
than current CNT
New PER is updated
with PERBUF value.
Capture Channel
The CC channels can be used as capture channels to capture external events and give them a timestamp. To use
capture, the counter must be set for normal operation.
Events are used to trigger the capture; i.e., any events from the event system, including pin change from any pin, can
trigger a capture operation. The event source select setting selects which event channel will trigger CC channel A. The
subsequent event channels then trigger events on subsequent CC channels, if configured. For example, setting the
event source select to event channel 2 results in CC channel A being triggered by event channel 2, CC channel B
triggered by event channel 3, and so on.
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Figure 14-10.Event source selection for capture operation.
Event System
CH0MUX
CH1MUX
CCA capture
Event channel 0
Event channel 1
CCB capture
CCC capture
CHnMUX
Event channel n
Rotate
CCD capture
Event Source Selection
The event action setting in the timer/counter will determine the type of capture that is done.
The CC channels must be enabled individually before capture can be done. When the capture condition occur, the
timer/counter will time-stamp the event by copying the current CNT value in the count register into the enabled CC
channel register.
When an I/O pin is used as an event source for the capture, the pin must be configured for edge sensing. For details on
sense configuration on I/O pins, refer to “Input Sense Configuration” on page 143. If the period register value is lower
than 0x8000, the polarity of the I/O pin edge will be stored in the most-significant bit (msb) of the capture register. If the
msb of the capture register is zero, a falling edge generated the capture. If the msb is one, a rising edge generated the
capture.
14.7.1 Input Capture
Selecting the input capture event action makes the enabled capture channel perform an input capture on an event. The
interrupt flags will be set and indicate that there is a valid capture result in the corresponding CC register. At the same
time, the buffer valid flags indicate valid data in the buffer registers.
The counter will continuously count from BOTTOM to TOP, and then restart at BOTTOM, as shown in Figure 14-11. The
figure also shows four capture events for one capture channel.
Figure 14-11.Input capture timing.
events
TOP
CNT
BOTTOM
Capture 0
Capture 1
Capture 2
Capture 3
14.7.2 Frequency Capture
Selecting the frequency capture event action makes the enabled capture channel perform an input capture and restart on
positive edge events. This enables the timer/counter to measure the period or frequency of a signal directly. The capture
result will be the time (T) from the previous timer/counter restart until the event occurred. This can be used to calculate
the frequency (f) of the signal:
f = --1T
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Figure 14-12 on page 170 shows an example where the period of an external signal is measured twice.
Figure 14-12.Frequency capture of an external signal.
Period (T)
external signal
events
MAX
"capture"
CNT
BOTTOM
Since all capture channels use the same counter (CNT), only one capture channel must be enabled at a time. If two
capture channels are used with different sources, the counter will be restarted on positive edge events from both input
sources, and the result will have no meaning.
14.7.3 Pulse Width Capture
Selecting the pulse width measure event action makes the enabled compare channel perform the input capture action on
falling edge events and the restart action on rising edge events. The counter will then restart on positive edge events,
and the input capture will be performed on the negative edge event. The event source must be an I/O pin, and the sense
configuration for the pin must be set to generate an event on both edges. Figure 14-13 on page 170 shows and example
where the pulse width is measured twice for an external signal.
Figure 14-13.Pulse width capture of an external signal.
Pulsewitdh (tp)
external signal
events
MAX
"capture"
CNT
BOTTOM
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14.7.4 32-bit Input Capture
Two timer/counters can be used together to enable true 32-bit input capture. In a typical 32-bit input capture setup, the
overflow event of the least-significant timer is connected via the event system and used as the clock input for the mostsignificant timer.
The most-significant timer will be updated one peripheral clock period after an overflow occurs for the least-significant
timer. To compensate for this, the capture event for the most-significant timer must be equally delayed by setting the
event delay bit for this timer.
14.7.5 Capture Overflow
The timer/counter can detect buffer overflow of the input capture channels. When both the buffer valid flag and the
capture interrupt flag are set and a new capture event is detected, there is nowhere to store the new timestamp. If a
buffer overflow is detected, the new value is rejected, the error interrupt flag is set, and the optional interrupt is
generated.
14.8
Compare Channel
Each compare channel continuously compares the counter value (CNT) with the CCx register. If CNT equals CCx, the
comparator signals a match. The match will set the CC channel's interrupt flag at the next timer clock cycle, and the
event and optional interrupt are generated.
The compare buffer register provides double buffer capability equivalent to that for the period buffer. The double
buffering synchronizes the update of the CCx register with the buffer value to either the TOP or BOTTOM of the counting
sequence according to the UPDATE condition. The synchronization prevents the occurrence of odd-length, nonsymmetrical pulses for glitch-free output.
14.8.1 Waveform Generation
The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform
visible on the connected port pin, the following requirements must be fulfilled:
1.
A waveform generation mode must be selected.
2.
Event actions must be disabled.
3.
The CC channels used must be enabled. This will override the corresponding port pin output register.
4.
The direction for the associated port pin must be set to output.
Inverted waveform output is achieved by setting the invert output bit for the port pin.
14.8.2 Frequency (FRQ) Waveform Generation
For frequency generation the period time (T) is controlled by the CCA register instead of PER. The waveform generation
(WG) output is toggled on each compare match between the CNT and CCA registers, as shown in Figure 14-14 on page
172.
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Figure 14-14.Frequency waveform generation.
Period (T)
Direction Change
CNT written
MAX
"update"
CNT
TOP
BOTTOM
WG Output
The waveform frequency (fFRQ) is defined by the following equation:
fclk PER
f FRQ = --------------------------------2N CCA + 1
where N represents the prescaler divider used. The waveform generated will have a maximum frequency of half of the
peripheral clock frequency (fclkPER) when CCA is set to zero (0x0000) and no prescaling is used. This also applies when
using the hi-res extension, since this increases the resolution and not the frequency.
14.8.3 Single-slope PWM Generation
For single-slope PWM generation, the period (T) is controlled by PER, while CCx registers control the duty cycle of the
WG output. Figure 14-15 shows how the counter counts from BOTTOM to TOP and then restarts from BOTTOM. The
waveform generator (WG) output is set on the compare match between the CNT and CCx registers and cleared at TOP.
Figure 14-15.Single-slope pulse width modulation.
Period (T)
CCx=BOTTOM
CCx=TOP
"update"
"match"
MAX
TOP
CNT
CCx
BOTTOM
WG Output
The PER register defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum
resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for single-slope PWM (RPWM_SS):
PER + 1 -
R PWM_SS = log
-------------------------------log 2
The single-slope PWM frequency (fPWM_SS) depends on the period setting (PER) and the peripheral clock frequency
(fclkPER), and can be calculated by the following equation:
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fclk PER
f PWM_SS = ---------------------------N PER + 1
where N represents the prescaler divider used.
14.8.4 Dual-slope PWM
For dual-slope PWM generation, the period (T) is controlled by PER, while CCx registers control the duty cycle of the WG
output. Figure 14-16 shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOP and then from
TOP to BOTTOM. The waveform generator output is set on BOTTOM, cleared on compare match when up-counting,
and set on compare match when down-counting.
Figure 14-16.Dual-slope pulse width modulation.
Period (T)
CCx=BOTTOM
CCx=TOP
"update"
"match"
MAX
CCx
TOP
CNT
BOTTOM
WG Output
Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slope PWM operation.
The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the
maximum resolution is 16 bits (PER=MAX).
The following equation calculate the exact resolution for dual-slope PWM (RPWM_DS):
PER + 1 R PWM_DS = log
-------------------------------log 2
The PWM frequency depends on the period setting (PER) and the peripheral clock frequency (fclkPER), and can be
calculated by the following equation:
fclk PER
f PWM_DS = -----------------2NPER
N represents the prescaler divider used.
14.8.5 Port Override for Waveform Generation
To make the waveform generation available on the port pins, the corresponding port pin direction must be set as output.
The timer/counter will override the port pin values when the CC channel is enabled (CCENx) and a waveform generation
mode is selected.
Figure 14-17 on page 174 shows the port override for a timer/counter. The timer/counter CC channel will override the
port pin output value (OUT) on the corresponding port pin. Enabling inverted I/O on the port pin (INVEN) inverts the
corresponding WG output.
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Figure 14-17.Port override for timer/counter 0 and 1.
OUT
OCx
Waveform
CCExEN
14.9
INVEN
Interrupts and events
The timer/counter can generate both interrupts and events. The counter can generate an interrupt on overflow/underflow,
and each CC channel has a separate interrupt that is used for compare or capture. In addition, an error interrupt can be
generated if any of the CC channels is used for capture and a buffer overflow condition occurs on a capture channel.
Events will be generated for all conditions that can generate interrupts. For details on event generation and available
events, refer to “Event System” on page 70.
14.10 DMA Support
The interrupt flags can be used to trigger DMA transactions. Table 14-2 on page 174 lists the transfer triggers available
from the timer/counter and the DMA action that will clear the transfer trigger. For more details on using DMA, refer to
“DMAC - Direct Memory Access Controller” on page 53.
Table 14-2. DMA request sources.
Request
Acknowledge
OVFIF/UNFIF
DMA controller writes to CNT
DMA controller writes to PER
DMA controller writes to PERBUF
DMA controller writes to DTHSBUF or DTLSBUF in
AWex in Pattern generation mode
ERRIF
N/A
CCxIF
DMA controller access of CCx
DMA controller access of CCxBUF
Comment
Input capture operation
Output compare operation
14.11 Timer/Counter Commands
A set of commands can be given to the timer/counter by software to immediately change the state of the module. These
commands give direct control of the UPDATE, RESTART, and RESET signals.
An update command has the same effect as when an update condition occurs. The update command is ignored if the
lock update bit is set.
The software can force a restart of the current waveform period by issuing a restart command. In this case the counter,
direction, and all compare outputs are set to zero.
A reset command will set all timer/counter registers to their initial values. A reset can be given only when the
timer/counter is not running (OFF).
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14.12 Register Description
14.12.1 CTRLA – Control register A
Bit
7
6
5
4
+0x00
–
–
–
–
3
Read/Write
R
R
R
R
R/W
Initial Value
0
0
0
0
0
2
1
0
R/W
R/W
R/W
0
0
0
CLKSEL[3:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:0 – CLKSEL[3:0]: Clock Select
These bits select the clock source for the timer/counter according to Table 14-3.
CLKSEL=0001 must be set to ensure a correct output from the waveform generator when the hi-res extension is
enabled.
Table 14-3. Clock select options.
CLKSEL[3:0]
Group configuration
Description
0000
OFF
None (i.e, timer/counter in OFF state)
0001
DIV1
Prescaler: Clk
0010
DIV2
Prescaler: Clk/2
0011
DIV4
Prescaler: Clk/4
0100
DIV8
Prescaler: Clk/8
0101
DIV64
Prescaler: Clk/64
0110
DIV256
Prescaler: Clk/256
0111
DIV1024
Prescaler: Clk/1024
1nnn
EVCHn
Event channel n, n= [0,...,7]
14.12.2 CTRLB – Control register B
Bit
7
6
5
4
3
CCDEN
CCCEN
CCBEN
CCAEN
–
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x01
2
1
0
WGMODE[2:0]
Bit 7:4 – CCxEN: Compare or Capture Enable
Setting these bits in the FRQ or PWM waveform generation mode of operation will override the port output register
for the corresponding OCn output pin.
When input capture operation is selected, the CCxEN bits enable the capture operation for the corresponding CC
channel.
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
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Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode
These bits select the waveform generation mode, and control the counting sequence of the counter, TOP value,
UPDATE condition, interrupt/event condition, and type of waveform that is generated according to Table 14-4 on
page 176.
No waveform generation is performed in the normal mode of operation. For all other modes, the result from the
waveform generator will only be directed to the port pins if the corresponding CCxEN bit has been set to enable
this. The port pin direction must be set as output
Table 14-4. Timer waveform generation mode.
WGMODE[2:0]
Group configuration
Mode of operation
Top
Update
OVFIF/Event
000
NORMAL
Normal
PER
TOP
TOP
001
FRQ
Frequency
CCA
TOP
TOP
Reserved
–
–
–
Single-slope PWM
PER
BOTTOM
BOTTOM
Reserved
–
–
–
010
011
SINGLESLOPE
100
101
DSTOP
Dual-slope PWM
PER
BOTTOM
TOP
110
DSBOTH
Dual-slope PWM
PER
BOTTOM
TOP and BOTTOM
111
DSBOTTOM
Dual-slope PWM
PER
BOTTOM
BOTTOM
14.12.3 CTRLC – Control register C
Bit
7
6
5
4
3
2
1
0
+0x02
–
–
–
–
CMPD
CMPC
CMPB
CMPA
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:0 – CMPx: Compare Output Value x
These bits allow direct access to the waveform generator's output compare value when the timer/counter is set in
the OFF state. This is used to set or clear the WG output value when the timer/counter is not running.
14.12.4 CTRLD – Control register D
Bit
7
+0x03
6
5
EVACT[2:0]
4
3
2
EVDLY
1
0
EVSEL[3:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:5 – EVACT[2:0]: Event Action
These bits define the event action the timer will perform on an event according to Table 14-5 on page 177.
The EVSEL setting will decide which event source or sources have control in this case.
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Table 14-5. Timer event action selection.
EVACT[2:0]
Group configuration
Event action
000
OFF
001
CAPT
010
UPDOWN
011
QDEC
100
RESTART
101
FRQ
Frequency capture
110
PW
Pulse width capture
None
Input capture
Externally controlled up/ down count
Quadrature decode
111
Restart waveform period
Reserved
Selecting any of the capture event actions changes the behavior of the CCx registers and related status and control bits
to be used for capture. The error status flag (ERRIF) will indicate a buffer overflow in this configuration. See “Event
Action Controlled Operation” on page 167 for further details.
Bit 4 – EVDLY: Timer Delay Event
When this bit is set, the selected event source is delayed by one peripheral clock cycle. This is intended for 32-bit
input capture operation. Adding the event delay is necessary to compensate for the carry propagation delay when
cascading two counters via the event system.
Bit 3:0 – EVSEL[3:0]:Timer Event Source Select
These bits select the event channel source for the timer/counter. For the selected event channel to have any
effect, the event action bits (EVACT) must be set according to Table 14-6 on page 177. When the event action is
set to a capture operation, the selected event channel n will be the event channel source for CC channel A, and
event channel (n+1)%8, (n+2)%8, and (n+3)%8 will be the event channel source for CC channel B, C, and D.
Table 14-6. Timer event source selection.
EVSEL[3:0]
Group configuration
0000
OFF
Event source
None
0001
Reserved
0010
Reserved
0011
Reserved
0100
Reserved
0101
Reserved
0110
Reserved
0111
Reserved
1nnn
CHn
Event channel n, n={0,...,7}
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14.12.5 CTRLE – Control register E
Bit
7
6
5
4
3
2
1
0
+0x04
–
–
–
–
–
–
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
BYTEM[1:0]
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1:0 – BYTEM[1:0]: Byte Mode
These bits select the timer/counter operation mode according to Table 14-7 on page 178.
Table 14-7. Clock select.
BYTEM[1:0]
Group configuration
Description
00
NORMAL
01
BYTEMODE
Upper byte of the counter (CNTH) will be set to zero after each counter clock cycle
10
SPLITMODE
Timer/counter 0 is split into two 8-bit timer/counters (timer/counter type 2)
Timer/counter is set to normal mode (timer/counter type 0)
11
Reserved
14.12.6 INTCTRLA – Interrupt Enable register A
Bit
7
6
5
4
3
2
1
0
+0x06
–
–
–
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ERRINTLVL[1:0]
OVFINTLVL[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level
These bits enable the timer error interrupt and select the interrupt level as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131.
Bit 1:0 – OVFINTLVL[1:0]:Timer Overflow/Underflow Interrupt Level
These bits enable the timer overflow/underflow interrupt and select the interrupt level as described in “Interrupts
and Programmable Multilevel Interrupt Controller” on page 131.
14.12.7 INTCTRLB – Interrupt Enable register B
Bit
+0x07
7
6
CCDINTLVL[1:0]
5
4
CCCINTLVL[1:0]
3
2
CCBINTLVL[1:0]
1
0
CCAINTLVL[1:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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Bit 7:0 – CCxINTLVL[7:0] - Compare or Capture x Interrupt Level:
These bits enable the timer compare or capture interrupt for channel x and select the interrupt level as described in
“Interrupts and Programmable Multilevel Interrupt Controller” on page 131.
14.12.8 CTRLFCLR/CTRLFSET – Control register F Clear/Set
This register is mapped into two I/O memory locations, one for clearing (CTRLxCLR) and one for setting the register bits
(CTRLxSET) when written. Both memory locations will give the same result when read.
The individual status bit can be set by writing a one to its bit location in CTRLxSET, and cleared by writing a one to its bit
location in CTRLxCLR. This allows each bit to be set or cleared without use of a read-modify-write operation on a single
register.
Bit
7
6
5
4
3
2
1
0
+0x08
–
–
–
QDECINDX
LUPD
DIR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
+0x09
–
–
–
QDECINDX
Read/Write
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
CMD[1:0]
2
1
0
LUPD
DIR
R/W
R/W
R/W
0
0
0
CMD[1:0]
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – QDECINDX: QDEC Index Flag
This bit indicates that a QDEC index is observed. The flag is cleared when counting up or down from zero. Normally this bit is controlled in hardware by the event actions, but this bit can also be changed from software.
Bit 3:2 – CMD[1:0]: Command
These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits
are always read as zero.
Table 14-8. Command selections.
CMD
Group configuration
Command action
00
NONE
01
UPDATE
Force update
10
RESTART
Force restart
11
RESET
None
Force hard reset (ignored if T/C is not in OFF state)
Bit 1 – LUPD: Lock Update
When this bit is set, no update of the buffered registers is performed, even though an UPDATE condition has
occurred. Locking the update ensures that all buffers, including DTI buffers, are valid before an update is
performed.
This bit has no effect when input capture operation is enabled.
Bit 0 – DIR: Counter Direction
When zero, this bit indicates that the counter is counting up (incrementing). A one indicates that the counter is in
the down-counting (decrementing) state.
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Normally this bit is controlled in hardware by the waveform generation mode or by event actions, but this bit can
also be changed from software.
14.12.9 CTRLGCLR/CTRLGSET – Control register G Clear/Set
Bit
7
6
5
4
3
2
1
0
+0x0A/ +0x0B
–
–
–
CCDBV
CCCBV
CCBBV
CCABV
PERBV
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Refer to “CTRLFCLR/CTRLFSET – Control register F Clear/Set” on page 179 for information on how to access this type
of status register.
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4:1 – CCxBV: Compare or Capture x Buffer Valid
These bits are set when a new value is written to the corresponding CCxBUF register. These bits are automatically
cleared on an UPDATE condition.
Note that when input capture operation is used, this bit is set on a capture event and cleared if the corresponding
CCxIF is cleared.
Bit 0 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared on an UPDATE
condition.
14.12.10 INTFLAGS – Interrupt Flag register
Bit
+0x0C
7
6
5
4
3
2
1
0
CCDIF
CCCIF
CCBIF
CCAIF
–
–
ERRIF
OVFIF
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag
The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the corresponding CC channel.
For all modes of operation except for capture, the CCxIF will be set when a compare match occurs between the
count register (CNT) and the corresponding compare register (CCx). The CCxIF is automatically cleared when the
corresponding interrupt vector is executed.
For input capture operation, the CCxIF will be set if the corresponding compare buffer contains valid data (i.e.,
when CCxBV is set). The flag will be cleared when the CCx register is read. Executing the interrupt vector in this
mode of operation will not clear the flag.
The flag can also be cleared by writing a one to its bit location.
The CCxIF can be used for requesting a DMA transfer. A DMA read or write access of the corresponding CCx or
CCxBUF will then clear the CCxIF and release the request.
Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – ERRIF: Error Interrupt Flag
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This flag is set on multiple occasions, depending on the mode of operation.
In the FRQ or PWM waveform generation mode of operation, ERRIF is set on a fault detect condition from the fault
protection feature in the AWeX extention. For timer/counters which do not have the AWeX extention available, this
flag is never set in FRQ or PWM waveform generation mode.
For capture operation, ERRIF is set if a buffer overflow occurs on any of the CC channels.
For event controlled QDEC operation, ERRIF is set when an incorrect index signal is given.
This flag is automatically cleared when the corresponding interrupt vector is executed. The flag can also be
cleared by writing a one to this location.
Bit 0 – OVFIF: Overflow/Underflow Interrupt Flag
This flag is set either on a TOP (overflow) or BOTTOM (underflow) condition, depending on the WGMODE setting.
OVFIF is automatically cleared when the corresponding interrupt vector is executed. The flag can also be cleared
by writing a one to its bit location.
OVFIF can also be used for requesting a DMA transfer. A DMA write access of CNT, PER, or PERBUF will then
clear the OVFIF bit.
14.12.11 TEMP – Temporary bits for 16-bit Access
The TEMP register is used for single-cycle, 16-bit access to the 16-bit timer/counter registers by the CPU. The DMA
controller has a separate temporary storage register. There is one common TEMP register for all the 16-bit Timer/counter
registers.
For more details, refer to “The combined EIND + Z register.” on page 12.
Bit
7
6
5
4
+0x0F
3
2
1
0
TEMP[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
14.12.12 CNTL – Counter register Low
The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the
timer/counter. CPU and DMA write access has priority over count, clear, or reload of the counter.
For more details on reading and writing 16-bit registers, refer to “The combined EIND + Z register.” on page 12.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
+0x20
CNT[7:0]
Bit 7:0 – CNT[7:0]: Counter low byte
These bits hold the LSB of the 16-bit counter register.
14.12.13 CNTH – Counter register High
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x21
CNT[15:8]
Bit 7:0 – CNT[15:8]: Counter high byte
These bits hold the MSB of the 16-bit counter register.
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14.12.14 PERL – Period register Low
The PERH and PERL register pair represents the 16-bit value, PER. PER contains the 16-bit TOP value in the
timer/counter.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
3
2
1
0
+0x26
PER[7:0]
Bit 7:0 – PER[7:0]: Periodic low byte
These bits hold the LSB of the 16-bit period register.
14.12.15 PERH – Period register H
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
+0x27
PER[15:8]
Bit 7:0 – PER[15:8]: Periodic high byte
These bits hold the MSB of the 16-bit period register.
14.12.16 CCxL – Compare or Capture x register Low
The CCxH and CCxL register pair represents the 16-bit value, CCx. These 16-bit register pairs have two functions,
depending of the mode of operation.
For capture operation, these registers constitute the second buffer level and access point for the CPU and DMA.
For compare operation, these registers are continuously compared to the counter value. Normally, the outputs form the
comparators are then used for generating waveforms.
CCx registers are updated with the buffer value from their corresponding CCxBUF register when an UPDATE condition
occurs.
Bit
7
6
5
4
3
2
1
0
CCx[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – CCx[7:0]: Compare or Capture x low byte
These bits hold the LSB of the 16-bit compare or capture register.
14.12.17 CCxH – Compare or Capture x register High
Bit
7
6
5
4
3
2
1
0
CCx[15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – CCx[15:8]: Compare or Capture x high byte
These bits hold the MSB of the 16-bit compare or capture register.
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14.12.18 PERBUFL – Timer/Counter Period Buffer Low
The PERBUFH and PERBUFL register pair represents the 16-bit value, PERBUF. This 16-bit register serves as the
buffer for the period register (PER). Accessing this register using the CPU or DMA will affect the PERBUFV flag.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
2
1
0
+0x36
PERBUF[7:0]
Bit 7:0 – PERBUF[7:0]: Period Buffer low byte
These bits hold the LSB of the 16-bit period buffer register.
14.12.19 PERBUFH – Timer/Counter Period Buffer High
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
+0x37
3
PERBUF[15:8]
Bit 7:0 – PERBUF[15:8]: Period Buffer high byte
These bits hold the MSB of the 16-bit period buffer register.
14.12.20 CCxBUFL – Compare or Capture x Buffer register Low
The CCxBUFH and CCxBUFL register pair represents the 16-bit value, CCxBUF. These 16-bit registers serve as the
buffer for the associated compare or capture registers (CCx). Accessing any of these registers using the CPU or DMA
will affect the corresponding CCxBV status bit.
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
2
1
0
CCxBUFx[7:0]
Bit 7:0 – CCxBUF[7:0]: Compare or Capture low byte
These bits hold the LSB of the 16-bit compare or capture buffer register.
14.12.21 CCxBUFH – Compare or Capture x Buffer register High
Bit
7
6
5
4
3
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
CCxBUF[15:8]
Bit 7:0 – CCxBUF[15:8]: Compare or Capture high byte
These bits hold the MSB of the 16-bit compare or capture buffer register.
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14.13 Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
+0x00
CTRLA
–
–
–
–
+0x01
CTRLB
CCDEN
CCCEN
CCBEN
CCAEN
–
+0x02
CTRLC
–
–
–
–
CMPD
+0x03
CTRLD
+0x04
CTRLE
–
–
–
–
–
–
+0x05
Reserved
–
–
–
–
–
–
+0x06
INTCTRLA
–
–
–
–
+0x07
INTCTRLB
+0x08
CTRLFCLR
–
–
–
QDECINDX
CMD[1:0]
LUPD
DIR
179
+0x09
CTRLFSET
–
–
–
QDECINDX
CMD[1:0]
LUPD
DIR
180
+0x0A
CTRLGCLR
–
–
–
CCDBV
CCCBV
CCBBV
CCABV
PERBV
180
+0x0B
CTRLGSET
–
–
–
CCDBV
CCCBV
CCBBV
CCABV
PERBV
180
+0x0C
INTFLAGS
CCDIF
CCCIF
CCBIF
CCAIF
–
–
ERRIF
OVFIF
180
+0x0D
Reserved
–
–
–
–
–
–
–
–
+0x0E
Reserved
–
–
–
–
–
–
–
–
+0x0F
TEMP
+0x10 to
+0x1F
Reserved
+0x20
CNTL
CNT[7:0]
181
+0x21
CNTH
CNT[15:8]
181
+0x22 to
+0x25
Reserved
+0x26
PERL
PER[7:0]
182
+0x27
PERH
PER[8:15]
182
+0x28
CCAL
CCA[7:0]
182
+0x29
CCAH
CCA[15:8]
182
+0x2A
CCBL
CCB[7:0]
182
+0x2B
CCBH
CCB[15:8]
182
+0x2C
CCCL
CCC[7:0]
182
+0x02D
CCCH
CCC[15:8]
182
+0x2E
CCDL
CCD[7:0]
182
+0x2F
CCDH
CCD[15:8]
182
+0x30 to
+0x35
Reserved
+0x36
PERBUFL
EVACT[2:0]
CCCINTLVL[1:0]
Bit 3
Bit 2
Bit 1
Bit 0
CLKSEL[3:0]
175
WGMODE[2:0]
CMPC
EVDLY
CMPB
175
CMPA
EVSEL[3:0]
CCCINTLVL[1:0]
–
–
–
–
–
–
–
–
–
BYTEM
–
178
–
ERRINTLVL[1:0]
OVINTLVL[1:0]
178
CCBINTLVL[1:0]
CCAINTLVL[1:0]
178
–
181
–
–
176
176
TEMP[7:0]
–
Page
–
–
–
–
–
–
–
–
–
–
–
PERBUF[7:0]
183
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Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x37
PERBUFH
PERBUF[15:8]
183
+0x38
CCABUFL
CCABUF[7:0]
183
+0x39
CCABUFH
CCABUF[15:8]
183
+0x3A
CCBBUFL
CCBBUF[7:0]
183
+0x3B
CCBBUFH
CCBBUF[15:8]
183
+0x3C
CCCBUFL
CCCBUF[7:0]
183
+0x3D
CCCBUFH
CCCBUF[15:8]
183
+0x3E
CCDBUFL
CCDBUF[7:0]
183
+0x3F
CCDBUFH
CCDBUF[15:8]
183
14.14 Interrupt vector summary
Table 14-9. Timer/counter interrupt vectors and their word offset address.
Offset
Source
Interrupt description
0x00
OVF_vect
Timer/counter overflow/underflow interrupt vector offset
0x02
ERR_vect
Timer/counter error interrupt vector offset
0x04
CCA_vect
Timer/counter compare or capture channel A interrupt vector offset
0x06
CCB_vect
Timer/counter compare or capture channel B interrupt vector offset
0x08
CCC_vect(1)
Timer/counter compare or capture channel C interrupt vector offset
0x0A
CCD_vect(1)
Timer/counter compare or capture channel D interrupt vector offset
Note:
1. Available only on timer/counters with four compare or capture channels.
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15.
TC2 – 16-bit Timer/Counter Type 2
15.1
Features
A system of two eight-bit timer/counters
Low-byte timer/counter
High-byte timer/counter
Eight compare channels
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
Can be used to trigger DMA transactions
15.2
Overview
A timer/counter 2 is realized when a timer/counter 0 is set in split mode. It is a system of two eight-bit
timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM)
channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM
channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers.
The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be
clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always
counting down.
The high resolution (hi-res) extension can be used to increase the waveform output resolution by up to eight times by
using an internal clock source running up to four times faster than the peripheral clock.
The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as
either type 0 or type 2.
A detailed block diagram of the timer/counter 2 showing the low-byte (L) and high-byte (H) timer/counter register split and
compare modules is shown in Figure 15-1 on page 187.
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15.3
Block Diagram
Figure 15-1. Block diagram of the 16-bit timer/counter 0 with split mode.
Base Counter
HPER
"count high"
"load high"
"count low"
"load low"
Counter
HCNT
Clock Select
CTRLA
LPER
LCNT
HUNF
Control Logic
(INT/DMA Req.)
LUNF
(INT/DMA Req.)
=0
BOTTOML
BOTTOMH
=0
Compare
(Unit x = {A,B,C,D})
LCMPx
Waveform
Generation
OCLx Out
LCMPx
"match"
=
(INT/DMA
Req.)
Compare
(Unit x = {A,B,C,D})
HCMPx
=
15.4
Waveform
Generation
OCHx Out
"match"
Clock Sources
The timer/counter can be clocked from the peripheral clock (clkPER) and from the event system. Figure 15-2 shows the
clock and event selection.
Figure 15-2. Clock selection.
clkPER
Common
Prescaler
clkPER /
2{0,...,15}
clkPER /
{1,2,4,8,64,256,1024}
Event
System
events
event channels
CLKSEL
CNT
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The peripheral clock (clkPER) is fed into the common prescaler (common for all timer/counters in a device). A selection of
prescaler outputs from 1 to 1/1024 is directly available. In addition, the whole range of time prescalings from 1 to 215 is
available through the event system.
The clock selection (CLKSEL) selects one of the clock prescaler outputs or an event channel for the high-byte counter
(HCNT) and low-byte counter (LCNT). By using the event system, any event source, such as an external clock signal, on
any I/O pin can be used as the clock input.
By default, no clock input is selected, and the counters are not running.
15.5
Counter Operation
The counters will always count in single-slope mode. Each counter counts down for each clock cycle until it reaches
BOTTOM, and then reloads the counter with the period register value at the following clock cycle.
Figure 15-3. Counter operation.
CNT written
MAX
"reload"
TOP
CNT
BOTTOM
As shown in Figure 15-3, the counter can change the counter value while running. The write access has higher priority
than the count clear, and reloads and will be immediate.
15.5.1 Changing the Period
The counter period is changed by writing a new TOP value to the period register. Since the counter is counting down, the
period register can be written at any time without affecting the current period, as shown in Figure 15-4 on page 188. This
prevents wraparound and generation of odd waveforms.
Figure 15-4. Changing the period.
MAX
"reload"
"write"
CNT
BOTTOM
New TOP written to
PER that is higher
than current CNT
15.6
New TOP written to
PER that is lower
than current CNT
Compare Channel
Each compare channel continuously compares the counter value with the CMPx register. If CNT equals CMPx, the
comparator signals a match. For the low-byte timer/counter, the match will set the compare channel's interrupt flag at the
next timer clock cycle, and the event and optional interrupt is generated. The high-byte timer/counter does not have
compare interrupt/event.
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15.6.1 Waveform Generation
The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform
visible on the connected port pin, the following requirements must be fulfilled:
1.
The compare channels to be used must be enabled. This will override the corresponding port pin output register.
2.
The direction for the associated port pin must be set to output.
Inverted waveform output can be achieved by setting invert I/O on the port pin. Refer to “I/O Ports” on page 139 for more
details.
15.6.2 Single-slope PWM Generation
For PWM generation, the period (T) is controlled by the PER register, while the CMPx registers control the duty cycle of
the waveform generator (WG) output. Figure 15-5 on page 189 shows how the counter counts from TOP to BOTTOM,
and then restarts from TOP. The WG output is set on the compare match between the CNT and CMPx registers, and
cleared at BOTTOM.
Figure 15-5. Single-slope pulse width modulation.
Period (T)
CMPx=TOP
CMPx=BOT
"match"
MAX
TOP
CNT
CMPx
BOTTOM
WG Output
The PER register defines the PWM resolution. The minimum resolution is two bits (PER=0x0003), and the maximum
resolution is eight bits (PER=MAX).
The following equation is used to calculate the exact resolution for a single-slope PWM (RPWM_SS) waveform:
PER + 1 -
R PWM_SS = log
-------------------------------log 2
The single, slow PWM frequency (fPWM_SS) depends on the period setting (PER) and the peripheral clock frequency
(fPER), and it is calculated by using the following equation:
f PER
f PWM_SS = ---------------------------N PER + 1
where N represents the prescaler divider used (1, 2, 4, 8, 64, 256, 1024, or event channel n).
15.6.3 Port Override for Waveform Generation
To make the waveform generation available on the port pins, the corresponding port pin direction must be set as output.
The timer/counter will override the port pin values when the CMP channel is enabled (LCMPENx/HCMPENx).
Figure 15-6 on page 190 shows the port override for the low- and high-byte timer/counters. For the low-byte
timer/counter, CMP channels A to D will override the output value (OUTxn) of port pins 0 to 3 on the corresponding port
pins (Pxn). For the high-byte timer/counter, CMP channels E to H will override port pins 4 to 7. Enabling inverted I/O on
the port pin (INVENxn) inverts the corresponding WG output.
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Figure 15-6. Port override for low- and high-byte timer/counters.
OUT
OCx
Waveform
LCMPENx /
HCMPENx
15.7
INVEN
Interrupts and Events
The timer/counters can generate interrupts and events. The counter can generate an interrupt on underflow, and each
CMP channel for the low-byte counter has a separate compare interrupt.
Events will be generated for all conditions that can generate interrupts. For details on event generation and available
events, refer to “Event System” on page 70.
15.8
DMA Support
Timer/counter underflow and compare interrupt flags can trigger a DMA transaction. The acknowledge condition that
clears the flag/request is listed in Table 15-1 on page 190.
Table 15-1. DMA request sources.
15.9
Request
Acknowledge
LUNFIF
DMAC writes to LCNT
DMAC writes to LPER
HUNFIF
DMAC writes to HCNT
DMAC writes to HPER
CCIF{D,C,B,A}
DMAC access of
LCMP{D,C,B,A}
Comment
Output compare operation
Timer/Counter Commands
A set of commands can be given to the timer/counter by software to immediately change the state of the module. These
commands give direct control of the update, restart, and reset signals.
The software can force a restart of the current waveform period by issuing a restart command. In this case the counter,
direction, and all compare outputs are set to zero.
A reset command will set all timer/counter registers to their initial values. A reset can only be given when the
timer/counter is not running (OFF).
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15.10 Register description
15.10.1 CTRLA – Control register A
Bit
7
6
5
4
+0x00
–
–
–
–
3
2
Read/Write
R
R
R
R
R/W
Initial Value
0
0
0
0
0
1
0
R/W
R/W
R/W
0
0
0
CLKSEL[3:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:0 – CLKSEL[3:0]: Clock Select
These bits select clock source for the timer/counter according to Table 15-2 on page 191. The clock select is identical for both high- and low-byte timer/counters.
Table 15-2. Clock select.
CLKSEL[3:0]
Group configuration
Description
0000
OFF
None (i.e., timer/counter in OFF state)
0001
DIV1
Prescaler: ClkPER
0010
DIV2
Prescaler: ClkPER/2
0011
DIV4
Prescaler: ClkPER/4
0100
DIV8
Prescaler: ClkPER/8
0101
DIV64
Prescaler: ClkPER/64
0110
DIV256
Prescaler: ClkPER/256
0111
DIV1024
Prescaler: ClkPER/1024
1nnn
EVCHn
Event channel n, n= [0,...,7]
15.10.2 CTRLB – Control register B
Bit
7
6
5
4
3
2
1
0
HCMPEND
HCMPENC
HCMPENB
HCMPENA
LCMPEND
LCMPENC
LCMPENB
LCMPENA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x01
Bit 7:0 – HCMPENx / LCMPENx: High/Low Byte Compare Enable x
Setting these bits will enable the compare output and override the port output register for the corresponding OCn
output pin.
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15.10.3 CTRLC – Control register C
Bit
+0x02
7
6
5
4
3
2
1
0
HCMPD
HCMPC
HCMPB
HCMPA
LCMPD
LCMPC
LCMPB
LCMPA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value
These bits allow direct access to the waveform generator's output compare value when the timer/counter is OFF.
This is used to set or clear the WG output value when the timer/counter is not running.
15.10.4 CTRLE – Control register E
Bit
7
6
5
4
3
2
1
0
+0x04
–
–
–
–
–
–
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
BYTEM[1:0]
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1:0 – BYTEM[1:0]: Byte Mode
These bits select the timer/counter operation mode according to Table 15-3 on page 192.
Table 15-3. Byte mode.
BYTEM[1:0]
Group configuration
Description
00
NORMAL
01
BYTEMODE
Upper byte of the counter (HCNT) will be set to zero after each counter clock.
10
SPLITMODE
Timer/counter is split into two eight-bit timer/counters (timer/counter type 2)
11
–
Timer/counter is set to normal mode (timer/counter type 0)
Reserved
15.10.5 INTCTRLA – Interrupt Enable register A
Bit
7
6
5
4
3
2
1
0
+0x06
–
–
–
–
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
HUNFINTLVL[1:0]
LUNFINTLVL[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – HUNFINTLVL[1:0]: High-byte Timer Underflow Interrupt Level
These bits enable the high-byte timer underflow interrupt and select the interrupt level, as described in “Interrupts
and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will be triggered when HUNFIF in the INTFLAGS register is set.
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Bit 1:0 – LUNFINTLVL[1:0]: Low-byte Timer Underflow Interrupt Level
These bits enable the low-byte timer underflow interrupt and select the interrupt level, as described in “Interrupts
and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will be triggered when LUNFIF in the INTFLAGS register is set.
15.10.6 INTCTRLB – Interrupt Enable register B
Bit
7
6
5
4
3
2
1
0
+0x07
LCMPDINTLVL[1:0]
LCMPCINTLVL[1:0]
LCMPBINTLVL[1:0]
LCMPAINTLVL[1:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – LCMPxINTLVL[1:0]: Low-byte Compare x Interrupt Level
These bits enable the low-byte timer compare interrupt and select the interrupt level, as described in “Interrupts
and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will be triggered when
LCMPxIF in the INTFLAGS register is set.
15.10.7 CTRLF – Control register F
Bit
7
6
5
4
+0x08
–
–
–
–
3
2
1
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
CMD[1:0]
0
CMDEN[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – CMD[1:0]: Timer/Counter Command
These command bits are used for software control of timer/counter update, restart, and reset. The command bits
are always read as zero. The CMD bits must be used together with CMDEN.
Table 15-4. Command selections.
CMD
Group configuration
00
NONE
01
–
10
RESTART
11
RESET
Description
None
Reserved
Force restart
Force hard reset (ignored if T/C is not in OFF state)
Bit 1:0 – CMDEN[1:0]: Command Enable
These bits are used to indicate for which timer/counter the command (CMD) is valid
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Table 15-5. Command selections.
CMD
Group configuration
Description
00
–
01
LOW
Command valid for low-byte T/C
10
HIGH
Command valid for high-byte T/C
11
BOTH
Command valid for both low-byte and high-byte T/C
Reserved
15.10.8 INTFLAGS – Interrupt Flag register
Bit
+0x0C
7
6
5
4
3
2
1
0
LCMPDIF
LCMPCIF
LCMPBIF
LCMPAIF
–
–
HUNFIF
LUNFIF
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:4 – LCMPxIF: Compare Channel x Interrupt Flag
The compare interrupt flag (LCMPxIF) is set on a compare match on the corresponding CMP channel.
For all modes of operation, LCMPxIF will be set when a compare match occurs between the count register (LCNT)
and the corresponding compare register (LCMPx). The LCMPxIF is automatically cleared when the corresponding
interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
Bit 3:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – HUNFIF: High-byte Timer Underflow Interrupt Flag
HUNFIF is set on a BOTTOM (underflow) condition. This flag is automatically cleared when the corresponding
interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
Bit 0 – LUNFIF: Low-byte Timer Underflow Interrupt Flag
LUNFIF is set on a BOTTOM (underflow) condition. This flag is automatically cleared when the corresponding
interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
15.10.9 LCNT – Low-byte Count register
Bit
7
6
5
4
+0x20
3
2
1
0
LCNT[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – LCNT[7:0]
LCNT contains the eight-bit counter value for the low-byte timer/counter. The CPU and DMA write accesses have
priority over count, clear, or reload of the counter.
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15.10.10 HCNT – High-byte Count register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x21
HCNT[7:0]
Bit 7:0 – HCNT[7:0]
HCNT contains the eight-bit counter value for the high-byte timer/counter. The CPU and DMA write accesses have
priority over count, clear, or reload of the counter.
15.10.11 LPER – Low-byte Period register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
+0x27
LPER[7:0]
Bit 7:0 – LPER[7:0]
LPER contains the eight-bit period value for the low-byte timer/counter.
15.10.12 HPER – High-byte Period register
Bit
7
6
5
4
+0x26
HPER[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – HPER[7:0]
HPER contains the eight-bit period for the high-byte timer/counter.
15.10.13 LCMPx – Low-byte Compare register x
Bit
7
6
5
4
3
2
1
0
LCMPx[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – LCMPx[7:0], x =[A, B, C, D]
LCMPx contains the eight-bit compare value for the low-byte timer/counter.
These registers are all continuously compared to the counter value. Normally, the outputs from the comparators
are then used for generating waveforms.
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15.10.14 HCMPx – High-byte Compare register x
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
HCMPx[7:0]
Bit 7:0 – HCMPx[7:0], x =[A, B, C, D]
HCMPx contains the eight-bit compare value for the high-byte timer/counter.
These registers are all continuously compared to the counter value. Normally the outputs from the comparators
are then used for generating waveforms.
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15.11 Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
+0x00
CTRLA
–
–
–
–
+0x01
CTRLB
HCMPDEN
HCMPCEN
HCMPBEN
HCMPAEN
LCMPDEN
LCMPCEN
LCMPBEN
LCMPAEN
191
+0x02
CTRLC
HCMPD
HCMPC
HCMPB
HCMPA
LCMPD
LCMPC
LCMPB
LCMPA
192
+0x05
Reserved
+0x04
CTRLE
+0x05
Reserved
+0x06
INTCTRLA
+0x07
INTCTRLB
+0x08
Reserved
–
–
–
–
+0x09
CTRLF
–
–
–
–
+0x0A
Reserved
–
–
–
–
–
–
–
–
+0x0B
Reserved
–
–
–
–
–
–
–
–
+0x0C
INTFLAGS
LCMPDIF
LCMPCIF
LCMPBIF
LCMPAIF
–
–
HUNFIF
LUNFIF
+0x0D
Reserved
–
–
–
–
–
–
–
–
+0x0E
Reserved
–
–
–
–
–
–
–
–
+0x0F
Reserved
–
–
–
–
–
–
–
–
+0x10 to
+0x1F
Reserved
–
–
–
–
–
–
–
–
+0x20
LCNT
Low-byte Timer/Counter Count Register
195
+0x21
HCNT
High-byte Timer/Counter Count Register
195
+0x22 to
+0x25
Reserved
+0x26
LPER
Low-byte Timer/Counter Period Register
195
+0x27
HPER
High-byte Timer/Counter Period Register
196
+0x28
LCMPA
Low-byte Compare Register A
195
+0x29
HCMPA
High-byte Compare Register A
196
+0x2A
LCMPB
Low-byte Compare Register B
195
+0x2B
HCMPB
High-byte Compare Register B
196
+0x2C
LCMPC
Low-byte Compare Register C
195
+0x02D
HCMPC
High-byte Compare Register C
196
+0x2E
LCMPD
Low-byte Compare Register D
195
+0x2F
HCMPD
High-byte Compare Register D
196
+0x30 to
+0x3F
Reserved
–
–
LCMPDINTLVL[1:0]
–
–
–
–
–
–
LCMPCINTLVL[1:0]
–
–
–
–
Bit 3
Bit 2
Bit 1
Bit 0
CLKSEL[3:0]
Page
191
BYTEM[1:0]
192
HUNFINTLVL[1:0]
LUNFINTLVL[1:0]
192
LCMPBINTLVL[1:0]
LCMPAINTLVL[1:0]
193
–
–
–
CMD[1:0]
–
–
–
CMDEN[1:0]
–
–
–
–
193
194
–
–
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15.12 Interrupt vector summary
Table 15-6. Timer/counter interrupt vectors and their word offset addresses.
Offset
Source
Interrupt description
0x00
LUNF_vect
Low-byte Timer/counter underflow interrupt vector offset
0x02
HUNF_vect
High-byte Timer/counter underflow interrupt vector offset
0x4
LCMPA_vect
Low-byte Timer/counter compare channel A interrupt vector offset
0x6
LCMPB_vect
Low-byte Timer/counter compare channel B interrupt vector offset
0x8
LCMPC_vect
Low-byte Timer/counter compare channel C interrupt vector offset
0x0A
LCMPD_vect
Low-byte Timer/counter compare channel D interrupt vector offset
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16.
AWeX – Advanced Waveform Extension
16.1
Features
Waveform output with complementary output from each compare channel
Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
Pattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
Event controlled fault protection for instant and predictable fault triggering
16.2
Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Figure 16-1. Advanced waveform extention and closely related peripherals (grey).
AWeX
Pattern
Generation
Timer/Counter 0
WG
Channel A
DTI
Channel A
WG
Channel B
DTI
Channel B
Px0
Px1
Px2
Port
Override
WG
Channel C
DTI
Channel C
WG
Channel D
DTI
Channel D
Event
System
Fault
Protection
Px3
Px4
Px5
Px6
Px7
As shown in Figure 16-1 on page 199, each of the waveform generator outputs from timer/counter 0 are split into a
complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time
insertion (DTI) unit that generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-
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time insertion between LS and HS switching. The DTI output will override the normal port value according to the port
override setting. Refer to “I/O Ports” on page 139 for more details.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
16.3
Port Override
The port override logic is common for all the timer/counter extensions. Figure 16-2 on page 201 shows a schematic
diagram of the port override logic. When the dead-time enable (DTIENx) bit is set, the timer/counter extension takes
control over the pin pair for the corresponding channel. Given this condition, the output override enable (OOE) bits take
control over the CCxEN bits.
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Figure 16-2. Timer/counter extensions and port override logic.
CWCM
WG 0A
OUT0
DTI
CCAEN
LS
WG 0A
Channel
A
HS
DTICCAEN
OUTOVEN1
CCBEN
OUT1
WG 0C
OUT2
CCCEN
LS
WG 0B
Channel
B
HS
CCDEN
OUT4
CCAEN
Channel
C
HS
WG 1B
Px2
OC0C
OCBLS
INVEN2
DTICCBEN
WG 1A
WG 0C
Px1
OC0B
OCAHS
OUTOVEN3
OUT3
LS
INVEN1
OUTOVEN2
WG 0D
DTI
INVEN0
OUTOVEN0
WG 0B
DTI
Px0
OC0A
OCALS
INVEN3
Px3
OC0D
OCBHS
Px4
OC1A
OCCLS
INVEN4
OUTOVEN4
DTICCCEN
OUTOVEN5
CCBEN
INVEN5
Px5
OC1B
OCCHS
OUT5
OUT6
Px6
OCDLS
DTI
"0"
LS
WG 0D
Channel
D
HS
OUTOVEN6
DTICCDEN
OUTOVEN7
"0"
INVEN7
Px7
OUT7
16.4
INVEN6
OCDHS
Dead-time Insertion
The dead-time insertion (DTI) unit generates OFF time where the non-inverted low side (LS) and inverted high side (HS)
of the WG output are both low. This OFF time is called dead time, and dead-time insertion ensures that the LS and HS
never switch simultaneously.
The DTI unit consists of four equal dead-time generators, one for each compare channel in timer/counter 0. Figure 16-3
on page 202 shows the block diagram of one DTI generator. The four channels have a common register that controls the
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dead time. The high side and low side have independent dead-time setting, and the dead-time registers are double
buffered.
In clear override mode the operation will resume when the fault condition is cleared, and pattern generation is used, or
the write strobe goes high to the awex.
In pattern generation mode, the same waveform will be output on all channels until the next update, usually setting up a
short-circuit on the outside. If neither of these happens the normal operation will resume 1-2 cycles early
Figure 16-3. Dead-time generator block diagram.
BV
DTLSBUF
BV
DTHSBUF
DTHS
DTLS
Dead Time Generator
LOAD
EN
Counter
=0
"DTLS"
WG output
D
Q
(To PORT)
"DTHS"
Edge Detect
(To PORT)
As shown in Figure 16-4 on page 202, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle,
until it reaches zero. A nonzero counter value will force both the low side and high side outputs into their OFF state.
When a change is detected on the WG output, the dead-time counter is reloaded according to the edge of the input. A
positive edge initiates a counter reload of the DTLS register, and a negative edge a reload of DTHS register.
Figure 16-4. Dead-time generator timing diagram.
"dti_cnt"
T
tP
tDTILS
tDTIHS
"WG output"
"DTLS"
"DTHS"
16.5
Pattern Generation
The pattern generator unit reuses the DTI registers to produce a synchronized bit pattern across the port it is connected
to. In addition, the waveform generator output from compare channel A (CCA) can be distributed to and override all the
port pins. These features are primarily intended for handling the commutation sequence in brushless DC motor (BLDC)
and stepper motor applications. A block diagram of the pattern generator is shown in “Pattern generator block diagram.”
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on page 203. For each port pin where the corresponding OOE bit is set, the multiplexer will output the waveform from
CCA.
Figure 16-5. Pattern generator block diagram.
Timer/Counter 0 (TCx0)
UPDATE
BV
DTLSBUF
EN
OUTOVEN
BV
CCA WG output
1 to 8
Expand
DTHSBUF
EN
OUTx
Px[7:0]
As with the other timer/counter double buffered registers, the register update is synchronized to the UPDATE condition
set by the waveform generation mode. If the synchronization provided is not required by the application, the application
code can simply access the DTIOE and PORTx registers directly.
The pin directions must be set for any output from the pattern generator to be visible on the port.
16.6
Fault Protection
The fault protection feature enables fast and deterministic action when a fault is detected. The fault protection is event
controlled. Thus, any event from the event system can be used to trigger a fault action, such as over-current indication
from analog comparator or ADC measurements.
When fault protection is enabled, an incoming event from any of the selected event channels can trigger the event action.
Each event channel can be separately enabled as a fault protection input, and the specified event channels will be ORed
together, allowing multiple event sources to be used for fault protection at the same time.
16.6.1 Fault Actions
When a fault is detected, the direction clear action will clear the direction (DIR) register in the associated port, setting all
port pins as tri-stated inputs.
The fault detection flag is set, the timer/counter’s error interrupt flag is set, and the optional interrupt is generated.
There is maximum of two peripheral clock cycles from when an event occurs in a peripheral until the fault protection
triggers the event action. Fault protection is fully independent of the CPU and DMA, but requires the peripheral clock to
run.
16.6.2 Fault Restore Modes
How the AWeX and timer/counter return from the fault state to normal operation after a fault, when the fault condition is
no longer active, can be selected from one of two different modes:
In latched mode, the waveform output will remain in the fault state until the fault condition is no longer active and
the fault detect flag has been cleared by software. When both of these conditions are met, the waveform output will
return to normal operation at the next UPDATE condition.
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In cycle-by-cycle mode the waveform output will remain in the fault state until the fault condition is no longer active.
When this condition is met, the waveform output will return to normal operation at the next UPDATE condition.
When returning from a fault state the DIR[7:0] bits corresponding to the enabled DTI channels are restored. OUTOVEN is
unaffected by the fault except that writing to the register from software is blocked.
The UPDATE condition used to restore normal operation is the same as the one in the timer/counter.
16.6.3 Change Protection
To avoid unintentional changes in the fault protection setup, all the control registers in the AWeX extension can be
protected by writing the corresponding lock bit in the advanced waveform extension lock register. For more details, refer
to “I/O Memory Protection” on page 25 and “AWEXLOCK – Advanced Waveform Extension Lock register” on page 46.
When the lock bit is set, control register A, the output override enable register, and the fault detection event mask register
cannot be changed.
To avoid unintentional changes in the fault event setup, it is possible to lock the event system channel configuration by
writing the corresponding event system lock register. For more details, refer to “I/O Memory Protection” on page 25 and
“EVSYSLOCK – Event System Lock register” on page 46.
16.6.4 On-Chip Debug
When fault detection is enabled, an on-chip debug (OCD) system receives a break request from the debugger, which will
by default function as a fault source. When an OCD break request is received, the AWeX and corresponding
timer/counter will enter a fault state, and the specified fault action will be performed.
After the OCD exits from the break condition, normal operation will be started again. In cycle-by-cycle mode, the
waveform output will start on the first UPDATE condition after exit from break, while in latched mode, the fault condition
flag must be cleared in software before the output will be restored. This feature guarantees that the output waveform
enters a safe state during a break.
It is possible to disable this feature.
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16.7
Register Description
16.7.1 CTRL – Control register
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
PGM
CWCM
DTICCDEN
DTICCCEN
DTICCBEN
DTICCAEN
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 5 – PGM: Pattern Generation Mode
Setting this bit enables the pattern generation mode. This will override the DTI, and the pattern generation reuses
the dead-time registers for storing the pattern.
Bit 4 – CWCM: Common Waveform Channel Mode
If this bit is set, the CC channel A waveform output will be used as input for all the dead-time generators. CC channel B, C, and D waveforms will be ignored.
Bit 3:0 – DTICCxEN: Dead-Time Insertion CCx Enable
Setting these bits enables the dead-time generator for the corresponding CC channel. This will override the
timer/counter waveform outputs.
16.7.2 FDEMASK – Fault Detect Event Mask register
Bit
7
6
5
+0x02
4
3
2
1
0
FDEVMASK[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:0 – FDEVMASK[7:0]: Fault Detect Event Mask
These bits enable the corresponding event channel as a fault condition input source. Events from all event channels will be ORed together, allowing multiple sources to be used for fault detection at the same time. When a fault
is detected, the fault detect flag (FDF) is set and the fault detect action (FDACT) will be performed.
16.7.3 FDCTRL - Fault Detection Control register
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
FDDBD
–
FDMODE
Read/Write
R
R
R
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
FDACT[1:0]
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – FDDBD: Fault Detection on Debug Break Detection
By default, when this bit is cleared and fault protection is enabled, and OCD break request is treated as a fault.
When this bit is set, an OCD break request will not trigger a fault condition.
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Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written.
Bit 2 – FDMODE: Fault Detection Restart Mode
This bit sets the fault protection restart mode. When this bit is cleared, latched mode is used, and when it is set,
cycle-by-cycle mode is used.
In latched mode, the waveform output will remain in the fault state until the fault condition is no longer active and
the FDF has been cleared by software. When both conditions are met, the waveform output will return to normal
operation at the next UPDATE condition.
In cycle-by-cycle mode, the waveform output will remain in the fault state until the fault condition is no longer
active. When this condition is met, the waveform output will return to normal operation at the next UPDATE
condition.
Bit 1:0 – FDACT[1:0]: Fault Detection Action
These bits define the action performed, according to Table 16-1, when a fault condition is detected.
Table 16-1. Fault actions.
FDACT[1:0]
Group configuration
Description
00
NONE
01
–
Reserved
10
–
Reserved
11
CLEARDIR
None (fault protection disabled)
Clear all direction (DIR) bits which correspond to the enabled DTI
channel(s); i.e., tri-state the outputs
16.7.4 STATUS – Status register
Bit
7
6
5
4
3
2
1
0
+0x04
–
–
–
–
–
FDF
DTHSBUFV
DTLSBUFV
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – FDF: Fault Detect Flag
This flag is set when a fault detect condition is detected; i.e., when an event is detected on one of the event channels enabled by FDEVMASK. This flag is cleared by writing a one to its bit location.
Bit 1 – DTHSBUFV: Dead-time High Side Buffer Valid
If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied into the DTLS register on the next UPDATE condition. If this bit is zero, no action will be taken. The connected timer/counter unit’s
lock update (LUPD) flag also affects the update for dead-time buffers.
Bit 0 – DTLSBUFV: Dead-time Low Side Buffer Valid
If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied into the DTHS
register on the next UPDATE condition. If this bit is zero, no action will be taken. The connected timer/counter
unit's lock update (LUPD) flag also affects the update for dead-time buffers.
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16.7.5 DTBOTH – Dead-time Concurrent Write to Both Sides
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x06
DTBOTH[7:0]
Bit 7:0 – DTBOTH: Dead-time Both Sides
Writing to this register will update the DTHS and DTLS registers at the same time (i.e., at the same I/O write
access).
16.7.6 DTBOTHBUF – Dead-time Concurrent Write to Both Sides Buffer register
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
+0x07
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
DTBOTHBUF[7:0]
Bit 7:0 – DTBOTHBUF: Dead-time Both Sides Buffer
Writing to this memory location will update the DTHSBUF and DTLSBUF registers at the same time (i.e., at the
same I/O write access).
16.7.7 DTLS – Dead-time Low Side register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x08
DTLS[7:0]
Bit 7:0 – DTLS: Dead-time Low Side
This register holds the number of peripheral clock cycles for the dead-time low side.
16.7.8 DTHS – Dead-time High Side register
Bit
7
6
5
4
+0x09
3
2
1
0
DTHS[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
2
1
0
Bit 7:0 – DTHS: Dead-time High Side
This register holds the number of peripheral clock cycles for the dead-time high side.
16.7.9 DTLSBUF – Dead-time Low Side Buffer register
Bit
7
6
5
+0x0A
4
3
DTLSBUF[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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Bit 7:0 – DTLSBUF: Dead-time Low Side Buffer
This register is the buffer for the DTLS register. If double buffering is used, valid content in this register is copied to
the DTLS register on an UPDATE condition.
16.7.10 DTHSBUF – Dead-time High Side Buffer register
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
+0x0B
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
DTHSBUF[7:0]
Bit 7:0 – DTHSBUF: Dead-time High Side Buffer
This register is the buffer for the DTHS register. If double buffering is used, valid content in this register is copied to
the DTHS register on an UPDATE condition.
16.7.11 OUTOVEN – Output Override Enable register
Bit
7
6
5
4
Read/Write
R/W(1)
R/W(1)
R/W(1)
R/W(1)
Initial Value
0
0
0
0
+0x0C
Note:
3
2
1
0
R/W(1)
R/W(1)
R/W(1)
R/W(1)
0
0
0
0
OUTOVEN[7:0]
1.
Can be written only if the fault detect flag (FDF) is zero.
Bit 7:0 – OUTOVEN[7:0]: Output Override Enable
These bits enable override of the corresponding port output register (i.e., one-to-one bit relation to pin position).
The port direction is not overridden.
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16.8
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
CTRL
–
–
PGM
CWCM
DTICDAEN
DTICCCEN
DTICCBEN
DTICCAEN
205
+0x01
Reserved
–
–
–
–
–
–
–
–
+0x02
FDEMASK
+0x03
FDCTRL
–
–
–
FDDBD
–
FDMODE
+0x04
STATUS
–
–
–
–
–
FDF
DTBHSV
DTBLSV
+0x05
Reserved
–
–
–
–
–
–
–
–
+0x06
DTBOTH
DTBOTH[7:0]
207
+0x07
DTBOTHBUF
DTBOTHBUF[7:0]
207
+0x08
DTLS
DTLS[7:0]
207
+0x09
DTHS
DTHS[7:0]
207
+0x0A
DTLSBUF
DTLSBUF[7:0]
207
+0x0B
DTHSBUF
DTHSBUF[7:0]
207
+0x0C
OUTOVEN
OUTOVEN[7:0]
208
FDEVMASK[7:0]
205
FDACT[1:0]
205
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17.
Hi-Res – High-Resolution Extension
17.1
Features
Increases waveform generator resolution up to 8x (3 bits)
Supports frequency, single-slope PWM, and dual-slope PWM generation
Supports the AWeX when this is used for the same timer/counter
17.2
Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled. Refer to “System Clock Selection and Prescalers” on page 86 for more details.
Figure 17-1. Timer/counter operation with hi-res extension enabled.
PER[15:2]
0
CNT[15:2]
clkPER
0
=
=0
BOTTOM
=
TOP
HiRes
AWeX
" match"
2
CCx[15:2]
clkPER4
Waveform
Generation
2
[1:0]
Dead - Time
Insertion
Pattern
Generation
Fault
Protection
Pxn
2
CCxBUF[15:0]
Time /Counter
When the hi-res extension is enabled, the timer/counter must run from a non-prescaled peripheral clock. The
timer/counter will ignore its two least-significant bits (lsb) in the counter, and counts by four for each peripheral clock
cycle. Overflow/underflow and compare match of the 14 most-significant bits (msb) is done in the timer/counter. Count
and compare of the two lsb is handled and compared in the hi-res extension running from the peripheral 4x clock.
The two lsb of the timer/counter period register must be set to zero to ensure correct operation. If the count register is
read from the application code, the two lsb will always be read as zero, since the timer/counter run from the peripheral
clock. The two lsb are also ignored when generating events.
When the hi-res plus feature is enabled, the function is the same as with the hi-res extension, but the resolution will
increase by eight instead of four. This also means that the 3 lsb are handled by the hi-res extension instead of 2 lsb, as
when only hi-res is enabled. The extra resolution is achieved by counting on both edges of the peripheral 4x clock.
The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than
four will have no visible output.
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17.3
Register Description
17.3.1 CTRLA – Control register A
Bit
7
6
5
4
3
2
+0x00
–
–
–
–
–
HRPLUS
1
0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
HREN[1:0]
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2 – HRPLUS: High Resolution Plus
Setting this bit enables high resolution plus. Hi-res plus is the same as hi-res, but will increase the resolution by
eight (3 bits) instead of four.
The extra resolution is achieved by operating at both edges of the peripheral 4x clock.
Bit 1:0 – HREN[1:0]: High Resolution Enable
These bits enables the high-resolution mode for a timer/counter according to Table 17-1.
Setting one or both HREN bits will enable high-resolution waveform generation output for the entire general purpose I/O port. This means that both timer/counters connected to the same port must enable hi-res if both are used
for generating PWM or FRQ output on pins.
Table 17-1. High resolution enable.
HREN[1:0]
17.4
High resolution enabled
00
None
01
Timer/counter 0
10
Timer/counter 1
11
Both timer/counters
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
+0x00
CTRLA
–
–
–
–
–
HRPLUS
Bit 1
Bit 0
HREN[1:0]
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18.
RTC – Real-Time Counter
18.1
Features
16-bit resolution
Selectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
Programmable 10-bit clock prescaling
One compare register
One period register
Clear counter on period overflow
Optional interrupt/event on overflow and compare match
18.2
Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum time-out period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 18-1. Real-time counter overview.
External Clock
TOSC1
TOSC2
32.768kHz Crystal Osc
32.768kHz Int. Osc
DIV32
DIV32
32kHz int ULP (DIV32)
PER
RTCSRC
clkRTC
10-bit
prescaler
=
TOP/
Overflow
=
”match”/
Compare
CNT
COMP
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18.2.1 Clock Domains
The RTC is asynchronous, operating from a different clock source independently of the main system clock and its
derivative clocks, such as the peripheral clock. For control and count register updates, it will take a number of RTC clock
and/or peripheral clock cycles before an updated register value is available in a register or until a configuration change
has effect on the RTC. This synchronization time is described for each register. Refer to “RTCCTRL – RTC Control
register” on page 92 for selecting the asynchronous clock source for the RTC.
18.2.2 Interrupts and Events
The RTC can generate both interrupts and events. The RTC will give a compare interrupt and/or event at the first count
after the counter value equals the Compare register value. The RTC will give an overflow interrupt request and/or event
at the first count after the counter value equals the Period register value. The overflow will also reset the counter value to
zero.
Due to the asynchronous clock domain, events will be generated only for every third overflow or compare match if the
period register is zero. If the period register is one, events will be generated only for every second overflow or compare
match. When the period register is equal to or above two, events will trigger at every overflow or compare match, just as
the interrupt request.
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18.3
Register Descriptions
18.3.1 CTRL – Control register
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
–
–
–
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PRESCALER[2:0]
Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 2:0 – PRESCALER[2:0]: Clock Prescaling factor
These bits define the prescaling factor for the RTC clock according to Table 18-1 on page 214.
Table 18-1. Real-time counter clock prescaling factor.
PRESCALER[2:0]
Group configuration
RTC clock prescaling
000
OFF
No clock source, RTC stopped
001
DIV1
RTC clock / 1 (no prescaling)
010
DIV2
RTC clock / 2
011
DIV8
RTC clock / 8
100
DIV16
RTC clock / 16
101
DIV64
RTC clock / 64
110
DIV256
RTC clock / 256
111
DIV1024
RTC clock / 1024
18.3.2 STATUS – Status register
Bit
7
6
5
4
3
2
1
0
+0x01
–
–
–
–
–
–
–
SYNCBUSY
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CNT, CTRL, PER, or COMP register is busy synchronizing between the RTC clock and
system clock domains after writing any of these registers or when waking up from a sleep mode where the peripheral clock is stopped. This flag is automatically cleared when the synchronisation is complete.
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18.3.3 INTCTRL – Interrupt Control register
Bit
7
6
5
4
+0x02
–
–
–
–
COMPINTLVL[1:0]
3
2
1
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
OVFINTLVL[1:0]
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Enable
These bits enable the RTC compare match interrupt and select the interrupt level, as described in “Interrupts and
Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will trigger when COMPIF in the
INTFLAGS register is set.
Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Enable
These bits enable the RTC overflow interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will trigger when OVFIF in the
INTFLAGS register is set.
18.3.4 INTFLAGS – Interrupt Flag register
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
–
–
–
COMPIF
OVFIF
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. It is cleared automatically when the RTC
compare match interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. It is cleared automatically when the RTC overflow interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
18.3.5 TEMP – Temporary register
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x04
TEMP[7:0]
Bit 7:0 – TEMP[7:0]: Temporary bits
This register is used for 16-bit access to the counter value, compare value, and TOP value registers. The low byte
of the 16-bit register is stored here when it is written by the CPU. The high byte of the 16-bit register is stored when
the low byte is read by the CPU. For more details, refer to “The combined EIND + Z register.” on page 12.
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18.3.6 CNTL – Counter register Low
The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT counts positive clock edges on the prescaled
RTC clock. Reading and writing 16-bit values requires special attention. Refer to “The combined EIND + Z register.” on
page 12 for details.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the SYNCBUSY flag in the
“STATUS – Status register” on page 214 is cleared before writing to this register or reading the register after waking up
from a sleep mode where the peripheral clock is stopped
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
+0x08
CNT[7:0]
Bit 7:0 – CNT[7:0]: Counter Value low byte
These bits hold the LSB of the 16-bit real-time counter value.
18.3.7 CNTH – Counter register High
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x09
CNT[15:8]
Bit 7:0 – CNT[15:8]: Counter Value highbyte
These bits hold the MSB of the 16-bit real-time counter value.
18.3.8 PERL – Period register Low
The PERH and PERL register pair represents the 16-bit value, PER. PER is constantly compared with the counter value
(CNT). A match will set OVFIF in the INTFLAGS register and clear CNT. Reading and writing 16-bit values requires
special attention. Refer to “The combined EIND + Z register.” on page 12 for details.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the SYNCBUSY flag in the
“STATUS – Status register” on page 214 is cleared before writing to this register.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
3
2
1
0
+0x0A
PER[7:0]
Bit 7:0 – PER[7:0]: Period low byte
These bits hold the LSB of the 16-bit RTC TOP value.
18.3.9 PERH – Period register High
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
+0x0B
PER[15:8]
Bits 7:0 – PER[15:8]: Period high byte
These bits hold the MSB of the 16-bit RTC TOP value.
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18.3.10 COMPL – Compare register Low
The COMPH and COMPL register pair represent the 16-bit value, COMP. COMP is constantly compared with the
counter value (CNT). A compare match will set COMPIF in the INTFLAGS register. Reading and writing 16-bit values
requires special attention. Refer “The combined EIND + Z register.” on page 12 for details.
Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles
from updating the register until this has an effect. Application software needs to check that the SYNCBUSY flag in the
“STATUS – Status register” on page 214 is cleared before writing to this register.
If the COMP value is higher than the PER value, no RTC compare match interrupt requests or events will ever be
generated.
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
3
2
1
0
+0x0C
COMP[7:0]
Bit 7:0 – COMP[7:0]: Compare value low byte
These bits hold the LSB of the 16-bit RTC compare value.
18.3.11 COMPH – Compare register High
Bit
7
6
5
4
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x0D
COMP[15:8]
Bit 7:0 – COMP[15:8]: Compare value high byte
These bits hold the MSB of the 16-bit RTC compare value.
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18.4
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
+0x00
CTRL
–
–
–
–
–
+0x01
STATUS
–
–
–
–
–
+0x02
INTCTRL
–
–
–
–
+0x03
INTFLAGS
–
–
–
–
–
–
COMPIF
OVFIF
215
+0x04
TEMP
–
–
–
–
–
–
COMPIF
OVFIF
215
+0x05
Reserved
–
–
–
–
–
–
–
–
+0x06
Reserved
–
–
–
–
–
–
–
–
+0x07
Reserved
–
–
–
–
–
–
–
–
+0x08
CNTL
TEMP[7:0]
216
+0x09
CNTH
CNT[7:0]
216
+0x0A
PERL
CNT[15:8]
216
+0x0B
PERH
PER[7:0]
216
+0x0C
COMPL
PER[15:8]
217
+0x0D
COMPH
COMP[7:0]
217
18.5
Bit 2
Bit 1
Bit 0
PRESCALER[2:0]
–
COMPINTLVL[1:0]
–
Page
214
SYNCBUSY
OVFINTLVL[1:0]
214
215
Interrupt Vector Summary
Table 18-2. RTC interrupt vectors and their word offset.
Offset
Source
Interrupt description
0x00
OVF_vect
Real-time counter overflow interrupt vector
0x02
COMP_vect
Real-time counter compare match interrupt vector
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19.
RTC32 – 32-bit Real-Time Counter
19.1
Features
32-bit resolution
32.768kHz external crystal clock source with selectable prescaling
1.024kHz
1Hz
One compare register
One period register
Clear counter on period overflow
Optional interrupt/ event on overflow and compare match
19.2
Overview
The 32-bit real-time counter (RTC32) is a 32-bit counter that typically runs continuously, including in low-power sleep
modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically a 1Hz prescaled output from a high-accuracy crystal of 32.768kHz, a configuration
optimized for low power consumption and 1s resolution. The faster 1.024kHz output can be selected if the timer needs
1ms resolution.
The RTC32 will give a compare interrupt and/or event when the counter equals the compare register value, and a
overflow interrupt and/or event when it equals the period register value.
Figure 19-1. 32-bit real-time counter overview.
PER
=
TOSC1
TOSC2
32.768 kHz
Crystal Osc
Overflow
1.024 kHz
DIV32
DIV1024
CNT
=
Compare
Match
COMP
19.2.1 Clock selection
An external 32.768kHz crystal oscillator must be used as the clock source. Two different frequency outputs are available
from this, and the RTC32 clock input can be 1.024kHz or 1Hz.
19.2.2 Clock Domains
The RTC32 is asynchronous, operating from a different clock source, and the counter is independent of the main system
clock and its derivative clocks, such as the peripheral clock. For control and count register updates, it will take a number
of RTC32 clocks and/or peripheral clock cycles before an updated register value is available in the register or until a
configuration change has effect on the RTC. This synchronization time is described for each register.
The Peripheral clock must be more than eight times faster than the RTC32 clock (1.024kHz or 1Hz) when any of the
Control or the Count register are accessed (read or written), more than 12 times faster when the Count register is written.
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19.2.3 Power Domains
For devices where the RTC32 is located in the VBAT power domain, the battery backup feature enables the RTC32 to also
function with no main VCC available. A dynamic power switch is used to automatically switch from the VCC domain to the
VBAT domain if VCC falls below the operating voltage level for the device. When the VCC voltage is restored, the power is
automatically switched back to VCC.
19.2.4 Interrupts and Events
The RTC32 can generate both interrupts and events. The RTC32 will give a compare interrupt request and/or event at
the next count after the counter value equals the compare register value. The RTC32 will give an overflow interrupt
request and/or event at the next count after the counter value equals the period register value. The overflow will also
reset the counter value to zero.
Due to the asynchronous clock domains, events will be generated only for every third overflow or compare match if the
period register is zero. If the period register is one, events will be generated only for every second overflow or compare
match. When the period register is equal to or above two, events will trigger at every overflow or compare match, just as
the interrupt request.
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19.3
Register Descriptions
19.3.1 CTRL – Control register
Bit
7
6
5
4
3
2
1
0
+0x00
–
–
–
–
–
–
–
ENABLE
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – ENABLE: Enable
Setting this bit enables the RTC32. The synchronization time between the RTC32 and the system clock domains is
one half RTC32 clock cycle from writing the register until this has an effect in the RTC32 clock domain; i.e., until
the RTC32 starts.
For the RTC32 to start running, the PER register must also be set to a value different from zero.
19.3.2 SYNCCTRL – Synchronisation Control/Status register
Bit
7
6
5
4
3
2
1
0
+0x01
–
–
–
SYNCCNT
–
–
–
SYNCBUSY
Read/Write
R
R
R
R/W
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 4 – SYNCCNT: Enable Synchronization of the CNT Register
Setting this bit will start synchronization of the CNT register from the RTC32 clock to the system clock domain. The
bit is automatically cleared when synchronization is done.
Bit 3:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 0 – SYNCBUSY: Synchronization Busy Flag
This flag is set when the CTRL or CNT register is busy synchronizing from the system clock to the RTC32 clock
domain. The CTRL register synchronization is triggered when it is written. The CNT register is synchronized when
the most-significant byte of the register is written.
19.3.3 INTCTRL – Interrupt Control register
Bit
7
6
5
4
3
2
1
0
+0x02
–
–
–
–
COMPINTLVL[1:0]
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
OCINTLVL[1:0]
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Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Level
These bits enable the RTC32 compare match interrupt and select the interrupt level, as described in “Interrupts
and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will trigger when COMPIF in
the INTFLAGS register is set.
Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Level
These bits enable the RTC32 overflow interrupt and select the interrupt level, as described in “Interrupts and Programmable Multilevel Interrupt Controller” on page 131. The enabled interrupt will trigger when OVFIF in the
INTFLAGS register is set.
19.3.4 INTFLAGS – Interrupt Flag register
Bit
7
6
5
4
3
2
1
0
+0x03
–
–
–
–
–
–
COMPIF
OVFIF
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written.
Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. The flag is cleared automatically when
the RTC32 compare match interrupt vector is executed. The flag can also be cleared by writing a one to its bit
location.
Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. The flag is cleared automatically when the
RTC32 overflow interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
19.3.5 CNT0 – Counter register 0
The CNT0, CNT1, CNT2, and CNT3 registers represent the 32-bit value, CNT. CNT counts positive clock edges on the
RTC32 clock.
Synchronization of a new CNT value to the RTC32 domain is triggered by writing CNT3. The synchronization time is up
to 12 peripheral clock cycles from updating the register until this has an effect in the RTC32 domain. Write operations to
the CNT register will be blocked if the SYNCBUSY flag is set.
The synchronization of the CNT register value from the RTC32 domain to the system clock domain can be done by
writing one to the SYNCCNT bit in the SYNCCTRL register. The updated and synchronized CNT register value is
available after eight peripheral clock cycles.
After writing to the high byte of the CNT register, the condition for setting OVFIF and COMPIF, as well as the overflow
and compare match wake-up condition, will be disabled for the following two RTC32 clock cycles.
Bit
7
6
5
4
+0x04
3
2
1
0
CNT[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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19.3.6 CNT1 – Counter register 1
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
+0x05
CNT[15:8]
19.3.7 CNT2 – Counter register 2
Bit
+0x06
CNT[23:16]
19.3.8 CNT3 – Counter register 3
Bit
7
+0x07
CNT[31:24]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
19.3.9 PER0 – Period register 0
The PER0, PER1, PER2, and PER3 registers represent the 32-bit value, PER. PER is constantly compared with the
counter value (CNT). A compare match will set OVFIF in the INTFLAGS register, and CNT will be set to zero in the next
RTC32 clock cycle. OVFIF will be set on the next count after match.
The PER register can be written only if the RTC32 is disabled and not currently synchronizing; i.e., when both ENABLE
and SYNCBUSY are zero.
After writing a byte in the PER register, the write (HW/SW) condition for setting OVFIF and the overflow wake-up
condition are disabled for the following two RTC32 clock cycles.
Bit
7
6
5
4
+0x08
3
2
1
0
PER[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
19.3.10 PER1 – Period register 1
Bit
+0x09
PER[15:8]
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19.3.11 PER2 – Period register 2
Bit
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
+0x0A
PER[23:16]
19.3.12 PER3 – Period register 3
Bit
+0x0B
PER[31:24]
19.3.13 COMP0 – Compare register 0
The COMP0, COMP1, COMP2, and COMP3 registers represents the 32-bit value, COMP. COMP is constantly
compared with the counter value (CNT). A compare match will set COMPIF in the INTFLAGS register, and an interrupt is
generated if it is enabled. COMPIF will be set on next count after a match.
If the COMP value is higher than the PER value, no RTC compare match interrupt requests or events will be generated.
After writing the high byte of the COMP register, the write condition for setting OVFIF and COMPIF, as well as the
overflow and compare match wake-up condition, will be disabled for the following two RTC32 clock cycles.
Bit
7
6
5
4
+0x0C
3
2
1
0
COMP[7:0]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
19.3.14 COMP1 – Compare register 1
Bit
7
+0x0D
COMP[15:8]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
19.3.15 COMP2 – Compare register 2
Bit
+0x0E
COMP[23:16]
19.3.16 COMP3 – Compare register 3
Bit
7
+0x0F
COMP[31:24]
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
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19.4
Register summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
CTRL
–
–
–
–
–
–
–
ENABLE
221
+0x01
SYNCCTRL
–
–
–
SYNCCNT
–
–
–
SYNCBUSY
+0x02
INTCTRL
–
–
–
–
+0x03
INTFLAGS
–
–
–
–
+0x04
CNT0
CNT[7:0]
222
+0x05
CNT1
CNT[15:8]
223
+0x06
CNT2
CNT[23:16]
223
+0x07
CNT3
CNT[31:24]
223
+0x08
PER0
PER[7:0]
223
+0x09
PER1
PER[15:8]
223
+0x0A
PER2
PER[23:16]
224
+0x0B
PER3
PER[31:24]
224
+0x0C
COMP0
COMP[7:0]
224
+0x0D
COMP1
COMP[15:8]
224
+0x0E
COMP2
COMP[23:16]
224
+0x0F
COMP3
COMP[31:24]
224
19.5
COMPINTLVL[1:0]
–
–
OVFINTLVL[1:0]
COMPIF
OVFIF
221
221
Interrupt vector summary
Table 19-1. RTC32 interrupt vectors and their word offset addresses.
Offset
Source
Interrupt description
0x00
OVF_vect
Real-time counter overflow interrupt vector
0x02
COMP_vect
Real-time counter compare match interrupt vector
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20.
USB – Universal Serial Bus Interface
20.1
Features
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
One input endpoint per endpoint address
One output endpoint per endpoint address
Endpoint address transfer type selectable to
Control transfers
Interrupt transfers
Bulk transfers
Isochronous transfers
Configurable data payload size per endpoint, up to 1023 bytes
Endpoint configuration and data buffers located in internal SRAM
Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
Built-in direct memory access (DMA) to internal SRAM for:
Endpoint configurations
Reading and writing endpoint data
Ping-pong operation for higher throughput and double buffered operation
Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
Multi-packet transfer for reduced interrupt load and software intervention
Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
Transaction complete FIFO for workflow management when using multiple endpoints
Tracks all completed transactions in a first-come, first-served work queue
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
20.2
Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types: control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and
a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep
mode.
Figure 20-1. USB OUT transfer: data packet from host to USB device.
HOST
Internal SRAM
BULK OUT
EPT 2
D
A
T
A
0
D
A
T
A
1
BULK OUT
EPT 3
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
BULK OUT
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
USB
D
A
T
A
0
USB Endpoints
Configuration Table
USBEPPTR
ENDPOINT 1 DATA
DP
DM
USB
Buffers
ENDPOINT 3 DATA
ENDPOINT 2 DATA
time
Figure 20-2. USB IN transfer: data packet from USB device to host after request from host.
Internal SRAM
CPU
HOST
EPT 2
D
A
T
A
0
D
A
T
A
1
EPT 3
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
EPT 1
D
A
T
A
1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
USB
I
N
EPT 2
T
O
K
E
N
I
N
EPT 3
T
O
K
E
N
USBEPPTR
ENDPOINT 1 DATA
USB
Buffers
DP
DM
USB Endpoints
Configuration Table
ENDPOINT 3 DATA
I
N
EPT 1
ENDPOINT 2 DATA
T
O
K
E
N
time
20.3
Operation
This section gives an overview of the USB module operation during normal transactions. For general details on USB and
the USB protocol, please refer to http://www.usb.org and the USB specification documents.
20.3.1 Start of Frame
When a start of frame (SOF) token is detected and storing of the frame numbers is enabled, the frame number from the
token is stored in the frame number register (FRAMENUM) and the start of frame interrupt flag (SOFIF) in the interrupt
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flag B clear/set register (INTFLAGSBCLR/SET) is set. If there was a CRC or bit-stuff error, the frame error (FRAMEERR)
flag in FRAMENUM is set.
20.3.2 SETUP
When a SETUP token is detected, the USB module fetches the endpoint control register (CTRL) from the addressed
output endpoint in the endpoint configuration table. If the endpoint type is not set to control, the USB module returns to
idle and waits for the next token packet.
Figure 20-3. SETUP transaction.
IDLE
SETUP
TOKEN
ADDRESS
ADDRESS
MATCH?
Yes
LEGAL
ENDPOINT?
ENDPOINT
No
DATA
BIT STUFF
CRC
READ
CONFIG
No
BIT STUFF
OK?
No
STORE
DATA
Yes
Yes
CRC OK?
EP TYPE
CTRL SET?
Yes
PID
PID OK?
No
Yes
Yes
No
ACK
No
UPDATE
STATUS
The USB module then fetches the endpoint data pointer register (DATAPTR) and waits for a DATA0 packet. If a PID
error or any other PID than DATA0 is detected, the USB module returns to idle and waits for the next token packet.
The incoming data are written to the data buffer pointed to by DATAPTR. If a bit-stuff error is detected in the incoming
data, the USB module returns to idle and waits for the next token packet. If the number of received data bytes exceeds
the endpoint's maximum data payload size, as specified by the data size (SIZE) in the endpoint CTRL register, the
remaining received data bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. Software must
never report a maximum data payload size to the host that is greater than specified in SIZE. If there was a bit-stuff or
CRC error in the packet, the USB module returns to idle and waits for the next token packet.
If data was successfully received, an ACK handshake is returned to the host, and the number of received data bytes,
excluding the CRC, is written to the endpoint byte counter (CNT). If the number of received data bytes is the maximum
data payload specified by SIZE, no CRC data are written in the data buffer. If the number of received data bytes is the
maximum data payload specified by SIZE minus one, only the first CRC data byte is written in the data buffer. If the
number of received data bytes is equal or less than the data byte payload specified by SIZE minus two, the two CRC
data bytes are written in the data buffer.
Finally, the setup transaction complete flag (SETUP), data buffer 0 not acknowledge flag (NACK0), and data toggle flag
(TOGGLE) are set, while the remaining flags in the endpoint status register (STATUS) are cleared for the addressed
input and output endpoints. The setup transaction complete interrupt flag (SETUPIF) in INTFLAGSBCLR/SET is set. The
STALL flag in the endpoint CTRL register is cleared for the addressed input and output endpoints.
When a SETUP token is detected and the device address of the token packet does not match that of the endpoint, the
packet is discarded, and the USB module returns to idle and waits for the next token packet.
20.3.3 OUT
When an OUT token is detected, the USB module fetches the endpoint CTRL and STATUS register data from the
addressed output endpoint in its endpoint configuration table. If the endpoint is disabled, the USB module returns to idle
and waits for the next token packet.
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Figure 20-4. OUT transaction.
IDLE
OUT
TOKEN
ADDRESS
MATCH?
ADDRESS
Yes
LEGAL
ENDPOINT?
ENDPOINT
No
READ
CONFIG
PIDO/1
OK?
No
Yes
READ
CONFIG
No
No
PID OK?
Yes
UPDATE
STATUS
NAK
STALL?
PID
No
No
Yes
Yes
BIT STUFF
DATA
CRC
BIT STUFF
OK?
No
Yes
CRC OK?
Yes
STALL
No
ISO?
No
BUSNACK0
SET?
Yes
No
Yes
STALL &
ISO?
EP STATUS
ENABLED?
Yes
Yes
BUSNACK0
SET?
No
DATA
STORE
DATA
Yes
NAK
No
No
DATA
BIT STUFF
CRC
BIT STUFF
OK?
No
Yes
CRC OK?
Yes
ACK
UPDATE
STATUS
STORE
DATA
The USB module then fetches the endpoint DATAPTR register and waits for a DATA0 or DATA1 packet. If a PID error or
any other PID than DATA0 or DATA1 is detected, the USB module returns to idle and waits for the next token packet.
If the STALL flag in the endpoint CTRL register is set, the incoming data are discarded. If the endpoint is not
isochronous, and the bit stuffing and CRC of the received data are OK, a STALL handshake is returned to the host, and
the STALL interrupt flag is set.
For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other endpoint types, the
PID is checked against TOGGLE. If they don't match, the incoming data are discarded and a NAK handshake is returned
to the host. If BUSNACK0 is set, the incoming data are discarded. The overflow flag (OVF) in the endpoint STATUS
register and the overflow interrupt flag (OVFIF) in the INTFLAGSASET/CLR register are set. If the endpoint is not
isochronous, a NAK handshake is returned to the host.
The incoming data are written to the data buffer pointed to by DATAPTR. If a bit-stuff error is detected in the incoming
data, the USB module returns to idle and waits for the next token packet. If the number of received data bytes exceeds
the maximum data payload specified by SIZE, the remaining received data bytes are discarded. The packet will still be
checked for bit-stuff and CRC errors. If there was a bit-stuff or CRC error in the packet, the USB module returns to idle
and waits for the next token packet.
If the endpoint is isochronous and there was a bit-stuff or CRC error in the incoming data, the number of received data
bytes, excluding CRC, is written to the endpoint CNT register. Finally, CRC and BUSNACK0 in the endpoint and
STATUS and CRCIF in INTFLAGSASET/CLR are set.
If data was successfully received, an ACK handshake is returned to the host if the endpoint is not isochronous, and the
number of received data bytes, excluding CRC, is written to CNT. If the number of received data bytes is the maximum
data payload specified by SIZE no CRC data are written in the data buffer. If the number of received data bytes is the
maximum data payload specified by SIZE minus one, only the first CRC data byte is written in the data buffer If the
number of received data bytes is equal or less than the data payload specified by SIZE minus two, the two CRC data
bytes are written in the data buffer.
Finally, the transaction complete flag (TRNCOMPL0) and BUSNACK0 are set and TOGGLE is toggled if the endpoint is
not isochronous. The transaction complete interrupt flag (TRNIF) in INTFLAGSBCLR/SET is set. The endpoint's
configuration table address is written to the FIFO if the transaction complete FIFO mode is enabled.
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When an OUT token is detected and the device address of the token packet does not match that of the endpoint, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
20.3.4 IN
If an IN token is detected the, the USB module fetches the endpoint CTRL and STATUS register data from the addressed
input endpoint in the endpoint configuration table. If the endpoint is disabled, the USB module returns to idle and waits for
the next token packet.
If the STALL flag in endpoint CTRL register is set, and the endpoint is not isochronous, a STALL handshake is returned
to the host, the STALL flag in the endpoint STATUS register and the STALL interrupt flag (STALLIF) in
INTFLAGSACLR/SET are set.
If BUSNACK0 is set, OVF in the endpoint STATUS register and OVFIF in the INTFLAGSACLR/SET register are set. If
the endpoint is not isochronous, a NAK handshake is returned to the host.
The data in the data buffer pointed to by the endpoint DATAPTR register are sent to the host in a DATA0 packet if the
endpoint is isochronous; otherwise, a DATA0 or DATA1 packet according to TOGGLE is sent. When the number of data
bytes specified in endpoint CNT is sent, the CRC is appended and sent to the host. If not, a ZLP handshake is returned
to the host.
For isochronous endpoints, BUSNACK0 and TRNCOMPL0 in the endpoint STATUS register are set. TRNIF is set, and
the endpoint's configuration table address is written to the FIFO if the transaction complete FIFO mode is enabled.
For all non-isochronous endpoints, the USB module waits for an ACK handshake from the host. If an ACK handshake is
not received within 16 USB clock cycles, the USB module returns to idle and waits for the next token packet. If an ACK
handshake was successfully received, BUSNACK0 and TRNCOMPL0 are set and TOGGLE is toggled. TRNIF is set and
the endpoint's configuration table address is written to the FIFO if the transaction complete FIFO mode is enabled.
When an IN token is detected and the device address of the token packet does not match that of the endpoint, the packet
is discarded and the USB module returns to idle and waits for the next token packet.
Figure 20-5. IN transaction.
IDLE
IN
TOKEN
ADDRESS
MATCH?
ADDRESS
Yes
ENDPOINT
No
READ
CONFIG
STALL &
NO ISO?
LEGAL
ENDPOINT?
Yes
READ
CONFIG
No
Yes
EP STATUS
ENABLED?
Yes
No
STALL
No
BUSNACK0
SET?
No
Yes
ISO?
No
NAK
Yes
ZLP
No
READ
DATA
DATA
PAYLOAD
OK?
Yes
CRC
ISO?
Yes
No
ACK
ACK
SET?
No
UPDATE
STATUS
Yes
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20.4
SRAM Memory Mapping
The USB module uses internal SRAM to store the:
• Endpoint configuration table
• USB frame number
• Transaction complete FIFO
The endpoint pointer register (EPPTR) is used to set the SRAM address for the endpoint configuration table. The USB
frame number (FRAMENUM) and transaction complete FIFO (FIFO) locations are derived from this. The locations of
these areas are selectable inside the internal SRAM. Figure on page 231 gives the relative memory location of each
area.
Figure 20-6. SRAM memory mapping.
EP_ADDRH_MAX
FIFO
(MAXEP+1) x 4 Bytes
Active when FIFOEN==1
EPPTR
ENDPOINT
DESCRIPTORS
TABLE
EPPTR +
(MAXEP+1)*16
FRAME
NUMBER
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
(MAXEP+1)