ATxmega128A1U/ATxmega64A1U
XMEGA® A1U Data Sheet
Introduction
The AVR® XMEGA® AU is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. The XMEGA A1U is a 100-pins device ranging
from 64KB to 128KB Flash, with 4KB to 8KB SRAM, 2KB EEPROM and up to 8KB boot section. The
ATxmegaA1U devices operate at a maximum frequency of 32MHz. By executing instructions in a single
clock cycle, the devices achieve CPU throughput approaching one million instructions per second (MIPS)
per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Features
High-performance, low-power AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
64K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2KBytes EEPROM
4K - 8KBytes internal SRAM
External bus interface for up to 16Mbytes SRAM
External bus interface for up to 128Mbit SDRAM
Peripheral features
Four-channel DMA controller
Eight-channel event system
Eight 16-bit timer/counters
Four timer/counters with 4 output compare or input capture channels
Four timer/counters with 2 output compare or input capture channels
High resolution extension on all timer/counters
Advanced waveform extension (AWeX) on two timer/counters
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
Eight USARTs with IrDA support for one USART
Four two-wire interfaces with dual address match (I2C and SMBus compatible)
Four serial peripheral interfaces (SPIs)
AES and DES crypto engine
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 1
ATxmega128A1U/ATxmega64A1U
CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
16-bit real time counter (RTC) with separate oscillator
Two sixteen channel, 12-bit, 2msps Analog to Digital Converters
Two Two-channel, 12-bit, 1msps Digital to Analog Converters
Four Analog Comparators (ACs) with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
JTAG (IEEE 1149.1 compliant) interface, including boundary scan
PDI (Program and Debug Interface)
I/O and packages
78 Programmable I/O pins
100 lead TQFP
100 ball BGA
100 ball VFBGA
Operating voltage
1.6 – 3.6V
0 – 32MHz from 2.7V
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 2
ATxmega128A1U/ATxmega64A1U
Table of Contents
1
Ordering Information ............................................................................... 8
2
Pinout/Block Diagram .............................................................................. 9
3
Overview ................................................................................................. 11
3.1
4
Block Diagram ................................................................................................. 12
Resources ............................................................................................... 13
4.1
Recommended reading ................................................................................... 13
5
Capacitive touch sensing ...................................................................... 13
6
AVR CPU ................................................................................................. 14
7
8
6.1
Features .......................................................................................................... 14
6.2
Overview.......................................................................................................... 14
6.3
Architectural Overview..................................................................................... 14
6.4
ALU - Arithmetic Logic Unit ............................................................................. 15
6.5
Program Flow .................................................................................................. 16
6.6
Status Register ................................................................................................ 16
6.7
Stack and Stack Pointer .................................................................................. 16
6.8
Register File .................................................................................................... 16
Memories ................................................................................................ 17
7.1
Features .......................................................................................................... 17
7.2
Overview.......................................................................................................... 17
7.3
Flash Program Memory ................................................................................... 18
7.4
Fuses and Lock bits......................................................................................... 19
7.5
Data Memory ................................................................................................... 19
7.6
EEPROM ......................................................................................................... 20
7.7
I/O Memory...................................................................................................... 20
7.8
External Memory ............................................................................................. 20
7.9
Data Memory and Bus Arbitration ................................................................... 20
7.10
Memory Timing ................................................................................................ 21
7.11
Device ID and Revision ................................................................................... 21
7.12
I/O Memory Protection..................................................................................... 21
7.13
JTAG Disable .................................................................................................. 21
7.14
Flash and EEPROM Page Size....................................................................... 21
DMAC – Direct Memory Access Controller .......................................... 23
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 3
ATxmega128A1U/ATxmega64A1U
9
8.1
Features .......................................................................................................... 23
8.2
Overview.......................................................................................................... 23
Event System .......................................................................................... 24
9.1
Features .......................................................................................................... 24
9.2
Overview.......................................................................................................... 24
10 System Clock and Clock options ......................................................... 25
10.1
Features .......................................................................................................... 25
10.2
Overview.......................................................................................................... 25
10.3
Clock Sources ................................................................................................. 26
11 Power Management and Sleep Modes ................................................. 28
11.1
Features .......................................................................................................... 28
11.2
Overview.......................................................................................................... 28
11.3
Sleep Modes.................................................................................................... 28
12 System Control and Reset .................................................................... 30
12.1
Features .......................................................................................................... 30
12.2
Overview.......................................................................................................... 30
12.3
Reset Sequence .............................................................................................. 30
12.4
Reset Sources ................................................................................................. 30
13 WDT – Watchdog Timer ......................................................................... 32
13.1
Features .......................................................................................................... 32
13.2
Overview.......................................................................................................... 32
14 Interrupts and Programmable Multilevel Interrupt Controller ........... 33
14.1
Features .......................................................................................................... 33
14.2
Overview.......................................................................................................... 33
14.3
Interrupt vectors............................................................................................... 33
15 I/O Ports .................................................................................................. 36
15.1
Features .......................................................................................................... 36
15.2
Overview.......................................................................................................... 36
15.3
Output Driver ................................................................................................... 37
15.4
Input sensing ................................................................................................... 39
15.5
Alternate Port Functions .................................................................................. 39
16 TC0/1 – 16-bit Timer/Counter Type 0 and 1 ......................................... 40
16.1
Features .......................................................................................................... 40
16.2
Overview.......................................................................................................... 40
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 4
ATxmega128A1U/ATxmega64A1U
17 TC2 – Time/Counter Type 2 ................................................................... 42
17.1
Features .......................................................................................................... 42
17.2
Overview.......................................................................................................... 42
18 AWeX – Advanced Waveform Extension ............................................. 43
18.1
Features .......................................................................................................... 43
18.2
Overview.......................................................................................................... 43
19 Hi-Res – High Resolution Extension .................................................... 44
19.1
Features .......................................................................................................... 44
19.2
Overview.......................................................................................................... 44
20 RTC – 16-bit Real-Time Counter ........................................................... 45
20.1
Features .......................................................................................................... 45
20.2
Overview.......................................................................................................... 45
21 USB – Universal Serial Bus Interface ................................................... 46
21.1
Features .......................................................................................................... 46
21.2
Overview.......................................................................................................... 46
22 TWI – Two-Wire Interface ...................................................................... 48
22.1
Features .......................................................................................................... 48
22.2
Overview.......................................................................................................... 48
23 SPI – Serial Peripheral Interface ........................................................... 50
23.1
Features .......................................................................................................... 50
23.2
Overview.......................................................................................................... 50
24 USART ..................................................................................................... 51
24.1
Features .......................................................................................................... 51
24.2
Overview.......................................................................................................... 51
25 IRCOM – IR Communication Module .................................................... 52
25.1
Features .......................................................................................................... 52
25.2
Overview.......................................................................................................... 52
26 AES and DES Crypto Engine ................................................................ 53
26.1
Features .......................................................................................................... 53
26.2
Overview.......................................................................................................... 53
27 CRC – Cyclic Redundancy Check Generator ...................................... 54
27.1
Features .......................................................................................................... 54
27.2
Overview.......................................................................................................... 54
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 5
ATxmega128A1U/ATxmega64A1U
28 EBI – External Bus Interface ................................................................. 55
28.1
Features .......................................................................................................... 55
28.2
Overview.......................................................................................................... 55
29 ADC – 12-bit Analog to Digital Converter ............................................ 56
29.1
Features .......................................................................................................... 56
29.2
Overview.......................................................................................................... 56
30 DAC – 12-bit Digital to Analog Converter ............................................ 58
30.1
Features .......................................................................................................... 58
30.2
Overview.......................................................................................................... 58
31 AC – Analog Comparator ...................................................................... 60
31.1
Features .......................................................................................................... 60
31.2
Overview.......................................................................................................... 60
32 PDI – Programming and Debugging ..................................................... 62
32.1
Features .......................................................................................................... 62
32.2
Overview.......................................................................................................... 62
33 Pinout and Pin Functions ...................................................................... 63
33.1
Alternate Pin Function Description .................................................................. 63
33.2
Alternate Pin Functions ................................................................................... 65
34 Peripheral Module Address Map .......................................................... 69
35 Instruction Set Summary ....................................................................... 72
36 Packaging information .......................................................................... 77
36.1
100A ................................................................................................................ 77
36.2
100C1 .............................................................................................................. 78
36.3
100C2 .............................................................................................................. 79
37 Electrical Characteristics ...................................................................... 80
37.1
ATxmega64A1U .............................................................................................. 80
37.2
ATxmega128A1U .......................................................................................... 103
38 Typical Characteristics ........................................................................ 126
38.1
ATxmega64A1U ............................................................................................ 126
38.2
ATxmega128A1U .......................................................................................... 168
39 Errata ..................................................................................................... 209
39.1
ATxmega64A1U ............................................................................................ 209
39.2
ATxmega128A1U .......................................................................................... 213
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 6
ATxmega128A1U/ATxmega64A1U
40 Datasheet Revision History ................................................................. 217
40.1
Rev. A – 08/2018 ........................................................................................... 217
40.2
8385I – 07/2014............................................................................................. 217
40.3
8385H – 05/2014 ........................................................................................... 217
40.4
8385G – 11/2013........................................................................................... 217
40.5
8385F – 12/2012 ........................................................................................... 217
40.6
8385E – 11/2012 ........................................................................................... 218
40.7
8385D – 07/2012 ........................................................................................... 218
40.8
8385C – 07/2012 ........................................................................................... 218
40.9
8385B – 03/2012 ........................................................................................... 218
40.10
8385A – 11/2011 ........................................................................................... 218
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 7
ATxmega128A1U/ATxmega64A1U
1. Ordering Information
Flash (bytes)
EEPROM
(bytes)
SRAM
(bytes)
ATxmega128A1U-AU
128K + 8K
2K
8K
ATxmega128A1U-AUR(4)
128K + 8K
2K
8K
ATxmega64A1U-AU
64K + 4K
2K
4K
ATxmega64A1U-AUR(4)
64K + 4K
2K
4K
ATxmega128A1U-CU
128K + 8K
2K
8K
ATxmega128A1U-CUR(4)
128K + 8K
2K
8K
ATxmega64A1U-CU
64K + 4K
2K
4K
ATxmega64A1U-CUR(4)
64K + 4K
2K
4K
ATxmega128A1U-C7U
128K + 8K
2K
8K
ATxmega128A1U-C7UR(4)
128K + 8K
2K
8K
ATxmega64A1U-C7U
64K + 4K
2K
4K
ATxmega64A1U-C7UR(4)
64K + 4K
2K
4K
ATxmega128A1U-AN
128K + 8K
2K
8K
ATxmega128A1U-ANR(4)
128K + 8K
2K
8K
ATxmega128A1U-CN
128K + 8K
2K
8K
ATxmega128A1U-CNR(4)
128K + 8K
2K
8K
Ordering code
Speed (MHz)
Power
supply
Package
(1)(2)(3)
Temp.
100A
100C1
32
-40C - 85C
1.6 - 3.6V
100C2
100A
-40C - 105C
Notes:
1.
2.
3.
4.
100C1
This device can also be supplied in wafer form. Please contact your local Microchip sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see “Packaging information” on page 77.
Tape and Reel.
Package Type
100A
100-lead, 14 x 14 x 1.0mm, 0.5mm lead pitch, thin profile plastic quad flat package (TQFP)
100C1
100-ball, 9 x 9 x 1.2mm body, ball pitch 0.80mm, chip ball grid array (CBGA)
100C2
100-ball, 7 x 7 x 1.0mm body, ball pitch 0.65mm, very thin fine-pitch ball grid array (VFBGA)
Typical Applications
Industrial control
Climate control
Low power battery applications
Factory automation
RF and ZigBee®
Power tools
Building control
USB connectivity
HVAC
Board control
Sensor control
Utility metering
White goods
Optical
Medical applications
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 8
ATxmega128A1U/ATxmega64A1U
2. Pinout/Block Diagram
Figure 2-1.
Block diagram and pinout.
PA3
PA2
PA1
PA0
AVCC
GND
PR1
PR0
PDI/ RESET
PDI
PQ3
PQ2
PQ1
PQ0
GND
VCC
PK7
PK6
PK5
PK4
PK3
PK2
PK1
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AC0:1
TWI
SPI
USART0:1
TC0:1
TWI
43
44
45
46
47
48
49
VCC
PF0
PF1
PF2
PF3
PF4
Port K
Port J
PJ0
64
VCC
63
GND
62
PH7
61
PH6
60
PH5
59
PH4
58
PH3
57
PH2
56
PH1
55
PH0
54
VCC
53
GND
52
PF7
51
PF6
50
SPI
USART0:1
GND
Port F
42
36
PE1
Port E
PE7
35
Port D
65
PF5
Port C
PE0
25
34
PD0
VCC
24
33
VCC
SRAM
EVENT ROUTING NETWORK
GND
23
EEPROM
DATA BUS
32
22
FLASH
PD7
PC7
GND
JTAG
31
21
CPU
PD6
PC6
DMA
Controller
30
20
Internal
Reference
PD5
PC5
BUS
matrix
Port H
DAC
IRCOM
19
External Bus Interface
ADC
Interrupt
Controller
29
PC4
PJ1
PD4
18
66
28
PC3
PJ2
PD3
17
Prog/Debug
Interface
67
OCD
AREF
16
PC2
Crypto /
CRC
27
PC1
15
Event System
Controller
PD2
PC0
14
PJ3
26
VCC
68
AC0:1
TC0:1
13
PJ4
41
GND
69
PE6
12
Reset
Controller
USB
11
PB7
Watchdog
Timer
40
PB6
Real Time
Counter
PE5
10
Sleep
Controller
TWI
PB5
PJ5
DAC
9
PJ7
70
PD1
PB4
8
72
PJ6
ADC
Port B
PB3
GND
71
39
7
73
Power
Supervision
PE4
PB2
VCC
Watchdog
Oscillator
SPI
6
PK0
74
Internal
Oscillators
38
PB1
75
OSC/CLK
Control
AREF
PE3
5
37
PB0
DATA BUS
PE2
4
TOSC
USART0:1
AVCC
XOSC
TC0:1
3
Port Q
TWI
GND
Port R
SPI
2
USART0:1
PA7
TC0:1
1
Port A
PA6
98
EBI
PA4
General Purpose I/O
Analog function / Oscillators
99
External clock / Crystal pins
Digital function
PA5
Programming, debug, test
Ground
100
Power
For details on pinout and pin functions refer to “Pinout and Pin Functions” on page 63.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 9
ATxmega128A1U/ATxmega64A1U
Figure 2-2.
BGA-pinout.
Top view
1
2
3
4
5
6
Bottom view
7
8
9
10
10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
Table 2-1.
BGA-pinout.
1
2
3
4
5
6
7
8
9
10
A
PK0
VCC
GND
PJ3
VCC
GND
PH1
GND
VCC
PF7
B
PK3
PK2
PK1
PJ4
PH7
PH4
PH2
PH0
PF6
PF5
C
VCC
PK5
PK4
PJ5
PJ0
PH5
PH3
PF2
PF3
VCC
D
GND
PK6
PK7
PJ6
PJ1
PH6
PF0
PF1
PF4
GND
E
PQ0
PQ1
PQ2
PJ7
PJ2
PE7
PE6
PE5
PE4
PE3
F
PR1
PR0
RESET/
PDI_CLK
PDI_DATA
PQ3
PC2
PE2
PE1
PE0
VCC
G
GND
PA1
PA4
PB3
PB4
PC1
PC6
PD7
PD6
GND
H
AVCC
PA2
PA5
PB2
PB5
PC0
PC5
PD5
PD4
PD3
J
PA0
PA3
PB0
PB1
PB6
PC3
PC4
PC7
PD2
PD1
K
PA6
PA7
GND
AVCC
PB7
VCC
GND
VCC
GND
PD0
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 10
ATxmega128A1U/ATxmega64A1U
3. Overview
The AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the
AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU
throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA A1U devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable multilevel
interrupt controller, 78 general purpose I/O lines, 16-bit real-time counter (RTC); eight flexible, 16-bit timer/counters with
compare and PWM channels, eight USARTs; four two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; four
serial peripheral interfaces (SPIs); AES and DES cryptographic engine; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3)
generator; two 16-channel, 12-bit ADCs with programmable gain; two 2-channel, 12-bit DACs; four Analog Comparators
(ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with
PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The devices
also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip debug and
programming.
The XMEGA A1U devices have five software selectable power saving modes. The idle mode stops the CPU while allowing
the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB
resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal
oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer
continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be
stopped in active mode and idle sleep mode.
Microchip offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The device are manufactured using Microchip high-density, nonvolatile memory technology. The program flash memory
can be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/
16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications.
All AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers,
macro assemblers, program debugger/simulators, programmers, and evaluation kits.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 11
ATxmega128A1U/ATxmega64A1U
3.1
Block Diagram
Figure 3-1.
XMEGA A1U Block Diagram.
Digital function
Bus masters, programming, debug, test
Analog function
EBI
Oscillator/Crystal/Clock
PR[0..1]
XTAL1
PQ[0..3]
TOSC1
General Purpose I/O
TOSC2
XTAL2
PORT R (2)
PORT Q (4)
Real Time
Counter
Watchdog
Oscillator
DATA BUS
DACA
PA[0..7]
Oscillator
Circuits/
Clock
Generation
PORT A (8)
Watchdog
Timer
Event System
Controller
Oscillator
Control
DMA
Controller
ADCA
VCC
Power
Supervision
POR/BOD &
RESET
SRAM
ACA
Sleep
Controller
GND
RESET/
PDI_CLK
AREFA
PDI
Prog/Debug
Controller
BUS Matrix
PDI_DATA
VCC/10
Int. Refs.
AES
Tempref
JTAG
OCD
AREFB
PORT B
DES
Interrupt
Controller
CPU
ADCB
PORT K (8)
PK[0..7]
PORT J (8)
PJ[0..7]
CRC
ACB
NVM Controller
PB[0..7]/
JTAG
EBI
PORT B (8)
Flash
PORT E/F
EEPROM
PORT H (8)
DACB
IRCOM
PH[0..7]
DATA BUS
PORT D (8)
PORT E (8)
PC[0..7]
PD[0..7]
PE[0..7]
Data Sheet Complete
SPIF
TWIF
TCF0:1
USARTF0:1
SPIE
PORT C (8)
TWIE
TCE0:1
USARTE0:1
USB
SPID
TWID
TCD0:1
USARTD0:1
SPIC
TWIC
TCC0:1
2018 Microchip Technology Inc.
USARTC0:1
EVENT ROUTING NETWORK
PORT F (8)
PF[0..7]
DS40002058A-page 12
ATxmega128A1U/ATxmega64A1U
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
www.microchip.com.
4.1
Recommended reading
• AVR XMEGA AU manual
• XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentations are available from www.microchip.com.
5. Capacitive touch sensing
The QTouch library provides a simple to use solution to realize touch sensitive interfaces on most AVR microcontrollers.
The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys
and includes Adjacent Key Suppression™ (AKS™) technology for unambiguous detection of key events. The QTouch
library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate QTouch library for the AVR microcontroller. This
is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to
retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Microchip website www.microchip.com.
For implementation details and other information, refer to the QTouch library user guide - also available for download from
the Microchip website.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 13
ATxmega128A1U/ATxmega64A1U
6. AVR CPU
6.1
Features
8/16-bit, high-performance AVR RISC CPU
142 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in RAM
Stack pointer accessible in I/O memory space
Direct addressing of up to 16MB of program memory and 16MB of data memory
True 16/24-bit access to 16/24-bit I/O registers
Efficient support for 8-, 16-, and 32-bit arithmetic
Configuration change protection of system-critical features
6.2
Overview
All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all
calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in
the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel
Interrupt Controller” on page 33.
6.3
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and
buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be
executed on every clock cycle. For details of all AVR instructions, refer to www.microchip.com.
Figure 6-1.
Block diagram of the AVR CPU architecture.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 14
ATxmega128A1U/ATxmega64A1U
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space
addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory
mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The
rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data
space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-programming of
the application flash memory must reside in the boot program section. The application section contains an application table
section with separate lock bits for write and read/write protection. The application table section can be used for safe storing
of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose
registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register
is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic
is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports
signed and unsigned multiplication and fractional format.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
• Multiplication of unsigned integers
• Multiplication of signed integers
• Multiplication of a signed integer with an unsigned integer
• Multiplication of unsigned fractional numbers
• Multiplication of signed fractional numbers
• Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 15
ATxmega128A1U/ATxmega64A1U
6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset,
the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status
register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the
need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that
are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the
stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and
the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address
0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory,
the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more
than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by
three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for
up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 20.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 16
ATxmega128A1U/ATxmega64A1U
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory.
7. Memories
7.1
Features
Flash program memory
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
Data memory
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O memory
Configuration and status registers for all peripherals and modules
16 bit-accessible general purpose register for global variables or flags
External memory support
SRAM
SDRAM
Memory mapped external hardware
Bus arbitration
Deterministic priority handling between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM, I/O memory and external memory
Simultaneous bus access for CPU and DMA controller
Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
Calibration bytes for factory calibrated peripherals
User signature row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can
reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no
memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This
prevents unrestricted access to the application software.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 17
ATxmega128A1U/ATxmega64A1U
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 8. In addition each device has a
flash memory signature rows for calibration data, device identification, serial number etc.
7.3
Flash Program Memory
The AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running
in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in
two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when
executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory.
Figure 7-1.
Flash program memory (Hexadecimal address).
Word Address
ATxmega128A1U
ATxmega64A1U
0
0
Application Section (bytes)
(128K/64K)
...
EFFF
/
77FF
F000
/
7800
FFFF
/
7FFF
10000
/
8000
10FFF
/
87FF
Application Table Section (bytes) (8K/
4K)
Boot Section (bytes)
(8K/4K)
7.3.1
Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2
Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data. The
size is identical to the boot loader section. The protection level for the application table section can be selected by the boot
lock bits for this section. The possibilities for different protection levels on the application section and the application table
section enable safe parameter storage in the program memory. If this section is not used for data, application code can
reside here.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 18
ATxmega128A1U/ATxmega64A1U
7.3.3
Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be
stored here.
7.3.4
Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the
corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical Characteristics”
on page 80.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates
for the device. The device ID for the available devices is shown in Table 7-1.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1.
Device ID bytes.
Device
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega64A1U
4E
96
1E
ATxmega128A1U
4C
97
1E
7.3.5
User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software and
external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data,
custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple
program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if
available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 20. To simplify devel-
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 19
ATxmega128A1U/ATxmega64A1U
opment, I/O Memory, EEPROM and SRAM will always have the same start addresses for all AVR XMEGA devices. The
address space for External Memory will always start at the end of Internal SRAM and end at address 0xFFFFFF.
Figure 7-2.
Data memory map (hexadecimal address).
Byte Address
ATxmega64A1U
0
I/O Registers (4K)
FFF
1000
EEPROM (2K)
17FF
Byte Address
0
FFF
1000
17FF
RESERVED
2000
Internal SRAM (4K)
2FFF
4000
FFFFFF
7.6
External Memory (0 to 16MB)
ATxmega128A1U
I/O Registers (4KB)
EEPROM (2K)
RESERVED
2000
3FFF
3000
FFFFFF
Internal SRAM (8K)
External Memory (0 to 16MB)
EEPROM
XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default)
or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000.
7.7
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which is
used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F, single- cycle instructions
for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA A1U is shown in the “Peripheral Module Address Map”
on page 69.
7.7.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.8
External Memory
Four ports can be used for external memory, supporting external SRAM, SDRAM, and memory mapped peripherals such
as LCD displays. Refer to “EBI – External Bus Interface” on page 55. The external memory address space will always start
at the end of internal SRAM.
7.9
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 20
ATxmega128A1U/ATxmega64A1U
7.10
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External memory
has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the external bus
interface. Refer to the instruction summary for more details on instructions and instruction timing.
7.11
Device ID and Revision
Each device has a three-byte device ID. This ID identifies the manufacturer of the device and the device type. A separate
register contains the revision number of the device.
7.12
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O
register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.13
JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is disabled,
the I/O pins required for JTAG can be used as normal I/O pins.
7.14
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 21 shows the Flash Program Memory organization. Flash write and erase operations are performed on
one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for
addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2.
Number of words and Pages in the Flash.
Devices
PC size
bits
Flash
bytes
Page Size
FWORD
FPAGE
words
Application
Size
No of pages
Boot
Size
No of pages
ATxmega64A1U
16
64K + 4K
128
Z[7:1]
Z[16:8]
64K
256
4K
16
ATxmega128A1U
17
128K + 8K
256
Z[8:1]
Z[17:9]
128K
256
8K
16
Table 7-3 on page 22 shows EEPROM memory organization for the AVR XMEGA A1U devices. EEPROM write and erase
operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For
EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address
(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 21
ATxmega128A1U/ATxmega64A1U
Table 7-3.
Number of Bytes and Pages in the EEPROM.
Devices
EEPROM
Page Size
Size
bytes
ATxmega64A1U
2K
ATxmega128A1U
2K
2018 Microchip Technology Inc.
E2BYTE
E2PAGE
No of Pages
32
ADDR[4:0]
ADDR[10:5]
64
32
ADDR[4:0]
ADDR[10:5]
64
Data Sheet Complete
DS40002058A-page 22
ATxmega128A1U/ATxmega64A1U
8. DMAC – Direct Memory Access Controller
8.1
Features
Allows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
from peripheral to data memory
from peripheral to peripheral
Four DMA channels with separate
transfer triggers
interrupt vectors
addressing modes
Programmable channel priority
From 1 byte to 16MB of data in a single transaction
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
Multiple addressing modes
Static
Incremental
Decremental
Optional reload of source and destination addresses at the end of each
Burst
Block
Transaction
Optional interrupt on end of transaction
Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination addresses
can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and
events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction
is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first
is finished, and vice versa.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 23
ATxmega128A1U/ATxmega64A1U
9. Event System
9.1
Features
System for direct peripheral-to-peripheral communication and signaling
Peripherals can directly send, receive, and react to peripheral events
CPU and DMA controller independent operation
100% predictable signal timing
Short and guaranteed response time
Eight event channels for up to eight different and parallel signal routing configurations
Events can be sent and/or used by most peripherals, clock system, and software
Additional functions include
Quadrature decoders
Digital filtering of I/O pin state
Works in active mode and idle sleep mode
9.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and
predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the
use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions.
Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How
events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 24 shows a basic diagram of all connected peripherals. The event system can directly connect together
analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication
module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also be
generated from software and the peripheral clock.
Figure 9-1.
Event system overview and connected peripherals.
CPU /
Software
DMA
Controller
Event Routing Network
ADC
AC
clkPER
Prescaler
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
USB
Port pins
IRCOM
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 24
ATxmega128A1U/ATxmega64A1U
10. System Clock and Clock options
10.1
Features
Fast start-up time
Safe run-time clock switching
Internal oscillators:
32MHz run-time calibrated and tunable oscillator
2MHz run-time calibrated oscillator
32.768kHz calibrated oscillator
32kHz ultra low power (ULP) oscillator with 1kHz output
External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
External clock
PLL with 20MHz - 128MHz output frequency
Internal and external clock options and 1x to 31x multiplication
Lock detector
Clock prescalers with 1x to 2048x division
Fast peripheral clocks running at two and four times the CPU clock
Automatic run-time calibration of internal oscillators
External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2
Overview
AVR XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and
clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and
can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if
the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will
always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers
can be changed from software at any time.
Figure 10-1 on page 26 presents the principal clock system in the XMEGA A1U family devices. Not all of the clocks need to
be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction
registers as described in “Power Management and Sleep Modes” on page 28.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 25
ATxmega128A1U/ATxmega64A1U
Figure 10-1. The clock system, clock sources, and clock distribution.
Real Time
Counter
Peripherals
RAM
AVR CPU
Non-Volatile
Memory
clkPER
clkCPU
clkPER2
clkPER4
USB
clkUSB
Brown-out
Detector
System Clock Prescalers
Watchdog
Timer
Prescaler
clkSYS
clkRTC
System Clock Multiplexer
(SCLKSEL)
RTCSRC
USBSRC
DIV32
DIV32
DIV32
PLL
PLLSRC
DIV4
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
32 MHz
Int. Osc
2 MHz
Int. Osc
XTAL2
XTAL1
TOSC2
TOSC1
10.3
0.4 – 16 MHz
XTAL
Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources
can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on
peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources,
DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 26
ATxmega128A1U/ATxmega64A1U
10.3.1
32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This
oscillator can be selected as the clock source for the RTC.
10.3.2
32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
10.3.3
32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be
used as a clock source for the system clock and RTC, and as the DFLL reference clock.
10.3.4
0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
10.3.5
2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration
of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6
32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide
a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic
run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The production signature
row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB clock source.
10.3.7
External Clock
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a 32.768kHz
crystal oscillator.
10.3.8
PLL with 1x-31x Multiplication factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies
from all clock sources.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 27
ATxmega128A1U/ATxmega64A1U
11. Power Management and Sleep Modes
11.1
Features
Power management for adjusting power consumption and functions
Five sleep modes
Idle
Power down
Power save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2
Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This
enables the AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code.
When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device
again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all
enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this
is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces
the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than
sleep modes alone.
11.3
Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution.
A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep,
and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt
occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from
the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs,
their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up
interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
11.3.1
Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all
peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled interrupt will
wake the device.
11.3.2
Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-wire
interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 28
ATxmega128A1U/ATxmega64A1U
11.3.3
Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
11.3.4
Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while
the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
11.3.5
Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 29
ATxmega128A1U/ATxmega64A1U
12. System Control and Reset
12.1
Features
Reset the microcontroller and set it to initial state when a reset source goes active
Multiple reset sources that cover different situations
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
Asynchronous operation
No running system clock in the device is required for reset
Reset status register for reading the reset source from the application code
12.2
Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation
should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source
goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values.
The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed
location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running
from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset
vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset
feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which
sources have issued a reset since the last power-on.
12.3
Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active.
When all reset requests are released, the device will go through three stages before the device starts running again:
• Reset counter delay
• Oscillator startup
• Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4
Reset Sources
12.4.1
Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 30
ATxmega128A1U/ATxmega64A1U
12.4.2
Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and
when the PDI is enabled.
12.4.3
External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be held
as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4
Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the
software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two
clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 32.
12.4.5
Software reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6
Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 31
ATxmega128A1U/ATxmega64A1U
13. WDT – Watchdog Timer
13.1
Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
13.2
Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period,
and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller
reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must
be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the
normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 32
ATxmega128A1U/ATxmega64A1U
14. Interrupts and Programmable Multilevel Interrupt Controller
14.1
Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
14.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will
generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller
(PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC,
the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt
handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt
priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within
a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3
Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the AVR XMEGA A1U devices are shown in Table 14-1 on page 33. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page 33. The program
address is the word address.
Table 14-1. Reset and interrupt vectors.
Program address
(base address)
Source
0x000
RESET
0x002
OSCF_INT_vect
Crystal oscillator failure interrupt vector (NMI)
0x004
PORTC_INT_base
Port C interrupt base
0x008
PORTR_INT_base
Port R interrupt base
0x00C
DMA_INT_base
DMA controller interrupt base
0x014
RTC_INT_base
Real time counter interrupt base
0x018
TWIC_INT_base
Two-Wire interface on port C interrupt base
0x01C
TCC0_INT_base
Timer/counter 0 on port C interrupt base
2018 Microchip Technology Inc.
Interrupt description
Data Sheet Complete
DS40002058A-page 33
ATxmega128A1U/ATxmega64A1U
Program address
(base address)
Source
Interrupt description
0x028
TCC1_INT_base
Timer/counter 1 on port C interrupt base
0x030
SPIC_INT_vect
SPI on port C interrupt vector
0x032
USARTC0_INT_base
USART 0 on port C interrupt base
0x038
USARTC1_INT_base
USART 1 on port C interrupt base
0x03E
AES_INT_vect
AES interrupt vector
0x040
NVM_INT_base
Nonvolatile memory interrupt base
0x044
PORTB_INT_base
Port B interrupt base
0x048
ACB_INT_base
Analog comparator on port B interrupt base
0x04E
ADCB_INT_base
Analog to digital converter on port B interrupt base
0x056
PORTE_INT_base
Port E interrupt base
0x05A
TWIE_INT_base
Two-Wire interface on port E interrupt base
0x05E
TCE0_INT_base
Timer/counter 0 on port E interrupt base
0x06A
TCE1_INT_base
Timer/counter 1 on port E interrupt base
0x072
SPIE_INT_vect
SPI on port E interrupt vector
0x074
USARTE0_INT_base
USART 0 on port E interrupt base
0x07A
USARTE1_INT_base
USART 1 on port E interrupt base
0x080
PORTD_INT_base
Port D interrupt base
0x084
PORTA_INT_base
Port A interrupt base
0x088
ACA_INT_base
Analog comparator on Port A interrupt base
0x08E
ADCA_INT_base
Analog to digital converter on Port A interrupt base
0x096
TWID_INT_base
Two-Wire Interface on port D interrupt base
0x09A
TCD0_INT_base
Timer/counter 0 on port D interrupt base
0x0A6
TCD1_INT_base
Timer/counter 1 on port D interrupt base
0x0AE
SPID_INT_vector
SPI on port D interrupt vector
0x0B0
USARTD0_INT_base
USART 0 on port D interrupt base
0x0B6
USARTD1_INT_base
USART 1 on port D interrupt base
0x0BC
PORTQ_INT_base
Port Q INT base
0x0C0
PORTH_INT_base
Port H INT base
0x0C4
PORTJ_INT_base
Port J INT base
0x0C8
PORTK_INT_base
Port K INT base
0x0D0
PORTF_INT_base
Port F INT base
0x0D4
TWIF_INT_base
Two-Wire interface on Port F INT base
0x0D8
TCF0_INT_base
Timer/counter 0 on port F interrupt base
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 34
ATxmega128A1U/ATxmega64A1U
Program address
(base address)
Source
Interrupt description
0x0E4
TCF1_INT_base
Timer/counter 1 on port F interrupt base
0x0EC
SPIF_INT_vector
SPI ion port F interrupt base
0x0EE
USARTF0_INT_base
USART 0 on port F interrupt base
0x0F4
USARTF1_INT_base
USART 1 on port F interrupt base
0x0FA
USB_INT_base
USB on port D interrupt base
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 35
ATxmega128A1U/ATxmega64A1U
15. I/O Ports
15.1
Features
78 General purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
Optional slew rate control
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
15.2
Selectable USART, SPI, and timer/counter input/output pin locations
Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all
sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have
hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs.
The notation of these ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, PORTH, PORTJ, PORTK, PORTQ
and PORTR.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 36
ATxmega128A1U/ATxmega64A1U
15.3
Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
15.3.1
Push-pull
Figure 15-1. I/O configuration - Totem-pole.
DIRn
OUTn
Pn
INn
15.3.2
Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input).
DIRn
OUTn
Pn
INn
15.3.3
Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).
DIRn
OUTn
Pn
INn
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 37
ATxmega128A1U/ATxmega64A1U
15.3.4
Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
Figure 15-4. I/O configuration - Totem-pole with bus-keeper.
DIRn
OUTn
Pn
INn
15.3.5
Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down.
OUTn
Pn
INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
INn
Pn
OUTn
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 38
ATxmega128A1U/ATxmega64A1U
15.4
Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7 on page 39.
Figure 15-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IRQ
Synchronous sensing
Pxn
Synchronizer
INn
D
Q D
R
Q
EDGE
DETECT
Synchronous
Events
R
INVERTED I/O
Asynchronous
Events
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5
Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that
peripheral. “Pinout and Pin Functions” on page 63 shows which modules on peripherals that enable alternate functions on
a pin, and what alternate functions that are available on a pin.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 39
ATxmega128A1U/ATxmega64A1U
16. TC0/1 – 16-bit Timer/Counter Type 0 and 1
16.1
Features
Eight 16-bit timer/counters
Four timer/counters of type 0
Four timer/counters of type 1
32-bit timer/counter support by cascading two timer/counters
Up to four compare or capture (CC) channels
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
Double buffered timer period setting
Double buffered capture or compare channels
Waveform generation:
Frequency generation
Single-slope pulse width modulation
Dual-slope pulse width modulation
Input capture:
Input capture with noise cancelling
Frequency capture
Pulse width capture
32-bit input capture
Timer overflow and error interrupt events
One compare match or input capture interrupt event per CC channel
Can be used with event system for:
Quadrature decoding
Count and direction control
Capture
Can be used with DMA and trigger DMA transactions
High-resolution extension
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
Advanced waveform extension
16.2
Low and high-side output with programmable dead-time insertion (DTI)
Event controlled fault protection for safe disabling of external drivers
Overview
AVR XMEGA devices have a set of eight flexible 16-bit timer/counters (TC). Their capabilities include accurate program
execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital
signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used
to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can
be used together with the base counter to do compare match control, frequency generation, and pulse width waveform
modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare
functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The
event system can also be used for direction control and capture trigger or to synchronize operations.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 40
ATxmega128A1U/ATxmega64A1U
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/
Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also
generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This is only available for Timer/Counter 0. See ”“AWeX – Advanced Waveform Extension” on page 43 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 44 for more details.
Figure 16-1. Overview of a timer/counter (TC) and closely related peripherals.
Timer/Counter
Base Counter
Timer Period
Counter
Prescaler
Control Logic
clkPER
Event
System
clkPER4
Buffer
Capture
Control
Waveform
Generation
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORT
Comparator
AWeX
Hi-Res
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
PORTC, PORTD, PORTE and PORTF each has one timer/counter 0 and one timer/counter1. Notation of these timer/counters are TCC0 (timer/counter C0), TCC1, TCD0, TCD1, TCE0, TCE1, TCF0, and TCF1, respectively.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 41
ATxmega128A1U/ATxmega64A1U
17. TC2 – Time/Counter Type 2
17.1
Features
Eight eight-bit timer/counters
Four Low-byte timer/counters
Four High-byte timer/counters
Up to eight compare channels in each timer/counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
Can be used to trigger DMA transactions
17.2
Overview
There are four Timer/counter 2. These are realized when a Timer/counter 0 is set in split mode. It is then a system of two
eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM)
channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM
channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match
interrupts, events and DMA triggers.
The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be
clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always
counting down.
PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2),
TCD2, TCE2 and TCF2, respectively.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 42
ATxmega128A1U/ATxmega64A1U
18. AWeX – Advanced Waveform Extension
18.1
Features
Waveform output with complementary output from each compare channel
Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
Double buffered dead time
Optionally halts timer during dead-time insertion
Pattern generation unit creating synchronised bit pattern across the port pins
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
Event controlled fault protection for instant and predictable fault triggering
18.2
Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It enables
low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It
can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the Timer/Counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-inverted
low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI
output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit
is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the
AWeX output. The event system ensures predictable and instant fault reaction, and gives great flexibility in the selection of
fault triggers.
The AWeX is available for TCC0 and TCE0. The notation of these are AWEXC and AWEXE.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 43
ATxmega128A1U/ATxmega64A1U
19. Hi-Res – High Resolution Extension
19.1
Features
Increases waveform generator resolution up to 8x (three bits)
Supports frequency, single-slope PWM and dual-slope PWM generation
Supports the AWeX when this is used for the same timer/counter
19.2
Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (Clk PER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There are four hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD, PORTE and
PORTF. The notation of these peripherals are HIRESC, HIRESD, HIRESE and HIRESF, respectively.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 44
ATxmega128A1U/ATxmega64A1U
20. RTC – 16-bit Real-Time Counter
20.1
Features
16-bit resolution
Selectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
Programmable 10-bit clock prescaling
One compare register
One period register
Clear counter on period overflow
Optional interrupt/event on overflow and compare match
20.2
Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration
most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution
higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz
internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter.
A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is
more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the
compare register value, and an overflow interrupt and/or event when it equals the period register value.
Figure 20-1. Real-time counter overview.
External Clock
TOSC1
TOSC2
32.768kHz Crystal Osc
32.768kHz Int. Osc
DIV32
DIV32
32kHz int ULP (DIV32)
PER
RTCSRC
clkRTC
10-bit
prescaler
=
TOP/
Overflow
=
”match”/
Compare
CNT
COMP
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 45
ATxmega128A1U/ATxmega64A1U
21. USB – Universal Serial Bus Interface
21.1
Features
One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
Integrated on-chip USB transceiver, no external components needed
16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
One input endpoint per endpoint address
One output endpoint per endpoint address
Endpoint address transfer type selectable to
Control transfers
Interrupt transfers
Bulk transfers
Isochronous transfers
Configurable data payload size per endpoint, up to 1023 bytes
Endpoint configuration and data buffers located in internal SRAM
Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
Built-in direct memory access (DMA) to internal SRAM for:
Endpoint configurations
Reading and writing endpoint data
Ping-pong operation for higher throughput and double buffered operation
Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
Multi packet transfer for reduced interrupt load and software intervention
Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
Transaction complete FIFO for workflow management when using multiple endpoints
Tracks all completed transactions in a first-come, first-served work queue
Clock selection independent of system clock source and selection
Minimum 1.5MHz CPU clock required for low speed USB operation
Minimum 12MHz CPU clock required for full speed operation
Connection to event system
On chip debug possibilities during USB transactions
21.2
Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 31
configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured for any
of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports
data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations and
data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of endpoints
in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data
from/to the SRAM when a USB transaction takes place.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 46
ATxmega128A1U/ATxmega64A1U
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output
endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the
USB module writes/reads the others, and vice versa. This gives double buffered communication.
Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a
suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode.
PORTD has one USB. Notation of this is USB.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 47
ATxmega128A1U/ATxmega64A1U
22. TWI – Two-Wire Interface
22.1
Features
Four identical two-wire interface peripherals
Bidirectional two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes, including power-down
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2
Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several
masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit
data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequencies are supported. Quick command and
smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for address
range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to
wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be
handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 48
ATxmega128A1U/ATxmega64A1U
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by the
TWI bus.
PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are TWIC, TWID, TWIE, and
TWIF.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 49
ATxmega128A1U/ATxmega64A1U
23. SPI – Serial Peripheral Interface
23.1
Features
Four identical SPI peripherals
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
23.2
Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows
fast communication between an AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI
supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC, PORTD, PORTE, and PORTF each has one SPI. Notation of these peripherals are SPIC, SPID, SPIE, and SPIF.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 50
ATxmega128A1U/ATxmega64A1U
24. USART
24.1
Features
Eight identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
Synchronous02 clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
Transmit complete
Transmit data register empty
Receive complete
Multiprocessor communication mode
Addressing scheme to address a specific devices on a multi device bus
Enable unaddressed devices to automatically ignore all frames
Master SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
24.2
Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The
USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also
be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to
achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers,
shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2Kbps.
PORTC, PORTD, PORTE, and PORTF each has two USARTs. Notation of these peripherals are USARTC0, USARTC1,
USARTD0, USARTD1, USARTE0, USARTE1, USARTF0 and USARTF1.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 51
ATxmega128A1U/ATxmega64A1U
25. IRCOM – IR Communication Module
25.1
Features
Pulse modulation/demodulation for infrared communication
IrDA compatible for baud rates up to 115.2Kbps
Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
Built-in filtering
Can be connected to and used by any USART
25.2
Overview
AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to
115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 52
ATxmega128A1U/ATxmega64A1U
26. AES and DES Crypto Engine
26.1
Features
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
Encryption and decryption
DES supported
Encryption/decryption in 16 CPU clock cycles per 8-byte block
AES crypto module
Encryption and decryption
Supports 128-bit keys
Supports XOR data load mode to the state memory
Encryption/decryption in 375 clock cycles per 16-byte block
26.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the communication
interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the register
file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be
loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock
cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when encryption/decryption is
done and optional auto-start of encryption/decryption when the state memory is fully loaded.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 53
ATxmega128A1U/ATxmega64A1U
27. CRC – Cyclic Redundancy Check Generator
27.1
Features
Cyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
Data in SRAM and I/O memory space
Integrated with flash memory, DMA controller and CPU
Continuous CRC on data going through a DMA channel
Automatic CRC of the complete or a selectable range of the flash memory
CPU can load data to the CRC generator through the I/O interface
CRC polynomial software selectable to
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
Zero remainder detection
27.2
Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it
is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to
the data and used as a checksum. When the same data are later received or read, the device or application repeats the
calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using
the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts.
The CRC module in AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3).
• CRC-16:
Polynomial:
x16+x12+x5+1
Hex value:
0x1021
• CRC-32:
Polynomial:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value:
0x04C11DB7
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 54
ATxmega128A1U/ATxmega64A1U
28. EBI – External Bus Interface
28.1
Features
Supports SRAM up to:
512KB using 2- or 3-port EBI configuration
16MB using 3- or 4-port EBI configuration
Supports SDRAM up to:
128Mb using 3- or 4-port EBI configuration
4-bit SDRAM with 3-port EBI configuration
4- or 8-bit SDRAM with 4-port EBI configuration
Four software configurable chip selects
Software configurable wait state insertion
Can run from the 2x peripheral clock frequency for fast access
Simultaneous SRAM and SDRAM support with 4-port EBI configuration
28.2
Overview
The External Bus Interface (EBI) is used to connect external peripherals and memory for accessthrough the data memory
space. When the EBI is enabled, data address space outside the internal SRAM becomes available using dedicated EBI
pins.
The EBI can interface external SRAM, SDRAM, and peripherals, such as LCD displays and other memory mapped
devices.
The address space for the external memory is selectable from 256 bytes (8-bit) up to 16MB (24-bit). Various multiplexing
modes for address and data lines can be selected for optimal use of pins when more or fewer pins are available for the EBI.
The complete memory will be mapped into one linear data address space continuing from the end of the internal SRAM.
The EBI has four chip selects, each with separate configuration. Each can be configured for SRAM, SRAM low pin count
(LPC), or SDRAM.
The EBI is clocked from the fast, 2x peripheral clock, running up to two times faster than the CPU.
Four-bit and eight-bit SDRAM are supported, and SDRAM configurations, such as CAS latency and refresh rate, are configurable in software.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 55
ATxmega128A1U/ATxmega64A1U
29. ADC – 12-bit Analog to Digital Converter
29.1
Features
Two Analog to Digital Converters
12-bit resolution
Up to two million samples per second
Two inputs can be sampled simultaneously using ADC and 1x gain stage
Four inputs can be sampled within 1.5µs
Down to 2.5µs conversion time with 8-bit resolution
Down to 3.5µs conversion time with 12-bit resolution
Differential and single-ended input
Up to 16 single-ended inputs
16x4 differential inputs without gain
8x4 differential input with gain
Built-in differential gain stage
1/2x,
1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
Single, continuous and scan conversion options
Four internal inputs
Internal temperature sensor
DAC output
AVCC voltage divided by 10
1.1V bandgap voltage
Four conversion channels with individual input control and result registers
Enable four parallel configurations and results
Internal and external reference options
Compare function for accurate monitoring of user defined thresholds
Optional event triggered conversion for accurate timing
Optional DMA transfer of conversion results
Optional interrupt/event on compare result
29.2
Overview
The ADC converts analog signals to digital values. There are two Analog to Digital Converters (ADCs) modules that can be
operated simultaneously, individually or synchronized.
The ADC has 12-bit resolution and is capable of converting up to two million samples per second (msps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an
optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The
ADC can provide both signed and unsigned results.
This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at a
low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started while other
ADC conversions are still ongoing. This removes dependencies between sample rate and propagation delay.
The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start control.
The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with high
data throughput or for multiple modules using the ADC independently. It is possible to use DMA to move ADC results
directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The output from the DAC, AVCC/10 and the bandgap voltage can also be measured by the ADC.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 56
ATxmega128A1U/ATxmega64A1U
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
Figure 29-1. ADC overview.
ADC0
Compare
•
••
ADC15
ADC0
Internal
signals
VINP
••
•
ADC7
ADC4
CH1 Result
Threshold
(Int Req)
½x - 64x
CH2 Result
•
••
ADC7
Int. signals
<
>
CH0 Result
Internal
signals
CH3 Result
VINN
ADC0
•
••
ADC3
Int. signals
Internal 1.00V
Internal AVCC/1.6V
Internal AVCC/2
AREFA
AREFB
Reference
Voltage
Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the
gain stage has 1x gain setting.
Four inputs can be sampled within 1.5µs without any intervention by the application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs
for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the
result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 57
ATxmega128A1U/ATxmega64A1U
30. DAC – 12-bit Digital to Analog Converter
30.1
Features
Two digital to analog converters (DACs)
12-bit resolution
Two independent, continuous-drive output channels
Up to one million samples per second conversion rate per DAC channel
Built-in calibration that removes:
Offset error
Gain error
Multiple conversion trigger sources
On new available data
Events from the event system
High drive capabilities and support for
Resistive loads
Capacitive loads
Combined resistive and capacitive loads
Internal and external reference options
DAC output available as input to analog comparator and ADC
Low-power mode, with reduced drive strength
Optional DMA transfer of data
30.2
Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in calibration
system can remove offset and gain error when loaded with calibration values from software.
Figure 30-1. DAC overview.
DMA req
(Data Empty)
CH0DATA
12
D
A
T
A
Trigger
AVCC
Internal 1.00V
AREFA
AREFB
Reference
selection
Output
Driver
Select
CTRLB
Int.
driver
Enable
To
AC/ADC
CTRLA
Internal Output enable
Trigger
CH1DATA
12
Select
Enable
D
A
T
A
Output
Driver
DMA req
(Data Empty)
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 58
ATxmega128A1U/ATxmega64A1U
A DAC conversion is automatically started when new data to be converted are available. Events from the event system can
also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other
peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.
The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both. A low-power mode is available, which will reduce the drive strength of the output.
Internal and external voltage references can be used. The DAC output is also internally available for use as input to the
analog comparator or ADC.
PORTA and PORTB each has one DAC. Notation of these peripherals are DACA and DACB, respectively.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 59
ATxmega128A1U/ATxmega64A1U
31. AC – Analog Comparator
31.1
Features
Four Analog Comparators
Selectable propagation delay versus current consumption
Selectable hysteresis
No
Small
Large
Analog comparator output available on pin
Flexible input selection
All pins on the port
Output from the DAC
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal AVCC voltage
Interrupt and event generation on:
Rising edge
Falling edge
Toggle
Window function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
Constant current source with configurable output pin selection
31.2
Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different
combinations of input change.
Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of
these parameters may be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 60
ATxmega128A1U/ATxmega64A1U
Figure 31-1. Analog comparator overview.
Pin Input
+
AC0OUT
Pin Input
Hysteresis
DAC
Voltage
Scaler
Enable
ACnMUXCTRL
ACnCTRL
Interrupt
Mode
WINCTRL
Enable
Bandgap
Interrupt
Sensititivity
Control
&
Window
Function
Interrupts
Events
Hysteresis
+
Pin Input
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 31-2.
Figure 31-2. Analog comparator window function.
+
AC0
Upper limit of window
Interrupt
sensitivity
control
Input signal
Interrupts
Events
+
AC1
Lower limit of window
2018 Microchip Technology Inc.
-
Data Sheet Complete
DS40002058A-page 61
ATxmega128A1U/ATxmega64A1U
32. PDI – Programming and Debugging
32.1
Features
Programming
External programming through PDI or JTAG interfaces
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
Debugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
No limitation on device clock frequency
Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
JTAG interface
32.2
Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging
Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG)
Overview
The Program and Debug Interface (PDI) is a proprietary interface for external programming and on-chip debugging of a
device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Microchip tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer,
which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one
other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this can
be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std. 1149.1
compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected
to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical
layer.
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 62
ATxmega128A1U/ATxmega64A1U
33. Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 9. In addition to general purpose I/O functionality, each pin
can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only
one of the pin functions can be used at time.
33.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
33.1.1
Operation/ Power Supply
VCC
Digital supply voltage
AVCC
Analog supply voltage
GND
Ground
33.1.2
Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
33.1.3
Analog functions
ACn
Analog Comparator input pin n
ACnOUT
Analog Comparator n Output
ADCn
Analog to Digital Converter input pin n
DACn
Digital to Analog Converter output pin n
AREF
Analog Reference input pin
33.1.4
External Bus Interface functions
An
Address line n
Dn
Data line n
CSn
Chip Select n
ALEn
Address Latch Enable pin n
(SRAM)
RE
Read Enable
(SRAM)
WE
External Data Memory Write
(SRAM /SDRAM)
BAn
Bank Address
(SDRAM)
CAS
Column Access Strobe
(SDRAM)
CKE
SDRAM Clock Enable
(SDRAM)
CLK
SDRAM Clock
(SDRAM)
DQM
Data Mask Signal/Output Enable
(SDRAM)
RAS
Row Access Strobe
(SDRAM)
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 63
ATxmega128A1U/ATxmega64A1U
33.1.5
Timer/Counter and AWEX functions
OCnxLS
Output Compare Channel x Low Side for Timer/Counter n
OCnxHS
Output Compare Channel x High Side for Timer/Counter n
33.1.6
Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
Serial Clock In for TWI when external driver interface is enabled
SCLOUT
Serial Clock Out for TWI when external driver interface is enabled
SDAIN
Serial Data In for TWI when external driver interface is enabled
SDAOUT
Serial Data Out for TWI when external driver interface is enabled
XCKn
Transfer Clock for USART n
RXDn
Receiver Data for USART n
TXDn
Transmitter Data for USART n
SS
Slave Select for SPI
MOSI
Master Out Slave In for SPI
MISO
Master In Slave Out for SPI
SCK
Serial Clock for SPI
D-
Data- for USB
D+
Data+ for USB
33.1.7
Oscillators, Clock and Event
TOSCn
Timer Oscillator pin n
XTALn
Input/Output for Oscillator pin n
CLKOUT
Peripheral Clock Output
EVOUT
Event Channel 0 Output
33.1.8
Debug/System functions
RESET
Reset pin
PDI_CLK
Program and Debug Interface Clock pin
PDI_DATA
Program and Debug Interface Data pin
TCK
JTAG Test Clock
TDI
JTAG Test Data In
TDO
JTAG Test Data Out
TMS
JTAG Test Mode Select
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 64
ATxmega128A1U/ATxmega64A1U
33.2
Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second
column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and
use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
the first table where this apply.
Table 33-1.
PORTA
Port A - alternate functions.
PIN #
INTERRUPT
ADCA POS
/GAINPOS
ADCB POS
ADCA
NEG
ADCA
ACA
ACA
ACA
GAINNEG
POS
NEG
OUT
GND
93
AVCC
94
PA0
95
SYNC
ADC0
ADC8
ADC0
AC0
AC0
PA1
96
SYNC
ADC1
ADC9
ADC1
AC1
AC1
PA2
97
SYNC/ASYNC
ADC2
ADC10
ADC2
AC2
PA3
98
SYNC
ADC3
ADC11
ADC3
AC3
PA4
99
SYNC
ADC4
ADC12
ADC4
AC4
PA5
100
SYNC
ADC5
ADC13
ADC5
AC5
PA6
1
SYNC
ADC6
ADC14
ADC6
AC6
PA7
2
SYNC
ADC7
ADC15
ADC7
Table 33-2.
PORT B
REFA
AREF
DAC0
AC3
DAC1
AC5
AC1OUT
AC7
AC0OUT
Port B - alternate functions.
PIN#
INTERRUPT
ADCAPOS
ADCBPOS/
GAINPOS
ADCB
NEG
ADCB
GAIN
NEG
ACB
POS
ACB
NEG
GND
3
AVCC
4
PB0
5
SYNC
ADC8
ADC0
ADC0
AC0
AC0
PB1
6
SYNC
ADC9
ADC1
ADC1
AC1
AC1
PB2
7
SYNC/
ASYNC
ADC10
ADC2
ADC2
AC2
PB3
8
SYNC
ADC11
ADC3
ADC3
AC3
PB4
9
SYNC
ADC12
ADC4
ADC4
AC4
PB5
10
SYNC
ADC13
ADC5
ADC5
AC5
PB6
11
SYNC
ADC14
ADC6
ADC6
AC6
PB7
12
SYNC
ADC15
ADC7
ADC7
Table 33-3.
PORT C
DACA
ACB
OUT
DACB
REFB
JTAG
AREF
DAC0
AC3
DAC1
TMS
AC5
AC7
TDI
AC1OUT
TCK
AC0OUT
TDO
Port C - alternate functions.
PIN#
GND
13
VCC
14
PC0
15
INTERRUPT
TCC0(1)(2)
AWEXC
SYNC
OC0A
OC0ALS
2018 Microchip Technology Inc.
TCC1
USARTC0(3)
USARTC1
SPIC(4)
TWIC
CLOCKOUT(5)
EVENTOUT(6)
SDA
Data Sheet Complete
DS40002058A-page 65
ATxmega128A1U/ATxmega64A1U
PIN#
INTERRUPT
TCC0(1)(2)
AWEXC
PC1
16
SYNC
OC0B
OC0AHS
XCK0
PC2
17
SYNC/ASYNC
OC0C
OC0BLS
RXD0
PC3
18
SYNC
OC0D
OC0BHS
TXD0
PC4
19
SYNC
OC0CLS
OC1A
PC5
20
SYNC
OC0CHS
OC1B
PC6
21
SYNC
PC7
22
SYNC
PORT C
Notes:
TCC1
USARTC0(3)
SPIC(4)
TWIC
CLOCKOUT(5)
EVENTOUT(6)
SCL
SS
XCK1
MOSI
OC0DLS
RXD1
MISO
clkRTC
OC0DHS
TXD1
SCK
clkPER
EVOUT
1.
Pin mapping of all TC0 can optionally be moved to high nibble of port. Refer to Pin Remap register in I/O Ports in the XMEGA AU Manual.
2.
3.
4.
5.
If TC0 is configured as TC2 all eight pins can be used for PWM output. Refer to Pin Remap register in I/O Ports in the XMEGA AU Manual..
Pin mapping of all USART0 can optionally be moved to high nibble of port. Refer to Pin Remap register in I/O Ports in the XMEGA AU Manual..
Pins MOSI and SCK for all SPI can optionally be swapped.Refer to Pin Remap register in I/O Ports in the XMEGA AU Manual.
CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7. Refer to CLKEVOUT register in I/O port configuration in the XMEGA AU
Manual.
EVOUT can optionally be moved between port C, D and E and between pin 4 and 7. Refer to CLKEVOUT register in I/O port configuration in the XMEGA AU
Manual.
6.
Table 33-4.
PORT D
Port D - alternate functions.
PIN#
INTERRUPT
TCD0
TCD1
USBD
USARTD0
GND
23
VCC
24
PD0
25
SYNC
OC0A
PD1
26
SYNC
OC0B
XCK0
PD2
27
SYNC/
ASYNC
OC0C
RXD0
PD3
28
SYNC
OC0D
TXD0
PD4
29
SYNC
OC1A
PD5
30
SYNC
OC1B
PD6
31
SYNC
PD7
32
SYNC
Table 33-5.
PORT E
USARTC1
USARTD1
SPID
TWID
CLOCKOUT
EVENTOUT
clkPER
EVOUT
SDA
SCL
SS
XCK1
MOSI
D-
RXD1
MISO
D+
TXD1
SCK
Port E - alternate functions.
PIN #
INTERRUPT
TCE0
AWEXE
TCE1
USARTE0
GND
33
VCC
34
PE0
35
SYNC
OC0A
OC0ALS
PE1
36
SYNC
OC0B
OC0AHS
XCK0
PE2
37
SYNC/ASYNC
OC0C
OC0BLS
RXD0
PE3
38
SYNC
OC0D
OC0BHS
TXD0
PE4
39
SYNC
OC0CLS
OC1A
PE5
40
SYNC
OC0CHS
OC1B
PE6
41
SYNC
PE7
42
SYNC
2018 Microchip Technology Inc.
USARTE1
SPIE
TWIE
CLOCKOUT
EVENTOUT
clkPER
EVOUT
SDA
SCL
SS
XCK1
MOSI
OC0DLS
RXD1
MISO
OC0DHS
TXD1
SCK
Data Sheet Complete
DS40002058A-page 66
ATxmega128A1U/ATxmega64A1U
Notes:
1.
All pins on the port can optionally be used for EBI chip select or address lines. Refer to the EBIOUT register description in the XMEGA AU Manual.
Table 33-6.
PORT F
Port F - alternate functions.
PIN #
INTERRUPT
TCF0
TCF1
USARTF0
GND
43
VCC
44
PF0
45
SYNC
OC0A
PF1
46
SYNC
OC0B
XCK0
PF2
47
SYNC/ASYNC
OC0C
RXD0
PF3
48
SYNC
OC0D
TXD0
PF4
49
SYNC
OC1A
PF5
50
SYNC
OC1B
PF6
51
PF7
52
Note:
1.
USARTF1
SPIF
TWIF
SDA
SCL
SS
XCK1
MOSI
SYNC
RXD1
MISO
SYNC
TXD1
SCK
All pins on the port can optionally be used for EBI chip select or address lines. Refer to the EBIOUT register description in the XMEGA AU Manual.
Table 33-7.
PORT H
Port H - alternate functions.
PIN #
INTERRUPT
SDRAM 3P
SRAM ALE1
SRAM ALE12
LPC3 ALE1
LPC2 ALE1
LPC2 ALE12
GND
53
VCC
54
PH0
55
SYNC
WE
WE
WE
WE
WE
WE
PH1
56
SYNC
CAS
RE
RE
RE
RE
RE
PH2
57
SYNC/ASYNC
RAS
ALE1
ALE1
ALE1
ALE1
ALE1
PH3
58
SYNC
DQM
PH4
59
SYNC
BA0
CS0/A16
CS0
CS0/A16
CS0
CS0/A16
PH5
60
SYNC
BA1
CS1/A17
CS1
CS1/A17
CS1
CS1/A17
PH6
61
SYNC
CKE
CS2/A18
CS2
CS2/A18
CS2
CS2/A18
PH7
62
SYNC
CLK
CS3/A19
CS3
CS3/A19
CS3
CS3/A19
Notes:
1.
2.
ALE2
CS0 - CS3 can optionally be moved to Port E or F
A16-A23 can optionally be moved to Port E or F when EBI configured in 4PORT mode. Refer to the EBIOUT register description in the XMEGA AU Manual.
Table 33-8.
PORT J
ALE2
Port J - alternate functions.
PIN #
INTERRUPT
SDRAM 3P
SRAM ALE1
SRAM ALE12
LPC3 ALE1
LPC2 ALE1
LPC2 ALE12
GND
63
VCC
64
PJ0
65
SYNC
D0
D0
D0
D0/A0
D0/A0
D0/A0/A8
PJ1
66
SYNC
D1
D1
D1
D1/A1
D1/A1
D1/A1/A9
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 67
ATxmega128A1U/ATxmega64A1U
PORT J
PIN #
INTERRUPT
SDRAM 3P
SRAM ALE1
SRAM ALE12
LPC3 ALE1
LPC2 ALE1
LPC2 ALE12
PJ2
67
SYNC/ASYNC
D2
D2
D2
D2/A2
D2/A2
D2/A2/A10
PJ3
68
SYNC
D3
D3
D3
D3/A3
D3/A3
D3/A3/A11
PJ4
69
SYNC
A8
D4
D4
D4/A4
D4/A4
D4/A4/A12
PJ5
70
SYNC
A9
D5
D5
D5/A5
D5/A5
D5/A5/A13
PJ6
71
SYNC
A10
D6
D6
D6/A6
D6/A6
D6/A6/A14
PJ7
72
SYNC
A11
D7
D7
D7/A7
D7/A7
D7/A7/A15
Table 33-9.
PORT K
Port K - alternate functions.
PIN #
INTERRUPT
SDRAM 3P
SRAM ALE1
SRAM ALE2
LPC3 ALE1
GND
73
VCC
74
PK0
75
SYNC
A0
A0/A8
A0/A8/A16
A8
PK1
76
SYNC
A1
A1/A9
A1/A9/A17
A9
PK2
77
SYNC/ASYNC
A2
A2/A10
A2/A10/A18
A10
PK3
78
SYNC
A3
A3/A11
A3/A11/A19
A11
PK4
79
SYNC
A4
A4/A12
A4/A12/A20
A12
PK5
80
SYNC
A5
A5/A13
A5/A13/A21
A13
PK6
81
SYNC
A6
A6/A14
A6/A14/A22
A14
PK7
82
SYNC
A7
A7/A15
A7/A15/A23
A15
Table 33-10. Port Q - alternate functions.
PORT Q
PIN #
INTERRUPT
TOSC
VCC
83
GND
84
PQ0
85
SYNC
TOSC1
PQ1
86
SYNC
TOSC2
PQ2
87
SYNC/ASYNC
PQ3
88
SYNC
Table 33-11. Port R - alternate functions.
PORT R
PIN #
INTERRUPT
PDI
XTAL
PDI
89
PDI_DATA
RESET
90
PDI_CLOCK
PRO
91
SYNC
XTAL2
PR1
92
SYNC
XTAL1
2018 Microchip Technology Inc.
Data Sheet Complete
DS40002058A-page 68
ATxmega128A1U/ATxmega64A1U
34. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA A1U. For complete register description and summary for each peripheral module, refer to the XMEGA AU manual.
Table 34-1.
Peripheral module address map.
Base address
Name
Description
0x0000
GPIO
General Purpose IO Registers
0x0010
VPORT0
Virtual Port 0
0x0014
VPORT1
Virtual Port 1
0x0018
VPORT2
Virtual Port 2
0x001C
VPORT3
Virtual Port 3
0x0030
CPU
CPU
0x0040
CLK
Clock Control
0x0048
SLEEP
Sleep Controller
0x0050
OSC
Oscillator Control
0x0060
DFLLRC32M
DFLL for the 32MHz Internal RC Oscillator
0x0068
DFLLRC2M
DFLL for the 2MHz RC Oscillator
0x0070
PR
Power Reduction
0x0078
RST
Reset Controller
0x0080
WDT
Watch-Dog Timer
0x0090
MCU
MCU Control
0x00A0
PMIC
Programmable Multilevel Interrupt Controller
0x00B0
PORTCFG
0x00C0
AES
AES Module
0x00D0
CRC
CRC Module
0x0100
DMA
DMA Controller
0x0180
EVSYS
0x01C0
NVM
Non Volatile Memory (NVM) Controller
0x0200
ADCA
Analog to Digital Converter on port A
0x0240
ADCB
Analog to Digital Converter on port B
0x0300
DACA
Digital to Analog Converter on port A
0x0320
DACB
Digital to Analog Converter on port B
0x0380
ACA
Analog Comparator pair on port A
0x0390
ACB
Analog Comparator pair on port B
0x0400
RTC
Real Time Counter
0x0440
EBI
External Bus Interface
2018 Microchip Technology Inc.
Port Configuration
Event System
Data Sheet Complete
DS40002058A-page 69
ATxmega128A1U/ATxmega64A1U
Base address
Name
Description
0x0480
TWIC
Two Wire Interface on port C
0x0490
TWID
Two Wire Interface on port D
0x04A0
TWIE
Two Wire Interface on port E
0x04B0
TWIF
Two Wire Interface on port F
0x04C0
USB
USB Device
0x0600
PORTA
Port A
0x0620
PORTB
Port B
0x0640
PORTC
Port C
0x0660
PORTD
Port D
0x0680
PORTE
Port E
0x06A0
PORTF
Port F
0x06E0
PORTH
Port H
0x0700
PORTJ
Port J
0x0720
PORTK
Port K
0x07C0
PORTQ
Port Q
0x07E0
PORTR
Port R
0x0800
TCC0
Timer/Counter 0 on port C
0x0840
TCC1
Timer/Counter 1 on port C
0x0880
AWEXC
Advanced Waveform Extension on port C
0x0890
HIRESC
High Resolution Extension on port C
0x08A0
USARTC0
USART 0 on port C
0x08B0
USARTC1
USART 1 on port C
0x08C0
SPIC
0x08F8
IRCOM
0x0900
TCD0
Timer/Counter 0 on port D
0x0940
TCD1
Timer/Counter 1 on port D
0x0990
HIRESD
0x09A0
USARTD0
USART 0 on port D
0x09B0
USARTD1
USART 1 on port D
0x09C0
SPID
Serial Peripheral Interface on port D
0x0A00
TCE0
Timer/Counter 0 on port E
0x0A40
TCE1
Timer/Counter 1 on port E
0x0A80
AWEXE
2018 Microchip Technology Inc.
Serial Peripheral Interface on port C
Infrared Communication Module
High Resolution Extension on port D
Advanced Waveform Extension on port E
Data Sheet Complete
DS40002058A-page 70
ATxmega128A1U/ATxmega64A1U
Base address
Name
Description
0x0A90
HIRESE
0x0AA0
USARTE0
USART 0 on port E
0x0AB0
USARTE1
USART 1 on port E
0x0AC0
SPIE
Serial Peripheral Interface on port E
0x0B00
TCF0
Timer/Counter 0 on port F
0x0B40
TCF1
Timer/Counter 1 on port F
0x0B90
HIRESF
0x0BA0
USARTF0
USART 0 on port F
0x0BB0
USARTF1
USART 1 on port F
0x0BC0
SPIF
2018 Microchip Technology Inc.
High Resolution Extension on port E
High Resolution Extension on port F
Serial Peripheral Interface on port F
Data Sheet Complete
DS40002058A-page 71
ATxmega128A1U/ATxmega64A1U
35. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
Rd, Rr
Add without Carry
Rd
Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd
Rd + Rr + C
Z,C,N,V,S,H
1
ADIW
Rd, K
Add Immediate to Word
Rd
Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd
Rd + 1:Rd - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND
Rd
Rd Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
Rd K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
Rd Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
Rd ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
Rd Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
Rd Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0
Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0
Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0
Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0
Rd x Rr