CEC1302
Low Power Crypto Embedded Controller
Product Features
®
®
• ARM Cortex -M4 Processor Core
- 32-Bit ARM v7-M Instruction Set Architecture
- Hardware Floating Point Unit (FPU)
- Single 4GByte Addressing Space (Von Neumann Model)
- Little-Endian Byte Ordering
- Bit-Banding Feature Included
- NVIC Nested Vectored Interrupt Controller
- Up to 240 Individually-Vectored Interrupt Sources
Supported
- 8 Levels of Priority, Individually Assignable By Vector
- Chip-Level Interrupt Aggregator supported, to
expand number of interrupt sources or reduce
number of vectors
- System Tick Timer
- Complete ARM-Standard Debug Support
- JTAG-Based DAP Port, Comprised of SWJ-DP and
AHB-AP Debugger Access Functions
- Full DWT Hardware Functionality: 4 Data
Watchpoints and Execution Monitoring
- Full FPB Hardware Breakpoint Functionality: 6
Execution Breakpoints and 2 Literal (Data)
Breakpoints
• Public Key Cryptographic Engine
- Hardware support for RSA and Elliptic Curve
public key algorithms
- RSA keys length from 512 to 2048 bits
- ECC Prime Field keys up to 256 bits
• Cryptographic Features
- True Random Number Generator
- 1K bit FIFO
- Secure Boot from ROM
- Hardware based root of trust
•
•
•
- Comprehensive ARM-Standard Trace Support
- Full DWT Hardware Trace Functionality for
Watchpoint and Performance Monitoring
- Full ITM Hardware Trace Functionality for
Instrumented Firmware Support and Profiling
- Full ETM Hardware Trace Functionality for
Instruction Trace
- Full TPIU Functionality for Trace Output
Communication
• 128K SRAM (Code and Data)
- 96K Optimized for Code
- 32K Optimized for Data
• Multi-purpose AES Cryptographic Engine
- Hardware support for ECB, CTR, CBC and
OFB AES modes
- Support for 128-bit, 192-bit and 256-bit key
length
- DMA interface to SRAM, shared with Hash
engine
• Cryptographic Hash Engine
- Support for SHA-1 & SHA-256
- DMA interface to SRAM, shared with AES
engine
2016 Microchip Technology Inc.
•
•
- Support Secure Firmware Updates
Two SPI Memory Interfaces
- 3-pin Full Duplex serial communication interface
- Two Private and Two Shared Chip Selects
- DMA Support
Battery Backed (VCC0/VBAT) Resources
- Power Fail Register
- Power-Fail Status Register
- Battery backed 64 byte memory
Real Time Clock (RTC)
- VCC0 (VBAT) Powered
- 32KHz Crystal Oscillator
- 32KHz Clock output available under VCC1
power
- Time-of-Day and Calendar Registers
- Programmable Alarms
- Supports Leap Year and Daylight Savings
Time
Hibernation Timers
General Purpose Analog to Digital Converter
- 10-bit conversion precision
- 10-bit conversion per channel is completed in
less than 12us
- 5 ADC channels
- 10-bit Conversion with 2.9mV resolution
- 0 to 3.3 VDC Conversion Range
- Optional continuous sampling at a programmable
rate
- Internal Analog Voltage Reference (3.0V +/1%)
• Watch Dog Timer
• Four Programmable 16-bit and Two 32-bit Timers
- Wake-capable Auto-reloading Timers
• Four Programmable Pulse-Width Modulator Outputs
- Independent Clock Rates
- 16-Bit Duty Cycle Granularity
- Operational in both Full on and Standby modes
DS00002022B-page 1
CEC1302
• Four I2C/SMBus 2.0 Host Controllers
- Allows Master or Dual Slave Operation
- Controllers are Fully Operational on Standby
Power
- DMA-driven I2C Network Layer Hardware
- I2C Datalink Compatibility Mode
- Multi-Master Capable
- Supports Clock Stretching
- Programmable Bus Speeds
- 400 KHz Fast-mode Capable
- 1 Mbps Fast-mode Plus Capable
•
•
•
•
•
•
•
•
•
•
•
•
- Hardware Bus Access "Fairness" Interface
- SMBus Time-outs Interface
- 5 Ports
- 2 Port Flexible Multiplexing
Keyboard Matrix Scan Interface
- 18 x 8 Interrupt/Wake Capable Multiplexed
Keyboard Scan Matrix
- Row Predrive Option
Four Breathing/Blinking LED Interfaces
- Programmable Blink Rates
- Piecewise Linear Breathing LED Output Controller
- Operational in EC Sleep States
Dual Fan Tachometer Inputs
RPM-Based Fan Speed Control Algorithm
- Utilizes one TACH input and one PWM output
- 3% accurate from 500 RPM to 16k RPM
- Automatic Tachometer feedback
- Aging Fan or Invalid Drive Detection
- Spin Up Routine
- Ramp Rate Control
- RPM-based Fan Speed Control Algorithm
Glue Logic Functionality Supporting System Deep
Sleep
Integrated Power-on Reset Generator
- VCC1_RST# open drain output
- Accepts External driven Reset
Anti-Glitch Protection on Power-on
All Blocks Support Low Power Sleep Modes
General Purpose Input/Output Pins
- Low Power
- High Configurability
Two pin Debug Port with standard 16C550A register interface
BC-Link Interconnection Bus
- One High Speed Bus Master Controller
- Connects to a Microchip GPIO Expander
Package
- 144-pin WFBGA
DS00002022B-page 2
Description
The CEC1302 incorporates a high-performance 32-bit
ARM® Cortex®-M4 embedded microcontroller with 128
Kilobytes of SRAM and 32 Kilobytes of Boot ROM. It
communicates with the system host using the I2C bus.
The CEC1302 has two SPI memory interfaces that
allow the EC to read its code from external SPI flash
memory: private SPI and/or shared SPI. The Shared
SPI interface allows for EC code to be stored in a
shared SPI chip. The private SPI memory interface provides for a dedicated SPI flash that is only accessible
by the EC.
The CEC1302 provides support for loading EC code
from the private or shared SPI flash device on a VCC1
power-on. Before executing the EC code loaded from a
SPI Flash Device, the CEC1302 validates the EC code
using a digital signature encoded according to PKCS
#1. The signature uses RSA-2048 encryption and
SHA-256 hashing. This provides automated detection
of invalid EC code that may be a result of malicious or
accidental corruption. It occurs before each boot of the
host processor, thereby ensuring a HW based root of
trust not easily thwarted via physical replacement
attack.
The CEC1302 is directly powered by two separate suspend supply planes (VBAT and VCC1) and senses the
runtime power plane (VCC) to provide “Instant On” and
system power management functions. It also contains
an integrated VCC1 Reset Interface and a system
Power Management Interface that supports low-power
states and can drive state changes as a result of hardware wake events.
2016 Microchip Technology Inc.
CEC1302
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
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2016 Microchip Technology Inc.
DS00002022B-page 3
CEC1302
Table of Contents
1.0 Pin Configuration ............................................................................................................................................................................. 5
2.0 Block Overview ............................................................................................................................................................................. 39
3.0 Power, Clocks, and Resets ........................................................................................................................................................... 41
4.0 Security Features .......................................................................................................................................................................... 63
5.0 VBAT Register Bank ..................................................................................................................................................................... 67
6.0 ARM M4F Based Embedded Controller ........................................................................................................................................ 70
7.0 RAM and ROM .............................................................................................................................................................................. 79
8.0 UART ............................................................................................................................................................................................ 81
9.0 EC Interrupt Aggregator ................................................................................................................................................................ 95
10.0 Watchdog Timer (WDT) ............................................................................................................................................................ 121
11.0 Basic Timer ............................................................................................................................................................................... 125
12.0 Hibernation Timer ...................................................................................................................................................................... 131
13.0 RTC With Date and DST Adjustment ........................................................................................................................................ 134
14.0 GPIO Interface .......................................................................................................................................................................... 146
15.0 Internal DMA Controller ............................................................................................................................................................. 161
16.0 I2C/SMBus Interface ................................................................................................................................................................. 175
17.0 TACH ........................................................................................................................................................................................ 178
18.0 PWM ......................................................................................................................................................................................... 185
19.0 RPM-PWM Interface ................................................................................................................................................................. 190
20.0 General Purpose Serial Peripheral Interface ............................................................................................................................ 208
21.0 Blinking/Breathing PWM ........................................................................................................................................................... 227
22.0 Keyboard Scan Interface ........................................................................................................................................................... 243
23.0 BC-Link Master ......................................................................................................................................................................... 250
24.0 Trace FIFO Debug Port (TFDP) ................................................................................................................................................ 256
25.0 Analog to Digital Converter ....................................................................................................................................................... 260
26.0 VBAT-Powered RAM ................................................................................................................................................................ 267
27.0 EC Subsystem Registers .......................................................................................................................................................... 270
28.0 Test Mechanisms ...................................................................................................................................................................... 274
29.0 Electrical Specifications ............................................................................................................................................................ 281
30.0 Timing Diagrams ....................................................................................................................................................................... 288
31.0 Memory Map ............................................................................................................................................................................. 306
Appendix A: Revision History ............................................................................................................................................................ 330
The Microchip Web Site .................................................................................................................................................................... 331
Customer Change Notification Service ............................................................................................................................................. 331
Customer Support ............................................................................................................................................................................. 331
Product Identification System ............................................................................................................................................................ 332
DS00002022B-page 4
2016 Microchip Technology Inc.
CEC1302
1.0
PIN CONFIGURATION
1.1
Description
The Pin Configuration chapter includes a Pin List, Pin Description, Pin Multiplexing and Package Outline.
1.2
Terminology and Symbols for Pins/Buffers
Term
Definition
Pin Ref. Number
There is a unique reference number for each pin name.
#
The ‘#’ sign at the end of a signal name indicates an active-low signal
n
The lowercase ‘n’ preceding a signal name indicates an active-low signal
PWR
Power
I
Digital Input
IS
Input with Schmitt Trigger
I_AN
Analog Input
O
Push-Pull Output
OD
Open Drain Output
IO
Bi-directional pin
IOD
Bi-directional pin with Open Drain Output
PIO
Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output.
PCI_I
Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1-1)
PCI_O
Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1-1)
PCI_OD
Open Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1-1)
PCI_IO
Input/Output These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1-1)
PCI_ICLK
PCI_PIO
Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 1-2)
Note 1-1
Programmable as Input, Output, Open Drain Output, Bi-directional or Bi-directional with Open
Drain Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1-1).
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
Note 1-2
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
1.3
Pin List
The Pin List is shown in Table 1-1.
Note:
The Pin Ref. Number is a numerical reference for the ball number in the package.
Note 1: The XTAL2 pin can be used as a single ended clock input. See Note 9 in Section 1.6, "Notes for Tables in
this Chapter," on page 36.
2: See Note 10 in Section 1.6, "Notes for Tables in this Chapter," on page 36 for information about the SPI pins.
3: The VCC1_RST#/GPIO131 pin cannot be used as a GPIO pin. The input path to the VCC1_RST# logic is
always active and will cause a reset if this pin is set low in GPIO mode.
4: The GPIO041 pin defaults to output low. This pin must be reprogrammed to the GPIO function upon powerup.
2016 Microchip Technology Inc.
DS00002022B-page 5
CEC1302
Note:
Table 1-1, "CEC1302 144 WFBGA Pin Configuration" shows the mapping between Pin Ref. Number and
144 WFBGA ball number.
TABLE 1-1:
CEC1302 144 WFBGA PIN CONFIGURATION
Pin Ref.
Num ber
1
144
WFBGA
Num ber
C3
2
F5
GPIO153/PVT_SCLK
38
N5
ADC4/GPIO062
3
F6
GPIO122/SHD_SCLK
39
M5
ADC3/GPIO061
4
A2
GPIO011/KSO16
40
L5
AVCC
5
A1
KSO13/GPIO006
41
N6
GPIO206
6
B1
KSO12/GPIO005
42
M6
ADC2/GPIO060
7
B2
KSO11/GPIO107
43
L6
ADC1/GPIO057
8
C2
KSO10/GPIO004
44
N7
ADC0/GPIO056
9
C1
KSO09/GPIO106
45
M7
AVSS
10
D2
KSO08/GPIO003
46
N8
Reserved/GPIO112
11
D1
VSS
VSS
E2
KSO07/GPIO002
47
48
A5
12
M8
Reserved/GPIO114
13
E1
KSO06/GPIO001
49
J3
JTAG_RST#
14
G5
VCC1
50
L8
Reserved/GPIO113
15
F1
CAP
51
L9
Reserved/GPIO111
16
G2
KSO05/GPIO104/TFDP_CLK
52
N9
Reserved/GPIO120
17
H3
KSO04/GPIO103/TFDP_DATA/XNOR
53
N10
LRESET#/GPIO116
18
H1
KSO03/GPIO102/JTAG_TDO
54
M9
Reserved/GPIO117
Pin Nam e
GPIO036
Pin Ref.
Num ber
37
144
WFBGA
Num ber
H5
Pin Nam e
VCC1
19
J1
KSO02/GPIO101/JTAG_TDI
55
M10
20
H2
KSO01/GPIO100/JTAG_TMS
56
F3
VSS
Reserved/GPIO014
Reserved/GPIO115
21
J2
KSO00/GPIO000/JTAG_TCK
K1
KSI7/GPIO043
57
58
L10
22
23
K3
KSI6/GPIO042
59
N11
24
K2
KSI5/GPIO040
60
N12
nRESET_OUT/GPIO121
25
L1
KSI4/GPIO142/TRACECLK
61
N13
Reserved/GPIO050
26
L2
KSI3/GPIO032/TRACEDATA0
62
L11
Reserved/GPIO065
27
L3
KSI2/GPIO144/TRACEDATA1
63
M12
GPIO035
28
M2
KSI1/GPIO126/TRACEDATA2
64
M13
GPIO027
29
M1
KSI0/GPIO125/TRACEDATA3
65
L12
GPIO033
30
N2
GPIO031
66
K11
Reserved/GPIO046
31
N1
GPIO127
67
J12
Reserved/GPIO047
32
M3
Reserved/GPIO052
68
K12
VBAT
33
N3
GPIO147
69
L13
XTAL2
34
M4
GPIO151
70
K13
VSS_VBAT
35
L4
Reserved/GPIO051
71
J13
XTAL1
36
E3
VSS
72
J11
VCC_PWRGD/GPIO063
DS00002022B-page 6
J5
VCC1
Reserved/GPIO041
2016 Microchip Technology Inc.
CEC1302
Pin Ref.
Num ber
73
144
WFBGA
Num ber
H13
74
H11
75
H12
76
G13
Pin Ref.
Num ber
109
144
WFBGA
Num ber
B9
Pin Nam e
I2C0_DAT1/GPIO017
GPIO130
110
A9
I2C0_CLK1/GPIO134
32KHZ_OUT/GPIO013
111
A8
I2C0_DAT0/GPIO016
Reserved/GPIO026
112
C8
I2C0_CLK0/GPIO015
LED0/GPIO154
Pin Nam e
GPIO110
77
H8
VCC1_RST#/GPIO131
113
A7
78
G8
GPIO141/PWM3/LED3
114
B8
LED1/GPIO155
79
G12
VSS
115
C7
LED2/GPIO156
80
G9
GPIO132
116
B7
GPIO163
81
G11
GPIO007/KSO14
117
C10
VSS
GPIO136/PWM1
82
J9
VSS
118
A6
83
F13
GPIO010/KSO15
119
G6
VCC1
84
J6
VCC1
120
B6
GPIO133/PWM0
85
F11
GPIO143/RSMRST#
121
C5
GPIO034/PWM2/TACH2PWM_OUT
86
D13
GPIO162/RXD
122
A4
GPIO135
87
F7
GPIO165/TXD/SHD_CS1#
123
B4
GPIO044
88
E13
GPIO023/I2C1_DAT0
124
C4
GPIO066
89
E12
GPIO022/I2C1_CLK0
125
B3
GPIO025/I2C3_DAT0
90
E11
GPIO021/I2C2_DAT0
126
A3
GPIO024/I2C3_CLK0
91
D11
GPIO020/I2C2_CLK0
127
E6
GPIO054/PVT_MOSI
92
D12
GPIO105/TACH1
128
E5
GPIO064/SHD_MOSI
93
C13
GPIO145
129
G3
GPIO067
94
F9
GPIO164/PVT_MISO
130
F2
GPIO055
95
E9
GPIO124/SHD_MISO
131
G1
GPIO210
96
F8
GPIO146/PVT_CS0#
132
N4
GPIO211
97
E8
GPIO150/SHD_CS0#
133
L7
GPIO200
98
B12
GPIO157/BC_CLK
134
J7
GPIO123
99
B13
GPIO160/BC_DAT
135
H7
VCC1
100
A12
GPIO161/BC_INT#
136
F12
GPIO202
101
A13
GPIO140/TACH2/TACH2PWM_IN
137
C12
GPIO201
102
E7
GPIO045/PVT_CS1#
138
H9
VSS
103
C11
GPIO053
139
B11
GPIO203
104
J8
VSS
140
C9
VSS
105
A11
GPIO152
141
C6
106
H6
VCC1
142
M11
107
A10
GPIO030
143
D3
VSS
108
B10
GPIO012/KSO17
144
B5
VSS
Note:
GPIO204
NC
The NC pin in the 144 WFBGA package should be left unconnected on the board.
2016 Microchip Technology Inc.
DS00002022B-page 7
CEC1302
The pin name to package ball mapping of the 144 pin WFBGA package is shown in FIGURE 1-1:
FIGURE 1-1:
CEC1302 PIN NAME TO 144-PIN WFBGA BALL MAPPING (TOP)
1
A
B
C
4
5
6
7
KSO13/GPIO00 GPIO011/KSO1 GPIO024/I2C3_C
6
6
LK0
GPIO135
VSS
GPIO136/PWM1
LED0/GPIO154
KSO12/GPIO00 KSO11/GPIO10 GPIO025/I2C3_D
5
7
AT0
GPIO044
VSS
GPIO133/PWM0
GPIO163
KSO09/GPIO10 KSO10/GPIO00
6
4
GPIO036
GPIO066
GPIO034/PWM2/
TACH2PWM_OU
T
GPIO204
LED2/GPIO156
KSO08/GPIO00
3
VSS
No Ball
No Ball
No Ball
No Ball
KSO06/GPIO00 KSO07/GPIO00
1
2
VSS
No Ball
GPIO064/SHD_M GPIO054/PVT_M GPIO045/PVT_C
OSI
OSI
S1#
GPIO153/PVT_S GPIO122/SHD_S GPIO165/TXD/SH
CLK
CLK
D_CS1#
VSS
D
E
2
3
CAP
GPIO055
VSS
No Ball
GPIO210
KSO05/GPIO10
4/TFDP_CLK
GPIO067
No Ball
VCC1
VCC1
No Ball
KSO04/GPIO103/
KSO03/GPIO10 KSO01/GPIO10
TFDP_DATA/XNO
2/JTAG_TDO
0/JTAG_TMS
R
No Ball
VCC1
VCC1
VCC1
KSO02/GPIO10 KSO00/GPIO00
1/JTAG_TDI
0/JTAG_TCK
JTAG_RST#
No Ball
VCC1
VCC1
GPIO123
KSI6/GPIO042
No Ball
No Ball
No Ball
No Ball
AVCC
ADC1/GPIO057
GPIO200
GPIO151
ADC3/GPIO061
ADC2/GPIO060
AVSS
GPIO211
ADC4/GPIO062
GPIO206
ADC0/GPIO056
F
G
H
J
KSI7/GPIO043
KSI5/GPIO040
K
L
M
KSI4/GPIO142/T KSI3/GPIO032/T KSI2/GPIO144/TR Reserved/GPIO05
RACECLK
RACEDATA0
ACEDATA1
1
KSI0/GPIO125/T KSI1/GPIO126/T Reserved/GPIO05
RACEDATA3
RACEDATA2
2
GPIO127
GPIO031
GPIO147
N
DS00002022B-page 8
2016 Microchip Technology Inc.
CEC1302
8
9
I2C0_DAT0/GPIO I2C0_CLK1/GPIO
016
134
LED1/GPIO155
10
11
GPIO030
GPIO152
I2C0_DAT1/GPIO
GPIO012/KSO17
017
I2C0_CLK0/GPIO
015
VSS
No Ball
No Ball
VSS
GPIO053
13
GPIO161/BC_INT GPIO140/TACH2/
#
TACH2PWM_IN
GPIO157/BC_CL GPIO160/BC_DA
K
T
GPIO201
A
B
GPIO145
C
No Ball
GPIO150/SHD_C GPIO124/SHD_MI
S0#
SO
No Ball
GPIO146/PVT_C GPIO164/PVT_MI
S0#
SO
No Ball
GPIO141/PWM3/
LED3
GPIO132
No Ball
VCC1_RST#/GPI
O131
VSS
VSS
VSS
No Ball
GPIO203
12
No Ball
No Ball
No Ball
No Ball
GPIO020/I2C2_C
GPIO105/TACH1
LK0
GPIO162/RXD
D
GPIO021/I2C2_D GPIO022/I2C1_C GPIO023/I2C1_D
AT0
LK0
AT0
GPIO143/RSMRS
T#
GPIO202
GPIO007/KSO14
VSS
GPIO130
32KHZ_OUT/GPI
O013
VBAT
Reserved/GPIO02
6
G
GPIO110
H
XTAL1
J
VSS_VBAT
K
Reserved/GPIO11 Reserved/GPIO11 Reserved/GPIO11 Reserved/GPIO06
3
1
5
5
GPIO033
Reserved/GPIO11 Reserved/GPIO11 Reserved/GPIO01
4
7
4
GPIO035
NC
GPIO010/KSO15
F
VCC_PWRGD/G Reserved/GPIO04
PIO063
7
Reserved/GPIO04
6
E
XTAL2
L
GPIO027
M
Reserved/GPIO11 Reserved/GPIO12 LRESET#/GPIO1 Reserved/GPIO04 nRESET_OUT/G Reserved/GPIO05
2
0
16
1
PIO121
0
N
1.3.1
NON 5 VOLT TOLERANT PINS
There are no 5 Volt tolerant pins in the CEC1302.
2016 Microchip Technology Inc.
DS00002022B-page 9
CEC1302
1.3.2
POR GLITCH PROTECTED PINS
All pins in the CEC1302 have POR output glitch protection. POR output glitch protection ensures that pins will have a
steady-state output during VCC1 POR.
In addition, signals in Table 1-2 have additional drive low POR circuitry. Signals in Table 1-2 refer to Pin Reference Numbers as defined in Table 1.
These pins are anti-glitch, driven low on VCC1 POR.
TABLE 1-2:
GLITCH PROTECTED POR DRIVE LOW PINS
Pin Reference
Number
60
77
85
125
Note:
Pin Name
nRESET_OUT/GPIO121
VCC1_RST#/GPIO131
GPIO143/RSMRST#
GPIO025/I2C3_DAT0
The GPIO025/I2C3_DAT0 pin is driven low, glitch free, while VCC1 is coming up. However, after VCC1 is
up and stable, the pin becomes an input (i.e., tri-stated Open Drain type), as shown in Table 1-32, “Multiplexing Table (16 of 18),” on page 33.
The following signals require a pull-down on the board:
• nRESET_OUT/GPIO121
• GPIO143/RSMRST#
Note:
1.3.3
These glitch protected pins have no backdrive protection. See Section 1.3.3, "Non Backdrive Protected
Pins".
NON BACKDRIVE PROTECTED PINS
Table 1-3 lists pins which do not have backdrive protection. Signals in Table 1-3 refer to Pin Reference Numbers as
defined in Table 1.
These pins have no backdrive protection. If VCC1 is off must insure that none of these pins is above 0V to prevent backdrive onto the VCC1 supply.
DS00002022B-page 10
2016 Microchip Technology Inc.
CEC1302
TABLE 1-3:
NON BACKDRIVE PROTECTED PINS
Pin Reference
Number
38
39
42
43
44
46
48
50
51
52
53
54
55
57
60
69
71
77
80
85
125
1.4
1.4.1
Pin Name
ADC4/GPIO062
ADC3/GPIO061
ADC2/GPIO060
ADC1/GPIO057
ADC0/GPIO056
Reserved/GPIO112
Reserved/GPIO114
Reserved/GPIO113
Reserved/GPIO111
Reserved/GPIO120
LRESET#/GPIO116
Reserved/GPIO117
Reserved/GPIO014
Reserved/GPIO115
nRESET_OUT/GPIO121
XTAL2
XTAL1
VCC1_RST#/GPIO131
GPIO132
GPIO143/RSMRST#
GPIO025/I2C3_DAT0
Pin Description
OVERVIEW
The following tables describe the signal functions in the CEC1302 pin configuration. See Section 1.6, "Notes for Tables
in this Chapter," on page 36 for notes that are referenced in the Pin Description tables.
1.4.2
BC-LINK INTERFACE
TABLE 1-4:
BC-LINK INTERFACE
BC-Link Interface
Pin Ref. Number
98
99
100
Signal Name
BC_CLK
BC_DAT
BC_INT#
2016 Microchip Technology Inc.
Description
BC-Link Master clock
BC-Link Master data I/O
BC-Link Master interrupt
(3 Pins)
Notes
Note 7
DS00002022B-page 11
CEC1302
1.4.3
JTAG INTERFACE
TABLE 1-5:
JTAG INTERFACE
JTAG Interface
Pin Ref. Number
21
19
18
20
49
Note:
1.4.4
Signal Name
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_RST#
MASTER CLOCK INTERFACE
MASTER CLOCK INTERFACE
Master Clock Interface
Pin Ref. Number Signal Name
71
XTAL1
69
XTAL2
75
32KHZ_OUT
Description
32.768 KHz Crystal Output
32.768 KHz Crystal Input (single-ended 32.768
KHz clock input)
32.768 KHz Digital Output
(3 Pins)
Notes
Note 9
Note 9
ANALOG DATA ACQUISITION INTERFACE
TABLE 1-7:
ANALOG DATA ACQUISITION
Analog Data Acquisition Interface
Pin Ref. Number Signal Name
44
ADC0
43
ADC1
42
ADC2
39
ADC3
38
ADC4
1.4.6
Note 2
JTAG_TDO is a push-pull output. This function is not configured through the associated GPIO Pin Control
Register; however the drive strength is configured through the associated GPIO Pin Control Register 2.
TABLE 1-6:
1.4.5
(5 Pins)
Notes
Description
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
JTAG Test Reset (active low)
Description
ADC channel
ADC channel
ADC channel
ADC channel
ADC channel
0
1
2
3
4
(5 Pins)
Notes
Note 8
Note 8
Note 8
Note 8
Note 8
FAN TACHOMETER AND PWM INTERFACE
TABLE 1-8:
FAN TACHOMETER AND PWM INTERFACE
PWM & TACHOMETER
Pin Ref. Number Signal Name
92
TACH1
101
TACH2PWM_IN
120
118
78
PWM0
PWM1
PWM3
121
TACH2PWM_OUT
DS00002022B-page 12
Description
Fan Tachometer Input 2
Tach input to RPM-Based Fan Speed Control
Algorithm
Pulse Width Modulator Output 0
Pulse Width Modulator Output 1
Pulse Width Modulator Output 3
Pulse Width Modulator Output from RPM
Based Fan Speed Control Algorithm
(6 Pins)
Notes
2016 Microchip Technology Inc.
CEC1302
1.4.7
GENERAL PURPOSE I/O INTERFACE
TABLE 1-9:
GPIO INTERFACE
GPIO Interface
Pin Ref. Number Signal Name
See Pin Configuration
GPIO
Table
Note:
1.4.8
b)
c)
d)
General Purpose Input Output Pins
Note 12
MISCELLANEOUS FUNCTIONS
MISCELLANEOUS FUNCTIONS
MISC Functions
Pin Ref. Number
113
114
115
78
16
17
60
72
77
85
17
53
a)
Notes
No GPIO pin should be left floating in a system. If a GPIO pin is not in use, it should be either tied high, tied
low, or pulled to either power or ground through a resistor.
TABLE 1-10:
Note:
Description
Signal Name
LED0
LED1
LED2
LED3
TFDP_CLK
TFDP_DATA
nRESET_OUT
VCC_PWRGD
VCC1_RST#
RSMRST#
XNOR
LRESET#
Description
LED (Bllinking/Breathing PWM) Output
LED (Bllinking/Breathing PWM) Output
LED (Bllinking/Breathing PWM) Output
LED (Bllinking/Breathing PWM) Output
Trace FIFO debug port - clock
Trace FIFO debug port - data
EC-driven External System Reset
System Main Power Indication
Reset Generator Output
Resume Reset Output
Test Output
Reset Signal
(12 Pins)
Notes
0
1
2
3
Note 6
Note 6
Note 1
See Section 1.6, "Notes for Tables in this Chapter," on page 36 for numbered notes.
The nRESET_OUT pin function is an external output signal version of the internal signal nSIO_RESET. See
the iRESET_OUT bit in the Power Reset Control (PWR_RST_CTRL) Register on page 62 and nSIO_RESET in Table 3-6, “Definition of Reset Signals,” on page 44.
XNOR is a push-pull output. This function is not configured through the associated GPIO Pin Control Register; however the drive strength is configured through the associated GPIO Pin Control Register 2.
The Resume Reset Output (RSMRST#) pin drives low as a push-pull output following a VCC1 power-on until
firmware reconfigures the GPIO143 control register. This pin may be used to hold the system in reset until
the CEC1302 firmware is ready to release it.
The LRESET# system reset pin requires an external weak pull-up resistor to VCC1 of 10k-100k ohms. See
Note 1 in Section 1.6, "Notes for Tables in this Chapter," on page 36.
2016 Microchip Technology Inc.
DS00002022B-page 13
CEC1302
1.4.9
POWER INTERFACE
TABLE 1-11:
POWER INTERFACE
Power Interface
(24 Pins)
Pin Ref. Number
70
68
15
11, 36, 47, 56, 79, 82,
104, 138, 117, 140,
143, 144
14, 37, 58, 135, 84,
106, 119
45
40
Signal Name
Description
Notes
VSS_VBAT
VBAT
CAP
VBAT associated ground
VBAT supply
Internal Voltage Regulator Capacitor
Note 3
VSS
VCC1 associated ground
VCC1
VCC1 supply
AVSS
AVCC
Analog ADC supply associated ground
Analog ADC VCC1 associated Supply
APPLICATION NOTE: See FIGURE 3-1: Recommended Battery Circuit on page 42.
1.4.10
I2C/SMBUS INTERFACE
TABLE 1-12:
I2C/SMBUS INTERFACE
I2C/SMBus Interface
Pin Ref. Number
112
111
110
109
89
88
91
90
126
125
DS00002022B-page 14
Signal Name
I2C0_CLK0
I2C0_DAT0
I2C0_CLK1
I2C0_DAT1
I2C1_CLK0
I2C1_DAT0
I2C2_CLK0
I2C2_DAT0
I2C3_CLK0
I2C3_DAT0
Description
I2C/SMBus Controller 0 Port 0 Clock
I2C/SMBus Controller 0 Port 0 Data
I2C/SMBus Controller 0 Port 1 Clock
I2C/SMBus Controller 0 Port 1 Data
I2C/SMBus Controller 1 Clock
I2C/SMBus Controller 1 Data
I2C/SMBus Controller 2 Clock
I2C/SMBus Controller 2 Data
I2C/SMBus Controller 3 Clock
I2C/SMBus Controller 3 Data
(10 Pins)
Notes
2016 Microchip Technology Inc.
CEC1302
1.4.11
KEYBOARD SCAN INTERFACE
TABLE 1-13:
KEYBOARD SCAN INTERFACE
Keyboard Scan Interface
Pin Ref. Number Signal Name
29
KSI0
28
KSI1
27
KSI2
26
KSI3
25
KSI4
24
KSI5
23
KSI6
22
KSI7
21
KSO00
20
KSO01
19
KSO02
18
KSO03
17
KSO04
16
KSO05
13
KSO06
12
KSO07
10
KSO08
9
KSO09
8
KSO10
7
KSO11
6
KSO12
5
KSO13
81
KSO14
83
KSO15
4
KSO16
108
KSO17
1.4.12
Description
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Keyboard Scan Matrix
Input 0
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
Output 0
Output 1
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
Output 8
Output 9
Output 10
Output 11
Output 12
Output 13
Output 14
Output 15
Output 16
Output 17
(26 Pins)
Notes
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
Note 11
SPI CONTROLLER INTERFACE
TABLE 1-14:
SPI CONTROLLER INTERFACE
SPI Controllers Interface
Pin Ref. Number Signal Name
3
SHD_SCLK
128
SHD_MOSI
95
SHD_MISO
97
SHD_CS0#
87
SHD_CS1#
2
PVT_SCLK
127
PVT_MOSI
94
PVT_MISO
96
PVT_CS0#
102
PVT_CS1#
2016 Microchip Technology Inc.
Description
Shared SPI Clock
Shared SPI Output
Shared SPI Input
Shared SPI Chip Select 0
Shared SPI Chip Select 1
Private SPI Clock
Private SPI Output
Private SPI Input
Private SPI Chip Select 0
Private SPI Chip Select 1
(10 Pins)
Notes
Note 10
Note 10
Note 10
Note 10
Note 10
Note 10
Note 10
Note 10
DS00002022B-page 15
CEC1302
1.4.13
TRACE DEBUG INTERFACE
TABLE 1-15:
TRACE DEBUG INTERFACE
Trace Debug Interface
Pin Ref. Number Signal Name
25
TRACECLK
26
TRACEDATA0
27
TRACEDATA1
28
TRACEDATA2
29
TRACEDATA3
Description
Trace Clock
Trace Data 0
Trace Data 1
Trace Data 2
Trace Data 3
(5 Pins)
Notes
The Trace Debug Interface is enabled using the TRACE_EN bit in the ETM TRACE Enable register defined in Chapter
27.0, "EC Subsystem Registers".
Note:
1.4.14
These pins are push-pull outputs when enabled as the Trace Debug Interface pin functions. This functionality is not configured through the associated GPIO Pin Control Register; however the drive strength of
these pins is configured through the associated GPIO Pin Control Register 2.
UART PORT
TABLE 1-16:
UART PORT
UART Port
Pin Ref. Number
86
87
1.5
Signal Name
RXD
TXD
Description
UART Receive Data
UART Transmit Data
(2 Pins)
Notes
Pin Multiplexing
Multifunction Pin Multiplexing in the CEC1302 is controlled by the GPIO Interface and illustrated in the Multiplexing
Tables that follow. See Section 1.6, "Notes for Tables in this Chapter," on page 36 for notes that are referenced in the
Pin Multiplexing tables. See Section 14.8.1, "Pin Control Register," on page 153 for Pin Multiplexing programming
details. See also Section 14.7, "Pin Multiplexing Control," on page 151.
Pin signal functions that exhibit power domain emulation (see Multiplexing Tables below) have a different power supply
designation in the “Emulated Power Well” column and “Signal Power Well“ columns of the Multiplexing Tables in
Section 1.5.2.
1.5.1
VCC2 POWER DOMAIN EMULATION
The System Runtime Supply power VCC2 is not connected to the CEC1302. The VCC_PWRGD signal is used to indicate when power is applied to the System Runtime Supply.
Pin signal functions with VCC2 power domain emulation are documented in the Multiplexing Tables as “Signal Power
Well“= VCC1 and “Emulated Power Well” = VCC2. These pins are powered by VCC1 and controlled by the VCC_PWRGD signal input. Outputs on VCC2 power domain emulation pin signal functions are tri-stated when VCC_PWRGD
is not asserted and are functional when VCC_PWRGD is active. Inputs on VCC2 power domain emulation pin signal
functions are gated according as defined by the Gated State column in the following tables.
Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating
Signals field in the GPIO Pin Control Register.
DS00002022B-page 16
2016 Microchip Technology Inc.
CEC1302
1.5.2
MULTIPLEXING TABLES
In the following tables, the columns have the following meanings:
MUX
If the pin has an associated GPIO, then the MUX column refers to the Mux Control field in the GPIO Pin Control Register.
Setting the Mux Control field to value listed in the row will configure the pin for the signal listed in the Signal column on
the same row. The row marked “Default” is the setting that is assigned on system reset.
If there is no GPIO associated with a pin, then the pin has a single function.
Signal
This column lists the signals that can appear on each pin, as configured by the MUX control.
Buffer Type
Pin buffer types are defined in Table 29-4, “DC Electrical Characteristics,” on page 283.
Note that all GPIO pins are of buffer type PIO, which may be configured as input/output, push-pull/OD etc. via the GPIO
Pin Control Register and Pin Control Register 2. There are some pins where the buffer type is configured by the alternate
function selection, in which case that buffer type is shown in this column.
Default Operation
This column gives the pin behavior following the power-up of VCC1. All GPIO pins are programmable after this event.
This default pin behavior corresponds to the row marked “Default” in the MUX column.
Note:
An internal pull-up resistor is indicated by (PU) and and internal pull-down is indicated by (PD). These are
configured via the GPIO Pin Control Register.
Signal Power Well
This column defines the power well that powers the pin.
Emulated Power Well
Power well emulation for GPIOs and for signals that are multiplexed with GPIO signals is controlled by the Power Gating
Signals field in the GPIO Pin Control Register.
Power well emulation for signals that are not multiplexed with GPIO signals is defined by the entries in this column.
See Section 1.5.1, "VCC2 Power Domain Emulation".
Note:
The Glitch Protected POR Drive Low Pins are configured as “always on”, as indicated by “ON” in this column.
Gated State
This column defines the internal value of an input signal when either its emulated power well is inactive or it is not
selected by the GPIO alternate function MUX. A value of “No Gate” means that the internal signal always follows the
pin even when the emulated power well is inactive.
Note:
Gated state is only meaningful to the operation of input signals. A gated state on an output pin defines the
internal behavior of the GPIO MUX and does not imply pin behavior.
2016 Microchip Technology Inc.
DS00002022B-page 17
CEC1302
TABLE 1-17:
Pin Ref.
Number
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
MULTIPLEXING TABLE (1 OF 18)
MUX
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
0
1
2
Default: 3
0
1
2
Default: 3
0
1
2
Default: 3
0
1
2
Default: 3
DS00002022B-page 18
Signal
Buffer
Type
GPIO036
Reserved
Reserved
Reserved
GPIO153
PVT_SCLK
Reserved
Reserved
GPIO122
SHD_SCLK
Reserved
Reserved
GPIO011
Reserved
Reserved
KSO16
GPIO006
Reserved
Reserved
KSO13
GPIO005
Reserved
Reserved
KSO12
GPIO107
Reserved
Reserved
KSO11
GPIO004
Reserved
Reserved
KSO10
PIO
Reserved
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I (PU)
I
I (PD)
IOD (PD)
O-4mA
O-4mA (PD)
O-4mA
O-4mA
VCC1
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Notes
No Gate
No Gate
Note 10
Note 10
No Gate
Note 10
Note 10
No Gate
No Gate
No Gate
No Gate
No Gate
2016 Microchip Technology Inc.
CEC1302
TABLE 1-18:
Pin Ref.
Number
9
9
9
9
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
MULTIPLEXING TABLE (2 OF 18)
Signal
Buffer
Type
0
1
2
Default: 3
0
1
2
Default: 3
GPIO106
Reserved
Reserved
KSO09
GPIO003
Reserved
Reserved
KSO08
VSS
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PWR
0
1
2
Default: 3
0
1
2
Default: 3
GPIO002
Reserved
Reserved
KSO07
GPIO001
Reserved
Reserved
KSO06
VCC1
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PWR
CAP
GPIO104
TFDP_CLK
Reserved
KSO05
MUX
0
1
2
Default: 3
2016 Microchip Technology Inc.
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
PWR
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
PWR
No Gate
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
PWR
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
PWR
No Gate
PWR
PWR
PWR
PIO
PIO
Reserved
PIO
VCC1
VCC1
Reserved
VCC1
VCC1
VCC1
Reserved
VCC1
O-4mA
O-4mA
O-4mA
O-4mA
O-4mA
Notes
No Gate
No Gate
Note 3
No Gate
DS00002022B-page 19
CEC1302
TABLE 1-19:
Pin Ref.
Number
17
17
17
17
18
18
18
18
19
19
19
19
20
20
20
20
21
21
21
21
22
22
22
22
23
23
23
23
24
24
24
24
MULTIPLEXING TABLE (3 OF 18)
MUX
Default:
Default:
Default:
Default:
Default:
Default:
Default:
Default:
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
DS00002022B-page 20
Signal
Buffer
Type
GPIO103
TFDP_DATA
Reserved
KSO04
GPIO102
Reserved
Reserved
KSO03
GPIO101
Reserved
Reserved
KSO02
GPIO100
Reserved
Reserved
KSO01
GPIO000
Reserved
Reserved
KSO00
GPIO043
Reserved
Reserved
KSI7
GPIO042
Reserved
Reserved
KSI6
GPIO040
Reserved
Reserved
KSI5
PIO
PIO
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
O-4mA
O-4mA
O-4mA
O-4mA
O-4mA
I
I
I
VCC1
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Notes
No Gate
No Gate
No Gate
No Gate
No Gate
No Gate
Low
No Gate
Note 11
Low
No Gate
Note 11
Low
Note 11
2016 Microchip Technology Inc.
CEC1302
TABLE 1-20:
Pin Ref.
Number
MULTIPLEXING TABLE (4 OF 18)
MUX
25
25
25
25
26
26
26
26
27
27
27
27
28
28
28
28
29
29
29
29
30
30
30
30
31
31
31
31
32
32
32
32
Default:
Default:
Default:
Default:
Default:
Default:
Default:
Default:
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Signal
Buffer
Type
GPIO142
Reserved
Reserved
PIO
Reserved
Reserved
KSI4
GPIO032
Reserved
Reserved
KSI3
GPIO144
Reserved
Reserved
KSI2
GPIO126
Reserved
KSI1
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
PIO
Reserved
GPIO125
Reserved
KSI0
Reserved
PIO
Reserved
PIO
Reserved
GPIO031
Reserved
Reserved
Reserved
GPIO127
Reserved
Reserved
Reserved
GPIO052
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
Reserved
2016 Microchip Technology Inc.
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
Notes
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
No Gate
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
VCC1
Low
No Gate
Note 11
Low
No Gate
Note 11
Low
No Gate
Note 11
I
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
VCC1
Low
Note 11
I
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
Reserved
I
I
I
I (PU)
I
No Gate
Low
Note 11
No Gate
No Gate
No Gate
DS00002022B-page 21
CEC1302
TABLE 1-21:
Pin Ref.
Number
33
33
33
33
34
34
34
34
35
35
35
35
36
36
36
36
37
37
37
37
38
38
38
38
39
39
39
39
40
40
40
MULTIPLEXING TABLE (5 OF 18)
MUX
Default: 0
1
2
3
Default: 0
1
2
3
0
1
2
Default: 3
0
Default: 1
2
3
0
Default: 1
2
3
Signal
Buffer
Type
GPIO147
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
GPIO151
Reserved
Reserved
Reserved
GPIO051
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
VSS
Default
Signal
Emulated
Gated State Notes
Operation Power Well Power Well
I (PU)
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
Reserved
PWR
Reserved
PWR
VCC1
PWR
PWR
PWR
GPIO062
ADC4
Reserved
Reserved
GPIO061
ADC3
Reserved
Reserved
AVCC
PIO
I_AN
Reserved
Reserved
PIO
I_AN
Reserved
Reserved
PWR
I (PU)
I_AN
I_AN
VCC1
VCC1
AVCC1_ADC AVCC1_ADC
Reserved
Reserved
Reserved
Reserved
VCC1
VCC1
AVCC1_ADC AVCC1_ADC
Reserved
Reserved
Reserved
Reserved
PWR
PWR
No Gate
No Gate
No Gate
No Gate
Low
Note 8
No Gate
Low
Note 8
40
DS00002022B-page 22
2016 Microchip Technology Inc.
CEC1302
TABLE 1-22:
Pin Ref.
Number
41
41
41
41
42
42
42
42
43
43
43
43
44
44
44
44
45
45
45
45
46
46
46
46
47
47
47
47
48
48
48
48
MULTIPLEXING TABLE (6 OF 18)
Signal
Buffer
Type
Default: 0
1
2
3
0
Default: 1
2
3
0
Default: 1
2
3
0
1
2
Default: 3
GPIO206
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
GPIO060
ADC2
Reserved
Reserved
GPIO057
ADC1
Reserved
Reserved
GPIO056
ADC0
Reserved
Reserved
PIO
I_AN
Reserved
Reserved
PIO
I_AN
Reserved
Reserved
PIO
I_AN
Reserved
ADC0
AVSS
I_AN
PWR
0
1
2
Default: 3
GPIO112
Reserved
Reserved
Reserved
VSS
PCI_PIO
Reserved
Reserved
Reserved
PWR
VCC1
Reserved
Reserved
Reserved
PWR
VCC1
Reserved
Reserved
Reserved
PWR
No Gate
0
1
2
Default: 3
GPIO114
Reserved
Reserved
PCI_PIO
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
No Gate
Reserved
Reserved
Reserved
Reserved
MUX
2016 Microchip Technology Inc.
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
I_AN (PU)
I_AN
I_AN
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
Reserved
VCC1
VCC1
AVCC1_ADC AVCC1_ADC
Reserved
Reserved
Reserved
Reserved
VCC1
VCC1
AVCC1_ADC AVCC1_ADC
Reserved
Reserved
Reserved
Reserved
VCC1
VCC1
AVCC1_ADC AVCC1_ADC
Reserved
Reserved
AVCC1_ADC AVCC1_ADC
PWR
PWR
Notes
No Gate
No Gate
Low
Note 8
No Gate
Low
Note 8
No Gate
Low
Note 8
Low
Note 8
DS00002022B-page 23
CEC1302
TABLE 1-23:
Pin Ref.
Number
49
49
49
49
50
50
50
50
51
51
51
51
52
52
52
52
53
53
53
53
54
54
54
54
55
55
55
55
56
56
56
56
MULTIPLEXING TABLE (7 OF 18)
MUX
Default: 0
1
2
3
0
1
2
Default: 3
0
1
2
Default: 3
0
1
2
Default: 3
0
Default: 1
2
3
0
1
2
Default: 3
0
1
2
Default: 3
DS00002022B-page 24
Signal
Buffer
Type
JTAG_RST#
Reserved
Reserved
Reserved
GPIO113
Reserved
Reserved
I
Reserved
Reserved
Reserved
PCI_PIO
Reserved
Reserved
Reserved
GPIO111
Reserved
Reserved
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PCI_PIO
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
GPIO120
Reserved
Reserved
Reserved
PCI_PIO
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
GPIO116
LRESET#
Reserved
Reserved
GPIO117
Reserved
Reserved
Reserved
GPIO014
Reserved
Reserved
Reserved
VSS
Reserved
PCI_PIO
PCI_I
Reserved
Reserved
PCI_PIO
Reserved
Reserved
Reserved
PCI_PIO
Reserved
Reserved
Reserved
PWR
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
PCI_I
No Gate
Notes
Note 2
No Gate
No Gate
No Gate
No Gate
Low
No Gate
No Gate
2016 Microchip Technology Inc.
CEC1302
TABLE 1-24:
Pin Ref.
Number
57
57
57
57
58
58
58
MULTIPLEXING TABLE (8 OF 18)
Signal
Buffer
Type
0
1
2
Default: 3
GPIO115
Reserved
Reserved
Reserved
VCC1
PCI_PIO
Reserved
Reserved
Reserved
PWR
0
GPIO041
PIO
MUX
Default
Signal
Emulated
Gated State Notes
Operation Power Well Power Well
VCC1
Reserved
Reserved
Reserved
PWR
VCC1
Reserved
Reserved
Reserved
PWR
No Gate
VCC1
VCC1
No Gate
VCC1
ON
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
Reserved
Reserved
VCC1
ON
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
58
59
59
Default: 1
Reserved
PIO
59
59
60
60
60
60
61
61
61
61
62
62
62
62
63
63
63
63
64
64
64
64
2
Default: 3
0
Default: 1
2
3
0
1
2
Default: 3
0
1
2
Default: 3
Default: 0
1
2
3
Default: 0
1
2
3
Reserved
Reserved
GPIO121
nRESET_OUT
Reserved
Reserved
GPIO050
Reserved
Reserved
Reserved
GPIO065
Reserved
Reserved
Reserved
GPIO035
Reserved
Reserved
Reserved
GPIO027
Reserved
Reserved
Reserved
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
2016 Microchip Technology Inc.
O-8mA (PD)
LOW
O-8mA
I (PU)
I (PU)
Note 12
No Gate
Note 6
No Gate
No Gate
No Gate
No Gate
DS00002022B-page 25
CEC1302
TABLE 1-25:
Pin Ref.
Number
65
65
65
65
66
66
66
66
67
67
67
67
68
68
68
68
69
69
69
69
70
70
70
70
71
71
71
71
72
72
72
72
MULTIPLEXING TABLE (9 OF 18)
Signal
Buffer
Type
Default: 0
1
2
3
0
1
2
Default: 3
0
1
2
Default: 3
GPIO033
Reserved
Reserved
Reserved
GPIO046
Reserved
Reserved
Reserved
GPIO047
Reserved
Reserved
Reserved
VBAT
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PWR
Default: 0
1
2
3
XTAL2
Reserved
Reserved
Reserved
VSS_VBAT
Default: 0
1
2
3
0
Default: 1
2
3
XTAL1
Reserved
Reserved
Reserved
GPIO063
VCC_PWRGD
Reserved
Reserved
MUX
DS00002022B-page 26
Default
Signal
Emulated
Gated State Notes
Operation Power Well Power Well
I (PU)
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
ICLK
Reserved
Reserved
Reserved
PWR
VBAT
Reserved
Reserved
Reserved
PWR
VBAT
Reserved
Reserved
Reserved
PWR
Note 9
OCLK
Reserved
Reserved
Reserved
PIO
PIO
Reserved
Reserved
VBAT
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VBAT
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
Note 9
I
No Gate
No Gate
No Gate
No Gate
High
2016 Microchip Technology Inc.
CEC1302
TABLE 1-26:
Pin Ref.
Number
73
73
73
73
74
74
74
74
75
75
75
75
76
76
76
76
77
77
77
77
78
78
78
78
79
79
79
79
80
80
80
80
MULTIPLEXING TABLE (10 OF 18)
MUX
Default: 0
1
2
3
Default: 0
1
2
3
0
1
Default: 2
3
0
1
2
Default: 3
0
Default: 1
2
3
Default: 0
1
2
3
0
Default: 1
2
3
Default: 0
1
2
3
Signal
Buffer
Type
GPIO110
Reserved
Reserved
Reserved
GPIO130
Reserved
Reserved
Reserved
GPIO013
Reserved
32KHZ_OUT
Reserved
GPIO026
Reserved
Reserved
Reserved
GPIO131
VCC1_RST#
Reserved
Reserved
GPIO141
PWM3
LED3
Reserved
Reserved
VSS
Reserved
Reserved
GPIO132
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
PIO
Reserved
Reserved
PWR
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
2016 Microchip Technology Inc.
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
I
O-4mA
OD-4mA
I
I
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
VCC1
Reserved
Reserved
PWR
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
ON
Reserved
Reserved
VCC1
VCC1
VCC1
Reserved
Reserved
PWR
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
Notes
No Gate
No Gate
No Gate
No Gate
No Gate
High
No Gate
Reserved
No Gate
DS00002022B-page 27
CEC1302
TABLE 1-27:
Pin Ref.
Number
81
81
81
81
82
82
82
82
83
83
83
83
84
84
84
84
85
85
85
85
86
86
86
86
87
87
87
87
88
88
88
88
MULTIPLEXING TABLE (11 OF 18)
Signal
Buffer
Type
Default: 0
1
2
3
GPIO007
Reserved
Reserved
KSO14
VSS
PIO
Reserved
Reserved
PIO
PWR
I
VCC1
Reserved
Reserved
VCC1
PWR
VCC1
Reserved
Reserved
VCC1
PWR
No Gate
Default: 0
1
2
3
GPIO010
Reserved
Reserved
KSO15
VCC1
PIO
Reserved
Reserved
PIO
PWR
I
VCC1
Reserved
Reserved
VCC1
PWR
VCC1
Reserved
Reserved
VCC1
PWR
No Gate
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
GPIO143
RSMRST#
Reserved
Reserved
GPIO162
RXD
Reserved
Reserved
GPIO165
TXD
SHD_CS1#
Reserved
GPIO023
Reserved
I2C1_DAT0
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
PIO
Reserved
PIO
Reserved
PIO
Reserved
I
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
ON
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
No Gate
MUX
DS00002022B-page 28
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
I
I
Notes
Note 6
No Gate
High
No Gate
High
High
No Gate
Note 5
High
2016 Microchip Technology Inc.
CEC1302
TABLE 1-28:
Pin Ref.
Number
MULTIPLEXING TABLE (12 OF 18)
Signal
Buffer
Type
GPIO022
Reserved
I2C1_CLK0
PIO
Reserved
PIO
Reserved
GPIO021
Reserved
I2C2_DAT0
Reserved
PIO
Reserved
PIO
Reserved
GPIO020
Reserved
I2C2_CLK0
Reserved
GPIO105
TACH1
Reserved
Reserved
PIO
Reserved
PIO
Reserved
PIO
PIO
Reserved
Reserved
GPIO145
Reserved
Reserved
Reserved
GPIO164
PVT_MISO
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
PIO
Reserved
94
95
95
95
95
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Reserved
GPIO124
SHD_MISO
Reserved
Reserved
Reserved
PIO
PIO
Reserved
Reserved
96
Default: 0
GPIO146
PIO
96
96
96
1
2
3
PVT_CS0#
Reserved
Reserved
PIO
Reserved
Reserved
89
89
89
89
90
90
90
90
91
91
91
91
92
92
92
92
93
93
93
93
94
94
94
MUX
2016 Microchip Technology Inc.
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
I
I
I
I (PU)
I
I
I
VCC1
Reserved
VCC1
VCC1
Reserved
VCC1
No Gate
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
No Gate
VCC1
Reserved
Reserved
VCC1
Reserved
Reserved
High
Notes
Note 5
High
No Gate
High
No Gate
High
No Gate
Low
No Gate
No Gate
Low
Note 10
Note 10
No Gate
Low
Note 10
Note 10
Note 4,
Note 10
Note 10
DS00002022B-page 29
CEC1302
TABLE 1-29:
Pin Ref.
Number
97
97
97
97
98
98
98
98
99
99
99
99
100
100
100
100
101
101
101
101
102
102
102
102
103
103
103
103
104
104
104
MULTIPLEXING TABLE (13 OF 18)
MUX
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Signal
Buffer
Type
GPIO150
SHD_CS0#
Reserved
Reserved
GPIO157
BC_CLK
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
GPIO160
BC_DAT
Reserved
Reserved
PIO
PIO
Reserved
Reserved
GPIO161
BC_INT#
Reserved
Reserved
PIO
PIO
Reserved
Reserved
GPIO140
TACH2
Reserved
Reserved
PIO
PIO
Reserved
TACH2PWM_IN
GPIO045
Reserved
PVT_CS1#
PIO
PIO
Reserved
PIO
Reserved
GPIO053
Reserved
Reserved
Reserved
VSS
Reserved
PIO
Reserved
Reserved
Reserved
PWR
Default
Signal
Emulated
Gated State Notes
Operation Power Well Power Well
I
I (PU)
I (PU)
I (PU)
I
I
I
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
No Gate
High
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
No Gate
Low
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
No Gate
High
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
No Gate
Low
VCC1
VCC1
Reserved
VCC1
VCC1
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
Note 10
Note 10
No Gate
Note 7
Low
No Gate
High
No Gate
104
DS00002022B-page 30
2016 Microchip Technology Inc.
CEC1302
TABLE 1-30:
Pin Ref.
Number
105
105
105
105
106
106
106
106
107
107
107
107
108
108
108
108
109
109
109
109
110
110
110
110
111
111
111
111
112
112
112
112
MULTIPLEXING TABLE (14 OF 18)
Signal
Buffer
Type
Default: 0
1
2
3
GPIO152
Reserved
Reserved
Reserved
VCC1
PIO
Reserved
Reserved
Reserved
PWR
I
VCC1
Reserved
Reserved
Reserved
PWR
VCC1
Reserved
Reserved
Reserved
PWR
No Gate
Default: 0
1
2
3
Default: 0
1
2
3
0
1
Default: 2
3
0
1
Default: 2
3
0
1
Default: 2
3
0
1
Default: 2
3
GPIO030
Reserved
Reserved
Reserved
GPIO012
Reserved
Reserved
KSO17
GPIO017
Reserved
I2C0_DAT1
Reserved
GPIO134
Reserved
I2C0_CLK1
Reserved
GPIO016
Reserved
I2C0_DAT0
Reserved
GPIO015
Reserved
I2C0_CLK0
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
PIO
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
I
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
No Gate
MUX
2016 Microchip Technology Inc.
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
IOD-4mA
IOD-4mA
IOD-4mA
IOD-4mA
Notes
No Gate
No Gate
High
No Gate
High
No Gate
High
No Gate
High
DS00002022B-page 31
CEC1302
TABLE 1-31:
Pin Ref.
Number
113
113
113
113
114
114
114
114
115
115
115
115
116
116
116
116
117
117
117
117
118
118
118
118
119
119
119
119
120
120
120
120
MULTIPLEXING TABLE (15 OF 18)
Signal
Buffer
Type
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
GPIO154
Reserved
LED0
Reserved
GPIO155
Reserved
LED1
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
GPIO156
Reserved
LED2
Reserved
PIO
Reserved
PIO
Reserved
GPIO163
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
VSS
Reserved
PWR
Default: 0
1
2
3
GPIO136
PWM1
Reserved
Reserved
VCC1
PIO
PIO
Reserved
Reserved
PWR
Default: 0
1
2
3
GPIO133
PWM0
Reserved
Reserved
PIO
PIO
Reserved
Reserved
MUX
Default:
Default:
Default:
Default:
DS00002022B-page 32
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
OD-12mA
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
OD-12mA
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
Reserved
PWR
I
VCC1
VCC1
Reserved
Reserved
PWR
VCC1
VCC1
Reserved
Reserved
PWR
No Gate
I
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
No Gate
OD-12mA
I
Notes
No Gate
No Gate
No Gate
No Gate
2016 Microchip Technology Inc.
CEC1302
TABLE 1-32:
Pin Ref.
Number
121
121
121
121
122
122
122
122
123
123
123
123
124
124
124
124
125
125
125
125
126
126
126
126
127
127
127
127
128
128
128
128
MULTIPLEXING TABLE (16 OF 18)
MUX
Signal
GPIO034
Default: 0
PWM2
1
Reserved
2
3 TACH2PWM_OUT
GPIO135
Default: 0
Reserved
1
Reserved
2
3
Reserved
GPIO044
Default: 0
Reserved
1
Reserved
2
3
Reserved
GPIO066
Default: 0
Reserved
1
Reserved
2
3
Reserved
GPIO025
Default: 0
Reserved
1
I2C3_DAT0
2
3
Reserved
GPIO024
Default: 0
Reserved
1
I2C3_CLK0
2
3
Reserved
GPIO054
Default: 0
PVT_MOSI
1
Reserved
2
3
Reserved
GPIO064
Default: 0
SHD_MOSI
1
Reserved
2
3
Reserved
2016 Microchip Technology Inc.
Buffer
Type
PIO
PIO
Reserved
PIO
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
Reserved
PIO
PIO
Reserved
Reserved
PIO
PIO
Reserved
Reserved
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I
I
I
I
I
I (PU)
I
I
VCC1
VCC1
Reserved
VCC1
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
VCC1
Reserved
ON
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
Reserved
VCC1
Reserved
VCC1
VCC1
Reserved
Reserved
VCC1
VCC1
Reserved
Reserved
Reserved
Notes
No Gate
No Gate
No Gate
No Gate
No Gate
High
No Gate
High
No Gate
Note 10
Note 10
No Gate
Note 10
Note 10
DS00002022B-page 33
CEC1302
TABLE 1-33:
Pin Ref.
Number
129
129
129
129
130
130
130
130
131
131
131
131
132
132
132
132
133
133
133
133
134
134
134
134
135
135
135
135
136
136
136
136
MULTIPLEXING TABLE (17 OF 18)
Signal
Buffer
Type
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
Default: 0
1
2
3
GPIO067
Reserved
Reserved
Reserved
GPIO055
Reserved
Reserved
Reserved
GPIO210
Reserved
Reserved
Reserved
GPIO211
Reserved
Reserved
Reserved
GPIO200
Reserved
Reserved
Reserved
GPIO123
Reserved
Reserved
Reserved
VCC1
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
PWR
I (PD)
Default: 0
1
2
3
GPIO202
Reserved
Reserved
Reserved
PIO
Reserved
Reserved
Reserved
I (PD)
MUX
DS00002022B-page 34
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
I (PD)
I (PD)
I (PD)
I (PD)
I (PD)
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
VCC1
Reserved
Reserved
Reserved
PWR
ON
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
PWR
No Gate
VCC1
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
No Gate
Notes
No Gate
No Gate
No Gate
No Gate
No Gate
2016 Microchip Technology Inc.
CEC1302
TABLE 1-34:
Pin Ref.
Number
137
137
137
137
138
138
138
138
139
139
139
139
140
140
140
140
141
141
141
141
142
142
142
142
143
143
143
143
144
144
144
MULTIPLEXING TABLE (18 OF 18)
Signal
Buffer
Type
Default: 0
1
2
3
GPIO201
Reserved
Reserved
Reserved
VSS
PIO
Reserved
Reserved
Reserved
PWR
I (PD)
VCC1
Reserved
Reserved
Reserved
PWR
ON
Reserved
Reserved
Reserved
PWR
No Gate
Default: 0
1
2
3
GPIO203
Reserved
Reserved
Reserved
VSS
PIO
Reserved
Reserved
Reserved
PWR
I (PD)
VCC1
Reserved
Reserved
Reserved
PWR
ON
Reserved
Reserved
Reserved
PWR
No Gate
Default: 0
1
2
3
GPIO204
Reserved
Reserved
Reserved
NC
PIO
Reserved
Reserved
Reserved
I (PD)
VCC1
Reserved
Reserved
Reserved
ON
Reserved
Reserved
Reserved
No Gate
VSS
PWR
PWR
PWR
VSS
PWR
PWR
PWR
MUX
Default
Signal
Emulated
Gated State
Operation Power Well Power Well
Notes
144
2016 Microchip Technology Inc.
DS00002022B-page 35
CEC1302
1.6
Notes for Tables in this Chapter
Note 1
The LRESET# pin requires an external weak pull-up resistor to VCC1 of 10k-100k ohms. If the LRESET#
pin is assigned to the GPIO function rather than LRESET#, the internal LRESET# signal is gated low, and
therefore the nRESET_OUT function, the UART and the GPIO blocks will not operate properly.
Note 2
W hen the JTAG_RST# pin is not asserted (logic '1'), the JTAG_TDI, JTAG_TDO, JTAG_TCK, JTAG_TMS
signal functions in the JTAG interface are unconditionally routed to the interface; the Pin Control register for
these pins has no effect. W hen the JTAG_RST# pin is asserted (logic '0'), the JTAG_TDI, JTAG_TDO,
JTAG_TCK, JTAG_TMS signal functions in the JTAG interface are not routed to the interface and the Pin
Control Register for these pins controls the muxing. The pin control registers can not be used to route the
JTAG interface to the pins. The System Board Designer should terminate this pin in all functional states
using jumpers and pull-up or pull down resistors, etc.
An external cap must be connected as close to the CAP pin/ball as possible with a routing resistance and
CAP ESR of less than 100mohms. The capacitor value is 1uF and must be ceramic with X5R or X7R
dielectric. The cap pin/ball should remain on the top layer of the PCB and traced to the CAP. Avoid adding
vias to other layers to minimize inductance.
A pull-down is required on the GPIO146/PVT_CS0# pin if there is no private SPI flash device on the board.
Note 3
Note 4
This I2C port supports 1Mbps (pin 88, GPIO023/I2C1_DAT0 and pin 89, GPIO022/I2C1_CLK0). For 1Mbps
I2C recommended capacitance/pull-up relationships from Intel, refer to the Shark Bay platform guide, Intel
ref number 486714. Refer to the PCH - SMBus 2.0/SMLink Interface Design Guidelines, Table 20-5 Bus
Capacitance/Pull-Up Resistor Relationship.
The following glitch protected pins require a pull-down on the board: pin 60, nRESET_OUT/GPIO121 and
pin 85, GPIO143/RSMRST#. The nRESET_OUT pin will drive low when VCC1 comes on and stays low
until the iRESET_OUT bit is cleared after VCC PW RGD asserts. The RSMRST# pin also drives low (as a
GPIO push-pull output) following a VCC1 power-on until firmware deasserts it by writing the GPIO data bit
to '1'. The GPIO143/RSMRST# pin operates in this manner as a GPIO; the RSMRST# function is not a true
alternate function and the GPIO143 control register must not be changed from the GPIO default function.
Note 5
Note 6
Note
Note
Note
Note
7
8
9
10
Note 11
1.7
The BC DAT pin requires a weak pull up resistor (100 K Ohms).
The voltage on the ADC pins must not exceed 3.6 V or damage to the device will occur.
The XTAL1 pin should be left floating when using the XTAL2 pin for the single ended clock input.
The SPI pins are configured to their SPI function by ROM boot code as follows. Shared SPI pins are
configured to the following SPI functions: SHD_CLK, SHD_MOSI, SHD_MISO and SHD_CS0#. If the
PVT_CS0# pin (pin 96) is sampled high, then the private SPI pins are configured to the following SPI
functions after a successful load from flash: PVT_CLK, PVT_MOSI, PVT_MISO and PVT_CS0#; otherwise
these pins are left as the GPIO function. It is recommended that user code reconfigures the shared SPI
pins to the GPIO input function before releasing RSMRST#.
The KSI[7:0] pins have the internal pull-up enabled by ROM boot code. Therefore the Buffer Type on these
pins is I (PU) after the ROM boot code runs.
Pin States After VCC1 Power-On
Pins that default to IOD or OD in the Multiplexing Tables are open drain and come up tri-stated after VCC1 power-on.
Pins that default to I are inputs and also come up tri-stated (high-z).
Table 1-35 shows pins that have specific states after VCC1 power-on.
DS00002022B-page 36
2016 Microchip Technology Inc.
CEC1302
TABLE 1-35:
PIN STATES AFTER VCC1 POWER-ON
P in
R e fe re n c e
Num be r
21
20
19
18
17
16
13
12
10
9
8
7
6
5
113
114
115
66
61
35
P in N a m e
K S O 0 0 /G P IO 0 0 0 /J T AG _ T C K
K S O 0 1 /G P IO 1 0 0 /J T AG _ T MS
K S O 0 2 /G P IO 1 0 1 /J T AG _ T D I
K S O 0 3 /G P IO 1 0 2 /J T AG _ T D O
K S O 0 4 /G P IO 1 0 3 /T F D P _ D AT A/XN O
R
K S O 0 5 /G P IO 1 0 4 /T F D P _ C L K
K S O 0 6 /G P IO 0 0 1
K S O 0 7 /G P IO 0 0 2
K S O 0 8 /G P IO 0 0 3
K S O 0 9 /G P IO 1 0 6
K S O 1 0 /G P IO 0 0 4
K S O 1 1 /G P IO 1 0 7
K S O 1 2 /G P IO 0 0 5
K S O 1 3 /G P IO 0 0 6
L E D 0 /G P IO 1 5 4
L E D 1 /G P IO 1 5 5
L E D 2 /G P IO 1 5 6
R e s e rve d /G P IO 0 4 6
R e s e rve d /G P IO 0 5 0
R e s e rve d /G P IO 0 5 1
n R E S E T _ O U T /G P IO 1 2 1
60
VC C 1 _ R S T # /G P IO 1 3 1
77
G P IO 1 4 3 /R S MR S T #
85
125
2016 Microchip Technology Inc.
G P IO 0 2 5 /I2 C 3 _ D AT 0
P in S ta te a fte r V C C 1 P o w e r-o n
P u s h -p u ll
P u s h -p u ll
P u s h -p u ll
P u s h -p u ll
-
H ig h
H ig h
H ig h
H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
P u s h -p u ll - H ig h
O D - lo w
O D - lo w
O D - lo w
IO D - lo w
IO D - lo w
IO D - lo w
G litc h P ro te c te d - d rive n lo w w h ile VC C 1 is
ris in g .
T h e p in b e c o m e s a p u s h -p u ll o u tp u t a fte r VC C 1
is u p a n d s ta b le (re q u ire s a p u ll-d o w n o n th e
b o a rd )
G litc h P ro te c te d - d rive n lo w w h ile VC C 1 is
ris in g .
T h e p in b e c o m e s O D a fte r VC C 1 is u p a n d s ta b le
(re q u ire s a p u ll-u p o n th e b o a rd )
G litc h P ro te c te d - d rive n lo w w h ile VC C 1 is
ris in g .
T h e p in b e c o m e s a p u s h -p u ll o u tp u t a fte r VC C 1
is u p a n d s ta b le (re q u ire s a p u ll-d o w n o n th e
b o a rd )
G litc h P ro te c te d - d rive n lo w w h ile VC C 1 is ris in g .
T h e p in b e c o m e s a n in p u t (i.e ., tri-s ta te d O D typ e )
a fte r VC C 1 is u p a n d s ta b le .
DS00002022B-page 37
CEC1302
1.8
Package Outline
FIGURE 1-2:
DS00002022B-page 38
144-PIN WFBGA PACKAGE OUTLINE
2016 Microchip Technology Inc.
CEC1302
2.0
BLOCK OVERVIEW
This Chapter provides an overview of the blocks in the CEC1302.
The block diagram of the CEC1302 is shown in Figure 2-1.
FIGURE 2-1:
BLOCK DIAGRAM
Port
0
Port
1
I2C/SMB0
Shared
SPI
Master
Port
0
Port
0
Port
0
I2C/SMB1
I2C/SMB2
I2C/SMB3
Tach 0
Tach 1
Executable SRAM
Floating Point Unit
Private
SPI
Master
PWM0
PWM1
ADC Ch0-4
EC Core
Boot
ROM
ADC to
PWM
Crypto HW
via Boot ROM
PWM2
PWM3
KB Scan
Timer
16-bit x4
Timer
32-bit x2
UART
Hibernation
Timer
GPIO
RTC
WDT
LED Control (x4)
BC-Link
EC_Reg
Bank
Glue Logic
nRESET_
OUT,
VCC1
_RST#,
RSMRST#
DMA
Controller
Interrupt
Aggregater
On-Chip
Clocking
RPM_PWM
Ring
Osc
VBAT Resources
VBAT Regs.
VBAT RAM
Crystal
Osc
Clock
Gen & Dist
TFDP
Debug
and Test
Table 2-1 lists Address Ranges for each of the blocks.
2016 Microchip Technology Inc.
DS00002022B-page 39
CEC1302
TABLE 2-1:
BLOCK ADDRESS RANGES
Feature
UART
Legacy (Fast KB)
RTC
GPIO
JTAG
PCR
Interrupts
DMA
16 bit timer
16 bit timer
16 bit timer
16 bit timer
32 bit timer
32 bit timer
I2C/SMB
I2C/SMB
I2C/SMB
I2C/SMB
64 Byte VBAT RAM
VBAT Registers
RPM FAN
KeyScan
Hibernation Timer
GP-SPI
GP-SPI
ADC
PWM
PWM
PWM
PWM
TACH
TACH
WDT
TFDP
BC-Link
B/B LED
B/B LED
B/B LED
B/B LED
PKE
RNG
HASH
AES
EC_REG_BANK
Data Space SRAM
Code Space SRAM
ROM
DS00002022B-page 40
Base Address
(Hex)
400F1C00
400F1800
400F2C00
40081000
40080000
40080100
4000C000
40002400
40000C00
40000C20
40000C40
40000C60
40000C80
40000CA0
4000AC00
4000B000
4000B400
40001800
4000A800
4000A400
4000A000
40009C00
40009800
40009400
40009480
40007C00
40005800
40005810
40005820
40005830
40006000
40006010
40000400
40008C00
4000BC00
4000B800
4000B900
4000BA00
4000BB00
4000BD00
4000BE00
4000D000
4000D200
4000FC00
00118000
00100000
00000000
2016 Microchip Technology Inc.
CEC1302
3.0
POWER, CLOCKS, AND RESETS
3.1
Introduction
The Power, Clocks, and Resets (PCR) chapter identifies all the power supplies, clock sources, and reset inputs to the
chip and defines all the derived power, clock, and reset signals. In addition, this section identifies Power, Clock, and
Reset events that may be used to generate an interrupt event, as well as, the Chip Power Management Features.
3.2
References
No references have been cited for this chapter.
3.3
Interrupts
The Power, Clocks, and Resets logic generates no events
3.4
Power
3.4.1
POWER SOURCES
Table 3-1 lists the power supplies from which the CEC1302 draws current. These current values are defined in Section
29.4, "Power Consumption," on page 287.
TABLE 3-1:
Power Well
POWER SOURCE DEFINITIONS
Nominal
Voltage
Description
Source
VCC1
3.3V
Main Battery Pack Supply Power Well. Pin Interface
This is the “Always-on” supply.
VBAT
(VCC0)
(Note 3-1)
3.0V
System Battery Back-up Power Well.
This is the “coin-cell” battery.
Note:
The Minimum rise/fall time requirement on VCC1 is 200us.
Note:
The Minimum rise time requirement on VBAT is 100us.
Note 3-1
Pin Interface
Note on Battery Replacement: Microchip recommends removing all power sources to the device
defined in Table 3-1, "Power Source Definitions" before removing and replacing the battery. In
addition, upon removing the battery, ground the battery pin before replacing the battery.
APPLICATION NOTE: Battery Circuit Requirement:
• VCC0 must always be present if VCC1 is present.
2016 Microchip Technology Inc.
DS00002022B-page 41
CEC1302
The following circuit is recommended to fulfill this requirement:
FIGURE 3-1:
RECOMMENDED BATTERY CIRCUIT
3.3V nom,
from AC Source
or Battery Pack
To EC as
VCC1
(Schottky Diode)
“RTC” Rail (PCH, System)
VCC0
to EC
3.4.2
3.3V max with
VCC1 = 0V,
3.6V max with
VCC1 = VBAT
(
(Schottky
Diode)
)
Possible
Current Limiter
(1K typ.)
+
3.0V nom
Coin Cell
POWER GOOD SIGNALS
The power good timing and thresholds are defined in the Section 30.1, "Voltage Thresholds and Power Good Timing,"
on page 288.
TABLE 3-2:
POWER GOOD SIGNAL DEFINITIONS
Power Good
Signal
Description
Source
VCC1GD
VCC1GD is an internal power good signal used
to indicate when the VCC1 rail is on and stable.
VCC1GD is asserted following a delay after the
VCC1 power well exceeds its preset voltage
threshold. VCC1GD is de-asserted
as soon as this voltage drops below this threshold.
PWRGD
PWRGD is used to indicate when the main
power rail voltage is on and stable.
VCC_PWRGD Input pin
3.4.3
SYSTEM POWER SEQUENCING
The following table defines the behavior of the Power Sources in each of the defined ACPI power states.
TABLE 3-3:
TYPICAL POWER SUPPLIES VS. ACPI POWER STATES
ACPI Power State
Supply
Name
S0
(FULL
ON)
S1
(POS)
S3
(STR)
S4
(STD)
S5
(Soft Off)
G3
(MECH Off)
VCC1
ON
ON
ON
ON
ON
OFF
VBAT (VCC0)
ON
ON
ON
Note 3-2
Note 3-3
Description
CEC1302 “Always-on”
Supply. (Note 3-2)
ON
ON
ON
CEC1302 Battery Back-up
(Note 3-3)
(Note 3-3)
(Note 3-3) Supply
VCC1 power supply is always on while the battery pack or ac power is applied to the system.
This device requires that the VBAT power is on when the VCC1 power supply is on. External circuitry,
a diode isolation circuit, is implemented on the motherboard to extend the battery life. This external
circuitry ensures the VBAT pin will derive power from the VCC1 power well when it is on. Therefore,
the VBAT supply will never appear to be off when the VCC1 rail is on. See APPLICATION NOTE: on
page 41.
DS00002022B-page 42
2016 Microchip Technology Inc.
CEC1302
3.5
Clocks
The following section defines the CEC1302 clocks that are generated or referenced.
TABLE 3-4:
CLOCK DEFINITIONS
Clock Name
Frequency
SUSCLK
32.768 KHz
32.768 kHz Suspend Well Clock
Pin Interface (XTAL2)
Source is a single-ended input that is
an accurate 32.768KHz clock.
(Note 3-4)
32.768 kHz Crystal
Oscillator
32.768 KHz
A 32.768 KHz parallel resonant crystal connected between the XTAL1
and XTAL2 pins.
48 MHz Ring
Oscillator
48MHz
The 48 MHz Ring Oscillator is a high- Enabled by VCC1 Power (Note 3-5).
accuracy, low power, low start-up
May be stopped by Chip Power Manlatency 48 MHz Ring Oscillator.
agement Features.
24MHz_Clk
24 MHz
Derived clock for UART
16MHz_Clk
16MHz
Derived clock for I2C/SMBus Control- 48 MHz Ring Oscillator
ler
1.8432MHz_Clk
1.843 MHz
100kHz_Clk
100 kHz
32KHz_Clk
32.768 KHz
Note 3-4
Description
Source
Pin Interface (XTAL1 and XTAL2)
48 MHz Ring Oscillator
Derived clock for UART
48 MHz Ring Oscillator
Derived for several blocks in the EC
Subsystem, including, but not limited
to, PWM, TACH.
48 MHz Ring Oscillator
Internal 32kHz clock domain
Pin Interface:
XTAL2: 32KHz Crystal input/ singleended clock source input pin.
XTAL1: 32KHz Crystal output
The XOSEL bit configures the source
of this clock domain as either a single-ended 32.768 KHz clock input
(SUSCLK) or the 32.768 kHz Crystal
Oscillator (Note 3-6). If neither of
these is available, this clock domain
is derived from the 48 MHz Ring
Oscillator.
The chipset will not produce a valid 32KHz clock until about 5 ms (PCH) or 110 ms (ICH) after the
deassertion of RSMRST#. See chipset specification for the actual timing.
Note 3-5
The 48 MHz Ring Oscillator is reset by VCC1GD.
Note 3-6
The Clock Enable Register contains the XOSEL bit and the 32K_EN bit (see Section 5.7.2, "Clock
Enable Register," on page 68). The 32.768 KHz Oscillator provides a stable timebase for the 48 MHz
Ring Oscillator as well as the clock source for the 32KHz Clock Domain. After VBAT POR there is a
500ms max time for the 48 MHz Ring Oscillator to become accurate.
3.5.1
32KHZ CLOCK SWITCHING
The 32kHz clock switching logic switches the clock source of the 32kHz clock domain to be either the single-ended
32.768 KHz clock input or the 32.768 kHz Crystal Oscillator. If neither of these is available, this clock domain is derived
from the 48 MHz Ring Oscillator.
Following a VBAT_POR, the XOSEL bit and the 32K_EN bit in the Clock Enable Register are programmed to configure
the source of this clock domain.
If the single-ended 32.768 KHz clock input is configured as the source of the 32kHz clock domain, then following a
VCC1_RESET, the time for this clock domain to become accurate at 32.768kHz after the SUSCLK input goes active is
100us (max).
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If the 32.768 kHz Crystal Oscillator is configured as the source of the 32kHz clock domain, then following a VCC1_RESET, there is 100us (max) delay time for this clock domain to become accurate at 32.768kHz.
3.5.2
CLOCK DOMAINS VS. ACPI POWER STATES
Table 3-5, "Typical CEC1302 Clocks vs. ACPI Power States" shows the relationship between ACPI power states and
CEC1302 clock domains:
TABLE 3-5:
TYPICAL CEC1302 CLOCKS VS. ACPI POWER STATES
ACPI Power State
Clock
Name
S0
(FULL
ON)
S1
(POS)
S3
(STR)
S4
(STD)
S5
(Soft
Off)
G3
(MECH
Off)
SUSCLK
ON
ON
ON
ON
ON
OFF
This clock is the system
suspend clock source.
(Note 3-4).
32.768 kHz Crystal
Oscillator
ON
ON
ON
ON
ON
ON
This clock is generated
from a 32.768 KHz parallel resonant crystal connected between the
XTAL1 and XTAL2 pins.
32KHz_Clk
ON
ON
ON
ON
ON
48 MHz Ring Oscillator
ON
ON
ON
ON
ON
3.6
Description
ON/ OFF This clock domain is generated from the 32KHz
clock input (SUSCLK)
when available or the
crystal oscillator pins.
Otherwise it is generated
internally from the 48
MHz Ring Oscillator.
OFF
This clock is powered by
the CEC1302 suspend
supply (VCC1) but may
start and stop as
described in Section 3.7,
"Chip Power Management Features," on
page 46 (see also
Note 3-2).
Resets
TABLE 3-6:
DEFINITION OF RESET SIGNALS
Reset
Description
Source
VBAT_POR
Internal VBAT Reset signal. This signal is used
to reset VBAT powered registers.
VBAT_POR is a pulse that is asserted at the rising edge of VCC1GD if the VBAT voltage is
below a nominal 1.25V. VBAT_POR is also
asserted as a level if, while VCC1GD is not
asserted (‘0’), the coin cell is replaced with a
new cell that delivers at least a nominal 1.25V. In
this latter case VBAT_POR is de-asserted when
VCC1GD is asserted. No action is taken if the
coin cell is replaced, or if the VBAT voltage falls
below 1.25 V nominal, while VCC1GD is
asserted.
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CEC1302
TABLE 3-6:
DEFINITION OF RESET SIGNALS (CONTINUED)
Reset
Description
VCC1_RESET
LRESET#
Source
Internal VCC1 Reset signal. This signal is used VCC1_RESET is asserted when VCC1GD is low
to reset VCC1 powered registers.
and is deasserted when VCC1GD is high. The
VCC1_RST# pin asserted as input will also
cause a VCC1_RESET. A WDT_RESET event
will also cause a VCC1_RESET assertion.
System reset signal connected to the LRESET# Pin Interface, LRESET# pin. See Note 3-7.
pin.
nSIO_RESET
Performs a reset when VCC is turned off or
nSIO_RESET is a signal that is asserted if
when the system host asserts the LRESET# pin. VCC1GD is low, PWRGD is low, or LRESET# is
asserted low and may be deasserted when
these three signals are all high. The iRESET_OUT bit controls the deassertion of
nSIO_RESET. See Note 3-7.
A WDT_RESET event will also cause an
nSIO_RESET assertion.
WDT_RESET
Internal WDT Reset signal. This signal resets
VCC1 powered registers with the exception of
the WDT Event Count register. Note that the
glitch protect circuits do not activate on a WDT
reset. WDT_RESETdoes not reset VBAT
registers or logic.
EC_PROC_
RESET
Note 3-7
3.6.1
A WDT_RESET is asserted by a WDT Event.
Note:
This event is indicated by the WDT
bit in the Power-Fail and Reset Status Register
Internal reset signal to reset the processor in the An EC_PROC_ RESET is a stretched version of
EC Subsystem.
the VCC1_RESET. This reset asserts at the
same time that VCC1_RESET asserts and is
held asserted for 1ms after the VCC1_RESET
deasserts.
If the LRESET# pin is assigned to the GPIO function rather than LRESET#, the internal LRESET#
signal is gated low, and therefore the nRESET_OUT function will not operate properly.
INTEGRATED VCC1 POWER ON RESET (VCC1_RST#)
The VCC1_RST# pin is used to control the power up sequence for external devices. The VCC1_RST# timing is shown
in Section 30.1.1, "VCC1_RST# Timing," on page 288.
The following summarizes the operation of the VCC1_RST# signal.
•
•
•
•
•
The VCC1_RST# pin is both a reset input and an output to the system.
The VCC1_RST# output provides a POR reset during power up transition
The VCC1_RST# output has Output Pin Glitch Protection
The VCC1_RST# output stretches an external driven reset by 1ms (typ).
The VCC1_RST# input detects an externally driven reset and places the CEC1302 into a VCC1 POR state.
The VCC1_RST# is an open drain pin. An external pull-up is required for the VCC1_RST# signal to be high.
Note:
The external pull-up on the VCC1_RST# pin must be chosen to meet the timing in Table 30-2,
“VCC1_RST# Rise Time,” on page 288.
The following sequence illustrates the interaction between the internally and externally driven assertion of VCC1_RST#:
1.
The Integrated VCC1 Power On Reset Generator insures VCC1_RST# is driven low during a VCC1 POR from
VCC1 = 1V to 2.4V (typ) without glitches.
2. The VCC1_RST# pin is driven low during the POR transition until VCC1 > 2.4V (typ) and then the VCC1_RST#
pin remains low afterwards for 1ms (typ) delay window. The VCC1_RST# input is not examined during the 1ms
(typ) delay window; therefore, the system input and/or the external pin termination may be modified (i.e. drive it
low, let it float, etc.)
- The VCC1_RST# input is not examined during the POR transition while VCC1 < 2.4V (typ); therefore, the
system input to the VCC1_RST# pin may modify the output termination (i.e. drive it low, let it float, etc.).
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3.
The VCC1_RST# pin is driven low during the 1ms (typ) delay window. The CEC1302 is in the VCC1_POR state
during this time.
4. After the 1ms (typ) window, the VCC1_RST# pin open drain output from the CEC1302 is not driven/released. The
strap option pins are sampled at this time.
5. The CEC1302 will remain in the VCC1 POR for 2.65us (min) after the VCC1_RST# pin is released The
VCC1_RST# input pin is ignored during this time.
6. The VCC1_RST# pin input is sampled at 2.65us (min) after the VCC1_RST# pin is released.
- If the VCC1_RST# pin is high when sampled, then the EC starts executing.
- If the VCC1_RST# pin is low when sampled, the pin is being driven externally (i.e., the system is forcing a
reset):
- The VCC1_RST# pin is driven low for 1ms (typ), then sampled at 2.65us (min) after the VCC1_RST# pin is
released (see step 3).
Note 1: The minimum low pulse provided to initiate reset = 20ns.
2: There is no glitch protection or noise filtering (i.e. a vary narrow noise pulse cause a reset).
3.7
Chip Power Management Features
This device is designed to always operate in its lowest power state during normal operation. In addition, this device
offers additional programmable options to put individual logical blocks to sleep as defined in Section 3.7.1, "Block Low
Power Modes," on page 46.
3.7.1
BLOCK LOW POWER MODES
All power related control signals are generated and monitored centrally in the chip’s Power, Clocks, and Resets (PCR)
block. The power manager of the PCR block uses a sleep interface to communicate with all the blocks. The sleep interface consists of three signals:
• sleep_en (request to sleep the block) is generated by the PCR block. A group of sleep_en signals are generated for every clock segment. Each group consists of a sleep_en signal for every block in that clock segment.
• clk_req (request clock on) is generated by every block. They are grouped by blocks on the same clock segment.
The PCR monitors these signals to see when it can gate off clocks.
• reset_en (reset on sleep) bits determine if the block (including registers) will be reset when it enters sleep mode.
A block can always drive clk_req low synchronously, but it MUST drive it high asynchronously since its internal clocks
are gated and it has to assume that the clock input itself is gated. Therefore the block can only drive clk_req high as a
result of a register access or some other input signal.
The following table defines a block’s power management protocol:
Power State
sleep_en
clk_req
Description
Normal operation
Low
Low
Block is idle and NOT requesting clocks. The block gates its
own internal clock.
Normal operation
Low
High
Block is NOT idle and requests clocks.
Request sleep
Rising Edge
Low
Block is IDLE and enters sleep mode immediately. The block
gates its own internal clock. The block cannot request clocks
again until sleep_en goes low.
Request sleep
Rising Edge High then Block is not IDLE and will stop requesting clocks and enter
Low
sleep when it finishes what it is doing. This delay is block
specific, but should be less than 1 ms. The block gates its
own internal clock. After driving clk_req low, the block cannot
request clocks again until sleep_en goes low.
Register Access
Register access to a block is always available regardless of
sleep_en. Therefore the block ungates its internal clock and
drives clk_req high during the access. The block will regate
its internal clock and drive clk_req low when the access is
done.
A wake event clears all sleep enable bits momentarily, and then returns the sleep enable bits back to their original state.
The block that needs to respond to the wake event will do so. See Section 9.8.1, "WAKE Generation," on page 97.
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High
2016 Microchip Technology Inc.
CEC1302
The Sleep Enable, Clock Required and Reset Enable registers are defined in Section 3.8, "EC-Only Registers," on
page 47.
3.8
EC-Only Registers
TABLE 3-7:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
PCR
0
EC
Note 3-8
TABLE 3-8:
Address Space
32-bit internal
4008_0100h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
POWER, CLOCKS AND RESET VCC1-POWERED REGISTERS SUMMARY
Offset
Register Name
00h
Chip Sleep Enable Register (CHIP_SLP_EN)
04h
Chip Clock Required Status Registers (CHIP_CLK_REQ_STS)
08h
EC Sleep Enable Register (EC_SLP_EN)
0Ch
EC Clock Required Status Registers (EC_CLK_REQ_STS)
10h
Host Sleep Enable Register (HOST_SLP_EN)
14h
Host Clock Required Status Registers (HOST_CLK_REQ)
18h
System Sleep Control Register (SYS_SLP_CNTRL)
20h
Processor Clock Control Register (PROC_CLK_CNTRL)
24h
EC Sleep Enable 2 Register (EC_SLP_EN2)
28h
EC Clock Required 2 Status Register (EC_CLK_REQ2_STS)
2Ch
Slow Clock Control Register (SLOW_CLK_CNTRL)
30h
Oscillator ID Register (CHIP_OSC_ID)
34h
PCR chip sub-system power reset status (CHIP_PWR_RST_STS)
38h
Chip Reset Enable Register (CHIP_RST_EN)
3Ch
Host Reset Enable Register (HOST_RST_EN)
40h
EC Reset Enable Register (EC_RST_EN)
44h
EC Reset Enable 2 Register (EC_RST_EN2)
48h
Power Reset Control (PWR_RST_CTRL) Register
Note:
Base Address (Note 3-8)
All register addresses are naturally aligned on 32-bit boundaries. Offsets for registers that are smaller than
32 bits are reserved and must not be used for any other purpose.
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CEC1302
3.9
Sleep Enable and Clock Required Registers
The following are the Sleep Enable and Clock Required registers for the CEC1302.
3.9.1
CHIP SLEEP ENABLE REGISTER (CHIP_SLP_EN)
00h
Offset
Bits
Description
31:2 RESERVED
Default
Reset
Event
RES
1 MCHP Reserved (Note 3-9)
R/W
0h
0 MCHP Reserved (Note 3-9)
R/W
0h
Note 3-9
3.9.2
Type
VCC1_R
ESET
VCC1_R
ESET
MCHP Reserved bits in the sleep_en registers must be written to 1 in order for the chip to be put
into sleep mode.
CHIP CLOCK REQUIRED STATUS REGISTERS (CHIP_CLK_REQ_STS)
Offset
04h
Bits
Description
31:2 RESERVED
Type
Default
Reset
Event
RES
1 MCHP Reserved
R
0h
VCC1_R
ESET
0 MCHP Reserved
R
-
VCC1_R
ESET
Type
Default
31 TIMER16_1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-10 on page 49.
R/W
0h
VCC1_R
ESET
30 TIMER16_0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-10 on page 49.
R/W
0h
VCC1_R
ESET
29 EC_REG_BANK Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
3.9.3
EC SLEEP ENABLE REGISTER (EC_SLP_EN)
Offset
08h
Bits
Description
28:23 RESERVED
Reset
Event
RES
22 PWM3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
21 PWM2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
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CEC1302
08h
Offset
Bits
Description
20 PWM1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
19:12 RESERVED
Reset
Event
Type
Default
R/W
0h
VCC1_R
ESET
RES
11 TACH1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
10 SMB0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
9 WDT Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
8 PROCESSOR Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
7 TFDP Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
6 DMA Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
5 PMC Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
4 PWM0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
3 RESERVED
RES
2 TACH0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
1 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
0 INT Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
Note 3-10
The basic timers in this device have an auto-reload mode. When this mode is selected, the block's
clk_req equation is always asserted, which will prevent the device from gating its clock tree and going
to sleep. When the firmware intends to put the device to sleep, none of the timers should be in autoreload mode. Alternatively, use the timer's HALT function inside the control register to stop the timer
in auto-reload mode so it can go to sleep.
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CEC1302
3.9.4
EC CLOCK REQUIRED STATUS REGISTERS (EC_CLK_REQ_STS)
Offset
0Ch
Bits
Description
Reset
Event
Type
Default
31 TIMER16_1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
30 TIMER16_0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
29 EC_REG_BANK Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
28:23 RESERVED
RES
22 PWM3 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
21 PWM2 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
20 PWM1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
19:12 RESERVED
RES
11 TACH1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
10 SMB0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
9 WDT Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
8 PROCESSOR Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
1h
VCC1_R
ESET
7 TFDP Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
6 DMA Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
5 PMC Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
4 PWM0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
3 RESERVED
DS00002022B-page 50
RES
2016 Microchip Technology Inc.
CEC1302
Offset
0Ch
Bits
Description
3.9.5
Reset
Event
Type
Default
2 TACH0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
1 MCHP Reserved (Note 3-9)
R
0h
VCC1_R
ESET
0 INT Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
Type
Default
HOST SLEEP ENABLE REGISTER (HOST_SLP_EN)
Offset
10h
Bits
Description
31:19 RESERVED
RES
18 RTC Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
17 RESERVED
RES
16:12 MCHP Reserved (Note 3-9)
RES
11:2 RESERVED
3.9.6
Reset
Event
0h
VCC1_R
ESET
0h
VCC1_R
ESET
RES
1 UART 0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
0 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
HOST CLOCK REQUIRED STATUS REGISTERS (HOST_CLK_REQ)
Offset
14h
Bits
Description
31:19 RESERVED
18 RTC Clock Required
0: block does NOT need clocks.
1: block requires clocks.
17 RESERVED
16:12 MCHP Reserved
11:2 RESERVED
Type
Default
Reset
Event
RES
R
0h
VCC1_R
ESET
0h
VCC1_R
ESET
RES
RES
RES
1 UART 0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
-
VCC1_R
ESET
0 MCHP Reserved
R
-
VCC1_R
ESET
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CEC1302
3.9.7
SYSTEM SLEEP CONTROL REGISTER (SYS_SLP_CNTRL)
18h
Offset
Bits
Description
Type
31:3 RESERVED
Default
Reset
Event
RES
2 Core regulator standby
0: keep regulator fully operational when sleeping.
1: standby the regulator when sleeping. Allows enough power for
chip static operation for memory retention.
R/W
0h
VCC1_R
ESET
1 Ring oscillator output gate
0: keep ROSC ungated when sleeping.
1: gate the ROSC output when sleeping.
R/W
0h
VCC1_R
ESET
0 Ring oscillator power down
0: keep ROSC operating when sleeping.
1: disable ROSC when sleeping. Clocks will start on wakeup, but
there is a clock lock latency penalty.
R/W
0h
VCC1_R
ESET
The System Sleep States shown in Table 3-9 and determined by the bits in this register, are only entered if all blocks
are sleeping; that is, if the sleep enable bits are set for all blocks and no clocks are required.
TABLE 3-9:
SYSTEM SLEEP CONTROL BIT ENCODING
D2
D1
D0
Wake Latency
(TYP)
0
0
0
0
The Core regulator and the Ring Oscillator remain powered and running during sleep cycles (SYSTEM HEAVY SLEEP 1) (DEFAULT)
0
1
0
0
The Core regulator remains powered and the Ring oscillator is running
but gated during sleep cycles (SYSTEM HEAVY SLEEP 2)
0
X
1
200us
(Note 3-11)
The Core regulator remains powered and the Ring oscillator is powered
down during sleep cycles (SYSTEM HEAVY SLEEP 3)
1
X
1
1ms
Note 3-11
3.9.8
Description
The Core regulator is suspended and the Ring oscillator is powered
down during sleep cycles. (SYSTEM DEEPEST SLEEP)
This is the latency following a wake event until the 48 MHz Ring Oscillator is locked and clocking the
system.
PROCESSOR CLOCK CONTROL REGISTER (PROC_CLK_CNTRL)
Offset
20h
Bits
Description
31:8 RESERVED
7:0 Processor Clock Divide Value
1: divide 48 MHz Ring Oscillator by 1.
4: divide 48 MHz Ring Oscillator by 4.
16: divide 48 MHz Ring Oscillator by 16.
48: divide 48 MHz Ring Oscillator by 48.
No other values are supported.
DS00002022B-page 52
Type
Default
Reset
Event
RES
R/W
4h
VCC1_R
ESET
2016 Microchip Technology Inc.
CEC1302
3.9.9
EC SLEEP ENABLE 2 REGISTER (EC_SLP_EN2)
Offset
24h
Bits
Description
31:29 RESERVED
Type
Default
Reset
Event
RES
28 AES and HASH Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment. Register
access to this block is not available in sleep mode.
R/W
0h
VCC1_R
ESET
27 RNG Sleep Enable
0: block is free to use clocks as necessary.
1: block is powered off immediately. Clock required will de-assert.
R/W
0h
VCC1_R
ESET
26 PKE Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment. Register
access to this block is not available in sleep mode.
R/W
0h
VCC1_R
ESET
25 LED3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
24 TIMER32_1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-10 on page 49.
R/W
0h
VCC1_R
ESET
23 TIMER32_0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-10 on page 49.
R/W
0h
VCC1_R
ESET
22 TIMER16_3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-10 on page 49.
R/W
0h
VCC1_R
ESET
21 TIMER16_2_Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note 3-10 on page 49.
R/W
0h
VCC1_R
ESET
20 SPI1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
19 BCM Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
18 LED2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
17 LED1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
16 LED0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
2016 Microchip Technology Inc.
DS00002022B-page 53
CEC1302
24h
Offset
Bits
Description
Reset
Event
Type
Default
15 SMB3 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
14 SMB2 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
13 SMB1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
12 RPM-PWM Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
11 KEYSCAN Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
10 HTIMER Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
9 SPI0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
8 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
7 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
6 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
5 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
4 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
3 ADC Sleep Enable (Note 3-12)
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
2:0 Reserved
Note 3-12
R
The ADC VREF must be powered down in order to get the lowest deep sleep current. The ADC
VREF Power down bit, ADC_VREF_PD_REF is in the EC Subsystem Registers ADC VREF PD on
page 273.
DS00002022B-page 54
2016 Microchip Technology Inc.
CEC1302
3.9.10
EC CLOCK REQUIRED 2 STATUS REGISTER (EC_CLK_REQ2_STS)
Offset
28h
Bits
Description
31:29 RESERVED
Type
Default
Reset
Event
RES
28 AES and HASH Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
27 RNG Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
26 PKE Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
25 LED3 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
24 TIMER32_1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
23 TIMER32_0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
22 TIMER16_3 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
21 TIMER16_2_Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
20 SPI1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
19 BCM Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
18 LED2 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
17 LED1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
16 LED0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
15 SMB3 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
14 SMB2 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
2016 Microchip Technology Inc.
DS00002022B-page 55
CEC1302
Offset
28h
Bits
Description
Reset
Event
Type
Default
13 SMB1 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
12 RPM-PWM Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
11 KEYSCAN Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
10 HTIMER Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
9 SPI0 Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
8 MCHP Reserved
R
0h
VCC1_R
ESET
7 MCHP Reserved
R
0h
VCC1_R
ESET
6 MCHP Reserved
R
0h
VCC1_R
ESET
5 MCHP Reserved
R
0h
VCC1_R
ESET
4 MCHP Reserved
R
0h
VCC1_R
ESET
3 ADC Clock Required
0: block does NOT need clocks.
1: block requires clocks.
R
0h
VCC1_R
ESET
2:0 RESERVED
3.9.11
RES
SLOW CLOCK CONTROL REGISTER (SLOW_CLK_CNTRL)
Offset
2Ch
Bits
Description
31:10 RESERVED
9:0 Slow Clock (100 kHz) Divide Value
Configures the 100kHz_Clk.
0: Clock off
n: divide by n.
Note:
DS00002022B-page 56
Type
Default
Reset
Event
RES
R/W
1E0h
VCC1_R
ESET
The default setting is for 100 kHz.
2016 Microchip Technology Inc.
CEC1302
3.9.12
OSCILLATOR ID REGISTER (CHIP_OSC_ID)
Offset
30h
Bits
Description
31:9 RESERVED
Default
Reset
Event
RES
8 OSC_LOCK
Oscillator Lock Status
7:0 MCHP Reserved
3.9.13
Type
R
0h
VCC1_R
ESET
R
N/A
VCC1_R
ESET
PCR CHIP SUB-SYSTEM POWER RESET STATUS (CHIP_PWR_RST_STS)
Offset
34h
Bits
Description
31:11 RESERVED
10 32K_ACTIVE
This bit monitors the state of the 32K clock input. This status bit
detects edges on the clock input but does not validate the frequency.
0: The 32K clock input is not present. The internal 32K clock is
derived from the ring oscillator
1: The 32K clock input is present. The internal 32K clock is derived
from the pin and the ring oscillator is synchronized to the external
32K clock.
9:7 RESERVED
6 VCC1 reset status
Indicates the status of VCC1_RESET.
0 = No reset occurred since the last time this bit was cleared.
1 = A reset occurred.
Note:
Default
Reset
Event
RES
R
-
VCC1_R
ESET
R/WC
1h
VCC1_R
ESET
R/WC
-
VCC1_R
ESET
xh
Note 313
RES
The bit will not clear if a write 1 is attempted at the same
time that a VCC1_RST_N occurs, this way a reset event
is never missed.
5 VBAT reset status
Indicates the status of VBAT_POR.
0 = No reset occurred while VCC1 was off or since the last time this
bit was cleared.
1 = A reset occurred.
Note:
Type
The bit will not clear if a write 1 is attempted at the same
time that a VBAT_RST_N occurs, this way a reset event
is never missed.
4 RESERVED
3 SIO_Reset Status
Indicates the status of nSIO_RESET.
0 = reset active.
1 = reset not active.
2016 Microchip Technology Inc.
RES
R
DS00002022B-page 57
CEC1302
34h
Offset
Bits
Description
2 VCC Reset Status
Indicates the status of PWRGD.
0 = reset active (PWRGD not asserted).
1 = reset not active (PWRGD asserted).
1:0 RESERVED
Note 3-13
3.9.14
Type
Default
R
xh
Reset
Event
Note 313
RES
This read-only status bit always reflects the current status of the event and is not affected by any
Reset events.
CHIP RESET ENABLE REGISTER (CHIP_RST_EN)
Offset
38h
Bits
Description
31:2 RESERVED
Note:
Type
Default
Reset
Event
RES
1 MCHP Reserved
R
0h
VCC1_R
ESET
0 MCHP Reserved
R/W
0h
VCC1_R
ESET
If a block is configured such that it is to be reset when it goes to sleep, then registers within the block may
not be writable when the block is asleep.
3.9.15
HOST RESET ENABLE REGISTER (HOST_RST_EN)
Offset
3Ch
Bits
Description
31:19 RESERVED
18 RTC Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
17 RESERVED
16:12 MCHP Reserved
11:2 RESERVED
Note:
Type
Default
Reset
Event
RES
R/W
0h
VCC1_R
ESET
0h
VCC1_R
ESET
RES
RES
RES
1 UART 0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
0 MCHP Reserved
R/W
0h
VCC1_R
ESET
If a block is configured such that it is to be reset when it goes to sleep, then registers within the block may
not be writable when the block is asleep.
DS00002022B-page 58
2016 Microchip Technology Inc.
CEC1302
3.9.16
EC RESET ENABLE REGISTER (EC_RST_EN)
Offset
40h
Bits
Description
Reset
Event
Type
Default
31 TIMER16_1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
30 TIMER16_0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
29 EC_REG_BANK Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
28:23 RESERVED
RES
22 PWM3 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
21 PWM2 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
20 PWM1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
19:12 RESERVED
RES
11 TACH1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
10 SMB0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
9 WDT Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
8 PROCESSOR Sleep Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
7 TFDP Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
6 DMA Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
5 PMC Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
4 PWM0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
3 RESERVED
RES
2016 Microchip Technology Inc.
DS00002022B-page 59
CEC1302
Offset
40h
Bits
Description
Note:
Reset
Event
Type
Default
2 TACH0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
1 MCHP Reserved (Note 3-9)
R/W
0h
VCC1_R
ESET
0 INT Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
If a block is configured such that it is to be reset when it goes to sleep, then registers within the block may
not be writable when the block is asleep.
3.9.17
EC RESET ENABLE 2 REGISTER (EC_RST_EN2)
Offset
44h
Bits
Description
31:29 RESERVED
Type
Default
Reset
Event
RES
28 AES and HASH Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
27 RNG Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
26 PKE Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
25 LED3 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
24 TIMER32_1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
23 TIMER32_0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
22 TIMER16_3 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
21 TIMER16_2_Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
20 SPI1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
DS00002022B-page 60
2016 Microchip Technology Inc.
CEC1302
Offset
44h
Bits
Description
Reset
Event
Type
Default
19 BCM Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
18 LED2 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
17 LED1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
16 LED0 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
15 SMB3 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
14 SMB2 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
13 SMB1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
12 RPM-PWM Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
11 KEYSCAN Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
10 HTIMER Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
9 SPI0 Reset Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
R/W
0h
VCC1_R
ESET
8 MCHP Reserved
R/W
0h
VCC1_R
ESET
7 MCHP Reserved
R/W
0h
VCC1_R
ESET
6 MCHP Reserved
R/W
0h
VCC1_R
ESET
5 MCHP Reserved
R/W
0h
VCC1_R
ESET
4 MCHP Reserved
R/W
0h
VCC1_R
ESET
3 ADC Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
R/W
0h
VCC1_R
ESET
2:0 RESERVED
2016 Microchip Technology Inc.
RES
DS00002022B-page 61
CEC1302
Note:
If a block is configured such that it is to be reset when it goes to sleep, then registers within the block may
not be writable when the block is asleep.
3.9.18
POWER RESET CONTROL (PWR_RST_CTRL) REGISTER
48h
Offset
Bits
Description
Type
31:1 RESERVED
Default
Reset
Event
RES
0 iRESET_OUT
The iRESET_OUT bit is used by firmware to control the internal
nSIO_RESET signal function and the external nRESET_OUT pin.
The external pin nRESET_OUT is always driven by nSIO_RESET.
Firmware can program the state of iRESET_OUT except when the
VCC PWRGD bit is not asserted (‘0’), in which case iRESET_OUT is
‘don’t care’ and nSIO_RESET is asserted (‘0’) (TABLE 3-10:).
R/W
1h
VCC1_R
ESET
The internal nSIO_RESET signal is asserted when iRESET_OUT is
asserted even if the nRESET_OUT pin is configured as an alternate
function.
The iRESET_OUT bit must be cleared to take the Host out of reset.
TABLE 3-10:
iRESET_OUT BIT BEHAVIOR
nSIO_RESET &
nRESET_OUT
VCC PWRGD
iRESET_OUT
0
X
0 (ASSERTED)
The iRESET_OUT bit does not affect the state of
nSIO_RESET when VCC PWRGD is not asserted.
1
1
0 (ASSERTED)
0
1 (NOT
ASSERTED)
The iRESET_OUT bit can only be written by firmware
when VCC PWRGD is asserted.
DS00002022B-page 62
Description
2016 Microchip Technology Inc.
CEC1302
4.0
SECURITY FEATURES
4.1
Overview
This device includes a set of components that can support a high level of system security. Hardware support is provided
for:
•
•
•
•
Authentication, using public key algorithms
Integrity, using Secure Hash Algorithms (SHA)
Privacy, using symmetric encryption (Advanced Encryption Standard, AES)
Entropy, using a true Random Number Generator
4.2
References
• American National Standards Institute, “Public Key Cryptography for the Financial Services Industry: Key Agreement and Key Transport Using Elliptic Curve Cryptography”, X9.63-2011, December 2011
• American National Standards Institute, “Public Key Cryptography for the Financial Servic3es Industry: The Elliptic
Curve Digital Signature Algorithm (ECDSA)”, X9.62-2005, November 2005
• International Standards Organization, “Information Technology - Security techniques - Cryptographic techniques
based on elliptic curves -- Part 2: Digital Signatures”, ISO/IEC 15946-2, December 2002
• National Institute of Standards and Technology, “Secure Hash Standard (SHS)”, FIPS Pub 180-4, March 2012
• National Institute of Standards and Technology, “Digital Signature Standard (DSS)”, FIPS Pub 186-3, June 2009
• National Institute of Standards and Technology, “Advanced Encryption Standard (AES)”, FIPS Pub 197, November
2001
• National Institute of Standards and Technology, “Recommendation for Block Cipher Modes of Operation”, FIPS SP
800-38A, 2001
• RSA Laboratories, “PKCS#1 v2.2: RSA Cryptography Standard”, October 2012
4.3
Terminology
There is no terminology defined for this section.
4.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
2016 Microchip Technology Inc.
DS00002022B-page 63
CEC1302
FIGURE 4-1:
I/O DIAGRAM OF BLOCK
Security Features
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
4.5
Signal Description
There are no external signals for this block.
4.6
Host Interface
Registers for the cryptographic hardware are accessible by the EC.
4.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
4.7.1
POWER DOMAINS
TABLE 4-1:
4.7.2
POWER SOURCES
Name
Description
VCC1
The Security Features are all implemented on this single power domain.
CLOCK INPUTS
This block does not require any special clock inputs. All register accesses are synchronized to the host clock.
4.7.3
RESETS
TABLE 4-2:
RESET SIGNALS
Name
Description
VCC1_RESET
This signal resets all the logic and registers to their initial default state.
DS00002022B-page 64
2016 Microchip Technology Inc.
CEC1302
4.8
Interrupts
This section defines the interrupt sources generated from this block.
Source
Description
Public Key Engine
PKE_ERROR
Public Key Engine core error detected
PKE END
Public Key Engine completed processing
Symmetric Encryption
AES
Symmetric Encryption block completed processing
Cryptographic Hashing
HASH
HASH
Random Number Generator
RNG
4.9
Random Number Generator filled its FIFO
Low Power Modes
The Security Features blocks may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
4.10
Description
The security hardware incorporates the following functions.
4.10.1
SYMMETRIC ENCRYPTION/DECRYPTION
Standard AES encryption and decryption, with key sizes of 128 bits, 192 bits and 256 bits, are supported with a hardware
accelerator. AES modes that can be configured include Electronic Code Block (ECB), Cipher Block Chaining (CBC),
Counter Mode (CTR), Output Feedback (OFB) and Cipher Feedback (CFB).
4.10.2
CRYPTOGRAPHIC HASHING
Standard SHA hash algorithms, including SHA-1 and SHA-256 are supported by hardware.
4.10.3
PUBLIC KEY CRYPTOGRAPHIC ENGINE
The Public Key Crypto engine supports RSA (with & without CRT) with key sizes of 512 bits, 1024 bits and 2048 bits. It
also supports Elliptic Curve operations with standard NIST prime field curves P-192, P-224, P-256.
A large variety of public key algorithms and operations are supported directly in hardware:
• High-level prime field PK Algorithms:
- RSA – Encryption
- RSA – Decryption
- RSA – Signature Generation
- RSA – Signature Verification
- CRT – Key Parameter Generation
- CRT – Decryption
- DSA – Key Gen
- DSA – Signature Generation
- DSA – Signature Verification
- Private Key Generation
• Standard PK crypto primitives for ECC:
- Point Addition
- Point Doubling
- Point Multiplication
- Check parameters a and b
- Check n
2016 Microchip Technology Inc.
DS00002022B-page 65
CEC1302
- Check Point Coordinates
- Check_Point_On_Curve
• Standard prime field primitive arithmetic operations:
- Modular Addition
- Modular Subtraction
- Modular Multiplication
- Modular Reduction
- Modular Division
- Modular Inversion
- Multiplication
- Modular Inversion
- Modular Reduction
- Modular Exponentiation (RSA)
The Public Key Engine includes a 16KB cryptographic SRAM, which can be accessed by the EC when the engine is
not in operation. With its private SRAM memory, the Public Key Engine can process public key operations independently
of the EC.
4.10.4
TRUE RANDOM NUMBER GENERATOR
A true Random Number Generator, which includes a 1K bit FIFO for pre-calculation of random bits.
4.10.5
API FUNCTIONS
The API functions include the following:
• Functions that support loading data from a SPI Flash device
• Functions that support generating a SHA Hash on a block of data
• Functions that support RSA public key decryption of data
4.11
EC-Only Registers
TABLE 4-3:
CRYPTOGRAPHIC SRAM
Block Instance
Start Address
End Address
Size
Cryptographic SRAM
4100_0000
4010_3FFF
16KB
TABLE 4-4:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address (Note 4-1)
PKE
0
EC
32-bit internal
address space
4000_BD00h
RNG
0
EC
32-bit internal
address space
4000_BE00h
HASH
0
EC
32-bit internal
address space
4000_D000h
AES
0
EC
Note 4-1
32-bit internal
4000_D200h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
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5.0
VBAT REGISTER BANK
5.1
Introduction
This chapter defines a bank of registers powered by VBAT.
5.2
Interface
This block is designed to be accessed internally by the EC via the register interface.
5.3
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
5.3.1
POWER DOMAINS
TABLE 5-1:
POWER SOURCES
Name
Description
VBAT
5.3.2
The VBAT Register Bank are all implemented on this single power
domain.
CLOCK INPUTS
This block does not require any special clock inputs. All register accesses are synchronized to the host clock.
5.3.3
RESETS
TABLE 5-2:
5.4
RESET SIGNALS
Name
Description
VBAT_POR
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
Interrupts
TABLE 5-3:
INTERRUPT SIGNALS
Name
Description
PFR_Status
5.5
This interrupt signal from the Power-Fail and Reset Status Register
indicates VBAT RST and WDT events.
Low Power Modes
The VBAT Register Bank is designed to always operate in the lowest power consumption state.
5.6
Description
The VBAT Register Bank block is a block implemented for aggregating miscellaneous battery-backed registers required
the host and by the Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem.
5.7
EC-Only Registers
TABLE 5-4:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
VBAT_REG_BANK
0
EC
Note 5-1
Address Space
Base Address (Note 5-1)
32-bit internal
4000A400h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
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TABLE 5-5:
RUNTIME REGISTER SUMMARY
Offset
Register Name
00h
Power-Fail and Reset Status Register
04h
MCHP Reserved
08h
Clock Enable Register
5.7.1
POWER-FAIL AND RESET STATUS REGISTER
The Power-Fail and Reset Status Register collects and retains the VBAT RST and WDT event status when VCC1 is
unpowered.
Address
00h
Bits
Description
7 VBAT_RST
The VBAT RST bit is set to ‘1’ by hardware when a VBAT_POR is
detected. This is the register default value. To clear VBAT RST EC
firmware must write a ‘1’ to this bit; writing a ‘0’ to VBAT RST has no
affect.
6 Reserved
Default
R/WC
1
Reset
Event
VBAT_P
OR
RES
-
-
R/WC
0
VBAT_P
OR
RES
-
-
R
X
VBAT_P
OR
Type
Default
Reset
Event
RES
-
-
1 32K_EN
This bit controls the 32.768 KHz Crystal Oscillator as defined in
Table 5-6.
R/W
0b
VBAT_P
OR
0 XOSEL
This bit controls whether a crystal or single ended clock source is
used.
1= the 32.768 KHz Crystal Oscillator is driven by a single-ended
32.768 KHz clock source connected to the XTAL2 pin.
0= the 32.768 KHz Crystal Oscillator requires a 32.768 KHz parallel
resonant crystal connected between the XTAL1 and XTAL2 pins
(default).
R/W
0b
VBAT_P
OR
5 WDT
The WDT bit is asserted (‘1’) following a Watch-Dog Timer Forced
Reset (WDT Event). To clear the WDT bit EC firmware must write a
‘1’ to this bit; writing a ‘0’ to the WDT bit has no affect.
4:1 Reserved
0 DET32K_IN
0 = No clock detected on the XTAL[1:2] pins.
1= Clock detected on the XTAL[1:2] pins.
5.7.2
Type
CLOCK ENABLE REGISTER
Address
08h
Bits
Description
31:2 RESERVED
APPLICATION NOTE: The XOSEL bit should be correctly configured by firmware before the 32K_EN bit is
assserted.
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TABLE 5-6:
32K_EN BIT
32K_EN
32.768 KHz Crystal Oscillator
0
OFF
VBAT_POR default.
1
ON
The 32.768 KHz Crystal Oscillator can only be
enabled by firmware (Note 5-2).
Note 5-2
Description
the 48MHz Ring Oscillator must not stop before 40 s min after the 32K_EN bit is asserted.
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6.0
ARM M4F BASED EMBEDDED CONTROLLER
6.1
Introduction
This chapter contains a description of the ARM M4F Embedded Controller (EC).
The EC is built around an ARM® Cortex®-M4F Processor provided by Arm Ltd. (the “ARM M4F IP”). The ARM Cortex®
M4F is a full-featured 32-bit embedded processor, implementing the ARMv7-M THUMB instruction set and FPU instruction set in hardware.
The ARM M4F IP is configured as a Von Neumann, Byte-Addressable, Little-Endian architecture. It provides a single
unified 32-bit byte-level address, for a total direct addressing space of 4GByte. It has multiple bus interfaces, but these
express priorities of access to the chip-level resources (Instruction Fetch vs. Data RAM vs. others), and they do not
represent separate addressing spaces.
The ARM M4F IP has configurable options, which are selected as follows.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Little-Endian byte ordering is selected at all times (hard-wired)
Bit Banding feature is included for efficient bit-level access.
Floating-Point Unit (FPU) is included, to implement the Floating-Point instruction set in hardware
Debug features are included at “Ex+” level, defined as follows:
DWT Unit provides 4 Data Watchpoint comparators and Execution Monitoring
FPB Unit provides HW Breakpointing with 6 Instruction and 2 Literal (Read-Only Data) address comparators. The
FPB comparators are also available for Patching: remapping Instruction and Literal Data addresses.
Trace features are included at “Full” level, defined as follows:
DWT for reporting breakpoints and watchpoints
ITM for profiling and to timestamp and output messages from instrumented firmware builds
ETM for instruction tracing, and for enhanced reporting of Core and DWT events
The ARM-defined HTM trace feature is not currently included.
NVIC Interrupt controller with 8 priority levels and up to 240 individually-vectored interrupt inputs.
A Microchip-defined Interrupt Aggregator function (at chip level) may be used to group multiple interrupts onto single NVIC inputs.
The ARM-defined WIC feature is not currently included.
Microchip Interrupt Aggregator function (at chip level) is expected to provide Wake control instead.
The ARM-defined MPU feature is not currently included.
Memory Protection functionality is not expected to be necessary.
6.2
References
•
•
•
•
•
•
•
•
•
•
•
•
ARM Limited: Cortex®-M4 Technical Reference Manual, DDI0439C, 29 June 2010
ARM Limited: ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010
NOTE: Filename DDI0403D_arm_architecture_v7m_reference_manual_errata_markup_1_0.pdf
ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification, IHI0048A, September 2008
ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999
ARM Limited: AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006
ARM Limited: AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006
ARM Limited: Cortex-M™ System Design Kit Technical Reference Manual, DDI0479B, 16 June 2011
ARM Limited: CoreSight™ v1.0 Architecture Specification, IHI0029B, 24 March 2005
ARM Limited: CoreSight™ Components Technical Reference Manual, DDI0314H, 10 July 2009
ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006
ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-008772,
17 August 2009
• ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification, IHI0014Q, 23 September 2011
• ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual, DDI0440C, 29 June 2010
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6.3
6.3.1
Terminology
ARM IP TERMS AND ACRONYMS
• Cortex-M4F
• The ARM designation for the specific IP selected for this product: a Cortex M4 processor core containing a hardware Floating Point Unit (FPU).
• ARMv7
• The identifying name for the general architecture implemented by the Cortex-M family of IP products.
• Note that ARMv7 has no relationship to the older “ARM 7” product line, which is classified as an “ARMv3” architecture, and is very different.
• FPU
• Floating-Point Unit: a subblock included in the Core for implementing the Floating Point instruction set in hardware.
• NVIC
• Nested Vectored Interrupt Controller subblock. Accepts external interrupt inputs. See documents ARM Limited:
ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010 and ARM® Generic Interrupt Controller
Architecture version 1.0 Architecture Specification, IHI0048A, September 2008.
• FPB
• FLASH Patch Breakpoint subblock. Provides either Remapping (Address substitution) or Breakpointing (Exception or Halt) for a set of Instruction addresses and Data addresses. See Section 8.3 of ARM Limited: Cortex®-M4
Technical Reference Manual, DDI0439C, 29 June 2010.
• DAP
• Debug Access Port, a subblock consisting of DP and AP subblocks
• DP
• Any of the ports in the DAP subblock for connection to an off-chip Debugger. A single SWJ-DP option is currently
selected for this function, providing JTAG connectivity.
• SWJ-DP
• Serial Wire / JTAG Debug Port, the DP option selected by Microchip for the DAP.
• AP
• Any of the ports on the DAP subblock for accessing on-chip resources on behalf of the Debugger, independent of
processor operations. A single AHB-AP option is currently selected for this function.
• AHB-AP
• AHB Access Port, the AP option selected by Microchip for the DAP.
• MEM-AP
• A generic term for an AP that connects to a memory-mapped bus on-chip. For this product, this term is synonymous with the AHB Access Port, AHB-AP.
• ROM Table
• A ROM-based data structure in the Debug section that allows an external Debugger and/or a FW monitor to determine which of the Debug features are present.
• DWT
• Data Watchdog and Trace subblock. This contains comparators and counters used for data watchpoints and Core
activity tracing.
• ETM
• Embedded Trace Macrocell subblock. Provides enhancements for Trace output reporting, mostly from the DWT
subblock. It adds enhanced instruction tracing, filtering, triggering and timestamping.
• ITM
• Instrumentation Trace Macrocell subblock. Provides a HW Trace interface for “printf”-style reports from instrumented firmware builds, with timestamping also provided.
• TPIU
• Trace Port Interface Unit subblock. Multiplexes and buffers Trace reports from the ETM and ITM subblocks.
• TPA
• Trace Port Analyzer: any off-chip device that uses the TPIU output.
• ATB
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• Interface standard for Trace data to the TPIU from ETM and/or ITM blocks, Defined in AMBA 3. See ARM Limited:
AMBA® 3 ATB Protocol Specification, IHI0032A, 19 June 2006.
• AMBA
• The collective term for bus standards originated by ARM Limited.
• AMBA 3 defines the IP’s AHB-Lite and ATB bus interfaces.
• AMBA 2 (AMBA Rev. 2.0) defines the EC’s AHB bus interface.
• AHB
• Advanced High-Performance Bus, a system-level on-chip AMBA 2 bus standard. See ARM Limited: AMBA®
Specification (Rev 2.0), IHI0011A, 13 May 1999.
• AHB-Lite
• A Single-Master subset of the AHB bus standard: defined in the AMBA 3 bus standard. See ARM Limited:
AMBA® 3 AHB-Lite Protocol Specification, IHI0033A, 6 June 2006.
• PPB
• Private Peripheral Bus: A specific APB bus with local connectivity within the EC.
• APB
• Advanced Peripheral Bus, a limited 32-bit-only bus defined in AMBA 2 for I/O register accesses. This term is relevant only to describe the PPB bus internal to the EC core. See ARM Limited: AMBA® Specification (Rev 2.0),
IHI0011A, 13 May 1999.
• MPU
• Memory Protection Unit. This is an optional subblock that is not currently included.
• HTM
• AHB Trace Macrocell. This is an optional subblock that is not currently included.
• WIC
• Wake-Up Interrupt Controller. This is an optional subblock that is not currently included.
6.3.2
MICROCHIP TERMS AND ACRONYMS
• PMU
• This Processor Memory Unit is a module that may be present at the chip level containing any memory resources
that are closely-coupled to the CEC1302 EC. It manages accesses from both the EC processor and chip-level bus
masters.
• Interrupt Aggregator
• This is a module that may be present at the chip level, which can combine multiple interrupt sources onto single
interrupt inputs at the EC, causing them to share a vector.
6.4
ARM M4F IP Interfaces
This section defines only the interfaces to the ARM IP itself. For the interfaces of the entire block, see Section 6.5, "Block
External Interfaces," on page 74.
The CEC1302 IP has the following major external interfaces, as shown in FIGURE 6-1: ARM M4F Based Embedded
Controller I/O Block Diagram on page 74:
•
•
•
•
•
•
ICode AHB-Lite Interface
DCode AHB-Lite Interface
System AHB-Lite Interface
Debug (JTAG) Interface
Trace Port Interface
Interrupt Interface
The EC operates on the model of a single 32-bit addressing space of byte addresses (4Gbytes, Von Neumann architecture) with Little-Endian byte ordering. On the basis of an internal decoder (part of the Bus Matrix shown in Figure 61), it routes Read/Write/Fetch accesses to one of three external interfaces, or in some cases internally (shown as the
PPB interface).
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The EC executes instructions out of closely-coupled memory via the ICode Interface. Data accesses to closely-coupled
memory are handled via the DCode Interface. The EC accesses the rest of the on-chip address space via the System
AHB-Lite interface. The Debugger program in the host can probe the EC and all EC addressable memory via the JTAG
debug interface.
Aliased addressing spaces are provided at the chip level so that specific bus interfaces can be selected explicitly where
needed. For example, the EC’s Bit Banding feature uses the System AHB-Lite bus to access resources normally
accessed via the DCode or ICode interface.
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6.5
Block External Interfaces
FIGURE 6-1:
ARM M4F BASED EMBEDDED CONTROLLER I/O BLOCK DIAGRAM
ARM_M4F EC Block
Chip-level JTAG TAP
DAP
Debug Access Port
Mux
TPIU
Trace Port Interface
ETM / ITM
Trace Outputs
Debug
Host
Directly Vectored
Connections
Processor
Core w/ FPU
Pulse
Sync &
Stretch
Grouped
(Summary)
Interrupts
Interrupts
NVIC
Nested
Vectored
Interrupt
Controller
Interrupt
Aggregator
ARM_M4F IP
Optionally
Grouped
Inputs
Unconditionally
Grouped Inputs
Clock
Gate
ICode
Interface
(AHB-Lite)
DCode
Interface
(AHB-Lite)
System
Interface
(AHB-Lite)
Chip-Level
Clock
Processor
Clock
Divider
Processor Reset
Core Reset (POR)
AMBA 2
AHB Adapt
Memory
Memory
Bus Adapt Bus Adapt
Misc. Sideband
Code
Port
Data
Port
PMC Block
(RAM / ROM)
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AHB
Port
Chip-Level
System Bus
(AMBA 2 AHB)
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6.6
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
6.6.1
POWER DOMAINS
TABLE 6-1:
POWER SOURCES
Name
VCC1
6.6.2
Description
The ARM M4F Based Embedded Controller is powered by VCC1.
CLOCK INPUTS
6.6.2.1
Basic Clocking
The basic clocking comes from a free-running Clock signal provided from the chip level.
TABLE 6-2:
CLOCK INPUTS
Name
48 MHz Ring Oscillator
Description
The EC clock derived from the 48 MHz Ring Oscillator is the clock
source to the ARM M4F Based Embedded Controller. Division of the
clock rate is allowed, according to the Processor Clock Enable.
Note:
6.6.2.2
The EC clock is controlled from the chip-level Power, Clocks,
and Reset (PCR) circuitry. See Section 3.9.8, "Processor
Clock Control Register (PROC_CLK_CNTRL)," on page 52.
System Tick Clocking
The System Tick clocking is controlled by a signal from chip-level logic. It is the 48 MHz Ring Oscillator divided by the
following:
- ((Processor Clock Divide Value)x2)+1.
6.6.2.3
Debug JTAG Clocking
The Debug JTAG clocking comes from chip-level logic, which may multiplex or gate this clock. See Section 6.9.3,
"Debugger Access Support," on page 78.
6.6.2.4
Trace Clocking
The Clock for the Trace interface is identical to the 48 MHz Ring Oscillator input.
6.6.3
RESETS
The reset interface from the chip level is given below.
TABLE 6-3:
RESET SIGNALS
Name
EC_PROC_ RESET
6.7
Description
The ARM M4F Based Embedded Controller is reset by EC_PROC_
RESET.
Interrupts
The ARM M4F Based Embedded Controller is equipped with an Interrupt Interface to respond to interrupts. These inputs
go to the IP’s NVIC block after a small amount of hardware processing to ensure their detection at varying clock rates.
See FIGURE 6-1: ARM M4F Based Embedded Controller I/O Block Diagram on page 74.
As shown in Figure 6-1, an Interrupt Aggregator block may exist at the chip level, to allow multiple related interrupts to
be grouped onto the same NVIC input, and so allowing them to be serviced using the same vector. This may allow the
same interrupt handler to be invoked for a group of related interrupt inputs. It may also be used to expand the total number of interrupt inputs that can be serviced.
Connections to the chip-level system are given in Table 9-3, “Interrupt Event Aggregator Routing Summary,” on
page 98.
The NMI (Non-Maskable Interrupt) connection is tied off and not used.
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6.7.1
NVIC INTERRUPT INTERFACE
The NVIC interrupt unit can be wired to up to 240 interrupt inputs from the chip level. The interrupts that are actually
connected from the chip level are defined in Table 9-3, “Interrupt Event Aggregator Routing Summary,” on page 98.
All NVIC interrupt inputs can be programmed as either pulse or level triggered. They can also be individually masked,
and individually assigned to their own hardware-managed priority level.
6.7.2
NVIC RELATIONSHIP TO EXCEPTION VECTOR TABLE ENTRIES
The Vector Table consists of 4-byte entries, one per vector. Entry 0 is not a vector, but provides an initial Reset value
for the Main Stack Pointer. Vectors start with the Reset vector, at Entry #1. Entries up through #15 are dedicated for
internal exceptions, and do not involve the NVIC.
NVIC entries in the Vector Table start with Entry #16, so that NVIC Interrupt #0 is at Entry #16, and all NVIC interrupt
numbers are incremented by 16 before accessing the Vector Table.
The number of connections to the NVIC determines the necessary minimum size of the Vector Table, as shown below.
It can extend as far as 256 entries (255 vectors, plus the non-vector entry #0).
A Vector entry is used to load the Program Counter (PC) and the EPSR.T bit. Since the Program Counter only expresses
code addresses in units of two-byte Halfwords, bit[0] of the vector location is used to load the EPSR.T bit instead, selecting THUMB mode for exception handling. Bit[0] must be ‘1’ in all vectors, otherwise a UsageFault exception will be
posted (INVSTATE, unimplemented instruction set). If the Reset vector is at fault, the exception posted will be HardFault
instead.
TABLE 6-4:
Table Entry
EXCEPTION AND INTERRUPT VECTOR TABLE LAYOUT
Exception
Number
Exception
Special Entry for Reset Stack Pointer
0
(none)
Holds Reset Value for the Main Stack Pointer. Not a Vector.
Core Internal Exception Vectors start here
1
1
Reset Vector (PC + EPSR.T bit)
2
2
NMI (Non-Maskable Interrupt) Vector
3
3
HardFault Vector
4
4
MemManage Vector
5
5
BusFault Vector
6
6
UsageFault Vector
7
(none)
(Reserved by ARM Ltd.)
8
(none)
(Reserved by ARM Ltd.)
9
(none)
(Reserved by ARM Ltd.)
10
(none)
(Reserved by ARM Ltd.)
11
11
SVCall Vector
12
12
Debug Monitor Vector
13
(none)
14
14
PendSV Vector
15
15
SysTick Vector
(Reserved by ARM Ltd.)
NVIC Interrupt Vectors start here
16
16
.
.
.
.
.
.
n + 16
n + 16
.
.
.
.
.
.
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NVIC Interrupt #0 Vector
.
.
.
NVIC Interrupt #n Vector
.
.
.
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TABLE 6-4:
EXCEPTION AND INTERRUPT VECTOR TABLE LAYOUT (CONTINUED)
Table Entry
Exception
Number
max + 16
max + 16
.
.
.
.
.
.
255
255
6.8
Exception
NVIC Interrupt #max Vector (Highest-numbered NVIC connection.)
. Table size may (but need not) extend further.
.
.
NVIC Interrupt #239 (Architectural Limit of Exception Table)
Low Power Modes
The ARM processor low power modes are handled through the Power, Clocks, and Resets registers, not directly through
the ARM core registers. See Section 3.7, "Chip Power Management Features," on page 46.
The ARM processor can enter Sleep or Deep Sleep mode internally. This action will cause an output signal Clock
Required to be turned off, allowing clocks to be stopped from the chip level. However, Clock Required will still be held
active, or set to active, unless all of the following conditions exist:
• No interrupt is pending.
• An input signal Sleep Enable from the chip level is active.
• The Debug JTAG port is inactive (reset or configured not present).
In addition, regardless of the above conditions, a chip-level input signal Force Halt may halt the processor and remove
Clock Required.
6.9
6.9.1
Description
BUS CONNECTIONS
There are three bus connections used from CEC1302 EC block, which are directly related to the IP bus ports. See FIGURE 6-1: ARM M4F Based Embedded Controller I/O Block Diagram on page 74.
For the mapping of addresses at the chip level, see Chapter 2.0, "Block Overview," on page 40.
6.9.1.1
Closely Coupled Instruction Fetch Bus
As shown in Figure 6-1, the AHB-Lite ICode port from the IP is converted to a more conventional SRAM memory-style
bus and connected to the on-chip memory resources with routing priority appropriate to Instruction Fetches.
6.9.1.2
Closely Coupled Data Bus
As shown in Figure 6-1, the AHB-Lite DCode port from the IP is converted to a more conventional SRAM memory-style
bus and connected to the on-chip memory resources with routing priority appropriate to fast Data Read/Write accesses.
6.9.1.3
Chip-Level System Bus
As shown in Figure 6-1, the AHB-Lite System port from the IP is converted from AHB-Lite to fully arbitrated multi-master
capability (the AMBA 2 defined AHB bus: see ARM Limited: AMBA® Specification (Rev 2.0), IHI0011A, 13 May 1999).
Using this bus, all addressable on-chip resources are available. The multi-mastering capability supports the Microchip
DMA and EMI features if present, as well as the Bit-Banding feature of the IP itself.
As also shown in Figure 6-1, the Closely-Coupled memory resources are also available through this bus connection
using aliased addresses. This is required in order to allow Bit Banding to be used in these regions, but it also allows
them to be accessed by DMA and other bus masters at the chip level.
APPLICATION NOTE: Registers with properties such as Write-1-to-Clear (W1C), Read-to-Clear and FIFOs need to
be handled with appropriate care when being used with the bit band alias addressing
scheme. Accessing such a register through a bit band alias address will cause the hardware
to perform a read-modify-write, and if a W1C-type bit is set, it will get cleared with such an
access. For example, using a bit band access to the Interrupt Aggregator, including the
Interrupt Enables and Block Interrupt Status to clear an IRQ will clear all active IRQs.
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6.9.2
INSTRUCTION PIPELINING
There are no special considerations except as defined by ARM documentation.
6.9.3
DEBUGGER ACCESS SUPPORT
An external Debugger accesses the chip through a JTAG standard interface. The debugger itself, however, is not an
ARM product, and its capabilities will depend on the third-party product selected for code development and debug.
As shown in FIGURE 6-1: ARM M4F Based Embedded Controller I/O Block Diagram on page 74, there may be other
resources at the chip level that share the JTAG port pins; for example chip-level Boundary Scan. See Section 1.4.3,
"JTAG Interface," on page 12 for configuring the JTAG pins at the chip level for Debug purposes.
6.9.3.1
Debug and Access Ports (SWJ-DP and AHB-AP Subblocks)
These two subblocks work together to provide access to the chip for the Debugger using the Debug JTAG connection,
as described in Chapter 4 of the ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006.
6.9.4
BREAKPOINT, WATCHPOINT AND TRACE SUPPORT
See ARM Limited: ARM® Debug Interface v5 Architecture Specification, IHI0031A, 8 February 2006 and also ARM Limited: ARM® Debug Interface v5 Architecture Specification ADIv5.1 Supplement, DSA09-PRDC-008772, 17 August
2009. A summary of functionality follows.
Breakpoint and Watchpoint facilities can be programmed to do one of the following:
• Halt the processor. This means that the external Debugger will detect the event by periodically polling the state of
the EC.
• Transfer control to an internal Debug Monitor firmware routine, by triggering the Debug Monitor exception (see
Table 6-4, “Exception and Interrupt Vector Table Layout,” on page 76).
6.9.4.1
Instrumentation Support (ITM Subblock)
The Instrumentation Trace Macrocell (ITM) is for profiling software. This uses non-blocking register accesses, with a
fixed low-intrusion overhead, and can be added to a Real-Time Operating System (RTOS), application, or exception
handler. If necessary, product code can retain the register access instructions, avoiding probe effects.
6.9.4.2
HW Breakpoints and ROM Patching (FPB Subblock)
The Flash Patch and Breakpoint (FPB) block. This block can remap sections of ROM, typically Flash memory, to regions
of RAM, and can set breakpoints on code in ROM. This block can be used for debug, and to provide a code or data
patch to an application that requires field updates to a product in ROM.
6.9.4.3
Data Watchpoints and Trace (DWT Subblock)
The Debug Watchpoint and Trace (DWT) block provides watchpoint support, program counter sampling for performance
monitoring, and embedded trace trigger control.
6.9.4.4
Trace Interface (ETM and TPIU)
The Embedded Trace Macrocell (ETM) provides instruction tracing capability. For details of functionality and usage, see
also ARM Limited: Embedded Trace Macrocell™ (ETMv1.0 to ETMv3.5) Architecture Specification, IHI0014Q, 23 September 2011 and ARM Limited: CoreSight™ ETM™-M4 Technical Reference Manual, DDI0440C, 29 June 2010.
The Trace Port Interface Unit (TPIU) provides the external interface for the ITM, DWT and ETM.
See Section 1.4.13, "Trace Debug Interface," on page 16 for configuring the Trace pins at the chip level for Trace output.
6.10
ARM Configuration
In order to function correctly, it is necessary to set the ARM Auxiliary Control Register (ACTLR), located at address 0xE000E008, to 0x02. This sets bit[1], DISDEFWBUF, to 1. This must be done as soon as possible after Power On Reset,
or register corruption may occur.
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CEC1302
7.0
RAM AND ROM
SRAM
The 128KBytes SRAM (Code or Data) is allocated as follows:
• 96K Optimized for Code
• 32K Optimized for Data.
Note:
120KBytes are available for application code as follows: 96K Optimized for Code, 24K Optimized for Data.
The distinction between “96KB optimized for instructions” and “32KB optimized for data” SRAMs: is as follows:
The CEC1302 has two blocks of SRAM, one of 96KB and one of 32KB. Both can be used for either instructions or
data. As long as the ARM fetches instructions from one SRAM and does loads and stores to the other, code and data
accesses operate in parallel and there are no wait states. If on the same cycle the ARM fetches an instruction and
does a load or a store to the same SRAM, either the code fetch will be delayed by one cycle or the data access will be
delayed by one cycle. The 96KB SRAM is optimized for instructions, in that if the ARM accesses this SRAM for both
instructions and data on the same cycle, the instruction fetch will complete in one cycle and the load/store will be
delayed for one cycle. The 32KB SRAM is optimized for data, in that if the ARM accesses this SRAM for both
instructions and data on the same cycle, the load/store will complete in once cycle and the instruction fetch will be
delayed for one cycle. In both cases, the SRAM arbiter ensures that the arbitration loser will win on subsequent cycles
and thus will not be locked out of the SRAM indefinitely. User applications, therefore, are free to allocate code and data
anywhere in the 128KB SRAM address space, except that there will be an occasional small performance hit if both
code and data are allocated in the same SRAM.
The application loader in the CEC1302 ROM requires the top 8KB of the 32KB SRAM in order to perform its functions.
The user can therefore load a maximum of 120KB into SRAM using the ROM loader. Once the ROM application loader
has completed its operation, the entire 128KB address space can be allocated to whatever functions, code or data, the
user wishes.
The SRAM is located at EC Base address 00100000h in 32-bit internal address space.
Note:
120KB is available for application code in the address range 00100000h to 0011DFFFh
ROM
The 32KByte Boot ROM is located at EC Base address 00000000h in 32-bit internal address space.
Note:
30KB is available for application code in the address range 00000000h to 000077FFh
The memory map of the RAM and ROM is represented as follows:
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CEC1302
FIGURE 7-1:
MEMORY LAYOUT
0x4010_3FFF
SPB
H ost
access
0x4000_0000
0x220F_FFFF
0x2200_0000
0x2000_7FFF
0x2000_0000
1M B D ata RAM
R eserved for AR M
Bit Band Alias
Region
32KB Alias D ata
R AM
0x0011_FFFF
32KB D ata R AM
0x0011_8000
0x0011_7FFF
ARM
access
only
H ost
access
ARM
access
only
96KB C ode R AM
H ost
access
32KB Boot R O M
H ost
read
access
0x0010_0000
0x0000_7FFF
0x0000_0000
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CEC1302
8.0
UART
8.1
Introduction
The 16550 UART (Universal Asynchronous Receiver/Transmitter) is a full-function Two Pin Serial Port that supports the
standard RS-232 Interface.
8.2
1.
8.3
References
EIA Standard RS-232-C specification
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 8-1:
I/O DIAGRAM OF BLOCK
UART
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
8.4
Signal Description
TABLE 8-1:
8.5
SIGNAL DESCRIPTION TABLE
Name
Direction
Description
TXD
Output
Transmit serial data output.
RXD
Input
Receiver serial data input.
Host Interface
The UART is accessed by host software via a registered interface, as defined in Section 8.10, "Configuration Registers"and Section 8.11, "Runtime Registers".
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8.6
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
8.6.1
POWER DOMAINS
TABLE 8-2:
POWER SOURCES
Name
VCC1
8.6.2
Description
This Power Well is used to power the registers and logic in this block.
CLOCK INPUTS
TABLE 8-3:
CLOCK INPUTS
Name
1.8432MHz_Clk
24MHz_Clk
8.6.3
Description
The UART requires a 1.8432 MHz ± 2% clock input for baud rate
generation.
24 MHz ± 2% clock input. This clock may be enabled to generate the
baud rate, which requires a 1.8432 MHz ± 2% clock input.
RESETS
TABLE 8-4:
RESET SIGNALS
Name
This reset is asserted when VCC1 is applied.
nSIO_RESET
This is an alternate reset condition, typically asserted when the main
power rail is asserted.
RESET
8.7
Description
VCC1_RESET
This reset is determined by the POWER bit signal. When the power bit
signal is 1, this signal is equal to nSIO_RESET. When the power bit
signal is 0, this signal is equal to VCC1_RESET.
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 8-5:
TABLE 8-6:
8.8
SYSTEM INTERRUPTS
Source
Description
UART
The UART interrupt event output indicates if an interrupt is pending. See
Table 8-13, “Interrupt Control Table,” on page 89.
EC INTERRUPTS
Source
Description
UART
The UART interrupt event output indicates if an interrupt is pending. See
Table 8-13, “Interrupt Control Table,” on page 89.
Low Power Modes
The UART may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
8.9
Description
The UART is compatible with the 16450, the 16450 ACE registers and the 16C550A. The UART performs serial-to-parallel conversions on received characters and parallel-to-serial conversions on transmit characters. Two sets of baud
rates are provided. When the 1.8432 MHz source clock is selected, standard baud rates from 50 to 115.2K are available.
When the source clock is 32.26 MHz, baud rates from 126K to 2,016K are available. The character options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UART contains a
programmable baud rate generator that is capable of dividing the input clock signal by 1 to 65535. The UART is also
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CEC1302
capable of supporting the MIDI data rate. Refer to the Configuration Registers for information on disabling, powering
down and changing the base address of the UART. The UART interrupt is enabled by programming OUT2 of the UART
to logic “1.” Because OUT2 is logic “0,” it disables the UART's interrupt. The UART is accessible by both the Host and
the EC.
8.9.1
PROGRAMMABLE BAUD RATE
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal clock source by
any divisor from 1 to 65535. The clock source is either the 1.8432MHz_Clk clock source or the 24MHz_Clk clock source.
The output frequency of the Baud Rate Generator is 16x the Baud rate. Two eight bit latches store the divisor in 16 bit
binary format. These Divisor Latches must be loaded during initialization in order to ensure desired operation of the
Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is loaded into the BRG registers, the output divides the clock by the number
3. If a 1 is loaded, the output is the inverse of the input oscillator. If a two is loaded, the output is a divide by 2 signal with
a 50% duty cycle. If a 3 or greater is loaded, the output is low for 2 bits and high for the remainder of the count.
The following tables show possible baud rates.
TABLE 8-7:
UART BAUD RATES USING CLOCK SOURCE 1.8432MHz_Clk
Desired Baud Rate
BAUD_CLOCK_SEL
Divisor Used to Generate
16X Clock
50
0
2304
75
0
1536
110
0
1047
134.5
0
857
150
0
768
300
0
384
600
0
192
1200
0
96
1800
0
64
2000
0
58
2400
0
48
3600
0
32
4800
0
24
7200
0
16
9600
0
12
19200
0
6
38400
0
3
57600
0
2
115200
0
1
TABLE 8-8:
UART BAUD RATES USING CLOCK SOURCE 24MHz_Clk
Desired Baud Rate
BAUD_CLOCK_SEL
Divisor Used to Generate
16X Clock
125000
1
12
136400
1
11
150000
1
10
166700
1
9
187500
1
8
214300
1
7
250000
1
6
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TABLE 8-8:
UART BAUD RATES USING CLOCK SOURCE 24MHz_Clk (CONTINUED)
Desired Baud Rate
BAUD_CLOCK_SEL
Divisor Used to Generate
16X Clock
300000
1
5
375000
1
4
500000
1
3
750000
1
2
1500000
1
1
8.10
Configuration Registers
The registers listed in the Configuration Register Summary table are for a single instance of the UART. The addresses
of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the Configuration
Register Base Address Table.
FIGURE 8-2:
CONFIGURATION REGISTER BASE ADDRESS TABLE
Block Instance
UART
Instance
Number
Logical
Device
Number
0
Host
EC
Address Space
Base Address
32-bit internal
address space
400F_1F00h
Each Configuration register access through the Host Access Port is via its LDN and its Host Access Port Index. EC
access is a relative offset to the EC Base Address.
TABLE 8-9:
CONFIGURATION REGISTER SUMMARY
Offset
Register Name (Mnemonic)
30h
Activate Register
F0h
Configuration Select Register
8.10.1
ACTIVATE REGISTER
Offset
30h
Bits
Description
7:1 Reserved
0 ACTIVATE
When this bit is 1, the UART logical device is powered and functional. When this bit is 0, the UART logical device is powered down
and inactive.
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Type
Default
Reset
Event
R
-
-
R/W
0b
RESET
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CEC1302
8.10.2
CONFIGURATION SELECT REGISTER
F0h
Offset
Bits
Description
Type
7:3 Reserved
2 POLARITY
Default
Reset
Event
R
-
-
R/W
0b
RESET
R/W
1b
RESET
R/W
0b
RESET
1=The UART_TX and UART_RX pins functions are inverted
0=The UART_TX and UART_RX pins functions are not inverted
1 POWER
1=The RESET reset signal is derived from nSIO_RESET
0=The RESET reset signal is derived from VCC1_RESET
0 CLK_SRC
1=The UART Baud Clock is derived from an external clock source
0=The UART Baud Clock is derived from one of the two internal clock
sources
8.11
Runtime Registers
The registers listed in the Runtime Register Summary table are for a single instance of the UART. The addresses of
each register listed in this table are defined as a relative offset to the host “Base Address” defined in Runtime Register
Base Address Table.
TABLE 8-10:
RUNTIME REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address (Note 8-1)
UART
0
EC
32-bit internal
address space
400F_1C00h
Note 8-1
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 8-11:
RUNTIME REGISTER SUMMARY
DLAB
(Note 8-2)
Offset
0
0h
Receive Buffer Register
0
0h
Transmit Buffer Register
1
0h
Programmable Baud Rate Generator LSB Register
1
1h
Programmable Baud Rate Generator MSB Register
0
1h
Interrupt Enable Register
x
02h
FIFO Control Register
x
02h
Interrupt Identification Register
x
03h
Line Control Register
x
04h
Modem Control Register
x
05h
Line Status Register
x
06h
Modem Status Register
x
Note 8-2
Register Name (Mnemonic)
07h
Scratchpad Register
DLAB is bit 7 of the Line Control Register.
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8.11.1
RECEIVE BUFFER REGISTER
Offset
0h (DLAB=0)
Bits
Description
7:0 RECEIVED_DATA
This register holds the received incoming data byte. Bit 0 is the least
significant bit, which is transmitted and received first. Received data
is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is
transferred to the Receive Buffer register. The shift register is not
accessible.
8.11.2
Type
Default
Reset
Event
R
0h
RESET
Type
Default
Reset
Event
W
0h
RESET
Type
Default
Reset
Event
R/W
0h
RESET
Type
Default
Reset
Event
R/W
0h
RESET
R/W
0h
RESET
TRANSMIT BUFFER REGISTER
Offset
0h (DLAB=0)
Bits
Description
7:0 TRANSMIT_DATA
This register contains the data byte to be transmitted. The transmit
buffer is double buffered, utilizing an additional shift register (not
accessible) to convert the 8 bit data word to a serial format. This shift
register is loaded from the Transmit Buffer when the transmission of
the previous byte is complete.
8.11.3
PROGRAMMABLE BAUD RATE GENERATOR LSB REGISTER
Offset
00h (DLAB=1)
Bits
Description
7:0 BAUD_RATE_DIVISOR_LSB
See Section 8.9.1, "Programmable Baud Rate".
8.11.4
PROGRAMMABLE BAUD RATE GENERATOR MSB REGISTER
Offset
01h (DLAB=1)
Bits
Description
7 BAUD_CLK_SEL
1=If CLK_SRC is ‘0’, the baud clock is derived from the 1.8432MHz_Clk. If CLK_SRC is ‘1’, this bit has no effect
1=If CLK_SRC is ‘0’, the baud clock is derived from the 24MHz_Clk.
If CLK_SRC is ‘1’, this bit has no effect
6:0 BAUD_RATE_DIVISOR_MSB
See Section 8.9.1, "Programmable Baud Rate".
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8.11.5
INTERRUPT ENABLE REGISTER
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible
to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits
of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the CEC1302. All other system functions operate in their
normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register
are described below.
Offset
01h (DLAB=0)
Type
Default
Reset
Event
R
-
-
3 EMSI
This bit enables the MODEM Status Interrupt when set to logic “1”.
This is caused when one of the Modem Status Register bits changes
state.
R/W
0h
RESET
2 ELSI
This bit enables the Received Line Status Interrupt when set to logic
“1”. The error sources causing the interrupt are Overrun, Parity,
Framing and Break. The Line Status Register must be read to determine the source.
R/W
0h
RESET
1 ETHREI
This bit enables the Transmitter Holding Register Empty Interrupt
when set to logic “1”.
R/W
0h
RESET
0 ERDAI
This bit enables the Received Data Available Interrupt (and timeout
interrupts in the FIFO mode) when set to logic “1”.
R/W
0h
RESET
Type
Default
Reset
Event
7:6 RECV_FIFO_TRIGGER_LEVEL
These bits are used to set the trigger level for the RCVR FIFO interrupt.
W
0h
RESET
5:4 Reserved
R
-
-
3 DMA_MODE_SELECT
Writing to this bit has no effect on the operation of the UART. The
RXRDY and TXRDY pins are not available on this chip.
W
0h
RESET
2 CLEAR_XMIT_FIFO
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and
resets its counter logic to “0”. The shift register is not cleared. This
bit is self-clearing.
W
0h
RESET
1 CLEAR_RECv_FIFO
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and
resets its counter logic to “0”. The shift register is not cleared. This
bit is self-clearing.
W
0h
RESET
Bits
Description
7:4 Reserved
8.11.6
FIFO CONTROL REGISTER
This is a write only register at the same location as the Interrupt Identification Register.
Note:
DMA is not supported.
Offset
02h
Bits
Description
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CEC1302
02h
Offset
Bits
Description
0 EXRF
Enable XMIT and RECV FIFO. Setting this bit to a logic “1” enables
both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” disables both the XMIT and RCVR FIFOs and clears all bytes from both
FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode,
data is automatically cleared from the FIFOs. This bit must be a 1
when other bits in this register are written to or they will not be properly programmed.
TABLE 8-12:
Type
Default
Reset
Event
W
0h
RESET
RECV FIFO TRIGGER LEVELS
Bit 7
Bit 6
RECV FIFO
Trigger Level (BYTES)
0
0
1
1
4
1
8.11.7
0
8
1
14
INTERRUPT IDENTIFICATION REGISTER
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority
interrupt exist. They are in descending order of priority:
1.
2.
3.
4.
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Table 8-13). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new
interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.
Offset
02h
Type
Default
Reset
Event
7:6 FIFO_EN
These two bits are set when the FIFO CONTROL Register bit 0
equals 1.
R
0h
RESET
5:4 Reserved
R
-
-
3:1 INTID
These bits identify the highest priority interrupt pending as indicated
by Table 8-13, "Interrupt Control Table". In non-FIFO mode, Bit[3] is
a logic “0”. In FIFO mode Bit[3] is set along with Bit[2] when a timeout interrupt is pending.
R
0h
RESET
Bits
Description
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CEC1302
Offset
02h
Bits
Description
0 IPEND
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit 0 is a
logic ‘0’ an interrupt is pending and the contents of the IIR may be
used as a pointer to the appropriate internal service routine. When
bit 0 is a logic ‘1’ no interrupt is pending.
TABLE 8-13:
Default
Reset
Event
R
1h
RESET
INTERRUPT CONTROL TABLE
FIFO
Mode
Only
Interrupt Identification
Register
Bit 3
Bit 2
Bit 1
Bit 0
Priority
Level
0
0
0
1
-
1
1
0
0
Interrupt SET and RESET Functions
Interrupt Reset
Control
Interrupt Source
None
Highest
Receiver Line Status
Overrun Error, Par- Reading the Line
ity Error, Framing
Status Register
Error or Break
Interrupt
Second
Received Data
Available
Receiver Data
Available
Character Timeout
Indication
No Characters
Reading the
Have Been
Receiver Buffer
Removed From or Register
Input to the RCVR
FIFO during the
last 4 Char times
and there is at least
1 char in it during
this time
0
1
Third
0
0
Fourth
2016 Microchip Technology Inc.
Interrupt Type
None
1
0
Type
-
Read Receiver Buffer or the FIFO
drops below the
trigger level.
Transmitter HoldTransmitter HoldReading the IIR
ing Register Empty ing Register Empty Register (if Source
of Interrupt) or Writing the Transmitter
Holding Register
MODEM Status
Clear to Send or
Reading the
Data Set Ready or MODEM Status
Ring Indicator or
Register
Data Carrier Detect
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CEC1302
8.11.8
LINE CONTROL REGISTER
Offset 03h
Bits
Type
Default
Reset
Event
7 DLAB
Divisor Latch Access Bit (DLAB). It must be set high (logic “1”) to
access the Divisor Latches of the Baud Rate Generator during read
or write operations. It must be set low (logic “0”) to access the
Receiver Buffer Register, the Transmitter Holding Register, or the
Interrupt Enable Register.
R/W
0h
RESET
6 BREAK_CONTROL
Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state and remains
there (until reset by a low level bit 6) regardless of other transmitter
activity. This feature enables the Serial Port to alert a terminal in a
communications system.
R/W
0h
RESET
5 STICK_PARITY
Stick Parity bit. When parity is enabled it is used in conjunction with
bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1
the Parity bit is transmitted and checked as a 0 (Space Parity). If bits
3 and 5 are 1 and bit 4 is a 0, then the Parity bit is transmitted and
checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled.
Bit 3 is a logic “1” and bit 5 is a logic “1”, the parity bit is transmitted
and then detected by the receiver in the opposite state indicated by
bit 4.
R/W
0h
RESET
4 PARITY_SELECT
Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”,
an odd number of logic “1”'s is transmitted or checked in the data
word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a
logic “1” an even number of bits is transmitted and checked.
R/W
0h
RESET
3 ENABLE_PARITY
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive data) between the last
data word bit and the first stop bit of the serial data. (The parity bit is
used to generate an even or odd number of 1s when the data word
bits and the parity bit are summed).
R/W
0h
RESET
2 STOP_BITS
This bit specifies the number of stop bits in each transmitted or
received serial character. Table 8-14 summarizes the information.
R/W
0h
RESET
1:0 WORD_LENGTH
These two bits specify the number of bits in each transmitted or
received serial character. The encoding of bits 0 and 1 is as follows:
R/W
0h
RESET
TABLE 8-14:
Description
STOP BITS
Bit 2
Word Length
Number of Stop Bits
0
--
1
1
5 bits
1.5
6 bits
2
7 bits
8 bits
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CEC1302
Note:
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
TABLE 8-15:
SERIAL CHARACTER
Bit 1
Bit 0
Word Length
0
0
0
1
1
0
1
1
The Start, Stop and Parity bits are not included in the word length.
8.11.9
5 Bits
6 Bits
7 Bits
8 Bits
MODEM CONTROL REGISTER
Offset
04h
Type
Default
Reset
Event
R
-
-
4 LOOPBACK
This bit provides the loopback feature for diagnostic testing of the
Serial Port. When bit 4 is set to logic “1”, the following occur:
1. The TXD is set to the Marking State (logic “1”).
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is “looped back”
into the Receiver Shift Register input.
4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are
disconnected.
5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and
OUT2) are internally connected to the four MODEM Control
inputs (nDSR, nCTS, RI, DCD).
6. The Modem Control output pins are forced inactive high.
7. Data that is transmitted is immediately received.
This feature allows the processor to verify the transmit and receive
data paths of the Serial Port. In the diagnostic mode, the receiver
and the transmitter interrupts are fully operational. The MODEM
Control Interrupts are also operational but the interrupts' sources are
now the lower four bits of the MODEM Control Register instead of
the MODEM Control inputs. The interrupts are still controlled by the
Interrupt Enable Register.
R/W
0h
RESET
3 OUT2
Output 2 (OUT2). This bit is used to enable an UART interrupt.
When OUT2 is a logic “0”, the serial port interrupt output is forced to
a high impedance state - disabled. When OUT2 is a logic “1”, the
serial port interrupt outputs are enabled.
R/W
0h
RESET
2 OUT1
This bit controls the Output 1 (OUT1) bit. This bit does not have an
output pin and can only be read or written by the CPU.
R/W
0h
RESET
1 RTS
This bit controls the Request To Send (nRTS) output. Bit 1 affects
the nRTS output in a manner identical to that described above for bit
0.
R/W
0h
RESET
Bits
Description
7:5 Reserved
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CEC1302
Offset
04h
Type
Default
Reset
Event
R/W
0h
RESET
Type
Default
Reset
Event
7 FIFO_ERROR
This bit is permanently set to logic “0” in the 450 mode. In the
FIFO mode, this bit is set to a logic “1” when there is at least one
parity error, framing error or break indication in the FIFO. This bit
is cleared when the LSR is read if there are no subsequent errors
in the FIFO.
R
0h
RESET
6 TRANSMIT_ERROR
Transmitter Empty. Bit 6 is set to a logic “1” whenever the Transmitter Holding Register (THR) and Transmitter Shift Register
(TSR) are both empty. It is reset to logic “0” whenever either the
THR or TSR contains a data character. Bit 6 is a read only bit. In
the FIFO mode this bit is set whenever the THR and TSR are both
empty,
R
0h
RESET
5 TRANSMIT_EMPTY
Transmitter Holding Register Empty Bit 5 indicates that the Serial
Port is ready to accept a new character for transmission. In addition, this bit causes the Serial Port to issue an interrupt when the
Transmitter Holding Register interrupt enable is set high. The
THRE bit is set to a logic “1” when a character is transferred from
the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the
XMIT FIFO is empty, it is cleared when at least 1 byte is written to
the XMIT FIFO. Bit 5 is a read only bit.
R
0h
RESET
4 BREAK_INTERRUPT
Break Interrupt. Bit 4 is set to a logic “1” whenever the received
data input is held in the Spacing state (logic “0”) for longer than a
full word transmission time (that is, the total time of the start bit +
data bits + parity bits + stop bits). The BI is reset after the CPU
reads the contents of the Line Status Register. In the FIFO mode
this error is associated with the particular character in the FIFO it
applies to. This error is indicated when the associated character is
at the top of the FIFO. When break occurs only one zero character
is loaded into the FIFO. Restarting after a break is received,
requires the serial data (RXD) to be logic “1” for at least 1/2 bit
time.
Bits 1 through 4 are the error conditions that produce a Receiver
Line Status Interrupt BIT 3 whenever any of the corresponding
conditions are detected and the interrupt is enabled
R
0h
RESET
Bits
Description
0 DTR
This bit controls the Data Terminal Ready (nDTR) output. When bit 0
is set to a logic “1”, the nDTR output is forced to a logic “0”. When bit
0 is a logic “0”, the nDTR output is forced to a logic “1”.
8.11.10
Offset
LINE STATUS REGISTER
05h
Bits
Description
DS00002022B-page 92
2016 Microchip Technology Inc.
CEC1302
Offset
05h
Type
Default
Reset
Event
3 FRAME_ERROR
Framing Error. Bit 3 indicates that the received character did not
have a valid stop bit. Bit 3 is set to a logic “1” whenever the stop bit
following the last data bit or parity bit is detected as a zero bit
(Spacing level). This bit is reset to a logic “0” whenever the Line
Status Register is read. In the FIFO mode this error is associated
with the particular character in the FIFO it applies to. This error is
indicated when the associated character is at the top of the FIFO.
The Serial Port will try to resynchronize after a framing error. To do
this, it assumes that the framing error was due to the next start bit,
so it samples this 'start' bit twice and then takes in the 'data'.
R
0h
RESET
2 PARITY ERROR
Parity Error. Bit 2 indicates that the received data character does
not have the correct even or odd parity, as selected by the even
parity select bit. This bit is set to a logic “1” upon detection of a
parity error and is reset to a logic “0” whenever the Line Status
Register is read. In the FIFO mode this error is associated with the
particular character in the FIFO it applies to. This error is indicated
when the associated character is at the top of the FIFO.
R
0h
RESET
1 OVERRUN_ERROR
Overrun Error. Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was transferred into
the register, thereby destroying the previous character. In FIFO
mode, an overrun error will occur only when the FIFO is full and
the next character has been completely received in the shift register, the character in the shift register is overwritten but not transferred to the FIFO. This bit is set to a logic “1” immediately upon
detection of an overrun condition, and reset whenever the Line
Status Register is read.
R
0h
RESET
0 DATA_READY
Data Ready. It is set to a logic ‘1’ whenever a complete incoming
character has been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a logic ‘0’ by reading
all of the data in the Receive Buffer Register or the FIFO.
R
0h
RESET
Type
Default
Reset
Event
7 DCD
This bit is the complement of the Data Carrier Detect (nDCD) input.
If bit 4 of the MCR is set to logic ‘1’, this bit is equivalent to OUT2 in
the MCR.
R
0h
RESET
6 RI#
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of
the MCR is set to logic ‘1’, this bit is equivalent to OUT1 in the MCR.
R
0h
RESET
Bits
8.11.11
Offset
Description
MODEM STATUS REGISTER
06h
Bits
Description
2016 Microchip Technology Inc.
DS00002022B-page 93
CEC1302
Offset
06h
Type
Default
Reset
Event
5 DSR
This bit is the complement of the Data Set Ready (nDSR) input. If bit
4 of the MCR is set to logic ‘1’, this bit is equivalent to DTR in the
MCR.
R
0h
RESET
4 CTS
This bit is the complement of the Clear To Send (nCTS) input. If bit 4
of the MCR is set to logic ‘1’, this bit is equivalent to nRTS in the
MCR.
R
0h
RESET
3 DCD
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD
input to the chip has changed state.
NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic ‘1’, a MODEM Status Interrupt is generated.
R
0h
RESET
2 RI
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI
input has changed from logic ‘0’ to logic ‘1’.
R
0h
RESET
1 DSR
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input
has changed state since the last time the MSR was read.
R
0h
RESET
0 CTS
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to
the chip has changed state since the last time the MSR was read.
R
0h
RESET
Bits
Description
Note:
The Modem Status Register (MSR) only provides the current state of the UART MODEM control lines in
Loopback Mode. The CEC1302 does not support external connections for the MODEM Control inputs
(nCTS, nDSR, nRI and nDCD) or for the four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2).
8.11.12
SCRATCHPAD REGISTER
Offset
07h
Bits
Description
7:0 SCRATCH
This 8 bit read/write register has no effect on the operation of the
Serial Port. It is intended as a scratchpad register to be used by the
programmer to hold data temporarily.
DS00002022B-page 94
Type
Default
Reset
Event
R/W
0h
RESET
2016 Microchip Technology Inc.
CEC1302
9.0
EC INTERRUPT AGGREGATOR
9.1
Introduction
The EC Interrupt Aggregator works in conjunction with the processor’s interrupt interface to handle hardware interrupts
and exceptions.
Exceptions are synchronous to instructions, are not maskable, and have higher priority than interrupts. All three exceptions - reset, memory error, and instruction error - are hardwired directly to the processor. Interrupts are typically asynchronous and are maskable.
Interrupts classified as wake events can be recognized without a running clock, e.g., while the CEC1302 is in sleep
state.
This chapter focuses on the EC Interrupt Aggregator. Please refer to embedded controller’s documentation for more
information on interrupt and exception handling.
9.2
References
None
9.3
Terminology
None
9.4
Interface
FIGURE 9-1:
BLOCK DIAGRAM OF EC Interrupt Aggregator
Interrupt Sources
31
31
31
31
GIRQ8 Source
Register
GIRQ9 Source
Register
GIRQ10 Source
Register
AOI
AOI
AOI
Masking
Bits
Masking
Bits
Masking
Bits
GIRQ23 Source
Register
AOI
Masking
Bits
16
Processor
2016 Microchip Technology Inc.
DS00002022B-page 95
CEC1302
9.4.1
SIGNAL INTERFACE
This block is not accessible from the pin interface.
9.4.2
HOST INTERFACE
The registers defined for the EC Interrupt Aggregator are only accessible by the embedded controller via the EC-Only
Registers.
9.5
9.5.1
Power, Clocks and Reset
BLOCK POWER DOMAIN
TABLE 9-1:
BLOCK POWER
Power Well Source
VCC1
9.5.2
Effect on Block
The EC Interrupt Aggregator block and registers operate on
this single power well.
BLOCK CLOCKS
None
9.5.3
BLOCK RESET
TABLE 9-2:
9.6
BLOCK RESETS
Reset Name
Reset Description
VCC1_RESET
This signal is used to indicate when the VCC1 logic and registers in this block are reset.
Interrupts
This block aggregates all the interrupts targeted for the embedded controller into the Source Registers defined in Section 9.9, "EC-Only Registers," on page 105. The unmasked bits of each source register are then OR’d together and
routed to the embedded controller’s interrupt interface. The name of each Source Register identifies the IRQ number of
the interrupt port on the embedded controller.
9.7
Low Power Modes
This block always automatically adjusts to operate in the lowest power mode.
9.8
Description
The interrupt generation logic is made of 16 groups of signals, each of which consist of a Status register, a Enable register and a Result register.
The Status and Enable are latched registers. The Result register is a bit by bit AND function of the Source and Enable
registers. All the bits of the Result register are OR’ed together and AND’ed with the corresponding bit in the Block Select
register to form the interrupt signal that is routed to the ARM interrupt controller.
The Result register bits may also be enabled to the NVIC block via the NVIC_EN bit in the Interrupt Control register.
See Chapter 27.0, "EC Subsystem Registers"
Section 9.8.1 shows a representation of the interrupt structure.
DS00002022B-page 96
2016 Microchip Technology Inc.
CEC1302
FIGURE 9-2:
INTERRUPT STRUCTURE
NVIC_EN
GIRQx
..
Int source
NVIC
Inputs for
blocks
.
result
Interrupt
from block
SOURCE0
Interrupt
from block
SOURCE1
.
..
Interrupt
from block
.
..
..
.
.
..
NVIC
Input for
GIRQx
SOURCEn
Int enable
ENABLE0
ENABLE1
..
.
ENABLEn
Block Enable
.
.
.
Bit x
..
.
To Wake
Interface
9.8.1
WAKE GENERATION
The EC Interrupt Aggregator notifies the Chip Power Management Features to wake the system when it detects a wake
capable event has occurred. This logic requires no clocks.
The interrupt sources AND’ed with the corresponding Enable bit will be OR’ed to produce a wake event
The wake up sources are identified with a “Y” in the “WAKE” column of the Bit definitions table for each IRQ’s Source
Register.
9.8.1.1
Configuring Wake Interrupts
All GPIO inputs are wake-capable. In order for a GPIO input to wake the CEC1302 from a sleep state, the Interrupt
Detection field of the GPIO Pin Control Register must be set to Rising Edge Triggered, Falling Edge Triggered, or Either
Edge Triggered. If the Interrupt Detection field is set to any other value, a GPIO input will not trigger a wake interrupt.
Some of the Wake Capable Interrupts are triggered by activity on pins that are shared with a GPIO. These interrupts will
only trigger a wake if the Interrupt Detection field of the corresponding GPIO Pin Control Register is set to Rising Edge
Triggered, Falling Edge Triggered, or Either Edge Triggered.
APPLICATION NOTE: JTAG debug accesses are not wake capable. EC firmware must enable an interrupt on the
falling edge of the GPIO associated with JTAG_CLK if JTAG debug accesses are required
while the CEC1302 is in a sleep mode in which the main clock is turned off.
2016 Microchip Technology Inc.
DS00002022B-page 97
CEC1302
9.8.2
INTERRUPT SUMMARY
Table 9-3, "Interrupt Event Aggregator Routing Summary" summarizes the interrupts, wake capabilities and NVIC vector
locations.
Table 9-4, "EC Interrupt Structure" summarizes the interrupts, priorities and vector locations.
TABLE 9-3:
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY
Interrupt
Aggregator IRQ
Aggregator Bit
GPIO140
GIRQ8
0
GPIO141
GIRQ8
1
GPIO142
GIRQ8
2
GPIO143
GIRQ8
3
GPIO144
GIRQ8
4
GPIO145
GIRQ8
5
GPIO146
GIRQ8
6
GPIO147
GIRQ8
7
GPIO150
GIRQ8
8
GPIO151
GIRQ8
9
GPIO152
GIRQ8
10
GPIO153
GIRQ8
11
GPIO154
GIRQ8
12
GPIO155
GIRQ8
13
GPIO156
GIRQ8
14
GPIO157
GIRQ8
15
GPIO160
GIRQ8
16
GPIO161
GIRQ8
17
GPIO162
GIRQ8
18
GPIO163
GIRQ8
19
GPIO164
GIRQ8
20
GPIO165
GIRQ8
21
DS00002022B-page 98
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
Yes
57
N/A
2016 Microchip Technology Inc.
CEC1302
TABLE 9-3:
Interrupt
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY (CONTINUED)
Aggregator IRQ
Aggregator Bit
GPIO100
GIRQ9
0
GPIO101
GIRQ9
1
GPIO102
GIRQ9
2
GPIO103
GIRQ9
3
GPIO104
GIRQ9
4
GPIO105
GIRQ9
5
GPIO106
GIRQ9
6
GPIO107
GIRQ9
7
GPIO110
GIRQ9
8
GPIO111
GIRQ9
9
GPIO112
GIRQ9
10
GPIO113
GIRQ9
11
GPIO114
GIRQ9
12
GPIO115
GIRQ9
13
GPIO116
GIRQ9
14
GPIO117
GIRQ9
15
GPIO120
GIRQ9
16
GPIO121
GIRQ9
17
GPIO122
GIRQ9
18
GPIO123
GIRQ9
19
GPIO124
GIRQ9
20
GPIO125
GIRQ9
21
GPIO126
GIRQ9
22
GPIO127
GIRQ9
23
GPIO130
GIRQ9
24
GPIO131
GIRQ9
25
GPIO132
GIRQ9
26
GPIO133
GIRQ9
27
GPIO134
GIRQ9
28
GPIO135
GIRQ9
29
GPIO136
GIRQ9
30
2016 Microchip Technology Inc.
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
Yes
58
N/A
DS00002022B-page 99
CEC1302
TABLE 9-3:
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY (CONTINUED)
Interrupt
Aggregator IRQ
Aggregator Bit
GPIO040
GIRQ10
0
GPIO041
GIRQ10
1
GPIO042
GIRQ10
2
GPIO043
GIRQ10
3
GPIO044
GIRQ10
4
GPIO045
GIRQ10
5
GPIO046
GIRQ10
6
GPIO047
GIRQ10
7
GPIO050
GIRQ10
8
GPIO051
GIRQ10
9
GPIO052
GIRQ10
10
GPIO053
GIRQ10
11
GPIO054
GIRQ10
12
GPIO055
GIRQ10
13
GPIO056
GIRQ10
14
GPIO057
GIRQ10
15
GPIO060
GIRQ10
16
GPIO061
GIRQ10
17
GPIO062
GIRQ10
18
GPIO063
GIRQ10
19
GPIO064
GIRQ10
20
GPIO065
GIRQ10
21
GPIO066
GIRQ10
22
GPIO067
GIRQ10
23
DS00002022B-page 100
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
Yes
59
N/A
2016 Microchip Technology Inc.
CEC1302
TABLE 9-3:
Interrupt
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY (CONTINUED)
Aggregator IRQ
Aggregator Bit
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
Yes
60
N/A
No
61
0
GPIO000
GIRQ11
0
GPIO001
GIRQ11
1
GPIO002
GIRQ11
2
GPIO003
GIRQ11
3
GPIO004
GIRQ11
4
GPIO005
GIRQ11
5
GPIO006
GIRQ11
6
GPIO007
GIRQ11
7
GPIO010
GIRQ11
8
GPIO011
GIRQ11
9
GPIO012
GIRQ11
10
GPIO013
GIRQ11
11
GPIO014
GIRQ11
12
GPIO015
GIRQ11
13
GPIO016
GIRQ11
14
GPIO017
GIRQ11
15
GPIO020
GIRQ11
16
GPIO021
GIRQ11
17
GPIO022
GIRQ11
18
GPIO023
GIRQ11
19
GPIO024
GIRQ11
20
GPIO025
GIRQ11
21
GPIO026
GIRQ11
22
GPIO027
GIRQ11
23
GPIO030
GIRQ11
24
GPIO031
GIRQ11
25
GPIO032
GIRQ11
26
GPIO033
GIRQ11
27
GPIO034
GIRQ11
28
GPIO035
GIRQ11
29
GPIO036
GIRQ11
30
I2C0 / SMB0
GIRQ12
0
I2C1 / SMB1
GIRQ12
1
1
I2C2 / SMB2
GIRQ12
2
2
I2C3 / SMB3
GIRQ12
3
I2C0_0_WK
GIRQ12
4
I2C0_1_WK
GIRQ12
5
I2C2_0_WK
GIRQ12
6
I2C1_0_WK
GIRQ12
7
I2C3_0_WK
GIRQ12
8
2016 Microchip Technology Inc.
3
Yes
N/A
DS00002022B-page 101
CEC1302
TABLE 9-3:
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY (CONTINUED)
Interrupt
Aggregator IRQ
Aggregator Bit
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
No
62
4
DMA0
GIRQ13
16
DMA1
GIRQ13
17
5
DMA2
GIRQ13
18
6
DMA3
GIRQ13
19
7
DMA4
GIRQ13
20
8
DMA5
GIRQ13
21
9
DMA6
GIRQ13
22
10
DMA7
GIRQ13
23
11
DMA8
GIRQ13
24
81
DMA9
GIRQ13
25
82
DMA10
GIRQ13
26
83
DMA11
GIRQ13
27
84
UART_0
GIRQ15
0
No
64
13
Reserved
GIRQ15
1
MCHP Reserved
GIRQ15
2
14
Reserved
GIRQ15
3
N/A
Reserved
GIRQ15
4
N/A
Reserved
GIRQ15
5
N/A
MCHP Reserved
GIRQ15
6
15
MCHP Reserved
GIRQ15
7
16
MCHP Reserved
GIRQ15
8
17
MCHP Reserved
GIRQ15
9
18
MCHP Reserved
GIRQ15
10
19
MCHP Reserved
GIRQ15
11
20
MCHP Reserved
GIRQ15
12
21
MCHP Reserved
GIRQ15
13
22
MCHP Reserved
GIRQ15
14
23
MCHP Reserved
GIRQ15
15
24
MCHP Reserved
GIRQ15
16
MCHP Reserved
GIRQ16
3
DS00002022B-page 102
N/A
40
No
65
25
2016 Microchip Technology Inc.
CEC1302
TABLE 9-3:
Interrupt
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY (CONTINUED)
Aggregator IRQ
Aggregator Bit
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
66
26
TACH_0
GIRQ17
0
No
TACH_1
GIRQ17
1
No
27
MCHP Reserved
GIRQ17
2
Yes
N/A
MCHP Reserved
GIRQ17
3
Yes
MCHP Reserved
GIRQ17
4
Yes
MCHP Reserved
GIRQ17
5
Yes
BC_INT_N_WK
GIRQ17
6
Yes
ADC_SNGL
GIRQ17
10
No
28
ADC_RPT
GIRQ17
11
No
29
MCHP Reserved
GIRQ17
12
No
30
MCHP Reserved
GIRQ17
13
No
31
MCHP Reserved
GIRQ17
14
No
32
MCHP Reserved
GIRQ17
15
No
33
MCHP Reserved
GIRQ17
16
No
34
MCHP Reserved
GIRQ17
17
No
35
RTC
GIRQ17
18
Yes
91
RTC ALARM
GIRQ17
19
Yes
92
HTIMER
GIRQ17
20
Yes
38
KSC_INT
GIRQ17
21
No
39
KSC_INT wake
GIRQ17
22
Yes
N/A
RPM_INT Stall
GIRQ17
23
No
41
RPM_INT Spin
GIRQ17
24
No
42
PFR_STS
GIRQ17
25
No
43
PWM_WDT0
GIRQ17
26
No
44
PWM_WDT1
GIRQ17
27
No
45
PWM_WDT2
GIRQ17
28
No
46
BCM_INT Err
GIRQ17
29
No
47
BCM_INT Busy
GIRQ17
30
No
48
SPI0 TX
GIRQ18
0
No
SPI0 RX
GIRQ18
1
37
SPI1 TX
GIRQ18
2
55
SPI1 RX
GIRQ18
3
56
PWM_WDT3
GIRQ18
4
85
PKE ERROR
GIRQ18
5
86
PKE END
GIRQ18
6
87
RNG
GIRQ18
7
88
AES
GIRQ18
8
89
HASH
GIRQ18
9
VCC_PWRGD
GIRQ19
0
LRESET#
GIRQ19
1
2016 Microchip Technology Inc.
67
36
90
Yes
68
N/A
DS00002022B-page 103
CEC1302
TABLE 9-3:
INTERRUPT EVENT AGGREGATOR ROUTING SUMMARY (CONTINUED)
Interrupt
Aggregator IRQ
Aggregator Bit
GPIO200
GIRQ20
0
GPIO201
GIRQ20
1
GPIO202
GIRQ20
2
GPIO203
GIRQ20
3
Wake
Event
Aggregated NVIC
Direct NVIC
Interrupt
Yes
69
N/A
No
72
49
GPIO204
GIRQ20
4
N/A
GIRQ20
5
GPIO206
GIRQ20
6
N/A
GIRQ20
7
GPIO210
GIRQ20
8
GPIO211
GIRQ20
9
TIMER_16_0
GIRQ23
0
TIMER_16_1
GIRQ23
1
50
TIMER_16_2
GIRQ23
2
51
TIMER_16_3
GIRQ23
3
52
TIMER_32_0
GIRQ23
4
53
TIMER_32_1
GIRQ23
5
54
TABLE 9-4:
EC INTERRUPT STRUCTURE
Vector
Name
Link
Register
Priority
(Default)
Relative
Priority
Byte
Offset
0
Reset
-
High
H1
00h
1
Memory Error
ILINK2
High
H2
08h
2
Instruction Error
ILINK2
High
H3
10h
3
IRQ3-Reserved
ILINK1
level 1 (low)
L27
18h
4
IRQ4-Reserved
ILINK1
level 1 (low)
L26
20h
5
IRQ5-Reserved
ILINK1
level 1 (low)
L25
28h
6
IRQ6-Reserved
ILINK2
level 2 (mid)
M2
30h
7
IRQ7-Reserved
ILINK2
level 2 (mid)
M1
38h
8
IRQ8
ILINK1
level 1 (low)
L24
40h
9
IRQ9
ILINK1
level 1 (low)
L23
48h
10
IRQ10
ILINK1
level 1 (low)
L22
50h
11
IRQ11
ILINK1
level 1 (low)
L21
58h
12
IRQ12
ILINK1
level 1 (low)
L20
60h
13
IRQ13
ILINK1
level 1 (low)
L19
68h
14
IRQ14
ILINK1
level 1 (low)
L18
70h
15
IRQ15
ILINK1
level 1 (low)
L17
78h
16
IRQ16
ILINK1
level 1 (low)
L16
80h
17
IRQ17
ILINK1
level 1 (low)
L15
88h
18
IRQ18
ILINK1
level 1 (low)
L14
90h
19
IRQ19
ILINK1
level 1 (low)
L13
98h
20
IRQ20
ILINK1
level 1 (low)
L12
A0h
21
IRQ21
ILINK1
level 1 (low)
L11
A8h
22
IRQ22
ILINK1
level 1 (low)
L10
B0h
DS00002022B-page 104
2016 Microchip Technology Inc.
CEC1302
TABLE 9-4:
EC INTERRUPT STRUCTURE (CONTINUED)
Vector
Name
Link
Register
Priority
(Default)
Relative
Priority
23
IRQ23
ILINK1
level 1 (low)
L9
B8h
24
IRQ24
ILINK1
level 1 (low)
L8
C0h
25
IRQ25
ILINK1
level 1 (low)
L7
C8h
26
IRQ26
ILINK1
level 1 (low)
L6
D0h
27
IRQ27
ILINK1
level 1 (low)
L5
D8h
28
IRQ28
ILINK1
level 1 (low)
L4
E0h
29
IRQ29
ILINK1
level 1 (low)
L3
E8h
30
IRQ30
ILINK1
level 1 (low)
L2
F0h
31
IRQ31
ILINK1
level 1 (low)
L1
F8h
Note:
Byte
Offset
IRQ Vector 31 is the highest L1 Priority
9.8.3
DISABLING INTERRUPTS
The Block Enable Clear Register and Block Enable Set Register should not be used for disabling and enabling interrupts
for software operations i.e., critical sections. The ARM enable disable mechanisms should be used.
9.9
EC-Only Registers
The configuration registers listed in EC-Only Register Summary table are for a single instance of the EC Interrupt Aggregator. The addresses of each register listed in the summary table are defined as a relative offset to the host “Begin
Address” defined in the EC-Only Register Base Address Table.
TABLE 9-5:
EC-ONLY REGISTER ADDRESS RANGE TABLE
Instance Name
Instance
Number
Host
Address Space
Interrupt Aggregator
0
EC
32-bit internal
address space
Note 9-1
TABLE 9-6:
Begin Address (Note 91)
4000_C000h
The Begin Address indicates the location of the first register accessable at offset 00h in the Interrupt
Aggregator EC-Only address space.
EC-ONLY REGISTER SUMMARY
Offset
Register Name
00h
GIRQ8 Source Register
04h
GIRQ8 Enable Set Register
08h
GIRQ8 Result Register
0Ch
GIRQ8 Enable Clear Register
14h
GIRQ9 Source Register
18h
GIRQ9 Enable Set Register
1Ch
GIRQ9 Result Register
20h
GIRQ9 Enable Clear Register
28h
GIRQ10 Source Register
2Ch
GIRQ10 Enable Set Register
30h
GIRQ10 Result Register
34h
GIRQ10 Enable Clear Register
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TABLE 9-6:
EC-ONLY REGISTER SUMMARY (CONTINUED)
Offset
Register Name
3Ch
GIRQ11 Source Register
40h
GIRQ11 Enable Set Register
44h
GIRQ11 Result Register
48h
GIRQ11 Enable Clear Register
50h
GIRQ12 Source Register
54h
GIRQ12 Enable Set Register
58h
GIRQ12 Result Register
5Ch
GIRQ12 Enable Clear Register
64h
GIRQ13 Source Register
68h
GIRQ13 Enable Set Register
6Ch
GIRQ13 Result Register
70h
GIRQ13 Enable Clear Register
78h
GIRQ14 Source Register
7Ch
GIRQ14 Enable Set Register
80h
GIRQ14 Result Register
84h
GIRQ14 Enable Clear Register
8Ch
GIRQ15 Source Register
90h
GIRQ15 Enable Set Register
94h
GIRQ15 Result Register
98h
GIRQ15 Enable Clear Register
A0h
GIRQ16 Source Register
A4h
GIRQ16 Enable Set Register
A8h
GIRQ16 Result Register
ACh
GIRQ16 Enable Clear Register
B4h
GIRQ17 Source Register
B8h
GIRQ17 Enable Set Register
BCh
GIRQ17 Result Register
C0h
GIRQ17 Enable Clear Register
C8h
GIRQ18 Source Register
CCh
GIRQ18 Enable Set Register
D0h
GIRQ18 Result Register
D4h
GIRQ18 Enable Clear Register
DCh
GIRQ19 Source Register
E0h
GIRQ19 Enable Set Register
E4h
GIRQ19 Result Register
E8h
GIRQ19 Enable Clear Register
F0h
GIRQ20 Source Register
F4h
GIRQ20 Enable Set Register
F8h
GIRQ20 Result Register
FCh
GIRQ20 Enable Clear Register
104h
GIRQ21 Source Register
108h
GIRQ21 Enable Set Register
10Ch
GIRQ21 Result Register
110h
GIRQ21 Enable Clear Register
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TABLE 9-6:
EC-ONLY REGISTER SUMMARY (CONTINUED)
Offset
Register Name
118h
GIRQ22 Source Register
11Ch
GIRQ22 Enable Set Register
120h
GIRQ22 Result Register
124h
GIRQ22 Enable Clear Register
12Ch
GIRQ23 Source Register
130h
GIRQ23 Enable Set Register
134h
GIRQ23 Result Register
138h
GIRQ23 Enable Clear Register
200h
Block Enable Set Register
204h
Block Enable Clear Register
208h
Block IRQ Vector Register
All of the GIRQx Source, Enable, and Result registers have the same format. The following tables define the generic
format for each of these registers. The bit definitions are defined in the sections that follow.
Note:
The behavior of the enable bit controlled by the GIRQx Enable Set and GIRQx Enable Clear Registers, the
GIRQx Source bit, and the GIRQx Result bit are illustrated in Section 9.8.1, "WAKE Generation," on
page 97.
TABLE 9-7:
Offset
Power
GIRQX SOURCE REGISTER
-
32-bit
VCC1
Size
0000_0000h
D30
D29
VCC1_RESET
Default
D2
D1
Bit
D31
Type
R
R/WC except for reserved bits, which are R
Bit Name
Reserved
See Tables in the following subsections
D0
The R/WC bits are sticky status bits indicating the state of interrupt source before the interrupt enable bit.
TABLE 9-8:
Offset
POWER
GIRQX ENABLE SET REGISTER
-
32-bit
VCC1
Size
0000_0000h
D30
D29
VCC1_RESET
Default
D2
D1
BIT
D31
TYPE
R
R/WS except for reserved bits, which are R
BIT NAME
Reserved
See Tables in the following subsections
D0
GIRQ Enable Set [31:0]
Each GIRQx bit can be individually enabled to assert an interrupt event.
0= Writing a zero has no effect.
1= Writing a one will enable respective GIRQx.
Reading always returns the current value of the GIRQx ENABLE bit. The state of the GIRQx ENABLE bit is determined
by the corresponding GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=disabled, 1-enabled)
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TABLE 9-9:
GIRQX RESULT REGISTER
-
Offset
32-bit
VCC1
POWER
8000_0000h
D30
D29
D2
BIT
D31
TYPE
R
R
BIT NAME
‘1’
See Tables in the following subsections
EC Size
VCC1_RESET
Default
D1
D0
GIRQx Interrupt Result
Bits D30 down to D0 are defined in the following subsections reflect the state of the GIRQx interrupt source after the
enable bit. The GIRQx result bits are OR’d together to generate the IRQx vector.
Bit D31
Bit D31 is hard-coded to ‘1’.
TABLE 9-10:
GIRQX ENABLE CLEAR REGISTER
-
Offset
32-bit
VCC1
POWER
0000_0000h
D30
BIT
D31
D29
D2
TYPE
R
R/WC except for reserved bits, which are R
BIT NAME
Reserved
See Tables in the following subsections
Size
VCC1_RESET
Default
D1
D0
GIRQx Enable Clear[31:0]
Each GIRQx bit can be individually disabled to assert an interrupt event.
0= Writing a zero has no effect.
1= Writing a one will disable respective GIRQx.
Reading always returns the current value of the GIRQx ENABLE bit. The state of the GIRQx ENABLE bit is determined
by the corresponding GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=disabled, 1-enabled)
9.9.1
GIRQ8
TABLE 9-11:
BIT DEFINITIONS FOR GIRQ8 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
[7:0]
GPIO[147:140]
GPIO_Event
Y
Source Description
Bits[0:7] are controlled by the GPIO_Events generated by GPIO140 through GPIO147, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling edge, as configured by the Interrupt Detection
(int_det) bits in the Pin Control Register associated
with the GPIO signal function.
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2016 Microchip Technology Inc.
CEC1302
TABLE 9-11:
BIT DEFINITIONS FOR GIRQ8 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[15:8]
GPIO[157:150]
GPIO_Event
Y
Bits[8:15] are controlled by the GPIO_Events generated by GPIO150 through GPIO157, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling edge, as configured by the Interrupt Detection
(int_det) bits in the Pin Control Register associated
with the GPIO signal function.
[21:16]
GPIO[165:160]
GPIO_Event
Y
Bits[16:21] are controlled by the GPIO_Events generated by GPIO160 through GPIO165, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling edge, as configured by the Interrupt Detection
(int_det) bits in the Pin Control Register associated
with the GPIO signal function.
[30:22]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx
Enable Clear Register", and Table 9-9, "GIRQx
Result Register" for a definition of this bit for the
Source, Enable, and Result registers.
9.9.2
GIRQ9
TABLE 9-12:
BIT DEFINITIONS FOR GIRQ9 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[7:0]
GPIO[107:100]
GPIO_Event
Y
Bits[0:7] are controlled by the GPIO_Events generated
by GPIO100 through GPIO107, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the
GPIO signal function.
[15:8]
GPIO[117:110]
GPIO_Event
Y
Bits[8:15] are controlled by the GPIO_Events generated by GPIO110 through GPIO117, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the
GPIO signal function.
[23:16]
GPIO[127:120]
GPIO_Event
Y
Bits[16:23] are controlled by the GPIO_Events generated by GPIO120 through GPIO127, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the
GPIO signal function.
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TABLE 9-12:
BIT DEFINITIONS FOR GIRQ9 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[30:24]
GPIO[136:130]
GPIO_Event
Y
Bits[24:30] are controlled by the GPIO_Events generated by GPIO130 through GPIO136, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the
GPIO signal function.
31
9.9.3
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx
Enable Clear Register", and Table 9-9, "GIRQx Result
Register" for a definition of this bit for the Source,
Enable, and Result registers.
GIRQ10
TABLE 9-13:
BIT DEFINITIONS FOR GIRQ10 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[7:0]
GPIO[047:040]
GPIO_Event
Y
Bits[0:7] are controlled by the GPIO_Events generated by
GPIO040 through GPIO047, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[15:8]
GPIO[057:050]
GPIO_Event
Y
Bits[8:15] are controlled by the GPIO_Events generated
by GPIO050 through GPIO057, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[23:16]
GPIO[067:060]
GPIO_Event
Y
Bits[16:23] are controlled by the GPIO_Events generated
by GPIO060 through GPIO067, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[30:24]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
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9.9.4
GIRQ11
TABLE 9-14:
BIT DEFINITIONS FOR GIRQ11 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[7:0]
GPIO[007:000]
GPIO_Event
Y
Bits[0:7] are controlled by the GPIO_Events generated by
GPIO000 through GPIO007, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[15:8]
GPIO[017:010]
GPIO_Event
Y
Bits[8:15] are controlled by the GPIO_Events generated
by GPIO010 through GPIO017, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[23:16]
GPIO[027:020]
GPIO_Event
Y
Bits[16:23] are controlled by the GPIO_Events generated
by GPIO020 through GPIO027, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[30:24]
GPIO[036:030]
GPIO_Event
Y
Bits[24:30] are controlled by the GPIO_Events generated
by GPIO030 through GPIO036, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
31
n/a
9.9.5
GIRQ12
TABLE 9-15:
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
BIT DEFINITIONS FOR GIRQ12 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
I2C0 / SMB0
SMB
N
I2C/SMBus controller 0 interrupt. This interrupt is signaled
when the I2C/SMBus controller 0 asserts its interrupt
request.
1
I2C1 / SMB1
SMB
N
I2C/SMBus controller 1 interrupt. This interrupt is signaled
when the I2C/SMBus controller 1 asserts its interrupt
request.
2
I2C2 / SMB2
SMB
N
I2C/SMBus controller 2 interrupt. This interrupt is signaled
when the I2C/SMBus controller 2 asserts its interrupt
request.
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TABLE 9-15:
BIT DEFINITIONS FOR GIRQ12 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
3
I2C3 / SMB3
SMB
N
I2C/SMBus controller 3 interrupt. This interrupt is signaled
when the I2C/SMBus controller 3 asserts its interrupt
request.
4
I2C0_0_WK
SMB
Y
I2C/SMBus controller 0 (port 0) Wake interrupt. This interrupt is signaled when there is activity on the I2C/SMBus
controller 0 port 0 data pin, I2C0_DAT0 (see Note 9-2 on
page 118).
5
I2C0_1_WK
SMB
Y
I2C/SMBus controller 0 (port 1) Wake interrupt. This interrupt is signaled when there is activity on the I2C/SMBus
controller 0 port 1 data pin, I2C0_DAT1 (see Note 9-2 on
page 118).
6
I2C2_0_WK
SMB
Y
I2C/SMBus controller 2 (port 0) Wake interrupt. This interrupt is signaled when there is activity on the I2C/SMBus
controller 2 (port 0) data pin, I2C2_DAT0 (see Note 9-2 on
page 118).
7
I2C1_0_WK
SMB
Y
I2C/SMBus controller 1 (port 0) Wake interrupt. This interrupt is signaled when there is activity on the I2C/SMBus
controller 1 port 0 data pin, I2C1_DAT0 (see Note 9-2 on
page 118).
8
I2C3_0_WK
SMB
Y
I2C/SMBus controller 3 (port 0) Wake interrupt. This interrupt is signaled when there is activity on the I2C/SMBus
controller 3 port 0 data pin, I2C3_DAT0 (see Note 9-2 on
page 118).
[30:9]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.6
GIRQ13
TABLE 9-16:
BIT DEFINITIONS FOR GIRQ13 SOURCE, ENABLE, AND RESULT REGISTERS
Block Instance
Name
Source Name
Wake
[15:0]
Reserved
Reserved
N
Reserved
16
IRQ_DMA0
DMA0
N
Direct Memory Access Channel 0
17
IRQ_DMA1
DMA1
N
Direct Memory Access Channel 1
18
IRQ_DMA2
DMA2
N
Direct Memory Access Channel 2
19
IRQ_DMA3
DMA3
N
Direct Memory Access Channel 3
20
IRQ_DMA4
DMA4
N
Direct Memory Access Channel 4
21
IRQ_DMA5
DMA5
N
Direct Memory Access Channel 5
22
IRQ_DMA6
DMA6
N
Direct Memory Access Channel 6
23
IRQ_DMA7
DMA7
N
Direct Memory Access Channel 7
24
IRQ_DMA8
DMA8
N
Direct Memory Access Channel 8
25
IRQ_DMA9
DMA9
N
Direct Memory Access Channel 9
26
IRQ_DMA10
DMA10
N
Direct Memory Access Channel 10
27
IRQ_DMA11
DMA11
N
Direct Memory Access Channel 11
Bit
DS00002022B-page 112
Source Description
2016 Microchip Technology Inc.
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TABLE 9-16:
BIT DEFINITIONS FOR GIRQ13 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
[30:28]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.7
GIRQ14
TABLE 9-17:
Source Description
BIT DEFINITIONS FOR GIRQ14 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
[1:0]
Reserved
Reserved
N
Source Description
Reserved
2
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
[30:3]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.8
GIRQ15
TABLE 9-18:
BIT DEFINITIONS FOR GIRQ15 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
0
UART_0
UART
N
The UART interrupt event output indicates if an interrupt
is pending. See Table 8-13, “Interrupt Control Table,” on
page 89.
Source Description
1
Reserved
Reserved
N
Reserved
2
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
5:3
Reserved
Reserved
N
Reserved
6
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
7
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
8
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
9
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
10
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
11
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
12
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
13
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
14
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
15
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
16
MCHP Reserved MCHP Reserved
N
MCHP Reserved
[30:17]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
2016 Microchip Technology Inc.
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9.9.9
GIRQ16
TABLE 9-19:
BIT DEFINITIONS FOR GIRQ16 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
[2:0]
Reserved
Reserved
N
Source Description
Reserved
3
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
[30:4]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.10
GIRQ17
TABLE 9-20:
BIT DEFINITIONS FOR GIRQ17 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
IRQ_TACH0
TACH
N
This internal signal is generated from the OR’d result of
the status events, as defined in the TACHx Status Register..
1
IRQ_TACH1
TACH
N
This internal signal is generated from the OR’d result of
the status events, as defined in the TACHx Status Register.
2
MCHP Reserved
MCHP Reserved
Y
MCHP Reserved
3
MCHP Reserved
MCHP Reserved
Y
MCHP Reserved
4
MCHP Reserved
MCHP Reserved
Y
MCHP Reserved
5
MCHP Reserved
MCHP Reserved
Y
MCHP Reserved
6
BC_INT_N_WK
BC_LINK
Y
Interrupt from the BC_LINK Companion BC_INT# pin
(see Note 9-2 on page 118).
[9:7]
Reserved
Reserved
N
Reserved
10
ADC_SNGL
ADC_Single_Int
N
Interrupt signal from ADC controller to EC for SingleSample ADC conversion
11
ADC_RPT
ADC_Repeat_Int
N
Interrupt signal from ADC controller to EC for Repeated
ADC conversion
12
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
13
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
14
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
15
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
16
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
17
MCHP Reserved
MCHP Reserved
N
MCHP Reserved
18
RTC
RTC
Y
RTC Interrupt
19
RTC ALARM
RTC ALARM
Y
RTC Alarm Interrupt
20
HTIMER
HTIMER
Y
Signal indicating that the hibernation timer is enabled and
has expired.
21
KEYSCAN
KSC_INT
N
Keyboard Scan Interface runtime interrupt
22
KEYSCAN wake
KSC_INT_WAKE
Y
Keyboard Scan Interface wake interrupt
23
RPM_INT Stall
Fan Stall Status
Interrupt
N
RPM-PWM Interface DRIVE_FAIL & FAN_SPIN indication
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2016 Microchip Technology Inc.
CEC1302
TABLE 9-20:
BIT DEFINITIONS FOR GIRQ17 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
24
Source Name
Wake
RPM_INT Spin
Fan Fail/Spin Status Interrupt
N
RPM-PWM Interface SPIN indication
25
PFR_Status
PFR_Status
N
Power-Fail and Reset Status Register events (VBAT POR
and WDT).
26
PWM_WDT[0]
PWM_WDT
N
PWM watchdog time out interrupt from Blinking/Breathing
PWM block
27
PWM_WDT[1]
PWM_WDT
N
PWM watchdog time out interrupt from Blinking/Breathing
PWM block
28
PWM_WDT[2]
PWM_WDT
N
PWM watchdog time out interrupt from Blinking/Breathing
PWM block
29
BCM_ERR
BCM_INT Err
N
BC_LINK Master Error Flag Interrupt
30
BCM_BUSY_CLR
BCM_INT Busy
N
BC_LINK Master Busy Clear Flag Interrupt
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.11
GIRQ18
TABLE 9-21:
Source Description
BIT DEFINITIONS FOR GIRQ18 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
0
SPI0 TX
TXBE_STS
N
SPI controller 0 Interrupt output to EC driven by TXBE
status bit
1
SPI0 RX
RXBF_STS
N
SPI controller 0 Interrupt output to EC driven by RXBE
status bit
2
SPI1 TX
TXBE_STS
N
SPI controller 1 Interrupt output to EC driven by TXBE
status bit
3
SPI1 RX
RXBF_STS
N
SPI controller 1 Interrupt output to EC driven by RXBE
status bit
4
PWM_WDT[3]
PWM_WDT
N
PWM watchdog time out interrupt from Blinking/Breathing
PWM block
5
PKE ERROR
PKE ERROR
N
PKE core error detected
6
PKE END
PKE END
N
PKE core finished processing data
7
RNG
RNG
N
Interrupt from RNG block
Interrupt from AES block
Source Description
8
AES
AES
N
9
HASH
HASH
N
Interrupt from HASH block
[30:10]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
2016 Microchip Technology Inc.
DS00002022B-page 115
CEC1302
9.9.12
GIRQ19
TABLE 9-22:
BIT DEFINITIONS FOR GIRQ19 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
0
VCC_PWRGD
VCC_PWRGD
Y
VCC_PWRGD interrupt from pin (see Note 9-2 on
page 118).
1
LRESET#
LRESET#
Y
LRESET# interrupt from pin (see Note 9-2 on page 118).
[30:2]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.13
Source Description
GIRQ20
TABLE 9-23:
BIT DEFINITIONS FOR GIRQ20 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
[4:0]
GPIO[204:200]
GPIO_Event
Y
Bits[0:4] are controlled by the GPIO_Events generated by
GPIO200 through GPIO204, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
5
Reserved
Reserved
N
Reserved
6
GPIO206
GPIO_Event
Y
Bit 6 is controlled by the GPIO_Events generated by
GPIO206.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
7
Reserved
Reserved
N
Reserved
[9:8]
GPIO[211:210]
GPIO_Event
Y
Bits[8:9] are controlled by the GPIO_Events generated by
GPIO210 through GPIO211, respectively.
The GPIO Interface can generate an interrupt source
event on a high level, low level, rising edge and falling
edge, as configured by the Interrupt Detection (int_det)
bits in the Pin Control Register associated with the GPIO
signal function.
[11:10]
MCHP Reserved
MCHP Reserved
N/A
[30:12]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
DS00002022B-page 116
MCHP Reserved
2016 Microchip Technology Inc.
CEC1302
9.9.14
GIRQ21
TABLE 9-24:
BIT DEFINITIONS FOR GIRQ21 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
[1:0]
MCHP Reserved
n/a
n/a
[30:2]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.15
Source Description
n/a
GIRQ22
TABLE 9-25:
BIT DEFINITIONS FOR GIRQ22 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
[30:0]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
9.9.16
Source Description
GIRQ23
TABLE 9-26:
BIT DEFINITIONS FOR GIRQ23 SOURCE, ENABLE, AND RESULT REGISTERS
Bit
Block Instance
Name
Source Name
Wake
Source Description
0
16-bit Timer_0
TIMER_32_x
N
This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
1
16-bit Timer_1
TIMER_32_x
N
This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
2
16-bit Timer_2
TIMER_32_x
N
This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
3
16-bit Timer_3
TIMER_32_x
N
This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
4
32-bit Timer_0
TIMER_32_x
N
This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
5
32-bit Timer_1
TIMER_32_x
N
This interrupt event fires when a 32-bit timer x reaches its
limit. This event is sourced by the tEVENT_INTERRUPT
status bit if enabled.
[30:6]
Reserved
Reserved
N
Reserved
31
n/a
n/a
N
See Table 9-7, "GIRQx Source Register", Table 9-8,
"GIRQx Enable Set Register", Table 9-10, "GIRQx Enable
Clear Register", and Table 9-9, "GIRQx Result Register"
for a definition of this bit for the Source, Enable, and
Result registers.
2016 Microchip Technology Inc.
DS00002022B-page 117
CEC1302
Note 9-2
9.9.17
All wakeup interrupts associated with pins must be configured as falling edge interrupts through the
associated GPIO control register.
BLOCK ENABLE SET REGISTER
Offset
POWER
200h
32-bit
VCC1
0000_0000h
Size
VCC1_RESET
Default
BIT
D31
D30
D29
D28
D27
D26
D25
D24
TYPE
R
R
R
R
R
R
R
R
Reserved
BIT NAME
BIT
D23
D22
D21
D20
D19
D18
D17
D16
TYPE
R/WS
R/WS
R/WS
R/WS
R/WS
R/WS
R/WS
R/WS
IRQ Vector Enable Set [23:16]
BIT NAME
BIT
D15
D14
D13
D12
D11
D10
D9
D8
TYPE
R/WS
R/WS
R/WS
R/WS
R/WS
R/WS
R/WS
R/WS
IRQ Vector Enable Set [15:8]
BIT NAME
BIT
D7
D6
D5
D4
D3
D2
D1
D0
TYPE
R
R
R
R
R
R
R
R
BIT NAME
Reserved
IRQ Vector Enable Set [31:0]
Each IRQ Vector can be individually enabled to assert an interrupt event to the EC.
0= Writing a zero has no effect.
1= Writing a one will enable respective IRQi.
Reading always returns the current value of the IRQ i VECTOR ENABLE bit. The state of the IRQ i VECTOR ENABLE
bit is determined by the corresponding IRQ i Vector Enable Set bit and the IRQ i Vector Enable Clear bit. (0=disabled,
1-enabled).
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2016 Microchip Technology Inc.
CEC1302
9.9.18
BLOCK ENABLE CLEAR REGISTER
Offset
POWER
204h
32-bit
VCC1
0000_0000h
Size
VCC1_RESET
Default
BIT
D31
D30
D29
D28
D27
D26
D25
D24
TYPE
R
R
R
R
R
R
R
R
Reserved
BIT NAME
BIT
D23
D22
D21
D20
D19
D18
D17
D16
TYPE
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
IRQ Vector Enable Clear [23:16]
BIT NAME
BIT
D15
D14
D13
D12
D11
D10
D9
D8
TYPE
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
IRQ Vector Enable Clear [15:8]
BIT NAME
BIT
D7
D6
D5
D4
D3
D2
D1
D0
TYPE
R
R
R
R
R
R
R
R
Reserved
BIT NAME
IRQ Vector Enable Clear[31:0]
Each IRQ Vector can be individually disabled to assert an interrupt event to the EC.
0= Writing a zero has no effect.
1= Writing a one will disable respective IRQi vector.
Reading always returns the current value of the IRQ i VECTOR ENABLE bit. The state of the IRQ i VECTOR ENABLE
bit is determined by the corresponding IRQ i Vector Enable Set bit and the IRQ i Vector Enable Clear bit. (0=disabled,
1-enabled).
9.9.19
BLOCK IRQ VECTOR REGISTER
Offset
POWER
208h
32-bit
VCC1
0000_0000h
Size
VCC1_RESET
Default
BIT
D31
D30
D29
D28
D27
D26
D25
D24
TYPE
R
R
R
R
R
R
R
R
Reserved
BIT NAME
BIT
D23
D22
D21
D20
D19
D18
D17
D16
TYPE
R
R
R
R
R
R
R
R
IRQ Vector [23:16]
BIT NAME
BIT
D15
D14
D13
D12
D11
D10
D9
D8
TYPE
R
R
R
R
R
R
R
R
IRQ Vector [15:8]
BIT NAME
BIT
D7
D6
D5
D4
D3
D2
D1
D0
TYPE
R
R
R
R
R
R
R
R
BIT NAME
2016 Microchip Technology Inc.
Reserved
DS00002022B-page 119
CEC1302
IRQ Vector [31:0]
Each read only bit reflects the current state of the IRQ i vector to the EC.
Note:
If the IRQ i vector is disabled via the Block Enable Clear Register the corresponding IRQ i vector to the EC
is forced to 0. If the IRQ i vector is enabled, the corresponding IRQ i vector to the EC represents the current
status of the IRQ event.
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2016 Microchip Technology Inc.
CEC1302
10.0
WATCHDOG TIMER (WDT)
10.1
Introduction
The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
When enabled, the Watchdog Timer (WDT) circuit will generate a WDT Event if the user program fails to reload the WDT
within a specified length of time known as the WDT Interval.
10.2
References
No references have been cited for this chapter.
10.3
Terminology
There is no terminology defined for this chapter.
10.4
Interface
This block is designed to be accessed internally via a registered host interface or externally via the signal interface.
10.5
Host Interface
FIGURE 10-1:
I/O DIAGRAM OF BLOCK
Watchdog Timer (WDT)
Host Interface
Clock Inputs
Resets
WDT Event
The registers defined for the Watchdog Timer (WDT) are accessible by the embedded controller as indicated in Section
10.8, "EC-Only Registers". All registers accesses are synchronized to the host clock and complete immediately. Register reads/writes are not delayed by the 32KHz_Clk.
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CEC1302
10.6
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
10.6.1
POWER DOMAINS
TABLE 10-1:
POWER SOURCES
Name
VCC1
10.6.2
Description
The logic and registers implemented in this block reside on this single
power well.
CLOCK INPUTS
TABLE 10-2:
CLOCK INPUTS
Name
32KHz_Clk
10.6.3
Description
The 32KHz_Clk clock input is the clock source to the Watchdog Timer
functional logic, including the counter.
RESETS
TABLE 10-3:
RESET SIGNALS
Name
Description
VCC1_RESET
Power on Reset to the block. This signal resets all the register and logic
in this block to its default state.
TABLE 10-4:
RESET OUTPUT EVENT
Source
WDT Event
Description
Pulse generated when WDT expires. This signal is used to reset the
embedded controller and its subsystem.
The event is cleared after an VCC1_RESET.
10.7
Description
10.7.1
10.7.1.1
WDT OPERATION
WDT Activation Mechanism
The WDT is activated by the following sequence of operations during normal operation:
1.
2.
Load the WDT Load Register with the count value.
Set the WDT Enable bit in the WDT Control Register.
The WDT Activation Mechanism starts the WDT decrementing counter.
10.7.1.2
WDT Deactivation Mechanism
The WDT is deactivated by the clearing the WDT Enable bit in the WDT Control Register. The WDT Deactivation Mechanism places the WDT in a low power state in which clock are gated and the counter stops decrementing.
10.7.1.3
WDT Reload Mechanism
The WDT must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise, the WDT
will underflow and a WDT Event will be generated and the WDT Status bit will be set in the WDT Control Register. It is
the responsibility of the user program to continually execute code which reloads the watchdog timer, causing the counter
to be reloaded
There are three methods of reloading the WDT: a write to the WDT Load Register, a write to the WDT Kick Register, or
WDT event.
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CEC1302
10.7.1.4
WDT Interval
The WDT Interval is the time it takes for the WDT to decrements from the WDT Load Register value to 0000h. The WDT
Count Register value takes 33/32KHz_Clk seconds (ex. 33/32.768 KHz = 1.007ms) to decrement by 1 count.
10.8
EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Watchdog Timer (WDT). The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
EC-Only Register Base Address Table.
TABLE 10-5:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address
WDT
0
EC
32-bit internal
address space
4000_0400h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 10-6:
EC-ONLY REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
WDT Load Register
04h
WDT Control Register
08h
WDT Kick Register
0Ch
WDT Count Register
10.8.1
WDT LOAD REGISTER
Offset
00h
Bits
Description
15:0 WDT Load
Writing this field reloads the Watch Dog Timer counter.
10.8.2
Reset
Event
Type
Default
R/W
Fh
Type
Default
Reset
Event
R
-
-
R/WC
0b
VCC1_R
ESET
VCC1_R
ESET
WDT CONTROL REGISTER
Offset
04h
Bits
Description
7:2 RESERVED
1 WDT Status
WDT_RST is set by hardware if the last reset of CEC1302 was
caused by an underflow of the WDT. See Section 10.7.1.3, "WDT
Reload Mechanism," on page 122 for more information.
This bit must be cleared by the EC firmware writing a ‘1’ to this bit.
Writing a ‘0’ to this bit has no effect.
2016 Microchip Technology Inc.
DS00002022B-page 123
CEC1302
Offset
04h
Bits
Description
0 WDT Enable
In WDT Operation, the WDT is activated by the sequence of operations defined in Section 10.7.1.1, "WDT Activation Mechanism" and
deactivated by the sequence of operations defined in Section
10.7.1.2, "WDT Deactivation Mechanism".
Type
Default
R/W
0b
Type
Default
W
n/a
Type
Default
R
Fh
Reset
Event
VCC1_R
ESET
0 = block disabled
1 = block enabled
Note:
10.8.3
The default of the WDT is inactive.
WDT KICK REGISTER
Offset
08h
Bits
Description
7:0 Kick
The WDT Kick Register is a strobe. Reads of the WDT Kick Register
return 0. Writes to the WDT Kick Register cause the WDT to reload
the WDT Load Register value and start decrementing when the
WDT Enable bit in the WDT Control Register is set to ‘1’. When the
WDT Enable bit in the WDT Control Register is cleared to ‘0’, writes
to the WDT Kick Register have no effect.
10.8.4
Reset
Event
VCC1_R
ESET
WDT COUNT REGISTER
Offset
0Ch
Bits
Description
15:0 WDT Count
This read-only register provide the current WDT count.
DS00002022B-page 124
Reset
Event
VCC1_R
ESET
2016 Microchip Technology Inc.
CEC1302
11.0
BASIC TIMER
11.1
Introduction
This timer block offers a simple mechanism for firmware to maintain a time base. This timer may be instantiated as 16
bits or 32 bits. The name of the timer instance indicates the size of the timer.
11.2
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 11-1:
I/O DIAGRAM OF BLOCK
Basic Timer
Host Interface
Clock Inputs
Signal Description
Resets
Interrupts
11.3
Signal Description
There are no external signals for this block.
11.4
Host Interface
The embedded controller may access this block via the registers defined in Section 11.9, "EC-Only Registers," on
page 127.
11.5
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
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DS00002022B-page 125
CEC1302
11.5.1
POWER DOMAINS
TABLE 11-1:
11.5.2
Description
VCC1
The timer control logic and registers are all implemented on this single
power domain.
CLOCK INPUTS
Name
Description
48 MHz Ring Oscillator
This is the clock source to the timer logic. The Pre-scaler may be used
to adjust the minimum resolution per bit of the counter.
RESETS
TABLE 11-3:
11.6
Name
CLOCK INPUTS
TABLE 11-2:
11.5.3
POWER SOURCES
RESET SIGNALS
Name
Description
VCC1_RESET
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
Soft Reset
This reset signal, which is created by this block, resets all the logic and
registers to their initial default state. This reset is generated by the block
when the SOFT_RESET bit is set in the Timer Control Register register.
Timer_Reset
This reset signal, which is created by this block, is asserted when either
the VCC1_RESET or the Soft Reset signal is asserted. The VCC1_RESET and Soft Reset signals are OR’d together to create this signal.
Interrupts
TABLE 11-4:
EC INTERRUPTS
Source
11.7
Description
TIMER_16_x
This interrupt event fires when a 16-bit timer x reaches its limit. This
event is sourced by the EVENT_INTERRUPT status bit if enabled.
TIMER_32_x
This interrupt event fires when a 32-bit timer x reaches its limit. This
event is sourced by the tEVENT_INTERRUPT status bit if enabled.
Low Power Modes
The Basic Timer may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry. This block
is only be permitted to enter low power modes when the block is not active.
The sleep state of this timer is as follows:
• Asleep while the block is not Enabled
• Asleep while the block is not running (start inactive).
• Asleep while the block is halted (even if running).
The block is active while start is active.
DS00002022B-page 126
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CEC1302
11.8
Description
FIGURE 11-2:
BLOCK DIAGRAM
Basic Timer
48 MHz
Pre-Scaler
Host Interface
REGS
Timer Logic
This timer block offers a simple mechanism for firmware to maintain a time base in the design. The timer may be enabled
to execute the following features:
•
•
•
•
•
Programmable resolution per LSB of the counter via the Pre-scale bits in the Timer Control Register
Programmable as either an up or down counter
One-shot or Continuous Modes
In one-shot mode the Auto Restart feature stops the counter when it reaches its limit and generates a level event.
In Continuous Mode the Auto Restart feature restarts that counter from the programmed preload value and generates a pulse event.
• Counter may be reloaded, halted, or started via the Timer Control register
• Block may be reset by either a Power On Reset (POR) or via a Soft Reset.
11.9
EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Basic Timer. The addresses
of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the EC-Only
Register Base Address Table.
TABLE 11-5:
EC-ONLY REGISTER BASE ADDRESS TABLE
Instance
Number
Host
Address Space
Base Address
TIMER16 (16-bit
Timer)
0
EC
32-bit internal
address space
4000_0C00h
TIMER16 (16-bit
Timer)
1
EC
32-bit internal
address space
4000_0C20h
TIMER16 (16-bit
Timer)
2
EC
32-bit internal
address space
4000_0C40h
TIMER16 (16-bit
Timer)
3
EC
32-bit internal
address space
4000_0C60h
TIMER32 (32-bit
Timer)
0
EC
32-bit internal
address space
4000_0C80h
TIMER32 (32-bit
Timer)
1
EC
32-bit internal
address space
4000_0CA0h
Block Instance
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CEC1302
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 11-6:
RUNTIME REGISTER SUMMARY
Offset
Register Name
00h
Timer Count Register
04h
Timer Preload Register
08h
Timer Status Register
0Ch
Timer Int Enable Register
10h
Timer Control Register
11.9.1
TIMER COUNT REGISTER
Offset
00h
Bits
Description
31:0 COUNTER
This is the value of the Timer counter. This is updated by Hardware
but may be set by Firmware. If it is set while the Hardware Timer is
operating, functionality can not be maintained. When read, it is buffered so single byte reads will be able to catch the full 4 byte register
without it changing.
Type
Default
R/W
0h
Type
Default
R/W
0h
Type
Default
Reset
Event
Timer_Reset
The size of the Counter is indicated by the instance name. Bits 0 to
(size-1) are r/w counter bits. Bits 31 down to size are reserved.
Reads return 0 and writes have no effect.
11.9.2
TIMER PRELOAD REGISTER
Offset
04h
Bits
Description
31:0 PRE_LOAD
This is the value of the Timer pre-load for the counter. This is used
by H/W when the counter is to be restarted automatically; this will
become the new value of the counter upon restart.
Reset
Event
Timer_Reset
The size of the Pre-Load value is the same as the size of the
counter. The size of the Counter is indicated by the instance name.
Bits 0 to (size-1) are r/w pre-load bits. Bits 31 down to size are
reserved. Reads return 0 and writes have no effect.
11.9.3
TIMER STATUS REGISTER
Offset
08h
Bits
Description
31:0 Reserved
0 EVENT_INTERRUPT
This is the interrupt status that fires when the timer reaches its limit.
This may be level or a self clearing signal cycle pulse, based on the
AUTO_RESTART bit in the Timer Control Register. If the timer is set
to automatically restart, it will provide a pulse, otherwise a level is
provided.
DS00002022B-page 128
Reset
Event
R
-
-
R/WC
0h
Timer_Reset
2016 Microchip Technology Inc.
CEC1302
11.9.4
TIMER INT ENABLE REGISTER
Offset
0Ch
Bits
Description
31:0 Reserved
0 EVENT_INTERRUPT_ENABLE
This is the interrupt enable for the status EVENT_INTERRUPT bit in
the Timer Status Register
11.9.5
Type
Default
Reset
Event
R
-
-
R/W
0h
Timer_Reset
Type
Default
R/W
0h
Timer_Reset
R
-
-
R/W
0h
Timer_Reset
R/W
0h
Timer_Reset
TIMER CONTROL REGISTER
Offset
10h
Bits
Description
31:16 PRE_SCALE
This is used to divide down the system clock through clock enables
to lower the power consumption of the block and allow slow timers.
Updating this value during operation may result in erroneous clock
enable pulses until the clock divider restarts.
The number of clocks per clock enable pulse is (Value + 1); a setting
of 0 runs at the full clock speed, while a setting of 1 runs at half
speed.
15:8 Reserved
7 HALT
This is a halt bit. This will halt the timer as long as it is active. Once
the halt is inactive, the timer will start from where it left off.
Reset
Event
1=Timer is halted. It stops counting. The clock divider will also be
reset.
0=Timer runs normally
6 RELOAD
This bit reloads the counter without interrupting it operation. This will
not function if the timer has already completed (when the START bit
in this register is ‘0’). This is used to periodically prevent the timer
from firing when an event occurs. Usage while the timer is off may
result in erroneous behavior.
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CEC1302
Offset
10h
Bits
Description
Reset
Event
Type
Default
R/W
0h
Timer_Reset
4 SOFT_RESET
This is a soft reset.
This is self clearing 1 cycle after it is written.
WO
0h
Timer_Reset
3 AUTO_RESTART
This will select the action taken upon completing a count.
R/W
0h
Timer_Reset
R/W
0h
Timer_Reset
R
-
-
R/W
0h
Timer_Reset
5 START
This bit triggers the timer counter. The counter will operate until it
hits its terminating condition. This will clear this bit. It should be
noted that when operating in restart mode, there is no terminating
condition for the counter, so this bit will never clear. Clearing this bit
will halt the timer counter.
Setting this bit will:
• Reset the clock divider counter.
• Enable the clock divider counter.
• Start the timer counter.
• Clear all interrupts.
Clearing this bit will:
• Disable the clock divider counter.
• Stop the timer counter.
1=The counter will automatically restart the count, using the contents
of the Timer Preload Register to load the Timer Count Register
The interrupt will be set in edge mode
0=The counter will simply enter a done state and wait for further control inputs. The interrupt will be set in level mode.
2 COUNT_UP
This selects the counter direction.
When the counter in incrementing the counter will saturate and trigger the event when it reaches all F’s. When the counter is decrementing the counter will saturate when it reaches 0h.
1=The counter will increment
0=The counter will decrement
1 Reserved
0 ENABLE
This enables the block for operation.
1=This block will function normally
0=This block will gate its clock and go into its lowest power state
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CEC1302
12.0
HIBERNATION TIMER
12.1
Introduction
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode.
This block supports wake events up to 2 hours in duration. The timer is a 16-bit binary count-down timer that can be
programmed in 30.5µs and 0.125 second increments for period ranges of 30.5µs to 2s or 0.125s to 136.5 minutes,
respectively. Writing a non-zero value to this register starts the counter from that value. A wake-up interrupt is generated
when the count reaches zero.
12.2
References
No references have been cited for this chapter
12.3
Terminology
No terms have been cited for this chapter.
12.4
Interface
This block is an IP block designed to be incorporated into a chip. It is designed to be accessed externally via the pin
interface and internally via a registered host interface. The following diagram illustrates the various interfaces to the
block.
FIGURE 12-1:
HIBERNATION TIMER INTERFACE DIAGRAM
Hibernation Timer
Host Interface
Signal Description
Clock Inputs
Resets
Interrupts
12.5
Signal Description
There are no external signals for this block.
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12.6
Host Interface
The registers defined for the Hibernation Timer are accessible by the various hosts as indicated in Section 12.10, "ECOnly Registers".
12.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
12.7.1
POWER DOMAINS
TABLE 12-1:
12.7.2
POWER SOURCES
Name
Description
VCC1
The timer control logic and registers are all implemented on this single
power domain.
CLOCK INPUTS
TABLE 12-2:
CLOCK INPUTS
Name
Description
32KHz_Clk
This is the clock source to the timer logic. The Pre-scaler may be used
to adjust the minimum resolution per bit of the counter.
if the main oscillator is stopped then an external 32.768kHz clock source
must be active for the Hibernation Timer to continue to operate.
12.7.3
RESETS
TABLE 12-3:
12.8
RESET SIGNALS
Name
Description
VCC1_RESET
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
Interrupts
This section defines the interrupt Interface signals routed to the chip interrupt aggregator.
Each instance of the Hibernation Timer in the CEC1302 can be used to generate interrupts and wake-up events when
the timer decrements to zero. The Hibernation Timer interrupt is are routed to the HTIMER bit in the GIRQ17 Source
Register.
TABLE 12-4:
12.9
INTERRUPT INTERFACE SIGNAL DESCRIPTION TABLE
Name
Direction
Description
HTIMER
Output
Signal indicating that the timer is enabled and decrements to 0. This
signal is used to generate an Hibernation Timer interrupt event.
Low Power Modes
The Hibernation Timer may be put into a low power state by the chip Power, Clocks, and Reset (PCR) circuitry.
The timer operates off of the 32KHz_Clk, and therefore will operate normally when 48 MHz Ring Oscillator is stopped.
The sleep enable inputs have no effect on the Hibernation Timer and the clock required outputs are only asserted during
register read/write cycles for as long as necessary to propagate updates to the block core.
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12.10 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Hibernation Timer. The
addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in the
EC-Only Register Base Address Table.
TABLE 12-5:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Hibernation Timer
0
EC
Address Space
Base Address
32-bit internal
4000_9800h
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 12-6:
HIBERNATION TIMER SUMMARY
Offset
Register Name
00h
HTimer Preload Register
04h
HTimer Control Register
08h
HTimer Count Register
12.10.1
Offset
HTIMER PRELOAD REGISTER
00h
Bits
Description
15:0 HT_PRELOAD
This register is used to set the Hibernation Timer Preload value.
Writing this register to a non-zero value resets the down counter to
start counting down from this programmed value. Writing this register to 0000h disables the hibernation counter. The resolution of this
timer is determined by the CTRL bit in the HTimer Control Register.
Writes to the HTimer Control Register are completed with an EC bus
cycle.
12.10.2
Offset
R/W
000h
Type
Default
Reset
Event
R
-
-
R
0000h
VCC1_R
ESET
Type
Default
R
0000h
VCC1_R
ESET
04h
Description
15:1 Reserved
0 CTRL
1= The Hibernation Timer has a resolution of 0.125s per LSB, which
yields a maximum time in excess of 2 hours.
0= The Hibernation Timer has a resolution of 30.5µs per LSB, which
yields a maximum time of ~2seconds.
Offset
Default
HTIMER CONTROL REGISTER
Bits
12.10.3
Reset
Event
Type
HTIMER COUNT REGISTER
08h
Bits
Description
15:0 COUNT
The current state of the Hibernation Timer.
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Reset
Event
VCC1_R
ESET
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13.0
RTC WITH DATE AND DST ADJUSTMENT
13.1
Introduction
This block provides the capabilities of an industry-standard 146818B Real-Time Clock module, without CMOS RAM.
Enhancements to this architecture include:
•
•
•
•
Industry standard Day of Month Alarm field, allowing for monthly alarms
Configurable, automatic Daylight Savings adjustment
Week Alarm for periodic interrupts and wakes based on Day of Week
System Wake capability on interrupts.
13.2
1.
2.
References
Motorola 146818B Data Sheet, available on-line
Intel Lynx Point PCH EDS specification
13.3
Terminology
Time and Date Registers:
This is the set of registers that are automatically counted by hardware every 1 second while the block is enabled to run
and to update. These registers are: Seconds, Minutes, Hours, Day of Week, Day of Month, Month, and Year.
13.4
Interface
This block’s connections are entirely internal to the chip.
FIGURE 13-1:
I/O DIAGRAM OF BLOCK
RTC With Date and DST Adjustment
Host Interface
Signal Description
Clocks
Resets
Interrupts
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13.5
Signal Description
There are no external signals.
13.6
Host Interface
The registers defined for the RTC With Date and DST Adjustment are accessible by the host and EC.
13.7
Power, Clocks and Resets
This section defines the Power, Clock, and Reset parameters of the block.
13.7.1
POWER DOMAINS
TABLE 13-1:
POWER SOURCES
Name
13.7.2
This power well sources all of the internal registers and logic in this
block.
VCC1
This power well sources only bus communication. The block continues
to operate internally while this rail is down.
CLOCKS
Name
Description
32KHz_Clk
This 32KHz clock input drives all internal logic, and will be present at all
times that the VBAT well is powered.
RESETS
TABLE 13-3:
13.8
VBAT
CLOCKS
TABLE 13-2:
13.7.3
Description
RESET SIGNALS
Name
Description
VBAT_POR
This reset signal is used in the RTC_RST signal to reset all of the
registers and logic in this block. It directly resets the Soft Reset bit in the
RTC Control Register.
RTC_RST
This reset signal resets all of the registers and logic in this block, except
for the Soft Reset bit in the RTC Control Register. It is triggered by
VBAT_POR, but can also be triggered by a Soft Reset from the RTC
Control Register.
VCC1_RESET
This reset signal is used to inhibit the bus communication logic, and
isolates this block from VCC1 powered circuitry on-chip. Otherwise it has
no effect on the internal state.
Interrupts
TABLE 13-4:
SYSTEM INTERRUPTS
Source
Description
RTC
This interrupt source for the SIRQ logic is generated when any of the following events occur:
• Update complete. This is triggered, at 1-second intervals, when the
Time register updates have completed
• Alarm. This is triggered when the alarm value matches the current
time (and date, if used)
• Periodic. This is triggered at the chosen programmable rate
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TABLE 13-5:
13.9
EC INTERRUPTS
Source
Description
RTC
This interrupt is signaled to the Interrupt Aggregator when any of the following events occur:
• Update complete. This is triggered, at 1-second intervals, when the
Time register updates have completed
• Alarm. This is triggered when the alarm value matches the current
time (and date, if used)
• Periodic. This is triggered at the chosen programmable rate
RTC ALARM
This wake interrupt is signaled to the Interrupt Aggregator when an Alarm
event occurs.
Low Power Modes
The RTC has no low-power modes. It runs continuously while the VBAT well is powered.
13.10 Description
This block provides the capabilities of an industry-standard 146818B Real-Time Clock module, excluding the CMOS
RAM and the SQW output. See the following registers, which represent enhancements to this architecture. These
enhancements are listed below.
See the Date Alarm field of Register D for a Day of Month qualifier for alarms.
See the Week Alarm Register for a Day of Week qualifier for alarms.
See the registers Daylight Savings Forward Register and Daylight Savings Backward Register for setting up hands-off
Daylight Savings adjustments.
See the RTC Control Register for enhanced control over the block’s operations.
13.11 Runtime Registers
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
Runtime Register Base Address Table.
TABLE 13-6:
RUNTIME REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
RTC
0
EC
Address Space
Base Address
32-bit internal
400F_2C00h
Address Space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
Add the register’s Offset to this value to obtain the direct address of the register.
TABLE 13-7:
RUNTIME REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
Seconds Register
01h
Seconds Alarm Register
02h
Minutes Register
03h
Minutes Alarm Register
04h
Hours Register
05h
Hours Alarm Register
06h
Day of Week Register
07h
Day of Month Register
08h
Month Register
09h
Year Register
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TABLE 13-7:
RUNTIME REGISTER SUMMARY (CONTINUED)
Offset
Register Name (Mnemonic)
0Ah
Register A
0Bh
Register B
0Ch
Register C
0Dh
Register D
0Eh
(reserved)
0Fh
(reserved)
10h
RTC Control Register
14h
Week Alarm Register
18h
Daylight Savings Forward Register
1Ch
Daylight Savings Backward Register
20h
MCHP Reserved
Note:
This extended register set occupies offsets that have historically been used as CMOS RAM. Code ported
to use this block should be examined to ensure that it does not assume that RAM exists in this block.
13.11.1
SECONDS REGISTER
Offset
00h
Bits
Description
7:0 SECONDS
Displays the number of seconds past the current minute, in the range
0--59. Presentation may be selected as binary or BCD, depending on
the DM bit in Register B. Values written must also use the format
defined by the current setting of the DM bit.
13.11.2
Type
Default
R/W
00h
Type
Default
R/W
00h
Reset
Event
RTC_R
ST
SECONDS ALARM REGISTER
Offset
01h
Bits
Description
7:0 SECONDS_ALARM
Holds a match value, compared against the Seconds Register to trigger the Alarm event. Values written to this register must use the format defined by the current setting of the DM bit in Register B. A value
of 11xxxxxxb written to this register makes it don’t-care (always
matching).
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Reset
Event
RTC_R
ST
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13.11.3
MINUTES REGISTER
Offset
02h
Bits
Description
7:0 MINUTES
Displays the number of minutes past the current hour, in the range 0-59. Presentation may be selected as binary or BCD, depending on
the DM bit in Register B. Values written must also use the format
defined by the current setting of the DM bit.
13.11.4
Type
Default
R/W
00h
Reset
Event
RTC_RS
T
MINUTES ALARM REGISTER
Offset
03h
Bits
Description
7:0 MINUTES_ALARM
Holds a match value, compared against the Minutes Register to trigger the Alarm event. Values written to this register must use the format defined by the current setting of the DM bit in Register B. A value
of 11xxxxxxb written to this register makes it don’t-care (always
matching).
13.11.5
Reset
Event
Type
Default
R/W
00h
Type
Default
R/W
0b
RTC_R
ST
R/W
00h
RTC_R
ST
RTC_R
ST
HOURS REGISTER
Offset
04h
Bits
Description
7 HOURS_AM_PM
In 12-hour mode (see bit “24/12” in register B), this bit indicates AM or
PM.
Reset
Event
1=PM
0=AM
6:0 HOURS
Displays the number of the hour, in the range 1--12 for 12-hour mode
(see bit “24/12” in register B), or in the range 0--23 for 24-hour mode.
Presentation may be selected as binary or BCD, depending on the
DM bit in Register B. Values written must also use the format defined
by the current setting of the DM bit.
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13.11.6
HOURS ALARM REGISTER
Offset
05h
Bits
Description
7:0 HOURS_ALARM
Holds a match value, compared against the Hours Register to trigger
the Alarm event. Values written to this register must use the format
defined by the current settings of the DM bit and the 24/12 bit in Register B. A value of 11xxxxxxb written to this register makes it don’tcare (always matching).
13.11.7
Type
Default
R/W
00h
Type
Default
R/W
00h
Type
Default
R/W
00h
Type
Default
R/W
00h
Reset
Event
RTC_R
ST
DAY OF WEEK REGISTER
Offset
06h
Bits
Description
7:0 DAY_OF_WEEK
Displays the day of the week, in the range 1 (Sunday) through 7 (Saturday). Numbers in this range are identical in both binary and BCD
notation, so this register’s format is unaffected by the DM bit.
13.11.8
Reset
Event
RTC_R
ST
DAY OF MONTH REGISTER
Offset
07h
Bits
Description
7:0 DAY_OF_MONTH
Displays the day of the current month, in the range 1--31. Presentation may be selected as binary or BCD, depending on the DM bit in
Register B. Values written must also use the format defined by the
current setting of the DM bit.
13.11.9
Reset
Event
RTC_R
ST
MONTH REGISTER
Offset
08h
Bits
Description
7:0 MONTH
Displays the month, in the range 1--12. Presentation may be selected
as binary or BCD, depending on the DM bit in Register B. Values written must also use the format defined by the current setting of the DM
bit.
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Reset
Event
RTC_R
ST
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CEC1302
13.11.10 YEAR REGISTER
09h
Offset
Bits
Description
7:0 YEAR
Displays the number of the year in the current century, in the range 0
(year 2000) through 99 (year 2099). Presentation may be selected as
binary or BCD, depending on the DM bit in Register B. Values written
must also use the format defined by the current setting of the DM bit.
Reset
Event
Type
Default
R/W
00h
Type
Default
R
0b
RTC_R
ST
R/W
000b
RTC_R
ST
R/W
0h
RTC_R
ST
RTC_R
ST
13.11.11 REGISTER A
0Ah
Offset
Bits
Description
7 UPDATE_IN_PROGRESS
‘0’ indicates that the Time and Date registers are stable and will not be
altered by hardware soon. ‘1’ indicates that a hardware update of the
Time and Date registers may be in progress, and those registers
should not be accessed by the host program. This bit is set to ‘1’ at a
point 488us (16 cycles of the 32K clock) before the update occurs, and
is cleared immediately after the update. See also the Update-Ended
Interrupt, which provides more useful status.
6:4 DIVISION_CHAIN_SELECT
This field provides general control for the Time and Date register
updating logic.
Reset
Event
11xb=Halt counting. The next time that 010b is written, updates will
begin 500ms later.
010b=Required setting for normal operation. It is also necessary to set
the Block Enable bit in the RTC Control Register to ‘1’ for counting
to begin
000b=Reserved. This field should be initialized to another value before
Enabling the block in the RTC Control Register
Other values Reserved
3:0 RATE_SELECT
This field selects the rate of the Periodic Interrupt source. See
Table 13-8
TABLE 13-8:
REGISTER A FIELD RS: PERIODIC INTERRUPT SETTINGS
RS (hex)
0
Interrupt Period
Never Triggered
1
3.90625 ms
2
7.8125 ms
3
122.070 us
4
244.141 us
5
488.281 us
6
976.5625 us
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CEC1302
TABLE 13-8:
REGISTER A FIELD RS: PERIODIC INTERRUPT SETTINGS (CONTINUED)
RS (hex)
Interrupt Period
7
1.953125 ms
8
3.90625 ms
9
7.8125 ms
A
15.625 ms
B
31.25 ms
C
62.5 ms
D
125 ms
E
250 ms
F
500 ms
13.11.12 REGISTER B
Offset
0Bh
Bits
Description
Reset
Event
Type
Default
7 UPDATE_CYCLE_INHIBIT
In its default state ‘0’, this bit allows hardware updates to the Time
and Date registers, which occur at 1-second intervals. A ‘1’ written to
this field inhibits updates, allowing these registers to be cleanly written to different values. Writing ‘0’ to this bit allows updates to continue.
R/W
0b
RTC_R
ST
6 PERIODIC_INTERRUPT_ENABLE
R/W
0b
RTC_R
ST
R/W
0b
RTC_R
ST
R/W
0b
RTC_R
ST
1=Alows the Periodic Interrupt events to be propagated as interrupts
0=Periodic events are not propagates as interrupts
5 ALARM_INTERRUPT_ENABLE
1=Alows the Alarm Interrupt events to be propagated as interrupts
0=Alarm events are not propagates as interrupts
4 UPDATE_ENDED_INTERRUPT_ENABLE
1=Alows the Update Ended Interrupt events to be propagated as interrupts
0=Update Ended events are not propagates as interrupts
3 Reserved
2 DATA_MODE
R
-
-
R/W
0b
RTC_R
ST
R/W
0b
RTC_R
ST
1=Binary Mode for Dates and Times
0=BCD Mode for Dates and Times
1 HOUR_FORMAT_24_12
1=24-Hour Format for Hours and Hours Alarm registers. 24-Hour format keeps the AM/PM bit off, with value range 0--23
0=12-Hour Format for Hours and Hours Alarm registers. 12-Hour format has an AM/PM bit, and value range 1--12
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CEC1302
Offset
0Bh
Bits
Description
0 DAYLIGHT_SAVINGS_ENABLE
Type
Default
R/W
0b
Reset
Event
RTC_R
ST
1=Enables automatic hardware updating of the hour, using the registers Daylight Savings Forward and Daylight Savings Backward to
select the yearly date and hour for each update
0=Automatic Daylight Savings updates disabled
Note:
The DATA_MODE and HOUR_FORMAT_24_12 bits affect only how values are presented as they are
being read and how they are interpreted as they are being written. They do not affect the internal contents
or interpretations of registers that have already been written, nor do they affect how those registers are
represented or counted internally. This mode bits may be set and cleared dynamically, for whatever I/O
data representation is desired by the host program.
13.11.13 REGISTER C
Offset
0Ch
Bits
Description
7 INTERRUPT_REQUEST_FLAG
Reset
Event
Type
Default
RC
0b
RTC_R
ST
RC
0b
RTC_R
ST
RC
0b
RTC_R
ST
1=Any of bits[6:4] below is active after masking by their respective
Enable bits in Register B.
0=No bits in this register are active
This bit is automatically cleared by every Read access to this register.
6 PERIODIC_INTERRUPT_FLAG
1=A Periodic Interrupt event has occurred since the last time this register was read. This bit displays status regardless of the Periodic
Interrupt Enable bit in Register B
0=A Periodic Interrupt event has not occurred
This bit is automatically cleared by every Read access to this register.
5 ALARM_FLAG
1=An Alarm event has occurred since the last time this register was
read. This bit displays status regardless of the Alarm Interrupt
Enable bit in Register B.
0=An Alarm event has not occurred
This bit is automatically cleared by every Read access to this register.
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CEC1302
Offset
0Ch
Bits
Description
4 UPDATE_ENDED_INTERRUPT_FLAG
Reset
Event
Type
Default
RC
0b
RTC_R
ST
R
-
-
Type
Default
Reset
Event
1=A Time and Date update has completed since the last time this register was read. This bit displays status regardless of the UpdateEnded Interrupt Enable bit in Register B. Presentation of this status indicates that the Time and Date registers will be valid and stable for over 999ms
0=A Time and Data update has not completed since the last time this
register was read
This bit is automatically cleared by every Read access to this register.
3:0 Reserved
13.11.14 REGISTER D
Offset
0Dh
Bits
Description
7:6 Reserved
R
-
-
R/W
00h
RTC_R
ST
Type
Default
Reset
Event
R
-
-
R/W
0b
RTC_R
ST
2 Microchip Reserved
R/W
0b
RTC_R
ST
1 SOFT_RESET
A ‘1’ written to this bit position will trigger the RTC_RST reset, resetting the block and all registers except this one and the Test Register.
This bit is self-clearing at the end of the reset.
R/W
0b
VBAT_
POR
0 BLOCK_ENABLE
This bit must be ‘1’ in order for the block to function internally. Registers may be initialized first, before setting this bit to ‘1’ to start operation.
R/W
0b
RTC_R
ST
5:0 DATE_ALARM
This field, if set to a non-zero value, will inhibit the Alarm interrupt
unless this field matches the contents of the Month register also. If
this field contains 00h (default), it represents a don’t-care, allowing
more frequent alarms.
13.11.15 RTC CONTROL REGISTER
Offset
10h
Bits
Description
7:4 Reserved
3 ALARM_ENABLE
1=Enables the Alarm features
0=Disables the Alarm features
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13.11.16 WEEK ALARM REGISTER
Offset
14h
Bits
Description
7:0 ALARM_DAY_OF_WEEK
This register, if written to a value in the range 1--7, will inhibit the
Alarm interrupt unless this field matches the contents of the Day of
Week Register also. If this field is written to any value 11xxxxxxb (like
the default FFh), it represents a don’t-care, allowing more frequent
alarms, and will read back as FFh until another value is written.
Reset
Event
Type
Default
R/W
FFh
Type
Default
R/W
0b
RTC_R
ST
R/W
00h
RTC_R
ST
RTC_R
ST
13.11.17 DAYLIGHT SAVINGS FORWARD REGISTER
Offset
18h
Bits
Description
31 DST_FORWARD_AM_PM
This bit selects AM vs. PM, to match bit[7] of the Hours Register if 12Hour mode is selected in Register B at the time of writing.
30:24 DST_FORWARD_HOUR
This field holds the matching value for bits[6:0] of the Hours register.
The written value will be interpreted according to the 24/12 Hour
mode and DM mode settings at the time of writing.
23:19 Reserved
18:16 DST_FORWARD_WEEK
This value matches an internally-maintained week number within the
current month. Valid values for this field are:
Reset
Event
R
-
-
R/W
0h
RTC_R
ST
R
-
-
R/W
0h
RTC_R
ST
R/W
00h
RTC_R
ST
5=Last week of month
4 =Fourth week of month
3=Third week of month
2=Second week of month
1=First week of month
15:11 Reserved
10:8 DST_FORWARD_DAY_OF_WEEK
This field matches the Day of Week Register bits[2:0].
7:0 DST_FORWARD_MONTH
This field matches the Month Register.
This is a 32-bit register, accessible also as individual bytes. When writing as individual bytes, ensure that the DSE bit
(in Register B) is off first, or that the block is disabled or stopped (SET bit), to prevent a time update while this register
may have incompletely-updated contents.
When enabled by the DSE bit in Register B, this register defines an hour and day of the year at which the Hours register
will be automatically incremented by 1 additional hour.
There are no don’t-care fields recognized. All fields must be already initialized to valid settings whenever the DSE bit is
‘1’.
Fields other than Week and Day of Week use the current setting of the DM bit (binary vs. BCD) to interpret the information as it is written to them. Their values, as held internally, are not changed by later changes to the DM bit, without
subsequently writing to this register as well.
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2016 Microchip Technology Inc.
CEC1302
Note:
An Alarm that is set inside the hour after the time specified in this register will not be triggered, because
that one-hour period is skipped. This period includes the exact time (0 minutes: 0 seconds) given by this
register, through the 59 minutes: 59 seconds point afterward.
13.11.18 DAYLIGHT SAVINGS BACKWARD REGISTER
Offset
1Ch
Bits
Description
Reset
Event
Type
Default
31 DST_BACKWARD_AM_PM
This bit selects AM vs. PM, to match bit[7] of the Hours register if 12Hour mode is selected in Register B at the time of writing.
R/W
0b
RTC_R
ST
30:24 DST_BACKWARD_HOUR
This field holds the matching value for bits[6:0] of the Hours register.
The written value will be interpreted according to the 24/12 Hour
mode and DM mode settings at the time of writing.
R/W
00h
RTC_R
ST
R
-
-
R/W
0h
RTC_R
ST
23:19 Reserved
18:16 DST_BACKWARD_WEEK
This value matches an internally-maintained week number within the
current month. Valid values for this field are:
5=Last week of month
4 =Fourth week of month
3=Third week of month
2=Second week of month
1=First week of month
15:11 Reserved
10:8 DST_BACKWARD_DAY_OF_WEEK
This field matches the Day of Week Register bits[2:0].
7:0 DST_BACKWARD_MONTH
This field matches the Month Register.
R
-
-
R/W
0h
RTC_R
ST
R/W
00h
RTC_R
ST
This is a 32-bit register, accessible also as individual bytes. When writing as individual bytes, ensure that the DSE bit
(in Register B) is off first, or that the block is disabled or stopped (SET bit), to prevent a time update while this register
may have incompletely-updated contents.
When enabled by the DSE bit in Register B, this register defines an hour and day of the year at which the Hours register
increment will be inhibited from occurring. After triggering, this feature is automatically disabled for long enough to
ensure that it will not retrigger the second time this Hours value appears, and then this feature is re-enabled automatically.
There are no don’t-care fields recognized. All fields must be already initialized to valid settings whenever the DSE bit is
‘1’.
Fields other than Week and Day of Week use the current setting of the DM bit (binary vs. BCD) to interpret the information as it is written to them. Their values, as held internally, are not changed by later changes to the DM bit, without
subsequently writing to this register as well.
Note:
An Alarm that is set inside the hour before the time specified in this register will be triggered twice, because
that one-hour period is repeated. This period will include the exact time (0 minutes: 0 seconds) given by
this register, through the 59 minutes: 59 seconds point afterward.
2016 Microchip Technology Inc.
DS00002022B-page 145
CEC1302
14.0
GPIO INTERFACE
14.1
General Description
The CEC1302 GPIO Interface provides general purpose input monitoring and output control, as well as managing many
aspects of pin functionality; including, multi-function Pin Multiplexing Control, GPIO Direction control, PU/PD (PU_PD)
resistors, asynchronous wakeup and synchronous Interrupt Detection (int_det), GPIO Direction, and Polarity control, as
well as control of pin drive strength and slew rate.
Features of the GPIO Interface include:
• Inputs:
- Asynchronous rising and falling edge wakeup detection
- Interrupt High or Low Level
• On Output:
- Push Pull or Open Drain output
• Pull up or pull down resistor control
• Interrupt and wake capability available for all GPIOs
• Programmable pin drive strength and slew rate limiting
• Group- or individual control of GPIO data.
• Multiplexing of all multi-function pins are controlled by the GPIO interface
14.2
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
14.2.1
POWER DOMAINS
TABLE 14-1:
POWER SOURCES
Name
VCC1
14.2.2
The registers and logic in this block are powered by VCC1.
CLOCK INPUTS
TABLE 14-2:
CLOCK INPUTS
Name
48 MHz Ring Oscillator
14.2.3
Description
Description
The 48 MHz Ring Oscillator is used for synchronizing the GPIO inputs.
RESETS
TABLE 14-3:
RESET SIGNALS
Name
Description
VCC1_RESET
This reset is asserted when VCC1 is applied.
nSIO_RESET
This is an alternate reset condition, typically asserted when the main
power rail is asserted. This reset is used for VCC Power Well Emulation.
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2016 Microchip Technology Inc.
CEC1302
14.3
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 14-4:
INTERRUPTS
Source
GPIO_Event
Description
Each pin in the GPIO Interface has the ability to generate an interrupt
event. This event may be used as a wake event.
The GPIO Interface can generate an interrupt source event on a high
level, low level, rising edge and falling edge, as configured by the Interrupt Detection (int_det) bits in the Pin Control Register associated with
the GPIO signal function.
Note:
14.4
The minimum pulse width ensured to generate an interrupt/wakeup event is 5ns.
Accessing GPIOs
There are two ways to access GPIO output data. Bit [10] is used to determine which GPIO output data bit affects the
GPIO output pin.
• Output GPIO Data
- Outputs to individual GPIO ports are grouped into 32-bit GPIO Output Registers.
• Alternative GPIO data
- Alternatively, each GPIO output port is individually accessible via Bit [16] in the port’s Pin Control Register. On
reads, Bit [16] returns the programmed value, not the value on the pin.
There are two ways to access GPIO input data.
• Input GPIO Data
- Inputs from individual GPIO ports are grouped into 32-bit GPIO Input Registers and always reflect the current
state of the GPIO input from the pad.
• GPIO input from pad
- Alternatively, each GPIO input port is individually accessible via Bit [24] in the port’s Pin Control Register. Bit
[24] always reflects the current state of GPIO input from the pad.
14.5
GPIO Indexing
Each GPIO signal function name consists of a 4-character prefix (“GPIO”) followed by a 3-digit octal-encoded index
number. In the CEC1302 GPIO indexing is done sequentially starting from ‘GPIO000.’
14.6
GPIO Multiplexing Control
Pin multiplexing depends upon the Mux Control bits in the Pin Control Register. There are two Pin Control Registers for
each GPIO signal function.
The CEC1302 Pin Control Register address offsets shown in the following tables depends on the GPIO Index number.
Pin Control Register defaults are also shown in these tables.
Note 1: Pin Control Register 2 default values are not shown in these tables.
2: The GPIO143/RSMRST# pin operates as described in Section 1.6, "Notes for Tables in this Chapter," on
page 36 when it is configured as a GPIO; the RSMRST# function is not a true alternate function. For proper
RSMRST# operation on the pin, the GPIO143 control register must not be changed from the GPIO default
function.
3: The VCC1_RST#/GPIO131 pin cannot be used as a GPIO pin. The input path to the VCC1_RST# logic is
always active and will cause a reset if this pin is set low in GPIO mode.
4: The KSI[7:0] pins have the internal pullups enabled by ROM boot code. Therefore the Pin Control Reg. POR
Value is as follows after the ROM boot code runs:
GPIO043 = 00003001h
GPIO042 = 00003001h
2016 Microchip Technology Inc.
DS00002022B-page 147
CEC1302
GPIO040 = 00003001h
GPIO142 = 00003001h
GPIO032 = 00003001h
GPIO144 = 00003001h
GPIO126 = 00002001h
GPIO125 = 00002001h
TABLE 14-5:
GPIO
Name
(Octal)
GPIO000
GPIO001
GPIO002
GPIO003
GPIO004
GPIO005
GPIO006
GPIO007
GPIO010
GPIO011
GPIO012
GPIO013
GPIO014
GPIO015
GPIO016
GPIO017
GPIO020
GPIO021
GPIO022
GPIO023
GPIO024
GPIO025
GPIO026
GPIO027
GPIO030
GPIO031
GPIO032
GPIO033
GPIO034
GPIO035
GPIO036
GPIO040
PIN CONTROL REGISTERS
Pin Control
Reg. Offset
(Hex)
Pin Control
Reg. POR
Value (Hex)
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
0040
0044
0048
004C
0050
0054
0058
005C
0060
0064
0068
006C
0070
0074
0078
0080
00003000
00003000
00003000
00003000
00003000
00003002
00003000
00000000
00000000
00000002
00000000
00002000
00003000
00002100
00002100
00002100
00000000
00000000
00000000
00000000
00000001
00000000
00003100
00000001
00000000
00000001
00003000
00000001
00000000
00000001
00000001
00003000
DS00002022B-page 148
POR Default Signal Mux Control = Mux Control =
Function
00
01
Mux Control = Mux Control =
10
11
KSO00
KSO06
KSO07
KSO08
KSO10
KSO12
KSO13
GPIO007
GPIO010
GPIO011
GPIO012
32KHZ_OUT
Reserved
I2C0_CLK0
I2C0_DAT0
I2C0_DAT1
GPIO020
GPIO021
GPIO022
GPIO023
GPIO024
GPIO025
Reserved
GPIO027
GPIO030
GPIO031
KSI3
GPIO033
GPIO034
GPIO035
GPIO036
KSI5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
32KHZ_OUT
Reserved
I2C0_CLK0
I2C0_DAT0
I2C0_DAT1
I2C2_CLK0
I2C2_DAT0
I2C1_CLK0
I2C1_DAT0
I2C3_CLK0
I2C3_DAT0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO000
GPIO001
GPIO002
GPIO003
GPIO004
GPIO005
GPIO006
GPIO007
GPIO010
GPIO011
GPIO012
GPIO013
GPIO014
GPIO015
GPIO016
GPIO017
GPIO020
GPIO021
GPIO022
GPIO023
GPIO024
GPIO025
GPIO026
GPIO027
GPIO030
GPIO031
GPIO032
GPIO033
GPIO034
GPIO035
GPIO036
GPIO040
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM2
Reserved
Reserved
Reserved
KSO00
KSO06
KSO07
KSO08
KSO10
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
KSI3
Reserved
TACH2PWM_OUT
Reserved
Reserved
KSI5
2016 Microchip Technology Inc.
CEC1302
GPIO
Name
(Octal)
GPIO041
GPIO042
GPIO043
GPIO044
GPIO045
GPIO046
GPIO047
GPIO050
GPIO051
GPIO052
GPIO053
GPIO054
GPIO055
GPIO056
GPIO057
GPIO060
GPIO061
GPIO062
GPIO063
GPIO064
GPIO065
GPIO066
GPIO067
GPIO100
GPIO101
GPIO102
GPIO103
GPIO104
GPIO105
GPIO106
GPIO107
GPIO110
Pin Control
Reg. Offset
(Hex)
Pin Control
Reg. POR
Value (Hex)
0084
0088
008C
0090
0094
0098
009C
00A0
00A4
00A8
00AC
00B0
00B4
00B8
00BC
00C0
00C4
00C8
00CC
00D0
00D4
00D8
00DC
0100
0104
0108
010C
0110
0114
0118
011C
0120
00001002
00003000
00003000
00000000
00000000
00003100
00003100
00003100
00003100
00003100
00000000
00000000
0000000C
00003000
00001000
00001001
00001000
00001000
00001000
00000000
00003100
00000000
0000000C
00003000
00003000
00003000
00003000
00003000
00000000
00003000
00003000
00000000
2016 Microchip Technology Inc.
POR Default Signal Mux Control = Mux Control =
Function
00
01
Mux Control = Mux Control =
10
11
Reserved
KSI6
KSI7
GPIO044
GPIO045
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO053
GPIO054
GPIO055
ADC0
ADC1
ADC2
ADC3
ADC4
VCC_PWRGD
GPIO064
Reserved
GPIO066
GPIO067
KSO01
KSO02
KSO03
KSO04
KSO05
GPIO105
KSO09
KSO11
GPIO110
Reserved
Reserved
Reserved
Reserved
PVT_CS1#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO041
GPIO042
GPIO043
GPIO044
GPIO045
GPIO046
GPIO047
GPIO050
GPIO051
GPIO052
GPIO053
GPIO054
GPIO055
GPIO056
GPIO057
GPIO060
GPIO061
GPIO062
GPIO063
GPIO064
GPIO065
GPIO066
GPIO067
GPIO100
GPIO101
GPIO102
GPIO103
GPIO104
GPIO105
GPIO106
GPIO107
GPIO110
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PVT_MOSI
Reserved
ADC0
ADC1
ADC2
ADC3
ADC4
VCC_PWRGD
SHD_MOSI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TFDP_DATA
TFDP_CLK
TACH1
Reserved
Reserved
Reserved
Reserved
KSI6
KSI7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
KSO01
KSO02
KSO03
KSO04
KSO05
Reserved
KSO09
KSO11
Reserved
DS00002022B-page 149
CEC1302
GPIO
Name
(Octal)
GPIO111
GPIO112
GPIO113
GPIO114
GPIO115
GPIO116
GPIO117
GPIO120
GPIO121
GPIO122
GPIO123
GPIO124
GPIO125
GPIO126
GPIO127
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO136
GPIO140
GPIO141
GPIO142
GPIO143
GPIO144
GPIO145
GPIO146
GPIO147
GPIO150
GPIO151
GPIO
Name
(Octal)
GPIO152
GPIO153
GPIO154
GPIO155
GPIO156
GPIO157
GPIO160
GPIO161
GPIO162
GPIO163
GPIO164
GPIO165
GPIO200
GPIO201
GPIO202
GPIO203
GPIO204
GPIO206
GPIO210
GPIO211
Pin Control
Reg. Offset
(Hex)
Pin Control
Reg. POR
Value (Hex)
0124
0128
012C
0130
0134
0138
013C
0140
0144
0148
014C
0150
0154
0158
015C
0160
0164
0168
016C
0170
0174
0178
0180
0184
0188
018C
0190
0194
0198
019C
01A0
01A4
00003000
00003000
00003000
00003000
00003000
00001000
00003000
00003000
00001000
00000000
0000000C
00000000
00002000
00002000
00000000
00000000
00001100
00000000
00000000
00002100
00000000
00000000
00000000
00000000
00003000
00000200
00003000
00000001
00000000
00000001
00000000
00000001
Pin Control
Reg. Offset
(Hex)
Pin Control
Reg. POR
Value (Hex)
01A8
01AC
01B0
01B4
01B8
01BC
01C0
01C4
01C8
01CC
01D0
01D4
0200
0204
0208
020C
0210
0218
0220
0224
00000000
00000000
00002000
00002000
00002000
00000001
00000001
00000001
00000000
00000000
00000000
00000000
0000000C
0000000C
0000000C
0000000C
0000000C
00000000
0000000C
0000000C
DS00002022B-page 150
POR Default Signal Mux Control = Mux Control =
Function
00
01
Mux Control = Mux Control =
10
11
Reserved
Reserved
Reserved
Reserved
Reserved
LRESET#
Reserved
Reserved
nRESET_OUT
GPIO122
GPIO123
GPIO124
KSI0
KSI1
GPIO127
GPIO130
VCC1_RST#
GPIO132
GPIO133
I2C0_CLK1
GPIO135
GPIO136
GPIO140
GPIO141
KSI4
GPIO143
KSI2
GPIO145
GPIO146
GPIO147
GPIO150
GPIO151
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
KSI0
KSI1
Reserved
Reserved
Reserved
Reserved
Reserved
I2C0_CLK1
Reserved
Reserved
Reserved
LED3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO111
GPIO112
GPIO113
GPIO114
GPIO115
GPIO116
GPIO117
GPIO120
GPIO121
GPIO122
GPIO123
GPIO124
GPIO125
GPIO126
GPIO127
GPIO130
GPIO131
GPIO132
GPIO133
GPIO134
GPIO135
GPIO136
GPIO140
GPIO141
GPIO142
GPIO143
GPIO144
GPIO145
GPIO146
GPIO147
GPIO150
GPIO151
Reserved
Reserved
Reserved
Reserved
Reserved
LRESET#
Reserved
Reserved
nRESET_OUT
SHD_SCLK
Reserved
SHD_MISO
Reserved
Reserved
Reserved
Reserved
VCC1_RST#
Reserved
PWM0
Reserved
Reserved
PWM1
TACH2
PWM3
Reserved
RSMRST#
Reserved
Reserved
PVT_CS0#
Reserved
SHD_CS0#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TACH2PWM_IN
Reserved
KSI4
Reserved
KSI2
Reserved
Reserved
Reserved
Reserved
Reserved
POR Default Signal Mux Control = Mux Control =
Function
00
01
Mux Control = Mux Control =
10
11
GPIO152
GPIO153
LED0
LED1
LED2
GPIO157
GPIO160
GPIO161
GPIO162
GPIO163
GPIO164
GPIO165
GPIO200
GPIO201
GPIO202
GPIO203
GPIO204
GPIO206
GPIO210
GPIO211
Reserved
Reserved
LED0
LED1
LED2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SHD_CS1#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO152
GPIO153
GPIO154
GPIO155
GPIO156
GPIO157
GPIO160
GPIO161
GPIO162
GPIO163
GPIO164
GPIO165
GPIO200
GPIO201
GPIO202
GPIO203
GPIO204
GPIO206
GPIO210
GPIO211
Reserved
PVT_SCLK
Reserved
Reserved
Reserved
BC_CLK
BC_DAT
BC_INT#
RXD
Reserved
PVT_MISO
TXD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2016 Microchip Technology Inc.
CEC1302
Note 1: The value of the Pin Control Register 2 for each pin is not shown in the tables above. The default value can
be determined by the current value shown in the “Default Operation” column of the Multiplexing Tables in
Section 1.5.2, "Multiplexing Tables," on page 17 as follows:
2mA: 00000000h
4mA: 00000010h
8mA: 00000020h
12mA: 00000030h
2: The default slew rate is slow.
3: The GPIO041 pin defaults to output low. This pin must be reprogrammed to the GPIO function upon powerup.
14.7
Pin Multiplexing Control
Pin multiplexing depends upon the Mux Control bits in the Pin Control Register. There is a Pin Control Register for
each GPIO signal function. TABLE 14-5: shows default of the register for each GPIO pin.
The registers listed in the Register Summary table are for a single instance of the CEC1302. The addresses of each
register listed in this table are defined as a relative offset to the host “Base Address” defined in the Register Base
Address Table.
TABLE 14-6:
REGISTER BASE ADDRESS TABLE
Instance Name
GPIO
Note 14-1
TABLE 14-7:
Instance
Number
Host
0
EC
Base Address (Note 14-1)
32-bit internal
4008_1000h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
REGISTER SUMMARY
Offset
Register Name
000h - 01Ch
GPIO000-GPIO007 Pin Control Register
020h - 03Ch
GPIO010-GPIO017 Pin Control Register
040h - 05Ch
GPIO020-GPIO027 Pin Control Register
060h - 078h
GPIO030-GPIO036 Pin Control Register
080h - 09Ch
GPIO040-GPIO047 Pin Control Register
0A0h - 0BCh
GPIO050-GPIO057 Pin Control Register
0C0h - 0DCh
GPIO060-GPIO067 Pin Control Register
100h - 11Ch
GPIO100-GPIO107 Pin Control Register
120h - 13Ch
GPIO110-GPIO117 Pin Control Register
140h - 15Ch
GPIO120-GPIO127 Pin Control Register
160h - 178h
GPIO130-GPIO136 Pin Control Register
180h - 19Ch
GPIO140-GPIO147 Pin Control Register
1A0h - 1BCh
GPIO150-GPIO157 Pin Control Register
1C0h - 1D4h
GPIO160-GPIO165 Pin Control Register
200h - 210h
GPIO200-GPIO204 Pin Control Register
218h
Address Space
GPIO206 Pin Control Register
220h - 224h
GPIO210-GPIO211 Pin Control Register
280h
(Note 14-2)
Output GPIO[000:036]
284h
(Note 14-2)
Output GPIO[040:076]
288h
(Note 14-2)
Output GPIO[100:127]
2016 Microchip Technology Inc.
DS00002022B-page 151
CEC1302
TABLE 14-7:
REGISTER SUMMARY (CONTINUED)
Offset
Register Name
28Ch
(Note 14-2)
Output GPIO[140:176]
290h
(Note 14-2)
Output GPIO[200:236]
300h
(Note 14-2)
Input GPIO[000:036]
304h
(Note 14-2)
Input GPIO[040:076]
308h
(Note 14-2)
Input GPIO[100:127]
30Ch
(Note 14-2)
Input GPIO[140:176]
310h
(Note 14-2)
Input GPIO[200:236]
500h - 51Ch
GPIO000-GPIO007 Pin Control Register 2
520h - 53Ch
GPIO010-GPIO017 Pin Control Register 2
540h - 55Ch
GPIO020-GPIO027 Pin Control Register 2
560h - 578h
GPIO030-GPIO036 Pin Control Register 2
580h - 59Ch
GPIO040-GPIO047 Pin Control Register 2
5A0h - 5BCh
GPIO050-GPIO057 Pin Control Register 2
5C0h - 5DCh
GPIO060-GPIO067 Pin Control Register 2
5E0h - 5FCh
GPIO100-GPIO107 Pin Control Register 2
600h
GPIO110 Pin Control Register 2
604h - 623h
MCHP Reserved (Note 14-2)
624h - 63Ch
GPIO121-GPIO127 Pin Control Register 2
640h - 658h
GPIO130-GPIO136 Pin Control Register 2
660h - 67Ch
GPIO140-GPIO147 Pin Control Register 2
680h - 69Ch
GPIO150-GPIO157 Pin Control Register 2
6A0h - 6B4h
GPIO160-GPIO165 Pin Control Register 2
720h - 730h
738h
740h - 744h
Note 14-2
GPIO200-GPIO204 Pin Control Register 2
GPIO206 Pin Control Register 2
GPIO210-GPIO211 Pin Control Register 2
There is no Pin Control Register 2 for GPIO111-GPIO117 and GPIO120, which are PCI_PIO buffer
type pins. The drive strength and slew rate are not configurable on these pins.
DS00002022B-page 152
2016 Microchip Technology Inc.
CEC1302
14.8
Pin Control Registers
Two Pin Control Registers are implemented for each GPIO. The Pin Control Register format is described in Section
14.8.1, "Pin Control Register," on page 153. The Pin Control Register 2 format is described in Section 14.8.2, "Pin
Control Register 2," on page 156. Pin Control Register address offsets and defaults are defined in Table 14-5, “Pin
Control Registers,” on page 148.
14.8.1
PIN CONTROL REGISTER
Offset
See Note 14-3
Bits
Description
31:25 RESERVED
24 GPIO input from pad
Type
Default
Reset
Event
RES
-
-
R
Note 14-3
VCC1_R
ESET
RES
-
-
R/W
Note 14-3
VCC1_R
ESET
On reads, Bit [24] reflects the state of GPIO input from the pad
regardless of setting of Bit [10].
Note:
This bit is forced high when the selected power well is off
as selected by the Power Gating Signal bits. See bits[3:2].
23:17 RESERVED
16 Alternative GPIO data
If enabled by the Output GPIO Write Enable bit, the Alternative GPIO
data bit determines the level on the GPIO pin when the pin is configured for the GPIO output function.
On writes:
If enabled via the Output GPIO Write Enable
0: GPIO[x] out = ‘0’
1: GPIO[x] out = ‘1’
Note:
If disabled via the Output GPIO Write Enable then the
GPIO[x] out pin is unaffected by writing this bit.
On reads:
Bit [16] returns the last programmed value, not the value on the pin.
15:14 RESERVED
RES
-
-
13:12 Mux Control
The Mux Control field determines the active signal function for a pin.
R/W
Note 14-3
VCC1_R
ESET
R/W
Note 14-3
VCC1_R
ESET
00 = GPIO Function Selected
01 = Signal Function 1 Selected
10 = Signal Function 2 Selected
11 = Signal Function 3 Selected
11 Polarity
0 = Non-inverted
1 = Inverted
When the Polarity bit is set to ‘1’ and the Mux Control bits are greater
than ‘00,’ the selected signal function outputs are inverted and Interrupt Detection (int_det) sense defined in Table 14-8, "Edge Enable
and Interrupt Detection Bits Definition" is inverted. When the Mux
Control field selects the GPIO signal function (Mux = ‘00’), the Polarity bit does not effect the output. Regardless of the state of the Mux
Control field and the Polarity bit, the state of the pin is always
reported without inversion in the GPIO input register.
2016 Microchip Technology Inc.
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Offset
See Note 14-3
Bits
Description
10 Output GPIO Write Enable
Every GPIO has two mechanisms to set a GPIO data output: Output
GPIO Bit located in the GPIO Output Registers and the Alternative
GPIO data bit located in bit 16 of this register.
Reset
Event
Type
Default
R/W
Note 14-3
VCC1_R
ESET
R/W
Note 14-3
VCC1_R
ESET
R/W
Note 14-3
VCC1_R
ESET
R/W
Note 14-3
VCC1_R
ESET
R/W
Note 14-3
VCC1_R
ESET
This control bit determines the source of the GPIO output.
0 = Alternative GPIO data write enabled
When this bit is zero the Alternative GPIO data write is enabled and
the Output GPIO is disabled.
1 = Output GPIO enable
When this bit is one the Alternative GPIO data write is disabled and
the Output GPIO is enabled.
Note:
See description in Section 14.4, "Accessing GPIOs".
9 GPIO Direction
0 = Input
1 = Output
The GPIO Direction bit controls the buffer direction only when the
Mux Control field is ‘00’ selecting the pin signal function to be
GPIO. When the Mux Control field is greater than ‘00’ (i.e., a nonGPIO signal function is selected) the GPIO Direction bit has no affect
and the selected signal function logic directly controls the pin direction.
8 Output Buffer Type
0 = Push-Pull
1 = Open Drain
Note:
Unless explicitly stated otherwise, pins with (I/O/OD) or
(O/OD) in their buffer type column in the tables in are
compliant with the following Programmable OD/PP Multiplexing Design Rule: Each compliant pin has a programmable open drain/push-pull buffer controlled by the
Output Buffer Type bit in the associated Pin Control
Register. The state of this bit controls the mode of the
interface buffer for all selected functions, including the
GPIO function.
7 Edge Enable (edge_en)
0 = Edge detection disabled
1 = Edge detection enabled
Note:
See Table 14-8, "Edge Enable and Interrupt Detection
Bits Definition".
6:4 Interrupt Detection (int_det)
The interrupt detection bits determine the event that generates a
GPIO_Event.
Note:
DS00002022B-page 154
See Table 14-8, "Edge Enable and Interrupt Detection
Bits Definition".
2016 Microchip Technology Inc.
CEC1302
See Note 14-3
Offset
Bits
Description
3:2 Power Gating Signals
Reset
Event
Type
Default
R/W
Note 14-3
VCC1_R
ESET
R/W
Note 14-3
VCC1_R
ESET
The Power Gating Signals provide the GPIO pin Power Emulation
options. The pin will be tristated when the selected power well is off
(i.e., gated) as indicated.
The Emulated Power Well column defined in the Multiplexing Tables
in Section 1.5, "Pin Multiplexing," on page 16 indicates the emulation
options supported for each signal. The Signal Power Well column
defines the actual buffer power supply per function.
00 = VCC1 Power Rail
The output buffer is tristated when VCC1GD = 0.
01 = VCC2 Power Rail
The output buffer is tristated when PWRGD = 0.
10 = Reserved
11 = Reserved
1:0 PU/PD (PU_PD)
These bits are used to enable an internal pull-up.
00 = None
01 = Pull Up Enabled
10 = Pull Down Enabled (Note 14-4)
11 = None
Note 14-3
See Section 14.7, "Pin Multiplexing Control," on page 151 for the offset and default values for each
GPIO Pin Control Register.
Note 14-4
The Pin Control Registers for GPIO111-GPIO117 and GPIO120, which are PCI_PIO buffer type pins,
do not have an internal pull-down. This configuration option has no effect on the pin.
TABLE 14-8:
EDGE ENABLE AND INTERRUPT DETECTION BITS DEFINITION
Edge
Enable
Interrupt Detection Bits
Selected Function
D7
D6
D5
D4
0
0
0
0
Low Level Sensitive
0
0
0
1
High Level Sensitive
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
Interrupt events are disabled
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
1
0
1
Rising Edge Triggered
1
1
1
0
Falling Edge Triggered
1
1
1
1
Either edge triggered
Note:
Only edge triggered interrupts can wake up the main ring oscillator. The GPIO must be enabled for edgetriggered interrupts and the GPIO interrupt must be enabled in the interrupt aggregator in order to wake up
the ring when the ring is shut down.
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CEC1302
APPLICATION NOTE: All GPIO interrupt detection configurations default to '0000', which is low level interrupt.
Having interrupt detection enabled will un-gated the clock to the GPIO module whenever the
interrupt is active, which increases power consumption. Interrupt detection should be
disabled when not required to save power; this is especially true for pin interfaces.
14.8.2
PIN CONTROL REGISTER 2
Offset
See Note 14-3
Bits
Description
31:6 RESERVED
Type
Default
Reset
Event
RES
-
-
5:4 Drive Strength
These bits are used to select the drive strength on the pin.
00 = 2mA
01 = 4mA
10 = 8mA
11 = 12mA
R/W
Note 1: on
page 151
VCC1_R
ESET
3:1 RESERVED
RES
-
-
R/W
0
VCC1_R
ESET
0 Slew Rate
This bit is used to select the slew rate on the pin.
0 = slow (half frequency)
1 = fast
14.8.3
GPIO OUTPUT REGISTERS
If enabled by the Output GPIO Write Enable bit, the GPIO Output bits determine the level on the GPIO pin when the pin
is configured for the GPIO output function.
On writes:
If enabled via the Output GPIO Write Enable
0: GPIO[x] out = ‘0’
1: GPIO[x] out = ‘1’
If disabled via the Output GPIO Write Enable then the GPIO[x] out pin is unaffected by writing this bit.
On reads:
Bit [16] returns the last programmed value, not the value on the pin.
Note:
Bits associated with GPIOs that are not implemented are shown as Reserved.
14.8.3.1
Output GPIO[000:036]
Offset
280h (Note 14-2)
Type
Default
Reset
Event
RES
-
-
30:24 GPIO[036:030] Output
R/W
00h
VCC1_R
ESET
23:16 GPIO[027:020] Output
R/W
00h
VCC1_R
ESET
15:8 GPIO[017:010] Output
R/W
00h
VCC1_R
ESET
7:0 GPIO[007:000] Output
R/W
00h
VCC1_R
ESET
Bits
Description
31 RESERVED
DS00002022B-page 156
2016 Microchip Technology Inc.
CEC1302
14.8.3.2
Output GPIO[040:076]
Offset
284h (Note 14-2)
Bits
Description
Type
Default
Reset
Event
31:24 RESERVED
RES
-
-
23:16 GPIO[067:060] Output
R/W
00h
VCC1_R
ESET
15:8 GPIO[057:050] Output
R/W
00h
VCC1_R
ESET
7:0 GPIO[047:040] Output
R/W
00h
VCC1_R
ESET
Type
Default
Reset
Event
RES
-
-
30:24 GPIO[136:130] Output
R/W
00h
VCC1_R
ESET
23:16 GPIO[127:120] Output
R/W
00h
VCC1_R
ESET
15:8 GPIO[117:110] Output
R/W
00h
VCC1_R
ESET
7:0 GPIO[107:100] Output
R/W
00h
VCC1_R
ESET
Type
Default
Reset
Event
31:22 RESERVED
RES
-
-
21:16 GPIO[165:160] Output
R/W
00h
VCC1_R
ESET
15:8 GPIO[157:150] Output
R/W
00h
VCC1_R
ESET
7:0 GPIO[147:140] Output
R/W
00h
VCC1_R
ESET
14.8.3.3
Output GPIO[100:127]
Offset
288h (Note 14-2)
Bits
Description
31 RESERVED
14.8.3.4
Offset
Output GPIO[140:176]
28Ch (Note 14-2)
Bits
Description
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CEC1302
14.8.3.5
Output GPIO[200:236]
Offset
290h (Note 14-2)
Bits
Description
Type
Default
Reset
Event
31 RESERVED
RES
-
-
30:24 RESERVED
RES
-
-
23:12 RESERVED
RES
-
-
11:10 MCHP Reserved
R/W
00h
VCC1_R
ESET
R/W
00h
VCC1_R
ESET
9:8 GPIO[211:210] Output
7 RESERVED
RES
-
-
6 GPIO206 Output
R/W
00h
VCC1_R
ESET
5 RESERVED
RES
-
-
R/W
00h
VCC1_R
ESET
4:0 GPIO[204:200] Output
14.8.4
GPIO INPUT REGISTERS
The GPIO Input Registers can always be used to read the state of a pin, even when the pin is in an output mode and/or
when a signal function other than the GPIO signal function is selected; i.e., the Pin Control Register Mux Control bits
are not equal to ‘00.’
The MSbit of the Input GPIO registers have been implemented as a read/write scratch pad bit to support processor specific instructions.
Note:
Bits associated with GPIOs that are not implemented are shown as Reserved.
14.8.4.1
Input GPIO[000:036]
Offset
300h (Note 14-2)
Bits
Description
Reset
Event
Type
Default
R/W
0b
VCC1_R
ESET
30:24 GPIO[036:030] Input
R
00h
VCC1_R
ESET
23:16 GPIO[027:020] Input
R
00h
VCC1_R
ESET
15:8 GPIO[017:010] Input
R
00h
VCC1_R
ESET
7:0 GPIO[007:000] Input
R
00h
VCC1_R
ESET
31 Scratchpad Bit
DS00002022B-page 158
2016 Microchip Technology Inc.
CEC1302
14.8.4.2
Input GPIO[040:076]
Offset
304h (Note 14-2)
Bits
Description
31 Scratchpad Bit
Type
Default
R/W
0b
Reset
Event
VCC1_R
ESET
30:24 RESERVED
R
-
-
23:16 GPIO[067:060] Input
R
00h
VCC1_R
ESET
15:8 GPIO[057:050] Input
R
00h
VCC1_R
ESET
7:0 GPIO[047:040] Input
R
00h
VCC1_R
ESET
Type
Default
R/W
0b
VCC1_R
ESET
30:24 GPIO[136:130] Input
R
00h
VCC1_R
ESET
23:16 GPIO[127:120] Input
R
00h
VCC1_R
ESET
15:8 GPIO[117:110] Input
R
00h
VCC1_R
ESET
7:0 GPIO[107:100] Input
R
00h
VCC1_R
ESET
Type
Default
R/W
0b
VCC1_R
ESET
30:22 Reserved
R
00h
VCC1_R
ESET
21:16 GPIO[165:160] Input
R
00h
VCC1_R
ESET
15:8 GPIO[157:150] Input
R
00h
VCC1_R
ESET
7:0 GPIO[147:140] Input
R
00h
VCC1_R
ESET
14.8.4.3
Input GPIO[100:127]
Offset
308h (Note 14-2)
Bits
Description
31 Scratchpad Bit
14.8.4.4
Reset
Event
Input GPIO[140:176]
Offset
30Ch(Note 14-2)
Bits
Description
31 Scratchpad Bit
2016 Microchip Technology Inc.
Reset
Event
DS00002022B-page 159
CEC1302
14.8.4.5
Input GPIO[200:236]
Offset
310h(Note 14-2)
Bits
Description
Reset
Event
Type
Default
R/W
0b
VCC1_R
ESET
30:24 Scratchpad Bits
R/W
00h
VCC1_R
ESET
23:16 Scratchpad Bits
R/W
00h
VCC1_R
ESET
15:12 RESERVED
RES
-
-
11:10 MCHP Reserved
R/W
00h
VCC1_R
ESET
R/W
00h
VCC1_R
ESET
7 RESERVED
RES
-
-
6 GPIO206 Input
R/W
00h
VCC1_R
ESET
5 RESERVED
RES
-
-
R/W
00h
VCC1_R
ESET
31 Scratchpad Bit
9:8 GPIO[211:210] Input
4:0 GPIO[204:200] Input
DS00002022B-page 160
2016 Microchip Technology Inc.
CEC1302
15.0
INTERNAL DMA CONTROLLER
15.1
Introduction
The Internal DMA Controller transfers data to/from the source from/to the destination. The firmware is responsible for
setting up each channel. Afterwards either the firmware or the hardware may perform the flow control. The hardware
flow control exists entirely inside the source device. Each transfer may be 1, 2, or 4 bytes in size, so long as the device
supports a transfer of that size. Every device must be on the internal 32-bit address space.
15.2
References
No references have been cited for this chapter
15.3
Terminology
TABLE 15-1:
TERMINOLOGY
Term
Definition
DMA Transfer
This is a complete DMA Transfer which is done after the Master Device
terminates the transfer, the Firmware Aborts the transfer or the DMA
reaches its transfer limit.
A DMA Transfer may consist of one or more data packets.
Data Packet
Each data packet may be composed of 1, 2, or 4 bytes. The size of the data
packet is limited by the max size supported by both the source and the destination. Both source and destination will transfer the same number of bytes
per packet.
Channel
The Channel is responsible for end-to-end (source-to-destination) Data
Packet delivery.
Device
A Device may refer to a Master or Slave connected to the DMA Channel.
Each DMA Channel may be assigned one or more devices.
Master Device
This is the master of the DMA, which determines when it is active.
The Firmware is the master while operating in Firmware Flow Control.
The Hardware is the master while operating in Hardware Flow Control.
The Master Device in Hardware Mode is selected by DMA Channel Control:Hardware Flow Control Device. It is the index of the Flow Control
Port.
Slave Device
The Slave Device is defined as the device associated with the targeted
Memory Address.
Source
The DMA Controller moves data from the Source to the Destination. The
Source provides the data. The Source may be either the Master or Slave
Controller.
Destination
The DMA Controller moves data from the Source to the Destination. The
Destination receives the data. The Destination may be either the Master or
Slave Controller.
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15.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 15-1:
INTERNAL DMA CONTROLLER I/O DIAGRAM
Internal DMA Controller
Host Interface
DMA Interface
Power, Clocks and Reset
Interrupts
15.4.1
SIGNAL DESCRIPTION
This block doesn’t have any external signals that may be routed to the pin interface. This DMA Controller is intended to
be used internally to transfer large amounts of data without the embedded controller being actively involved in the transfer.
15.4.2
HOST INTERFACE
The registers defined for the Internal DMA Controller are accessible by the various hosts as indicated in Section 15.9,
"EC-Only Registers".
15.4.3
DMA INTERFACE
Each DMA Master Device that may engage in a DMA transfer must have a compliant DMA interface. The following table
lists the DMA Devices in the CEC1302.
TABLE 15-2:
DMA CONTROLLER DEVICE SELECTION
Device Name
Device Number
(Note 15-1)
Controller Source
SMBus 0 Controller
0
Slave
1
Master
SMBus 1 Controller
2
Slave
3
Master
SMBus 2 Controller
4
Slave
5
Master
SMBus 3 Controller
6
Slave
7
Master
SPI 0 Controller
8
Transmit
9
Receive
SPI 1 Controller
10
Transmit
Note 15-1
11
Receive
The Device Number is programmed into field HARDWARE_FLOW_CONTROL_DEVICE of the DMA
Channel N Control register.
DS00002022B-page 162
2016 Microchip Technology Inc.
CEC1302
TABLE 15-3:
DMA CONTROLLER MASTER DEVICES SIGNAL LIST
Device Name
SMBus 0 Controller
Dev
Num
(15.5)
Device Signal Name
Direction
0
SMB_SDMA_Req
INPUT
DMA request control from SMBus Slave
channel.
SMB_SDMA_Term
INPUT
DMA termination control from SMBus
Slave channel.
SMB_SDMA_Done
OUTPUT
DMA termination control from DMA Controller to Slave channel.
SMB_MDMA_Req
INPUT
DMA request control from SMBus Master
channel.
SMB_MDMA_Term
INPUT
DMA termination control from SMBus Master channel.
SMB_MDMA_Done
OUTPUT
DMA termination control from DMA Controller to Master channel.
SMB_SDMA_Req
INPUT
DMA request control from SMBus Slave
channel.
SMB_SDMA_Term
INPUT
DMA termination control from SMBus
Slave channel.
SMB_SDMA_Done
OUTPUT
DMA termination control from DMA Controller to Slave channel.
SMB_MDMA_Req
INPUT
DMA request control from SMBus Master
channel.
SMB_MDMA_Term
INPUT
DMA termination control from SMBus Master channel.
SMB_MDMA_Done
OUTPUT
DMA termination control from DMA Controller to Master channel.
SMB_SDMA_Req
INPUT
DMA request control from SMBus Slave
channel.
SMB_SDMA_Term
INPUT
DMA termination control from SMBus
Slave channel.
SMB_SDMA_Done
OUTPUT
DMA termination control from DMA Controller to Slave channel.
SMB_MDMA_Req
INPUT
DMA request control from SMBus Master
channel.
SMB_MDMA_Term
INPUT
DMA termination control from SMBus Master channel.
SMB_MDMA_Done
OUTPUT
1
SMBus 1 Controller
2
3
SMBus 2 Controller
4
5
2016 Microchip Technology Inc.
Description
DMA termination control from DMA Controller to Master channel.
DS00002022B-page 163
CEC1302
TABLE 15-3:
DMA CONTROLLER MASTER DEVICES SIGNAL LIST (CONTINUED)
Device Name
SMBus 3 Controller
Dev
Num
(15.5)
Device Signal Name
Direction
6
SMB_SDMA_Req
INPUT
DMA request control from SMBus Slave
channel.
SMB_SDMA_Term
INPUT
DMA termination control from SMBus
Slave channel.
SMB_SDMA_Done
OUTPUT
DMA termination control from DMA Controller to Slave channel.
SMB_MDMA_Req
INPUT
DMA request control from SMBus Master
channel.
SMB_MDMA_Term
INPUT
DMA termination control from SMBus Master channel.
SMB_MDMA_Done
OUTPUT
SPI_SDMA_Req
INPUT
DMA request control from SPI TX channel.
SPI_SDMA_Term
INPUT
DMA termination control from SPI TX
channel. Not supported.
SPI_SDMA_Done
OUTPUT
SPI_MDMA_Req
INPUT
DMA request control from SPI RX channel.
SPI_MDMA_Term
INPUT
DMA termination control from SPI RX
channel. Not supported.
SPI_MDMA_Done
OUTPUT
SPI_SDMA_Req
INPUT
DMA request control from SPI TX channel.
SPI_SDMA_Term
INPUT
DMA termination control from SPI TX
channel. Not supported.
SPI_SDMA_Done
OUTPUT
SPI_MDMA_Req
INPUT
DMA request control from SPI RX channel.
SPI_MDMA_Term
INPUT
DMA termination control from SPI RX
channel. Not supported.
SPI_MDMA_Done
OUTPUT
7
SPI 0 Controller
8
9
SPI 1 Controller
10
11
15.5
Description
DMA termination control from DMA Controller to Master channel.
DMA termination control from DMA Controller to TX Channel. Not supported.
DMA termination control from DMA Controller to RX channel. Not supported.
DMA termination control from DMA Controller to TX Channel. Not supported.
DMA termination control from DMA Controller to RX channel. Not supported.
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
15.5.1
POWER DOMAINS
TABLE 15-4:
POWER SOURCES
Name
VCC1
15.5.2
Description
This power well sources the registers and logic in this block.
CLOCK INPUTS
TABLE 15-5:
CLOCK INPUTS
Name
48 MHz Ring Oscillator
DS00002022B-page 164
Description
This clock signal drives selected logic (e.g., counters).
2016 Microchip Technology Inc.
CEC1302
15.5.3
RESETS
TABLE 15-6:
RESET SIGNALS
Name
VCC1_RESET
RESET
15.6
Description
This reset signal resets all of the registers and logic in this block.
This reset is generated if either the VCC1_RESET is asserted or the
SOFT_RESET is asserted.
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 15-7:
INTERRUPTS
Source
15.7
Description
DMA0
Direct Memory Access Channel 0
This signal is generated by the STATUS_DONE bit.
DMA1
Direct Memory Access Channel 1
This signal is generated by the STATUS_DONE bit.
DMA2
Direct Memory Access Channel 2
This signal is generated by the STATUS_DONE bit.
DMA3
Direct Memory Access Channel 3
This signal is generated by the STATUS_DONE bit.
DMA4
Direct Memory Access Channel 4
This signal is generated by the STATUS_DONE bit.
DMA5
Direct Memory Access Channel 5
This signal is generated by the STATUS_DONE bit.
DMA6
Direct Memory Access Channel 6
This signal is generated by the STATUS_DONE bit.
DMA7
Direct Memory Access Channel 7
This signal is generated by the STATUS_DONE bit.
DMA8
Direct Memory Access Channel 8
This signal is generated by the STATUS_DONE bit.
DMA9
Direct Memory Access Channel 9
This signal is generated by the STATUS_DONE bit.
DMA10
Direct Memory Access Channel 10
This signal is generated by the STATUS_DONE bit.
DMA11
Direct Memory Access Channel 11
This signal is generated by the STATUS_DONE bit.
Low Power Modes
The Internal DMA Controller may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
When the block is commanded to go to sleep it will place the DMA block into sleep mode only after all transactions on
the DMA have been completed. For Firmware Flow Controlled transactions, the DMA will wait until it hits its terminal
count and clears the Go control bit. For Hardware Flow Control, the DMA will go to sleep after either the terminal count
is hit, or the Master device flags the terminate signal.
15.8
Description
The CEC1302 features a 12 channel DMA controller. The DMA controller can autonomously move data from/to any
DMA capable master device to/from any populated memory location. This mechanism allows hardware IP blocks to
transfer large amounts of data into or out of memory without EC intervention.
The DMA has the following characteristics:
• Data is only moved 1 Data Packet at a time
• Data only moves between devices on the accessible via the internal 32-bit address space
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• The DMA Controller has 12 DMA Channels
• Each DMA Channel may be configured to communicate with any DMA capable device on the 32-bit internal
address space. Each device has been assigned a device number. See Section 15.4.3, "DMA Interface," on
page 162.
The controller will accesses SRAM buffers only with incrementing addresses (that is, it cannot start at the top of a buffer,
nor does it handle circular buffers automatically). The controller does not handle chaining (that is, automatically starting
a new DMA transfer when one finishes).
15.8.1
CONFIGURATION
The DMA Controller is enabled via the ACTIVATE bit in DMA Main Control register.
Each DMA Channel must also be individually enabled via the CHANNEL_ACTIVATE bit in the DMA Channel N Activate
to be operational.
Before starting a DMA transaction on a DMA Channel the host must assign a DMA Master to the channel via HARDWARE_FLOW_CONTROL_DEVICE. The host must not configure two different channels to the same DMA Master at
the same time.
Data will be transfered between the DMA Master, starting at the programmed DEVICE_ADDRESS, and the targeted
memory location, starting at the MEMORY_START_ADDRESS. The address for either the DMA Master or the targeted
memory location may remain static or it may increment. To enable the DMA Master to increment its address set the
INCREMENT_DEVICE_ADDRESS bit. To enable the targeted memory location to increment its addresses set the
INCREMENT_MEMORY_ADDRESS. The DMA transfer will continue as long as the target memory address being
accessed is less than the MEMORY_END_ADDRESS. If the DMA Controller detects that the memory location it is
attempting to access on the Target is equal to the MEMORY_END_ADDRESS it will notify the DMA Master that the
transaction is done. Otherwise the Data will be transferred in packets. The size of the packet is determined by the
TRANSFER_SIZE.
15.8.2
OPERATION
The DMA Controller is designed to move data from one memory location to another.
15.8.2.1
Establishing a Connection
A DMA Master will initiate a DMA Transaction by requesting access to a channel. The DMA arbiter, which evaluates
each channel request using a basic round robin algorithm, will grant access to the DMA master. Once granted, the channel will hold the grant until it decides to release it, by notifying the DMA Controller that it is done.
Note:
15.8.2.2
If Firmware wants to prevent any other channels from being granted while it is active it can set the
LOCK_CHANNEL bit.
Initiating a Transfer
Once a connection is established the DMA Master will issue a DMA request to start a DMA transfer. If Firmware wants
to have a transfer request serviced it must set the RUN bit to have its transfer requests serviced.
Firmware can initiate a transaction by setting the TRANSFER_GO bit. The DMA transfer will remain active until either
the Master issues a Terminate or the DMA Controller signals that the transfer is DONE. Firmware may terminate a transaction by setting the TRANSFER_ABORT bit.
Note:
Before initiating a DMA transaction via firmware the hardware flow control mus be disabled via the DISABLE_HARDWARE_FLOW_CONTROL bit.
Data may be moved from the DMA Master to the targeted Memory address or from the targeted Memory Address to the
DMA Master. The direction of the transfer is determined by the TRANSFER_DIRECTION bit.
Once a transaction has been initiated firmware can use the STATUS_DONE bit to determine when the transaction is
completed. This status bit is routed to the interrupt interface. In the same register there are additional status bits that
indicate if the transaction completed successfully or with errors. This bits are OR’d together with the STATUS_DONE
bit to generate the interrupt event. Each status be may be individually enabled/disabled from generating this event.
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CEC1302
15.9
EC-Only Registers
The DMA Controller consists of a Main Block and a number of Channels. Table 15-9, "Main EC-Only Register Summary"
lists the registers in the Main Block and Table 15-10, "Channel EC-Only Register Summary" lists the registers in each
channel. The addresses of each register listed in these tables are defined as a relative offset to the “Base Address”
defined in the EC-Only Register Base Address Table. The Base Address for the Main Block and each Channel is defined
in the table:
TABLE 15-8:
EC-ONLY REGISTER BASE ADDRESS TABLE
Instance Name
Channel
Number
Host
Address Space
Base Address
DMA Controller
Main Block
EC
32-bit internal
address space
4000_2400h
DMA Controller
0
EC
32-bit internal
address space
4000_2410h
DMA Controller
1
EC
32-bit internal
address space
4000_2430h
DMA Controller
2
EC
32-bit internal
address space
4000_2450h
DMA Controller
3
EC
32-bit internal
address space
4000_2470h
DMA Controller
4
EC
32-bit internal
address space
4000_2490h
DMA Controller
5
EC
32-bit internal
address space
4000_24B0h
DMA Controller
6
EC
32-bit internal
address space
4000_24D0h
DMA Controller
7
EC
32-bit internal
address space
4000_24F0h
DMA Controller
8
EC
32-bit internal
address space
4000_2510h
DMA Controller
9
EC
32-bit internal
address space
4000_2530h
DMA Controller
10
EC
32-bit internal
address space
4000_2550h
DMA Controller
11
EC
32-bit internal
4000_2570h
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 15-9:
Offset
MAIN EC-ONLY REGISTER SUMMARY
REGISTER NAME (Mnemonic)
00h
DMA Main Control
04h
DMA Data Packet
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15.9.1
DMA MAIN CONTROL
00h
Offset
Bits
Description
7:2 Reserved
1 SOFT_RESET
Soft reset the entire module.
Type
Default
Reset
Event
R
-
-
W
0b
-
R/WS
0b
RESET
Type
Default
Reset
Event
R
0000h
-
This bit is self-clearing.
0 ACTIVATE
Enable the blocks operation.
1=Enable block. Each individual channel must be enabled separately.
0=Disable all channels.
15.9.2
DMA DATA PACKET
04h
Offset
Bits
Description
31:0 DATA_PACKET
Debug register that has the data that is stored in the Data Packet.
This data is read data from the currently active transfer source.
TABLE 15-10: CHANNEL EC-ONLY REGISTER SUMMARY
Register Name (Mnemonic)
(Note 15-2)
Offset
00h
DMA Channel N Activate
04h
DMA Channel N Memory Start Address
08h
DMA Channel N Memory End Address
0Ch
DMA Channel N Device Address
10h
DMA Channel N Control
14h
DMA Channel N Interrupt Status
18h
Note 15-2
15.9.3
DMA Channel N Interrupt Enable
The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel implemented will
have these registers to determine that channel’s operation.
DMA CHANNEL N ACTIVATE
Offset
00h
Bits
Description
7:1 Reserved
0 CHANNEL_ACTIVATE
Enable this channel for operation.
The DMA Main Control:Activate must also be enabled for this channel to be operational.
DS00002022B-page 168
Type
Default
Reset
Event
R
-
-
R/W
0h
RESET
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CEC1302
15.9.4
DMA CHANNEL N MEMORY START ADDRESS
Offset
04h
Bits
Description
31:0 MEMORY_START_ADDRESS
This is the starting address for the Memory device.
Type
Default
Reset
Event
R/W
0000h
RESET
Type
Default
Reset
Event
R/W
0000h
RESET
This field is updated by Hardware after every packet transfer by the
size of the transfer, as defined by DMA Channel Control:Channel
Transfer Size while the DMA Channel Control:Increment Memory
Address is Enabled.
The Memory device is defined as the device that is the slave device
in the transfer.
ex. With Hardware Flow Control, the Memory device is the device
that is not connected to the Hardware Flow Controlling device.
Note:
15.9.5
This field is only as large as the maximum allowed AHB
Address Size in the system. If the HADDR size is 24 Bits,
then Bits [31:24] will be RESERVED.
DMA CHANNEL N MEMORY END ADDRESS
Offset
08h
Bits
Description
31:0 MEMORY_END_ADDRESS
This is the ending address for the Memory device.
This will define the limit of the transfer, so long as DMA Channel
Control:Increment Memory Address is Enabled. When the Memory
Start Address is equal to this value, the DMA will terminate the transfer and flag the status DMA Channel Interrupt:Status Done.
Note:
This field is only as large as the maximum allowed AHB
Address Size in the system. If the HADDR size is 24 Bits,
then Bits [31:24] will be RESERVED.
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15.9.6
DMA CHANNEL N DEVICE ADDRESS
Offset
0Ch
Type
Default
Reset
Event
R/W
0000h
RESET
Type
Default
Reset
Event
R
-
-
25 TRANSFER_ABORT
This is used to abort the current transfer on this DMA Channel. The
aborted transfer will be forced to terminate immediately.
R/W
0h
RESET
24 TRANSFER_GO
This is used for the Firmware Flow Control DMA transfer.
R/W
0h
RESET
Bits
Description
31:0 DEVICE_ADDRESS
This is the Master Device address.
This is used as the address that will access the Device on the DMA.
The Device is defined as the Master of the DMA transfer; as in the
device that is controlling the Hardware Flow Control.
This field is updated by Hardware after every Data Packet transfer
by the size of the transfer, as defined by DMA Channel Control:Transfer Size while the DMA Channel Control:Increment Device
Address is Enabled.
Note:
15.9.7
This field is only as large as the maximum allowed AHB
Address Size in the system. If the HADDR size is 24 Bits,
then Bits [31:24] will be RESERVED.
DMA CHANNEL N CONTROL
Offset
10h
Bits
Description
31:26 Reserved
This is used to start a transfer under the Firmware Flow Control.
Do not use this in conjunction with the Hardware Flow Control;
DMA Channel Control:Disable Hardware Flow Control must be
set in order for this field to function correctly.
23 Reserved
22:20 TRANSFER_SIZE
This is the transfer size in Bytes of each Data Packet transfer.
Note:
-
-
0h
RESET
RW
0h
RESET
The transfer size must be a legal transfer size. Valid
sizes are 1, 2 and 4 Bytes.
19 DISABLE_HARDWARE_FLOW_CONTROL
This will Disable the Hardware Flow Control. When disabled, any
DMA Master device attempting to communicate to the DMA over the
DMA Flow Control Interface (Ports: dma_req, dma_term, and
dma_done) will be ignored.
This should be set before using the DMA channel in Firmware Flow
Control mode.
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R
R/W
2016 Microchip Technology Inc.
CEC1302
Offset
10h
Bits
Description
18 LOCK_CHANNEL
This is used to lock the arbitration of the Channel Arbiter on this
channel once this channel is granted.
Once this is locked, it will remain on the arbiter until it has completed
it transfer (either the Transfer Aborted, Transfer Done or Transfer
Terminated conditions).
Note:
Type
Default
Reset
Event
RW
0h
RESET
RW
0h
RESET
RW
0h
RESET
RW
0h
RESET
RW
0h
RESET
This setting may starve other channels if the locked channel takes an excessive period of time to complete.
17 INCREMENT_DEVICE_ADDRESS
This will enable an auto-increment to the DMA Channel Device
Address.
1: Increment the DMA Channel Device Address by DMA Channel
Control:Transfer Size after every Data Packet transfer
0: Do nothing
16 INCREMENT_MEMORY_ADDRESS
This will enable an auto-increment to the DMA Channel Memory
Address.
1=Increment the DMA Channel Memory Address by DMA Channel
Control:Transfer Size after every Data Packet transfer
0=Do nothing
Note:
If this is not set, the DMA will never terminate the transfer
on its own. It will have to be terminated through the Hardware Flow Control or through a DMA Channel Control:Transfer Abort.
15:9 HARDWARE_FLOW_CONTROL_DEVICE
This is the device that is connected to this channel as its Hardware
Flow Control master.
The Flow Control Interface is a bus with each master concatenated
onto it. This selects which bus index of the concatenated Flow Control Interface bus is targeted towards this channel.
The Flow Control Interface Port list is dma_req, dma_term, and
dma_done.
8 TRANSFER_DIRECTION
This determines the direction of the DMA Transfer.
1=Data Packet Read from Memory Start Address followed by Data
Packet Write to Device Address
0=Data Packet Read from Device Address followed by Data Packet
Write to Memory Start Address
7:6 Reserved
5 BUSY
This is a status signal.
R
-
-
RO
0h
RESET
1=The DMA Channel is busy (FSM is not IDLE)
0=The DMA Channel is not busy (FSM is IDLE)
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CEC1302
Offset
10h
Bits
Description
4:3 STATUS
This is a status signal. The status decode is listed in priority order
with the highest priority first.
Type
Default
Reset
Event
R
0h
RESET
RO
0h
RESET
RO
0h
RESET
RW
0h
RESET
3: Error detected by the DMA
2: The DMA Channel is externally done, in that the Device has terminated the transfer over the Hardware Flow Control through the
Port dma_term
1: The DMA Channel is locally done, in that Memory Start Address
equals Memory End Address
0: DMA Channel Control:Run is Disabled (0x0)
Note:
This functionality has been replaced by the Interrupt field,
and as such should never be used.
The field will not flag back appropriately timed status, and
if used may cause the firmware to become out-of-sync
with the hardware.
This field has multiple non-exclusive statuses, but may
only display a single status. As such, multiple statuses
may be TRUE, but this will appear as though only a single
status has been triggered.
2 DONE
This is a status signal. It is only valid while DMA Channel Control:Run is Enabled. This is the inverse of the DMA Channel Control:Busy field, except this is qualified with the DMA Channel
Control:Run field.
1=Channel is done
0=Channel is not done or it is OFF
1 REQUEST
This is a status field.
1= There is a transfer request from the Master Device
0= There is no transfer request from the Master Device
0 RUN
This is a control field.
Note:
This bit only applies to Hardware Flow Control mode.
1= This channel is enabled and will service transfer requests
0=This channel is disabled. All transfer requests are ignored
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CEC1302
15.9.8
DMA CHANNEL N INTERRUPT STATUS
Offset
14h
Bits
Description
7:3 Reserved
2 STATUS_DONE
This is an interrupt source register.
This flags when the DMA Channel has completed a transfer successfully on its side.
A completed transfer is defined as when the DMA Channel reaches
its limit; Memory Start Address equals Memory End Address.
A completion due to a Hardware Flow Control Terminate will not
flag this interrupt.
Type
Default
Reset
Event
R
-
-
R/WC
0h
RESET
0h
RESET
0h
RESET
1=Memory Start Address equals Memory End Address
0=Memory Start Address does not equal Memory End Address
1 STATUS_FLOW_CONTROL
This is an interrupt source register.
This flags when the DMA Channel has encountered a Hardware
Flow Control Request after the DMA Channel has completed the
transfer. This means the Master Device is attempting to overflow the
DMA.
1=Hardware Flow Control is requesting after the transfer has completed
0=No Hardware Flow Control event
0 STATUS_BUS_ERROR
This is an interrupt source register.
This flags when there is an Error detected over the internal 32-bit
Bus.
R/WC
1: Error detected.
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15.9.9
DMA CHANNEL N INTERRUPT ENABLE
Offset
18h
Bits
Description
7:3 Reserved
2 STATUS_ENABLE_DONE
This is an interrupt enable for DMA Channel Interrupt:Status
Done.
Type
Default
Reset
Event
R
-
-
R/W
0h
RESET
R/W
0h
RESET
R/W
0h
RESET
1=Enable Interrupt
0=Disable Interrupt
1 STATUS_ENABLE_FLOW_CONTROL_ERROR
This is an interrupt enable for DMA Channel Interrupt:Status Flow
Control Error.
1=Enable Interrupt
0=Disable Interrupt
0 STATUS_ENABLE_BUS_ERROR
This is an interrupt enable for DMA Channel Interrupt:Status Bus
Error.
1=Enable Interrupt
0=Disable Interrupt
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CEC1302
16.0
I2C/SMBUS INTERFACE
16.1
Introduction
The CEC1302 I2C/SMBus Interface includes one instance of the I2C/SMBus controller core. This chapter describes
aspects of the I2C/SMBus Interface that are unique to the CEC1302 instantiations of this core; including, Power Domain,
Resets, Clocks, Interrupts, Registers and the Physical Interface. For a General Description, Features, Block Diagram,
Functional Description, Registers Interface and other core-specific details, see Ref [1] (note: in this chapter, italicized
text typically refers to SMBus controller core interface elements as described in Ref [1]).
16.2
1.
References
SMBus Controller Core Interface, Revision 3.4, Core-Level Architecture Specification, SMSC, 7/16/12
16.3
Terminology
There is no terminology defined for this chapter.
16.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface. In
addition, this block is equipped with
FIGURE 16-1:
I/O DIAGRAM OF BLOCK
Host Interface
I2C/SMBus Interface
DMA Interface
Signal Description
Power, Clocks and Reset
Interrupts
16.5
Signal Description
The Signal Description Table lists the signals that are typically routed to the pin interface.
TABLE 16-1:
Note:
SIGNAL DESCRIPTION TABLE
Name
Direction
Description
SMB_DAT0
Input/Output
SMBus Data Port 0
SMB_CLK0
Input/Output
SMBus Clock Port 0
SMB_DAT1
Input/Output
SMBus Data Port 1
SMB_CLK1
Input/Output
SMBus Clock Port 1
The SMB block signals that are shown in Table 16-1 are routed to the SMB pins as listed in Table 16-2.
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TABLE 16-2:
16.6
SIGNAL TO PIN NAME LOOKUP TABLE
Block Name
Pin Name
Description
SMBx_DATn
I2Cx_DATn
I2C/SMBus Controller x Port n Data
SMBx_CLKn
I2Cx_CLKn
I2C/SMBus Controller x Port n Clock
Host Interface
The registers defined for the I2C/SMBus Interface are accessible as indicated in Section 16.12, "SMBus Registers".
16.7
DMA Interface
This block is designed to communicate with the Internal DMA Controller. This feature is defined in the SMBus Controller
Core Interface specification (See Ref [1]).
Note:
16.8
For a description of the Internal DMA Controller implemented in this design see Chapter 15.0, "Internal DMA
Controller".
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
16.8.1
POWER DOMAINS
TABLE 16-3:
POWER SOURCES
Name
VCC1
16.8.2
This power well sources the registers and logic in this block.
CLOCK INPUTS
TABLE 16-4:
CLOCK INPUTS
Name
Description
48 MHz Ring Oscillator
This is the clock signal drives the SMBus controller core. The core also
uses this clock to generate the SMB_CLK on the pin interface.
16MHz_Clk
16.8.3
Description
This is the clock signal is used for baud rate generation.
RESETS
TABLE 16-5:
RESET SIGNALS
Name
VCC1_RESET
16.9
Description
This reset signal resets all of the registers and logic in the SMBus
controller core.
Interrupts
TABLE 16-6:
EC INTERRUPTS
Source
SMB
Description
SMBus Activity Interrupt Event
16.10 Low Power Modes
The I2C/SMBus Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
16.11 Description
16.11.1
SMBUS CONTROLLER CORE
The CEC1302 I2C/SMBus Interface behavior is defined in the SMBus Controller Core Interface specification (See Ref
[1]).
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CEC1302
16.11.2
PHYSICAL INTERFACE
The I2C/SMBus Interface has two physical ports, selected by the PORT SEL [3:0] bits in the Configuration Register as
described in Ref [1].
Note 1: SMBus controller 0 uses port 0 and port 1. SMBus controllers 1-3 use port 0.
2: The buffer type for these pins must be configured as open-drain outputs in the GPIO Configuration registers
associated with the GPIO signals that share the ports.
16.12 SMBus Registers
The registers listed in the SMBus Core Register Summary table in the SMBus Controller Core Interface specification
(Ref [1]) are for a single instance of the SMBus Controller Core. The addresses of each register listed in this table are
defined as a relative offset to the host “Base Address” defined in the following table:
TABLE 16-7:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address (Note 16-1)
SMBus Controller
0
EC
32-bit internal
address space
4000_1800h
SMBus Controller
1
EC
32-bit internal
address space
4000_AC00h
SMBus Controller
2
EC
32-bit internal
address space
4000_B000h
SMBus Controller
3
EC
Note 16-1
32-bit internal
4000_B400h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
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17.0
TACH
17.1
Introduction
This block monitors TACH output signals (or locked rotor signals) from various types of fans, and determines their
speed.
17.2
References
No references have been cited for this feature.
17.3
Terminology
There is no terminology defined for this section.
17.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 17-1:
I/O DIAGRAM OF BLOCK
TACH
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
17.5
Signal Description
TABLE 17-1:
17.6
SIGNAL DESCRIPTION TABLE
Name
Direction
TACH INPUT
Input
Description
Tachometer signal from TACHx Pin.
Host Interface
The registers defined for the TACH are accessible by the various hosts as indicated in Section 17.11, "EC-Only Registers".
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CEC1302
17.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
17.7.1
POWER DOMAINS
Name
VCC1
17.7.2
Description
The logic and registers implemented in this block are powered by this
power well.
CLOCK INPUTS
Name
100kHz_Clk
17.7.3
Description
This is the clock input to the tachometer monitor logic. In Mode 1, the
TACH is measured in the number of these clocks.
RESETS
Name
VCC1_RESET
17.8
Description
This signal resets all the registers and logic in this block to their default
state.
Interrupts
This section defines the Interrupt Sources generated from this block.
Source
TACH
17.9
Description
This internal signal is generated from the OR’d result of the status
events, as defined in the TACHx Status Register.
Low Power Modes
The TACH may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
17.10 Description
The TACH block monitors Tach output signals or locked rotor signals generated by various types of fans. These signals
can be used to determine the speed of the attached fan. This block is designed to monitor fans at fan speeds from 100
RPMs to 30,000 RPMs.
Typically, these are DC brushless fans that generate (with each revolution) a 50% duty cycle, two-period square wave,
as shown in Figure 17-2 below.
FIGURE 17-2:
FAN GENERATED 50%DUTY CYCLE WAVEFORM
one revolution
In typical systems, the fans are powered by the main power supply. Firmware may disable this block when it detects that
the main power rail has been turned off by either clearing the TACH_ENABLE bit or putting the block to sleep
via the supported Low Power Mode interface (see Low Power Modes).
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17.10.1
MODES OF OPERATION
The Tachometer block supports two modes of operation. The mode of operation is selected via the TACH_READING_MODE_SELECT bit.
17.10.1.1
Free Running Counter
In Mode 0, the Tachometer block uses the TACH input as the clock source for the internal TACH pulse counter (see
TACHX_COUNTER). The counter is incremented when it detects a rising edge on the TACH input. In this mode, the
firmware may periodically poll the TACHX_COUNTER field to determine the average speed over a period of time. The
firmware must store the previous reading and the current reading to compute the number of pulses detected over a
period of time. In this mode, the counter continuously increments until it reaches FFFFh. It then wraps back to 0000h
and continues counting. The firmware must ensure that the sample rate is greater than the time it takes for the counter
to wrap back to the starting point.
Note:
17.10.1.2
Tach interrupts should be disabled in Mode 0.
Mode 1 -- Number of Clock Pulses per Revolution
In Mode 1, the Tachometer block uses its 100kHz_Clk clock input to measure the programmable number of TACH
pulses. In this mode, the internal TACH pulse counter (TACHX_COUNTER) returns the value in number of 100kHz_Clk
pulses per programmed number of TACH_EDGES. For fans that generate two square waves per revolution, these bits
should be configured to five edges.
When the number of edges is detected, the counter is latched and the COUNT_READY_STATUS bit is asserted. If the
COUNT_READY_INT_EN bit is set a TACH interrupt event will be generated.
17.10.2
OUT-OF-LIMIT EVENTS
The TACH Block has a pair of limit registers that may be configured to generate an event if the Tach indicates that the
fan is operating too slow or too fast. If the exceeds one of the programmed limits, the TACHx High
Limit Register and the TACHx Low Limit Register, the bit TACH_OUT_OF_LIMIT_STATUS will be set. If the
TACH_OUT_OF_LIMIT_STATUS bit is set, the Tachometer block will generate an interrupt event.
17.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the TACH. The addresses of
each register listed in this table are defined as a relative offset to the host “Base Address” defined in the EC-Only Register Base Address Table.
TABLE 17-2:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
TACH
TACH
Instance
Number
Host
Address Space
Base Address
0
EC
32-bit internal
address space
4000_6000h
1
EC
32-bit internal
address space
4000_6010h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 17-3:
TACH REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
TACHx Control Register
04h
TACHx Status Register
08h
TACHx High Limit Register
0Ch
TACHx Low Limit Register
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CEC1302
17.11.1
TACHX CONTROL REGISTER
Offset
00h
Bits
Description
31:16 TACHX_COUNTER
This 16-bit field contains the latched value of the internal Tach pulse
counter, which may be configured by the Tach Reading Mode Select
field to operate as a free-running counter or to be gated by the Tach
input signal.
Reset
Event
Type
Default
R
00h
VCC1_
RESET
R/W
0b
VCC1_
RESET
R/W
0b
VCC1_
RESET
If the counter is free-running (Mode 0), the internal Tach counter
increments (if enabled) on transitions of the raw Tach input signal
and is latched into this field every time it is incremented. The act of
reading this field will not reset the counter, which rolls over to 0000h
after FFFFh. The firmware will compute the delta between the current
count reading and the previous count reading, to determine the number of pulses detected over a programmed period.
If the counter is gated by the Tach input and clocked by 100kHz_Clk
(Mode 1), the internal counter will be latched into the reading register
when the programmed number of edges is detected or when the
counter reaches FFFFh. The internal counter is reset to zero after it
is copied into this register.
Note:
In Mode 1, a counter value of FFFFh means that the Tach
did not detect the programmed number of edges in
655ms. A stuck fan can be detected by setting the TACHx
High Limit Register to a number less than FFFFh. If the
internal counter then reaches FFFFh, the reading register
will be set to FFFFh and an out-of-limit interrupt can be
sent to the EC.
15 TACH_INPUT_INT_EN
1=Enable Tach Input toggle interrupt from Tach block
0=Disable Tach Input toggle interrupt from Tach block
14 COUNT_READY_INT_EN
1=Enable Count Ready interrupt from Tach block
0=Disable Count Ready interrupt from Tach block
13 Reserved
12:11 TACH_EDGES
A Tach signal is a square wave with a 50% duty cycle. Typically, two
Tach periods represents one revolution of the fan. A Tach period consists of three Tach edges.
R
-
-
R/W
00b
VCC1_
RESET
This programmed value represents the number of Tach edges that
will be used to determine the interval for which the number of
100kHz_Clk pulses will be counted
11b=9 Tach edges (4 Tach periods)
10b=5 Tach edges (2 Tach periods)
01b=3 Tach edges (1 Tach period)
00b=2 Tach edges (1/2 Tach period)
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Offset
00h
Bits
Description
10 TACH_READING_MODE_SELECT
Reset
Event
Type
Default
R/W
0b
VCC1_
RESET
R
-
-
R/W
0b
VCC1_
RESET
1=Counter is incremented on the rising edge of the 100kHz_Clk input.
The counter is latched into the TACHX_COUNTER field and
reset when the programmed number of edges is detected.
0=Counter is incremented when Tach Input transitions from low-tohigh state (default)
9 Reserved
8 FILTER_ENABLE
This filter is used to remove high frequency glitches from Tach Input.
When this filter is enabled, Tach input pulses less than two 100kHz_Clk periods wide get filtered.
1= Filter enabled
0= Filter disabled (default)
It is recommended that the Tach input filter always be enabled.
7:2 Reserved
1 TACH_ENABLE
This bit gates the clocks into the block. When clocks are gated, the
TACHx pin is tristated. When re-enabled, the internal counters will
continue from the last known state and stale status events may still
be pending. Firmware should discard any status or reading values
until the reading value has been updated at least one time after the
enable bit is set.
R
-
-
R/W
0b
VCC1_
RESET
R/W
0b
VCC1_
RESET
1= TACH Monitoring enabled, clocks enabled.
0= TACH Idle, clocks gated
0 TACH_OUT_OF_LIMIT_ENABLE
This bit is used to enable the TACH_OUT_OF_LIMIT_STATUS bit in
the TACHx Status Register to generate an interrupt event.
1=Enable interrupt output from Tach block
0=Disable interrupt output from Tach block (default)
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17.11.2
Offset
TACHX STATUS REGISTER
04h
Bits
Description
31:4 Reserved
3 COUNT_READY_STATUS
This status bit is asserted when the Tach input changes state and
when the counter value is latched. This bit remains cleared to '0'
when the TACH_READING_MODE_SELECT bit in the TACHx Control Register is '0'.
When the TACH_READING_MODE_SELECT bit in the TACHx Control Register is set to '1', this bit is set to ‘1’ when the counter value is
latched by the hardware. It is cleared when written with a ‘1’. If
COUNT_READY_INT_EN in the TACHx Control Register is set to 1,
this status bit will assert the Tach Interrupt signal.
Type
Default
Reset
Event
R
-
-
R/WC
0b
VCC1_R
ESET
R/WC
0b
VCC1_R
ESET
R
0b
VCC1_R
ESET
R/WC
0b
VCC1_R
ESET
1=Reading ready
0=Reading not ready
2 TOGGLE_STATUS
This bit is set when Tach Input changes state. It is cleared when written with a ’1’. If TACH_INPUT_INT_EN in the TACHx Control Register is set to ’1’, this status bit will assert the Tach Interrupt signal.
1=Tach Input changed state (this bit is set on a low-to-high or high-tolow transition)
0=Tach stable
1 TACH_PIN_STATUS
This bit reflects the state of Tach Input. This bit is a read only bit that
may be polled by the embedded controller.
1= Tach Input is high
0= Tach Input is low
0 TACH_OUT_OF_LIMIT_STATUS
This bit is set when the Tach Count value is greater than the high
limit or less than the low limit. It is cleared when written with a ’1’. To
disable this status event set the limits to their extreme values. If
TACH_OUT_OF_LIMIT_ENABLE in the TACHx Control Register is
set to 1’, this status bit will assert the Tach Interrupt signal.
1=Tach is outside of limits
0=Tach is within limits
Note 1: Some fans offer a Locked Rotor output pin that generates a level event if a locked rotor is detected. This bit
may be used in combination with the Tach pin status bit to detect a locked rotor signal event from a fan.
2: Tach Input may come up as active for Locked Rotor events. This would not cause an interrupt event because
the pin would not toggle. Firmware must read the status events as part of the initialization process, if polling
is not implemented.
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17.11.3
Offset
TACHX HIGH LIMIT REGISTER
08h
Bits
Description
31:16 Reserved
15:0 TACH_HIGH_LIMIT
This value is compared with the value in the TACHX_COUNTER
field. If the value in the counter is greater than the value programmed
in this register, the TACH_OUT_OF_LIMIT_STATUS bit will be set.
The TACH_OUT_OF_LIMIT_STATUS status event may be enabled
to generate an interrupt to the embedded controller via the
TACH_OUT_OF_LIMIT_ENABLE bit in the TACHx Control Register.
17.11.4
Offset
Type
Default
Reset
Event
-
-
-
R/W
FFFFh
VCC1_
RESET
Type
Default
Reset
Event
R
-
-
R/W
0000h
VCC1_
RESET
TACHX LOW LIMIT REGISTER
0Ch
Bits
Description
31:16 Reserved
15:0 TACHX_LOW_LIMIT
This value is compared with the value in the TACHX_COUNTER field
of the TACHx Control Register. If the value in the counter is less than
the value programmed in this register, the TACH_OUT_OF_LIMIT_STATUS bit will be set. The TACH_OUT_OF_LIMIT_STATUS status event may be enabled to generate an interrupt to the embedded
controller via the TACH_OUT_OF_LIMIT_ENABLE bit in the TACHx
Control Register
To disable the TACH_OUT_OF_LIMIT_STATUS low event, program
0000h into this register.
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18.0
PWM
18.1
Introduction
This block generates a PWM output that can be used to control 4-wire fans, blinking LEDs, and other similar devices.
Each PWM can generate an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz. The PWM controller can also used to generate the PROCHOT output and Speaker output.
The PWMx Counter ON Time registers and PWMx Counter OFF Time registers determine the operation of the
PWM_OUTPUT signals. See Section 18.11.1, "PWMx Counter ON Time Register," on page 188 and Section 18.11.2,
"PWMx Counter OFF Time Register," on page 189 for a description of the PWM_OUTPUT signals.
18.2
References
There are no standards referenced in this chapter.
18.3
Terminology
There is no terminology defined for this section.
18.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 18-1:
I/O DIAGRAM OF BLOCK
PWM
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
There are no external signals for this block.
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18.5
Signal Description
TABLE 18-1:
18.6
SIGNAL DESCRIPTION TABLE
Name
Direction
PWM_OUTPUT
OUTPUT
Description
Pulse Width Modulated signal to PWMx pin.
Host Interface
The registers defined for the PWM Interface are accessible by the various hosts as indicated in Section 18.11, "EC-Only
Registers".
18.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
18.7.1
POWER DOMAINS
TABLE 18-2:
18.7.2
Name
Description
VCC1
The PWM logic and registers are powered by this single power source.
CLOCK INPUTS
TABLE 18-3:
18.7.3
POWER SOURCES
CLOCK INPUTS
Name
Description
100kHz_Clk
100kHz_Clk clock input for generating low PWM frequencies, such as 10
Hz to 100 Hz.
48 MHz Ring Oscillator
48 MHz Ring Oscillator clock input for generating high PWM frequencies,
such as 15 kHz to 30 kHz.
RESETS
TABLE 18-4:
RESET SIGNALS
Name
VCC1_RESET
18.8
Description
This reset signal resets all the logic in this block to its initial state
including the registers, which are set to their defined default state.
Interrupts
The PWM block does not generate any interrupt events.
18.9
Low Power Modes
The PWM may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry. When the PWM is
in the sleep state, the internal counters reset to 0 and the internal state of the PWM and the PWM_OUTPUT signal set
to the OFF state.
18.10 Description
The PWM_OUTPUT signal is used to generate a duty cycle of specified frequency. This block can be programmed so
that the PWM signal toggles the PWM_OUTPUT, holds it high, or holds it low. When the PWM is configured to toggle,
the PWM_OUTPUT alternates from high to low at the rate specified in the PWMx Counter ON Time Register and PWMx
Counter OFF Time Register.
The following diagram illustrates how the clock inputs and registers are routed to the PWM Duty Cycle & Frequency
Control logic to generate the PWM output.
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FIGURE 18-2:
BLOCK DIAGRAM OF PWM CONTROLLER
PWM BLOCK
Clock Select
CLOCK_HIGH
Clock
PreDivider
(15:0)
CLOCK_LOW
Invert_PWM
PWM_ OUTPUT
PWM Duty Cycle &
Frequency Control
EC I/F
Note:
16-bit down
counter
PWM Registers
In Figure 18-2, the 48 MHz Ring Oscillator is represented as CLOCK_HIGH and 100kHz_Clk is represented as CLOCK_LOW.
The PWM clock source to the PWM Down Counter, used to generate a duty cycle and frequency on the PWM, is determined through the Clock select[1] and Clock Pre-Divider[6:3] bits in the PWMx Configuration Register register.
The PWMx Counter ON/OFF Time registers determine both the frequency and duty cycle of the signal generated on
PWM_OUTPUT as described below.
The PWM frequency is determined by the selected clock source and the total on and off time programmed in the PWMx
Counter ON Time Register and PWMx Counter OFF Time Register registers. The frequency is the time it takes (at that
clock rate) to count down to 0 from the total on and off time.
The PWM duty cycle is determined by the relative values programmed in the PWMx Counter ON Time Register and
PWMx Counter OFF Time Register registers.
The PWM Frequency Equation and PWM Duty Cycle Equation are shown below.
FIGURE 18-3:
PWM FREQUENCY EQUATION
PWM Frequency =
1
------------------------------------------- P reDivisor + 1
ClockSourceFrequency
------------------------------------------------------------------------------------------------------------------------------ PWMCounterOnTime + PWMCounterOffTime
In Figure 18-3, the ClockSourceFrequency variable is the frequency of the clock source selected by the Clock Select
bit in the PWMx Configuration Register, and PreDivisor is a field in the PWMx Configuration Register. The PWMCounterOnTime, PWMCounterOffTime are registers that are defined in Section 18.11, "EC-Only Registers".
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FIGURE 18-4:
PWM DUTY CYCLE EQUATION
PWM Duty Cycle =
PWMCounterOnTime
------------------------------------------------------------------------------------------------------------------------------- PWMCounterOnTime + P WMCounterOffTime
The PWMx Counter ON Time Register and PWMx Counter OFF Time Register registers should be accessed as 16-bit
values.
18.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the PWM. The addresses of
each register listed in this table are defined as a relative offset to the host “Base Address” defined in the EC-Only Register Base Address Table.
TABLE 18-5:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address
PWM
0
EC
32-bit internal
address space
4000_5800h
PWM
1
EC
32-bit internal
address space
4000_5810h
PWM
2
EC
32-bit internal
address space
4000_5820h
PWM
3
EC
32-bit internal
address space
4000_5830h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 18-6:
EC-ONLY REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
PWMx Counter ON Time Register
04h
PWMx Counter OFF Time Register
08h
PWMx Configuration Register
18.11.1
Offset
PWMX COUNTER ON TIME REGISTER
00h
Bits
Description
31:16 Reserved
15:0 PWMX_COUNTER_ON_TIME
This field determine both the frequency and duty cycle of the PWM
signal.
When this field is set to zero and the PWMX_COUNTER_OFF_TIME is not set to zero, the PWM_OUTPUT is held low (Full Off).
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Type
Default
Reset
Event
R
-
-
R/W
0000h
VCC1_R
ESET
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18.11.2
PWMX COUNTER OFF TIME REGISTER
Offset
04h
Bits
Description
31:16 Reserved
15:0 PWMX_COUNTER_OFF_TIME
This field determine both the frequency and duty cycle of the PWM
signal.
When this field is set to zero, the PWM_OUTPUT is held high (Full
On).
18.11.3
Type
Default
Reset
Event
R
-
-
R/W
FFFFh
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
0000b
VCC1_R
ESET
R/W
0b
VCC1_R
ESET
R/W
0b
VCC1_R
ESET
R/W
0b
VCC1_R
ESET
PWMX CONFIGURATION REGISTER
Offset
08h
Bits
Description
31:7 Reserved
6:3 CLOCK_PRE_DIVIDER
The Clock source for the 16-bit down counter (see PWMx Counter
ON Time Register and PWMx Counter OFF Time Register) is determined by bit D1 of this register. The Clock source is then divided by
the value of Pre-Divider+1 and the resulting signal determines the
rate at which the down counter will be decremented. For example, a
Pre-Divider value of 1 divides the input clock by 2 and a value of 2
divides the input clock by 3. A Pre-Divider of 0 will disable the PreDivider option.
2 INVERT
1= PWM_OUTPUT ON State is active low
0=PWM_OUTPUT ON State is active high
1 CLOCK_SELECT
This bit determines the clock source used by the PWM duty cycle
and frequency control logic.
1=CLOCK_LOW
0=CLOCK_HIGH
0 PWM_ENABLE
1=Enabled (default)
0=Disabled (gates clocks to save power)
Note:
When the PWM enable bit is set to 0 the internal counters
are reset and the internal state machine is set to the OFF
state. In addition, the PWM_OUTPUT signal is set to the
inactive state as determined by the Invert bit. The PWMx
Counter ON Time Register and PWMx Counter OFF
Time Register are not affected by the PWM enable bit
and may be read and written while the PWM enable bit is
0.
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19.0
RPM-PWM INTERFACE
19.1
Introduction
The RPM-PWM Interface is closed-loop RPM based Fan Control Algorithm that monitors the fan’s speed and automatically adjusts the drive to maintain the desired fan speed.
The RPM-PWM Interface functionality consists of a closed-loop “set-and-forget” RPM based fan controller.
19.2
References
No references have been cited for this chapter
19.3
Terminology
There is no terminology defined for this chapter.
19.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
The registers in the block are accessed by embedded controller code at the addresses shown in Section 19.9, "Fan
Control Register Bank".
Figure 19-1 illustrates and categorizes the RPM-PWM Interface block signals. These signals are described in Table 191.
FIGURE 19-1:
RPM-PWM INTERFACE I/O DIAGRAM
RPM-PWM Interface
Host Interface
Fan Control
Power, Clocks and Reset
Interrupts
19.4.1
FAN CONTROL
The Fan Control Signal Description Table lists the signals that are routed to/from the block.
TABLE 19-1:
FAN CONTROL SIGNAL DESCRIPTION TABLE
Name
19.4.2
Direction
TACH
Input
PWM
Output
Description
Tachometer input from fan
PWM fan drive output
HOST INTERFACE
The registers defined for the RPM-PWM Interface are accessible by the various hosts as indicated in Section 19.9, "Fan
Control Register Bank".
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19.5
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
19.5.1
POWER DOMAINS
TABLE 19-2:
POWER SOURCES
Name
VCC1
19.5.2
Description
This power well sources the registers and logic in this block.
CLOCK INPUTS
TABLE 19-3:
CLOCK INPUTS
Name
48 MHz Ring Oscillator
19.5.3
Description
This clock signal drives selected logic (e.g., counters).
RESETS
TABLE 19-4:
RESET SIGNALS
Name
VCC1_RESET
19.6
Description
This reset signal resets all of the registers and logic in this block.
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 19-5:
INTERRUPTS
Source
Fan Fail/Spin Status Interrupt
Fan Stall Status Interrupt
19.7
Description
The DRIVE_FAIL & FAN_SPIN bits in the Fan Status Register are logically ORed and routed to the FAIL_SPIN Interrupt
The FAN_STALL bit in the Fan Status Register is routed to the
FAN_STALL Interrupt
Low Power Modes
The RPM-PWM Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
19.8
Description
This section defines the functionality of the block.
19.8.1
GENERAL OPERATION
The RPM-PWM Interface is an RPM based Fan Control Algorithm that monitors the fan’s speed and automatically
adjusts the drive to maintain the desired fan speed. This RPM based Fan Control Algorithm controls a PWM output
based on a tachometer input.
19.8.2
FAN CONTROL MODES OF OPERATION
The RPM-PWM Interface has two modes of operation for the PWM Fan Driver. They are:
1.
•
•
•
•
Manual Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver
Setting Register (see Section 19.9.1, "Fan Setting Register") will update the fan drive based on the programmed
ramp rate (default disabled).
The Manual Mode is enabled by clearing the EN_ALGO bit in the Fan Configuration Register (see Section 19.9.3,
"Fan Configuration 1 Register").
Whenever the Manual Mode is enabled the current drive settings will be changed to what was last used by the
RPM control algorithm.
Setting the drive value to 00h will disable the PWM Fan Driver.
Changing the drive value from 00h will invoke the Spin Up Routine.
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2.
Using RPM based Fan Control Algorithm - in this mode of operation, the user determines a target tachometer
reading and the drive setting is automatically updated to achieve this target speed.
TABLE 19-6:
FAN CONTROLS ACTIVE FOR OPERATING MODE
Manual Mode
Algorithm
Fan Driver Setting (read / write)
Fan Driver Setting (read only)
EDGES[1:0] (Fan Configuration)
EDGES[1:0] (Fan Configuration)
UPDATE[2:0] (Fan configuration)
UPDATE[2:0] (Fan configuration)
LEVEL (Spin Up Configuration)
LEVEL (Spin Up Configuration)
SPINUP_TIME[1:0] (Spin Up Configuration)
SPINUP_TIME[1:0] (Spin Up Configuration)
Fan Step
Fan Step
-
Fan Minimum Drive
Valid TACH Count
Valid TACH Count
-
TACH Target
TACH Reading
TACH Reading
RANGE[2:0] (Fan Configuration 2)
RANGE[2:0] (Fan Configuration 2)
-
DRIVE_FAIL_CNT[2:0] (Spin Up Config) and
Drive Fail Band
19.8.3
RPM BASED FAN CONTROL ALGORITHM
The RPM-PWM Interface includes an RPM based Fan Control Algorithm.
The fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach and maintain the
system’s desired fan speed to an accuracy directly proportional to the accuracy of the clock source. Figure 19-2, "RPM
based Fan Control Algorithm" shows a simple flow diagram of the RPM based Fan Control Algorithm operation.
The desired tachometer count is set by the user inputting the desired number of 32.768KHz cycles that occur per fan
revolution. The user may change the target count at any time. The user may also set the target count to FFh in order to
disable the fan driver.
For example, if a desired RPM rate for a 2-pole fan is 3000 RPMs, the user would input the hexadecimal equivalent of
1312d (52_00h in the TACH Target Registers). This number represents the number of 32.768KHz cycles that would
occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs (see Section
19.9.11, "TACH Target Register" and Section 19.9.12, "TACH Reading Register").
The RPM-PWM Interface’s RPM based Fan Control Algorithm has programmable configuration settings for parameters
such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a
stalled/stuck fan condition while also asserting the interrupt signal. The RPM-PWM Interface works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally
supplied 32.768KHz clock source or with its own internal 32KHz oscillator depending on the required accuracy.
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FIGURE 19-2:
RPM BASED FAN CONTROL ALGORITHM
Set TACH Target
Count
Measure Fan Speed
Spin Up
Required
?
Yes
Perform Spin Up
Routine
No
Maintain Fan Drive
Yes
TACH
Reading=
TACH
Target?
No
Yes
Reduce Fan Drive
19.8.3.1
TACH
Reading <
TACH
Target?
Ramp Rate Control
No
Increase Fan Drive
Programming the RPM Based Fan Control Algorithm
The RPM based Fan Control Algorithm powers-up disabled. The following registers control the algorithm. The RPMPWM Interface fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the TACH
Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm
behavior based on application requirements.
1.
2.
3.
4.
5.
6.
7.
Set the Valid TACH Count Register to the minimum tachometer count that indicates the fan is spinning.
Set the Spin Up Configuration Register to the spin up level and Spin Time desired.
Set the Fan Step Register to the desired step size.
Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation.
Set the Update Time, and Edges options in the Fan Configuration Register.
Set the TACH Target Register to the desired tachometer count.
Enable the RPM based Fan Control Algorithm by setting the EN_ALGO bit.
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19.8.3.2
Tachometer Measurement
In both modes of operation, the tachometer measurement operates independently of the mode of operation of the fan
driver and RPM based Fan Speed Control algorithm. Any tachometer reading that is higher than the Valid TACH Count
(see Section 19.9.9, "Valid TACH Count Register") will flag a stalled fan and trigger an interrupt.
When measuring the tachometer, the fan must provide a valid tachometer signal at all times to ensure proper operation.
The tachometer measurement circuitry is programmable to detect the fan speed of a variety of fan configurations and
architectures including 1-pole, 2-pole (default), 3-pole, and 4-pole fans.
APPLICATION NOTE: The tachometer measurement works independently of the drive settings. If the device is put
into manual mode and the fan drive is set at a level that is lower than the fan can operate
(including zero drive), the tachometer measurement may signal a Stalled Fan condition and
assert an interrupt.
STALLED FAN
If the TACH Reading Register exceeds the user-programmable Valid TACH Count setting, it will flag the fan as stalled
and trigger an interrupt. If the RPM based Fan Control Algorithm is enabled, the algorithm will automatically attempt to
restart the fan until it detects a valid tachometer level or is disabled.
The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the
mode of operation.
• Whenever the Manual Mode is enabled or whenever the drive value is changed from 00h, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 19-17, “Spin time,” on page 203)
to allow the fan an opportunity to reach a valid speed without generating unnecessary interrupts.
• In Manual Mode, whenever the TACH Reading Register exceeds the Valid TACH Count Register setting, the
FAN_STALL status bit will be set.
• When the RPM based Fan Control Algorithm, the stalled fan condition is checked whenever the Update Time is
met and the fan drive setting is updated. It is not a continuous check.
19.8.3.3
Spin Up Routine
The RPM-PWM Interface also contains programmable circuitry to control the spin up behavior of the fan driver to ensure
proper fan operation. The Spin Up Routine is initiated under the following conditions:
• The TACH Target High Byte Register value changes from a value of FFh to a value that is less than the Valid
TACH Count (see Section 19.9.9, "Valid TACH Count Register").
• The RPM based Fan Control Algorithm’s measured tachometer reading is greater than the Valid TACH Count.
• When in Manual Mode, the Drive Setting changes from a value of 00h.
When the Spin Up Routine is operating, the fan driver is set to full scale for one quarter of the total user defined spin up
time. For the remaining spin up time, the fan driver output is set a a user defined level (30% to 65% drive).
After the Spin Up Routine has finished, the RPM-PWM Interface measures the tachometer. If the measured tachometer
reading is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine
will automatically attempt to restart the fan.
APPLICATION NOTE: When the device is operating in manual mode, the FAN_SPIN status bit may be set if the
fan drive is set at a level that is lower than the fan can operate (excluding zero drive which
disables the fan driver). If the FAN_SPIN interrupt is unmasked, this condition will trigger an
errant interrupt.
Figure 19-3, "Spin Up Routine" shows an example of the Spin Up Routine in response to a programmed fan speed
change based on the first condition above.
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FIGURE 19-3:
SPIN UP ROUTINE
100%
(optional)
30% through 65%
Fan Step
New Target Count
Algorithm controlled drive
Prev Target
Count = FFh
¼ of Spin Up Time
Update Time
Spin Up Time
Target Count
Changed
19.8.4
Check TACH
Target Count
Reached
PWM DRIVER
The RPM-PWM Interface contains an optional, programmable 8-bit PWM driver which can serve as part of the RPM
based Fan Speed Control Algorithm or in Manual Mode.
When enabled, the PWM driver can operate in four programmable frequency bands. The lower frequency bands offer
frequencies in the range of 9.5Hz to 4.8kHz while the higher frequency options offer frequencies of 21Hz or 25.2kHz.
19.8.5
ALERTS AND LIMITS
Figure 19-4, "Interrupt Flow" shows the interactions of the interrupts for fan events.
If the Fan Driver detects a drive fail, spin-up or stall event, the interrupt signal will be asserted (if enabled).
All of these interrupts can be masked from asserting the interrupt signal individually. If any bit of either Status register is
set, the interrupt signal will be asserted provided that the corresponding interrupt enable bit is set accordingly.
The Status register will be updated due to an active event, regardless of the setting of the individual enable bits. Once
a status bit has been set, it will remain set until the Status register bit is written to 1 (and the error condition has been
removed).
If the interrupt signal is asserted, it will be cleared immediately if either the status or enable bit is cleared.
See Section 19.6, "Interrupts," on page 191.
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FIGURE 19-4:
INTERRUPT FLOW
Interrupt
Status Bit 1
Interrupt Event 1
.
.
.
Interrupt
Enable Bit 1
Interrupt
Status Bit n
.
.
.
.
.
.
..
Interrupt Signal
Interrupt Event n
Interrupt
Enable Bit n
19.9
Fan Control Register Bank
The registers listed in the Table 19-8, "Fan Control Register Summary" are for a single instance of the RPM-PWM Interface block. The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in Table 19-7, "Fan Control Register Bank Base Address Table".
TABLE 19-7:
FAN CONTROL REGISTER BANK BASE ADDRESS TABLE
Instance
Number
Instance Name
Host
Address Space
Base Address (Note 19-1)
RPM-PWM Inter0
EC
32-bit internal
4000_A000h
face
address space
Note 19-1
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
TABLE 19-8:
FAN CONTROL REGISTER SUMMARY
Register Name
Offset
Fan Setting
00h
PWM Divide
01h
Fan Configuration 1
02h
Fan Configuration 2
03h
MCHP Reserved
04h
Gain
05h
Fan Spin Up Configuration
06h
Fan Step
07h
Fan Minimum Drive
08h
Valid Tach Count
09h
Fan Drive Fail Band Low Byte
0Ah
Fan Drive Fail Band High Byte
0Bh
Tach Target Low Byte
0Ch
Tach Target High Byte
0Dh
Tach Reading Low Byte
0Eh
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TABLE 19-8:
19.9.1
FAN CONTROL REGISTER SUMMARY (CONTINUED)
Register Name
Offset
Tach Reading High Byte
0Fh
PWM Driver Base Frequency
10h
Fan Status
11h
FAN SETTING REGISTER
The Fan Setting Registers are used to control the output of the Fan Driver. The driver setting operates independently
of the Polarity bit for the PWM output. That is, a setting of 00h will mean that the fan drive is at minimum drive while a
value of FFh will mean that the fan drive is at maximum drive.
If the Spin Up Routine is invoked, reading from the registers will return the current fan drive setting that is being used
by the Spin Up Routine instead of what was previously written into these registers.
The Fan Driver Setting Registers, when the RPM based Fan Control Algorithm is enabled, are read only. Writing to the
register will have no effect and the data will not be stored. Reading from the register will always return the current fan
drive setting.
If the INT_PWRGD pin is de-asserted, the Fan Driver Setting Register will be made read only. Writing to the register will
have no effect and reading from the register will return 000h.
When the RPM based Fan Control Algorithm is disabled, the current fan drive setting that was last used by the algorithm
is retained and will be used.
If the Fan Driver Setting Register is set to a value of 00h, all tachometer related status bits will be masked until the setting
is changed. Likewise, the FAN_SHORT bit will be cleared and masked until the setting is changed.
The contents of the register represent the weighting of each bit in determining the final duty cycle. The output drive for
a PWM output is given by the following equation:
- Drive = (FAN_SETTING VALUE/255) x 100%.
Offset
00h
Bits
Description
7:0 FAN_SETTING[7:0]
The Fan Driver Setting used to control the output of the Fan Driver.
19.9.2
Type
Default
R/W
00h
Reset
Event
VCC1_R
ESET
PWM DIVIDE REGISTER
The PWM Divide Register determines the final PWM frequency. The base frequency set by the PWM_BASE[1:0] bits is
divided by the decimal equivalent of the register settings.
The final PWM frequency is derived as the base frequency divided by the value of this register as shown in the equation
below:
- PWM_Frequency = base_clk / PWM_D
Where:
- base_clk = The base frequency set by the PWMx_CFG[1:0] bits
- PWM_D = the divide setting set by the PWM Divide Register.
Offset
01h
Bits
Description
7:0 PWM_DIVIDE[7:0]
The PWM Divide value determines the final frequency of the PWM
driver. The driver base frequency is divided by the PWM Divide
value to determine the final frequency.
2016 Microchip Technology Inc.
Type
Default
R/W
01h
Reset
Event
VCC1_R
ESET
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19.9.3
FAN CONFIGURATION 1 REGISTER
The Fan Configuration Register 1 controls the general operation of the RPM based Fan Control Algorithm used by the
fan driver.
Offset
02h
Bits
Description
Reset
Event
Type
Default
R/W
0b
VCC1_R
ESET
6:5 RANGE[1:0]
Adjusts the range of reported and programmed tachometer reading
values. The RANGE bits determine the weighting of all TACH values
(including the Valid TACH Count, TACH Target, and TACH reading)
as shown in Table 19-9, "Range Decode".
R/W
01b
VCC1_R
ESET
4:3 EDGES[1:0]
Determines the minimum number of edges that must be detected on
the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan).
Increasing the number of edges measured with respect to the number of poles of the fan will cause the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In
order for the FSC Algorithm to operate correctly, the TACH Target
must be updated by the user to accommodate this shift. The Effective Tach Multiplier shown in Table 19-10, "Minimum Edges for Fan
Rotation" is used as a direct multiplier term that is applied to the
Actual RPM to achieve the Reported RPM. It should only be applied
if the number of edges measured does not match the number of
edges expected based on the number of poles of the fan (which is
fixed for any given fan).
Contact Microchip for recommended settings when using fans with
more or less than 2 poles.
R/W
01b
VCC1_R
ESET
2:0 UPDATE[2:0]
Determines the base time between fan driver updates. The Update
Time, along with the Fan Step Register, is used to control the ramp
rate of the drive response to provide a cleaner transition of the actual
fan operation as the desired fan speed changes. The Update Time is
set as shown in Table 19-11, "Update Time".
R/W
011b
VCC1_R
ESET
7 EN_ALGO
Enables the RPM based Fan Control Algorithm.
• ‘0’ - (default) the control circuitry is disabled and the fan driver
output is determined by the Fan Driver Setting Register.
• ‘1’ - the control circuitry is enabled and the Fan Driver output will
be automatically updated to maintain the programmed fan
speed as indicated by the TACH Target Register.
APPLICATION NOTE: This ramp rate control applies for all
changes to the active PWM output
including when the RPM based Fan Speed
Control Algorithm is disabled.
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TABLE 19-9:
RANGE DECODE
Range [1:0]
1
0
Reported Minimum RPHM
TACH Count Multiplier
0
0
500
1
0
1
1000 (default)
2
1
0
2000
4
1
1
4000
8
TABLE 19-10: MINIMUM EDGES FOR FAN ROTATION
Edges 1:0]
Number of Fan Poles
Effective TACH Multiplier (Based
on 2 Pole Fans)
If Edges Changed
3
1
0.5
5
2 (default)
1
0
7
3
1.5
1
9
4
2
1
0
Minimum TACH Edges
0
0
0
1
1
1
TABLE 19-11: UPDATE TIME
Update [2:0]
2
1
0
TACH Count Multiplier (ms)
0
0
0
100
0
0
1
200
0
1
0
300
0
1
1
400 (default)
1
0
0
500
1
0
1
800
1
1
0
1200
1
1
1
1600
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19.9.4
FAN CONFIGURATION 2 REGISTER
The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the RPM based Fan
Control Algorithm.
Offset
03h
Bits
Description
Reset
Event
Type
Default
7 MCHP Reserved
R/W
0b
VCC1_R
ESET
6 EN_RRC
Enables the ramp rate control circuitry during the Manual Mode of
operation.
• ‘0’ (default) - The ramp rate control circuitry for the Manual
Mode of operation is disabled. When the Fan Drive Setting values are changed and the RPM based Fan Control Algorithm is
disabled, the fan driver will be set to the new setting immediately.
• ‘1’ - The ramp rate control circuitry for the Manual Mode of operation is enabled. The PWM setting will follow the ramp rate controls as determined by the Fan Step and Update Time settings.
The maximum PWM step is capped at the Fan Step setting and
is updated based on the Update Time as given by Table 19-11,
"Update Time".
R/W
0b
VCC1_R
ESET
5 DIS_GLITCH
Disables the low pass glitch filter that removes high frequency noise
injected on the TACH pin.
• ‘0’ (default) - The glitch filter is enabled.
• ‘1’ - The glitch filter is disabled.
R/W
0b
VCC1_R
ESET
4:3 DER_OPT[1:0]
Control some of the advanced options that affect the derivative portion of the RPM based fan control algorithm as shown in Table 1912, "Derivative Options". These bits only apply if the Fan Speed
Control Algorithm is used.
R/W
11b
VCC1_R
ESET
2:1 ERR_RNG[1:0]
Control some of the advanced options that affect the error window.
When the measured fan speed is within the programmed error window around the target speed, the fan drive setting is not updated.
These bits only apply if the Fan Speed Control Algorithm is used.
See Table 19-13, "Error Range Options".
R/W
01b
VCC1_R
ESET
0 POLARITY
Determines the polarity of the PWM driver. This does NOT affect the
drive setting registers. A setting of 0% drive will still correspond to
0% drive independent of the polarity.
• ‘0’ (default) - the Polarity of the PWM driver is normal. A drive
setting of 00h will cause the output to be set at 0% duty cycle
and a drive setting of FFh will cause the output to be set at
100% duty cycle.
• ‘1’ - The Polarity of the PWM driver is inverted. A drive setting of
00h will cause the output to be set at 100% duty cycle and a
drive setting of FFh will cause the output to be set at 0% duty
cycle.
R/W
0b
VCC1_R
ESET
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TABLE 19-12: DERIVATIVE OPTIONS
DER_OPT[1:0]
NOTE
(see Section 19.9.7, "Fan Step
Register")
1
0
0
0
No derivative options used
0
1
Basic derivative. The derivative of the
PWM steps are limited to the maxierror from the current drive setting and mum PWM drive step value in Fan
the target is added to the iterative PWM Step Register
drive setting (in addition to proportional
and integral terms)
1
0
Step derivative. The derivative of the
error from the current drive setting and
the target is added to the iterative PWM
drive setting and is not capped by the
maximum PWM drive step. This allows
for very fast response times
PWM steps are not limited to the maximum PWM drive step value in Fan
Step Register (i.e., maximum fan step
setting is ignored)
1
1
Both the basic derivative and the step
derivative are used effectively causing
the derivative term to have double the
effect of the derivative term (default).
PWM steps are not limited to the maximum PWM drive step value in Fan
Step Register (i.e., maximum fan step
setting is ignored)
Operation
PWM steps are limited to the maximum PWM drive step value in Fan
Step Register
TABLE 19-13: ERROR RANGE OPTIONS
ERR_RNGX[1:0]
19.9.5
1
0
Operation
0
0
0 RPM
0
1
50 RPM (default)
1
0
100 RPM
1
1
200 RPM
GAIN REGISTER
The Gain Register The Gain Register stores the gain terms used by the proportional and integral portions of the RPM
based Fan Control Algorithm. These terms will affect the FSC closed loop acquisition, overshoot, and settling as would
be expected in a classic PID system.
This register only applies if the Fan Speed Control Algorithm is used.
Offset
05h
Bits
Description
Reset
Event
Type
Default
7:6 RESERVED
R/W
00h
-
5:4 GAIND[1:0]
The derivative gain term. See Table 19-14, "Gain Decode".
R/W
10h
VCC1_R
ESET
3:2 GAINI[1:0]
The integral gain term. See Table 19-14, "Gain Decode".
R/W
10h
VCC1_R
ESET
1:0 GAINP[1:0]
The proportional gain term. See Table 19-14, "Gain Decode".
R/W
10h
VCC1_R
ESET
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TABLE 19-14: GAIN DECODE
GAIND or GAINP or GAINI [1:0]
19.9.6
1
0
Respective Gain Factor
0
0
1x
0
1
2x
1
0
4x (default)
1
1
8x
FAN SPIN UP CONFIGURATION REGISTER
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine.
Offset
06h
Bits
Description
Reset
Event
Type
Default
7:6 DRIVE_FAIL_CNT[1:0]
Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 19-15, "DRIVE_FAIL_CNT[1:0]
Bit Decode". This circuitry determines whether the fan can be driven
to the desired Tach target. These settings only apply if the Fan
Speed Control Algorithm is enabled.
R/W
00b
VCC1_R
ESET
5 NOKICK
Determines if the Spin Up Routine will drive the fan to 100% duty
cycle for 1/4 of the programmed spin up time before driving it at the
programmed level.
• ‘0’ (default) - The Spin Up Routine will drive the PWM to 100%
for 1/4 of the programmed spin up time before reverting to the
programmed spin level.
• ‘1’ - The Spin Up Routine will not drive the PWM to 100%. It will
set the drive at the programmed spin level for the entire duration
of the programmed spin up time.
R/W
0b
VCC1_R
ESET
4:2 SPIN_LVL[2:0]
SPIN_LVL[2:0] - Determines the final drive level that is used by the
Spin Up Routine as shown in Table 19-16, "Spin Level".
R/W
110b
VCC1_R
ESET
1:0 SPINUP_TIME[1:0]
Determines the maximum Spin Time that the Spin Up Routine will
run for. If a valid tachometer measurement is not detected before the
Spin Time has elapsed, an interrupt will be generated. When the
RPM based Fan Control Algorithm is active, the fan driver will
attempt to re-start the fan immediately after the end of the last spin
up attempt.
The Spin Time is set as shown in Table 19-17, "Spin time".
R/W
01b
VCC1_R
ESET
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TABLE 19-15: DRIVE_FAIL_CNT[1:0] BIT DECODE
DRIVE_FAIL_CNT[1:0]
1
0
0
0
Disabled - the Drive Fail detection circuitry is disabled
0
1
16 - the Drive Fail detection circuitry will count for 16 update periods
1
0
32 - the Drive Fail detection circuitry will count for 32 update periods
1
1
64 - the Drive Fail detection circuitry will count for 64 update periods
Number of Update Periods
TABLE 19-16: SPIN LEVEL
SPIN_LVL[2:0]
2
1
0
Spin Up Drive Level
0
0
0
30%
0
0
1
35%
0
1
0
40%
0
1
1
45%
1
0
0
50%
1
0
1
55%
1
1
0
60% (default)
1
1
1
65%
TABLE 19-17: SPIN TIME
SPINUP_TIME[1:0]
1
0
0
0
250 ms
0
1
500 ms (default)
1
0
1 sec
1
1
2 sec
19.9.7
Total Spin Up Time
FAN STEP REGISTER
The Fan Step Register, along with the Update Time, controls the ramp rate of the fan driver response calculated by the
RPM based Fan Control Algorithm for the Derivative Options field values of “00” and “01” in the Fan Configuration 2
Register (see Table 19-12, “Derivative Options,” on page 201).
The value of the register represents the maximum step size the fan driver will take for each update (see Section 19.9.3,
"Fan Configuration 1 Register," on page 198).
When the maximum step size limitation is applied, if the necessary fan driver delta is larger than the Fan Step, it will be
capped at the Fan Step setting and updated every Update Time ms.
The maximum step size is ignored for the Derivative Options field values of “10” and “11”.
Offset
07h
Type
Default
Reset
Event
7:6 RESERVED
R/W
00h
-
5:0 FAN_STEP[5:0]
R/W
10h
VCC1_R
ESET
Bits
Description
The Fan Step value represents the maximum step size the fan driver
will take between update times
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19.9.8
FAN MINIMUM DRIVE REGISTER
the Fan Minimum Drive Register stores the minimum drive setting for the RPM based Fan Control Algorithm. The RPM
based Fan Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed
is set at FFh (see "TACH Target Registers").
During normal operation, if the fan stops for any reason (including low drive), the RPM based Fan Control Algorithm will
attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful
way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation.
These registers only apply if the Fan Speed Control Algorithm is used.
Offset
08h
Bits
Description
7:0 MIN_DRIVE[7:0]
The minimum drive setting.
Type
Default
R/W
66h
Reset
Event
VCC1_R
ESET
APPLICATION NOTE: To ensure proper operation, the Fan Minimum Drive register must be set prior to setting the
Tach Target High and Low Byte registers, and then the Tach Target registers can be
subsequently updated. At a later time, if the Fan Minimum Drive register is changed to a
value higher than current Fan value, the Tach Target registers must also be updated.
19.9.9
VALID TACH COUNT REGISTER
The Valid TACH Count Register stores the maximum TACH Reading Register value to indicate that the fan is spinning
properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and
decide if the device needs to retry. See the equation in the TACH Reading Registers section for translating the RPM to
a count.
If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the
threshold set by this count), a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up
Routine.
APPLICATION NOTE: The automatic invoking of the Spin Up Routine only applies if the Fan Speed Control
Algorithm is used. If the FSC is disabled, then the device will only invoke the Spin Up Routine
when the PWM setting changes from 00h.
If a TACH Target setting is set above the Valid TACH Count setting, that setting will be ignored and the algorithm will
use the current fan drive setting.
These registers only apply if the Fan Speed Control Algorithm is used.
Offset
09h
Bits
Description
7:0 VALID_TACH_CNT[7:0]
The maximum TACH Reading Register value to indicate that the fan
is spinning properly.
19.9.10
Type
Default
R/W
F5h
Reset
Event
VCC1_R
ESET
FAN DRIVE FAIL BAND REGISTER
The Fan Drive Fail Band Registers store the number of Tach counts used by the Fan Drive Fail detection circuitry. This
circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed
is compared against the target fan speed.
This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching.
If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a
period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits in the Fan Spin Up Configuration Register on page
202, the DRIVE_FAIL status bit will be set and an interrupt generated.
These registers only apply if the Fan Speed Control Algorithm is used.
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Offset
0Ah
Bits
Description
15:3 FAN_DRIVE_FAIL_BAND[12:0]
The number of Tach counts used by the Fan Drive Fail detection circuitry
2:0 RESERVED
19.9.11
Type
RES
R/W
Default
Reset
Event
000000000 VCC1_R
0000b
ESET
000b
-
TACH TARGET REGISTER
The TACH Target Registers hold the target tachometer value that is maintained for the RPM based Fan Control Algorithm.
If the algorithm is enabled, setting the TACH Target Register High Byte to FFh will disable the fan driver (or set the PWM
duty cycle to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause the algorithm to invoke
the Spin Up Routine after which it will function normally.
These registers only apply if the Fan Speed Control Algorithm is used.
Offset
0Ch
Bits
Description
15:3 TACH_TARGET[12:0]
The target tachometer value.
2:0 RESERVED
19.9.12
Type
RES
R/W
Default
Reset
Event
1111111111 VCC1_R
111b
ESET
000b
-
TACH READING REGISTER
The TACH Reading Registers’ contents describe the current tachometer reading for the fan. By default, the data represents the fan speed as the number of 32.768kHz clock periods that occur for a single revolution of the fan.
The Equation below shows the detailed conversion from tachometer measurement (COUNT) to RPM.
1
n – 1
RPM = -------------- -------------------------------- fTACH 60
Poles
1
COUNT ---m
where:
-
Poles = number of poles of the fan (typically 2)
fTACH = the frequency of the tachometer measurement clock
n = number of edges measured (typically 5 for a 2 pole fan)
m = the multiplier defined by the RANGE bits
COUNT = TACH Reading Register value (in decimal)
The following equation shows the simplified translation of the TACH Reading Register count to RPM assuming a 2-pole
fan, measuring 5 edges, with a frequency of 32.768kHz.
3932160 m
RPM = ------------------------------COUNT
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Offset
0Eh
Bits
Description
Type
15:3 TACH_READING[12:0]
The current tachometer reading value.
RES
2:0 RESERVED
Default
Reset
Event
1111111111 VCC1_R
111b
ESET
R/W
000b
-
Type
Default
Reset
Event
7:2 RESERVED
RES
000000b
-
1:0 PWM_BASE[1:0]
Determines the frequency range of the PWM fan driver (when
enabled) as shown in Table 19-18.
R/W
00b
VCC1_R
ESET
19.9.13
PWM DRIVER BASE FREQUENCY REGISTER
- The PWM Driver Base Register controls the base PWM frequency range.
Offset
10h
Bits
Description
TABLE 19-18: PWM_BASE[1:0] DECODE
PWM_BASE[1:0]
1
19.9.14
0
PWM Frequency
0
0
26.83KHz
0
1
20.87kHz
1
0
4.82kHz
1
1
2.41KHz
FAN STATUS REGISTER
The bits in this register are routed to interrupts.
Offset
11h
Bits
Description
7:6 RESERVED
5 DRIVE_FAIL
The bit Indicates that the RPM-based Fan Speed Control Algorithm
cannot drive the Fan to the desired target setting at maximum drive.
• ‘0’ - The RPM-based Fan Speed Control Algorithm can drive
Fan to the desired target setting.
• ‘1’ - The RPM-based Fan Speed Control Algorithm cannot drive
Fan to the desired target setting at maximum drive.
4:2 RESERVED
DS00002022B-page 206
Type
Default
Reset
Event
RES
00b
-
R/WC
0b
VCC1_R
ESET
RES
000b
-
2016 Microchip Technology Inc.
CEC1302
Offset
11h
Bits
Description
Reset
Event
Type
Default
1 FAN_SPIN
The bit Indicates that the Spin up Routine for the Fan could not
detect a valid tachometer reading within its maximum time window.
• ‘0’ - The Spin up Routine for the Fan detected a valid tachometer reading within its maximum time window.
• ‘1’ - The Spin up Routine for the Fan could not detect a valid
tachometer reading within its maximum time window.
R/WC
0b
VCC1_R
ESET
0 FAN_STALL
The bit Indicates that the tachometer measurement on the Fan
detects a stalled fan.
• ‘0’ - Stalled fan not detected.
• ‘1’ - Stalled fan not detected.
R/WC
0b
VCC1_R
ESET
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20.0
GENERAL PURPOSE SERIAL PERIPHERAL INTERFACE
20.1
Overview
The General Purpose Serial Peripheral Interface (GP-SPI) may be used to communicate with various peripheral
devices, e.g., EEPROMS, DACs, ADCs, that use a standard Serial Peripheral Interface.
Characteristics of the GP-SPI Controller include:
• 8-bit serial data transmitted and received simultaneously over two data pins in Full Duplex mode with options to
transmit and receive data serially on one data pin in Half Duplex (Bidirectional) mode.
• An internal programmable clock generator and clock polarity and phase controls allowing communication with various SPI peripherals with specific clocking requirements.
• SPI cycle completion that can be determined by status polling or interrupts.
• The ability to read data in on both SPDIN and SPDOUT in parallel. This allows this SPI Interface to support dual
data rate read accesses for emerging double rate SPI flashes
• Support of back-to-back reads and writes without clock stretching, provided the host can read and write the data
registers within one byte transaction time.
20.2
References
No references have been cited for this feature.
20.3
Terminology
No terminology for this block.
20.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 20-1:
I/O DIAGRAM OF BLOCK
General Purpose Serial
Peripheral Interface
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
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20.5
Signal Description
TABLE 20-1:
SIGNAL DESCRIPTION TABLE
Name
Note:
SPDIN
Input
SPDOUT
Input/Output
Description
Serial Data In pin
Serial Data Output pin. Switches to input when used in double-datarate mode
SPI_CLK
Output
SPI Clock output used to drive the SPCLK pin.
SPI_CS#
Output
SPI chip select
The SPI block signals that are shown in Table 20-1 are routed to the SPI pins as listed in Table 20-2.
TABLE 20-2:
20.6
Direction
SIGNAL TO PIN NAME LOOKUP TABLE
Block Name
Pin Name
SPDIN
SHD_MISO, PVT_MISO
SPDOUT
SHD_MOSI, PVT_MOSI
SPI_CLK
SHD_SCLK, PVT_SCLK
SPI_CS#
SHD_CS0#, PVT_CS0#
Host Interface
The registers defined for the General Purpose Serial Peripheral Interface are accessible by the various hosts as indicated in Section 20.12, "EC-Only Registers".
20.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
20.7.1
POWER DOMAINS
TABLE 20-3:
POWER SOURCES
Name
VCC1
20.7.2
The logic and registers implemented in this block are powered by this
power well.
CLOCK INPUTS
TABLE 20-4:
CLOCK INPUTS
Name
20.7.3
Description
Description
48 MHz Ring Oscillator
This is a clock source for the SPI clock generator.
2MHz
This is a clock source for the SPI clock generator.
RESETS
TABLE 20-5:
RESET SIGNALS
Name
Description
VCC1_RESET
This signal resets all the registers and logic in this block to their default
state.
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20.8
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 20-6:
EC INTERRUPTS
Source
Description
TXBE_STS
Transmit buffer empty status (TXBE), in the SPI Status Register, sent as
an interrupt request to the Interrupt Aggregator.
RXBF_STS
Receive buffer full status (RXBF), in the SPI Status Register, sent as an
interrupt request to the Interrupt Aggregator.
These status bits are also connected respectively to the DMA Controller’s SPI Controller TX and RX requests signals.
20.9
Low Power Modes
The GP-SPI Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
20.10 Description
The Serial Peripheral Interface (SPI) block is a master SPI block used to communicate with external SPI devices. The
SPI master is responsible for generating the SPI clock and is designed to operate in Full Duplex, Half Duplex, and Dual
modes of operation. The clock source may be programmed to operated at various clock speeds. The data is transmitted serially via 8-bit transmit and receive shift registers. Communication with SPI peripherals that require transactions
of varying lengths can be achieved with multiple 8-bit cycles.
This block has many configuration options: The data may be transmitted and received either MSbit or LSbit first; The
SPI Clock Polarity may be either active high or active low; Data may be sampled or presented on either the rising of
falling edge of the clock (referred to as the transmit clock phase); and the SPI_CLK SPDOUT frequency may be programmed to a range of values as illustrated in Table 20-7, "SPI_CLK Frequencies". In addition to these many programmable options, this feature has several status bits that may be enabled to notify the host that data is being transmitted
or received.
20.10.1
INITIATING AN SPI TRANSACTION
All SPI transactions are initiated by a write to the TX_DATA register. No read or write operations can be initiated until
the Transmit Buffer is Empty, which is indicated by a one in the TXBE status bit.
If the transaction is a write operation, the host writes the TX_DATA register with the value to be transmitted. Writing the
TX_DATA register causes the TXBE status bit to be cleared, indicating that the value has been registered. If empty, the
SPI Core loads this TX_DATA value into an 8-bit transmit shift register and begins shifting the data out. Loading the
value into the shift register causes the TXBE status bit to be asserted, indicating to software that the next byte can be
written to the TX_DATA register.
If the transaction is a read operation, the host initiates a write to the TX_DATA register in the same manner as the write
operation. Unlike the transmit command, the host must clear the RXBF status bit by reading the RX_DATA register
before writing the TX_DATA register. This time, the host will be required to poll the RXBF status bit to determine when
the value in the RX_DATA register is valid.
Note 1: If the SPI interface is configured for Half Duplex mode, the host must still write a dummy byte to receive data.
2: Since RX and TX transactions are executed by the same sequence of transactions, data is always shifted
into the RX_DATA register. Therefore, every write operation causes data to be latched into the RX_DATA
register and the RXBF bit is set. This status bit should be cleared before initiating subsequent transactions.
The host utilizing this SPI core to transmit SPI Data must discard the unwanted receive bytes.
3: The length and order of data sent to and received from a SPI peripheral varies between peripheral devices.
The SPI must be properly configured and software-controlled to communicate with each device and determine whether SPIRD data is valid slave data.
The following diagrams show sample single byte and multi-byte SPI Transactions.
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FIGURE 20-2:
SINGLE BYTE SPI TX/RX TRANSACTIONS (FULL DUPLEX MODE)
Single SPI BYTE Transactions
MCLK
SPDOUT_Direction
TX_DATA
BYTE 0
Write TX_Data
TX_DATA Buffer Empty (TxBE)
Rx_DATA Buffer Full (RxBF)
Read RX_Data
BYTE 0
RX_DATA
Data Out Shift Register
7
6
5
4
3
2
1
0
Data In Shift Register
7
6
5
4
3
2
1
0
SPCLKO
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FIGURE 20-3:
MULTI-BYTE SPI TX/RX TRANSACTIONS (FULL DUPLEX MODE)
SPI BYTE Transactions
MCLK
SPDOUT_Direction
TX_DATA
BYTE
0
BYTE 1
BYTE 2
Write TX_Data
TX_DATA Buffer Empty (TxBE)
Rx_DATA Buffer Full (RxBF)
Read RX_Data
BYTE 1
BYTE 0
RX_DATA
BYT
Data Out Shift Register
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Data In Shift Register
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SPCLKO
The data may be configured to be transmitted MSB or LSB first. This is configured by the LSBF bit in the SPI Control
Register. The transmit data is shifted out on the edge as selected by the TCLKPH bit in the SPI Clock Control Register.
All received data can be sampled on a rising or falling SPI_CLK edge using the RCLKPH bit in the SPI Clock Control
Register This clock setting must be identical to the clocking requirements of the current SPI slave.
Note:
Common peripheral devices require a chip select signal to be asserted during a transaction. Chip selects
for SPI devices may be controlled by CEC1302 GPIO pins.
There are three types of transactions that can be implemented for transmitting and receiving the SPI data. They are Full
Duplex, Half Duplex, and Dual Mode. These modes are define in Section 20.10.3, "Types of SPI Transactions".
20.10.2
DMA MODE
Transmit and receive operations can use a DMA channel. Note that only one DMA channel may be enabled at a
time. Setting up the DMA Controller involves specifying the device (Flash GP-SPI), direction (transmit/receive), and
the start and end addresses of the DMA buffers in the closely couple memory. Please refer to the DMA Controller chapter for register programming information.
SPI transmit / DMA write: the GP-SPI block’s transmit empty (TxBE) status signal is used as a write request to the DMA
controller, which then fetches a byte from the DMA transmit buffer and writes it to the GP-SPI’s SPI TX Data Register
(SPITD). As content of the latter is transferred to the internal Tx shift register from which data is shifted out onto the SPI
bus bit by bit, the Tx Empty signal is again asserted, triggering the DMA fetch-and-write cycle. The process continues
until the end of the DMA buffer is reached - the DMA controller stops responding to an active Tx Empty until the buffer’s
address registers are reprogrammed.
SPI receive / DMA read: the AUTO_READ bit in the SPI Control Register must be set. The driver first writes (dummy
data) to the SPI TX Data Register (SPITD) to initiate the toggling of the SPI clock, enabling data to be shifted in. After
one byte is received, the Rx Full (RxBF) status signal, used as a read request to the DMA controller, is asserted. The
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DMA controller then reads the received byte from the GP-SPI’s SPI RX Data Register (SPIRD) and stores it in the DMA
receive buffer. With AUTO_READ set, this read clears both the RxBF and TxBE. Clearing TxBE causes (dummy) data
from the SPI TX Data Register (SPITD) to be transferred to the internal shift register, mimicking the effect of the aforementioned write to the SPI TX Data Register (SPITD) by the driver. SPI clock is toggled again to shift in the second read
byte. This process continues until the end of the DMA buffer is reached - the DMA controller stops responding to an
active Tx Empty until the buffer’s address registers are reprogrammed.
20.10.3
TYPES OF SPI TRANSACTIONS
The GP-SPI controller can be configured to operate in three modes: Full Duplex, Half Duplex, and Dual Mode.
20.10.3.1
Full Duplex
In Full Duplex Mode, serial data is transmitted and received simultaneously by the SPI master over the SPDOUT and
SPDIN pins. To enable Full Duplex Mode clear SPDIN Select.
When a transaction is completed in the full-duplex mode, the RX_DATA shift register always contains received data
(valid or not) from the last transaction.
20.10.3.2
Half Duplex
In Half Duplex Mode, serial data is transmitted and received sequentially over a single data line (referred to as the SPDOUT pin). To enable Half Duplex Mode set SPDIN Select to 01b. The direction of the SPDOUT signal is determined by
the BIOEN bit.
• To transmit data in half duplex mode set the BIOEN bit before writing the TX_DATA register.
• To receive data in half duplex mode clear the BIOEN bit before writing the TX_DATA register with a dummy byte.
Note:
20.10.3.3
The Software driver must properly drive the BIOEN bit and store received data depending on the transaction format of the specific slave device.
Dual Mode of Operation
In Dual Mode, serial data is transmitted sequentially from the SPDOUT pin and received in by the SPI master from the
SPDOUT and SPDIN pins. This essentially doubles the received data rate and is often available in SPI Flash devices.
To enable Dual Mode of operation the SPI core must be configured to receive data in path on the SPDIN1 and SPDIN2
inputs via SPDIN Select. The BIOEN bit determines if the SPI core is transmitting or receiving. The setting of this bit
determines the direction of the SPDOUT signal. The SPDIN Select bits are configuration bits that remain static for the
duration of a dual read command. The BIOEN bit must be toggled to indicate when the SPI core is transmitting and
receiving.
• To transmit data in dual mode set the BIOEN bit before writing the TX_DATA register.
• To receive data in dual mode clear the BIOEN bit before writing the TX_DATA register with a dummy byte. The
even bits (0,2,4,and 6) are received on the SPDOUT pin and the odd bits (1,3,5,and 7) are received on the SPDIN
pin. The hardware assembles these received bits into a single byte and loads them into the RX_DATA register
accordingly.
The following diagram illustrates a Dual Fast Read Command that is supported by some SPI Flash devices.
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FIGURE 20-4:
DUAL FAST READ FLASH COMMAND
MCLK
BIOEN
TX_DATA
Address
23:16
Comm
and
Address
7:0
Address
15:8
Byte 1
Dummy Byte
Write TX_Data
TX_DATA Buffer Empty (TxBE)
Rx_DATA Buffer Full (RxBF)
Read RX_Data
Address Byte
[16:8]
Address [23:16]
Command Byte
RX_DATA
Address Byte
[7:0]
Driven by Master
SPDOUT Pin
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SPDIN1
SPDIN2
7
6
5
4
3
2
1
0
SPCLKO
MCLK
BIOEN
Byte 2
TX_DATA
Byte 3
Byte 4
Write TX_Data
TX_DATA Buffer Empty (TxBE)
Rx_DATA Buffer Full (RxBF)
Read RX_Data
BYTE 1
Dummy Byte
RX_DATA
BYTE 2
BYTE 3
BYTE 4
Driven by Slave
SPDOUT Pin
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SPDIN1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SPDIN2
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SPCLKO
Note:
20.10.4
When the SPI core is used for flash commands, like the Dual Read command, the host discards the bytes
received during the command, address, and dummy byte portions of the transaction.
HOW BIOEN BIT CONTROLS DIRECTION OF SPDOUT BUFFER
When the SPI is configured for Half Duplex mode or Dual Mode the SPDOUT pin operates as a bi-directional signal.
The BIOEN bit is used to determine the direction of the SPDOUT buffer when a byte is transmitted. Internally, the BIOEN
bit is sampled to control the direction of the SPDOUT buffer when the TX_DATA value is loaded into the transmit shift
register. The direction of the buffer is never changed while a byte is being transmitted.
Since the TX_DATA register may be written while a byte is being shifted out on the SPDOUT pin, the BIOEN bit does
not directly control the direction of the SPDOUT buffer. An internal DIRECTION bit, which is a latched version of the
BIOEN bit determines the direction of the SPDOUT buffer. The following list summarizes when the BIOEN bit is sampled.
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• The DIRECTION bit is equal to the BIOEN bit when data is not being shifted out (i.e., SPI interface is idle).
• The hardware samples the BIOEN bit when it is shifting out the last bit of a byte to determine if the buffer needs to
be turned around for the next byte.
• The BIOEN bit is also sampled any time the value in the TX_DATA register is loaded into the shift register to be
transmitted.
If a TAR (Turn-around time) is required between transmitting and receiving bytes on the SPDOUT signal, software
should allow all the bytes to be transmitted before changing the buffer to an input and then load the TX_DATA register
to begin receiving bytes. If TAR greater than zero is required, software must wait for the transmission in one direction
to complete before writing the TX_DATA register to start sending/receiving in the opposite direction. This allows the SPI
block to operate the same as legacy Microchip SPI devices.
20.10.5
CONFIGURING THE SPI CLOCK GENERATOR
The SPI controller generates the SPI_CLK signal to the external SPI device. The frequency of the SPI_CLK signal is
determined by one of two clock sources and the Preload value of the clock generator down counter. The clock generator
toggles the SPI_CLK output every time the counter underflows, while data is being transmitted.
Note:
When the SPI interface is in the idle state and data is not being transmitted, the SPI_CLK signal stops in
the inactive state as determined by the configuration bits.
The clock source to the down counter is determined by Bit CLKSRC. Either the main system clock or the 2MHz clock
can be used to decrement the down counter in the clock generator logic.
The SPI_CLK frequency is determined by the following formula:
1
SPI_CLK_FREQ= --- REFERENCE_CLOCK PRELOAD
2
The REFERENCE_CLOCK frequency is selected by CLKSRC in the SPI Clock Control Register and PRELOAD is the
PRELOAD field of the SPI Clock Generator Register. The frequency can be either the 48 MHz Ring Oscillator clock or
a 2MHz clock. When the PRELOAD value is 0, the REFERENCE_CLOCK is always the 48 MHz Ring Oscillator clock
and the CLKSRC bit is ignored.
Sample SPI Clock frequencies are shown in the following table:
TABLE 20-7:
20.10.6
SPI_CLK FREQUENCIES
Clock Source
PRELOAD
SPI_CLK Frequency
Don’t Care
0
48MHz
48MHz
1
24MHz
48MHz
2
12MHz
(default)
48MHz
3
6MHz
48MHz
63
381KHz
2MHz
1
1MHz
2MHz
2
500KHz
2MHz
3
333KHz
2MHz
63
15.9KHz
CONFIGURING SPI MODE
In practice, there are four modes of operation that define when data should be latched. These four modes are the combinations of the SPI_CLK polarity and phase.
The output of the clock generator may be inverted to create an active high or active low clock pulse. This is used to
determine the inactive state of the SPI_CLK signal and is used for determining the first edge for shifting the data. The
polarity is selected by CLKPOL in the SPI Clock Control Register.
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The phase of the clock is selected independently for receiving data and transmitting data. The receive phase is determine by RCLKPH and the transmit phase is determine by TCLKPH in the SPI Clock Control Register.
The following table summarizes the effect of CLKPOL, RCLKPH and TCLKPH.
TABLE 20-8:
SPI DATA AND CLOCK BEHAVIOR
CLKPOL
RCLKPH
TCLKPH
Behavior
0
0
0
Inactive state is low. First edge is rising edge.
Data is sampled on the rising edge.
Data is transmitted on the falling edge.
Data is valid before the first rising edge.
0
0
1
Inactive state is low. First edge is rising edge.
Data is sampled on the rising edge.
Data is transmitted on the rising edge.
0
1
0
Inactive state is low. First edge is rising edge.
Data is sampled on the falling edge.
Data is transmitted on the falling edge.
Data is valid before the first rising edge.
0
1
1
Inactive state is low. First edge is rising edge.
Data is sampled on the falling edge.
Data is transmitted on the rising edge.
1
0
0
Inactive state is high. First edge is falling edge.
Data is sampled on the falling edge.
Data is transmitted on the rising edge.
Data is valid before the first falling edge.
1
0
1
Inactive state is high. First edge is falling edge.
Data is sampled on the falling edge.
Data is transmitted on the falling edge.
1
1
0
Inactive state is high. First edge is falling edge.
Data is sampled on the rising edge.
Data is transmitted on the rising edge.
Data is valid before the first falling edge.
1
1
1
Inactive state is high. First edge is falling edge.
Data is sampled on the rising edge.
Data is transmitted on the falling edge.
20.11 SPI Examples
20.11.1
20.11.1.1
FULL DUPLEX MODE TRANSFER EXAMPLES
Read Only
The slave device used in this example is a MAXIM MAX1080 10 bit, 8 channel ADC:
• The SPI block is activated by setting the enable bit in SPIAR - SPI Enable Register
• The SPIMODE bit is de-asserted '0' to enable the SPI interface in Full Duplex mode.
• The CLKPOL and TCLKPH bits are de-asserted '0', and RCLKPH is asserted '1' to match the clocking requirements of the slave device.
• The LSBF bit is de-asserted '0' to indicate that the slave expects data in MSB-first order.
• Assert CS# using a GPIO pin.
• Write a valid command word (as specified by the slave device) to the SPITD - SPI TX_Data Register with TXFE
asserted '1'. The SPI master automatically clears the TXFE bit indicating the byte has been put in the TX buffer. If
the shift register is empty the TX_DATA byte is loaded into the shift register and the SPI master reasserts the
TXFE bit. Once the data is in the shift register the SPI master begins shifting the data value onto the SPDOUT pin
and drives the SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
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• A dummy 8 bit data value (any value) is written to the TX_DATA register. The SPI master automatically clears the
TXFE bit, but does not begin shifting the dummy data value onto the SPDOUT pin. This byte will remain in the
TX_DATA register until the TX shift register is empty.
• After 8 SPI_CLK pulses from the first transmit bytes:
- The first SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The
data now contained in SPIRD - SPI RX_Data Register is invalid since the last cycle was initiated solely to
transmit command data to the slave. This particular slave device drives '0' on the SPDIN pin to the master
while it is accepting command data. This SPIRD data is ignored.
- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register and
loads it into the TX shift register. Loading the shift register automatically asserts the TXFE bit, begins shifting
the dummy data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
• The final SPI cycle is initiated when another dummy 8 bit data value (any value) is written to the TX_DATA register. Note that this value may be another dummy value or it can be a new 8 bit command to be sent to the ADC.
The new command will be transmitted while the final data from the last command is received simultaneously. This
overlap allows ADC data to be read every 16 SPCLK cycles after the initial 24 clock cycle.The SPI master automatically clears the TXFE bit, but does not begin shifting the dummy data value onto the SPDOUT pin. This byte
will remain in the TX_DATA register until the TX shift register is empty.
• After 8 SPI_CLK pulses, the second SPI cycle is complete:
- The first SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The
data now contained in SPIRD - SPI RX_Data Register is the first half of a valid 16 bit ADC value. SPIRD is
read and stored.
- Once the second SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register and
loads it into the TX shift register. Loading the shift register automatically asserts the TXFE bit, begins shifting
the data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled on
each clock.
• After 8 SPI_CLK pulses, the final SPI cycle is complete, TXBF is asserted '1', and the SPINT interrupt is asserted
(if enabled). The data now contained in SPIRD - SPI RX_Data Register is the second half of a valid 16 bit ADC
value. SPIRD is read and stored.
• If a command was overlapped with the received data in the final cycle, #CS should remain asserted and the SPI
master will initiate another SPI cycle. If no new command was sent, #CS is released and the SPI is idle.
20.11.1.2
Read/Write
The slave device used in this example is a Fairchild NS25C640 FM25C640 64K Bit Serial EEPROM. The following subsections describe the read and write sequences.
Read
• The SPI block is activated by setting the enable bit in SPIAR - SPI Enable Register
• The SPIMODE bit is de-asserted '0' to enable the SPI interface in Full Duplex mode.
• The CLKPOL, TCLKPH and RCLKPH bits are de-asserted '0' to match the clocking requirements of the slave
device.
• The LSBF bit is de-asserted '0' to indicate that the slave expects data in MSB-first order.
• Assert CS# low using a GPIO pin.
• Write a valid command word (as specified by the slave device) to the SPITD - SPI TX_Data Register with TXFE
asserted '1'. The SPI master automatically clears the TXFE bit indicating the byte has been put in the TX buffer. If
the shift register is empty the TX_DATA byte is loaded into the shift register and the SPI master reasserts the
TXFE bit. Once the data is in the shift register the SPI master begins shifting the data value onto the SPDOUT pin
and drives the SPI_CLK pin. Data on the SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
• Next, EEPROM address A15-A8 is written to the TX_DATA register. The SPI master automatically clears the
TXFE bit, but does not begin shifting the dummy data value onto the SPDOUT pin. This byte will remain in the
TX_DATA register until the TX shift register is empty.
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• After 8 SPI_CLK pulses from the first transmit byte (Command Byte transmitted):
- The first SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The
data now contained in SPIRD - SPI RX_Data Register is invalid since the last cycle was initiated solely to
transmit command data to the slave. This particular slave device tri-states the SPDIN pin to the master while
it is accepting command data. This SPIRD data is ignored.
Note:
•
•
•
•
•
•
•
•
•
•
External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register
(EEPROM address A15-A8) and loads it into the TX shift register. Loading the shift register automatically
asserts the TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK
pin. Data on the SPDIN pin is also sampled on each clock. Note: The particular slave device ignores address
A15-A13.
Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
Next, EEPROM address A7-A0 is written to the TX_DATA register. The SPI master automatically clears the TXFE
bit, but does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register
until the TX shift register is empty.
After 8 SPI_CLK pulses from the second transmit byte (Address Byte (MSB) transmitted):
- EEPROM address A15-A8 has been transmitted to the slave completing the second SPI cycle. Once again,
the RXBF bit is asserted '1' and the SPINT interrupt is asserted, if enabled. The data now contained in SPIRD
- SPI RX_Data Register is invalid since the last cycle was initiated solely to transmit address data to the
slave.
- Once the second SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register
(EEPROM address A7-A0) and loads it into the TX shift register. Loading the shift register automatically
asserts the TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPCLK pin.
Data on the SPDIN pin is also sampled on each clock.
Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
Next, a dummy byte is written to the TX_DATA register. The SPI master automatically clears the TXFE bit, but
does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register until
the TX shift register is empty.
After 8 SPI_CLK pulses, the third SPI cycle is complete (Address Byte (LSB) transmitted):
- EEPROM address A7-A0 has been transmitted to the slave completing the third SPI cycle. Once again, the
RXBF bit is asserted '1' and the SPINT interrupt is asserted, if enabled. The data now contained in SPIRD SPI RX_Data Register is invalid since the last cycle was initiated solely to transmit address data to the slave.
- Once the third SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register
(dummy byte) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE
bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the
SPDIN pin is also sampled on each clock.
Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
If only one receive byte is required, the host would not write any more value to the TX_DATA register until this
transaction completes. If more than one byte of data is to be received, another dummy byte would be written to the
TX_DATA register (one dummy byte per receive byte is required). The SPI master automatically clears the TXFE
bit when the TX_DATA register is written, but does not begin shifting this data value onto the SPDOUT pin. This
byte will remain in the TX_DATA register until the TX shift register is empty.
After 8 SPI_CLK pulses, the fourth SPI cycle is complete (First Data Byte received):
- The dummy byte has been transmitted to the slave completing the fourth SPI cycle. Once again, the RXBF bit
is asserted '1' and the SPINT interrupt is asserted, if enabled. Unlike the command and address phases, the
data now contained in SPIRD - SPI RX_Data Register is the 8-bit EEPROM data since the last cycle was initiated to receive data from the slave.
- Once the fourth SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (if
any) and loads it into the TX shift register. This process will be repeated until all the desired data is received.
The host software will read and store the EEPROM data value in SPIRD - SPI RX_Data Register.
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• If no more data needs to be received by the master, CS# is released and the SPI is idle. Otherwise, master continues reading the data by writing a dummy value to the TX_DATA register after every 8 SPI_CLK cycles.
Write
• The SPI block is activated by setting the enable bit in SPIAR - SPI Enable Register
• The SPIMODE bit is de-asserted '0' to enable the SPI interface in Full Duplex mode.
• The CLKPOL, TCLKPH and RCLKPH bits are de-asserted '0' to match the clocking requirements of the slave
device.
• The LSBF bit is de-asserted '0' to indicate that the slave expects data in MSB-first order.
• Assert WR# high using a GPIO pin.
• Assert CS# low using a GPIO pin.
• Write a valid command word (as specified by the slave device) to the SPITD - SPI TX_Data Register with TXFE
asserted '1'. The SPI master automatically clears the TXFE bit indicating the byte has been put in the TX buffer. If
the shift register is empty the TX_DATA byte is loaded into the shift register and the SPI master reasserts the
TXFE bit. Once the data is in the shift register the SPI master begins shifting the data value onto the SPDOUT pin
and drives the SPI_CLK pin. Data on the SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
• Next, EEPROM address A15-A8 is written to the TX_DATA register. The SPI master automatically clears the
TXFE bit, but does not begin shifting the dummy data value onto the SPDOUT pin. This byte will remain in the
TX_DATA register until the TX shift register is empty.
• After 8 SPI_CLK pulses from the first transmit byte (Command Byte transmitted):
- The first SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The
data now contained in SPIRD - SPI RX_Data Register is invalid since the last cycle was initiated solely to
transmit command data to the slave. This particular slave device tri-states the SPDIN pin to the master while
it is accepting command data. This SPIRD data is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
•
•
•
•
•
•
- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register
(EEPROM address A15-A8) and loads it into the TX shift register. Loading the shift register automatically
asserts the TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK
pin. Data on the SPDIN pin is also sampled on each clock. Note: The particular slave device ignores address
A15-A13.
Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
Next, EEPROM address A7-A0 is written to the TX_DATA register. The SPI master automatically clears the TXFE
bit, but does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register
until the TX shift register is empty.
After 8 SPI_CLK pulses from the second transmit byte (Address Byte (MSB) transmitted):
- EEPROM address A15-A8 has been transmitted to the slave completing the second SPI cycle. Once again,
the RXBF bit is asserted '1' and the SPINT interrupt is asserted, if enabled. The data now contained in SPIRD
- SPI RX_Data Register is invalid since the last cycle was initiated solely to transmit address data to the
slave.
- Once the second SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register
(EEPROM address A7-A0) and loads it into the TX shift register. Loading the shift register automatically
asserts the TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPCLK pin.
Data on the SPDIN pin is also sampled on each clock.
Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
Next, a data byte (D7:D0) is written to the TX_DATA register. The SPI master automatically clears the TXFE bit,
but does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register
until the TX shift register is empty.
After 8 SPI_CLK pulses, the third SPI cycle is complete (Address Byte (LSB) transmitted):
- EEPROM address A7-A0 has been transmitted to the slave completing the third SPI cycle. Once again, the
RXBF bit is asserted '1' and the SPINT interrupt is asserted, if enabled. The data now contained in SPIRD -
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•
•
•
•
SPI RX_Data Register is invalid since the last cycle was initiated solely to transmit address data to the slave.
- Once the third SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (data
byte D7:D0) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE
bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the
SPDIN pin is also sampled on each clock.
Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
If only one data byte is to be written, the host would not write any more values to the TX_DATA register until this
transaction completes. If more than one byte of data is to be written, another data byte would be written to the
TX_DATA register. The SPI master automatically clears the TXFE bit when the TX_DATA register is written, but
does not begin shifting this data value onto the SPDOUT pin. This byte will remain in the TX_DATA register until
the TX shift register is empty.
After 8 SPI_CLK pulses, the fourth SPI cycle is complete (First Data Byte transmitted):
- The data byte has been transmitted to the slave completing the fourth SPI cycle. Once again, the RXBF bit is
asserted '1' and the SPINT interrupt is asserted, if enabled. Like the command and address phases, the data
now contained in SPIRD - SPI RX_Data Register is invalid since the last cycle was initiated to transmit data to
the slave.
- Once the fourth SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (if
any) and loads it into the TX shift register. This process will be repeated until all the desired data is transmitted.
If no more data needs to be transmitted by the master, CS# and WR# are released and the SPI is idle.
20.11.2
HALF DUPLEX (BIDIRECTIONAL MODE) TRANSFER EXAMPLE
The slave device used in this example is a National LM74 12 bit (plus sign) temperature sensor.
• The SPI block is activated by setting the enable bit in SPIAR - SPI Enable Register
• The SPIMODE bit is asserted '1' to enable the SPI interface in Half Duplex mode.
• The CLKPOL, TCLKPH and RCLKPH bits are de-asserted '0' to match the clocking requirements of the slave
device.
• The LSBF bit is de-asserted '0' to indicate that the slave expects data in MSB-first order.
• BIOEN is asserted '0' to indicate that the first data in the transaction is to be received from the slave.
• Assert CS# using a GPIO pin.
//Receive 16-bit Temperature Reading
• Write a dummy command byte (as specified by the slave device) to the SPITD - SPI TX_Data Register with TXFE
asserted '1'. The SPI master automatically clears the TXFE bit indicating the byte has been put in the TX buffer. If
the shift register is empty the TX_DATA byte is loaded into the shift register and the SPI master reasserts the
TXFE bit. Once the data is in the shift register the SPI master begins shifting the data value onto the SPDOUT pin
and drives the SPI_CLK pin. This data is lost because the output buffer is disabled. Data on the SPDIN pin is sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
• Next, another dummy byte is written to the TX_DATA register. The SPI master automatically clears the TXFE bit,
but does not begin shifting the dummy data value onto the SPDOUT pin. This byte will remain in the TX_DATA
register until the TX shift register is empty.
• After 8 SPI_CLK pulses from the first receive byte
- The first SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The
data now contained in SPIRD - SPI RX_Data Register is the first half of the 16 bit word containing the temperature data.
- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register
(dummy byte 2) and loads it into the TX shift register. Loading the shift register automatically asserts the
TXFE bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK pin. Data on
the SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
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//Transmit next reading command
• BIOEN is asserted '1' to indicate that data will now be driven by the master.
• Next, a command byte is written to the TX_DATA register. This value is the first half of a 16 bit command to be
sent to temperature sensor peripheral. The SPI master automatically clears the TXFE bit, but does not begin shifting the command data value onto the SPDOUT pin. This byte will remain in the TX_DATA register until the TX shift
register is empty. This data will be transmitted because the output buffer is enabled. Data on the SPDIN pin is
sampled on each clock.
• After 8 SPI_CLK pulses from the second receive byte:
- The second SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled.
The data now contained in SPIRD - SPI RX_Data Register is the second half of the 16 bit word containing the
temperature data.
- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (command byte 1) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE
bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK pin. Data on the
SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to receive its next byte. Before writing the next TX_DATA
value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
• Next, the second command byte is written to the TX_DATA register. The SPI master automatically clears the
TXFE bit, but does not begin shifting the command data value onto the SPDOUT pin. This byte will remain in the
TX_DATA register until the TX shift register is empty.
• After 8 SPI_CLK pulses from the first transmit byte:
- The third SPI cycle is complete, RXBF bit is asserted '1', and the SPINT interrupt is asserted, if enabled. The
data now contained in SPIRD - SPI RX_Data Register is invalid, since this command was used to transmit the
first command byte to the SPI slave.
- Once the first SPI cycle is completed, the SPI master takes the pending data in the TX_DATA register (command byte 2) and loads it into the TX shift register. Loading the shift register automatically asserts the TXFE
bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the SPI_CLK pin. Data on the
SPDIN pin is also sampled on each clock.
• Once the TXFE bit is asserted the SPI Master is ready to transmit or receive its next byte. Before writing the next
TX_DATA value, software must clear the RXBF status bit by reading the SPIRD - SPI RX_Data Register.
• Since no more data needs to be transmitted, the host software will wait for the RXBF status bit to be asserted indicating the second command byte was transmitted successfully.
• CS# is de-asserted.
20.12 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the General Purpose Serial
Peripheral Interface. The addresses of each register listed in this table are defined as a relative offset to the host “Base
Address” defined in the EC-Only Register Base Address Table.
TABLE 20-9:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address
0
EC
32-bit internal
address space
4000_9400h
1
EC
General Purpose Serial
Peripheral Interface
(GP-SPI)
32-bit internal
4000_9480h
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
Note:
The Shared SPI controller is instance 0 and the Private SPI is instance 1 of the General Purpose Serial
Peripheral Interface (GP-SPI) block.
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TABLE 20-10: EC-ONLY REGISTER SUMMARY
Offset
Register Name
0h
SPI Enable Register
4h
SPI Control Register
8h
SPI Status Register
Ch
SPI TX_Data Register
10h
SPI RX_Data Register
14h
SPI Clock Control Register
18h
SPI Clock Generator Register
20.12.1
SPI ENABLE REGISTER
Offset
00h
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
5 AUTO_READ
Auto Read Enable.
1=A read of the SPI RX_DATA Register will clear both the RXBF status bit and the TXBE status bit
0=A read of the SPI RX_DATA Register will clear the RXBF status bit.
The TXBE status bit will not be modified
R/W
0h
VCC1_R
ESET
4 SOFT_RESET
Soft Reset is a self-clearing bit. Writing zero to this bit has no effect.
Writing a one to this bit resets the entire SPI Interface, including all
counters and registers back to their initial state.
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
Bits
Description
31:1 Reserved
0 ENABLE
1=Enabled. The device is fully operational
0=Disabled. Clocks are gated to conserve power and the SPDOUT
and SPI_CLK signals are set to their inactive state
20.12.2
SPI CONTROL REGISTER
Offset
00h
Bits
Description
31:7 Reserved
6 CE
SPI Chip Select Enable.
1= SPI_CS# output signal is asserted, i.e., driven to logic ‘0’
0= SPI_CS# output signal is deasserted, i.e., driven to logic ‘1’
3:2 SPDIN_SELECT
The SPDIN Select which SPI input signals are enabled when the
BIOEN bit is configured as an input.
1xb=SPDIN1 and SPDIN2. Select this option for Dual Mode
01b=SPDIN2 only. Select this option for Half Duplex
00b=SPDIN1 only. Select this option for Full Duplex
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Offset
00h
Bits
Description
1 BIOEN
Bidirectional Output Enable control. When the SPI is configured for
Half Duplex mode or Dual Mode the SPDOUT pin operates as a bidirectional signal. The BIOEN bit is used by the internal DIRECTION
bit to control the direction of the SPDOUT buffers. The direction of
the buffer is never changed while a byte is being transmitted.
Reset
Event
Type
Default
R/W
1h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
Type
Default
1=The SPDOUT_Direction signal configures the SPDOUT signal as
an output.
0=The SPDOUT_Direction signal configures the SPDOUT signal as
an input.
See Section 20.10.4, "How BIOEN Bit Controls Direction of SPDOUT Buffer" for details on the use of BIOEN.
0 LSBF
Least Significant Bit First
1= The data is transferred in LSB-first order.
0= The data is transferred in MSB-first order. (default)
20.12.3
Offset
SPI STATUS REGISTER
08h
Bits
Description
31:3 Reserved
Reset
Event
R
-
-
2 ACTIVE
R
0h
VCC1_R
ESET
1 RXBF
Receive Data Buffer Full status. When this bit is ‘1’ the Rx_Data buffer is full. Reading the SPI RX_Data Register clears this bit. This signal may be used to generate a SPI_RX interrupt to the EC.
R
0h
VCC1_R
ESET
R
1h
VCC1_R
ESET
1=RX_Data buffer is full
0=RX_Data buffer is not full
0 TXBE
Transmit Data Buffer Empty status. When this bit is ‘1’ the Tx_Data
buffer is empty. Writing the SPI TX_Data Register clears this bit. This
signal may be used to generate a SPI_TX interrupt to the EC.
1=TX_Data buffer is empty
0=TX_Data buffer is not empty
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20.12.4
SPI TX_DATA REGISTER
Offset
00h
Bits
Description
31:8 Reserved
7:0 TX_DATA
A write to this register when the Tx_Data buffer is empty (TXBE in
the SPI Status Register is ‘1’) initiates a SPI transaction. The byte
written to this register will be loaded into the shift register and the
TXBE flag will be asserted. This indicates that the next byte can be
written into the TX_DATA register. This byte will remain in the TX_DATA register until the SPI core has finished shifting out the previous byte. Once the shift register is empty, the hardware will load the
pending byte into the shift register and once again assert the TxBE
bit.
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
The TX_DATA register must not be written when the TXBE bit is
zero. Writing this register may overwrite the transmit data before it is
loaded into the shift register.
20.12.5
SPI RX_DATA REGISTER
Offset
00h
Bits
Description
31:8 Reserved
7:0 RX_DATA
This register is used to read the value returned by the external SPI
device. At the end of a byte transfer the RX_DATA register contains
serial input data (valid or not) from the last transaction and the RXBF
bit is set to one. This status bit indicates that the RX_DATA register
has been loaded with a the serial input data. The RX_DATA register
should not be read before the RXBF bit is set.
The RX_DATA register must be read, clearing the RXBF status bit
before writing the TX_DATA register. The data in the receive shift
register is only loaded into the RX_DATA register when this bit is
cleared. If a data byte is pending in the receive shift register the
value will be loaded immediately into the RX_DATA register and the
RXBF status flag will be asserted. Software should read the RX_DATA register twice before starting a new transaction to make sure
the RX_DATA buffer and shift register are both empty.
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20.12.6
SPI CLOCK CONTROL REGISTER
This register should not be changed during an active SPI transaction.
Offset
00h
Bits
Description
31:5 Reserved
4 CLKSRC
Clock Source for the SPI Clock Generator. This bit should not be
changed during a SPI transaction. When the field PRELOAD in the
SPI Clock Generator Register is 0, this bit is ignored and the Clock
Source is always the main system clock (the equivalent of setting
this bit to ‘0’).
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
1=2MHz
0=48 MHz Ring Oscillator
3 Reserved
2 CLKPOL
SPI Clock Polarity.
R
-
-
R/W
0h
VCC1_R
ESET
R/W
1h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
1=The SPI_CLK signal is high when the interface is idle and the first
clock edge is a falling edge
0=The SPI_CLK is low when the interface is idle and the first clock
edge is a rising edge
1 RCLKPH
Receive Clock Phase, the SPI_CLK edge on which the master will
sample data. The receive clock phase is not affected by the SPI
Clock Polarity.
1=Valid data on SPDIN signal is expected after the first SPI_CLK
edge. This data is sampled on the second and following even
SPI_CLK edges (i.e., sample data on falling edge)
0=Valid data is expected on the SPDIN signal on the first SPI_CLK
edge. This data is sampled on the first and following odd SPI_CLK edges (i.e., sample data on rising edge)
0 TCLKPH
Transmit Clock Phase, the SPCLK edge on which the master will
clock data out. The transmit clock phase is not affected by the SPI
Clock Polarity.
1=Valid data is clocked out on the first SPI_CLK edge on SPDOUT
signal. The slave device should sample this data on the second
and following even SPI_CLK edges (i.e., sample data on falling
edge)
0=Valid data is clocked out on the SPDOUT signal prior to the first
SPI_CLK edge. The slave device should sample this data on the
first and following odd SPI_CLK edges (i.e., sample data on rising edge)
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20.12.7
SPI CLOCK GENERATOR REGISTER
Offset
00h
Bits
Description
31:16 Reserved
5:0 PRELOAD
SPI Clock Generator Preload value.
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Type
Default
Reset
Event
R
-
-
R/W
2h
VCC1_R
ESET
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21.0
BLINKING/BREATHING PWM
21.1
Introduction
LEDs are used in computer applications to communicate internal state information to a user through a minimal interface.
Typical applications will cause an LED to blink at different rates to convey different state information. For example, an
LED could be full on, full off, blinking at a rate of once a second, or blinking at a rate of once every four seconds, in order
to communicate four different states.
As an alternative to blinking, an LED can “breathe”, that is, oscillate between a bright state and a dim state in a continuous, or apparently continuous manner. The rate of breathing, or the level of brightness at the extremes of the oscillation
period, can be used to convey state information to the user that may be more informative, or at least more novel, than
traditional blinking.
The blinking/breathing hardware is implemented using a PWM. The PWM can be driven either by the 48 MHz clock or
by a 32.768 KHz clock input. When driven by the 48 MHz clock, the PWM can be used as a standard 8-bit PWM in order
to control a fan. When used to drive blinking or breathing LEDs, the 32.768 KHz clock source is used.
Features:
•
•
•
•
•
•
•
•
Each PWM independently configurable
Each PWM configurable for LED blinking and breathing output
Highly configurable breathing rate from 60ms to 1min
Non-linear brightness curves approximated with 8 piece wise-linear segments
All LED PWMs can be synchronized
Each PWM configurable for 8-bit PWM support
Multiple clock rates
Configurable Watchdog Timer
21.2
Interface
This block is designed to drive a pin on the pin interface and to be accessed internally via a registered host interface.
FIGURE 21-1:
I/O DIAGRAM OF BLOCK
Blinking/Breathing PWM
Host Interface
Signal Description
Clock Inputs
Resets
Interrupts
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21.3
Signal Description
TABLE 21-1:
SIGNAL DESCRIPTION
Name
Direction
PWM Output
Output
Description
Output of PWM
By default, the PWM pin is configured to be active high: when the
PWM is configured to be fully on, the pin is driving high. When the
PWM is configured to be fully off, the pin is low. If firmware requires
the Blinking/Breathing PWM to be active low, the Polarity bit in the
GPIO Pin Control Register associated with the PWM can be set to
1, which inverts the output polarity.
21.4
Host Interface
The blinking/breathing PWM block is accessed by a controller over the standard register interface.
21.5
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
21.5.1
POWER DOMAINS
TABLE 21-2:
POWER SOURCES
Name
VCC1
21.5.2
Description
Main power. The source of main power for the device is system
dependent.
CLOCK INPUTS
TABLE 21-3:
CLOCK INPUTS
Name
32KHz_Clk
48 MHz Ring Oscillator
21.5.3
Description
32.768 KHz clock
48 MHz clock
RESETS
TABLE 21-4:
RESET SIGNALS
Name
VCC1_RESET
21.6
Description
Block reset
Interrupts
Each PWM can generate an interrupt. The interrupt is asserted for one 48 MHz clock period whenever the PWM WDT
times out. The PWM WDT is described in Section 21.8.3.1, "PWM WDT," on page 232.
Note:
PWM_WDT[0], PWM_WDT[1], PWM_WDT[2], PWM_WDT[3] bits in the GIRQ17 and GIRQ18 registers
are the interrupt source bits for the three instances of the Blinking/Breathing PWM in the CEC1302.
TABLE 21-5:
EC INTERRUPTS
Source
PWM_WDT
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Description
PWM watchdog time out
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21.7
Low Power Mode
The Blinking/Breathing PWM may be put into a low power mode by the chip-level power, clocks, and reset (PCR)
circuitry. The low power mode is only applicable when the Blinking/Breathing PWM is operating in the General Purpose PWM mode. When the low speed clock mode is selected, the blinking/breathing function continues to operate,
even when the 48 MHz clock is stopped. Low power mode behavior is summarized in the following table:
TABLE 21-6:
LOW POWER MODE BEHAVIOR
CLOCK_S
OURCE
CONTROL
Mode
Low Power
Mode
X
‘00’b
PWM ‘OFF’
Yes
X
‘01’b
Breathing
Yes
1
‘10’b
General Purpose PWM
No
48 MHz clock is required,
even when a sleep command to the block is
asserted.
0
‘10’b
Blinking
Yes
X
‘11’b
PWM ‘ON’
Yes
32.768 KHz clock is
required.
Note:
21.8
Description
32.768 KHz clock is
required.
In order for the CEC1302 to enter its.heavy and deep sleep states, the SLEEP_ENABLE input for all Blinking/Breathing PWM instances must be asserted, even if the PWMs are configured to use the low speed
clock.
Description
21.8.1
BREATHING
If an LED blinks rapidly enough, the eye will interpret the light as reduced brightness, rather than a blinking pattern.
Therefore, if the blinking period is short enough, modifying the duty cycle will set the apparent brightness, rather than a
blinking rate. At a blinking rate of 128Hz or greater, almost all people will perceive a continuous light source rather than
an intermittent pattern.
Because making an LED appear to breathe is an aesthetic effect, the breathing mechanism must be adjustable or customers may find the breathing effect unattractive. There are several variables that can affect breathing appearance, as
described below.
The following figure illustrates some of the variables in breathing:
FIGURE 21-2:
BREATHING LED EXAMPLE
Full on
Max Duty Cycle
Min Duty Cycle
Full off
RISING RAMP TIME
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FALLING RAMP TIME
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The breathing range of and LED can range between full on and full off, or in a range that falls within the full-on/full-off
range, as shown in this figure. The ramp time can be different in different applications. For example, if the ramp time
was 1 second, the LED would appear to breathe quickly. A time of 2 seconds would make the LED appear to breathe
more leisurely.
The breathing pattern can be clipped, as shown in the following figure, so that the breathing effect appears to pause at
its maximum and minimum brightnesses:
FIGURE 21-3:
CLIPPING EXAMPLE
Full on
Max Duty Cycle
Min Duty Cycle
Full off
The clipping periods at the two extremes can be adjusted independently, so that for example an LED can appear to
breathe (with a short delay at maximum brightness) followed by a longer “resting” period (with a long delay at minimum
brightness).
The brightness can also be changed in a non-linear fashion, as shown in the following figure:
FIGURE 21-4:
EXAMPLE OF A SEGMENTED CURVE
Full on
Full off
In this figure, the rise and fall curves are implemented in 4 linear segments and are the rise and fall periods are symmetric.
The breathing mode uses the 32.768 KHz clock for its time base.
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21.8.2
BLINKING
When configured for blinking, a subset of the hardware used in breathing is used to implement the blinking function. The
PWM (an 8-bit accumulator plus an 8-bit duty cycle register) drives the LED directly. The Duty Cycle register is programmed directly by the user, and not modified further. The PWM accumulator is configured as a simple 8-bit up counter.
The counter uses the 32.768 KHz clock, and is pre-scaled by the Delay counter, to slow the PWM down from the 128Hz
provided by directly running the PWM on the 32.768 KHz clock.
With the pre-scaler, the blink rate of the LED could be as fast as 128Hz (which, because it is blinking faster than the eye
can distinguish, would appear as a continuous level) to 0.03125Hz (that is, with a period of 7.8ms to 32 seconds). Any
duty cycle from 0% (0h) to 100% (FFh) can be configured, with an 8-bit precision. An LED with a duty cycle value of 0h
will be fully off, while an LED with a duty cycle value of FFh will be fully on.
In Blinking mode the PWM counter is always in 8-bit mode.
Table 21-7, "LED Blink Configuration Examples" shows some example blinking configurations:
TABLE 21-7:
LED BLINK CONFIGURATION EXAMPLES
Prescale
Duty Cycle
Blink Frequency
Blink
000h
00h
128Hz
full off
000h
FFh
128Hz
full on
001h
40h
64Hz
3.9ms on, 11.6ms off
003h
80h
32Hz
15.5ms on, 15.5ms off
07Fh
20h
1Hz
125ms on, 0.875s off
0BFh
16h
0.66Hz
125ms on, 1.375s off
0FFh
10h
0.5Hz
125ms on, 1.875s off
180h
0Bh
0.33Hz
125ms on, 2.875s off
1FFh
40h
0.25Hz
1s on, 3s off
The Blinking and General Purpose PWM modes share the hardware used in the breathing mode. The Prescale value
is derived from the LD field of the LED_DELAY register and the Duty Cycle is derived from the MIN field of the LED_LIMITS register.
TABLE 21-8:
BLINKING MODE CALCULATIONS
Parameter
Unit
Frequency
Hz
Equation
(32KHz_Clk frequency) /(PRESCALE + 1)/255
‘H’ Width
Seconds
(1/PERIOD) x (DutyCycle/255)
‘L’ Width
Seconds
(1/PERIOD) x (255 - DutyCycle)
21.8.3
GENERAL PURPOSE PWM
When used in the Blinking configuration with the 48 MHz Ring Oscillator, the LED module can be used as a generalpurpose programmable Pulse-Width Modulator with an 8-bit programmable pulse width. It can be used for fan speed
control, sound volume, etc. With the 48 MHz Ring Oscillator source, the PWM frequency can be configured in the range
shown in Table 21-9.
TABLE 21-9:
PWM CONFIGURATION EXAMPLES
Prescale
PWM Frequency
000h
187.5 KHz
001h
93.75 KHz
003h
46.875 KHz
006h
26.8 KHz
00Bh
15.625 KHz
07Fh
1.46 KHz
1FFh
366 Hz
FFFh
46 Hz
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TABLE 21-10: GENERAL PURPOSE PWM MODE CALCULATIONS
Parameter
Frequency
Unit
Hz
Equation
(48 MHz Ring Oscillator frequency) / (PRESCALE + 1) / 255
‘H’ Width
Seconds
(1/PERIOD) x (DutyCycle/255)
‘L’ Width
Seconds
(1/PERIOD) x (255 - DutyCycle)
21.8.3.1
PWM WDT
When the PWM is configured as a general-purpose PWM (in the Blinking configuration with the 48 MHz clock), the PWM
includes a Watch Dog Timer (WDT). The WDT consists of an internal 8-bit counter and an 8-bit reload value (the field
WDTLD in LED Configuration Register register). The internal counter is loaded with the reset value of WDTLD (14h, or
4 seconds) on system VCC1_RESET and loaded with the contents of WDTLD whenever either the LED Configuration
Register register is written or the MIN byte in the LED Limits Register register is written (the MIN byte controls the duty
cycle of the PWM).
Whenever the internal counter is non-zero, it is decremented by 1 for every tick of the 5 Hz clock. If the counter decrements from 1 to 0, a WDT Terminal Count causes an interrupt to be generated and reset sets the CONTROL bit in the
LED Configuration Register to 3h, which forces the PWM to be full on. No other PWM registers or fields are affected.
If the 5 Hz clock halts, the watchdog timer stops decrementing but retains its value, provided the device continues to be
powered. When the 5 Hz clock restarts, the watchdog counter will continue decrementing where it left off.
Setting the WDTLD bits to 0 disables the PWM WDT. Other sample values for WDTLD are:
01h = 200 ms
02h = 400 ms
03h = 600 ms
04h = 800 ms
…
14h = 4seconds
FFh = 51 seconds
21.9
Implementation
In addition to the registers described in Section 21.10, "EC-Only Registers", the PWM is implemented using a number
of components that are interconnected differently when configured for breathing operation and when configured for
blinking/PWM operation.
21.9.1
BREATHING CONFIGURATION
The PSIZE parameter can configure the PWM to one of three modes: 8-bit, 7-bit and 6-bit. The PERIOD CTR counts
ticks of its input clock. In 8-bit mode, it counts from 0 to 255 (that is, 256 steps), then repeats continuously. In this mode,
a full cycle takes 7.8ms (128Hz). In 7-bit mode it counts from 0 to 127 (128 steps), and a full cycle takes 3.9ms (256Hz).
In 6-bit mode it counts from 0 to 63 (64 steps) and a full cycle takes 1.95ms (512Hz).
The output of the LED circuit is asserted whenever the PERIOD CTR is less than the contents of the DUTY CYCLE
register. The appearance of breathing is created by modifying the contents of the DUTY CYCLE register in a continuous
manner. When the LED control is off the internal counters and registers are all reset to 0 (i.e. after a write setting the
RESET bit in the LED Configuration Register Register.) Once enabled, the DUTY CYCLE register is increased by an
amount determined by the LED_STEP register and at a rate determined by the DELAY counter. Once the duty cycle
reaches its maximum value (determined by the field MAX), the duty cycle is held constant for a period determined by
the field HD. Once the hold time is complete, the DUTY CYCLE register is decreased, again by an amount determined
by the LED_STEP register and at a rate determined by the DELAY counter. When the duty cycle then falls at or below
the minimum value (determined by the field MIN), the duty cycle is held constant for a period determined by the field
HD. Once the hold time is complete, the cycle repeats, with the duty cycle oscillating between MIN and MAX.
The rising and falling ramp times as shown in FIGURE 21-3: Clipping Example on page 230 can be either symmetric or
asymmetric depending on the setting of the SYMMETRY bit in the LED Configuration Register Register. In Symmetric
mode the rising and falling ramp rates have mirror symmetry; both rising and falling ramp rates use the same (all) 8
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segments fields in each of the following registers (see Table 21-11): the LED Update Stepsize Register register and the
LED Update Interval Register register. In Asymmetric mode the rising ramp rate uses 4 of the 8 segments fields and the
falling ramp rate uses the remaining 4 of the 8 segments fields (see Table 21-11).
The parameters MIN, MAX, HD, LD and the 8 fields in LED_STEP and LED_INT determine the brightness range of the
LED and the rate at which its brightness changes. See the descriptions of the fields in Section 21.10, "EC-Only Registers", as well as the examples in Section 21.9.3, "Breathing Examples" for information on how to set these fields.
TABLE 21-11:
SYMMETRIC BREATHING MODE REGISTER USAGE
Rising/ Falling
Ramp Times
in Figure 21-3,
"Clipping Example"
Duty Cycle
Segment Index
X
000xxxxxb
000b
STEP[0]/INT[0]
Bits[3:0]
X
001xxxxxb
001b
STEP[1]/INT[1]
Bits[7:4]
X
010xxxxxb
010b
STEP[2]/INT[2]
Bits[11:8]
X
011xxxxxb
011b
STEP[3]/INT[3]
Bits[15:12]
X
100xxxxxb
100b
STEP[4]/INT[4]
Bits[19:16]
X
101xxxxxb
101b
STEP[5]/INT[5]
Bits[23:20]
X
110xxxxxb
110b
STEP[6]/INT[6]
Bits[27:24]
X
111xxxxxb
111b
STEP[7]/INT[7]
Bits[31:28]
Note:
Symmetric Mode Register Fields Utilized
In Symmetric Mode the Segment_Index[2:0] = Duty Cycle Bits[7:5]
TABLE 21-12:
ASYMMETRIC BREATHING MODE REGISTER USAGE
Rising/ Falling
Ramp Times
in Figure 21-3,
"Clipping Example"
Duty Cycle
Segment Index
Rising
00xxxxxxb
000b
STEP[0]/INT[0]
Rising
01xxxxxxb
001b
STEP[1]/INT[1]
Bits[7:4]
Rising
10xxxxxxb
010b
STEP[2]/INT[2]
Bits[11:8]
Note:
21.9.2
Asymmetric Mode Register Fields Utilized
Bits[3:0]
Rising
11xxxxxxb
011b
STEP[3]/INT[3]
Bits[15:12]
falling
00xxxxxxb
100b
STEP[4]/INT[4]
Bits[19:16]
falling
01xxxxxxb
101b
STEP[5]/INT[5]
Bits[23:20]
falling
10xxxxxxb
110b
STEP[6]/INT[6]
Bits[27:24]
falling
11xxxxxxb
111b
STEP[7]/INT[7]
Bits[31:28]
In Asymmetric Mode the Segment_Index[2:0] is the bit concatenation of following: Segment_Index[2] =
(FALLING RAMP TIME in Figure 21-3, "Clipping Example") and Segment_Index[1:0] = Duty Cycle Bits[7:6].
BLINKING CONFIGURATION
The Delay counter and the PWM counter are the same as in the breathing configuration, except in this configuration
they are connected differently. The Delay counter is clocked on either the 32.768 KHz clock or the 48 MHz clock, rather
than the output of the PWM. The PWM counter is clocked by the zero output of the Delay counter, which functions as a
prescalar for the input clocks to the PWM. The Delay counter is reloaded from the LD field of the LED_DELAY register.
When the LD field is 0 the input clock is passed directly to the PWM counter without prescaling. In Blinking/PWM mode
the PWM counter is always 8-bit, and the PSIZE parameter has no effect.
The frequency of the PWM pulse waveform is determined by the formula:
f clock
f PWM = ----------------------------------------- 256 LD + 1
where fPWM is the frequency of the PWM, fclock is the frequency of the input clock (32.768 KHz clock or 48 MHz clock)
and LD is the contents of the LD field.
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Note:
At a duty cycle value of 00h (in the MIN register), the LED output is fully off. At a duty cycle value of 255h,
the LED output is fully on. Alternatively, In order to force the LED to be fully on, firmware can set the CONTROL field of the Configuration register to 3 (always on).
The other registers in the block do not affect the PWM or the LED output in Blinking/PWM mode.
21.9.3
BREATHING EXAMPLES
21.9.3.1
Linear LED brightness change
In this example, the brightness of the LED increases and diminishes in a linear fashion. The entire cycle takes 5 seconds. The rise time and fall time are 1.6 seconds, with a hold time at maximum brightness of 200ms and a hold time at
minimum brightness of 1.6 seconds. The LED brightness varies between full off and full on. The PWM size is set to 8bit, so the time unit for adjusting the PWM is approximately 8ms. The registers are configured as follows:
TABLE 21-13: LINEAR EXAMPLE CONFIGURATION
Field
PSIZE
Value
8-bit
MAX
255
MIN
0
HD
25 ticks (200ms)
LD
200 ticks (1.6s)
Duty cycle most
significant bits
000b
001b
010b
011b
100b
101b
110b
1110
LED_INT
8
8
8
8
8
8
8
8
LED_STEP
10
10
10
10
10
10
10
10
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FIGURE 21-5:
LINEAR BRIGHTNESS CURVE EXAMPLE
300
250
200
e
l
c
y
C150
y
t
u
D
100
50
0
0
0
2
3
0
4
6
0
6
9
0
8
2
1
0
0
6
1
0
2
9
1
0
4
2
2
0
6
5
2
0
8
8
2
0
0
2
3
0
2
5
3
0
4
8
3
0
6
1
4
0
8
4
4
0
0
8
4
0
2
1
5
0
4
4
5
0
6
7
5
0
8
0
6
0
0
4
6
0
2
7
6
0
4
0
7
0
6
3
7
0
8
6
7
0
0
0
8
0
2
3
8
0
4
6
8
0
6
9
8
0
8
2
9
0
0
6
9
0
2
9
9
0
4
2
0
1
0
6
5
0
1
0
8
8
0
1
Time in ms
21.9.3.2
Non-linear LED brightness change
In this example, the brightness of the LED increases and diminishes in a non-linear fashion. The brightness forms a
curve that is approximated by four piece wise-linear line segments. The entire cycle takes about 2.8 seconds. The rise
time and fall time are about 1 second, with a hold time at maximum brightness of 320ms and a hold time at minimum
brightness of 400ms. The LED brightness varies between full off and full on. The PWM size is set to 7-bit, so the time
unit for adjusting the PWM is approximately 4ms. The registers are configured as follows:
TABLE 21-14: NON-LINEAR EXAMPLE CONFIGURATION
Field
Value
PSIZE
7-bit
MAX
255 (effectively 127)
MIN
0
HD
80 ticks (320ms)
LD
100 ticks (400ms)
Duty cycle most
significant bits
000b
001b
010b
011b
100b
101b
110b
1110
LED_INT
2
3
6
6
9
9
16
16
LED_STEP
4
4
4
4
4
4
4
4
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The resulting curve is shown in the following figure:
FIGURE 21-6:
NON-LINEAR BRIGHTNESS CURVE EXAMPLE
300
250
200
e
l
c
y
C150
ty
u
D
100
50
0
0
0
6
1
0
2
3
0
8
4
0
4
6
0
0
8
0
6
9
0
2
1
1
0
8
2
1
0
4
4
1
0
0
6
1
0
6
7
1
0
2
9
1
0
8
0
2
0
4
2
2
0
0
4
2
0 0 0 0
6 2 8 4
5 7 8 0
2 2 2 3
Time in ms
0
0
2
3
0
6
3
3
0
2
5
3
0
8
6
3
0
4
8
3
0
0
0
4
0
6
1
4
0
2
3
4
0
8
4
4
0
4
6
4
0
0
8
4
0
6
9
4
0
2
1
5
0
8
2
5
0
4
4
5
21.10 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Blinking/Breathing PWM.
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
the EC-Only Register Base Address Table.
TABLE 21-15: EC-ONLY REGISTER BASE ADDRESS TABLE
Instance
Number
Host
Address Space
Base Address
Blinking/Breathing
PWM
0
EC
32-bit internal
address space
4000_B800h
Blinking/Breathing
PWM
1
EC
32-bit internal
address space
4000_B900h
Blinking/Breathing
PWM
2
EC
32-bit internal
address space
4000_BA00h
Block Instance
Blinking/Breathing
3
EC
32-bit internal
4000_BB00h
PWM
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
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TABLE 21-16: EC-ONLY REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
LED Configuration Register
04h
LED Limits Register
08h
LED Delay Register
0Ch
LED Update Stepsize Register
10h
LED Update Interval Register
In the following register definitions, a “PWM period” is defined by time the PWM counter goes from 000h to its maximum
value (FFh in 8-bit mode, FEh in 7-bit mode and FCh in 6-bit mode, as defined by the PSCALE field in register
LED_CFG). The end of a PWM period occurs when the PWM counter wraps from its maximum value to 0.
The registers in this block can be written 32-bits, 16-bits or 8-bits at a time. Writes to LED Configuration Register take
effect immediately. Writes to LED Limits Register are held in a holding register and only take effect only at the end of a
PWM period. The update takes place at the end of every period, even if only one byte of the register was updated. This
means that in blink/PWM mode, software can change the duty cycle with a single 8-bit write to the MIN field in the
LED_LIMIT register. Writes to LED Delay Register, LED Update Stepsize Register and LED Update Interval Register
also go initially into a holding register. The holding registers are copied to the operating registers at the end of a PWM
period only if the Enable Update bit in the LED Configuration Register is set to 1. If LED_CFG is 0, data in the holding
registers is retained but not copied to the operating registers when the PWM period expires. To change an LED breathing configuration, software should write these three registers with the desired values and then set LED_CFG to 1. This
mechanism ensures that all parameters affecting LED breathing will be updated consistently, even if the registers are
only written 8 bits at a time.
21.10.1
LED CONFIGURATION REGISTER
Offset
00h
Bits
Description
31:16 Reserved
Type
Default
Reset
Event
R
-
-
R/W
0b
VCC1_
RESET
15:8 WDT_RELOAD
The PWM Watchdog Timer counter reload value. On system reset, it
defaults to 14h, which corresponds to a 4 second Watchdog timeout
value.
R/W
14h
VCC1_
RESET
7 RESET
Writes of’1’ to this bit resets the PWM registers to their default values. This bit is self clearing.
Writes of ‘0’ to this bit have no effect.
W
0b
VCC1_
RESET
16 SYMMETRY
1=The rising and falling ramp times are in Asymmetric mode.
Table 21-12, "Asymmetric Breathing Mode Register Usage"
shows the application of the Stepsize and Interval registers to the
four segments of rising duty cycles and the four segments of falling duty cycles.
0=The rising and falling ramp times (as shown in Figure 21-2, "Breathing LED Example") are in Symmetric mode. Table 21-11, "Symmetric Breathing Mode Register Usage" shows the application of
the Stepsize and Interval registers to the 8 segments of both rising and falling duty cycles.
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Offset
00h
Bits
Description
6 ENABLE_UPDATE
This bit is set to 1 when written with a ‘1’. Writes of ‘0’ have no effect.
Hardware clears this bit to 0 when the breathing configuration registers are updated at the end of a PWM period. The current state of the
bit is readable any time.
Reset
Event
Type
Default
R/WS
0b
VCC1_
RESET
R/W
0b
VCC1_
RESET
R/W
0b
VCC1_
RESET
R/W
0b
VCC1_
RESET
R/W
00b
VCC1_
RESET
11b
WDT TC
This bit is used to enable consistent configuration of LED_DELAY,
LED_STEP and LED_INT. As long as this bit is 0, data written to
those three registers is retained in a holding register. When this bit is
1, data in the holding register are copied to the operating registers at
the end of a PWM period. When the copy completes, hardware
clears this bit to 0.
5:4 PWM_SIZE
This bit controls the behavior of PWM:
3=Reserved
2=PWM is configured as a 6-bit PWM
1=PWM is configured as a 7-bit PWM
0=PWM is configured as an 8-bit PWM
3 SYNCHRONIZE
When this bit is ‘1’, all counters for all LEDs are reset to their initial
values. When this bit is ‘0’ in the LED Configuration Register for all
LEDs, then all counters for LEDs that are configured to blink or
breathe will increment or decrement, as required.
To synchronize blinking or breathing, the SYNCHRONIZE bit should
be set for at least one LED, the control registers for each LED should
be set to their required values, then the SYNCHRONIZE bits should
all be cleared. If the all LEDs are set for the same blink period, they
will all be synchronized.
2 CLOCK_SOURCE
This bit controls the base clock for the PWM. It is only valid when
CNTRL is set to blink (2).
1=Clock source is the 48 MHz clock
0=Clock source is the 32.768 KHz clock
1:0 CONTROL
This bit controls the behavior of PWM:
3=PWM is always on
2=LED blinking (standard PWM)
1=LED breathing configuration
0=PWM is always off. All internal registers and counters are reset to
0. Clocks are gated
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21.10.2
LED LIMITS REGISTER
This register may be written at any time. Values written into the register are held in an holding register, which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads of
this register return the current contents and not the value of the holding register.
Offset
04h
Bits
Description
31:16 Reserved
Type
Default
Reset
Event
R
-
-
15:8 MAXIMUM
In breathing mode, when the current duty cycle is greater than or
equal to this value the breathing apparatus holds the current duty
cycle for the period specified by the field HD in register LED_DELAY,
then starts decrementing the current duty cycle
R/W
0h
VCC1_
RESET
7:0 MINIMUM
In breathing mode, when the current duty cycle is less than or equal
to this value the breathing apparatus holds the current duty cycle for
the period specified by the field LD in register LED_DELAY, then
starts incrementing the current duty cycle
R/W
0h
VCC1_
RESET
In blinking mode, this field defines the duty cycle of the blink function.
21.10.3
LED DELAY REGISTER
This register may be written at any time. Values written into the register are held in an holding register, which is transferred into the actual register at the end of a PWM period if the Enable Update bit in the LED Configuration register is
set to 1. Reads of this register return the current contents and not the value of the holding register.
Offset
08h
Bits
Description
31:24 Reserved
23:12 HIGH_DELAY
In breathing mode, the number of PWM periods to wait before updating the current duty cycle when the current duty cycle is greater than
or equal to the value MAX in register LED_LIMIT.
Type
Default
Reset
Event
R
-
-
R/W
000h
VCC1_
RESET
R/W
000h
VCC1_
RESET
4095=The current duty cycle is decremented after 4096 PWM periods
…
1=The delay counter is bypassed and the current duty cycle is decremented after two PWM period
0=The delay counter is bypassed and the current duty cycle is decremented after one PWM period
11:0 LOW_DELAY
The number of PWM periods to wait before updating the current duty
cycle when the current duty cycle is greater than or equal to the value
MIN in register LED_LIMIT.
4095=The current duty cycle is incremented after 4096 PWM periods
…
0=The delay counter is bypassed and the current duty cycle is incremented after one PWM period
In blinking mode, this field defines the prescalar for the PWM clock
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21.10.4
LED UPDATE STEPSIZE REGISTER
This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every
PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized
depends on the SYMMETRY bit in the LED Configuration Register Register)
• In Symmetric Mode the Segment_Index[2:0] = Duty Cycle Bits[7:5].
• In Asymmetric Mode the Segment_Index[2:0] is the bit concatenation of following: Segment_Index[2] = (FALLING
RAMP TIME in Figure 21-3, "Clipping Example") and Segment_Index[1:0] = Duty Cycle Bits[7:6].
This register may be written at any time. Values written into the register are held in an holding register, which is transferred into the actual register at the end of a PWM period if the Enable Update bit in the LED Configuration register is
set to 1. Reads of this register return the current contents and not the value of the holding register.
In 8-bit mode, each 4-bit STEPSIZE field represents 16 possible duty cycle modifications, from 1 to 16 as the duty cycle
is modified between 0 and 255:
15: Modify the duty cycle by 16
...
1: Modify the duty cycle by 2
0: Modify the duty cycle by 1
In 7-bit mode, the least significant bit of the 4-bit field is ignored, so each field represents 8 possible duty cycle modifications, from 1 to 8, as the duty cycle is modified between 0 and 127:
14, 15: Modify the duty cycle by 8
...
2, 3: Modify the duty cycle by 2
0, 1: Modify the duty cycle by 1
In 6-bit mode, the two least significant bits of the 4-bit field is ignored, so each field represents 4 possible duty cycle
modifications, from 1 to 4 as the duty cycle is modified between 0 and 63:
12, 13, 14, 15: Modify the duty cycle by 4
8, 9, 10, 11: Modify the duty cycle by 3
4, 5, 6, 7: Modify the duty cycle by 2
0, 1, 2, 3: Modify the duty cycle by 1
Offset
0Ch
Bits
Reset
Event
Type
Default
31:28 UPDATE_STEP7
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 111.
R/W
0h
VCC1_
RESET
27:24 UPDATE_STEP6
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 110.
R/W
0h
VCC1_
RESET
23:20 UPDATE_STEP5
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 101
R/W
0h
VCC1_
RESET
19:16 UPDATE_STEP4
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 100.
R/W
0h
VCC1_
RESET
15:12 UPDATE_STEP3
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 011.
R/W
0h
VCC1_
RESET
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Description
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Offset
0Ch
Bits
Description
Reset
Event
Type
Default
11:8 UPDATE_STEP2
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 010.
R/W
0h
VCC1_
RESET
7:4 UPDATE_STEP1
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 001.
R/W
0h
VCC1_
RESET
3:0 UPDATE_STEP0
Amount the current duty cycle is adjusted at the end of every PWM
period when the segment index is equal to 000.
R/W
0h
VCC1_
RESET
21.10.5
LED UPDATE INTERVAL REGISTER
This register has eight segment fields which provide the number of PWM periods between updates to current duty cycle.
Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the
SYMMETRY bit in the LED Configuration Register Register)
• In Symmetric Mode the Segment_Index[2:0] = Duty Cycle Bits[7:5]
• In Asymmetric Mode the Segment_Index[2:0] is the bit concatenation of following: Segment_Index[2] = (FALLING
RAMP TIME in Figure 21-3, "Clipping Example") and Segment_Index[1:0] = Duty Cycle Bits[7:6].
This register may be written at any time. Values written into the register are held in an holding register, which is transferred into the actual register at the end of a PWM period if the Enable Update bit in the LED Configuration register is
set to 1. Reads of this register return the current contents and not the value of the holding register.
Offset
10h
Bits
Description
31:28 UPDATE_INTERVAL7
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 111b.
Reset
Event
Type
Default
R/W
0h
VCC1_
RESET
R/W
0h
VCC1_
RESET
R/W
0h
VCC1_
RESET
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
27:24 UPDATE_INTERVAL6
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 110b.
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
23:20 UPDATE_INTERVAL5
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 101b.
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
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Offset
10h
Bits
Description
19:16 UPDATE_INTERVAL4
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 100b.
Reset
Event
Type
Default
R/W
0h
VCC1_
RESET
R/W
0h
VCC1_
RESET
R/W
0h
VCC1_
RESET
R/W
0h
VCC1_
RESET
R/W
0h
VCC1_
RESET
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
15:12 UPDATE_INTERVAL3
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 011b.
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
11:8 UPDATE_INTERVAL2
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 010b.
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
7:4 UPDATE_INTERVAL1
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 001b.
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
3:0 UPDATE_INTERVAL0
The number of PWM periods between updates to current duty cycle
when the segment index is equal to 000b.
15=Wait 16 PWM periods
…
0=Wait 1 PWM period
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22.0
KEYBOARD SCAN INTERFACE
22.1
Overview
The Keyboard Scan Interface block provides a register interface to the EC to directly scan an external keyboard matrix
of size up to 18x8.
The maximum configuration of the Keyboard Scan Interface is 18 outputs by 8 inputs. For a smaller matrix size, firmware
should configure unused KSO pins as GPIOs or another alternate function, and it should mask out unused KSIs and
associated interrupts.
22.2
References
No references have been cited for this feature.
22.3
Terminology
There is no terminology defined for this section.
22.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 22-1:
I/O DIAGRAM OF BLOCK
Keyboard Scan Interface
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
22.5
Signal Description
TABLE 22-1:
SIGNAL DESCRIPTION TABLE
Name
Direction
KSI[7:0]
Input
KSO[17:0]
Output
2016 Microchip Technology Inc.
Description
Column inputs from external keyboard matrix.
Row outputs to external keyboard matrix.
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22.6
Host Interface
The registers defined for the Keyboard Scan Interface are accessible by the various hosts as indicated in Section 22.11,
"EC-Only Registers".
22.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
22.7.1
POWER DOMAINS
TABLE 22-2:
POWER SOURCES
Name
VCC1
22.7.2
Description
The logic and registers implemented in this block are powered by this
power well.
CLOCK INPUTS
TABLE 22-3:
CLOCK INPUTS
Name
48 MHz Ring Oscillator
22.7.3
This is the clock source for Keyboard Scan Interface logic.
RESETS
TABLE 22-4:
22.8
Description
RESET SIGNALS
Name
Description
VCC1_RESET
This signal resets all the registers and logic in this block to their default
state.
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 22-5:
EC INTERRUPTS
Source
Description
KSC_INT
Interrupt request to the Interrupt Aggregator.
KSC_INT_WAKE
Wake-up request to the Interrupt Aggregator’s wake-up interface.
22.9
Low Power Modes
The Keyboard Scan Interface automatically enters a low power mode whenever it is not actively scanning the keyboard
matrix. The block is also placed in a low-power state when it is disabled by the KSEN bit. When the interface is in a lowpower mode it will not prevent the chip from entering a sleep state. When the interface is active it will inhibit the chip
sleep state until the interface has re-entered its low power mode.
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22.10 Description
FIGURE 22-2:
Keyboard Scan Interface Block Diagram
48MHz
KSO
Select
Register
EC Bus
Output
Decoder
KSO[17:0]
SPB
I/F
KSC_INT_WAKE
KSC_INT
VCC1_RESET
KSI
Interrupt
Interface
KSI Input
and
Status
Registers
KSI[7:0]
During scanning the firmware sequentially drives low one of the rows (KSO[17:0]) and then reads the column data line
(KSI[7:0]). A key press is detected as a zero in the corresponding position in the matrix. Keys that are pressed are
debounced by firmware. Once confirmed, the corresponding keycode is loaded into host data read buffer in the 8042
Host Interface module. Firmware may need to buffer keycodes in memory in case this interface is stalled or the host
requests a Resend.
22.10.1
INITIALIZATION OF KSO PINS
If the Keyboard Scan Interface is not configured for PREDRIVE Mode, KSO pins should be configured as open-drain
outputs. Internal or external pull-ups should be used so that the GPIO functions that share the pins do not have a floating
input when the KSO pins are tri-stated.
If the Keyboard Scan Interface is configured for PREDRIVE Mode, KSO pins must be configured as push-pull outputs.
Internal or external pull-ups should be used to protect the GPIO inputs associated with the KSO pins from floating inputs.
22.10.2
PREDRIVE MODE
There is an optional Predrive Mode that can be enabled to actively drive the KSO pins high before switching to opendrain operation. The PREDRIVE ENABLE bit in the Keyscan Extended Control Register is used to enable the PREDRIVE option. Timing for the Predive mode is shown in Section 30.5, Keyboard Scan Matrix Timing.
22.10.2.1
Predrive Mode Programming
The following precautions should be taken to prevent output pad damage during Predrive Mode Programming.
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22.10.2.2
1.
2.
3.
4.
Disable Key Scan Interface (KSEN = '1')
Enable Predrive function (PREDRIVE_ENABLE = '1')
Program buffer type for all KSO pins to "push-pull”
Enable Keyscan Interface (KSEN ='0')
22.10.2.3
1.
2.
3.
4.
Asserting PREDRIVE_ENABLE
De-asserting PREDRIVE_ENABLE
Disable Key Scan Interface (KSEN = '1')
Program buffer type for all KSO pins to "open-drain”
Disable Predrive function (PREDRIVE_ENABLE = '0')
Enable Keyscan Interface (KSEN ='0')
22.10.3
INTERRUPT GENERATION
To support interrupt-based processing, an interrupt can optionally be generated on the high-to-low transition on any of
the KSI inputs. A running clock is not required to generate interrupts.
22.10.3.1
Runtime interrupt
KSC_INT is the block’s runtime active-high level interrupt. It is connected to the interrupt interface of the Interrupt Aggregator, which then relays interrupts to the EC.
Associated with each KSI input is a status register bit and an interrupt enable register bit. A status bit is set when the
associated KSI input goes from high to low. If the interrupt enable bit for that input is set, an interrupt is generated. An
Interrupt is de-asserted when the status bit and/or interrupt enable bit is clear. A status bit cleared when written to a ‘1’.
Interrupts from individual KSIs are logically ORed together to drive the KSC_INT output port. Once asserted, an interrupt
is not asserted again until either all KSI[7:0] inputs have returned high or the has changed.
22.10.3.2
Wake-up Interrupt
KSC_INT_WAKE is the block’s wakeup interrupt. It is routed to the Interrupt Aggregator.
During sleep mode, i.e., when the bus clock is stopped, a high-to-low transition on any KSI whose interrupt enable bit
is set causes the KSC_INT_WAKE to be asserted. Also set is the associated status bit in the EC Clock Required 2 Status
Register (EC_CLK_REQ2_STS). KSC_WAKEUP_INT remains active until the bus clock is started.
The aforementioned transition on KSI also sets the corresponding status bit in the KSI STATUS Register. If enabled, a
runtime interrupt is also asserted on KSC_INT when the bus clock resumes running.
22.10.4
WAKE PROGRAMMING
Using the Keyboard Scan Interface to ‘wake’ the CEC1302 can be accomplished using either the Keyboard Scan Interface wake interrupt, or using the wake capabilities of the GPIO Interface pins that are multiplexed with the Keyboard
Scan Interface pins. Enabling the Keyboard Scan Interface wake interrupt requires only a single interrupt enable access
and is recommended over using the GPIO Interface for this purpose.
22.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Keyboard Scan Interface.
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
the EC-Only Register Base Address Table.
TABLE 22-6:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
Address Space
Base Address
Keyboard Scan
0
EC
32-bit internal
4000_9C00h
Interface
address space
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
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TABLE 22-7:
EC-ONLY REGISTER SUMMARY
Offset
Register Name
0h
Reserved
4h
KSO Select Register
8h
KSI INPUT Register
Ch
KSI STATUS Register
10h
KSI INTERRUPT ENABLE Register
14h
Keyscan Extended Control Register
22.11.1
KSO SELECT REGISTER
Offset
04h
Bits
Description
31:4 Reserved
7 KSO_INVERT
This bit controls the output level of KSO pins when selected.
Type
Default
Reset
Event
R
-
-
R/W
0b
VCC1_R
ESET
R/W
1h
VCC1_R
ESET
R/W
0b
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
0= KSO[x] driven low when selected
1= KSO[x] driven high when selected.
6 KSEN
This field enables and disables keyboard scan
0= Keyboard scan enabled
1= Keyboard scan disabled. All KSO output buffers disabled.
5 KSO_ALL
0=When key scan is enabled, KSO output controlled by the KSO_SELECT field.
1=KSO[x] driven high when selected.
4:0 KSO_SELECT
This field selects a KSO line (00000b = KSO[0] etc.) for output
according to the value off KSO_INVERT in this register. See
Table 22-8, "KSO Select Decode"
TABLE 22-8:
KSO SELECT DECODE
KSO Select [4:0]
KSO Selected
00h
KSO00
01h
KSO01
02h
KSO02
03h
KSO03
04h
KSO04
05h
KSO05
06h
KSO06
07h
KSO07
08h
KSO08
09h
KSO09
0Ah
KSO10
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TABLE 22-8:
KSO SELECT DECODE (CONTINUED)
KSO Select [4:0]
KSO Selected
0Bh
KSO11
0Ch
KSO12
0Dh
KSO13
0Eh
KSO14
0Fh
KSO15
10h
KSO16
11h
KSO17
TABLE 22-9:
KEYBOARD SCAN OUT CONTROL SUMMARY
KSO_INVERTt
KSEN
KSO_ALL
KSO_SELECT
Description
X
1
x
x
Keyboard Scan disabled. KSO[17:0]
output buffers disabled.
0
0
0
10001b-00000b
KSO[Drive Selected] driven low. All
others driven high
1
0
0
10001b-00000b
KSO[Drive Selected] driven high. All
others driven low
0
0
0
11111b-10010b
All KSO’s driven high
1
0
0
11111b-10010b
All KSO’s driven low
0
0
1
x
All KSO’s driven high
1
0
1
x
All KSO’s driven low
22.11.2
KSI INPUT REGISTER
Offset
08h
Bits
Description
31:8 Reserved
7:0 KSI
This field returns the current state of the KSI pins.
22.11.3
Type
Default
Reset
Event
R
-
-
R
0h
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/WC
0h
VCC1_R
ESET
KSI STATUS REGISTER
Offset
0Ch
Bits
Description
31:8 Reserved
7:0 KSI_STATUS
Each bit in this field is set on the falling edge of the corresponding
KSI input pin.
A KSI interrupt is generated when its corresponding status bit and
interrupt enable bit are both set. KSI interrupts are logically ORed
together to produce KSC_INT and KSC_INT_WAKE.
Writing a ‘1’ to a bit will clear it. Writing a ‘0’ to a bit has no effect.
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CEC1302
22.11.4
KSI INTERRUPT ENABLE REGISTER
Offset
10h
Bits
Description
Type
31:8 Reserved
7:0 KSI_INT_EN
Each bit in KSI_INT_EN enables interrupt generation due to high-tolow transition on a KSI input. An interrupt is generated when the corresponding bits in KSI_STATUS and KSI_INT_EN are both set.
22.11.5
Offset
Reset
Event
Default
R
-
-
R/W
0h
VCC1_R
ESET
KEYSCAN EXTENDED CONTROL REGISTER
14h
Bits
Description
32:1 Reserved
0 PREDRIVE_ENABLE
PREDRIVE_ENABLE enables the PREDRIVE mode to
actively drive the KSO pins high for approximately 100 ns
before switching to open-drain operation.
Type
Default
Reset Event
R
-
-
RW
0
VCC1_RESET
0=Disable predrive on KSO pins
1=Enable predrive on KSO pins.
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23.0
BC-LINK MASTER
23.1
Overview
This block provides BC-Link connectivity to a slave device. The BC-Link protocol includes a start bit to signal the
beginning of a message and a turnaround (TAR) period for bus transfer between the Master and Companion devices.
23.2
References
No references have been cited for this feature.
23.3
Terminology
There is no terminology defined for this section.
23.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 23-1:
I/O DIAGRAM OF BLOCK
BC-Link Master
Interface
Signal Description
Power, Clocks and Reset
Interrupts
23.5
Signal Description
TABLE 23-1:
SIGNAL DESCRIPTION TABLE
Name
Direction
Description
BCM_CLK
Output
BC-Link output clock
BCM_DAT
Input/Output
Bidirectional data line
BCM_INT#
Input
Note:
Input from the companion device
A weak pull-up resistor is recommended on the data line (100K
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CEC1302
The maximum speed at which the BC-Link Master Interface can operate reliably depends on the drive strength of the
BC-Link BCM_CLK and BCM_DAT pins, as well as the nature of the connection to the Companion device (over ribbon
cable or on a PC board). The following table shows the recommended maximum speeds over a PC board as well as a
12 inch ribbon cable for selected drive strengths. The frequency is set with the BC-Link Clock Select Register.
TABLE 23-2:
BC-LINK MASTER PIN DRIVE STRENGTH VS. FREQUENCY
Pin Drive
Strength
Max Freq
on PC Board
Min Value in
BC-Link Clock Select
Register
Max Freq
over Ribbon cable
Min Value in BC-Link
Clock Select Register
16mA
24Mhz
1
16Mhz
2
23.6
Host Interface
The registers defined for the BC-Link Master Interface are accessible by the various hosts as indicated in Section 23.11,
"EC-Only Registers".
23.7
23.7.1
Power, Clocks and Reset
POWER DOMAINS
TABLE 23-3:
POWER SOURCES
Name
VCC1
23.7.2
Description
The logic and registers implemented in this block are powered by this
power well.
CLOCK INPUTS
TABLE 23-4:
CLOCK INPUTS
Name
48 MHz Ring Oscillator
23.7.3
This is the clock source for Keyboard Scan Interface logic.
RESETS
TABLE 23-5:
23.8
Description
RESET SIGNALS
Name
Description
VCC1_RESET
This signal resets all the registers and logic in this block to their default
state.
Interrupts
This section defines the Interrupt Sources generated from this block.
TABLE 23-6:
EC INTERRUPTS
Source
Description
BCM_INT Busy
Interrupt request to the Interrupt Aggregator, generated from the status
event BUSYdefined in the BC-Link Status Register.
BCM_INT Err
Interrupt request to the Interrupt Aggregator, generated from the status
event defined in the BC-Link Status Register.
BC_INT_N_WK
Wake-up request to the Interrupt Aggregator’s wake-up interface for BCLink Master port.
In order to enable BC-Link wakeup interrupts, the pin control registers for
the BC_INT# pin must be programmed to Input, Falling Edge Triggered,
non-inverted polarity detection.
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23.9
Low Power Modes
The BC-Link Master Interface automatically enters a low power mode whenever it is not active (that is, whenever the
BUSY bit in the BC-Link Status Register is ‘0’). When the interface is in a low-power mode it will not prevent the chip
from entering a sleep state. When the interface is active it will inhibit the chip sleep state until the interface has reentered its low power mode.
23.10 Description
FIGURE 23-2:
BC-LINK MASTER BLOCK DIAGRAM
Registers
BC_ERR
BC_BUSY_CLR
EC IF
BC Status / Control
Register
BC Address
Register
BC Data
Register
Clock
Divider
Bits
External Pin interface
MCLK/2
MCLK/4
MCLK=48MHz Ring Oscillator
23.10.1
Clock
Generator
MCLK/8
MCLK/
Divider
MCLK/
63
BCM_CLK
BC Bus Master IP
BCM_DAT
BCM_INT#
BC-LINK MASTER READ OPERATION
The BC-Link Read protocol requires two reads of the BC-Link Data Register. The two reads drive a two state-state
machine: the two states are Read#1 and Read#2. The Read#1 of the Data Register starts the read protocol on the BCLink pins and sets the BUSY bit in the BC-Link Status Register. The contents of the data read during Read#1 by the EC
is stale and is not to be used. After the BUSY bit in the BC-Link Status Register autonomously clears to ‘0’, the Read#2
of the Data Register transfers the data read from the peripheral/BC-Link companion chip to the EC.
1.
2.
3.
4.
Software starts by checking the status of the BUSY bit in the Status Register. If the BUSY bit is ‘0’, proceed. If
BUSY is ‘1’, firmware must wait until it is ‘0’.
Software writes the address of the register to be read into the BC-Link Address Register.
Software then reads the Data Register. This read returns random data. The read activates the BC-Link Master
state machine to transmit the read request packet to the BC-Link companion. When the transfer initiates, the
hardware sets the BUSY bit to a ‘1’.
The BC-Link Companion reads the selected register and transmits the read response packet to the BC-Link Master. The Companion will ignore the read request if there is a CRC error; this will cause the Master state machine
to time-out and issue a BC_ERR Interrupt.
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5.
6.
7.
8.
9.
The Master state machine loads the Data Register, issues a BUSY Bit Clear interrupt and clears the BUSY bit to
‘0’.
Software, after either receiving the Bit Clear interrupt, or polling the BUSY bit until it is ‘0’, checks the BC_ERR
bit in the Status Register.
Software can now read the Data Register which contains the valid data if there was no BC Bus error.
If a Bus Error occurs, firmware must issue a soft reset by setting the RESET bit in the Status Register to ‘1’.
The read can re-tried once BUSY is cleared.
Note:
Steps 3 thorough 7 should be completed as a contiguous sequence. If not the interface could be presenting
incorrect data when software thinks it is accessing a valid register read.
23.10.2
BC-LINK MASTER WRITE OPERATION
1.
Software starts by checking the status of the BUSY bit in the BC-Link Status Register. If the BUSY bit is ‘0’, proceed. If BUSY is ‘1’, firmware must wait until it is ‘0’.
2. Software writes the address of the register to be written into the BC-Link Address Register.
3. Software writes the data to be written into the addressed register in to the BC-Link Data Register.
4. The write to the Data Register starts the BC_Link write operation. The Master state machine sets the BUSY bit.
5. The BC-Link Master Interface transmits the write request packet.
6. When the write request packet is received by the BC-Link companion, the CRC is checked and data is written to
the addressed companion register.
7. The companion sends an ACK if the write is completed. A time-out will occur approximately 16 BC-Link clocks
after the packet is sent by the Master state machine. If a time-out occurs, the state machine will set the BC_ERR
bit in the Status Register to ‘1’ approximately 48 clocks later and then clear the BUSY bit.
8. The Master state machine issues the Bit Clear interrupt and clears the BUSY bit after receiving the ACK from the
Companion
9. If a Bus Error occurs, firmware must issue a soft reset by setting the RESET bit in the Status Register to ‘1’.
10. The write can re-tried once BUSY is cleared.
23.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the BC-Link Master interface.
The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in
the EC-Only Register Base Address Table.
TABLE 23-7:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
BC-LINK
0
EC
Address Space
Base Address (Note 23-1)
32-bit internal
4000_BC00h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
Note 23-1
TABLE 23-8:
EC-ONLY REGISTER SUMMARY
Register Name
EC Offset
BC-Link Status Register
00h
BC-Link Address Register
04h
BC-Link Data Register
08h
BC-Link Clock Select Register
0Ch
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23.11.1
BC-LINK STATUS REGISTER
Offset
00h
Bits
Description
31:4 Reserved
Type
Default
Reset
Event
R
-
-
R/W
1h
VCC1_R
ESET
R/WC
0h
VCC1_R
ESET
5 BC_ERR_INT_EN
This bit is an enable for generating an interrupt when the BC_ERR
bit is set by hardware. When this bit is ‘1’, the interrupt signal is
enabled. When this bit is ‘0’, the interrupt is disabled.
R/W
0b
VCC1_R
ESET
4 BC_BUSY_CLR_INT_EN
R/W
0h
VCC1_R
ESET
R
-
-
R
1h
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
7 RESET
When this bit is ‘1’the BC_Link Master Interface will be placed in
reset and be held in reset until this bit is cleared to ‘0’. Setting
RESET to ‘1’ causes the BUSY bit to be set to ‘1’. The BUSY
remains set to ‘1’ until the reset operation of the BC Interface is completed, which takes approximately 48 BC clocks.
The de-assertion of the BUSY bit on reset will not generate an interrupt, even if the BC_BUSY_CLR_INT_EN bit is ‘1’. The BUSY bit
must be polled in order to determine when the reset operation has
completed.
6 BC_ERR
This bit indicates that a BC Bus Error has occurred. If an error
occurs this bit is set by hardware when the BUSY bit is cleared. This
bit is cleared when written with a ’1’. An interrupt is generated If this
bit is ‘1’ and BC_ERR_INT_EN bit is ‘1’.
Errors that cause this interrupt are:
• Bad Data received by the BASE (CRC Error)
• Time-out caused by the COMPANION not responding.
All COMPANION errors cause the COMPANION to abort the operation and the BASE to time-out.
This bit is an enable for generating an interrupt when the BUSY bit in
this register is cleared by hardware. When this bit is set to ‘1’, the
interrupt signal is enabled. When the this bit is cleared to ‘0’, the interrupt is disabled. When enabled, the interrupt occurs after a BC Bus
read or write.
3:1 Reserved
0 BUSY
This bit is asserted to ‘1’ when the BC interface is transferring data
and on reset. Otherwise it is cleared to ‘0’. When this bit is cleared
by hardware, an interrupt is generated if the BC_BUSY_CLR_INT_EN bit is set to ‘1’.
23.11.2
BC-LINK ADDRESS REGISTER
Offset
04h
Bits
Description
31:8 Reserved
7:0 ADDRESS
Address in the Companion for the BC-Link transaction.
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23.11.3
BC-LINK DATA REGISTER
Offset
08h
Bits
Description
31:8 Reserved
7:0 DATA
As described in Section 23.10.1, "BC-Link Master READ Operation"
and Section 23.10.2, "BC-Link Master WRITE Operation", this register hold data used in a BC-Link transaction.
23.11.4
Type
Default
Reset
Event
R
-
-
R/W
0h
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
4h
VCC1_R
ESET
BC-LINK CLOCK SELECT REGISTER
Offset
0Ch
Bits
Description
31:8 Reserved
7:0 DIVIDER
The BC Clock is set to the Master Clock divided by this field, or
48MHz/ (Divider +1). The clock divider bits can only can be changed
when the BC Bus is in soft RESET (when either the Reset bit is set
by software or when the BUSY bit is set by the interface).
Example settings for DIVIDER are shown in Table 23-9, "Example
Frequency Settings".
TABLE 23-9:
EXAMPLE FREQUENCY SETTINGS
Divider
Frequency
0
48MHz
1
24MHz
2
16MHz
3
12MHz
4
9.6MHz
15
2.18MHz
2A
1.12MHz
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24.0
TRACE FIFO DEBUG PORT (TFDP)
24.1
Introduction
The TFDP serially transmits Embedded Controller (EC)-originated diagnostic vectors to an external debug trace system.
24.2
References
No references have been cited for this chapter.
24.3
Terminology
There is no terminology defined for this chapter.
24.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 24-1:
I/O DIAGRAM OF BLOCK
Trace FIFO Debug Port
(TFDP)
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
24.5
Signal Description
The Signal Description Table lists the signals that are typically routed to the pin interface.
TABLE 24-1:
24.6
SIGNAL DESCRIPTION TABLE
Name
Direction
Description
TFDP Clk
Output
Derived from EC Bus Clock.
TFDP Data
Output
Serialized data shifted out by TFDP Clk.
Host Interface
The registers defined for the Trace FIFO Debug Port (TFDP) are accessible by the various hosts as indicated in Section
24.11, "EC-Only Registers".
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24.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
24.7.1
POWER DOMAINS
TABLE 24-2:
POWER SOURCES
Name
Description
VCC1
24.7.2
This power well sources all of the registers and logic in this block.
CLOCK INPUTS
TABLE 24-3:
CLOCK INPUTS
Name
Description
48 MHz Ring Oscillator
24.7.3
This clock input is used to derive the TFDP Clk.
RESETS
TABLE 24-4:
RESET SIGNALS
Name
Description
VCC1_RESET
24.8
This reset signal resets all of the registers and logic in this block.
Interrupts
There are no interrupts generated from this block.
24.9
Low Power Modes
The Trace FIFO Debug Port (TFDP) may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR)
circuitry.
24.10 Description
The TFDP is a unidirectional (from processor to external world) two-wire serial, byte-oriented debug interface for use
by processor firmware to transmit diagnostic information.
The TFDP consists of the Debug Data Register, Debug Control Register, a Parallel-to-Serial Converter, a Clock/Control
Interface and a two-pin external interface (TFDP Clk, TFDP Data).
FIGURE 24-2:
BLOCK DIAGRAM OF TFDP DEBUG PORT
Data
Register
CLOCK/CONTROL
INTERFACE
TFDP_DAT
TFDP_CLK
MCLK
WRITE_COMPLETE
PARALLEL-TO-SERIAL
CONVERTER
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The firmware executing on the embedded controller writes to the Debug Data Register to initiate a transfer cycle. At first,
data from the Debug Data Register is shifted into the LSB. Afterwards, it is transmitted at the rate of one byte per transfer
cycle.
Data is transferred in one direction only from the Debug Data Register to the external interface. The data is shifted out
at the clock edge. The clock edge is selected by the EDGE_SEL bit in the Debug Control Register. After being shifted
out, valid data is provided at the opposite edge of the TFDP_CLK. For example, when the EDGE_SEL bit is ‘0’ (default),
valid data is maintained at the falling edge of TFDP_CLK. The Setup Time (to the falling edge of TFDP_CLK) is 10 ns,
minimum. The Hold Time is 1 ns, minimum.
When the Serial Debug Port is inactive, the TFDP_CLK and TFDP_DAT outputs are ‘1.’ The EC Bus Clock clock input
is the transfer clock.
FIGURE 24-3:
DATA TRANSFER
TFDP_CLK
D0
TFDP_DAT
D1
D2
D3
D4
D5
D6
D7
CPU_CLOCK
24.11 EC-Only Registers
The registers listed in the EC-Only Register Summary table are for a single instance of the Trace FIFO Debug Port
(TFDP). The addresses of each register listed in this table are defined as a relative offset to the host “Base Address”
defined in the EC-Only Register Base Address Table.
TABLE 24-5:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
TFDP Debug Port
Instance
Number
Host
Address Space
Base Address
0
EC
32-bit internal
address space
4000_8C00h
The Base Address indicates where the first register can be accessed in a particular address space for a block instance.
TABLE 24-6:
EC-ONLY REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
Debug Data Register
04h
Debug Control Register
24.11.1
DEBUG DATA REGISTER
The Debut Data Register is Read/Write. It always returns the last data written by the TFDP or the power-on default ‘00h’.
Offset
00h
Bits
Description
7:0 DATA
Debug data to be shifted out on the TFDP Debug port. While data is
being shifted out, the Host Interface will ‘hold-off’ additional writes to
the data register until the transfer is complete.
DS00002022B-page 258
Type
Default
R/W
00h
Reset
Event
VCC1_R
ESET
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24.11.2
DEBUG CONTROL REGISTER
04h
Offset
Bits
Description
7 Reserved
Type
Default
Reset
Event
R
-
-
6:4 IP_DELAY
Inter-packet Delay. The delay is in terms of TFDP Debug output
clocks. A value of 0 provides a 1 clock inter-packet period, while a
value of 7 provides 8 clocks between packets:
R/W
000b
VCC1_R
ESET
3:2 DIVSEL
Clock Divider Select. The TFDP Debug output clock is determined
by this field, according to Table 24-7, "TFDP Debug Clocking":
R/W
00b
VCC1_R
ESET
R/W
0b
VCC1_R
ESET
R/W
0b
VCC1_R
ESET
1 EDGE_SEL
1= Data is shifted out on the falling edge of the debug clock
0= Data is shifted out on the rising edge of the debug clock (Default)
0 EN
Enable.
1=Clock enabled
0=Clock is disabled (Default)
TABLE 24-7:
TFDP DEBUG CLOCKING
divsel
TFDP Debug Clock
00
24 MHz
01
12 MHz
10
6 MHz
11
Reserved
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25.0
ANALOG TO DIGITAL CONVERTER
25.1
Introduction
This block is designed to convert external analog voltage readings into digital values. It consists of a single successiveapproximation Analog-Digital Converter that can be shared among five inputs.
Note:
25.2
Transitions on ADC GPIOs are not permitted when Analog to Digital Converter readings are being taken.
References
No references have been cited for this chapter
25.3
Terminology
No terminology is defined for this chapter
25.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 25-1:
I/O DIAGRAM OF BLOCK
Analog to Digital Converter
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
25.5
Signal Description
The Signal Description Table lists the signals that are typically routed to the pin interface.
TABLE 25-1:
Note:
SIGNAL DESCRIPTION TABLE
Name
Direction
ADC 4:0
Input
Description
ADC Analog Voltage Input 4:0 from pins
VREF_ADC, the Analog Voltage Reference of 3.0V, is internally generated in the IP block.
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25.6
Host Interface
The registers defined for the Trace FIFO Debug Port are accessible by the various hosts as indicated in Section 25.11,
"EC-Only Registers".
25.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
25.7.1
POWER DOMAINS
TABLE 25-2:
POWER SOURCES
Name
25.7.2
VCC1
This power well sources the registers tn this block.
AVCC
This power well sources of the logic in this block, except where noted.
AVSS
This is the ground signal for the block.
CLOCK INPUTS
TABLE 25-3:
25.7.3
CLOCK INPUTS
Name
Description
1.2MHz
This derived clock signal drives selected logic (1.2 MHz clock with a 50%
duty cycle).
RESETS
TABLE 25-4:
RESET SIGNALS
Name
VCC1_RESET
25.8
Description
This reset signal resets all of the registers and logic in this block.
Interrupts
TABLE 25-5:
EC INTERRUPTS
Source
25.9
Description
Description
ADC_Single_Int
Interrupt signal from ADC controller to EC for Single-Sample ADC conversion.
ADC_Repeat_Int
Interrupt signal from ADC controller to EC for Repeated ADC conversion.
Low Power Modes
The ADC may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
The ADC is designed to conserve power when it is either sleeping or disabled. It is disabled via the Activate Bit and
sleeps when the ADC_SLEEP_EN signal is asserted. The sleeping state only controls clocking in the ADC and does
not power down the analog circuitry. For lowest power consumption, the ADC Activate bit must be set to ‘0.’
Note:
The ADC VREF must be powered down in order to get the lowest deep sleep current. The ADC VREF
Power down bit, ADC_VREF_PD_REF is in the EC Subsystem Registers ADC VREF PD on page 273.
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25.10 Description
FIGURE 25-2:
ADC BLOCK DIAGRAM
ADC BLOCK
VREF
Analog Inputs
ADC Reading Registers
Host Interface
reading
Latch
Control
Logic
10-bit reading value
ADC
MUX
ADC_Single_Int
ADC_Repeat_Int
Control
ADC_SLEEP_EN
ADC_CLK_REQ
The CEC1302 features a five channel successive approximation Analog to Digital Converter. The ADC architecture features excellent linearity and converts analog signals to 10 bit words. Conversion takes less than 12 microseconds per
10-bit word. The five channels are implemented with a single high speed ADC fed by a five input analog multiplexer.
The multiplexer cycles through the five voltage channels, starting with the lowest-numbered channel and proceeding to
the highest-number channel, selecting only those channels that are programmed to be active.
The input range on the voltage channels spans from 0V to the internal voltage reference. With an internal voltage reference of 3.0V, this provides resolutions of 2.9mV. The range can easily be extended with the aid of resistor dividers.
The accuracy of any voltage reading depends on the accuracy and stability of the voltage reference input.
Note:
The ADC pins are 3.3V tolerant.
The ADC conversion cycle starts either when the Start_Single bit in the ADC to set to 1 or when the ADC Repeat Timer
counts down to 0. When the Start_Single is set to 1 the conversion cycle converts channels enabled by configuration
bits in the ADC Single Register. When the Repeat Timer counts down to 0 the conversion cycle converts channels
enabled by configuration bits in the ADC Repeat Register. When both the Start_Single bit and the Repeat Timer request
conversions the Start_Single conversion is completed first.
Conversions always start with the lowest-numbered enabled channel and proceed to the highest-numbered enabled
channel.
Note:
If software repeatedly sets Start_Single to 1 at a rate faster than the Repeat Timer count down interval, the
conversion cycle defined by the ADC Repeat Register will not be executed.
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25.10.1
REPEAT MODE
• Repeat Mode will start a conversion cycle of all ADC channels enabled by bits Rpt_En[4:0] in the ADC Repeat
Register. The conversion cycle will begin after a delay determined by Start_Delay[15:0] in the ADC Delay Register.
• After all channels enabled by Rpt_En[4:0] are complete, Repeat_Done_Status will be set to 1. This status bit is
cleared when the next repeating conversion cycle begins to give a reflection of when the conversion is in progress.
• As long as Start_Repeat is 1 the ADC will repeatedly begin conversion cycles with a period defined by
Repeat_Delay[15:0].
• If the delay period expires and a conversion cycle is already in progress because Start_Single was written with a
1, the cycle in progress will complete, followed immediately by a conversion cycle using Rpt_En[4:0] to control the
channel conversions.
25.10.2
SINGLE MODE
• The Single Mode conversion cycle will begin without a delay. After all channels enabled by Single_En[4:0] are
complete, Single_Done_Status will be set to 1. When the next conversion cycle begins the bit is cleared.
• If Start_Single is written with a 1 while a conversion cycle is in progress because Start_Repeat is set, the conversion cycle will complete, followed immediately by a conversion cycle using Single_En[4:0] to control the channel
conversions.
25.11 EC-Only Registers
The registers listed in the Table 25-7, "Analog to Digital Converter Register Summary" are for a single instance of the
Analog to Digital Converter block. The addresses of each register listed in this table are defined as a relative offset to
the host “Base Address” defined in Table 25-6, "Analog to Digital Converter Base Address Table".
TABLE 25-6:
ANALOG TO DIGITAL CONVERTER BASE ADDRESS TABLE
Instance Name
Instance
Number
Host
ADC
0
EC
Note 25-1
TABLE 25-7:
Address Space
Base Address (Note 25-1)
32-bit internal
4000_7C00h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
ANALOG TO DIGITAL CONVERTER REGISTER SUMMARY
Offset
Register Name (Mnemonic)
00h
ADC Control Register
04h
ADC Delay Register
08h
ADC Status Register
0Ch
ADC Single Register
10h
ADC Repeat Register
14h
ADC Channel 0 Reading Register
18h
ADC Channel 1 Reading Register
1Ch
ADC Channel 2 Reading Register
20h
ADC Channel 3 Reading Register
24h
ADC Channel 4 Reading Register
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25.11.1
ADC CONTROL REGISTER
The ADC Control Register is used to control the behavior of the Analog to Digital Converter.
Offset
00h
Bits
Description
31:8 RESERVED
7 Single_Done_Status
Type
Default
Reset
Event
RES
R/WC
0h
VCC1_R
ESET
R/WC
0h
VCC1_R
ESET
This bit is cleared when it is written with a 1. Writing a 0 to this bit
has no effect.
This bit can be used to generate an EC interrupt.
0: ADC single-sample conversion is not complete. This bit is cleared
whenever an ADC conversion cycle begins for a single conversion
cycle.
1: ADC single-sample conversion is completed. This bit is set to 1
when all enabled channels in the single conversion cycle.
6 Repeat_Done_Status
This bit is cleared when it is written with a 1. Writing a 0 to this bit
has no effect.
This bit can be used to generate an EC interrupt.
0: ADC repeat-sample conversion is not complete. This bit is cleared
whenever an ADC conversion cycle begins for a repeating conversion cycle.
1: ADC repeat-sample conversion is completed. This bit is set to 1
when all enabled channels in a repeating conversion cycle complete.
5 RESERVED
RES
4 Soft Reset
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
R/W
0h
VCC1_R
ESET
1: writing one causes a reset of the ADC block hardware (not the
registers)
0: writing zero takes the ADC block out of reset
3 Power_Saver_Dis
0: Power saving feature is enabled. The Analog to Digital Converter
controller powers down the ADC between conversion sequences.
1: Power saving feature is disabled.
2 Start_Repeat
0: The ADC Repeat Mode is disabled. Note: This setting will not terminate any conversion cycle in process, but will inhibit any further
periodic conversions.
1: The ADC Repeat Mode is enabled. This setting will start a conversion cycle of all ADC channels enabled by bits Rpt_En[4:0] in the
ADC Repeat Register.
1 Start_Single
0: The ADC Single Mode is disabled.
1: The ADC Single Mode is enabled. This setting starts a single conversion cycle of all ADC channels enabled by bits Single_En[4:0] in
the ADC Single Register.
Note:
DS00002022B-page 264
This bit is self-clearing
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CEC1302
Offset
00h
Bits
Description
0 Activate
Type
Default
R/W
0h
0: The ADC is disabled and placed in its lowest power state. Note:
Any conversion cycle in process will complete before the block is
shut down, so that the reading registers will contain valid data but no
new conversion cycles will begin.
1: ADC block is enabled for operation. Start_Single or Start_Repeat
can begin data conversions by the ADC. Note: A reset pulse is sent
to the ADC core when this bit changes from 0 to 1.
25.11.2
Reset
Event
VCC1_R
ESET
ADC DELAY REGISTER
The ADC Delay register determines the delay from setting Start_Repeat in the ADC Control Register and the start of a
conversion cycle. This register also controls the interval between conversion cycles in repeat mode.
Offset
04h
Bits
Description
31:16 Repeat_Delay[15:0]
Default
R/W
0000h
VCC1_R
ESET
R/W
0000h
VCC1_R
ESET
This field determines the interval between conversion cycles when
Start_Repeat is 1. The delay is in units of 40s. A value of 0 means
no delay between conversion cycles, and a value of 0xFFFF means
a delay of 2.6 seconds.
This field has no effect when Start_Single is written with a 1.
15:0 Start_Delay[15:0]
This field determines the starting delay before a conversion cycle is
begun when Start_Repeat is written with a 1. The delay is in units of
40s. A value of 0 means no delay before the start of a conversion
cycle, and a value of 0xFFFF means a delay of 2.6 seconds.
This field has no effect when Start_Single is written with a 1.
25.11.3
Reset
Event
Type
ADC STATUS REGISTER
The ADC Status Register indicates whether the ADC has completed a conversion cycle.
Offset
08h
Bits
Description
31:5 RESERVED
4:0 ADC_Ch_Status[4:0]
All bits are cleared by being written with a ‘1’.
0: conversion of the corresponding ADC channel is not complete
1: conversion of the corresponding ADC channel is complete
Note: for enabled single cycles, the Single_Done_Status bit in the
ADC Control Register is also set after all enabled channel conversion are done; for enabled repeat cycles, the Repeat_Done_Status
in the ADC Control Register is also set after all enabled channel conversion are done.
2016 Microchip Technology Inc.
Type
Default
Reset
Event
RES
R/WC
00h
VCC1_R
ESET
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25.11.4
ADC SINGLE REGISTER
The ADC Single Register is used to control which ADC channel is captured during a Single-Sample conversion cycle
initiated by the Start_Single bit in the ADC Control Register.
APPLICATION NOTE: Do not change the bits in this register in the middle of a conversion cycle to insure proper
operation.
Offset
0Ch
Bits
Description
31:5 RESERVED
Type
Default
RES
4:0 Single_En[4:0]
R/W
00h
0: single cycle conversions for this channel are disabled
1: single cycle conversions for this channel are enabled
Each bit in this field enables the corresponding ADC channel when a
single cycle of conversions is started when the Start_Single bit in the
ADC Control Register is written with a 1.
25.11.5
Reset
Event
VCC1_R
ESET
ADC REPEAT REGISTER
The ADC Repeat Register is used to control which ADC channels are captured during a repeat conversion cycle initiated
by the Start_Repeat bit in the ADC Control Register.
Offset
10h
Bits
Description
Type
31:5
RESERVED
RES
4:0
Rpt_En[4:0]
R/W
Default
00h
0: repeat conversions for this channel are disabled
1: repeat conversions for this channel are enabled
Each bit in this field enables the corresponding ADC channel for
each pass of the Repeated ADC Conversion that is controlled by bit
Start_Repeat in the ADC Control Register.
25.11.6
Reset
Event
VCC1_R
ESET
ADC CHANNEL READING REGISTERS
All 5 ADC channels return their results into a 32-bit reading register. In each case the low 10 bits of the reading register
return the result of the Analog to Digital conversion and the upper 22 bits return 0. Table 25-7, “Analog to Digital Converter Register Summary,” on page 263 shows the addresses of all the reading registers.
Note:
The ADC Channel Reading Registers access require single 16, or 32 bit reads; i.e., two 8 bit reads cannot
ensure data coherency.
Offset
See Table 25-7, "Analog to Digital Converter Register Summary"
Bits
Description
Type
31:10 RESERVED
RES
9:0 ADCx_[9:0]
R/W
This read-only field reports the 10-bit output reading of the Input
ADCx.
DS00002022B-page 266
Default
000h
Reset
Event
VCC1_R
ESET
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CEC1302
26.0
VBAT-POWERED RAM
26.1
Overview
The VBAT Powered RAM provides a 64 Byte Random Accessed Memory that is operational while the main power rail
is operational, and will retain its values powered by battery power while the main rail is unpowered.
26.2
References
No references have been cited for this feature.
26.3
Terminology
There is no terminology defined for this section.
26.4
Interface
This block is designed to be accessed externally via the pin interface and internally via a registered host interface.
FIGURE 26-1:
I/O DIAGRAM OF BLOCK
VBAT-Powered RAM
Host Interface
Signal Description
Power, Clocks and Reset
Interrupts
26.5
Signal Description
There are no external signals for this block.
26.6
Host Interface
The registers defined for the Keyboard Scan Interface are accessible by the various hosts as indicated in Section 26.11,
"Registers".
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26.7
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
26.7.1
POWER DOMAINS
TABLE 26-1:
26.7.2
POWER SOURCES
Name
Description
VCC1
The main power well used when the VBAT RAM is accessed by the EC.
VBAT
The power well used to retain memory state while the main power rail is
unpowered.
CLOCK INPUTS
No special clocks are required for this block.
26.7.3
RESETS
TABLE 26-2:
26.8
RESET SIGNALS
Name
Description
VBAT_POR
This signal resets all the registers and logic in this block to their default
state.
Interrupts
This block does not generate any interrupts.
26.9
Low Power Modes
The VBAT-Powered RAM automatically enters a low power mode whenever it is not being accessed by the EC. There
is no chip-level Sleep Enable input.
26.10 Description
FIGURE 26-2:
VBAT RAM BLOCK DIAGRAM
EC Interface
This interface is
only operational
when main
power is
present
VBAT Powered RAM
The VBAT Powered RAM provides a 64 Byte Random Accessed Memory that is operational while VCC1 is powered,
and will retain its values powered by VBAT while VCC1 is unpowered. The RAM is organized as a 16 words x 32-bit
wide for a total of 64 bytes.
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26.11 Registers
26.11.1
REGISTERS SUMMARY
The registers listed in the Table 26-3, "EC-Only Register Base Address Table" are for a single instance of the Keyboard
Scan Interface block. Each 32-bit RAM location is an offset from the EC base address.
TABLE 26-3:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
VBAT-Powered RAM
0
EC
Note 26-1
Address Space
Base Address (Note 26-1)
32-bit internal
4000_A800h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
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27.0
EC SUBSYSTEM REGISTERS
27.1
Introduction
This chapter defines a bank of registers associated with the EC Subsystem.
27.2
References
None
27.3
Interface
This block is designed to be accessed internally by the EC via the register interface.
27.4
Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
27.4.1
POWER DOMAINS
TABLE 27-1:
27.4.2
POWER SOURCES
Name
Description
VCC1
The EC Subsystem Registers are all implemented on this single power
domain.
CLOCK INPUTS
This block does not require any special clock inputs. All register accesses are synchronized to the host clock.
27.4.3
RESETS
TABLE 27-2:
27.5
RESET SIGNALS
Name
Description
VCC1_RESET
This reset signal, which is an input to this block, resets all the logic and
registers to their initial default state.
Interrupts
This block does not generate any interrupt events.
27.6
Low Power Modes
The EC Subsystem Registers may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
When this block is commanded to sleep it will still allow read/write access to the registers.
27.7
Description
The EC Subsystem Registers block is a block implemented for aggregating miscellaneous registers required by the
Embedded Controller (EC) Subsystem that are not unique to a block implemented in the EC subsystem.
27.8
EC-Only Registers
TABLE 27-3:
EC-ONLY REGISTER BASE ADDRESS TABLE
Block Instance
Instance
Number
Host
EC_REG_BANK
0
EC
Note 27-1
Address Space
Base Address (Note 27-1)
32-bit internal
4000_FC00h
address space
The Base Address indicates where the first register can be accessed in a particular address space
for a block instance.
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CEC1302
TABLE 27-4:
REGISTER SUMMARY
Offset
Register Name
04h
MCHP Reserved
08h
MCHP Reserved
0Ch
MCHP Reserved
10h
MCHP Reserved
14h
AHB Error Control
18h
Interrupt Control
1Ch
ETM TRACE Enable
20h
JTAG Enable
24h
MCHP Reserved
28h
WDT Event Count
2Ch
MCHP Reserved
30h
MCHP Reserved
34h
MCHP Reserved
38h
ADC VREF PD
3Ch
MCHP Reserved
40h
MCHP Reserved
27.8.1
AHB ERROR CONTROL
Offset
14h
Bits
Description
7:1 Reserved
0 AHB_ERROR_DISABLE
0: EC memory exceptions are enabled.
1: EC memory exceptions are disabled.
27.8.2
Type
Default
Reset
Event
R
-
-
RW
0h
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
1b
VCC1_R
ESET
INTERRUPT CONTROL
Offset
18h
Bits
Description
31:1 Reserved
0 NVIC_EN
This bit enables Alternate NVIC IRQ’s Vectors. The Alternate NVIC
Vectors provides each interrupt event with a dedicated (direct) NVIC
vector.
0 = Alternate NVIC vectors disabled
1= Alternate NVIC vectors enabled
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27.8.3
ETM TRACE ENABLE
Offset
1Ch
Bits
Description
31:1 Reserved
0 TRACE_EN
Type
Default
Reset
Event
R
-
-
R/W
0b
VCC1_R
ESET
Type
Default
Reset
Event
R
-
-
R/W
0b
VCC1_R
ESET
Type
Default
This bit enables the ARM TRACE debug port (ETM/ITM). The Trace
Debug Interface pins are forced to the TRACE functions.
0 = ARM TRACE port disabled
1= ARM TRACE port enabled
27.8.4
JTAG ENABLE
Offset
20h
Bits
Description
31:1 Reserved
0 JTAG_EN
This bit enables the JTAG debug port.
0 = JTAG port disabled. JTAG cannot be enabled (i.e., the TRST#
pin is ignored and the JTAG signals remain in their non-JTAG
state).
1= JTAG port enabled. A high on TRST# enables JTAG
27.8.5
WDT EVENT COUNT
Offset
28h
Bits
Description
31:4 Reserved
3:0 WDT_COUNT
Reset
Event
R
-
-
R/W
0b
VCC1_R
ESET
These EC R/W bits are cleared to 0 on VCC1 POR, but not on a
WDT.
Note:
DS00002022B-page 272
This field is written by Boot ROM firmware to indicate the
number of times a WDT fired before loading a good EC
code image.
2016 Microchip Technology Inc.
CEC1302
27.8.6
ADC VREF PD
Offset
38h
Bits
Description
31:1 Reserved
0 ADC_VREF_PD_REF
ADC VREF Power down
0=on
1=off
2016 Microchip Technology Inc.
Type
Default
Reset
Event
R
-
-
R/W
0b
VCC1_R
ESET
DS00002022B-page 273
CEC1302
28.0
TEST MECHANISMS
28.1
Introduction
This section defines the XNOR Chain for board test.
Other test mechanisms for the ARM are described in Chapter 6.0, "ARM M4F Based Embedded Controller".
28.2
28.2.1
XNOR Chain
OVERVIEW
The XNOR Chain test mode provides a means to confirm that all CEC1302 pins are in contact with the motherboard
during assembly and test operations.
An example of an XNOR Chain test structure is illustrated below in 28.2.3Figure 28-1. When the XNOR Chain test mode
is enabled all pins, except for the Excluded Pins shown in Section 28.2.2, are disconnected from their internal functions
and forced as inputs to the XNOR Chain. This allows a single input pin to toggle the XNOR Chain output if all other
input pins are held high or low. The XNOR Chain output is the Test Output Pin, pin 17: KSO04/GPIO103/TFDP_DATA/XNOR.
The tests that are performed when the XNOR Chain test mode is enabled require the board-level test hardware to control the device pins and observe the results at the XNOR Chain output pin; e.g., as described in Section 28.2.3, "Test
Procedure," on page 275.
28.2.2
EXCLUDED PINS
All pins in the pinout are included in the XNOR chain, except the following:
•
•
•
•
•
•
Power Pins (VCC1, AVCC, VBAT)
Ground Pins (VSS, AVSS, VSS_VBAT)
CAP
Crystal pins (XTAL1, XTAL2)
Test Output Pin, pin 17: KSO04/GPIO103/TFDP_DATA/XNOR
Test Port (JTAG_RST#, KSO02/GPIO101/JTAG_TDI, KSO03/GPIO102/JTAG_TDO,
KSO01/GPIO100/JTAG_TMS, and KSO00/GPIO000/JTAG_TCK)
FIGURE 28-1:
I/O#1
DS00002022B-page 274
XNOR CHAIN TEST STRUCTURE
I/O#2
I/O#3
I/O#n
XNOR
Out
2016 Microchip Technology Inc.
CEC1302
28.2.3
TEST PROCEDURE
28.2.3.1
Setup
Warning: Ensure power supply is off during Setup.
1.
2.
3.
4.
5.
Connect JTAG_RST# to ground.
Connect the VSS, AVSS, VSS_VBAT pins to ground.
Connect the VCC1, AVCC, VBAT pins to an unpowered 3.3V power source.
Connect an oscilloscope or voltmeter to the Test Output pin.
All other pins should be tied to ground.
Note:
There are 101 pins in the XNOR Chain.
28.2.3.2
1.
2.
Turn on the 3.3V power source.
Enable the XNOR Chain as defined in Section 28.2.3.3, "Procedure to Enable the XNOR Chain".
Note:
3.
4.
Testing
At this point all inputs to the XNOR Chain are low, except for the JTAG_RST# pin, and the output on the
Test Output pin is non-inverted from its initial state, which is dependent on the number of pins in the chain.
If the number of input pins in the chain is an even number, the initial state of the Test Output Pin, pin 17:
KSO04/GPIO103/TFDP_DATA/XNOR is low. If the number of input pins in the chain is an odd number, the
initial state of the Test Output Pin, pin 17: KSO04/GPIO103/TFDP_DATA/XNOR is high.
Bring one pin in the chain high. The output on the Test Output Pin, pin 17: KSO04/GPIO103/TFDP_DATA/XNOR pin should toggle. Then individually toggle each of the remaining pins in the chain. Each time an
input pin is toggled either high or low the Test Output Pin, pin 17: KSO04/GPIO103/TFDP_DATA/XNOR pin
should toggle.
Once the XNOR test is completed, exit the XNOR Chain Test Mode by cycling VCC1 power.
28.2.3.3
Procedure to Enable the XNOR Chain
//BEGIN PROCEDURE TO ENTER XNOR CHAIN
///////////////////////////////////
//Reset Test Interface
///////////////////////////////////
force JTAG_RST# = 0
force KSO00/GPIO000/JTAG_TCK = 0
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1
Wait 100 ns
////////////////////////////////
//Come out of reset
////////////////////////////////
force TRST#/JTAG_RST# = 1
Wait 100 ns
force KSO00/GPIO000/JTAG_TCK = 1
force KSO00/GPIO000/JTAG_TCK = 0
force KSO00/GPIO000/JTAG_TCK = 1
force KSO00/GPIO000/JTAG_TCK = 0
2016 Microchip Technology Inc.
DS00002022B-page 275
CEC1302
force KSO00/GPIO000/JTAG_TCK = 1
force KSO00/GPIO000/JTAG_TCK = 0
force KSO00/GPIO000/JTAG_TCK = 1
force KSO00/GPIO000/JTAG_TCK = 0
////////////////////////////////
//Sequence 1
// Write IR with 7h
////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //1N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //2N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //3N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //4N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //5N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
//////////////////////////////////////
//SHIFT IR 0x7h
/////////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //6N
force KSO02/GPIO101/JTAG_TDI = 1
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //7N
force KSO02/GPIO101/JTAG_TDI = 1
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //8N
force KSO02/GPIO101/JTAG_TDI = 1
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2016 Microchip Technology Inc.
CEC1302
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //9N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1; //Next will be EXIT1_IR
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //10N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1; //Next will be UPDATE_IR
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //11N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0; //Next will be IDLE
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //12N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0; //Next will be IDLE
Wait 0 ns
//////////////////////////////////////////////////////////
// Sequence 2
// DIR=0, CMD[2:0]=1, DATA[7:0]=01\h, ADDR[7:0]=88\h
//////////////////////////////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //1N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //2N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //3N
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
///////////////////////////////////////////
//DIR 0 - Write
//////////////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR1)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
2016 Microchip Technology Inc.
DS00002022B-page 277
CEC1302
///////////////////////////////////////////
//CMD 1 - Test
//////////////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR2)
force KSO02/GPIO101/JTAG_TDI = 1
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR3)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR4)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
///////////////////////////////////////////
//DATA 0x01 - XNOR_EN
//////////////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR5)
force KSO02/GPIO101/JTAG_TDI = 1
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR6)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR7)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR8)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
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2016 Microchip Technology Inc.
CEC1302
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR9)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR10)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR11)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR12)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
//////////////////////////////////////////////////////////////
//ADDRESS 0x88 - Customer Control
/////////////////////////////////////////////////////////////
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR13)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR14)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR15)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR16)
force KSO02/GPIO101/JTAG_TDI = 1
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
2016 Microchip Technology Inc.
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CEC1302
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR17)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 1//`TP_GPIO102.Check(1);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR18)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR19)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (DR20)
force KSO02/GPIO101/JTAG_TDI = 1
force KSO01/GPIO100/JTAG_TMS = 1
force KSO00/GPIO000/JTAG_TCK = 1; //P
**Verify KSO03/GPIO102/JTAG_TDO = 0//`TP_GPIO102.Check(0);
force KSO00/GPIO000/JTAG_TCK = 0; //N (E1_DR)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 1
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //N (UP_DR)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //N (EXTRA CLK)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
force KSO00/GPIO000/JTAG_TCK = 1; //P
force KSO00/GPIO000/JTAG_TCK = 0; //N (EXTRA CLK)
force KSO02/GPIO101/JTAG_TDI = 0
force KSO01/GPIO100/JTAG_TMS = 0
Wait 100 ns
////////////////////////////////////////////////////////////////////////////
//FINISHED PROCEDURE TO ENTER XNOR
///////////////////////////////////////////////////////////////////////////
DS00002022B-page 280
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CEC1302
29.0
ELECTRICAL SPECIFICATIONS
29.1
Maximum Ratings*
*Stresses exceeding those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification
is not implied.
Note:
29.1.1
When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line
may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
ABSOLUTE MAXIMUM THERMAL RATINGS
TABLE 29-1:
ABSOLUTE MAXIMUM THERMAL RATINGS
Parameter
Maximum Limits
Operating Temperature Range
0oC
Storage Temperature Range
-55o to +150oC
Lead Temperature Range
Refer to JEDEC Spec J-STD-020B
29.1.2
ABSOLUTE MAXIMUM SUPPLY VOLTAGE RATINGS
TABLE 29-2:
ABSOLUTE POWER SUPPLY RATINGS
Symbol
29.1.3
to +70oC
Parameter
Maximum Limits
VBAT
3.0V Battery Backup Power Supply with respect to ground
VCC1
3.3V Suspend Power Supply with respect to ground
-0.3V to +3.63V
-0.3V to +3.63V
VCC2
3.3V Main Power Supply with respect to ground
-0.3V to +3.63V
ABSOLUTE MAXIMUM I/O VOLTAGE RATINGS
Parameter
Maximum Limits
Voltage with respect to ground on any pin without back-0.3V to (Power Supply used to power the buffer) + 0.3V
drive protection
(Note 29-1)
Note 29-1
The Power Supply used to power the buffer is shown in the Signal Power Well column of the Pin
Multiplexing Tables in Section 1.0 “Pin Configuration”.
29.2
29.2.1
Operational Specifications
POWER SUPPLY OPERATIONAL CHARACTERISTICS
TABLE 29-3:
Note:
POWER SUPPLY OPERATING CONDITIONS
Symbol
Parameter
MIN
TYP
VBAT
VCC1
MAX
Units
Battery Backup Power Supply
2.0
Suspend Power Supply
3.135
3.0
3.6
V
3.3
3.465
V
The specification for the VCC1 supply is +/- 5%.
2016 Microchip Technology Inc.
DS00002022B-page 281
CEC1302
29.2.2
AC ELECTRICAL SPECIFICATIONS
The clock rise and fall times use the standard input thresholds of 0.8V and 2.0V unless otherwise specified and the
capacitive values listed in Section 29.2.2, "AC Electrical Specifications," on page 282.
29.2.3
CAPACITIVE LOADING SPECIFICATIONS
The following table defines the maximum capacitive load validated for the buffer characteristics listed in Table 29-4, “DC
Electrical Characteristics,” on page 283.
CAPACITANCE TA = 25°C; fc = 1MHz; Vcc = 3.3 VDC
Note:
All output pins, except pin under test, tied to AC ground.
Parameter
Symbol
Limits
MIN
TYP
MAX
Unit
Input Capacitance of PCI_I and
PCI_IO pins
CIN
Note 29-2
pF
Input Capacitance of PCI_CLK pin
CIN
Note 29-2
pF
Output Load Capacitance supported
by PCI_IO, PCI_O, and PCI_OD
COUT
Note 29-2
pF
SUSCLK Input Capacitance
CIN
10
pF
Input Capacitance (all other input
pins)
CIN
10
pF
Notes
Note 29-3
Output Capacitance (all other output COUT
20
pF
Note 29-4
pins)
Note 29-2
The PCI buffers are designed to meet the defined PCI Local Bus Specification, Rev. 2.1, electrical
requirements.
Note 29-3
All input buffers can be characterized by this capacitance unless otherwise specified.
Note 29-4
All output buffers can be characterized by this capacitance unless otherwise specified.
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CEC1302
29.2.4
DC ELECTRICAL CHARACTERISTICS FOR I/O BUFFERS
TABLE 29-4:
DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
MIN
TYP
MAX
Units
Comments
PIO Type Buffer
All PIO Buffers
Internal PU/PD selected via the GPIO
Pin Control Register.
Pull-up current
IPU
39
84
162
A
Pull-down current
IPD
39
65
105
A
I Type Input Buffer
TTL Compatible Schmitt Trigger Input
Low Input Level
VILI
High Input Level
VIHI
0.3x
VCC1
0.7x
VCC1
V
3.63
Tolerance
Schmitt Trigger Hyster- VHYS
esis
V
400
V
This buffer is not 5V tolerant.
mV
O-2 mA Type Buffer
Low Output Level
VOL
High Output Level
VOH
0.4
VCC10.4
V
IOL = 2 mA
V
IOH = -2 mA
This buffer is not 5V tolerant.
Tolerance
IO-2 mA Type Buffer
_
_
_
_
_
Same characteristics as an I and an O2mA.
OD-2 mA Type Buffer
Low Output Level
VOL
0.4
V
VOL = 2 mA
Tolerance
This buffer is not 5V tolerant.
IOD-2 mA Type Buffer
_
_
_
_
_
Same characteristics as an I and an
OD-2mA.
O-4 mA Type Buffer
Low Output Level
VOL
High Output Level
VOH
0.4
VCC10.4
V
IOL = 4 mA
V
IOH = -4 mA
This buffer is not 5V tolerant.
Tolerance
IO-4 mA Type Buffer
_
_
_
_
_
Same characteristics as an I and an O4mA.
OD-4 mA Type Buffer
Low Output Level
0.4
VOL
V
VOL = 4 mA
This buffer is not 5V tolerant.
Tolerance
IOD-4 mA Type Buffer
2016 Microchip Technology Inc.
_
_
_
_
_
Same characteristics as an I and an
OD-4mA.
DS00002022B-page 283
CEC1302
TABLE 29-4:
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
Symbol
MIN
TYP
MAX
Units
Comments
O-8 mA Type Buffer
Low Output Level
VOL
High Output Level
VOH
0.4
VCC10.4
V
IOL = 8 mA
V
IOH = -8 mA
This buffer is not 5V tolerant.
Tolerance
IO-8 mA Type Buffer
_
_
_
_
_
Same characteristics as an I and an O8mA.
OD-8 mA Type Buffer
Low Output Level
0.4
VOL
V
VOL = 8 mA
This buffer is not 5V tolerant.
Tolerance
IOD-8 mA Type Buffer
_
_
_
_
_
Same characteristics as an I and an
OD-8mA.
O-12 mA Type Buffer
Low Output Level
VOL
High Output Level
VOH
0.4
V
IOL = 12mA
V
IOH = -12mA
_
_
Same characteristics as an I and an O12mA.
0.4
V
IOL = 12mA
VCC10.4
This buffer is not 5V tolerant.
Tolerance
IO-12 mA Type Buffer
_
_
_
OD-12 mA Type Buffer
Low Output Level
Tolerance
VOL
This buffer is not 5V tolerant.
IOD-12 mA Type Buffer
_
_
_
_
_
Same characteristics as an I and an
OD-12mA.
I_AN Type Buffer
I_AN Type Buffer
(Analog Input Buffer)
I_AN
Voltage range on pins:
-0.3V to +3.63V
These buffers are not 5V tolerant
buffers and they are not backdrive protected
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CEC1302
TABLE 29-4:
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
Symbol
MIN
TYP
MAX
Units
Comments
PCI_PIO Type Buffer
All PCI_PIO Buffers
Internal PU is selected via the GPIO
Pin Control Register.
Pull-up current
IPU
PCI_CLK Type Buffer
PCI_ICLK
PCI_IO Type Buffers
PCI_IO
PCI_O
PCI_I
PCI_OD Type Buffer
PCI_OD
0.6
1
1.5
mA
See PCI Local Bus Specification Rev.
2.1
These buffers are not not 5V tolerant
buffers and they are not backdrive protected.
Crystal oscillator
XTAL1 (OCLK)
The CEC1302 crystal oscillator design requires a 32.768 KHz parallel resonant crystal with
load caps in the range 4-18pF. Refer to “Application Note PCB Layout Guide for CEC1302”
for more information.
XTAL2 (ICLK)
Low Input Level
VILI
High Input Level
VILH
29.2.4.1
0.4
V
2.0
V
VIN = 0 to VCC1
Pin Leakage
Leakage characteristics for all pins is shown in the following table:
TABLE 29-5:
PIN LEAKAGE
(TA = 0oC to +70oC)
Parameter
Leakage Current
29.2.4.2
Symbol
MIN
TYP
IIL
MAX
Units
+/-2
µA
Comments
VIN=0V to VCC1
Backdrive Protection
All signal pins are Backdrive Protected except those listed in the Pin Configuration chapter as non-backdrive protected.
TABLE 29-6:
BACKDRIVE PROTECTION
(TA = 0oC to +70oC)
Parameter
Input Leakage
Symbol
IIL
2016 Microchip Technology Inc.
MIN
-2
TYP
MAX
Units
+2
µA
Comments
VIN=3.47V@VCC1=0V
DS00002022B-page 285
CEC1302
29.2.5
ADC ELECTRICAL CHARACTERISTICS
TABLE 29-7:
ADC CHARACTERISTICS
Parameter
MIN
TYP
MAX
Units
3.135
3.3
3.465
V
Resolution
–
–
10
Bits
Accuracy
–
1
–
LSB
Analog Supply Voltage, AVCC
Differential Non Linearity, DNL
-1
–
+1
LSB
-1.5
–
+1.5
LSB
Gain Error, EGAIN
-2
–
2
LSB
Offset Error, EOFFSET
-2
–
2
LSB
Conversion Time
–
–
12
s/channel
Input Impedance
3
–
–
M
Integral Non Linearity, INL
Note:
29.3
The AVCC power supply accuracy is shown as 3.3V +/- 5%.
Thermal Characteristics
TABLE 29-8:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
TJ
—
0
—
—
+125
+70
°C
°C
Consumer Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VCC1 x IVCC1 from Table 29-10
(e.g., 3.45V x 9.75mA = 33.64mW)
I/O Pin Power Dissipation:
I/O = S (({VCC1 – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
TABLE 29-9:
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Package Thermal Resistance, 144-pin WFBGA
Note 1:
TA
Symbol Typical
Max.
Unit
Notes
JA
50.0
—
°C/W
1
JC
17.0
—
°C/W
1
Junction to ambient thermal resistance, Theta-JA (JA) and Junction to case thermal resistance, Theta-JC
(JC) numbers are achieved by package simulations.
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CEC1302
29.4
Power Consumption
TABLE 29-10: VCC1 SUPPLY CURRENT, I_VCC1
VCC2
VCC1
System
State
48 MHz Ring
Oscillator
Frequency
Typical
(3.3V, 250
C)
Max
(3.465V,
700 C)
Units
On/Off
On
S5
48MHz
7.75
9.25
mA
FULL ON, 48MHz
On/Off
On
S5
12MHz
5.25
7.00
mA
FULL ON, 12MHz
On/Off
On
S5
3MHz
4.75
6.25
mA
FULL ON, 3MHz
On/Off
On
S5
1MHz
4.50
6.00
mA
FULL ON, 1MHz
On/Off
On
S5
12MHz
2.00
2.75
mA
Heavy Sleep 1
(Note 29-1)
On/Off
On
S5
Off
0.65
1.25
mA
Heavy Sleep 2
(Note 29-1)
On/Off
On
S5
Off
0.33
0.95
mA
Heavy Sleep 3
(Note 29-1)
On/Off
On
S5
Off
0.30
0.90
mA
Deepest Sleep
(Note 29-1)
Note:
Comments
FULL ON is defined as follows: The processor is not sleeping, the Core regulator and the Ring Oscillator
remain powered, and at least one block is not sleeping.
Note 29-1
The sleep states are defined in the System Sleep Control Register in the Power, Clocks and Resets
Chapter. See Table 3-9, “System Sleep Control Bit Encoding,” on page 52.
TABLE 29-11: VBAT SUPPLY CURRENT, I_VBAT (VBAT=3.0V)
Max
(3.0V,
700 C)
VCC2 VCC1
System
State
48 MHz Ring
Oscillator
Frequency
Typical
(3.0V, 250
C)
Off
Off
S5
Off
2.50
6.50
uA
32kHz crystal oscillator
Off
Off
S5
Off
2.00
6.00
uA
External 32kHz clock on XTAL2 pin
Units
Comments
TABLE 29-12: VBAT SUPPLY CURRENT, I_VBAT (VBAT=3.3V)
Max
(3.3V,
700 C)
VCC2 VCC1
System
State
48 MHz Ring
Oscillator
Frequency
Typical
(3.3V, 250
C)
Off
Off
S5
Off
2.75
6.75
uA
32kHz crystal oscillator
Off
Off
S5
Off
2.50
6.25
uA
External 32kHz clock on XTAL2 pin
2016 Microchip Technology Inc.
Units
Comments
DS00002022B-page 287
CEC1302
30.0
TIMING DIAGRAMS
Note:
30.1
Timing values are preliminary and may change after characterization.
Voltage Thresholds and Power Good Timing
30.1.1
VCC1_RST# TIMING
FIGURE 30-1:
VCC1_RST# TIMING
VCC1
V TH1
G lit c h p r o t e c t e d
S ig n a l o u t p u t
U n d e fin e d
V TH2
V TH2
F o r c e d to lo g ic ‘0 ’
F u n c tio n a l
V TH1
F o r c e d to lo g ic ‘0 ’
t1
U n d e fin e d
t2
V C C 1 G D (in te r n a l)
t3
V C C 1 _ R S T # P in
TABLE 30-1:
VCC1_RST# TIMING
Parameters
Symbol
MIN
TYP
MAX
Unit
VCC1 Threshold for Pin Glitch Protection
active
VTH1
0.9
1
1.1
V
VCC1 Power Good Threshold
VTH2
2.16
2.4
2.64
V
VCC1 Rise Time (Off to VCC1 =VThreshold)
VRise
200
s
VCC1 Fall Time (VCC1 =VThreshold) to Off
VFall
200
s
VCC1 > VTH2 to VCC1GD (internal) asserted t1
600
s
VCC1 < VTH2 to VCC1GD (internal) deasserted and VCC1_RST# pin asserted
100
ns
1
ms
t2
VCC1 > VTH2 to VCC1_RST# pin deasserted t3
Note 30-1
Notes
Note 30-1
The ARM starts executing instructions when EC_PROC_ RESET deasserts, which has the same
timing as t3.
FIGURE 30-2:
VCC1_RST# RISE TIME
t1
V C C 1 _ R S T # P in
TABLE 30-2:
VCC1_RST# RISE TIME
Parameters
Symbol
MIN
TYP
MAX
Units
Notes
VCC1_RST# Rise Time
t1
2.65
s
Note 30-1
Note 30-1
This corresponds to the time 2.65us (min) after the VCC1_RST# pin is released, the VCC1_RST#
pin input is sampled. See Section 3.6.1, "Integrated Vcc1 Power On Reset (VCC1_RST#)," on
page 45.
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CEC1302
30.1.2
VBAT THRESHOLDS AND VBAT_POR
FIGURE 30-3:
VBAT THRESHOLDS AND VBAT_POR
VBAT TOD(master-clk) + Tprop(clk) +TOD(slave) + Tprop(slave data) + TIS(master).
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CEC1302
30.12 Serial Peripheral Interface (SPI) Timings
FIGURE 30-14:
SPI CLOCK TIMING
Tr
Tf
SPICLK
Th
Tl
Tp
TABLE 30-14: SPI CLOCK TIMING PARAMETERS
NAME
DESCRIPTION
MIN
TYP
MAX
UNITS
Tr
SPI Clock Rise Time. Measured
from 10% to 90%.
10% of SPCLK ns
Period
Tf
SPI Clock Fall Time. Measured
from 90% to 10%.
10% of SPCLK ns
Period
Th/Tl
SPI Clock High Time/SPI Clock
Low Time
40% of SPCLK 50% of SPCLK 60% of SPCLK ns
Period
Period
Period
Tp
SPI Clock Period – As selected 20.8 (Note 3062492.25
ns
by SPI Clock Generator Register 1)
This timing value applies when the 48MHz ring oscillator is at its 48MHz operating frequency (with
32 kHz present after frequency lock to 48MHz).
Note 30-1
FIGURE 30-15:
SPI SETUP AND HOLD TIMES, CLKPOL=0, TCLKPH=0, RCLKPH=0
Setup and Hold Times for
Full‐Duplex and Bidrectional Modes
SPCLK
(CLKPOL = 0,
TCLKPH = 0,
RCLKPH = 0)
T1
SPDOUT
T2
SPDIN
T3
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CEC1302
FIGURE 30-16:
SPI SETUP AND HOLD TIMES, CLKPOL=0, TCLKPH=0, RCLKPH=1
Setup and Hold Times for
Full‐Duplex and Bidrectional Modes
SPCLK
(CLKPOL = 0,
TCLKPH = 0,
RCLKPH = 1)
T1
SPDOUT
T2
SPDIN
T3
TABLE 30-15: SPI SETUP AND HOLD TIMES PARAMETERS
NAME
DESCRIPTION
MIN
TYP
MAX
T1
Data Output Delay
T2
Data IN Setup Time
10
ns
T3
Data IN Hold Time
0
ns
30.12.1
5
UNITS
ns
SPI INTERFACE TIMINGS
The following timing diagrams represent a single-byte transfer over the SPI interface using different SPCLK phase settings. Data bits are transmitted in bit order starting with the MSB (LSBF=‘0’) or the LSB (LSBF=‘1’). See the SPI Control
Register for information on the LSBF bit. The CS signal in each diagram is a generic bit-controlled chip select signal
required by most peripheral devices. This signal and additional chip selects can be GPIO controlled. Note that these
timings for Full Duplex Mode are also applicable to Half Duplex (or Bi-directional) mode.
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CEC1302
FIGURE 30-17:
INTERFACE TIMING, FULL DUPLEX MODE (TCLKPH = 0, RCLKPH = 0)
SPCLK (CLKPOL = 0)
SPCLK (CLKPOL = 1)
SPDOUT
(TCLKPH = 0)
SPDIN
(RCLKPH = 0)
CS (GPIO)
FIRST DATA BIT SAMPLED BY
MASTER AND SLAVE
LAST DATA BIT SAMPLED BY
MASTER AND SLAVE
.
In this mode, data is available immediately when a device is selected and is sampled on the first and following odd
SPCLK edges by the master and slave.
FIGURE 30-18:
SPI INTERFACE TIMING, FULL DUPLEX MODE (TCLKPH = 1, RCLKPH = 0)
SPCLK (CLKPOL = 0)
SPCLK (CLKPOL = 1)
SPDOUT
(TCLKPH = 1)
SPDIN
(RCLKPH = 0)
CS (GPIO)
FIRST DATA BIT SAMPLED BY
SLAVE
FIRST DATA BIT SAMPLED BY
MASTER
LAST DATA BIT SAMPLED BY
MASTER
LAST DATA BIT SAMPLED BY
SLAVE
.
In this mode, the master requires an initial SPCLK edge before data is available. The data from slave is available immediately when the slave device is selected. The data is sampled on the first and following odd edges by the master. The
data is sampled on the second and following even SPCLK edges by the slave.
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CEC1302
FIGURE 30-19:
SPI INTERFACE TIMING, FULL DUPLEX MODE (TCLKPH = 0, RCLKPH = 1)
SPCLK (CLKPOL = 0)
SPCLK (CLKPOL = 1)
SPDOUT
(TCLKPH = 0)
SPDIN
(RCLKPH = 1)
CS (GPIO)
FIRST DATA BIT SAMPLED BY
MASTER
FIRST DATA BIT SAMPLED BY
SLAVE
LAST DATA BIT SAMPLED BY
SLAVE
LAST DATA BIT SAMPLED BY
MASTER
In this mode, the data from slave is available immediately when the slave device is selected. The slave device requires
an initial SPCLK edge before data is available. The data is sampled on the second and following even SPCLK edges
by the master. The data is sampled on the first and following odd edges by the slave.
FIGURE 30-20:
SPI INTERFACE TIMING - FULL DUPLEX MODE (TCLKPH = 1, RCLKPH = 1)
SPCLK (CLKPOL = 0)
SPCLK (CLKPOL = 1)
SPDOUT
(TCLKPH = 1)
SPDIN
(RCLKPH = 1)
CS (GPIO)
FIRST DATA BIT SAMPLED BY
MASTER AND SLAVE
LAST DATA BIT SAMPLED BY
MASTER AND SLAVE
In this mode, the master and slave require an initial SPCLK edge before data is available. Data is sampled on the second
and following even SPCLK edges by the master and slave.
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CEC1302
30.13 Serial Debug Port Timing
FIGURE 30-21:
SERIAL DEBUG PORT TIMING PARAMETERS
TFDP Clock
tP
tOD
fCLK
tOH
tCLK-L
tCLK-H
TFDP Data
TABLE 30-16: SERIAL DEBUG PORT INTERFACE TIMING PARAMETERS
Name
Description
fclk
TFDP Clock frequency (Note 30-2)
tP
TFDP Clock Period.
MIN
6
MAX
Units
-
24
MHz
s
1/fclk
tOD
TFDP Data output delay after falling edge of MSCLK.
tOH
TFDP Data hold time after falling edge of TFDP Clock
tP - tOD
TFDP Clock Low Time
tP/2 - 3
tCLK-L
TYP
5
nsec
nsec
tP/2 + 3
nsec
tCLK-H TFDP Clock high Time (see Note 30-2)
tP/2 - 3
tP/2 + 3
nsec
Note 30-2
When the clock divider for the embedded controller is an odd number value greater than 2h, then
tCLK-L = tCLK-H + 15 ns. When the clock divider for the embedded controller is 0h, 1h, or an even
number value greater than 2h, then tCLK-L = tCLK-H.
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CEC1302
30.14 JTAG Interface Timing
FIGURE 30-22:
JTAG POWER-UP & ASYNCHRONOUS RESET TIMING
2.8V
VCC1 Power
tsu
tpw
JTAG_RST#
fclk
JTAG_CLK
FIGURE 30-23:
JTAG SETUP & HOLD PARAMETERS
JT A G _ C L K
tO D
tO H
JT A G _ T D O
t IS
t IH
JT A G _ T D I
TABLE 30-17: JTAG INTERFACE TIMING PARAMETERS
Name
Description
tsu
JTAG_RST# de-assertion after VCC1 power is applied
tpw
JTAG_RST# assertion pulse width
MIN
TYP
MAX
Units
5
ms
500
nsec
fclk
JTAG_CLK frequency (see note)
tOD
TDO output delay after falling edge of TCLK.
tOH
TDO hold time after falling edge of TCLK
1 TCLK - tOD
nsec
tIS
TDI setup time before rising edge of TCLK.
5
nsec
tIH
TDI hold time after rising edge of TCLK.
5
nsec
Note:
5
48
MHz
10
nsec
fclk is the maximum frequency to access a JTAG Register.
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CEC1302
31.0
MEMORY MAP
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
0
32K ROM
0
32K ROM
32K ROM
100000
128K SRAM
0
128K SRAM
128K SRAM
40000400
Watchdog Timer Interface
0
WDT Registers
WDT Load Register
40000404
Watchdog Timer Interface
0
WDT Registers
WDT Control Register
40000408
Watchdog Timer Interface
0
WDT Registers
WDT Kick Register
4000040C
Watchdog Timer Interface
0
WDT Registers
WDT Count Register
40000C00
Basic Timer
0
Basic_Timer_EC_Only
Timer Count
40000C04
Basic Timer
0
Basic_Timer_EC_Only
Timer Preload
40000C08
Basic Timer
0
Basic_Timer_EC_Only
Timer Status
40000C0C
Basic Timer
0
Basic_Timer_EC_Only
Timer Interrupt Enable
40000C10
Basic Timer
0
Basic_Timer_EC_Only
Timer Control
40000C20
Basic Timer
1
Basic_Timer_EC_Only
Timer Count
40000C24
Basic Timer
1
Basic_Timer_EC_Only
Timer Preload
40000C28
Basic Timer
1
Basic_Timer_EC_Only
Timer Status
40000C2C
Basic Timer
1
Basic_Timer_EC_Only
Timer Interrupt Enable
40000C30
Basic Timer
1
Basic_Timer_EC_Only
Timer Control
40000C40
Basic Timer
2
Basic_Timer_EC_Only
Timer Count
40000C44
Basic Timer
2
Basic_Timer_EC_Only
Timer Preload
40000C48
Basic Timer
2
Basic_Timer_EC_Only
Timer Status
40000C4C
Basic Timer
2
Basic_Timer_EC_Only
Timer Interrupt Enable
40000C50
Basic Timer
2
Basic_Timer_EC_Only
Timer Control
40000C60
Basic Timer
3
Basic_Timer_EC_Only
Timer Count
40000C64
Basic Timer
3
Basic_Timer_EC_Only
Timer Preload
40000C68
Basic Timer
3
Basic_Timer_EC_Only
Timer Status
40000C6C
Basic Timer
3
Basic_Timer_EC_Only
Timer Interrupt Enable
40000C70
Basic Timer
3
Basic_Timer_EC_Only
Timer Control
40000C80
Basic Timer
4
Basic_Timer_EC_Only
Timer Count
40000C84
Basic Timer
4
Basic_Timer_EC_Only
Timer Preload
40000C88
Basic Timer
4
Basic_Timer_EC_Only
Timer Status
40000C8C
Basic Timer
4
Basic_Timer_EC_Only
Timer Interrupt Enable
40000C90
Basic Timer
4
Basic_Timer_EC_Only
Timer Control
40000CA0
Basic Timer
5
Basic_Timer_EC_Only
Timer Count
40000CA4
Basic Timer
5
Basic_Timer_EC_Only
Timer Preload
40000CA8
Basic Timer
5
Basic_Timer_EC_Only
Timer Status
40000CAC
Basic Timer
5
Basic_Timer_EC_Only
Timer Interrupt Enable
40000CB0
Basic Timer
5
Basic_Timer_EC_Only
Timer Control
40001800
SMB Device Interface
0
SMB_EC_Only
Status Register
40001800
SMB Device Interface
0
SMB_EC_Only
Control Register
DS00002022B-page 306
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40001801
SMB Device Interface
0
SMB_EC_Only
Reserved
40001804
SMB Device Interface
0
SMB_EC_Only
Own Address Register
40001806
SMB Device Interface
0
SMB_EC_Only
Reserved
40001808
SMB Device Interface
0
SMB_EC_Only
Data
40001809
SMB Device Interface
0
SMB_EC_Only
Reserved
4000180C
SMB Device Interface
0
SMB_EC_Only
SMBus Master Command
Register
40001810
SMB Device Interface
0
SMB_EC_Only
SMBus Slave Command
Register
40001814
SMB Device Interface
0
SMB_EC_Only
PEC Register
40001815
SMB Device Interface
0
SMB_EC_Only
Reserved
40001818
SMB Device Interface
0
SMB_EC_Only
DATA_TIMING2
40001819
SMB Device Interface
0
SMB_EC_Only
Reserved
40001820
SMB Device Interface
0
SMB_EC_Only
Completion Register
40001824
SMB Device Interface
0
SMB_EC_Only
Idle Scaling Register
40001828
SMB Device Interface
0
SMB_EC_Only
Configuration Register
4000182C
SMB Device Interface
0
SMB_EC_Only
Bus Clock Register
4000182E
SMB Device Interface
0
SMB_EC_Only
Reserved
40001830
SMB Device Interface
0
SMB_EC_Only
Block ID Register
40001831
SMB Device Interface
0
SMB_EC_Only
Reserved
40001834
SMB Device Interface
0
SMB_EC_Only
Revision Register
40001835
SMB Device Interface
0
SMB_EC_Only
Reserved
40001838
SMB Device Interface
0
SMB_EC_Only
Bit-Bang Control Register
40001839
SMB Device Interface
0
SMB_EC_Only
Reserved
4000183C
SMB Device Interface
0
SMB_EC_Only
Clock Sync
40001840
SMB Device Interface
0
SMB_EC_Only
Data Timing Register
40001844
SMB Device Interface
0
SMB_EC_Only
Time-Out Scaling Register
40001848
SMB Device Interface
0
SMB_EC_Only
SMBus Slave Transmit
Buffer Register
40001849
SMB Device Interface
0
SMB_EC_Only
Reserved
4000184C
SMB Device Interface
0
SMB_EC_Only
SMBus Slave Receive Buffer Register
4000184D
SMB Device Interface
0
SMB_EC_Only
Reserved
40001850
SMB Device Interface
0
SMB_EC_Only
SMBus Master Transmit
Bufer Register
40001851
SMB Device Interface
0
SMB_EC_Only
Reserved
40001854
SMB Device Interface
0
SMB_EC_Only
SMBus Master Receive
Buffer Register
40001855
SMB Device Interface
0
SMB_EC_Only
Reserved
40002400
DMA
0
DMA Main
DMA Main Control Register
40002401
DMA
0
DMA Main
DMA Reserved
40002404
DMA
0
DMA Main
DMA Data Register
40002410
DMA
0
DMA_CH0
DMA Activate Register
40002414
DMA
0
DMA_CH0
DMA Memory Start
Address Register
2016 Microchip Technology Inc.
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CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40002418
DMA
0
DMA_CH0
DMA Memory End Address
Register
4000241C
DMA
0
DMA_CH0
AHB Address Register
40002420
DMA
0
DMA_CH0
DMA Control Register
40002424
DMA
0
DMA_CH0
DMA Channel Interrupt
Status
40002428
DMA
0
DMA_CH0
DMA Channel Interrupt
Enable
4000242C
DMA
0
DMA_CH0
DMA Test Register
40002430
DMA
0
DMA_CH1
DMA Activate Register
40002434
DMA
0
DMA_CH1
DMA Memory Start
Address Register
40002438
DMA
0
DMA_CH1
DMA Memory End Address
Register
4000243C
DMA
0
DMA_CH1
AHB Address Register
40002440
DMA
0
DMA_CH1
DMA Control Register
40002444
DMA
0
DMA_CH1
DMA Channel Interrupt
Status
40002448
DMA
0
DMA_CH1
DMA Channel Interrupt
Enable
4000244C
DMA
0
DMA_CH1
DMA Test Register
40002450
DMA
0
DMA_CH2
DMA Activate Register
40002454
DMA
0
DMA_CH2
DMA Memory Start
Address Register
40002458
DMA
0
DMA_CH2
DMA Memory End Address
Register
4000245C
DMA
0
DMA_CH2
AHB Address Register
40002460
DMA
0
DMA_CH2
DMA Control Register
40002464
DMA
0
DMA_CH2
DMA Channel Interrupt
Status
40002468
DMA
0
DMA_CH2
DMA Channel Interrupt
Enable
4000246C
DMA
0
DMA_CH2
DMA Test Register
40002470
DMA
0
DMA_CH3
DMA Activate Register
40002474
DMA
0
DMA_CH3
DMA Memory Start
Address Register
40002478
DMA
0
DMA_CH3
DMA Memory End Address
Register
4000247C
DMA
0
DMA_CH3
AHB Address Register
40002480
DMA
0
DMA_CH3
DMA Control Register
40002484
DMA
0
DMA_CH3
DMA Channel Interrupt
Status
40002488
DMA
0
DMA_CH3
DMA Channel Interrupt
Enable
4000248C
DMA
0
DMA_CH3
DMA Test Register
40002490
DMA
0
DMA_CH4
DMA Activate Register
DS00002022B-page 308
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40002494
DMA
0
DMA_CH4
DMA Memory Start
Address Register
40002498
DMA
0
DMA_CH4
DMA Memory End Address
Register
4000249C
DMA
0
DMA_CH4
AHB Address Register
400024A0
DMA
0
DMA_CH4
DMA Control Register
400024A4
DMA
0
DMA_CH4
DMA Channel Interrupt
Status
400024A8
DMA
0
DMA_CH4
DMA Channel Interrupt
Enable
400024AC
DMA
0
DMA_CH4
DMA Test Register
400024B0
DMA
0
DMA_CH5
DMA Activate Register
400024B4
DMA
0
DMA_CH5
DMA Memory Start
Address Register
400024B8
DMA
0
DMA_CH5
DMA Memory End Address
Register
400024BC
DMA
0
DMA_CH5
AHB Address Register
400024C0
DMA
0
DMA_CH5
DMA Control Register
400024C4
DMA
0
DMA_CH5
DMA Channel Interrupt
Status
400024C8
DMA
0
DMA_CH5
DMA Channel Interrupt
Enable
400024CC
DMA
0
DMA_CH5
DMA Test Register
400024D0
DMA
0
DMA_CH6
DMA Activate Register
400024D4
DMA
0
DMA_CH6
DMA Memory Start
Address Register
400024D8
DMA
0
DMA_CH6
DMA Memory End Address
Register
400024DC
DMA
0
DMA_CH6
AHB Address Register
400024E0
DMA
0
DMA_CH6
DMA Control Register
400024E4
DMA
0
DMA_CH6
DMA Channel Interrupt
Status
400024E8
DMA
0
DMA_CH6
DMA Channel Interrupt
Enable
400024EC
DMA
0
DMA_CH6
DMA Test Register
400024F0
DMA
0
DMA_CH7
DMA Activate Register
400024F4
DMA
0
DMA_CH7
DMA Memory Start
Address Register
400024F8
DMA
0
DMA_CH7
DMA Memory End Address
Register
400024FC
DMA
0
DMA_CH7
AHB Address Register
40002500
DMA
0
DMA_CH7
DMA Control Register
40002504
DMA
0
DMA_CH7
DMA Channel Interrupt
Status
40002508
DMA
0
DMA_CH7
DMA Channel Interrupt
Enable
4000250C
DMA
0
DMA_CH7
DMA Test Register
2016 Microchip Technology Inc.
DS00002022B-page 309
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40002510
DMA
0
DMA_CH8
DMA Activate Register
40002514
DMA
0
DMA_CH8
DMA Memory Start
Address Register
40002518
DMA
0
DMA_CH8
DMA Memory End Address
Register
4000251C
DMA
0
DMA_CH8
AHB Address Register
40002520
DMA
0
DMA_CH8
DMA Control Register
40002524
DMA
0
DMA_CH8
DMA Channel Interrupt
Status
40002528
DMA
0
DMA_CH8
DMA Channel Interrupt
Enable
4000252C
DMA
0
DMA_CH8
DMA Test Register
40002530
DMA
0
DMA_CH9
DMA Activate Register
40002534
DMA
0
DMA_CH9
DMA Memory Start
Address Register
40002538
DMA
0
DMA_CH9
DMA Memory End Address
Register
4000253C
DMA
0
DMA_CH9
AHB Address Register
40002540
DMA
0
DMA_CH9
DMA Control Register
40002544
DMA
0
DMA_CH9
DMA Channel Interrupt
Status
40002548
DMA
0
DMA_CH9
DMA Channel Interrupt
Enable
4000254C
DMA
0
DMA_CH9
DMA Test Register
40002550
DMA
0
DMA_CH10
DMA Activate Register
40002554
DMA
0
DMA_CH10
DMA Memory Start
Address Register
40002558
DMA
0
DMA_CH10
DMA Memory End Address
Register
4000255C
DMA
0
DMA_CH10
AHB Address Register
40002560
DMA
0
DMA_CH10
DMA Control Register
40002564
DMA
0
DMA_CH10
DMA Channel Interrupt
Status
40002568
DMA
0
DMA_CH10
DMA Channel Interrupt
Enable
4000256C
DMA
0
DMA_CH10
DMA Test Register
40002570
DMA
0
DMA_CH11
DMA Activate Register
40002574
DMA
0
DMA_CH11
DMA Memory Start
Address Register
40002578
DMA
0
DMA_CH11
DMA Memory End Address
Register
4000257C
DMA
0
DMA_CH11
AHB Address Register
40002580
DMA
0
DMA_CH11
DMA Control Register
40002584
DMA
0
DMA_CH11
DMA Channel Interrupt
Status
40002588
DMA
0
DMA_CH11
DMA Channel Interrupt
Enable
DS00002022B-page 310
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000258C
DMA
0
DMA_CH11
DMA Test Register
40005800
PWM
0
PWM_EC_Only
PWM Counter ON Time
Register
40005804
PWM
0
PWM_EC_Only
PWM Counter OFF Time
Register
40005808
PWM
0
PWM_EC_Only
PWM Configuration Register
4000580C
PWM
0
PWM_EC_Only
Reserved
40005810
PWM
1
PWM_EC_Only
PWM Counter ON Time
Register
40005814
PWM
1
PWM_EC_Only
PWM Counter OFF Time
Register
40005818
PWM
1
PWM_EC_Only
PWM Configuration Register
4000581C
PWM
1
PWM_EC_Only
Reserved
40005820
PWM
2
PWM_EC_Only
PWM Counter ON Time
Register
40005824
PWM
2
PWM_EC_Only
PWM Counter OFF Time
Register
40005828
PWM
2
PWM_EC_Only
PWM Configuration Register
4000582C
PWM
2
PWM_EC_Only
Reserved
40005830
PWM
3
PWM_EC_Only
PWM Counter ON Time
Register
40005834
PWM
3
PWM_EC_Only
PWM Counter OFF Time
Register
40005838
PWM
3
PWM_EC_Only
PWM Configuration Register
4000583C
PWM
3
PWM_EC_Only
Reserved
40006000
TACH
0
TACH_EC_ONLY
TACH Control Register
40006004
TACH
0
TACH_EC_ONLY
TACH Status Register
40006008
TACH
0
TACH_EC_ONLY
TACH High Limit Register
4000600C
TACH
0
TACH_EC_ONLY
TACH Low Limit Register
40006010
TACH
1
TACH_EC_ONLY
TACH Control Register
40006014
TACH
1
TACH_EC_ONLY
TACH Status Register
40006018
TACH
1
TACH_EC_ONLY
TACH High Limit Register
4000601C
TACH
1
TACH_EC_ONLY
TACH Low Limit Register
40007C00
ADC
0
ADC Registers
ADC Control Register
40007C04
ADC
0
ADC Registers
ADC Delay Register
40007C08
ADC
0
ADC Registers
ADC Status Register
40007C0C
ADC
0
ADC Registers
ADC Single Register
40007C10
ADC
0
ADC Registers
ADC Repeat Register
40007C14
ADC
0
ADC Registers
ADC Channel 0 Reading
Registers
40007C18
ADC
0
ADC Registers
ADC Channel 1 Reading
Registers
2016 Microchip Technology Inc.
DS00002022B-page 311
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40007C1C
ADC
0
ADC Registers
ADC Channel 2 Reading
Registers
40007C20
ADC
0
ADC Registers
ADC Channel 3 Reading
Registers
40007C24
ADC
0
ADC Registers
ADC Channel 4 Reading
Registers
40007C54
ADC
0
ADC Registers
ADC Test Register
40007C58
ADC
0
ADC Registers
ADC Test Register
40007C78
ADC
0
ADC Registers
ADC Test Register
40007C7C
ADC
0
ADC Registers
ADC Configuration Register
40008C00
Trace FIFO Debug Port
0
TFDP
Data
40008C04
Trace FIFO Debug Port
0
TFDP
Control
40009400
EC GP-SPI
0
GP-SPI_EC_Only
SPI Enable Register
40009404
EC GP-SPI
0
GP-SPI_EC_Only
SPI Control Register
40009408
EC GP-SPI
0
GP-SPI_EC_Only
SPI Status Register
4000940C
EC GP-SPI
0
GP-SPI_EC_Only
SPI TX_Data Register
40009410
EC GP-SPI
0
GP-SPI_EC_Only
SPI RX_Data Register
40009414
EC GP-SPI
0
GP-SPI_EC_Only
SPI Clock Control Register
40009418
EC GP-SPI
0
GP-SPI_EC_Only
SPI Clock Generator Register
40009480
EC GP-SPI
1
GP-SPI_EC_Only
SPI Enable Register
40009484
EC GP-SPI
1
GP-SPI_EC_Only
SPI Control Register
40009488
EC GP-SPI
1
GP-SPI_EC_Only
SPI Status Register
4000948C
EC GP-SPI
1
GP-SPI_EC_Only
SPI TX_Data Register
40009490
EC GP-SPI
1
GP-SPI_EC_Only
SPI RX_Data Register
40009494
EC GP-SPI
1
GP-SPI_EC_Only
SPI Clock Control Register
40009498
EC GP-SPI
1
GP-SPI_EC_Only
SPI Clock Generator Register
40009800
Hibernation Timer
0
Registers
HTimer x Preload Register
40009804
Hibernation Timer
0
Registers
Hibernation Timer x Control
Register
40009808
Hibernation Timer
0
Registers
Hibernation Timer x Count
Register
40009C00
Keyboard Matrix Scan
Support
0
Registers
Reserved
40009C04
Keyboard Matrix Scan
Support
0
Registers
KSO Select Register
40009C08
Keyboard Matrix Scan
Support
0
Registers
KSI Input Register
40009C0C
Keyboard Matrix Scan
Support
0
Registers
KSI Status Register
40009C10
Keyboard Matrix Scan
Support
0
Registers
KSI Interrupt Enable Register
40009C14
Keyboard Matrix Scan
Support
0
Registers
Keyscan Extended Control
Register
4000A000
RPM Fan Control
0
RPM_FAN
Fan Setting
DS00002022B-page 312
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000A001
RPM Fan Control
0
RPM_FAN
PWM Divide
4000A002
RPM Fan Control
0
RPM_FAN
Fan Configuration 1
4000A003
RPM Fan Control
0
RPM_FAN
Fan Configuration 2
4000A004
RPM Fan Control
0
RPM_FAN
MCHP Reserved
4000A005
RPM Fan Control
0
RPM_FAN
Gain
4000A006
RPM Fan Control
0
RPM_FAN
Fan Spin Up Configuration
4000A007
RPM Fan Control
0
RPM_FAN
Fan Step
4000A008
RPM Fan Control
0
RPM_FAN
Fan Minimum Drive
4000A009
RPM Fan Control
0
RPM_FAN
Valid Tach Count
4000A00A
RPM Fan Control
0
RPM_FAN
Fan Drive Fail Band Low
Byte
4000A00B
RPM Fan Control
0
RPM_FAN
Fan Drive Fail Band High
Byte
4000A00C
RPM Fan Control
0
RPM_FAN
Tach Target Low Byte
4000A00D
RPM Fan Control
0
RPM_FAN
Tach Target High Byte
4000A00E
RPM Fan Control
0
RPM_FAN
Tach Reading Low Byte
4000A00F
RPM Fan Control
0
RPM_FAN
Tach Reading High Byte
4000A010
RPM Fan Control
0
RPM_FAN
PWM Driver Base Frequency
4000A011
RPM Fan Control
0
RPM_FAN
Fan Status
4000A012
RPM Fan Control
0
RPM_FAN
Reserved
4000A014
RPM Fan Control
0
RPM_FAN
RPM Fan Test
4000A015
RPM Fan Control
0
RPM_FAN
RPM Fan Test1
4000A016
RPM Fan Control
0
RPM_FAN
RPM Fan Test2
4000A017
RPM Fan Control
0
RPM_FAN
RPM Fan Test3
4000A400
VBAT Registers
0
VBAT_EC_REG_BANK
Power-Fail and Reset Status Register
4000A404
VBAT Registers
0
VBAT_EC_REG_BANK
Control
4000A800
VBAT Powered RAM
0
Registers
VBAT Backed Memory
4000AC00
SMB Device Interface
1
SMB_EC_Only
Control Register
4000AC00
SMB Device Interface
1
SMB_EC_Only
Status Register
4000AC01
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC04
SMB Device Interface
1
SMB_EC_Only
Own Address Register
4000AC06
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC08
SMB Device Interface
1
SMB_EC_Only
Data
4000AC09
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC0C
SMB Device Interface
1
SMB_EC_Only
SMBus Master Command
Register
4000AC10
SMB Device Interface
1
SMB_EC_Only
SMBus Slave Command
Register
4000AC14
SMB Device Interface
1
SMB_EC_Only
PEC Register
4000AC15
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC18
SMB Device Interface
1
SMB_EC_Only
DATA_TIMING2
4000AC19
SMB Device Interface
1
SMB_EC_Only
Reserved
2016 Microchip Technology Inc.
DS00002022B-page 313
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000AC20
SMB Device Interface
1
SMB_EC_Only
Completion Register
4000AC24
SMB Device Interface
1
SMB_EC_Only
Idle Scaling Register
4000AC28
SMB Device Interface
1
SMB_EC_Only
Configuration Register
4000AC2C
SMB Device Interface
1
SMB_EC_Only
Bus Clock Register
4000AC2E
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC30
SMB Device Interface
1
SMB_EC_Only
Block ID Register
4000AC31
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC34
SMB Device Interface
1
SMB_EC_Only
Revision Register
4000AC35
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC38
SMB Device Interface
1
SMB_EC_Only
Bit-Bang Control Register
4000AC39
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC3C
SMB Device Interface
1
SMB_EC_Only
Clock Sync
4000AC40
SMB Device Interface
1
SMB_EC_Only
Data Timing Register
4000AC44
SMB Device Interface
1
SMB_EC_Only
Time-Out Scaling Register
4000AC48
SMB Device Interface
1
SMB_EC_Only
SMBus Slave Transmit
Buffer Register
4000AC49
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC4C
SMB Device Interface
1
SMB_EC_Only
SMBus Slave Receive Buffer Register
4000AC4D
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC50
SMB Device Interface
1
SMB_EC_Only
SMBus Master Transmit
Bufer Register
4000AC51
SMB Device Interface
1
SMB_EC_Only
Reserved
4000AC54
SMB Device Interface
1
SMB_EC_Only
SMBus Master Receive
Buffer Register
4000AC55
SMB Device Interface
1
SMB_EC_Only
Reserved
4000B000
SMB Device Interface
2
SMB_EC_Only
Control Register
4000B000
SMB Device Interface
2
SMB_EC_Only
Status Register
4000B001
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B004
SMB Device Interface
2
SMB_EC_Only
Own Address Register
4000B006
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B008
SMB Device Interface
2
SMB_EC_Only
Data
4000B009
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B00C
SMB Device Interface
2
SMB_EC_Only
SMBus Master Command
Register
4000B010
SMB Device Interface
2
SMB_EC_Only
SMBus Slave Command
Register
4000B014
SMB Device Interface
2
SMB_EC_Only
PEC Register
4000B015
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B018
SMB Device Interface
2
SMB_EC_Only
DATA_TIMING2
4000B019
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B020
SMB Device Interface
2
SMB_EC_Only
Completion Register
4000B024
SMB Device Interface
2
SMB_EC_Only
Idle Scaling Register
4000B028
SMB Device Interface
2
SMB_EC_Only
Configuration Register
DS00002022B-page 314
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000B02C
SMB Device Interface
2
SMB_EC_Only
Bus Clock Register
4000B02E
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B030
SMB Device Interface
2
SMB_EC_Only
Block ID Register
4000B031
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B034
SMB Device Interface
2
SMB_EC_Only
Revision Register
4000B035
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B038
SMB Device Interface
2
SMB_EC_Only
Bit-Bang Control Register
4000B039
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B03C
SMB Device Interface
2
SMB_EC_Only
Clock Sync
4000B040
SMB Device Interface
2
SMB_EC_Only
Data Timing Register
4000B044
SMB Device Interface
2
SMB_EC_Only
Time-Out Scaling Register
4000B048
SMB Device Interface
2
SMB_EC_Only
SMBus Slave Transmit
Buffer Register
4000B049
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B04C
SMB Device Interface
2
SMB_EC_Only
SMBus Slave Receive Buffer Register
4000B04D
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B050
SMB Device Interface
2
SMB_EC_Only
SMBus Master Transmit
Bufer Register
4000B051
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B054
SMB Device Interface
2
SMB_EC_Only
SMBus Master Receive
Buffer Register
4000B055
SMB Device Interface
2
SMB_EC_Only
Reserved
4000B400
SMB Device Interface
3
SMB_EC_Only
Control Register
4000B400
SMB Device Interface
3
SMB_EC_Only
Status Register
4000B401
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B404
SMB Device Interface
3
SMB_EC_Only
Own Address Register
4000B406
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B408
SMB Device Interface
3
SMB_EC_Only
Data
4000B409
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B40C
SMB Device Interface
3
SMB_EC_Only
SMBus Master Command
Register
4000B410
SMB Device Interface
3
SMB_EC_Only
SMBus Slave Command
Register
4000B414
SMB Device Interface
3
SMB_EC_Only
PEC Register
4000B415
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B418
SMB Device Interface
3
SMB_EC_Only
DATA_TIMING2
4000B419
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B420
SMB Device Interface
3
SMB_EC_Only
Completion Register
4000B424
SMB Device Interface
3
SMB_EC_Only
Idle Scaling Register
4000B428
SMB Device Interface
3
SMB_EC_Only
Configuration Register
4000B42C
SMB Device Interface
3
SMB_EC_Only
Bus Clock Register
4000B42E
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B430
SMB Device Interface
3
SMB_EC_Only
Block ID Register
2016 Microchip Technology Inc.
DS00002022B-page 315
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000B431
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B434
SMB Device Interface
3
SMB_EC_Only
Revision Register
4000B435
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B438
SMB Device Interface
3
SMB_EC_Only
Bit-Bang Control Register
4000B439
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B43C
SMB Device Interface
3
SMB_EC_Only
Clock Sync
4000B440
SMB Device Interface
3
SMB_EC_Only
Data Timing Register
4000B444
SMB Device Interface
3
SMB_EC_Only
Time-Out Scaling Register
4000B448
SMB Device Interface
3
SMB_EC_Only
SMBus Slave Transmit
Buffer Register
4000B449
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B44C
SMB Device Interface
3
SMB_EC_Only
SMBus Slave Receive Buffer Register
4000B44D
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B450
SMB Device Interface
3
SMB_EC_Only
SMBus Master Transmit
Bufer Register
4000B451
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B454
SMB Device Interface
3
SMB_EC_Only
SMBus Master Receive
Buffer Register
4000B455
SMB Device Interface
3
SMB_EC_Only
Reserved
4000B800
LED
0
EC-Only Registers
LED Configuration
4000B804
LED
0
EC-Only Registers
LED Limits
4000B808
LED
0
EC-Only Registers
LED Delay
4000B80C
LED
0
EC-Only Registers
LED Update Stepsize
4000B810
LED
0
EC-Only Registers
LED Update Interval
4000B900
LED
1
EC-Only Registers
LED Configuration
4000B904
LED
1
EC-Only Registers
LED Limits
4000B908
LED
1
EC-Only Registers
LED Delay
4000B90C
LED
1
EC-Only Registers
LED Update Stepsize
4000B910
LED
1
EC-Only Registers
LED Update Interval
4000BA00
LED
2
EC-Only Registers
LED Configuration
4000BA04
LED
2
EC-Only Registers
LED Limits
4000BA08
LED
2
EC-Only Registers
LED Delay
4000BA0C
LED
2
EC-Only Registers
LED Update Stepsize
4000BA10
LED
2
EC-Only Registers
LED Update Interval
4000BB00
LED
3
EC-Only Registers
LED Configuration
4000BB04
LED
3
EC-Only Registers
LED Limits
4000BB08
LED
3
EC-Only Registers
LED Delay
4000BB0C
LED
3
EC-Only Registers
LED Update Stepsize
4000BB10
LED
3
EC-Only Registers
LED Update Interval
4000BC00
BC-Link Master
0
Registers
BC-Link Status Register
4000BC04
BC-Link Master
0
Registers
BC-Link Address Register
4000BC08
BC-Link Master
0
Registers
BC-Link Data Register
DS00002022B-page 316
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000BC0C
BC-Link Master
0
Registers
BC-Link Clock Select Register
4000BD00 Public Key Crypto Engine
0
PKE Registers
PK_ConfigReg
4000BD04 Public Key Crypto Engine
0
PKE Registers
PK_CommandReg
4000BD08 Public Key Crypto Engine
0
PKE Registers
PK_ControlReg
4000BD0C Public Key Crypto Engine
0
PKE Registers
PK_StatusReg
4000BD10 Public Key Crypto Engine
0
PKE Registers
PK_VersionReg
4000BD14 Public Key Crypto Engine
0
PKE Registers
PK_LoadMicroCodeReg
4000BE00
Non Deterministic Random Number Generator
0
NDRNG Registers
ControlReg
4000BE04
Non Deterministic Random Number Generator
0
NDRNG Registers
FIFOLevelReg
4000BE08
Non Deterministic Random Number Generator
0
NDRNG Registers
VersionReg
4000C000
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ8 Source Register
4000C004
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ8 Enable Set Register
4000C008
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ8 Result Register
4000C00C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ8 Enable Clear Register
4000C014
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ9 Source Register
4000C018
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ9 Enable Set Register
4000C01C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ9 Result Register
4000C020
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ9 Enable Clear Register
4000C028
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ10 Source Register
4000C02C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ10 Enable Set Register
4000C030
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ10 Result Register
4000C034
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ10 Enable Clear Register
4000C03C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ11 Source Register
4000C040
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ11 Enable Set Register
4000C044
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ11 Result Register
4000C048
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ11 Enable Clear Register
4000C050
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ12 Source Register
2016 Microchip Technology Inc.
DS00002022B-page 317
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000C054
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ12 Enable Set Register
4000C058
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ12 Result Register
4000C05C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ12 Enable Clear Register
4000C064
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ13 Source Register
4000C068
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ13 Enable Set Register
4000C06C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ13 Result Register
4000C070
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ13 Enable Clear Register
4000C078
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ14 Source Register
4000C07C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ14 Enable Set Register
4000C080
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ14 Result Register
4000C084
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ14 Enable Clear Register
4000C08C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ15 Source Register
4000C090
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ15 Enable Set Register
4000C094
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ15 Result Register
4000C098
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ15 Enable Clear Register
4000C0A0
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ16 Source Register
4000C0A4
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ16 Enable Set Register
4000C0A8
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ16 Result Register
4000C0AC
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ16 Enable Clear Register
4000C0B4
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ17 Source Register
4000C0B8
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ17 Enable Set Register
4000C0BC
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ17 Result Register
4000C0C0
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ17 Enable Clear Register
4000C0C8
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ18 Source Register
4000C0CC
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ18 Enable Set Register
DS00002022B-page 318
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000C0D0
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ18 Result Register
4000C0D4
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ18 Enable Clear Register
4000C0DC
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ19 Source Register
4000C0E0
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ19 Enable Set Register
4000C0E4
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ19 Result Register
4000C0E8
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ19 Enable Clear Register
4000C0F0
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ20 Source Register
4000C0F4
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ20 Enable Set Register
4000C0F8
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ20 Result Register
4000C0FC
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ20 Enable Clear Register
4000C104
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ21 Source Register
4000C108
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ21 Enable Set Register
4000C10C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ21 Result Register
4000C110
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ21 Enable Clear Register
4000C118
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ22 Source Register
4000C11C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ22 Enable Set Register
4000C120
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ22 Result Register
4000C124
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ22 Enable Clear Register
4000C12C
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ23 Source Register
4000C130
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ23 Enable Set Register
4000C134
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ23 Result Register
4000C138
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
GIRQ23 Enable Clear Register
4000C200
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
Block Enable Set Register
4000C204
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
Block Enable Clear Register
4000C208
EC Interrupt Aggregator
(INTS)
0
INTS_EC_ONLY
Block IRQ Vector Register
2016 Microchip Technology Inc.
DS00002022B-page 319
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000D000
AES Crypto Engine &
Hash Function
0
HASH Registers
SHAMode register
4000D004
AES Crypto Engine &
Hash Function
0
HASH Registers
NbBlock register
4000D008
AES Crypto Engine &
Hash Function
0
HASH Registers
Control
4000D00C
AES Crypto Engine &
Hash Function
0
HASH Registers
Status
4000D010
AES Crypto Engine &
Hash Function
0
HASH Registers
Version
4000D014
AES Crypto Engine &
Hash Function
0
HASH Registers
GenericValue register
4000D018
AES Crypto Engine &
Hash Function
0
HASH Registers
Initial Hash Source
Address
4000D01C
AES Crypto Engine &
Hash Function
0
HASH Registers
Data Source Address
4000D020
AES Crypto Engine &
Hash Function
0
HASH Registers
Hash Result Destination
Address
4000D200
AES Crypto Engine &
Hash Function
0
AES Registers
ConfigReg
4000D204
AES Crypto Engine &
Hash Function
0
AES Registers
CommandReg
4000D208
AES Crypto Engine &
Hash Function
0
AES Registers
ControlReg
4000D20C
AES Crypto Engine &
Hash Function
0
AES Registers
StatusReg
4000D210
AES Crypto Engine &
Hash Function
0
AES Registers
VersionReg
4000D214
AES Crypto Engine &
Hash Function
0
AES Registers
NbHeaderReg
4000D218
AES Crypto Engine &
Hash Function
0
AES Registers
LastHeaderReg
4000D21C
AES Crypto Engine &
Hash Function
0
AES Registers
NbBlockReg
4000D220
AES Crypto Engine &
Hash Function
0
AES Registers
LastBlockReg
4000D224
AES Crypto Engine &
Hash Function
0
AES Registers
DMAInReg
4000D228
AES Crypto Engine &
Hash Function
0
AES Registers
DMAOutReg
4000D300
AES Crypto Engine &
Hash Function
0
AES Registers
Key1Reg
4000D320
AES Crypto Engine &
Hash Function
0
AES Registers
IVReg
4000D340
AES Crypto Engine &
Hash Function
0
AES Registers
Key2Reg
4000FC00
EC_REG_BANK
0
EC_REG_BANK
Reserved
4000FC04
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC08
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
DS00002022B-page 320
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
4000FC0C
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC10
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC11
EC_REG_BANK
0
EC_REG_BANK
Reserved
4000FC14
EC_REG_BANK
0
EC_REG_BANK
AHB Error Control
4000FC15
EC_REG_BANK
0
EC_REG_BANK
Reserved
4000FC18
EC_REG_BANK
0
EC_REG_BANK
Interrupt Control
4000FC1C
EC_REG_BANK
0
EC_REG_BANK
ETM Trace Enable
4000FC20
EC_REG_BANK
0
EC_REG_BANK
JTAG Enable
4000FC24
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC28
EC_REG_BANK
0
EC_REG_BANK
WDT Event Count
4000FC2C
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC30
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC34
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC38
EC_REG_BANK
0
EC_REG_BANK
ADC VREF PD
4000FC3C
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
4000FC40
EC_REG_BANK
0
EC_REG_BANK
MCHP Reserved
40080000
JTAG
0
JTAG_EC_Only
JTAG Message OBF
40080004
JTAG
0
JTAG_EC_Only
JTAG Message IBF
40080008
JTAG
0
JTAG_EC_Only
JTAG OBF Status
40080009
JTAG
0
JTAG_EC_Only
JTAG IBF Status
4008000C
JTAG
0
JTAG_EC_Only
JTAG DBG Ctrl
40080100
PCR
0
PCR
Chip Sleep Enable Register
40080104
PCR
0
PCR
Chip Clock Required Register
40080108
PCR
0
PCR
EC Sleep Enables Register
4008010C
PCR
0
PCR
EC Clock Required Status
Register
40080110
PCR
0
PCR
Host Sleep Enables Register
40080114
PCR
0
PCR
Host Clock Required Status
Register
40080118
PCR
0
PCR
CHIP_PCR_ADDR_SYS_SLEEP_CTRL_0
40080120
PCR
0
PCR
Processor Clock Control
40080124
PCR
0
PCR
EC Sleep Enable 2 Register
40080128
PCR
0
PCR
EC Clock Required 2 Status Register
4008012C
PCR
0
PCR
Slow Clock Control
40080130
PCR
0
PCR
Oscillator ID Register
40080134
PCR
0
PCR
Reserved
40080138
PCR
0
PCR
Chip Reset Enable
4008013C
PCR
0
PCR
Host Reset Enable
40080140
PCR
0
PCR
EC Reset Enable
2016 Microchip Technology Inc.
DS00002022B-page 321
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40080144
PCR
0
PCR
EC Reset Enable 2
40080148
PCR
0
PCR
PCR Clock Reset Control
40081000
GPIO
0
GPIO Registers
GPIO000 Pin Control
40081004
GPIO
0
GPIO Registers
GPIO001 Pin Control
40081008
GPIO
0
GPIO Registers
GPIO002 Pin Control
4008100C
GPIO
0
GPIO Registers
GPIO003 Pin Control
40081010
GPIO
0
GPIO Registers
GPIO004 Pin Control
40081014
GPIO
0
GPIO Registers
GPIO005 Pin Control
40081018
GPIO
0
GPIO Registers
GPIO006 Pin Control
4008101C
GPIO
0
GPIO Registers
GPIO007 Pin Control
40081020
GPIO
0
GPIO Registers
GPIO010 Pin Control
40081024
GPIO
0
GPIO Registers
GPIO011 Pin Control
40081028
GPIO
0
GPIO Registers
GPIO012 Pin Control
4008102C
GPIO
0
GPIO Registers
GPIO013 Pin Control
40081030
GPIO
0
GPIO Registers
GPIO014 Pin Control
40081034
GPIO
0
GPIO Registers
GPIO015 Pin Control
40081038
GPIO
0
GPIO Registers
GPIO016 Pin Control
4008103C
GPIO
0
GPIO Registers
GPIO017 Pin Control
40081040
GPIO
0
GPIO Registers
GPIO020 Pin Control
40081044
GPIO
0
GPIO Registers
GPIO021 Pin Control
40081048
GPIO
0
GPIO Registers
GPIO022 Pin Control
4008104C
GPIO
0
GPIO Registers
GPIO023 Pin Control
40081050
GPIO
0
GPIO Registers
GPIO024 Pin Control
40081054
GPIO
0
GPIO Registers
GPIO025 Pin Control
40081058
GPIO
0
GPIO Registers
GPIO026 Pin Control
4008105C
GPIO
0
GPIO Registers
GPIO027 Pin Control
40081060
GPIO
0
GPIO Registers
GPIO030 Pin Control
40081064
GPIO
0
GPIO Registers
GPIO031 Pin Control
40081068
GPIO
0
GPIO Registers
GPIO032 Pin Control
4008106C
GPIO
0
GPIO Registers
GPIO033 Pin Control
40081070
GPIO
0
GPIO Registers
GPIO034 Pin Control
40081074
GPIO
0
GPIO Registers
GPIO035 Pin Control
40081078
GPIO
0
GPIO Registers
GPIO036 Pin Control
40081080
GPIO
0
GPIO Registers
GPIO040 Pin Control
40081084
GPIO
0
GPIO Registers
GPIO041 Pin Control
40081088
GPIO
0
GPIO Registers
GPIO042 Pin Control
4008108C
GPIO
0
GPIO Registers
GPIO043 Pin Control
40081090
GPIO
0
GPIO Registers
GPIO044 Pin Control
40081094
GPIO
0
GPIO Registers
GPIO045 Pin Control
40081098
GPIO
0
GPIO Registers
GPIO046 Pin Control
4008109C
GPIO
0
GPIO Registers
GPIO047 Pin Control
400810A0
GPIO
0
GPIO Registers
GPIO050 Pin Control
400810A4
GPIO
0
GPIO Registers
GPIO051 Pin Control
DS00002022B-page 322
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
400810A8
GPIO
0
GPIO Registers
GPIO052 Pin Control
400810AC
GPIO
0
GPIO Registers
GPIO053 Pin Control
400810B0
GPIO
0
GPIO Registers
GPIO054 Pin Control
400810B4
GPIO
0
GPIO Registers
GPIO055 Pin Control
400810B8
GPIO
0
GPIO Registers
GPIO056 Pin Control
400810BC
GPIO
0
GPIO Registers
GPIO057 Pin Control
400810C0
GPIO
0
GPIO Registers
GPIO060 Pin Control
400810C4
GPIO
0
GPIO Registers
GPIO061 Pin Control
400810C8
GPIO
0
GPIO Registers
GPIO062 Pin Control
400810CC
GPIO
0
GPIO Registers
GPIO063 Pin Control
400810D0
GPIO
0
GPIO Registers
GPIO064 Pin Control
400810D4
GPIO
0
GPIO Registers
GPIO065 Pin Control
400810D8
GPIO
0
GPIO Registers
GPIO066 Pin Control
400810DC
GPIO
0
GPIO Registers
GPIO067 Pin Control
40081100
GPIO
0
GPIO Registers
GPIO100 Pin Control
40081104
GPIO
0
GPIO Registers
GPIO101 Pin Control
40081108
GPIO
0
GPIO Registers
GPIO102 Pin Control
4008110C
GPIO
0
GPIO Registers
GPIO103 Pin Control
40081110
GPIO
0
GPIO Registers
GPIO104 Pin Control
40081114
GPIO
0
GPIO Registers
GPIO105 Pin Control
40081118
GPIO
0
GPIO Registers
GPIO106 Pin Control
4008111C
GPIO
0
GPIO Registers
GPIO107 Pin Control
40081120
GPIO
0
GPIO Registers
GPIO110 Pin Control
40081124
GPIO
0
GPIO Registers
GPIO111 Pin Control
40081128
GPIO
0
GPIO Registers
GPIO112 Pin Control
4008112C
GPIO
0
GPIO Registers
GPIO113 Pin Control
40081130
GPIO
0
GPIO Registers
GPIO114 Pin Control
40081134
GPIO
0
GPIO Registers
GPIO115 Pin Control
40081138
GPIO
0
GPIO Registers
GPIO116 Pin Control
4008113C
GPIO
0
GPIO Registers
GPIO117 Pin Control
40081140
GPIO
0
GPIO Registers
GPIO120 Pin Control
40081144
GPIO
0
GPIO Registers
GPIO121 Pin Control
40081148
GPIO
0
GPIO Registers
GPIO122 Pin Control
4008114C
GPIO
0
GPIO Registers
GPIO123 Pin Control
40081150
GPIO
0
GPIO Registers
GPIO124 Pin Control
40081154
GPIO
0
GPIO Registers
GPIO125 Pin Control
40081158
GPIO
0
GPIO Registers
GPIO126 Pin Control
4008115C
GPIO
0
GPIO Registers
GPIO127 Pin Control
40081160
GPIO
0
GPIO Registers
GPIO130 Pin Control
40081164
GPIO
0
GPIO Registers
GPIO131 Pin Control
40081168
GPIO
0
GPIO Registers
GPIO132 Pin Control
4008116C
GPIO
0
GPIO Registers
GPIO133 Pin Control
40081170
GPIO
0
GPIO Registers
GPIO134 Pin Control
2016 Microchip Technology Inc.
DS00002022B-page 323
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40081174
GPIO
0
GPIO Registers
GPIO135 Pin Control
40081178
GPIO
0
GPIO Registers
GPIO136 Pin Control
40081180
GPIO
0
GPIO Registers
GPIO140 Pin Control
40081184
GPIO
0
GPIO Registers
GPIO141 Pin Control
40081188
GPIO
0
GPIO Registers
GPIO142 Pin Control
4008118C
GPIO
0
GPIO Registers
GPIO143 Pin Control
40081190
GPIO
0
GPIO Registers
GPIO144 Pin Control
40081194
GPIO
0
GPIO Registers
GPIO145 Pin Control
40081198
GPIO
0
GPIO Registers
GPIO146 Pin Control
4008119C
GPIO
0
GPIO Registers
GPIO147 Pin Control
400811A0
GPIO
0
GPIO Registers
GPIO150 Pin Control
400811A4
GPIO
0
GPIO Registers
GPIO151 Pin Control
400811A8
GPIO
0
GPIO Registers
GPIO152 Pin Control
400811AC
GPIO
0
GPIO Registers
GPIO153 Pin Control
400811B0
GPIO
0
GPIO Registers
GPIO154 Pin Control
400811B4
GPIO
0
GPIO Registers
GPIO155 Pin Control
400811B8
GPIO
0
GPIO Registers
GPIO156 Pin Control
400811BC
GPIO
0
GPIO Registers
GPIO157 Pin Control
400811C0
GPIO
0
GPIO Registers
GPIO160 Pin Control
400811C4
GPIO
0
GPIO Registers
GPIO161 Pin Control
400811C8
GPIO
0
GPIO Registers
GPIO162 Pin Control
400811CC
GPIO
0
GPIO Registers
GPIO163 Pin Control
400811D0
GPIO
0
GPIO Registers
GPIO164 Pin Control
400811D4
GPIO
0
GPIO Registers
GPIO165 Pin Control
40081200
GPIO
0
GPIO Registers
GPIO200 Pin Control
40081204
GPIO
0
GPIO Registers
GPIO201 Pin Control
40081208
GPIO
0
GPIO Registers
GPIO202 Pin Control
4008120C
GPIO
0
GPIO Registers
GPIO203 Pin Control
40081210
GPIO
0
GPIO Registers
GPIO204 Pin Control
40081214
GPIO
0
GPIO Registers
Reserved
40081218
GPIO
0
GPIO Registers
GPIO206 Pin Control
4008121C
GPIO
0
GPIO Registers
Reserved
40081220
GPIO
0
GPIO Registers
GPIO210 Pin Control
40081224
GPIO
0
GPIO Registers
GPIO211 Pin Control
40081280
GPIO
0
GPIO Registers
Output GPIO[000:036]
40081284
GPIO
0
GPIO Registers
Output GPIO[040:076]
40081288
GPIO
0
GPIO Registers
Output GPIO[100:136]
4008128C
GPIO
0
GPIO Registers
Output GPIO[140:176]
40081290
GPIO
0
GPIO Registers
Output GPIO[200:236]
40081300
GPIO
0
GPIO Registers
Input GPIO[000:036]
40081304
GPIO
0
GPIO Registers
Input GPIO[040:076]
40081308
GPIO
0
GPIO Registers
Input GPIO[100:136]
4008130C
GPIO
0
GPIO Registers
Input GPIO[140:176]
DS00002022B-page 324
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40081310
GPIO
0
GPIO Registers
Input GPIO[200:236]
40081314
GPIO
0
GPIO Registers
Reserved
40081500
GPIO
0
GPIO Registers
GPIO000 Pin Control 2
40081504
GPIO
0
GPIO Registers
GPIO001 Pin Control 2
40081508
GPIO
0
GPIO Registers
GPIO002 Pin Control 2
4008150C
GPIO
0
GPIO Registers
GPIO003 Pin Control 2
40081510
GPIO
0
GPIO Registers
GPIO004 Pin Control 2
40081514
GPIO
0
GPIO Registers
GPIO005 Pin Control 2
40081518
GPIO
0
GPIO Registers
GPIO006 Pin Control 2
4008151C
GPIO
0
GPIO Registers
GPIO007 Pin Control 2
40081520
GPIO
0
GPIO Registers
GPIO010 Pin Control 2
40081524
GPIO
0
GPIO Registers
GPIO011 Pin Control 2
40081528
GPIO
0
GPIO Registers
GPIO012 Pin Control 2
4008152C
GPIO
0
GPIO Registers
GPIO013 Pin Control 2
40081530
GPIO
0
GPIO Registers
GPIO014 Pin Control 2
40081534
GPIO
0
GPIO Registers
GPIO015 Pin Control 2
40081538
GPIO
0
GPIO Registers
GPIO016 Pin Control 2
4008153C
GPIO
0
GPIO Registers
GPIO017 Pin Control 2
40081540
GPIO
0
GPIO Registers
GPIO020 Pin Control 2
40081544
GPIO
0
GPIO Registers
GPIO021 Pin Control 2
40081548
GPIO
0
GPIO Registers
GPIO022 Pin Control 2
4008154C
GPIO
0
GPIO Registers
GPIO023 Pin Control 2
40081550
GPIO
0
GPIO Registers
GPIO024 Pin Control 2
40081554
GPIO
0
GPIO Registers
GPIO025 Pin Control 2
40081558
GPIO
0
GPIO Registers
GPIO026 Pin Control 2
4008155C
GPIO
0
GPIO Registers
GPIO027 Pin Control 2
40081560
GPIO
0
GPIO Registers
GPIO030 Pin Control 2
40081564
GPIO
0
GPIO Registers
GPIO031 Pin Control 2
40081568
GPIO
0
GPIO Registers
GPIO032 Pin Control 2
4008156C
GPIO
0
GPIO Registers
GPIO033 Pin Control 2
40081570
GPIO
0
GPIO Registers
GPIO034 Pin Control 2
40081574
GPIO
0
GPIO Registers
GPIO035 Pin Control 2
40081578
GPIO
0
GPIO Registers
GPIO036 Pin Control 2
40081580
GPIO
0
GPIO Registers
GPIO040 Pin Control 2
40081584
GPIO
0
GPIO Registers
GPIO041 Pin Control 2
40081588
GPIO
0
GPIO Registers
GPIO042 Pin Control 2
4008158C
GPIO
0
GPIO Registers
GPIO043 Pin Control 2
40081590
GPIO
0
GPIO Registers
GPIO044 Pin Control 2
40081594
GPIO
0
GPIO Registers
GPIO045 Pin Control 2
40081598
GPIO
0
GPIO Registers
GPIO046 Pin Control 2
4008159C
GPIO
0
GPIO Registers
GPIO047 Pin Control 2
400815A0
GPIO
0
GPIO Registers
GPIO050 Pin Control 2
400815A4
GPIO
0
GPIO Registers
GPIO051 Pin Control 2
2016 Microchip Technology Inc.
DS00002022B-page 325
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
400815A8
GPIO
0
GPIO Registers
GPIO052 Pin Control 2
400815AC
GPIO
0
GPIO Registers
GPIO053 Pin Control 2
400815B0
GPIO
0
GPIO Registers
GPIO054 Pin Control 2
400815B4
GPIO
0
GPIO Registers
GPIO055 Pin Control 2
400815B8
GPIO
0
GPIO Registers
GPIO056 Pin Control 2
400815BC
GPIO
0
GPIO Registers
GPIO057 Pin Control 2
400815C0
GPIO
0
GPIO Registers
GPIO060 Pin Control 2
400815C4
GPIO
0
GPIO Registers
GPIO061 Pin Control 2
400815C8
GPIO
0
GPIO Registers
GPIO062 Pin Control 2
400815CC
GPIO
0
GPIO Registers
GPIO063 Pin Control 2
400815D0
GPIO
0
GPIO Registers
GPIO064 Pin Control 2
400815D4
GPIO
0
GPIO Registers
GPIO065 Pin Control 2
400815D8
GPIO
0
GPIO Registers
GPIO066 Pin Control 2
400815DC
GPIO
0
GPIO Registers
GPIO067 Pin Control 2
400815E0
GPIO
0
GPIO Registers
GPIO100 Pin Control 2
400815E4
GPIO
0
GPIO Registers
GPIO101 Pin Control 2
400815E8
GPIO
0
GPIO Registers
GPIO102 Pin Control 2
400815EC
GPIO
0
GPIO Registers
GPIO103 Pin Control 2
400815F0
GPIO
0
GPIO Registers
GPIO104 Pin Control 2
400815F4
GPIO
0
GPIO Registers
GPIO105 Pin Control 2
400815F8
GPIO
0
GPIO Registers
GPIO106 Pin Control 2
400815FC
GPIO
0
GPIO Registers
GPIO107 Pin Control 2
40081600
GPIO
0
GPIO Registers
GPIO110 Pin Control 2
40081604
GPIO
0
GPIO Registers
GPIO111 Pin Control 2
40081608
GPIO
0
GPIO Registers
GPIO112 Pin Control 2
4008160C
GPIO
0
GPIO Registers
GPIO113 Pin Control 2
40081610
GPIO
0
GPIO Registers
GPIO114 Pin Control 2
40081614
GPIO
0
GPIO Registers
GPIO115 Pin Control 2
40081618
GPIO
0
GPIO Registers
GPIO116 Pin Control 2
4008161C
GPIO
0
GPIO Registers
GPIO117 Pin Control 2
40081620
GPIO
0
GPIO Registers
GPIO120 Pin Control 2
40081624
GPIO
0
GPIO Registers
GPIO121 Pin Control 2
40081628
GPIO
0
GPIO Registers
GPIO122 Pin Control 2
4008162C
GPIO
0
GPIO Registers
GPIO123 Pin Control 2
40081630
GPIO
0
GPIO Registers
GPIO124 Pin Control 2
40081634
GPIO
0
GPIO Registers
GPIO125 Pin Control 2
40081638
GPIO
0
GPIO Registers
GPIO126 Pin Control 2
4008163C
GPIO
0
GPIO Registers
GPIO127 Pin Control 2
40081640
GPIO
0
GPIO Registers
GPIO130 Pin Control 2
40081644
GPIO
0
GPIO Registers
GPIO131 Pin Control 2
40081648
GPIO
0
GPIO Registers
GPIO132 Pin Control 2
4008164C
GPIO
0
GPIO Registers
GPIO133 Pin Control 2
40081650
GPIO
0
GPIO Registers
GPIO134 Pin Control 2
DS00002022B-page 326
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
40081654
GPIO
0
GPIO Registers
GPIO135 Pin Control 2
40081658
GPIO
0
GPIO Registers
GPIO136 Pin Control 2
40081660
GPIO
0
GPIO Registers
GPIO140 Pin Control 2
40081664
GPIO
0
GPIO Registers
GPIO141 Pin Control 2
40081668
GPIO
0
GPIO Registers
GPIO142 Pin Control 2
4008166C
GPIO
0
GPIO Registers
GPIO143 Pin Control 2
40081670
GPIO
0
GPIO Registers
GPIO144 Pin Control 2
40081674
GPIO
0
GPIO Registers
GPIO145 Pin Control 2
40081678
GPIO
0
GPIO Registers
GPIO146 Pin Control 2
4008167C
GPIO
0
GPIO Registers
GPIO147 Pin Control 2
40081680
GPIO
0
GPIO Registers
GPIO150 Pin Control 2
40081684
GPIO
0
GPIO Registers
GPIO151 Pin Control 2
40081688
GPIO
0
GPIO Registers
GPIO152 Pin Control 2
4008168C
GPIO
0
GPIO Registers
GPIO153 Pin Control 2
40081690
GPIO
0
GPIO Registers
GPIO154 Pin Control 2
40081694
GPIO
0
GPIO Registers
GPIO155 Pin Control 2
40081698
GPIO
0
GPIO Registers
GPIO156 Pin Control 2
4008169C
GPIO
0
GPIO Registers
GPIO157 Pin Control 2
400816A0
GPIO
0
GPIO Registers
GPIO160 Pin Control 2
400816A4
GPIO
0
GPIO Registers
GPIO161 Pin Control 2
400816A8
GPIO
0
GPIO Registers
GPIO162 Pin Control 2
400816AC
GPIO
0
GPIO Registers
GPIO163 Pin Control 2
400816B0
GPIO
0
GPIO Registers
GPIO164 Pin Control 2
400816B4
GPIO
0
GPIO Registers
GPIO165 Pin Control 2
40081720
GPIO
0
GPIO Registers
GPIO200 Pin Control 2
40081724
GPIO
0
GPIO Registers
GPIO201 Pin Control 2
40081728
GPIO
0
GPIO Registers
GPIO202 Pin Control 2
4008172C
GPIO
0
GPIO Registers
GPIO203 Pin Control 2
40081730
GPIO
0
GPIO Registers
GPIO204 Pin Control 2
40081738
GPIO
0
GPIO Registers
GPIO206 Pin Control 2
40081740
GPIO
0
GPIO Registers
GPIO210 Pin Control 2
40081744
GPIO
0
GPIO Registers
GPIO211 Pin Control 2
400F1C00
M16C550A UART
0
UART_EC_Only
UART Programmable
BAUD Rate Generator
(LSB) Register
400F1C00
M16C550A UART
0
UART_EC_Only
UART Receive Buffer Register
400F1C00
M16C550A UART
0
UART_EC_Only
UART Transmit Buffer Register
400F1C01
M16C550A UART
0
UART_EC_Only
UART Programmable
BAUD Rate Generator
(MSB) Register
400F1C01
M16C550A UART
0
UART_EC_Only
UART Interrupt Enable
Register
2016 Microchip Technology Inc.
DS00002022B-page 327
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
400F1C02
M16C550A UART
0
UART_EC_Only
UART FIFO Control Register
400F1C02
M16C550A UART
0
UART_EC_Only
UART Interrupt Identification Register
400F1C03
M16C550A UART
0
UART_EC_Only
UART Line Control Register
400F1C04
M16C550A UART
0
UART_EC_Only
UART Modem Control
Register
400F1C05
M16C550A UART
0
UART_EC_Only
UART Line Status Register
400F1C06
M16C550A UART
0
UART_EC_Only
UART Modem Status Register
400F1C07
M16C550A UART
0
UART_EC_Only
UART Scratchpad Register
400F1C00
M16C550A UART
0
UART_Runtime
UART Transmit Buffer Register
400F1C00
M16C550A UART
0
UART_Runtime
UART Programmable
BAUD Rate Generator
(LSB) Register
400F1C00
M16C550A UART
0
UART_Runtime
UART Receive Buffer Register
400F1C01
M16C550A UART
0
UART_Runtime
UART Interrupt Enable
Register
400F1C01
M16C550A UART
0
UART_Runtime
UART Programmable
BAUD Rate Generator
(MSB) Register
400F1C02
M16C550A UART
0
UART_Runtime
UART FIFO Control Register
400F1C02
M16C550A UART
0
UART_Runtime
UART Interrupt Identification Register
400F1C03
M16C550A UART
0
UART_Runtime
UART Line Control Register
400F1C04
M16C550A UART
0
UART_Runtime
UART Modem Control
Register
400F1C05
M16C550A UART
0
UART_Runtime
UART Line Status Register
400F1C06
M16C550A UART
0
UART_Runtime
UART Modem Status Register
400F1C07
M16C550A UART
0
UART_Runtime
UART Scratchpad Register
400F1F30
M16C550A UART
0
UART_Config
UART Activate Register
400F1FF0
M16C550A UART
0
UART_Config
UART Config Select Register
400F2C00
RTC
0
RTC
Seconds
400F2C01
RTC
0
RTC
Seconds Alarm
400F2C02
RTC
0
RTC
Minutes
400F2C03
RTC
0
RTC
Minutes Alarm
400F2C04
RTC
0
RTC
Hours
400F2C05
RTC
0
RTC
Hours Alarm
400F2C06
RTC
0
RTC
Day of Week
400F2C07
RTC
0
RTC
Day of Month
400F2C08
RTC
0
RTC
Month
DS00002022B-page 328
2016 Microchip Technology Inc.
CEC1302
Address
(Hex)
HW Block Instance
Name
HW Block
Instance No.
Reg. Bank Name
Reg. Instance Name
400F2C09
RTC
0
RTC
Year
400F2C0A
RTC
0
RTC
Register A
400F2C0B
RTC
0
RTC
Register B
400F2C0C
RTC
0
RTC
Register C
400F2C0D
RTC
0
RTC
Register D
400F2C10
RTC
0
RTC
RTC Control
400F2C14
RTC
0
RTC
Week Alarm
400F2C18
RTC
0
RTC
Daylight Savings Forward
400F2C1C
RTC
0
RTC
Daylight Savings Backward
400F2C20
RTC
0
RTC
RTC Test Mode
2016 Microchip Technology Inc.
DS00002022B-page 329
CEC1302
APPENDIX A:
TABLE A-1:
REVISION HISTORY
DATA SHEET REVISION HISTORY
Revision
Section/Figure/Entry
DS00002022B (03-10-16)
Cover Page
DS00002022A (10-30-15)
First Release
DS00002022B-page 330
Correction
Changed title from “Keyboard and
Embedded Controller for Notebook PC”
to “Low Power Crypto Embedded Controller”
2016 Microchip Technology Inc.
CEC1302
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support
2016 Microchip Technology Inc.
DS00002022B-page 331
CEC1302
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.(1)
Device
Device:
Total SRAM:
X
Tape and Reel
Option:
XX
Version/
Revision
Total
SRAM
-
XXX(2)
Package
-
[X](3)
Tape and Reel
Option
Examples:
a)
CEC1302D-C0-SZ = 128kB SRAM, Standard
Version, 144-pin WFBGA, Tray packaging
CEC1302(1)
D
Version/Revision: C0
Package:
-
SZ
Blank
TR
DS00002022B-page 332
=
128kB
= Standard Version
=
Note 1:
These products meet the halogen maximum
concentration values per IEC61249-2-21.
Note 2:
All package options are RoHS compliant.
For RoHS compliance and environmental
information, please visit http://www.micro
chip.com/pagehandler/en-us/aboutus/
ehs.html .
Note 3:
Tape and Reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
144 pin WFBGA(2)
= Tray packaging
= Tape and Reel(3)
2016 Microchip Technology Inc.
CEC1302
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch,
Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522403654
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2016 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00002022B-page 333
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
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