CORE8051-SR

Core8051 Product Summary Intended Use • • • Embedded System Control Communication System Control I/O Control • • • • – Wait Cycles to Access Fast/Slow ROM – Dual Data Pointer to Fast Data Block Transfer Special Function Register (SFR) Interface – Services up to 101 External SFRs Optional On-Chip Instrumentation (OCI) Debug Logic Supports all Major Actel Device Families Optional Power-Saving Modes Key Features • • 100% ASM51 (8051/80C31/80C51) Compatible Instruction Set 1 Control Unit – 8-Bit Instruction Decoder – Reduced Instruction Time of up to 12 Cycles Arithmetic Logic Unit – 8-Bit Arithmetic and Logical Operations – – • Boolean Manipulations 8 by 8-Bit Multiplication and 8 by 8-Bit Division Supported Families • • • • • • • Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S SX-A RTSX-S • • • • • • 32-Bit I/O Ports – Four 8-Bit I/O Ports – Alternate Port Functions, such as External Interrupts, Provide Extra Port Pins when Compared with the Standard 8051 Serial Port – Simultaneous Transmit and Receive – Synchronous Mode, Fixed Baud Rate – 8-Bit UART Mode, Variable Baud Rate – 9-Bit UART Mode, Fixed Baud Rate – 9-Bit UART Mode, Variable Baud Rate – Multiprocessor Communication Two 16-Bit Timer/Counters Interrupt Controller – Four Priority Levels with 13 Interrupt Sources Internal Data Memory Interface – Can Address up to 256B of Data Memory Space External Memory Interface – Can Address up to 64kB of External Program Memory – Can Address up to 64kB of External Data Memory – Demultiplexed Address/Data Bus Enables Easy Connection to Memory – Variable Length MOVX to Access Fast/Slow RAM or Peripherals Core Deliverables • Evaluation Version – Compiled RTL Simulation Model Fully Supported in the Actel Libero® Integrated Design Environment (IDE) Netlist Version – Structural Verilog and VHDL Netlists (with and without I/O Pads) Compatible with the Actel Designer Software Place-and-Route Tool – Compiled RTL Simulation Model Fully Supported in Actel Libero IDE RTL Version – Verilog and VHDL Core Source Code – Core Synthesis Scripts Testbench (Verilog and VHDL) • • • Synthesis and Simulation Support • Synthesis – Synplicity® – Synopsys® (Design CompilerTM, FPGA CompilerTM, FPGA ExpressTM) – ExemplarTM Simulation – OVI - Compliant Verilog Simulators – Vital - Compliant VHDL Simulators • 1. For more information, see the Core8051 Instruction Set Details User’s Guide December 2005 © 2005 Actel Corporation v 6 .0 1 Core8051 Core Verification • • Comprehensive VHDL and Verilog Testbenches Users Can Easily Add Custom Tests by Modifying the User Testbench Using the Existing Format MUL and DIV instructions. Furthermore, each cycle in the 8051 used two memory fetches. In many cases, the second fetch was a "dummy" fetch and extra clocks were wasted. Table 1 shows the speed advantage of Core8051 over the standard 8051. A speed advantage of 12 in the first column means that Core8051 performs the same instruction 12 times faster than the standard 8051. The second column in Table 1 lists the number of types of instructions that have the given speed advantage. The third column lists the total number of instructions that have the given speed advantage. The third column can be thought of as a subcategory of the second column. For example, there are two types of instructions that have a three-time speed advantage over the classic 8051, for which there are nine explicit instructions. Table 1 • Core8051 Speed Advantage Summary Speed Advantage 24 12 9.6 8 6 4.8 4 3 Average: 8.0 Number of Instruction Types 1 27 2 16 44 1 18 2 Sum: 111 Number of Instructions (Opcodes) 1 83 2 38 89 2 31 9 Sum: 255 Contents General Description .................................................... 2 Core8051 Device Requirements ................................. 4 Core8051 Verification ................................................ 5 I/O Signal Descriptions ............................................... 5 Memory Organization ................................................ 8 Special Function Registers ........................................ 10 Instruction Set ........................................................... 11 Instruction Definitions ............................................. 19 Instruction Timing .................................................... 20 Core8051 Engine ...................................................... 27 Timers/Counters ........................................................ 28 Serial Interface .......................................................... 30 Interrupt Service Routine Unit ................................. 32 ISR Structure ............................................................. 35 Power Management Unit ........................................ 36 Power Management Implementation ..................... 36 Interface for On-Chip Instrumentation (Optional) . 37 Ordering Information .............................................. 39 List of Changes ......................................................... 40 Datasheet Categories ............................................... 40 General Description The Core8051 macro is a high-performance, single-chip, 8bit microcontroller. It is a fully functional eight-bit embedded controller that executes all ASM51 instructions and has the same instruction set as the 80C31. Core8051 provides software and hardware interrupts, a serial port, and two timers. The Core8051 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the one-byte instructions are performed in a single cycle. Core8051 uses one clock per cycle. This leads to an average performance improvement rate of 8.0 (in terms of MIPS) with respect to the Intel device working with the same clock frequency. The original 8051 had a 12-clock architecture. A machine cycle needed 12 clocks, and most instructions were either one or two machine cycles. Therefore, the 8051 used either 12 or 24 clocks for each instruction, except for the The average speed advantage is 8.0. However, the real speed improvement seen in any system will depend on the instruction mix. Core8051 consists of the following primary blocks: • • • • • • • • • • • • Memory Control Block – Logic that Controls Program and Data Memory Control Processor Block – Main Controller Logic RAM and SFR Control Block ALU – Arithmetic Logic Unit Reset Control Block – Provides Reset Condition Circuitry Clock Control Block Timer 0 and 1 Block ISR – Interrupt Service Routine Block Serial Port Block Port Registers Block PMU – Power Management Unit Block OCI block – On-Chip Instrumentation Logic for Debug Capabilities 2 v6.0 Core8051 Figure 1 shows the primary blocks of Core8051. Core8051 8051 Main Engine Memory Control Fetch Instr Cycle Timer_0_1 Control Unit Fetch Instr Cycle Special Function Register Bus Interrupt Service RAM_SFR Control Fetch Instr Cycle Ports Arithmetic Logic Unit Serial Channel Power Management Clock Control Figure 1 • Core8051 Block Diagram v6.0 3 Core8051 Core8051 Device Requirements Core8051 has been implemented in several of the Actel device families. A summary of the implementation data is listed in Table 2 through Table 4. Table 2 lists implementation data without OCI logic. Table 2 • Core8051 Device Utilization and Performance - No OCI Cells or Tiles Family Fusion ProASIC3/E ProASIC PLUS Utilization RAM Blocks 1 1 1 1 1 Device AFS600 A3PE600-2 APA150-STD AX250-3 RTAX1000S-1 A54SX72A-3 RT54SX72S-1 Total 30% 30% 72% 70% 16% 57% 57% Performance 36 MHz 36 MHz 24 MHz 52 MHz 29 MHz 33 MHz 19 MHz Sequential 528 528 528 619 619 646 646 Combinatorial 3629 3629 3909 2344 2344 2780 2780 Total 4157 4157 4437 2963 2963 3426 3426 Axcelerator RTAX-S SX-A RTSX-S Note: Data in this table was achieved using typical synthesis and layout settings. Performance was achieved using the Core8051 macro alone. Table 3 lists implementation data with OCI logic (no trace memory and no hardware triggers). Table 3 • Core8051 Device Utilization and Performance - OCI without Trace Memory and Hardware Trigger Cells or Tiles Utilization RAM Blocks 1 1 1 1 1 Device AFS600 A3PE600-2 APA150-STD AX500-3 RTAX1000S-1 A54SX72A-3 RT54SX72S-1 Total 33% 33% 79% 42% 19% 61% 61% Performance 33 MHz 33 MHz 20 MHz 44 MHz 25 MHz 29 MHz 19 MHz Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S SX-A RTSX-S Sequential 621 621 621 739 739 765 765 Combinatorial 3923 3923 4249 2646 2646 2914 2914 Total 4544 4544 4870 3385 3385 3679 3679 Note: Data in this table was achieved using typical synthesis and layout settings. Performance was achieved using the Core8051 macro alone. Table 4 lists implementation data with OCI logic (256-word trace memory and one hardware trigger). Table 4 • Core8051 Device Utilization and Performance - OCI with 256-Word Trace Memory and One Hardware Trigger Cells or Tiles Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S Sequential 718 718 717 843 843 Combinatorial 4323 4323 4709 3023 3023 Total 5041 5041 5426 3866 3866 RAM Blocks 3 3 4 3 3 Utilization Device AFS600 A3PE600-2 APA150-STD AX500-3 RTAX1000S-1 Total 37% 37% 88% 48% 21% Performance 33 MHz 33 MHz 20 MHz 40 MHz 24 MHz Note: Data in this table was achieved using typical synthesis and layout settings. Performance was achieved using the Core8051 macro alone. 4 v6.0 Core8051 Core8051 Verification The comprehensive verification simulation testbench (included with the Netlist and RTL versions of the core) verifies correct operation of the Core8051 macro. The verification testbench applies several tests to the Core8051 macro, including: • • • Operation Code Tests Peripheral Tests Miscellaneous Tests Using the supplied user testbench as a guide, the user can easily customize the verification of the core by adding or removing tests. I/O Signal Descriptions The port signals for the Core8051 macro are defined in Table 5 on page 6 and illustrated in Figure 2. Core8051 has 239 I/O signals that are described in Table 5 on page 6. Core8051 nreset clk clkcpu clkper clkcpu_en clkper_en nrsto nrsto_nc int0 int1 int0a int1a int2 int3 int4 int5 int6 int7 t0 t1 rxd0i rxd0o txd0 TCK TMS TDI TDO TRSTB TraceA TraceDI TraceDO TraceWr port0i port1i port2i port3i port0o port1o port2o port3o ramdatai ramdatao ramaddr ramoe ramwe sfrdatai sfrdatao sfraddr sfroe sfrwe memdatai memdatao memaddr mempsacki mempsrd memacki memwr memrd dbgmempswr membank BreakIn BreakOut TrigOut AuxOut movx Figure 2 • Core8051 I/O Signal Diagram v6.0 5 Core8051 Table 5 • Core8051 Pin Description Name port0i port0o port1i port1o port2i port2o port3i port3o clk clkcpu clkper clkcpu_en Type Input Output Input Output Input Output Input Output Input Input Input Output Polarity/Bus Size Description 8 8 8 8 8 8 8 8 Rise Rise Rise High Port 0 8-bit bidirectional I/O port with separated inputs and outputs Port 1 8-bit bidirectional I/O port with separated inputs and outputs Port 2 8-bit bidirectional I/O port with separated inputs and outputs Port 3 8-bit bidirectional I/O port with separated inputs and outputs Clock input for internal logic CPU Clock input for internal controller logic (must either be the same as the clk input or a gated version of the clk input) Peripheral Clock input for internal peripheral logic (must either be the same as the clk input or a gated version of the clk input) CPU Clock Enable This output may be used to optionally create a gated version of the clk input signal for connection to the clkcpu input (see "Power Management Implementation" section on page 36). clkper_en Output High Peripheral Clock Enable This output may be used to optionally create a gated version of the clk input signal for connection to the clkper input (see "Power Management Implementation" section on page 36). nreset Input Low Hardware Reset Input A logic 0 on this pin for two clock cycles while the oscillator is running resets the device. nrsto Output Low Peripheral Reset Output This globally buffered signal can be connected to logic outside Core8051 to provide an active-low asynchronous reset to peripherals. nrsto_nc Bidirectional (no-connect) Low Peripheral Reset No-Connect This signal is connected to nrsto internally and is only used by the SX-A/RTSX-S implementations, in which case it must be brought up to a top-level package pin and left unconnected at the board-level. This signal should not be used (connected) for any other device families. High Movx instruction executing On-Chip Debug Interface (Optional) TCK TMS TDI TDO nTRST dbgmempswr Input Input Input Output Input Output Rise High High High Low High JTAG test clock. If OCI is not used, connect to logic 1. JTAG test mode select. If OCI is not used, connect to logic 0. JTAG test data in. If OCI is not used, connect to logic 0. JTAG test data out JTAG test reset. If OCI is not used, connect to logic 1. Optional debug program storage write movx Output 6 v6.0 Core8051 Table 5 • Core8051 Pin Description (Continued) Name membank BreakIn BreakOut Type Input Input Output Polarity/Bus Size Description 4 High High Optional code memory bank selection. If not used, connect to logic 0 values. Break bus input. When sampled high, a breakpoint is generated. If not used, connect to logic 0. Break bus output. This will be driven high when Core8051 stops emulation. This can be connected to an open-drain Break bus that connects to multiple processors, so that when any CPU stops, all others on the bus are stopped within a few clock cycles. Trigger output. This signal can be optionally connected to external test equipment to cross-trigger with internal Core8051 activity. Auxiliary output. This signal is an optional general-purpose output that can be controlled via the OCI debugger software. Trace address outputs. This bus should be connected to external RAM address pins for trace debug memory. Trace data to external synchronous RAM data input pins for trace debug memory. Trace data from external synchronous RAM data output pins for trace debug memory. If OCI is not used, connect to logic 0 values. Trace write signal to external synchronous RAM write enable for trace debug memory. External Interrupt Inputs int0 int1 int0a int1a int2 int3 int4 int5 int6 int7 Input Input Input Input Input Input Input Input Input Input Low/Fall Low/Fall High High High High High High High High External interrupt 0 External interrupt 1 External interrupt 0a External interrupt 1a External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Serial Port Interface rxdi rxdo txd Input Output Output – – – Serial port receive data Serial port transmit data in mode 0 Serial port transmit data or data clock in mode 0 Timer Inputs t0 t1 Input Input Fall Fall Timer 0 external input Timer 1 external input External Memory Interface mempsacki Input High Program memory read acknowledge TrigOut AuxOut TraceA TraceDI TraceDO TraceWr Output Output Output Output Input Output High High 8 20 20 High v6.0 7 Core8051 Table 5 • Core8051 Pin Description (Continued) Name memacki memdatai memdatao memaddr mempsrd memwr memrd Type Input Input Output Output Output Output Output Polarity/Bus Size Description High 8 8 16 High High High Data memory acknowledge Memory data input Memory data output Memory address Program store read enable Data memory write enable Data memory read enable Internal Data Memory Interface ramdatai ramdatao ramaddr ramwe ramoe Input Output Output Output Output 8 8 8 High High Data bus input Data bus output Data file address Data file write enable Data file output enable External Special Function Registers Interface sfrdatai sfrdatao sfraddr sfrwe sfroe Input Output Output Output Output 8 8 7 High High SFR data bus input SFR data bus output SFR address SFR write enable SFR output enable Memory Organization The Core8051 microcontroller utilizes the Harvard architecture, with separate code and data spaces. Memory organization in Core8051 is similar to that of the industry standard 8051. There are three memory areas, as shown in Figure 3: FFFFH FFFFH • • • Program Memory (Internal RAM, External RAM, or External ROM) External Data Memory (External RAM) Internal Data Memory (Internal RAM) C000H 8000H C000H 8000H 4000H 4000H FFH 0000H Program memory 0000H External data memory 00H Internal data memory Figure 3 • Core8051 Memory Map 8 v6.0 Core8051 Program Memory Core8051 can address up to 64kB of program memory space, from 0000H to FFFFH. The External Bus Interface services program memory when the mempsrd signal is active. Program memory is read when the CPU performs fetching instructions or MOVC. After reset, the CPU starts program execution from location 0000H. The lower part of the program memory includes interrupt and reset vectors. The interrupt vectors are spaced at eight-byte intervals, starting from 0003H. Program memory can be implemented as Internal RAM, External RAM, External ROM, or a combination of all three. active. Writing to external program memory is only supported in debug mode using the OCI logic block and external debugger hardware and software. Core8051 writes into external data memory when the CPU executes MOVX @Ri,A or MOVX @DPTR,A instructions. The external data memory is read when the CPU executes MOVX A,@Ri or MOVX A,@DPTR instructions. There is improved variable length of the MOVX instructions to access fast or slow external RAM and external peripherals. The three low-ordered bits of the ckcon register control stretch memory cycles. Setting ckcon stretch bits to logic 1 values enables access to very slow external RAM or external peripherals. Table 6 shows how the External Memory Interface signals change when stretch values are set from zero to seven. The widths of the signals are counted in clk cycles. The reset state of the ckcon register has a stretch value equal to one (001), which enables MOVX instructions to be performed with a single stretch clock cycle inserted. External Data Memory Core8051 can address up to 64kB of external data memory space, from 0000H to FFFFH. The External Bus Interface services data memory when the memrd signal is Table 6 • Stretch Memory Cycle Width ckcon Register ckcon.2 0 0 0 0 1 1 1 1 ckcon.1 0 0 1 1 0 0 1 1 ckcon.0 0 1 0 1 0 1 0 1 Stretch Value 0 1 2 3 4 5 6 7 Read Signal Width memaddr 1 2 3 4 5 6 7 8 memrd 1 2 3 4 5 6 7 8 Write Signal Width memaddr 2 3 4 5 6 7 8 9 memwr 1 1 2 3 4 5 6 7 There are two types of instructions; one provides an 8-bit address to the external data RAM, the other a 16-bit indirect address to the external data RAM. In the first instruction type, the contents of R0 or R1 in the current register bank provide an 8-bit address. The eight high ordered bits of address are stuck at zero. Eight bits are sufficient for external l/O expansion decoding or a relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output higher-order address bits. These pins are controlled by an output instruction preceding the MOVX. In the second type of MOVX instructions, the data pointer generates a 16-bit address. This form is faster and more efficient when accessing very large data arrays (up to 64kB), since no additional instructions are needed to set up the output ports. In some situations, it is possible to mix the two MOVX types. A large RAM array, with its high-order address lines, can be addressed via the data pointer or with code to output high-order address bits to any port followed by a MOVX instruction using R0 or R1. Internal Data Memory The internal data memory interface services up to 256 bytes of off-core data memory. The internal data memory address is always one byte wide. The memory space is 256 bytes large (00H to FFH) and can be accessed by direct or indirect addressing. The SFRs occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing accesses the upper 128 bytes of internal RAM. The lower 128 bytes contain work registers and bitaddressable memory. The lower 32 bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select which bank is in use. The next 16 bytes form a block of bit-addressable memory space at bit addressees 00H-7FH. All of the bytes v6.0 9 Core8051 in the lower 128 bytes are accessible through direct or indirect addressing. The internal data memory is not instantiated in Core8051. The user may use internal memory resources if the ProASICPLUS or Axcelerator families are used. The SX-A and RTSXS-S families have no internal memory resources, thus the user would need to either create and instantiate a distributed RAM (comprised of FPGA combinatorial and sequential cells) or use an external memory device. Special Function Registers Internal Special Function Registers A map of the internal Special Function Registers is shown in Table 7. Only a few addresses are occupied; the others are not implemented. Read access to unimplemented Table 7 • Internal Special Function Register Memory Map Bin Hex F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 X000 – b – acc – psw – – ien1 p3 ien0 p2 scon p1 tcon p0 X001 X010 – – – – – – – – – – – – – dps tl0 dpl X011 – – – – – – – – – – – – – – tl1 dph X100 – – – – – – – – – – – – – – th0 dpl1 X101 – – – – – – – – – – – – – – th1 dph1 X110 – – – – – – – – – – – – – – ckcon – X111 – – – – – – – – – – – – – – – pcon Hex FF F7 EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 addresses will return undefined data, while write access will have no effect. – – – – – – – – ip1 – ip0 – sbuf – tmod sp The reset value for of each of the predefined special function registers is listed in Table 8. Table 8 • Special Function Register Reset Values Register p0 sp dpl dph dpl1 Location 80h 81h 82h 83h 84h Reset value FFh 07h 00h 00h 00h Description Port 0 Stack Pointer Data Pointer Low 0 Data Pointer High 0 Dual Data Pointer Low 1 10 v6.0 Core8051 Table 8 • Special Function Register Reset Values (Continued) dph1 pcon tcon tmod tl0 tl1 th0 th1 ckcon p1 dps scon sbuf p2 ien0 ien1 p3 ip0 ip1 psw 85h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 90h 92h 98h 99h A0h A8h B8h B0h A9h B9h D0h 00h 00h 00h 00h 00h 00h 00h 00h 01h FFh 00h 00h 00h FFh 00h 00h FFh 00h 00h 00h Dual Data Pointer High 1 Power Control Timer/Counter Control Timer Mode Control Timer 0, low byte Timer 1, high byte Timer 0, low byte Timer 1, high byte Clock Control (Stretch=1) Port 1 Data Pointer Select Register Serial Port 0, Control Register Serial Port 0, Data Buffer Port 2 Interrupt Enable Register 0 Interrupt Enable Register 1 Port 3 Interrupt Enable Register 0 Interrupt Enable Register 1 Program Status Word External Special Function Registers The external SFR interface services up to 101 off-core special function registers. The off-core peripherals can use all addresses from the SFR address space range 80H to FFH except for those that are already implemented inside the core. When a read instruction occurs with a SFR address that has been implemented both inside and outside the core, the read will return the contents of the internal SFR. When a write instruction occurs with a SFR that has been implemented both inside and outside the core, the value of the external SFR is overwritten. Instruction Set All Core8051 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051. Table 9 on page 12 and Table 10 on page 12 contain notes for mnemonics used in the various Instruction Set tables. In Table 11 on page 12 through Table 15 on page 15, the instructions are ordered in functional groups. In Table 16 on page 16, the instructions are ordered in the hexadecimal order of the operation code. For more detailed information about the Core8051 instruction set, refer to the Core8051 Instruction Set Details User’s Guide. v6.0 11 Core8051 Table 9 • Notes on Data Addressing Modules Rn direct @Ri #data #data 16 bit A Working register R0-R7 128 internal RAM locations, any l/O port, control or status register Indirect internal or external RAM location addressed by register R0 or R1 8-bit constant included in instruction 16-bit constant included as bytes 2 and 3 of instruction 128 software flags, any bit-addressable l/O pin, control or status bit Accumulator Table 10 • Notes on Program Addressing Modes addr16 addr11 Rel Destination address for LCALL and LJMP may be anywhere within the 64kB program memory address space. Destination address for ACALL and AJMP will be within the same 2kB page of program memory as the first byte of the following instruction. SJMP and all conditional jumps include an 8-bit offset byte. Range is from plus 127 to minus 128 bytes, relative to the first byte of the following instruction. Functional Ordered Instructions Table 11 through Table 15 on page 15 lists the Core8051 instructions, grouped according to function. Table 11 • Arithmetic Operations Mnemonic ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,direct SUBB A,@Ri SUBB A,#data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri Description Adds the register to the accumulator Adds the direct byte to the accumulator Adds the indirect RAM to the accumulator Adds the immediate data to the accumulator Adds the register to the accumulator with a carry flag Adds the direct byte to A with a carry flag Adds the indirect RAM to A with a carry flag Adds the immediate data to A with carry a flag Subtracts the register from A with a borrow Subtracts the direct byte from A with a borrow Subtracts the indirect RAM from A with a borrow Subtracts the immediate data from A with a borrow Increments the accumulator Increments the register Increments the direct byte Increments the indirect RAM Decrements the accumulator Decrements the register Decrements the direct byte Decrements the indirect RAM Byte 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 1 2 Cycle 1 2 2 2 1 2 2 2 1 2 2 2 1 2 3 3 1 1 2 3 12 v6.0 Core8051 Table 11 • Arithmetic Operations (Continued) Mnemonic INC DPTR MUL A,B DIV A,B DA A Description Increments the data pointer Multiplies A and B Divides A by B Decimal adjust accumulator Byte 1 1 1 1 Cycle 3 5 5 1 Table 12 • Logic Operations Mnemonic ANL A,Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A,direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description AND register to accumulator AND direct byte to accumulator AND indirect RAM to accumulator AND immediate data to accumulator AND accumulator to direct byte AND immediate data to direct byte OR register to accumulator OR direct byte to accumulator OR indirect RAM to accumulator OR immediate data to accumulator OR accumulator to direct byte OR immediate data to direct byte Exclusive OR register to accumulator Exclusive OR direct byte to accumulator Exclusive OR indirect RAM to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to direct byte Exclusive OR immediate data to direct byte Clears the accumulator Complements the accumulator Rotates the accumulator left Rotates the accumulator left through carry Rotates the accumulator right Rotates the accumulator right through carry Swaps nibbles within the accumulator Byte 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Cycle 1 2 2 2 3 4 1 2 2 2 3 4 1 2 2 2 3 4 1 1 1 1 1 1 1 v6.0 13 Core8051 Table 13 • Data Transfer Operations Mnemonic MOV A,Rn MOV A,direct MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,direct MOV Rn,#data MOV direct,A MOV direct,Rn MOV direct,direct MOV direct,@Ri MOV direct,#data MOV @Ri,A MOV @Ri,direct MOV @Ri,#data MOV DPTR,#data16 MOVC A,@A + DPTR MOVC A,@A + PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH direct POP direct XCH A,Rn XCH A,direct XCH A,@Ri XCHD A,@Ri Description Moves the register to the accumulator Moves the direct byte to the accumulator Moves the indirect RAM to the accumulator Moves the immediate data to the accumulator Moves the accumulator to the register Moves the direct byte to the register Moves the immediate data to the register Moves the accumulator to the direct byte Moves the register to the direct byte Moves the direct byte to the direct byte Moves the indirect RAM to the direct byte Moves the immediate data to the direct byte Moves the accumulator to the indirect RAM Moves the direct byte to the indirect RAM Moves the immediate data to the indirect RAM Loads the data pointer with a 16-bit constant Moves the code byte relative to the DPTR to the accumulator Moves the code byte relative to the PC to the accumulator Moves the external RAM (8-bit address) to A Moves the external RAM (16-bit address) to A Moves A to the external RAM (8-bit address) Moves A to the external RAM (16-bit address) Pushes the direct byte onto the stack Pops the direct byte from the stack Exchanges the register with the accumulator Exchanges the direct byte with the accumulator Exchanges the indirect RAM with the accumulator Exchanges the low-order nibble indirect RAM with A Byte 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 Cycle 1 2 2 2 2 4 2 3 3 4 4 3 3 5 3 3 3 3 3-10 3-10 4-11 4-11 4 3 2 3 3 3 Table 14 • Boolean Manipulation Operations Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit Description Clears the carry flag Clears the direct bit Sets the carry flag Sets the direct bit Complements the carry flag Complements the direct bit Byte 1 2 1 2 1 2 Cycle 1 3 1 3 1 3 14 v6.0 Core8051 Table 14 • Boolean Manipulation Operations (Continued) ANL C,bit ANL C,bit ORL C,bit ORL C,bit MOV C,bit MOV bit,C AND direct bit to the carry flag AND complements of direct bit to the carry OR direct bit to the carry flag OR complements of direct bit to the carry Moves the direct bit to the carry flag Moves the carry flag to the direct bit 2 2 2 2 2 2 2 2 2 2 2 3 Table 15 • Program Branch Operations Mnemonic ACALL addr11 LCALL addr16 RET Return RETI Return AJMP addr11 LJMP addr16 SJMP rel JMP @A + DPTR JZ rel JNZ rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel CJNE A,direct,rel CJNE A,#data,rel CJNE Rn,#data rel CJNE @Ri,#data,rel DJNZ Rn,rel DJNZ direct,rel NOP Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if direct bit is set Jump if direct bit is not set Jump if direct bit is set and clears bit Compares direct byte to A and jumps if not equal Compares immediate to A and jumps if not equal Compares immediate to the register and jumps if not equal Compares immediate to indirect and jumps if not equal Decrements register and jumps if not zero Decrements direct byte and jumps if not zero No operation Byte 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 Cycle 6 6 4 4 3 4 3 2 3 3 3 3 4 4 4 4 4 4 4 3 4 1 v6.0 15 Core8051 Hexadecimal Ordered Instructions The Core8051 instructions are listed in order of hexidecimal opcode (operation code) in Table 16. Table 16 • Core8051 Instruction Set in Hexadecimal Order Opcode 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 40H 41H Mnemonic NOP AJMP addr11 LJMP addr16 RR A INC A INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 JB bit,rel AJMP addr11 RET RL A ADD A,#data ADD A,direct ADD A,@R0 ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 JC rel AJMP addr11 Opcode 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 50H 51H Mnemonic JBC bit,rel ACALL addr11 LCALL addr16 RRC A DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 JNB bit,rel ACALL addr11 RETI RLC A ADDC A,#data ADDC A,direct ADDC A,@R0 ADDC A,@R1 ADDC A,R0 ADDC A,R1 ADDC A,R2 ADDC A,R3 ADDC A,R4 ADDC A,R5 ADDC A,R6 ADDC A,R7 JNC rel ACALL addr11 16 v6.0 Core8051 Table 16 • Core8051 Instruction Set in Hexadecimal Order (Continued) Opcode 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 80H 81H 82H 83H 84H 85H Mnemonic ORL direct,A ORL direct,#data ORL A,#data ORL A,direct ORL A,@R0 ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORL A,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORL A,R7 JZ rel AJMP addr11 XRL direct,A XRL direct,#data XRL A,#data XRL A,direct XRL A,@R0 XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 SJMP rel AJMP addr11 ANL C,bit MOVC A,@A+PC DIV AB MOV direct,direct Opcode 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 90H 91H 92H 93H 94H 95H Mnemonic ANL direct,A ANL direct,#data ANL A,#data ANL A,direct ANL A,@R0 ANL A,@R1 ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7 JNZ rel ACALL addr11 ORL C,bit JMP @A+DPTR MOV A,#data MOV direct,#data MOV @R0,#data MOV @R1,#data MOV R0,#data MOV R1,#data MOV R2,#data MOV R3,#data MOV R4,#data MOV R5,#data MOV R6,#data MOV R7,#data MOV DPTR,#data16 ACALL addr11 MOV bit,C MOVC A,@A+DPTR SUBB A,#data SUBB A,direct v6.0 17 Core8051 Table 16 • Core8051 Instruction Set in Hexadecimal Order (Continued) Opcode 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH A0H A1H A2H A3H A4H A5H 1 Mnemonic MOV direct,@R0 MOV direct,@R1 MOV direct,R0 MOV direct,R1 MOV direct,R2 MOV direct,R3 MOV direct,R4 MOV direct,R5 MOV direct,R6 MOV direct,R7 ORL C,~bit AJMP addr11 MOV C,bit INC DPTR MUL AB – MOV @R0,direct MOV @R1,direct MOV R0,direct MOV R1,direct MOV R2,direct MOV R3,direct MOV R4,direct MOV R5,direct MOV R6,direct MOV R7,direct PUSH direct AJMP addr11 CLR bit CLR C SWAP A XCH A,direct XCH A,@R0 XCH A,@R1 XCH A,R0 XCH A,R1 Opcode 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H Mnemonic SUBB A,@R0 SUBB A,@R1 SUBB A,R0 SUBB A,R1 SUBB A,R2 SUBB A,R3 SUBB A,R4 SUBB A,R5 SUBB A,R6 SUBB A,R7 ANL C,~bit ACALL addr11 CPL bit CPL C CJNE A,#data,rel CJNE A,direct,rel CJNE @R0,#data,rel CJNE @R1,#data,rel CJNE R0,#data,rel CJNE R1,#data,rel CJNE R2,#data,rel CJNE R3,#data,rel CJNE R4,#data,rel CJNE R5,#data,rel CJNE R6,#data,rel CJNE R7,#data,rel POP direct ACALL addr11 SETB bit SETB C DA A DJNZ direct,rel XCHD A,@R0 XCHD A,@R1 DJNZ R0,rel DJNZ R1,rel A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H 18 v6.0 Core8051 Table 16 • Core8051 Instruction Set in Hexadecimal Order (Continued) Opcode CAH CBH CCH CDH CEH CFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH Mnemonic XCH A,R2 XCH A,R3 XCH A,R4 XCH A,R5 XCH A,R6 XCH A,R7 MOVX A,@DPTR AJMP addr11 MOVX A,@R0 MOVX A,@R1 CLR A MOV A,direct MOV A,@R0 MOV A,@R1 MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 Opcode DAH DBH DCH DDH DEH DFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Mnemonic DJNZ R2,rel DJNZ R3,rel DJNZ R4,rel DJNZ R5,rel DJNZ R6,rel DJNZ R7,rel MOVX @DPTR,A ACALL addr11 MOVX @R0,A MOVX @R1,A CPL A MOV direct,A MOV @R0,A MOV @R1,A MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A 1. The A5H opcode is not used by the original set of ASM51 instructions. In Core8051, this opcode is used to implement a trap instruction for the OCI debugger logic. Instruction Definitions All Core8051 core instructions can be condensed to 53 basic operations, alphabetically ordered according to the operation mnemonic section, as shown in Table 17. Table 17 • PSW Flag Modification (CY, OV, AC) Flag Instruction ADD ADDC SUBB MUL CY X X X 0 OV X X X X AC X X X – Instruction SETB C CLR C CPL C ANL C,bit CY 1 0 X X Flag OV – – – – AC – – – – Note: In this table, 'X' denotes that the indicated flag is affected by the instruction and can be a logic 1 or logic 0, depending upon specific calculations. If a particular box is blank, that flag is unaffected by the listed instruction. v6.0 19 Core8051 Table 17 • PSW Flag Modification (CY, OV, AC) (Continued) Flag Instruction DIV DA RRC RLC CJNE CY 0 X X X X OV X – – – – AC – – – – – Instruction ANL C,~bit ORL C,bit ORL C,~bit MOV C,bit CY X X X X Flag OV – – – – AC – – – – Note: In this table, 'X' denotes that the indicated flag is affected by the instruction and can be a logic 1 or logic 0, depending upon specific calculations. If a particular box is blank, that flag is unaffected by the listed instruction. Instruction Timing Program Memory Bus Cycle The execution for instruction N is performed during the fetch of instruction N+1. A program memory fetch cycle without wait states is shown in Figure 4. A program memory fetch cycle with wait states is shown in Figure 5 on page 21. A program memory read cycle without wait states is shown in Figure 6 on page 21. A program Table 18 • Conventions used in Figure 4 to Figure 19 Convention Tclk N (N) N+1 Addr Data read sample write sample ramcs Description Time period of clk signal Address of actually executed instruction Instruction fetched from address N Address of next instruction Address of memory cell Data read from address Addrl Point of reading the data from the bus into the internal register Point of writing the data from the bus into memory Off-core signal is made on the base ramwe and clk signals memory read cycle with wait states is shown in Figure 7 on page 22. The following conventions are used in Figure 4 to Figure 19 on page 27: 20 v6.0 Core8051 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk memaddr memrd memwr mempsrd mempswr N N+1 N+2 sample sample sample mempsack memdatao read sample read sample read sample (N+2) memdatai (N) (N+1) Figure 4 • Program Memory Fetch Cycle without Wait States 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk memaddr memrd memwr mempsrd mempswr sample sample sample sample sample N N+1 N+2 mempsack memdatao read sample read sample (N+1) read sample memdatai Figure 5 • Program Memory Fetch with Wait States 0ns 50ns 100ns (N) 150ns 200ns 250ns 300ns 350ns clk memaddr memrd memwr mempsrd mempswr N N+1 Addr N+1 sample sample sample mempsack memdatao memdatai (N) read sample Data (N+1) read sample read sample Figure 6 • Program Memory Read Cycle without Wait States v6.0 21 Core8051 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns clk memaddr memrd memwr mempsrd mempswr N N+1 Addr N+1 sample sample sample sample sample sample mempsack memdatao read sample read sample Data (N+1) read sample memdatai (N) Figure 7 • Program Memory Read Cycle with Wait States External Data Memory Bus Cycle Example bus cycles for external data memory access are shown in Figure 8 through Figure 15 on page 25. Figure 8 shows an external data memory read cycle without stretch cycles. 0ns 50ns 100ns 150ns 200ns 250ns clk memaddr memrd memwr mempsrd memdatao max. 1*Tclk N N+1 Addr N+1 memdatai (N) read sample Data (N+1) read sample read sample Figure 8 • External Data Memory Read Cycle without Stretch Cycles 22 v6.0 Core8051 Figure 9 shows an external data memory read cycle with one stretch cycle. 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns clk memaddr memrd memwr mempsrd mempswr N N+1 Addr N+1 sample sample sample sample sample sample mempsack memdatao read sample read sample Data (N+1) read sample memdatai (N) Figure 9 • External Data Memory Read Cycle with One Stretch Cycle Figure 10 shows an external data memory read cycle with two stretch cycles. 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk memaddr memrd memwr mempsrd memdatao max. 3*Tclk N N+1 Addr N+1 memdatai (N) read sample Data (N+1) read sample read sample Figure 10 • External Data Memory Read Cycle with Two Stretch Cycles Figure 11 shows an external data memory read cycle with seven stretch cycles. 0ns 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns 500ns clk memaddr memrd memwr mempsrd memdatao max. 8*Tclk N N+1 Addr N+1 memdatai (N) read sample Data (N+1) read read sample sample Figure 11 • External Data Memory Read Cycle with Seven Stretch Cycles v6.0 23 Core8051 Figure 12 shows an external data memory write cycle without stretch cycles. 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk memaddr memrd memwr mempsrd memdatao memdatai (N) read sample Data write sample (N+1) read sample N N+1 Addr N+1 Figure 12 • External Data Memory Write Cycle without Stretch Cycles Figure 13 shows an external data memory write cycle with one stretch cycle. 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk memaddr memrd memwr mempsrd memdatao memdatai (N) read sample Data write sample (N+1) read sample N N+1 Addr N+1 Figure 13 • External Data Memory Write Cycle with One Stretch Cycle Figure 14 shows an external data memory write cycle with two stretch cycles. 0ns clk memaddr memrd memwr mempsrd memdatao memdatai (N) read sample Data write sample (N+1) read sample N+1 Addr N+1 50ns 100ns 150ns 200ns 250ns 300ns 350ns 400ns Figure 14 • External Data Memory Write Cycle with Two Stretch Cycles 24 v6.0 Core8051 Figure 15 shows an external data memory write cycle with seven stretch cycles. 0ns 100ns 200ns 300ns 400ns 500ns clk memaddr memrd memwr mempsrd memdatao memdatai (N) read sample Data write sample (N+1) read sample Addr N+1 Figure 15 • External Data Memory Write Cycle with Seven Stretch Cycles v6.0 25 Core8051 Internal Data Memory Bus Cycle Example bus cycles for internal data memory access are shown in Figure 16 and Figure 17. Figure 16 shows an internal data memory read cycle. 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk ramaddr ramoe ramwe ramdatao Addr Addr max 1*Tclk max 1*Tclk max 1*Tclk Data max 1*Tclk ramdatai Data read sample read sample Figure 16 • Internal Data Memory Read Cycle Figure 17 shows an internal data memory write cycle. 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk ramaddr ramoe ramwe ramcs ramdatao ramdatai Addr Addr Data write sample Data write sample Figure 17 • Internal Data Memory Write Cycle 26 v6.0 Core8051 External Special Function Register Bus Cycle Example bus cycles for external SFR access are shown in Figure 18 and Figure 19. Figure 18 shows an external SFR read cycle. Figure 19 shows an external SFR write cycle. 0ns 50ns 100ns 150ns 200ns 250ns 300ns clk sfraddr sfroe sfrwe sfrdatao Addr Addr max 1*Tclk max 1*Tclk max 1*Tclk Data max 1*Tclk sfrdatai Data read sample read sample Figure 18 • External SFR Read Cycle 0ns 50ns 100ns 150ns 200ns 250ns 250ns clk sfraddr sfroe sfrwe sfrdatao sfrdatai Figure 19 • External SFR Write Cycle Addr Addr Data write sample Data write sample Core8051 Engine The main engine of Core8051 is composed of four components: • • • • Control Unit Arithmetic Logic Unit Memory Control Unit RAM and SFR Control Unit B Register (b) The b register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Program Status Word (psw) The psw register flags and bit functions are listed in Table 19 and Table 20 on page 28. Table 19 • psw Register Flags cy ac f0 rs1 rs ov – p The Core8051 engine controls instruction fetches from program memory and execution using RAM or SFR. This section describes the main engine registers. Accumulator (acc) The acc register is the accumulator. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to the accumulator as A, not ACC. v6.0 27 Core8051 Table 20 • psw Bit Functions Bit 7 6 5 4 3 2 1 0 Symbol Function cy ac f0 rs1 rs0 ov – p Carry flag Auxiliary carry flag for BCD operations General purpose flag 0 available for user Register bank select control bit 1, used to select working register bank Register bank select control bit 0, used to select working register bank Overflow flag User defined flag Parity flag, affected by hardware to indicate odd / even number of "one" bits in the accumulator, i.e. even parity Ports Ports p0, p1, p2, and p3 are SFRs. The contents of the SFR can be observed on corresponding pins on the chip. Writing a logic 1 to any of the ports causes the corresponding pin to be at a high level (logic 1), and writing a logic 0 causes the corresponding pin to be held at a low level (logic 0). All four ports on the chip are bidirectional. Each bit of each port consists of a register, an output driver, and an input buffer. Core8051 can output or read data through any of these ports if they are not used for alternate purposes. When a read-modify-write instruction is being performed, a port read will return the value of the output register bits of the port. When a read-modifywrite instruction is not being performed, a port read will return the value of the input bits of the port. The state of bits rs1 and rs0 from the psw register select the working registers bank as listed in Table 21. Table 21 • rs1/rs0 Bit Selections rs1/rs0 00 01 10 11 Bank selected Bank 0 Bank 1 Bank 2 Bank 3 Location (00H – 07H) (08H – 0FH) (10H – 17H) (18H – 1FH) Timers/Counters Timers 0 and 1 Core8051 has two 16-bit timer/counter registers: Timer 0 and Timer 1. Both can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, which means that it counts up after every 12 oscillator periods. In counter mode, the register is incremented when a falling edge is observed at the corresponding t0 or t1 input pin. Since it takes two machine cycles to recognize a logic 1 to logic 0 transition event, the maximum input count rate is 1/24 of the oscillator (clk input pin) frequency. There are no restrictions on the duty cycle. However, an input should be stable for at least one machine cycle (12 clock periods) to ensure proper recognition of a logic 0 or logic 1 value. Four operating modes can be selected for Timer 0 and Timer 1. Two SFRs (tmod and tcon) are used to select the appropriate mode. The various register flags, bit descriptions, and mode descriptions are listed in Table 22 to Table 24 on page 29. Stack Pointer (sp) The stack pointer is a one-byte register initialized to 07H after reset. This register is incremented before PUSH and CALL instructions, causing the stack to begin at location 08H. Data Pointer (dptr) The data pointer (dptr) is two bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded as a twobyte register (MOV DPTR,#data16) or as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g. MOVC A,@A+DPTR or MOV A,@DPTR respectively). Program Counter (pc) The program counter is two bytes wide, and is initialized to 0000H after reset. This register is incremented during fetching operation code or operation data from program memory. 28 v6.0 Core8051 Timer/Counter Mode Control Register (tmod) Table 22 displays the tmod register functions. Table 22 • tmod Register Flags MSB GATE C/T M1 M0 GATE C/T M1 LSB M0 Timer 1 Timer 0 Table 23 provides tmod register bits descriptions. Table 23 • tmod Register Bits Description Bit 7,3 Symbol Function GATE If set, enables external gate control (pin int0 or int1 for Counter 0 or Counter 1, respectively). When int0 or int1 is high, and the trx bit is set (see tcon register), the counter is incremented every falling edge on the t0 or t1 input pin. Selects Timer or Counter operation. When set to logic 1, a Counter operation is performed. When cleared to logic 0, the corresponding register will function as a Timer. Selects the mode for Timer/Counter 0 or Timer/Counter 1. Selects the mode for Timer/Counter 0 or Timer/Counter 1. 6, 2 5, 1 4, 0 C/T M1 M0 Table 24 provides timer and counter mode descriptions. Table 24 • Timers/Counter Mode Description M1 0 M0 0 Mode Mode 0 Function 13-bit Counter/Timer, with five lower bits in the tl0 or tl1 register and eight bits in the th0 or th1 register (for Timer 0 and Timer 1, respectively). The three high order bits of the tl0 and tl1 registers are held at zero. 16-bit Counter/Timer 8-bit auto-reload Counter/Timer. The reload value is kept in the th0 or th1 register, while the tl0 or tl1 register is incremented every machine cycle. When the tl0 or tl1 register overflows, the value in the th0 or th1 register is copied to the tl0 or tl1 register, respectively. If the M1 and M0 bits in Timer 1 are set to logic 1, Timer 1 stops. If the M1 and M0 bits in Timer 0 are set to logic 1, Timer 0 acts as two independent 8-bit Timers/Counters. 0 1 1 0 Mode 1 Mode2 1 1 Mode3 Note: The th0 register is affected by the tr1 bit in the tcon register. When the th0 register overflows, the tf1 flag in the tcon register is set. Timer/Counter Control Register (tcon) Table 25 displays the tcon register flags. Table 25 • tcon Register Flags MSB TF1 TR1 TF0 TR0 IE1 IT1 IE0 LSB IT0 v6.0 29 Core8051 Table 26 displays the tcon register bit functions. Table 26 • tcon Register Bit Functions Bit 7 6 5 4 3 2 1 0 Symbol Function TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Timer 1 overflow flag. This flag is set when Timer 1 overflows. This flag should be cleared by the user’s software. Timer 1 Run control bit. If cleared, Timer 1 stops. Timer 0 overflow flag. This flag is set when Timer 0 overflows. This flag should be cleared by the user’s software. Timer 0 Run control bit. If cleared, Timer 0 stops. Interrupt 1 edge flag. This flag is set when a falling edge on the external pin int1 is observed. This flag is cleared when an interrupt is processed. Interrupt 1 type control bit. This bit selects whether a falling edge or a low level on input pin int1 causes an interrupt. Interrupt 0 edge flag. This flag is set when a falling edge on the external pin int0 is observed. This flag is cleared when an interrupt is processed. Interrupt 0 type control bit. This bit selects whether a falling edge or a low level on input pin int0 causes an interrupt. Serial Interface Serial Port 0 The serial buffer consists of two separate registers: transmit buffer and receive buffer. Writing data to the SFR sbuf sets this data in the serial output buffer and starts the transmission. Reading from the sbuf register reads data from the serial receive buffer. The serial port can simultaneously transmit and receive data. It can also buffer one byte at receive, which prevents the receive data from being lost if the CPU reads the first byte before transmission of the second byte is completed. The serial port can operate in one of four modes. On receive, a start bit synchronizes the transmission, eight data bits are available by reading the sbuf register, and a stop bit sets the flag RB8 in the SFR scon. Mode 2 This mode is similar to Mode 1 but has two main differences. The baud rate is fixed at 1/32 or 1/64 of the oscillator (clk input) frequency, and the following 11 bits are transmitted or received: • • • • One Start Bit (0) Eight Data Bits (LSB first) One Programmable Ninth Bit One Stop Bit (1) Mode 0 In this mode, the rxd0i pin receives serial data and the rxd0o pin transmits serial data. The txd0 pin outputs the shift clock. Eight bits are transmitted with LSB first. The baud rate is fixed at 1/12 of the crystal (clk input) frequency. The ninth bit can be used to control the parity of the serial interface. At transmission, the TB8 bit in the scon register is output as the ninth bit, and at receive, the ninth bit affects the RB8 bit in the SFR scon. Mode 3 The only difference between Mode 2 and Mode 3 is that the baud rate is variable in Mode 3. Reception is initialized in Mode 0 by setting the RI flag in the scon register to logic 0 and the REN flag in the scon register to logic 1. In other modes, if the REN flag is a logic 1, the reception of serial data will begin with a start bit. Mode 1 In this mode, the rxd0i pin receives serial data and the txd0 pin transmits serial data. No external shift clock is used, and the following 10 bits are transmitted: • • • One Start Bit (always 0) Eight Data Bits (LSB first) One Stop Bit (always 1) Multiprocessor Communication The nine-bit reception feature in Modes 2 and 3 can be used for multiprocessor communication. In this case, the SM2 bit in the scon register is set to logic 1 by the slave processors. When the master processor outputs the slave address, it sets the ninth bit to logic 1, causing a serial 30 v6.0 Core8051 port receive interrupt in all the slaves. The slave processors compare the received byte with their network address. If there is a match, the addressed slave will clear SM2 and receive the rest of the message, while other slaves will leave the SM2 bit unaffected and ignore this message. After addressing the slave, the master will output the rest of the message with the ninth bit set to logic 0, so no serial port receive interrupt will be generated in unselected slaves. Serial Port Control Register (scon) The function of the serial port depends on the setting of the Serial Port Control Register scon. The various register flags, bit descriptions, mode descriptions, and baud rates are listed in Table 27 to Table 30. Note that in the following tables, fosc represents the frequency of the clk input signal. Table 27 • scon Register Flags MSB SM0 SM1 SM2 REN TB8 RB8 TI LSB RI Table 28 • scon Bit Functions Bit 7 6 5 4 3 2 1 0 Symbol Function SM0 SM1 SM2 REN TB8 RB8 TI RI Sets baud rate Sets baud rate Enables multiprocessor communication feature If set, enables serial reception. Cleared by software to disable reception. The ninth transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication, etc.). In Modes 2 and 3, the ninth data bit received. In Mode 1, if SM2 is '0', RB8 is the stop bit. In Mode 0 this bit is not used. Must be cleared by the software. Transmits the interrupt flag and is set by the hardware after completion of a serial transfer. Must be cleared by the software. Receives the interrupt flag and is set by the hardware after completion of a serial reception. Must be cleared by the software. Table 29 • Serial Port Modes SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate fosc/12 variable fosc/32 or /64 variable Generating Variable Baud Rate in Modes 1 and 3 In Modes 1 and 3, the Timer 1 overflow rate is used to generate baud rates. If Timer 1 is configured at auto in auto-reload mode to establish a baud rate, the following equation is useful: × fosc 2 Baud Rate = -----------------------------------------------------32 × 12 × ( 256 - th1 ) SMOD Table 30 • Serial Port Baud Rates Mode Mode 0 Mode 1,3 Mode 2 Baud Rate fosc12 Timer 1 overflow rate SMOD = 0 fosc/64 SMOD = 1 fosc/32 v6.0 31 Core8051 Interrupt Service Routine Unit Core8051 provides 13 interrupt sources with four priority levels. Each source has its own request flag(s) located in a SFR (tcon, scon). Each interrupt requested by the corresponding flag can be individually enabled or disabled by the enable bits in the ien0 and ien1 registers. There are two external interrupts accessible through pins int0 and int1: edge or level sensitive (falling edge or low level). There are also internal interrupts associated with Timer 0 and Timer 1, and an internal interrupt from the serial port. Special Function Registers Table 31 displays the Interrupt Enable 0 register (ie0). Table 31 • ien0 Register MSB eal – – es0 et1 ex1 et0 LSB ex0 Table 32 provides the ien0 bit functions. Table 32 • ien0 Bit Functions External Interrupts The choice between external (int0 and int1) interrupt level or transition activity is made by setting the IT1 and IT0 bits in the SFR tcon. When the interrupt event happens, a corresponding interrupt control bit is set in the tcon register (IE0 or IE1). This control bit triggers an interrupt if the appropriate interrupt bit is enabled. When the interrupt service routine is vectored, the corresponding control bit (IE0 or IE1) is cleared provided the edge triggered mode was selected. If level mode is active, the external requesting source controls flags IE0 or IE1 by the logic level on pins int0 or int1 (logic 0 or logic 1). During high to low transitions, recognition of an interrupt event is possible if both high and low levels last at least one machine cycle. Bit 7 6 5 4 3 2 1 0 Symbol Function eal – – es0 et1 ex1 et0 ex0 eal=0 – disable all interrupts Not used for interrupt control Not used for interrupt control es0=0 – disable serial channel 0 interrupt et1=0 – disable timer 1 overflow interrupt ex1=0 – disable external interrupt 1 et0=0 – disable timer 0 overflow interrupt ex0=0 – disable external interrupt 0 Table 33 displays the Interrupt Enable 1 register (ien1). Table 33 • ien1 Register MSB ex7 ex6 ex5 ex4 ex3 ex2 ex1 LSB ex0 Timer 0 and Timer 1 Interrupts Timer 0 and 1 interrupts are generated by the TF0 and TF1 flags in the tcon register, which are set by the rollover of Timer 0 and 1, respectively. When an interrupt is generated, the flag that caused this interrupt is cleared if Core8051 has accessed the corresponding interrupt service vector. This can be done only if the interrupt is enabled in the ien0 register. Table 34 provides the ien1 bit functions. Table 34 • ien1 Bit Functions Bit 7 6 5 4 3 2 1 0 Symbol Function ex7 ex6 ex5 ex4 ex3 ex2 ex1 ex0 ex7=0 – disable int7 ex6=0 – disable int6 ex5=0 – disable int5 ex4=0 – disable int4 ex3=0 – disable int3 ex2=0 – disable int2 ex1=0 – disable int1a ex0=0 – disable int0a Serial Port Interrupt The serial port interrupt is generated by logical OR of the TI and RI flags in the SFR scon. The TI flag is set after the data transmission completes. The RI flag is set when the last bit of the incoming serial data was read. Neither RI nor TI is cleared by Core8051, so the user’s interrupt service routine must clear these flags. 32 v6.0 Core8051 Priority Level Structure All interrupt sources are combined in priority level groups and controlled in terms of priority level by bits in the ip0 and ip1 registers. Table 35 displays the Interrupt Priority 0 register (ip0). Table 35 • ip0 Register MSB – – ip0.5 ip0.4 ip0.3 ip0.2 ip0.1 LSB ip0.0 Table 39 displays the polling sequence. Table 39 • Polling Sequence External interrupt 0(ie0) int0a int1a Timer 0 interrupt int2 External interrupt 1(ie1) Table 36 displays the Interrupt Priority 1 register (ip1). Table 36 • ip1 Register MSB – – ip1.5 ip1.4 ip1.3 ip1.2 ip1.1 LSB ip1.0 int3 Timer 1 interrupt int4 Serial channel 0 interrupt int5 int6 int7 Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in the special function register ip0 and one in ip1. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced first. For example, in Table 38 the two interrupts, Timer 0 interrupt and external pin int2, are combined in a priority group and are priority level controlled by the combination of bit0 from the ip0 register and bit0 from the ip1 register. Table 37 displays the priority levels. Table 37 • Priority Levels ip1.x 0 0 1 1 ip0.x 0 1 0 1 Priority Level Level0 (lowest) Level1 Level2 Level3 (highest) Interrupt Vectors The interrupt vector addresses are listed in Table 40. Table 40 • Interrupt Vector Addresses Interrupt Request Flags ie0 – External interrupt 0 tf0 – Timer 0 interrupt ie1 – External interrupt 1 tf1 – Timer 1 interrupt ri0/ti0 – Serial channel 0 interrupt int6 int0a int1a Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0083H 0043H 004BH 0053H 005BH 0063H 006BH Table 38 displays the groups of priority. Table 38 • Groups of Priority Bit ip1.0,ip0.0 ip1.1,ip0.1 ip1.2,ip0.2 ip1.3,ip0.3 ip1.4,ip0.4 ip1.5,ip0.5 Group External interrupt 0(ie0), int0a, int1a Timer 0 interrupt, int2 External interrupt 1(ie1), int3 Timer 1 interrupt, int4 Serial channel 0 interrupt, int5 int6, int7 int2 int3 int4 int5 int7 v6.0 33 Core8051 Interrupt Detect The interrupts int0a, int1a, and int2 to int7 are activated by level and the active state is logic 1 (high). Each of these interrupt pins must be held at a logic 1 value until Core8051 starts to service the affected interrupt. The user's software must take the appropriate action to clear each interrupt request (by writing to external peripherals via the external SFR interface). External Interrupt Connection (int) Table 41 displays the interrupt source connection. Table 41 • Interrupt Source Connection Interrupt ie0 ie1 Tf0 Tf1 Ri0 Ti0 int0a int1a int2 int3 int4 int5 int6 int7 Device – – Timer 0 Timer 1 Serial 0 Serial 0 – – – – – – – – Source External pin External pin – – – – External pin External pin External pin External pin External pin External pin External pin External pin Figure 20 on page 35 illustrates an overview of the interrupt service routine hardware within Core8051, including the polling sequence. 34 v6.0 Core8051 ISR Structure ien0.7 ie0 ien1.0 int0a ien1.1 int1a ien0.1 tf0 ien1.2 int2 ien0.2 ie1 ien1.3 int3 ien0.3 tf1 ien1.4 int4 ip1.3 ip0.3 ip1.2 ip0.2 ip1.1 ip0.1 vect ien0.0 ip1.0 ip0.0 l0 l1 l2 l3 ri0 >1 ti0 ien0.4 ip1.4 ip0.4 ien1.5 int5 ien1.6 int6 ien1.7 int7 ip1.5 ip0.5 Figure 20 • ISR Structure v6.0 polling sequence 35 Core8051 Power Management Unit The Power Management Unit monitors two power management modes: IDLE and STOP. Power Management Implementation Core8051 contains internal logic that allows the user to implement clock gating for the clkcpu (CPU clock) and clkper (peripheral clock) domains. If the user doesn’t require usage of the IDLE or STOP modes, Actel recommends connecting the three clock inputs (clk, clkcpu, and clkper) together, as shown in Figure 21 on page 37 (leaving the clkcpu_en and clkper_en output signals unconnected). If the user wishes to implement the IDLE and STOP power-saving modes, this can be realized by connecting Core8051 as shown in Figure 22 on page 37, where the user must connect two AND gates, external to Core8051, to accomplish the clock gating (making use of the clkcpu_en and clkper_en signals as well as the clk signal); the gated clock signals must then connect to the clkcpu and clkper input signals, as shown in Figure 22 on page 37. If the user connects Core8051 as shown in Figure 22 on page 37, Actel recommends using the clkper signal to connect to peripherals, as it will be active during the IDLE mode. Idle Mode Setting the idle bit of the pcon register invokes the IDLE mode. The IDLE mode can be used to leave internal clocks and peripherals running. Power consumption drops because the CPU is not active. The CPU can exit the IDLE state with any interrupts or a reset. Stop Mode Setting the stop bit of the pcon register invokes the STOP mode. All internal clocking in this mode can be turned off. The CPU will exit this state from a non-clocked external interrupt or a reset condition. Internally generated interrupts (timer, serial port, etc.) are not useful since they require clocking activity. Special Function Registers Table 42 displays the pcon register. Table 42 • pcon Register MSB smod – – – gf1 gf0 stop LSB idle Table 43 provides the pcon bit functions. Table 43 • pcon Bit Functions Bit 7 6 5 6 3 4 1 Symbol Function smod – – – gf1 gf0 stop Not used for power management – – – General purpose flag 1 General purpose flag 0 Stop mode control bit. Setting this bit places Core8051 into Stop Mode. This bit is always read as logic 0. Idle mode control bit. Setting this bit places Core8051 into Idle Mode. This bit is always read as logic 0. 0 idle 36 v6.0 Core8051 clkcpu clkper clk idle stop Core8051 clkcpu_en interrupt request clkper_en Figure 21 • Core8051 Unified Clock Domain Connection Diagram clkcpu clkper clk idle stop Core8051 clkcpu_en interrupt request clkper_en Figure 22 • Core8051 Power Management Connection Diagram Interface for On-Chip Instrumentation (Optional) The optional OCI unit serves as the interface for on-chip instrumentation. The OCI communicates with external debugger hardware and software as a debugging aid to the user. The following signals are not directly visible at the I/O pins of Core8051, they are connected internally between the OCI block and the main logic of Core8051: • • • • • • • • debugreq debugack debugstep debugprog fetch flush instr acc RTL licensees of Core8051 have access to these internal signals. The JTAG interface pins: TCK, TMS, TDI, TDO, and nTRT are used in conjunction with external debugger hardware and software to control and monitor the above-mentioned OCI signals. The Run/Stop Control The debugger controls the CPU with the debugreq signal. The debugreq signal stops the CPU at the next instruction and holds it in an idle state. When in an idle state, the CPU executes the NOP instruction and returns the debugack signal. The debugreq signal is synchronized to the microcontroller instruction cycle and phase, as shown in Figure 23 on page 38. Figure 23 demonstrates the behavior of the debugreq and debugack signals. The LCALL and the LJMP are sample instructions of a user program. v6.0 37 Core8051 rst clk debugreq debugack debugstep debugprog fetch flush instr NOP LCALL LJMP Figure 23 • The Run/Stop Control Single-Step Mode To execute one instruction in the debug mode, the OCI asserts a signal debugstep for one system clock. The CPU responds by negating debugack, executing one user or rst clk debugreq debugack debugstep debugprog fetch flush instr user instr NOP usr instr CPL bit NOP debugger instruction, and then asserting debugack. The OCI can set debugprog high for execution of a debugger instruction or set debugprog low for execution of a user instruction (see Figure 24). LCALL LJMP Figure 24 • Single-Step Mode Software Breakpoint When the CPU executes the opcode 0xA5, the core enters debug mode and asserts the debugack signal. The rst clk debugreq debugack debugstep debugprog fetch flush instr A5 NOP debugger responds by setting debugreq high. The CPU leaves the debug mode when debugreq is high for at least one clock period and then goes low. LCALL LJMP Figure 25 • Software Breakpoint 38 v6.0 Core8051 Debugger Program The debugger can submit an instruction to the CPU. The OCI logic uses a multiplexer on the program memory input bus (memdatai) to optionally override the user instruction with the debugger instruction. The interrupts are disabled during execution of the debugger program. Setting the interrupt flag does not cause an interrupt request. The power down IDLE and STOP modes are supported. The CPU can only exit the IDLE or STOP state with a reset. Program Trace Core8051 provides several signals for tracing program execution. Two signals, fetch and flush, are internally connected to the OCI logic to monitor instruction fetch activity. The fetch signal is active when Core8051 performs an instruction fetch, and the flush signal is active when Core8051 fetches the first instruction after a branch instruction. The following signals are used to connect Core8051 to optional external RAM devices for debug mode trace memory control: TraceA, TraceDI, TraceDO, and TraceWr. Example wrapper RTL source code is provided with the RTL and Netlist releases of Core8051 to illustrate the connection of the ProASICPLUS and Axcelerator RAM cells that are used as optional trace memory. Hardware Breakpoint The debugger can monitor the program memory address bus (memaddr) for optional hardware breakpoint addresses. When a fetch is noted from this address, the debugger can replace the original user instruction with opcode 0xA5. When the CPU executes the opcode 0xA5, the core enters the debug mode and asserts the debugack signal. The debugger responds by setting debugreq high. The OCI can monitor the external memory address and data buses (memaddr, memdatai, memdatao) to monitor the program execution. The buses to and from internal data memory (ramaddr, ramdatao, ramdatai) are also visible for monitoring. Access to ACC (Accumulator) Register The external debugger hardware and software can observe the contents of the ACC register by way of the optional OCI logic block (through the JTAG interface). Ordering Information Order Core8051 through your local Actel sales representative. Use the following numbering convention when ordering: Core8051-XX, where XX is listed in Table 44. Table 44 • Ordering Codes XX EV SN AN SR AR UR Description Evaluation Version Netlist for single-use on Actel devices Netlist for unlimited use on Actel devices RTL for single-use on Actel devices RTL for unlimited use on Actel devices RTL for unlimited use and not restricted to Actel devices v6.0 39 Core8051 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v6 . 0) v5.0 The "Supported Families" section has been updated to include Fusion. The "Core8051 Device Requirements" section has been updated to include Fusion data. v4.0 The "Supported Families" section has been updated to include ProASIC3/E data. The "Core8051 Device Requirements" section has been updated to include ProASIC3/E data. v3.0 The "Key Features" section has been updated. The "Core8051 Device Requirements" section has been updated. The "I/O Signal Descriptions" section has been updated. Figure 9 • External Data Memory Read Cycle with One Stretch Cycle has been updated. The “Ports” description has been updated. The "Power Management Block Diagram" section has been replaced with "Power Management Implementation" section. v2.0 Table 2 • Core8051 Device Utilization and Performance - No OCI was updated. Table 3 • Core8051 Device Utilization and Performance - OCI without Trace Memory and Hardware Trigger was updated. Table 4 • Core8051 Device Utilization and Performance - OCI with 256-Word Trace Memory and One Hardware Trigger was updated. The descriptive text under "I/O Signal Descriptions" has been changed. Figure 2 • Core8051 I/O Signal Diagram has been updated. Table 5 • Core8051 Pin Description has been updated. 6 5 Page 1 4 1 4 1 4 5 23 28 36 4 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. 40 v6.0 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 Actel Japan www.jp.actel.com EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong www.actel.com.cn Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 51700022-6/12.05