DM163025-1

PIC18(L)F2X/45K50 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology Universal Serial Bus Features: • USB V2.0 Compliant • Crystal-less Full Speed (12 Mb/s) and Low-Speed Operation (1.5 Mb/s) • Supports Control, Interrupt, Isochronous and Bulk Transfers • Supports up to 32 Endpoints (16 Bidirectional) • 1 Kbyte Dual Access RAM for USB • On-Chip USB Transceiver Flexible Oscillator Structure: • 3x and 4xPLL Clock Multipliers • Two External Clock modes, Up to 48 MHz (12 MIPS) • Internal 31 kHz Oscillator • Internal Oscillator, 31 kHz to 16 MHz - Factory calibrated to ± 1% - Self-tune to ± 0.20% max. from USB or secondary oscillator • Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown if any clock stops Peripheral Highlights: • Up to 33 I/O pins plus 3 Input-Only Pins: - High-current Sink/Source 25 mA/25 mA - Three programmable external interrupts - 11 programmable interrupts-on-change - Nine programmable weak pull-ups - Programmable slew rate • SR Latch • Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart - Pulse steering control • Capture/Compare/PWM (CCP) module • Master Synchronous Serial Port (MSSP) module Supporting 3-Wire SPI (all four modes) and I2C™ Master and Slave modes • Two Analog Comparators with Input Multiplexing • 10-Bit Analog-to-Digital (A/D) Converter module: - Up to 25 input channels - Auto-acquisition capability - Conversion available during Sleep  2012-2014 Microchip Technology Inc. • Digital-to-Analog Converter (DAC) module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection • High/Low-Voltage Detect module • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches • Enhanced USART module: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect Extreme Low-Power Management with XLP: • • • • Sleep mode: 20 nA, typical Watchdog Timer: 300 nA, typical Timer1 Oscillator: 800 nA @ 32 kHz Peripheral Module Disable Special Microcontroller Features: • Low-Power, High-Speed CMOS Flash Technology • C Compiler Optimized Architecture for Re-Entrant Code • Power Management Features: - Run: CPU on, peripherals on, SRAM on - Idle: CPU off, peripherals on, SRAM on - Sleep: CPU off, peripherals off, SRAM on • Priority Levels for Interrupts • Self-Programmable under Software Control • 8 x 8 Single-Cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s • Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins • In-Circuit Debug (ICD) with Three Breakpoints via Two Pins • Optional dedicated ICD/ICSP Port (44-pin TQFP Package Only) • Wide Operating Voltage Range: - F devices: 2.3V to 5.5V - LF devices: 1.8V to 3.6V • Flash Program Memory of 10,000 Erase/Write Cycles Minimum and 20-year Data Retention DS30000684B-page 1 PIC18(L)F2X/45K50 10-Bit A/D Channels Comparators CCP/ ECCP BOR/LVD CTMU MSSP EUSART Timers 8-bit/16-bit USB 2.0 PIC18(L)F2X/45K50 Family Types PIC18(L)F45K50 32K 16384 2048 256 40/44 36 25-ch 2 1/1 Yes Yes 1 1 2/2 Yes PIC18(L)F25K50 32K 16384 2048 256 28 25 14-ch 2 1/1 Yes Yes 1 1 2/2 Yes PIC18(L)F24K50 16K 8192 2048 256 28 25 14-ch 2 1/1 Yes Yes 1 1 2/2 Yes Program Memory Device Flash (bytes) Data Memory Data Single-Word SRAM EEPROM Instructions (bytes) Pins I/O (bytes) Pin Diagrams 28-PIN SPDIP (300 MIL), SOIC, SSOP MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 VUSB3V3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 D+ D- 28-PIN QFN 28 27 26 25 24 23 22 RA1 RA0 MCLR/VPP/RE3 RB7 RB6 RB5 RB4 FIGURE 2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18(L)F2XK50 FIGURE 1: 1 21 RB3 2 20 RB2 3 19 RB1 PIC18(L)F2XK50 4 18 RB0 5 17 VDD 6 16 VSS 7 15 RC7 RC0 8 RC1 9 RC2 10 VUSB3V3 11 D- 12 D+ 13 RC6 14 RA2 RA3 RA4 RA5 VSS RA7 RA6 Note: For the QFN package, it is recommended that the bottom pad be connected to VSS. DS30000684B-page 2  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 40-PIN PDIP (600 MIL) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 RC2 VUSB3V3 RD0 RD1 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 D+ DRD3 RD2 40-PIN UQFN 40 39 38 37 36 35 34 33 32 31 RC6 D+ DRD3 RD2 RD1 RD0 VUSB3V3 RC2 RC1 FIGURE 4: PIC18(L)F45K50 FIGURE 3: 1 2 3 4 5 6 7 8 9 10 PIC18(L)F45K50 30 RC0 29 RA6 28 RA7 27 VSS 26 VDD 25 RE2 24 RE1 23 RE0 22 RA5 21 RA4 RB3 RB4 RB5 RB6 RB7 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 Note: For the UQFN package, it is recommended that the bottom pad be connected to VSS.  2012-2014 Microchip Technology Inc. DS30000684B-page 3 PIC18(L)F2X/45K50 44-PIN TQFP PIC18(L)F45K50 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC/ICRST(1)/ICVPP(1) RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 NC/ICCK(1)/ICPGC(1) NC/ICDT(1)/ICPGD(1) RB4 RB5 RB6 RB7 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 RC6 D+ DRD3 RD2 RD1 RD0 VUSB3V3 RC2 RC1 NC FIGURE 5: Note 1: Special ICPORT programming/debug port features available when ICPRT = 1 DS30000684B-page 4  2012-2014 Microchip Technology Inc. AN2 C2IN+ RA3 5 2 5 20 22 AN3 ICD 21 Basic 19 Pull-up 4 Interrupts 1 Timers 4 MSSP RA2 EUSART C12IN1- CTCMP (E)CCP C12IN0- AN1 USB AN0 20 — — — — — — — — — — — — — — — — — — — — — — — — — VREFDACOUT — — — — — — — — — C1IN+ — — VREF+ — — — — — — — — — — 6 3 6 21 23 — C1OUT RA5 7 4 7 22 24 AN4 C2OUT SRQ — — — — — T0CKI — — — — SRNQ HLVDIN — — — SS — — — — — RA6 10 7 14 29 31 — — — — — — — — — — — — OSC2 CLKO — RA7 9 6 13 28 30 — — — — — — — — — — — — OSC1 CLKI — RB0 21 18 33 8 8 AN12 — — SRI — — FLT0 — SDI SDA — INT0 Y — — RB1 22 19 34 9 9 AN10 C12IN3- — — — — P1C(5) — SCK SCL — INT1 Y — — RB2 23 20 35 10 10 AN8 — CTED1 — — — P1B(5) RB3 24 21 — — — INT2 Y — — 36 11 11 AN9 C12IN2- CTED2 — — — CCP2(1) — SDO — — — — RB4 25 — 22 37 12 14 AN11 — — — — — P1D(5) — — — IOCB4 Y — RB5 — 26 23 38 13 15 AN13 — — — — — — — — T1G IOCB5 T3CKI(2) — — — RB6 27 24 39 14 16 — — — — — — — — — Y PGC — DS30000684B-page 5 Alternate CCP2 pin location based on Configuration bit. Alternate T3CKI pin location based on Configuration bits. Pins are enabled when ICPRT = 1, otherwise, they are disabled. Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50). Alternate SDO pin location based on Configuration bits. RE3 can be used for digital input only (no output functionality). — IOCB6 PIC18(L)F2X/45K50 RA4 Note 1: 2: 3: 4: 5: 6: 7: Reference 19 18 SR Latch 17 3 CTMU 2 28 Analog 27 3 40-Pin PDIP 2 RA1 28-Pin QFN Comparator 44-Pin TQFP 40-Pin UQFN 28-Pin SPDIP/SOIC/SSOP PIC18(L)F2X/45K50 PIN SUMMARY RA0 I/O  2012-2014 Microchip Technology Inc. TABLE 1: Interrupts Pull-up Basic — — — — IOCB7 Y PGD — — — — — SOSCO IOCC0 T1CKI T3CKI T3G — — — ICD Timers — — MSSP — — EUSART — — (E)CCP — — USB — — Reference — 32 SR Latch 17 30 CTMU 15 15 Comparator 40 8 Analog 25 11 44-Pin TQFP 28-Pin QFN 28 40-Pin UQFN 28-Pin SPDIP/SOIC/SSOP RB7 RC0 40-Pin PDIP I/O PIC18(L)F2X/45K50 PIN SUMMARY (CONTINUED) RC1 12 9 16 31 35 — — — — — — CCP2 — — SOSCI IOCC1 — — — RC2 13 10 17 32 36 AN14 — CTPLS — — — CCP1 P1A — — — IOCC2 — — — — 14 11 18 33 37 — — — — — VUSB3V3 — — — — — — VDDCORE — — 15 12 23 38 42 — — — — — D- — — — — IOCC4 — — — — 16 13 24 39 43 — — — — — D+ — — — — IOCC5 — — — RC6 17 14 25 40 44 AN18 — — — — — — TX CK — — IOCC6 — — — RC7 18 15 26 1 1 AN19 — — — — — — RX DT SDO(6) — IOCC7 — — — RD0 — — 19 34 38 AN20 — — — — — — — — — — — — —  2012-2014 Microchip Technology Inc. RD1 — — 20 35 39 AN21 — — — — — — — — — — — — — RD2 — — 21 36 40 AN22 — — — — — — — — — — — — — RD3 — — 22 37 41 AN23 — — — — — — — — — — — — — RD4 — — 27 2 2 AN24 — — — — — — — — — — — — — RD5 — — 28 3 3 AN25 — — — — — P1B(4) — — — — — — — RD6 — — 29 4 4 AN26 — — — — — P1C(4) — — — — — — — RD7 — — 30 5 5 AN27 — — — — — P1D(4) — — — — — — — Note 1: 2: 3: 4: 5: 6: 7: Alternate CCP2 pin location based on Configuration bit. Alternate T3CKI pin location based on Configuration bits. Pins are enabled when ICPRT = 1, otherwise, they are disabled. Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50). Alternate SDO pin location based on Configuration bits. RE3 can be used for digital input only (no output functionality). PIC18(L)F2X/45K50 DS30000684B-page 6 TABLE 1: 44-Pin TQFP Analog USB (E)CCP EUSART MSSP Timers Interrupts Pull-up Basic ICD 8 23 25 AN5 — — — — — — — — — — — — — — 9 24 26 AN6 — — — — — — — — — — — — — Reference 40-Pin UQFN — — SR Latch 40-Pin PDIP — RE1 CTMU 28-Pin QFN RE0 Comparator 28-Pin SPDIP/SOIC/SSOP PIC18(L)F2X/45K50 PIN SUMMARY (CONTINUED) I/O  2012-2014 Microchip Technology Inc. TABLE 1: RE2 — — 10 25 27 AN7 — — — — — — — — — — — — — RE3(7) 1 26 1 16 18 — — — — — — — — — — — Y MCLR VPP — — 20 17 11, 32 7, 26 7, 28 — — — — — — — — — — — — VDD — — 8, 19 5, 16 12, 31 6, 27 6, 29 — — — — — — — — — — — — VSS — — — — – –- 12(3) — — — — — — — — — — — — ICPGC(3) ICCK(3) (3) — — — — — — — — — — — — ICPGD (3) ICDT(3) — — — — — — — — — — — — ICVPP(3) — — — – –- 13 — — — –- –- 33(3) Alternate CCP2 pin location based on Configuration bit. Alternate T3CKI pin location based on Configuration bits. Pins are enabled when ICPRT = 1, otherwise, they are disabled. Location on 40/44-Pin parts (PIC18(L)F45K50). Function not on this pin on 28-Pin parts (PIC18(L)F2XK50). Location on 28-Pin parts (PIC18(L)F2XK50). Function not on this pin on 40/44-Pin parts (PIC18(L)F45K50). Alternate SDO pin location based on Configuration bits. RE3 can be used for digital input only (no output functionality). DS30000684B-page 7 PIC18(L)F2X/45K50 Note 1: 2: 3: 4: 5: 6: 7: ICRST(3) PIC18(L)F2X/45K50 Table of Contents 1.0 Device Overview ....................................................................................................................................................................... 10 2.0 Guidelines for Getting Started with PIC18(L)F2X/45K50 Microcontrollers ................................................................................ 23 3.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 28 4.0 Power-Managed Modes ............................................................................................................................................................ 52 5.0 Reset ......................................................................................................................................................................................... 63 6.0 Memory Organization ................................................................................................................................................................ 73 7.0 Flash Program Memory ............................................................................................................................................................. 95 8.0 Data EEPROM Memory .......................................................................................................................................................... 104 9.0 8 x 8 Hardware Multiplier......................................................................................................................................................... 109 10.0 Interrupts .................................................................................................................................................................................. 111 11.0 I/O Ports .................................................................................................................................................................................. 128 12.0 Timer0 Module......................................................................................................................................................................... 153 13.0 Timer1/3 Module with Gate Control......................................................................................................................................... 156 14.0 Timer2 Module......................................................................................................................................................................... 168 15.0 Capture/Compare/PWM Modules............................................................................................................................................ 172 16.0 Master Synchronous Serial Port (MSSP) Module ................................................................................................................... 203 17.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................................................. 258 18.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................. 287 19.0 Comparator Module................................................................................................................................................................. 301 20.0 Charge Time Measurement Unit (CTMU)................................................................................................................................ 310 21.0 SR Latch.................................................................................................................................................................................. 325 22.0 Fixed Voltage Reference (FVR)............................................................................................................................................... 330 23.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 332 24.0 Universal Serial Bus (USB) ..................................................................................................................................................... 336 25.0 High/Low-Voltage Detect (HLVD) ............................................................................................................................................ 364 26.0 Special Features of the CPU ................................................................................................................................................... 370 27.0 Instruction Set Summary ......................................................................................................................................................... 390 28.0 Development Support.............................................................................................................................................................. 440 29.0 Electrical Specifications ........................................................................................................................................................... 444 30.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 485 31.0 Packaging Information............................................................................................................................................................. 486 Appendix A: Revision History............................................................................................................................................................ 503 Appendix B: Device Differences........................................................................................................................................................ 504 The Microchip Web Site .................................................................................................................................................................... 505 Customer Change Notification Service ............................................................................................................................................. 505 Customer Support ............................................................................................................................................................................. 505 Product Identification System............................................................................................................................................................ 506 DS30000684B-page 8  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2012-2014 Microchip Technology Inc. DS30000684B-page 9 PIC18(L)F2X/45K50 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18(L)F45K50 • PIC18(L)F25K50 • PIC18(L)F24K50 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Flash program memory. On top of these features, the PIC18(L)F2X/45K50 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 1.1.1 New Core Features XLP TECHNOLOGY All of the devices in the PIC18(L)F2X/45K50 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. • Peripheral Module Disable bits: User code can power down individual peripheral modules during Run and Idle modes for further lowering dynamic power reduction. • On-the-fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. • Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 29.0 “Electrical Specifications” for values. 1.1.2 UNIVERSAL SERIAL BUS (USB) Devices in the PIC18(L)F2X/45K50 family incorporate a fully-featured USB communications module with a built-in transceiver that is compliant with the USB Specification Revision 2.0. The module supports both low-speed and full-speed communication for all supported data transfer types. The device incorporates its own on-chip transceiver and 3.3V regulator for USB. DS30000684B-page 10 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18(L)F2X/45K50 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes, using crystals or ceramic resonators • Six External Clock modes, offering the option of using two pins (oscillator input and a divide-byfour clock output) or one pin (oscillator input, with the second pin reassigned as general I/O) • Two External RC Oscillator modes with the same pin options as the External Clock modes • An internal oscillator block which contains a 16 MHz HFINTOSC oscillator and a 31 kHz INTRC oscillator, which together provide eight user selectable clock frequencies, from 31 kHz to 16 MHz. This option frees the two oscillator pins for use as additional general purpose I/O. • 3x and 4x Phase Lock Loop (PLL) frequency multipliers, available to both external and internal oscillator modes, which allows clock speeds of up to 48 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 48 MHz – all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Active Clock Tuning: This option allows the internal oscillator to automatically tune itself to match USB host or external 32.768 kHz secondary oscillator clock sources. Full-speed USB operation can now meet specification requirements without an external crystal, enabling lower-cost designs. • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the INTRC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 1.2 Other Special Features • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Extended Instruction Set: The PIC18(L)F2X/ 45K50 family introduces an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. • Enhanced CCP module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include: - Auto-shutdown, for disabling PWM outputs on interrupt or other select conditions - Auto-restart, to reactivate outputs once the condition has cleared - Output steering to selectively enable one or more of four outputs to provide the PWM signal. • Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. • Dedicated ICD/ICSP™ Port: These devices introduce the use of debugger and programming pins that are not multiplexed with other microcontroller features. Offered as an option in the TQFP packaged devices, this feature allows users to develop I/O intensive applications while retaining the ability to program and debug in the circuit.  2012-2014 Microchip Technology Inc. • Charge Time Measurement Unit (CTMU): The CTMU is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Together with other on-chip analog modules, the CTMU can precisely measure time, measure capacitance or relative changes in capacitance or generate output pulses that are independent of the system clock. • SR Latch Output: A single SR latch with multiple Set and Reset inputs as well as separate latch outputs. 1.3 Details on Individual Family Members Devices in the PIC18(L)F2X/45K50 family are available in 28-pin and 40/44-pin packages. The block diagram for the device family is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. Flash program memory A/D channels I/O ports Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in the pin summary table (Table 1) and I/O description tables (Table 1-2 and Table 1-3). DS30000684B-page 11 PIC18(L)F2X/45K50 TABLE 1-1: DEVICE FEATURES Features PIC18(L)F24K50 PIC18(L)F25K50 PIC18(L)F45K50 Program Memory (Bytes) 16384 32768 32768 Program Memory (Instructions) 8192 16384 16384 Data Memory (Bytes) 2048 2048 2048 Data EEPROM Memory (Bytes) 256 256 (1) I/O Ports A, B, C, E Capture/Compare/PWM Modules (CCP) Enhanced CCP Modules (ECCP) 10-bit Analog-to-Digital Module (ADC) Packages 1 256 (1) A, B, C, E 1 1 1 1 1 3 internal 14 input 3 internal 14 input 3 internal 25 input 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 40-pin PDIP 40-pin UQFN 44-pin TQFP Interrupt Sources 25 Timers (16-bit) 2 Serial Communications MSSP, EUSART SR Latch Yes Charge Time Measurement Unit Module (CTMU) Yes Programmable High/Low-Voltage Detect (HLVD) Yes Programmable Brown-out Reset (BOR) Yes Resets (and Delays) Instruction Set Operating Frequency Note 1: A, B, C, D, E POR, BOR, LPBOR RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT 75 Instructions; 83 with Extended Instruction Set enabled DC – 48 MHz PORTE contains the single RE3 read-only bit. DS30000684B-page 12  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 1-1: PIC18(L)F2X/45K50 FAMILY BLOCK DIAGRAM Data Bus Table Pointer Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA0:RA7 12 Data Address 31-Level Stack 4 BSR Address Latch Program Memory (16/32 Kbytes) STKPTR 12 FSR0 FSR1 FSR2 Data Latch 8 4 Access Bank PORTB 12 RB0:RB7 inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus PORTC RC0:RC3 RC6:RC7 IR 8 State machine control signals Instruction Decode and Control PRODH PRODL PORTD 8 x 8 Multiply 3 8 W BITOP 8 Internal Oscillator Block OSC1(2) (2) OSC2 SOSCI INTRC Oscillator SOSCO 16 MHz Oscillator Single-Supply Programming In-Circuit Debugger MCLR(1) BOR HLVD FVR DAC Note Comparators C1/C2 Data EEPROM ECCP1 CCP2 Power-up Timer 8 8 8 8 Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor PORTE ALU RE0:RE2 8 Precision Band Gap Reference RD0:RD7 RE3(1) FVR Timer0 Timer1 Timer3 Timer2 CTMU DAC USB MSSP EUSART SR Latch ADC 10-bit FVR DAC 1: RE3 is only available when MCLR functionality is disabled. 2: OSC1/CLKIN and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 6.0 “Memory Organization” for additional information.  2012-2014 Microchip Technology Inc. DS30000684B-page 13 PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS Pin Number SPDIP, SOIC, SSOP QFN 2 27 3 4 5 6 7 10 Legend: Note 1: 2: Pin Name 28 1 2 3 4 7 Pin Type Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O TTL/DIG C12IN0- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O TTL/DIG C12IN1- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN1 I Analog Analog input 1. RA2 I/O TTL/DIG C2IN+ I Analog RA2/C2IN+/AN2/DACOUT/VREFDigital I/O. Comparator C2 non-inverting input. AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. RA3 I/O TTL/DIG C1IN+ I Analog RA3/C1IN+/AN3/VREF+ Digital I/O. Comparator C1 non-inverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. RA4/C1OUT/SRQ/T0CKI RA4 I/O ST/DIG C1OUT O DIG Comparator C1 output. Digital I/O. SRQ O DIG SR latch Q output. T0CKI I ST Timer0 external clock input. RA5/C2OUT/SRNQ/SS/HLVDIN/AN4 RA5 I/O TTL/DIG C2OUT O DIG Digital I/O. SRNQ O DIG SR latch Q output. SS I TTL SPI slave select input (MSSP). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. Comparator C2 output. RA6/CLKO/OSC2 RA6 I/O TTL/DIG CLKO O DIG OSC2 O — Digital I/O. Outputs 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator modes. TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. DS30000684B-page 14  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, SOIC, SSOP QFN 9 6 21 22 23 24 Pin Type Buffer Type RA7 I/O TTL/DIG CLKI I CMOS External clock source input. Always associated with pin function OSC1. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. Pin Name 18 19 20 21 RA7/CLKI/OSC1 Note 1: 2: Digital I/O. RB0/INT0/FLT0/SRI/SDI/SDA/AN12 RB0 I/O TTL/DIG INT0 I ST External interrupt 0. FLT0 I ST PWM Fault input for ECCP auto-shutdown. Digital Output or Input with internal pull-up option. SRI I ST SR latch input. SDI I ST SPI data in (MSSP). SDA I/O I2C™ I2C data I/O (MSSP). AN12 I Analog Analog input 12. RB1/INT1/P1C/SCK/SCL/C12IN3-/AN10 RB1 I/O TTL/DIG INT1 I ST External interrupt 1. P1C O DIG Enhanced CCP1 PWM output. SCK I/O ST/DIG Synchronous serial clock input/output for SPI mode (MSSP). SCL I/O I2C Synchronous serial clock input/output for I2C mode (MSSP). C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. Digital Output or Input with internal pull-up option. RB2/INT2/CTED1/P1B/AN8 RB2 I/O TTL/DIG INT2 I ST External interrupt 2. CTED1 I ST CTMU Edge 1 input. P1B O DIG Enhanced CCP1 PWM output. AN8 I Analog Digital Output or Input with internal pull-up option. I/O TTL/DIG Analog input 8. RB3/CTED2/CCP2/SDO/C12IN2-/AN9 RB3 Legend: Description Digital Output or Input with internal pull-up option. CTED2 I ST CCP2(2) I/O ST/DIG CTMU Edge 2 input. SDO(1) O DIG C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. Alternate Capture 2 input/Compare 2 output/PWM 2 output. SPI data out (MSSP). TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear.  2012-2014 Microchip Technology Inc. DS30000684B-page 15 PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, SOIC, SSOP QFN 25 22 Pin Name 27 28 11 12 Legend: Note 1: 2: 23 24 25 8 9 Buffer Type I/O TTL/DIG Description RB4/IOCB4/P1D/AN11 RB4 26 Pin Type Digital Output or Input with internal pull-up option. IOCB4 I TTL Interrupt-on-change pin. P1D O DIG Enhanced CCP1 PWM output. AN11 I Analog Analog input 11. RB5/IOCB5/T3CKI/T1G/AN13 RB5 I/O TTL/DIG IOCB5 I TTL Interrupt-on-change pin. Digital Output or Input with internal pull-up option. T3CKI(2) I ST Alternate Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. RB6/IOCB6/PGC RB6 I/O TTL/DIG IOCB6 I TTL Interrupt-on-change pin. Digital Output or Input with internal pull-up option. PGC I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/IOCB7/PGD RB7 I/O TTL/DIG IOCB7 I TTL PGD I/O ST/DIG Digital Output or Input with internal pull-up option. Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming data pin. RC0/IOCC0/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST/DIG IOCC0 I TTL Interrupt-on-change pin. Digital I/O. T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. RC1/IOCC1/CCP2/SOSCI RC1 I/O ST/DIG IOCC1 I TTL Digital I/O. CCP2(1) I/O ST/DIG Capture 2 input/Compare 2 output/PWM 2 output. SOSCI I Analog Secondary oscillator input. Interrupt-on-change pin. TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. DS30000684B-page 16  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 1-2: PIC18(L)F2XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number SPDIP, SOIC, SSOP QFN 13 10 Pin Name 15 16 17 18 1 11 12 13 14 15 26 Buffer Type I/O ST/DIG Description RC2/CTPLS/P1A/CCP1/IOCC2/AN14 RC2 14 Pin Type Digital I/O. CTPLS O DIG CTMU pulse generator output. P1A O DIG Enhanced CCP1 PWM output. CCP1 I/O ST/DIG IOCC2 I TTL AN14 I Analog VUSB3V3 P — Capture 1 input/Compare 1 output/PWM 1 output. Interrupt-on-change pin. Analog input 14. VUSB3V3 Internal 3.3V voltage regulator output, positive supply for USB transceiver. D-/IOCC4 D- I/O — USB differential minus line input/output. IOCC4 I ST Interrupt-on-change pin. D+ I/O — USB differential plus line input/output. IOCC5 I ST Interrupt-on-change pin. RC6 I/O ST/DIG IOCC6 I TTL D+/IOCC5 RC6/IOCC6/TX/CK/AN18 Digital I/O. Interrupt-on-change pin. TX O DIG EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). AN18 I Analog Analog input 18. RC7/SDO/IOCC7/RX/DT/AN19 RC7 I/O ST/DIG SDO(2) O DIG Digital I/O. IOCC7 I TTL Interrupt-on-change pin. RX I ST EUSART asynchronous receive. DT I/O ST/DIG EUSART synchronous data (see related TX/CK). AN19 I Analog Analog input 19. RE3 I ST VPP P MCLR I ST Alternate SPI data out pin assignment (MSSP). RE3/VPP/MCLR Digital input. Programming voltage input. Active-Low Master Clear (device Reset) input. 20 17 VDD P — Positive supply for logic and I/O pins. 8, 19 5, 16 VSS P — Ground reference for logic and I/O pins. Legend: Note 1: 2: TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear.  2012-2014 Microchip Technology Inc. DS30000684B-page 17 PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP TQFP UQFN 2 19 17 3 4 5 6 7 14 13 20 21 22 23 24 31 30 19 20 21 22 29 28 Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O TTL/DIG Digital I/O. C12IN0- I Analog Comparators C1 and C2 inverting input. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O TTL/DIG Digital I/O. C12IN1- I Analog Comparators C1 and C2 inverting input. AN1 I Analog Analog input 1. RA2/C2IN+/AN2/DACOUT/VREFRA2 I/O TTL/DIG Digital I/O. C2IN+ I Analog AN2 I Analog Analog input 2. DACOUT O Analog DAC Reference output. VREF- I Analog A/D reference voltage (low) input. Comparator C2 non-inverting input. RA3/C1IN+/AN3/VREF+ RA3 I/O C1IN+ I TTL/DIG Digital I/O. Analog Comparator C1 non-inverting input. AN3 I Analog Analog input 3. VREF+ I Analog A/D reference voltage (high) input. Digital I/O. RA4/C1OUT/SRQ/T0CKI RA4 I/O ST/DIG C1OUT O DIG Comparator C1 output. SRQ O TTL SR latch Q output. T0CKI I ST Timer0 external clock input. RA5/C2OUT/SRNQ/SS/HLVDIN/AN4 RA5 I/O TTL/DIG Digital I/O. C2OUT O DIG Comparator C2 output. SRNQ O DIG SR latch Q output. SS I TTL SPI slave select input (MSSP). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4. RA6/CLKO/OSC2 RA6 I/O CLKO O TTL/DIG Digital I/O. DIG OSC2 O — Outputs 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. RA7/CLKI/OSC1 RA7 I/O CLKI I TTL/DIG Digital I/O. CMOS OSC1 I ST External clock source input. Always associated with pin function OSC1. Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Legend: Note 18 Pin Type 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set. DS30000684B-page 18  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP UQFN 33 8 8 34 35 36 37 9 9 10 11 14 10 11 12 15 Description RB0 I/O INT0 I TTL/DIG Digital Output or Input with internal pull-up option. ST External interrupt 0. FLT0 I ST PWM Fault input for ECCP auto-shutdown. SDI I ST SPI Data in (MSSP). SDA I/O I2C™ I2C Data I/O (MSSP). SRI I ST AN12 I Analog SR latch input. Analog input 12. RB1/INT1/P1C/SCK/SCL/C12IN3-/AN10 RB1 I/O INT1 I TTL/DIG Digital Output or Input with internal pull-up option. ST External interrupt 1. Enhanced CCP1 PWM output. P1C O DIG SCK I/O ST/DIG Synchronous serial clock input/output for SPI mode (MSSP). SCL I/O I2C Synchronous serial clock input/output for I2C mode (MSSP). C12IN3- I Analog Comparators C1 and C2 inverting input. AN10 I Analog Analog input 10. RB2/P1B/INT2/CTED1/AN8 RB2 I/O P1B O TTL/DIG Digital Output or Input with internal pull-up option. DIG Enhanced CCP1 PWM output. External interrupt 2. INT2 I ST CTED1 I ST AN8 I Analog CTMU Edge 1 input. Analog input 8. RB3/CTED2/SDO/CCP2/C12IN2-/AN9 RB3 I/O CTED2 I TTL/DIG Digital Output or Input with internal pull-up option. ST SDO(1) O DIG SPI Data out (MSSP). CCP2(2) I/O ST Alternate Capture 2 input/Compare 2 output/PWM 2 output. C12IN2- I Analog Comparators C1 and C2 inverting input. AN9 I Analog Analog input 9. CTMU Edge 2 input. RB4/IOCB4/P1D/AN11 I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB4 I TTL Interrupt-on-change pin. P1D O DIG Enhanced CCP1 PWM output. AN11 I Analog Analog input 11. RB5/IOCB5/T3CKI/T1G/AN13 RB5 I/O IOCB5 I TTL/DIG Digital Output or Input with internal pull-up option. TTL Interrupt-on-change pin. T3CKI(2) I ST Alternate Timer3 clock input. T1G I ST Timer1 external clock gate input. AN13 I Analog Analog input 13. TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Legend: Note 13 Buffer Type RB0/INT0/FLT0/SDI/SDA/SRI/AN12 RB4 38 Pin Type 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set.  2012-2014 Microchip Technology Inc. DS30000684B-page 19 PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP UQFN 39 16 14 17 15 16 17 32 35 36 30 31 32 23 24 37 42 43 38 39 TTL/DIG Digital Output or Input with internal pull-up option. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming clock pin. RB7/IOCB7/PGD I/O TTL/DIG Digital Output or Input with internal pull-up option. IOCB7 I TTL Interrupt-on-change pin. PGD I/O ST In-Circuit Debugger and ICSP™ programming data pin. RC0/IOCC0/T3CKI/T3G/T1CKI/SOSCO RC0 I/O ST/DIG Digital I/O. IOCC0 I TTL Interrupt-on-change pin. T3CKI(1) I ST Timer3 clock input. T3G I ST Timer3 external clock gate input. T1CKI I ST Timer1 clock input. SOSCO O — Secondary oscillator output. RC1/IOCC1/CCP2/SOSCI RC1 I/O ST/DIG IOCC1 I TTL Digital I/O. CCP2(1) I/O ST/DIG Capture 2 input/Compare 2 output/PWM 2 output. SOSCI I Analog Secondary oscillator input. Interrupt-on-change pin. RC2/CTPLS/P1A/CCP1/IOCC2/AN14 I/O ST/DIG Digital I/O. CTPLS O DIG CTMU pulse generator output. P1A O DIG Enhanced CCP1 PWM output. CCP1 I/O ST/DIG IOCC2 I TTL AN14 I Analog VUSB3V3 P — Capture 1 input/Compare 1 output/PWM 1 output. Interrupt-on-change pin. Analog input 14. VUSB3V3 Internal 3.3V voltage regulator output, positive supply for USB transceiver. D-/IOCC4 D- I/O — USB differential minus line input/output. IOCC4 I ST Interrupt-on-change pin. D+/IOCC5 D+ I/O — USB differential plus line input/output. IOCC5 I ST Interrupt-on-change pin. TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Legend: Note 33 I/O PGC RC2 18 Description IOCB6 RB7 15 Buffer Type RB6/IOCB6/PGC RB6 40 Pin Type 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set. DS30000684B-page 20  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP UQFN 25 44 40 1 1 20 21 22 27 28 29 30 38 39 40 41 2 3 4 5 ST/DIG 35 36 37 2 3 4 5 Digital I/O. IOCC6 I TTL TX O — EUSART asynchronous transmit. CK I/O ST EUSART synchronous clock (see related RX/DT). AN18 I Analog Interrupt-on-change pin. Analog input 18. RC7/RX/DT/SDO/IOCC7/AN19 RC7 I/O ST/DIG RX I ST EUSART asynchronous receive. Digital I/O. DT I/O ST EUSART synchronous data (see related TX/CK). SDO O DIG Alternate SPI data out (MSSP). IOCC7 I TTL Interrupt-on-change pin. AN19 I Analog RD0 I/O ST/DIG Digital I/O. AN20 I Analog Analog input 20. RD1 I/O ST/DIG Digital I/O. AN21 I Analog Analog input 21. RD2 I/O ST/DIG Digital I/O AN22 I Analog Analog input 22. RD3 I/O ST/DIG Digital I/O. AN23 I Analog Analog input 23. RD4 I/O ST/DIG Digital I/O. AN24 I Analog Analog input 24. RD5 I/O ST/DIG Digital I/O. P1B O DIG AN25 I Analog Analog input 25. RD6 I/O ST/DIG Digital I/O. P1C O DIG AN26 I Analog Analog input 26. RD7 I/O ST/DIG Digital I/O. P1D O DIG AN27 I Analog Analog input 19. RD0/AN20 RD1/AN21 RD2/AN22 RD3/AN23 RD4/AN24 RD5/P1B/AN25 Enhanced CCP1 PWM output. RD6/P1C/AN26 Enhanced CCP1 PWM output. RD7/P1D/AN27 Enhanced CCP1 PWM output. Analog input 27. TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Legend: Note 34 Description I/O (2) 19 Buffer Type RC6/IOCC6/TX/CK/AN18 RC6 26 Pin Type 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set.  2012-2014 Microchip Technology Inc. DS30000684B-page 21 PIC18(L)F2X/45K50 TABLE 1-3: PIC18(L)F45K50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type RE0 I/O ST/DIG Digital I/O. AN5 I Analog Analog input 5. RE1 I/O ST/DIG Digital I/O. AN6 I Analog Analog input 6. Pin Name PDIP TQFP UQFN 8 25 23 9 26 10 24 27 1 25 18 — 16 12 — — 13 — RE0/AN5 RE1/AN6 RE2/AN7 RE2 I/O ST AN7 I Analog RE3 I ST VPP P MCLR I ST Active-low Master Clear (device Reset) input. ICCK I/O ST Dedicated In-Circuit Debugger clock. ICPGC(3) I/O ST Dedicated ICSP™ programming clock. I/O ST Dedicated In-Circuit Debugger data. — I/O ST Dedicated ICSP™ programming data. Digital input. Programming voltage input. ICCK/ICPGC ICDT/ICPGD ICPGD 33 Digital I/O. Analog input 7. RE3/VPP/MCLR ICDT — Description (3) ICRST/ICVPP ICRST I ST ICVPP(3) I P Dedicated Master Clear Reset input. Dedicated programming voltage input. 11,32 7, 28 7, 26 VDD P — Positive supply for logic and I/O pins. 12,31 6, 29 6, 27 VSS P — Ground reference for logic and I/O pins. 34 Note NC TTL = TTL compatible input; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power. Legend: 1: Default pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are set. 2: Alternate pin assignment for SDO, T3CKI and CCP2 when Configuration bits SDOMX, T3CMX and CCP2MX are clear. 3: Pin is “No Connect”, except on PIC18(L)F45K50 TQFP devices with ICPRT Configuration bit set. DS30000684B-page 22  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 Getting started with the PIC18(L)F2X/45K50 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. C2(2) VDD R1 R2 MCLR These pins must also be connected if they are being used in the end application: • PGC/PGD pins used for In-Circuit Serial Programming (ICSP) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented (1) VUSB3V3 C1 C7(2) PIC18F2X/45K50 The following pins must always be connected: VSS VDD VDD VSS C3(2) C6(2) VDD • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VUSB3V3 pins (see Section 2.4 “Voltage Regulator Pins (VUSB3V3)”) RECOMMENDED MINIMUM CONNECTIONS VSS Basic Connection Requirements FIGURE 2-1: VSS 2.1 GUIDELINES FOR GETTING STARTED WITH PIC18(L)F2X/45K50 MICROCONTROLLERS VDD 2.0 C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: 2: See Section 2.4 “Voltage Regulator Pins (VUSB3V3)” for explanation of VUSB3V3 pin connections. The example shown is for a PIC18F device with five VDD/VSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The minimum mandatory connections are shown in Figure 2-1.  2012-2014 Microchip Technology Inc. DS30684A-page 23 PIC18(L)F2X/45K50 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD and VSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. DS30684A-page 24 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 JP MCLR PIC18F2X/45K50 C1 Note 1: R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 Voltage Regulator Pins (VUSB3V3) The on-chip voltage regulator must always be connected directly to either a supply voltage or to an external capacitor. When the regulator is enabled (F devices), a low-ESR capacitor is required on the VUSB3V3 pin to stabilize the voltage regulator output voltage. The VUSB3V3 pin must not be connected to VDD and is recommended to use a ceramic capacitor connected to ground. Refer to Section 29.0 “Electrical Specifications” for additional information. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 29.0 “Electrical Specifications” for additional information. When the regulator is disabled (LF devices), the VUSB3V3 pin should be externally tied to a voltage source maintained at the VDD level. Refer to Section 29.0 “Electrical Specifications” for information on VDD and VUSB3V3. • LF devices (with the name PIC18LF2X/45K50) permanently disable the voltage regulator. The VDD level of these devices must comply with the “voltage regulator disabled” specification for Parameter D001, in Section 29.0 “Electrical Specifications”. • F devices permanently enable the voltage regulator. These devices require an external capacitor on the VUSB3V3 pin. Refer to Section 29.0 “Electrical Specifications” for additional information. 2.4.1 CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller. However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: ±15% over a wide temperature range, but consult the manufacturer’s data sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 F nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum internal voltage regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with the internal regulator if the application must operate over a wide temperature range. In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very significant, but is often overlooked or is not always documented. A typical DC bias voltage vs. capacitance graph for X7R type and Y5V type capacitors is shown in Figure 2-3. FIGURE 2-3: Capacitance Change (%) 2.4 DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS 10 0 -10 16V Capacitor -20 -30 -40 10V Capacitor -50 -60 -70 6.3V Capacitor -80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) When selecting a ceramic capacitor to be used with the internal voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at 16V for the 3.3V VUSB3V3 voltage. Typical low-cost, ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial tolerance specifications for these types of capacitors are often specified as ±10% to ±20% (X5R and X7R), or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification.  2012-2014 Microchip Technology Inc. DS30684A-page 25 PIC18(L)F2X/45K50 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. Pull-up resistors, series diodes and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 28.0 “Development Support”. 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application’s routing and I/O assignments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” 2.7 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output to logic low. DS30684A-page 26  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 2-4: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 ` OSC2 GND C2 ` SOSCO SOSCI Timer1 Oscillator Crystal ` T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS  2012-2014 Microchip Technology Inc. DS30684A-page 27 PIC18(L)F2X/45K50 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 3.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of three internal oscillators, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. The primary clock module can be configured to provide one of six clock sources as the primary clock. 1. 2. 3. 4. 5. 6. RC LP XT INTOSC HS EC External Resistor/Capacitor Low-Power Crystal Crystal/Resonator Internal Oscillator High-Speed Crystal/Resonator External Clock The HS and EC oscillator circuits can be optimized for power consumption and oscillator speed using settings in FOSC. Additional FOSC selections enable RA6 to be used as I/O or CLKO (FOSC/4) for RC, EC and INTOSC Oscillator modes. Primary clock modes are selectable by the FOSC bits of the CONFIG1H Configuration register. The primary clock operation is further defined by these Configuration and register bits: 1. 2. 3. 4. 5. 6. PCLKEN (CONFIG1H) PRISD (OSCCON2) CFGPLLEN (CONFIG1L) PLLEN (OSCCON2) IRCF (OSCCON) INTSRC (OSCCON2) The HFINTOSC and INTRC are factory calibrated high and low-frequency oscillators, respectively, which are used as the internal clock sources. DS30000684B-page 28  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 3-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) SOSCO Secondary Oscillator (SOSC) SOSCI Low-Power Mode Event Switch (SCS) SOSCOUT 2 Primary Clock Module Secondary Oscillator PCLKEN PRISD PLL_Select EN IDLE (4) CPU FOSC Primary Oscillator(2) ( OSC) Primary Oscillator INTOSC 6 3x or 4xPLL 0 0 1 1 PLL Postscaler OSC1 01 3 2 1 11 Primary Clock 10 00 01 00 Clock Switch MUX OSC2 CPUDIV (3) Peripherals RA6 4 CLKO Enabled Modes INTOSC 1x Internal Oscillator IRCF INTSRC FSEN 3 3 1 HFINTOSC INTOSC Divide Circuit INTRC USB Module Clock Internal Oscillator MUX(3) (16 MHz) HF-16 MHZ HF-8 MHZ HF-4 MHZ HF-2 MHZ HF-1 MHZ HF-500 kHZ HF-250 kHZ HF-31.25 kHZ 8 1 0 4 INTOSC Needs 48 MHz for FS Needs 6 MHz for LS 0 LS48MHZ LF-31.25 kHz (31.25 kHz) Note 1: Details in Figure 3-3. 2: Details in Figure 3-2. 3: Details in Table 3-1. 4: The Primary Oscillator MUX uses the INTOSC branch when FOSC = 100x.  2012-2014 Microchip Technology Inc. DS30000684B-page 29 PIC18(L)F2X/45K50 3.2 Oscillator Control The OSCCON, OSCCON2 and OSCTUNE registers (Register 3-1 to Register 3-3) control several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. • • • • • • Main System Clock Selection (SCS) Primary Oscillator Circuit Shutdown (PRISD) Secondary Oscillator Enable (SOSCGO) Primary Clock Frequency multiplier (PLLEN) Internal Frequency selection bits (IRCF, INTSRC) Clock Status bits (OSTS, HFIOFS, LFIOFS, SOSCRUN, PLLRDY) • Power management selection (IDLEN) 3.2.1 MAIN SYSTEM CLOCK SELECTION The System Clock Select bits, SCS, select the main clock source. The available clock sources are: • Primary clock defined by the FOSC bits of CONFIG1H. The primary clock can be the primary oscillator, an external clock, or the internal oscillator block. • Secondary clock (secondary oscillator) • Internal oscillator block (HFINTOSC and INTRC). 3.2.3 LOW-FREQUENCY SELECTION When a nominal output frequency of 31.25 kHz is selected (IRCF = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit of the OSCCON2 register. See Figure 3-2 and Register 3-1 for specific 31.25 kHz selection. This option allows users to select a 31.25 kHz clock (based on HFINTOSC) that can be tuned using the TUN bits in the OSCTUNE register, while maintaining power savings with a very low clock speed. INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor, regardless of the setting of the INTSRC bit. This option allows users to select the tunable and more precise HFINTOSC as a clock source, while maintaining power savings with a very low clock speed. 3.2.4 POWER MANAGEMENT The IDLEN bit of the OSCCON register determines whether the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared to select the primary clock on all forms of Reset. 3.2.2 INTERNAL FREQUENCY SELECTION The Internal Oscillator Frequency Select bits (IRCF) select the frequency output of the internal oscillator block. The choices are the INTRC source (31.25 kHz) and the HFINTOSC source (16 MHz) or one of the frequencies derived from the HFINTOSC postscaler (31.25 kHz to 16 MHz). If the internal oscillator block is supplying the main clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the output frequency of the internal oscillator is set to the default frequency of 1 MHz. DS30000684B-page 30  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 3-2: INTERNAL OSCILLATOR MUX BLOCK DIAGRAM IRCF INTSRC 3 HF-16 MHz HF-8 MHz HF-4 MHz HF-2 MHz HF-1 MHz HF-500 kHz HF-250 kHz 111 110 101 100 011 010 001 INTOSC HF-31.25 kHz 1 LF-31.25 kHz TABLE 3-1: 31.25 kHz 000 0 PLL_SELECT TRUTH TABLE Primary Clock MUX Source External Clock (ECHIO/ECHCLKO) HS Crystal (HSH) FOSC CFGPLLEN 010x 0010 0 PLLEN 1 x x 3xPLL(1) 0 x x 4xPLL(2) 1 3xPLL(1) 0 4xPLL(2) 0 x OFF x x OFF x SPLLMULT PLL_Select 1 INTOSC (INTOSCIO, INTOSCCLKO) 100x FOSC (all other modes) xxxx Note 1: 2: 1 PLLSEL x x The input clock source must be 16 MHz when 3xPLL is used. The input clock source must be 8 MHz to 12 MHz when 4xPLL is used.  2012-2014 Microchip Technology Inc. DS30000684B-page 31 PIC18(L)F2X/45K50 FIGURE 3-3: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS SOSCGO T1CON T3CON SOSCEN To Clock Switch Module SOSCI EN SOSCOUT Secondary Oscillator SOSCO T1CKI T3G T3CKI 1 T1CLK_EXT_SRC SOSCEN 0 T1CON SOSCEN T3G SOSCEN 1 T3CLK_EXT_SRC 0 0 1 T3CKI T1G T3CON T3CMX T1G DS30000684B-page 32  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.3 Register Definitions: Oscillator Control REGISTER 3-1: R/W-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 IDLEN R/W-1 R/W-1 IRCF R-q R-0 OSTS(1) HFIOFS R/W-0 R/W-0 SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF: Internal RC Oscillator Frequency Select bits 111 = HFINTOSC – (16 MHz) 110 = HFINTOSC/2 – (8 MHz) 101 = HFINTOSC/4 – (4 MHz) 100 = HFINTOSC/8 – (2 MHz) 011 = HFINTOSC/16 – (1 MHz)(2) 010 = HFINTOSC/32 – (500 kHz) 001 = HFINTOSC/64 – (250 kHz) If INTSRC = 1: 000 = HFINTOSC/512 – (31.25 kHz) If INTSRC = 0: 000 = INTRC – (31.25 kHz) bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Device is running from the clock defined by FOSC of the CONFIG1H register 0 = Device is running from the internal oscillator (HFINTOSC or INTRC) bit 2 HFIOFS: HFINTOSC Frequency Stable bit 1 = HFINTOSC frequency is stable 0 = HFINTOSC frequency is not stable bit 1-0 SCS: System Clock Select bit 1x = Internal oscillator block 01 = Secondary (SOSC) oscillator 00 = Primary clock (determined by FOSC in CONFIG1H). Note 1: 2: Reset state depends on state of the IESO Configuration bit. Default output frequency of HFINTOSC on Reset.  2012-2014 Microchip Technology Inc. DS30000684B-page 33 PIC18(L)F2X/45K50 REGISTER 3-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0/0 R-0/q R/W-0 R/W-0/0 R/W-0/u R/W-1/1 R-0/0 R-0/0 PLLRDY SOSCRUN INTSRC PLLEN SOSCGO(1) PRISD HFIOFR LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = depends on condition -n/n = Value at POR and BOR/Value at all other Resets bit 7 PLLRDY: PLL Run Status bit 1 = System clock comes from PLL 0 = System clock comes from an oscillator, other than PLL bit 6 SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillator, other than SOSC bit 5 INTSRC: HFINTOSC Divided by 512 Enable bit 1 = HFINTOSC used as the 31.25 kHz system clock reference – high accuracy 0 = INTRC used as the 31.25 kHz system clock reference – low power. bit 4 PLLEN: Software PLL Enable bit If FOSC = 100x, 010x or 001x 1 = PLL enabled 0 = PLL disabled Else, No effect on PLL operation. bit 3 SOSCGO(1): Secondary Oscillator Start Control bit 1 = Secondary oscillator is enabled. 0 = Secondary oscillator is shut off if no other sources are requesting it. bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit 1 = Oscillator drive circuit on 0 = Oscillator drive circuit off (zero power) bit 1 HFIOFR: HFINTOSC Status bit 1 = HFINTOSC is running 0 = HFINTOSC is not running bit 0 LFIOFS: INTRC Frequency Stable bit 1 = INTRC is stable 0 = INTRC is not stable Note 1: The SOSCGO bit is only reset on a POR Reset. DS30000684B-page 34  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.4 Clock Source Modes Clock source modes can be classified as external or internal. External Clock Modes 3.5.1 OSCILLATOR START-UP TIMER (OST) When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-2. • External Clock modes rely on external circuitry for the clock source. Examples are: Clock modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and ResistorCapacitor (RC mode) circuits. • Internal clock sources are contained internally within the Oscillator block. The Oscillator block has two internal oscillators: the 16 MHz HighFrequency Internal Oscillator (HFINTOSC) and the 31.25 kHz Low-Frequency Internal Oscillator (INTRC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits of the OSCCON register. See Section 3.11 “Clock Switching” for additional information. TABLE 3-2: 3.5 In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 3.12 “Two-Speed Clock Start-up Mode”). OSCILLATOR DELAY EXAMPLES Switch From Switch To Frequency Oscillator Delay Sleep/POR INTRC HFINTOSC 31.25 kHz 31.25 kHz to 16 MHz Sleep/POR EC, RC DC – 48 MHz 2 instruction cycles INTRC (31.25 kHz) EC, RC DC – 48 MHz 1 cycle of each Oscillator Warm-Up Delay (TWARM) Sleep/POR LP, XT, HS 32 kHz to 25 MHz 1024 Clock Cycles (OST) Sleep/POR PLL 32 MHz to 48 MHz 1024 Clock Cycles (OST) + 2 ms INTRC HFINTOSC 31.25 kHz to 16 MHz INTRC (31.25 kHz) 3.5.2 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-4 shows the pin connections for EC mode. The External Clock (EC) offers different power modes, Low Power (ECL), Medium Power (ECM) and High Power (ECH), selectable by the FOSC bits. Each mode is best suited for a certain range of frequencies. The ranges are: 1 s (approx.) FIGURE 3-4: EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN Clock from Ext. System PIC® MCU I/O OSC2/CLKO • ECL – below 4 MHz • ECM – between 4 MHz and 16 MHz • ECH – above 16 MHz The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or Wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.  2012-2014 Microchip Technology Inc. DS30000684B-page 35 PIC18(L)F2X/45K50 3.5.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-5). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, refer to the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode offers a Medium Power (MP) and a High Power (HP) option selectable by the FOSC bits. The MP selections are best suited for oscillator frequencies between 4 and 16 MHz. The HP selection has the highest gain setting of the internal inverteramplifier and is best suited for frequencies above 16 MHz. HS mode is best suited for resonators that require a high drive setting. FIGURE 3-5: FIGURE 3-6: CERAMIC RESONATOR OPERATION (XT OR HS MODE) QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) PIC® MCU OSC1/CLKIN C1 To Internal Logic PIC® MCU RP(3) OSC1/CLKIN C1 Sleep To Internal Logic Quartz Crystal C2 RF(2) RS(1) RF(2) Sleep OSC2/CLKO Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. DS30000684B-page 36 C2 Ceramic RS(1) Resonator OSC2/CLKO Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.5.4 EXTERNAL RC MODES 3.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. 3.5.4.1 FIGURE 3-7: EXTERNAL RC MODES VDD PIC® MCU REXT OSC1/CLKIN Internal Clock CEXT VSS FOSC/4 or I/O(2) OSC2/CLKO(1) Recommended values: 10 k  REXT  100 k CEXT > 20 pF Note 1: 2: 3.5.4.2 The oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source. 1. RC Mode In RC mode, the RC circuit connects to OSC1. OSC2/ CLKO outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-7 shows the external RC mode connections. Alternate pin functions are listed in Section 1.0 “Device Overview”. Output depends upon RC or RCIO clock mode. RCIO Mode In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes a general purpose I/O pin. Internal Clock Modes 2. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 3-3). The INTRC (Low-Frequency Internal Oscillator) is factory calibrated and operates at 31.25 kHz. The INTRC cannot be user-adjusted, but is designed to be stable over temperature and voltage. The system clock speed can be selected via software using the Internal Oscillator Frequency select bits IRCF of the OSCCON register. The INTSRC bit allows users to select which internal oscillator provides the clock source for the 31.25 kHz frequency option. This is covered in greater detail in Section 3.2.3 “LowFrequency Selection”. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bits of the OSCCON register. See Section 3.11 “Clock Switching” for more information. 3.6.1 INTOSC WITH I/O OR CLOCKOUT Two of the clock modes selectable with the FOSC bits of the CONFIG1H Configuration register configure the internal oscillator block as the primary oscillator. Mode selection determines whether OSC2/CLKO/RA6 will be configured as general purpose I/O (RA6) or FOSC/4 (CLKO). In both modes, OSC1/CLKIN/RA6 is configured as general purpose I/O. See Section 26.0 “Special Features of the CPU” for more information. The CLKO signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • input threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.  2012-2014 Microchip Technology Inc. DS30000684B-page 37 PIC18(L)F2X/45K50 3.6.1.1 OSCTUNE Register The OSCTUNE register also implements the SPLLMULT bit, which controls whether 3x or 4xPLL clock multiplication is used when the PLL is enabled dynamically in software. For more details about the function of the SPLLMULT bit see Section 3.8.2 “PLL in HFINTOSC Modes”. The HFINTOSC oscillator circuits are factory calibrated but can be adjusted in software by writing to the TUN bits of the OSCTUNE register (Register 3-3). The default value of the TUN is ‘0’. The value is a 7-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The TUN bits in OSCTUNE do not affect the INTRC frequency. Operation of features that depend on the INTRC clock source frequency, such as the Powerup Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 3.7 Register Definitions: Oscillator Tuning REGISTER 3-3: R/W-0 OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 SPLLMULT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPLLMULT: Software PLL Multiplier Select bit If PLL Enabled, SPLLMULT changes are ignored. Else, Selects which PLL multiplier will be used: 1 = 3xPLL is selected 0 = 4xPLL is selected bit 6-0 TUN: Frequency Tuning bits – affects HFINTOSC(1) 0111111 = Maximum frequency 0111110 = ••• 0000001 = 0000000 = Center frequency. Oscillator module is running at the factory calibrated frequency. 1111111 = ••• 1000000 = Minimum frequency Note 1: The TUN bits may be supplied and controlled by the Active Clock Tuning module (see Section 3.15 “Active Clock Tuning (ACT) Module”) When the Active Clock Tuning is enabled, the TUN bits are read-only. DS30000684B-page 38  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.7.1 INTRC The Low-Frequency Internal Oscillator (INTRC) is a 31.25 kHz internal clock source. The INTRC is not tunable, but is designed to be stable across temperature and voltage. See Section 29.0 “Electrical Specifications” for the INTRC accuracy specifications. The output of the INTRC can be a clock source to the primary clock or the INTOSC clock (see Figure 3-1). The INTRC is also the clock source for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). 3.7.2 FREQUENCY SELECT BITS (IRCF) The HFINTOSC (16 MHz) outputs to a divide circuit that provides frequencies of 16 MHz to 31.25 kHz. These divide circuit frequencies, along with the 31.25 kHz INTRC output, are multiplexed to provide a single INTOSC clock output (see Figure 3-1). The IRCF bits of the OSCCON register and the INTSRC bit of the OSCCON2 register select the output frequency of the internal oscillators. One of eight frequencies can be selected via software: • • • • • • • • 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz (Default after Reset) 500 kHz 250 kHz 31 kHz (INTRC or HFINTOSC) 3.7.3 INTOSC FREQUENCY DRIFT The factory calibrates the internal oscillator block outputs (HFINTOSC) for 16 MHz. However, this frequency may drift as VDD or temperature changes. It is possible to automatically tune the HFINTOSC frequency using USB or secondary oscillator sources using the active clock tuning module (see Section 3.15 “Active Clock Tuning (ACT) Module”). The HFINTOSC frequency may be manually adjusted using the TUN bits in the OSCTUNE register. This has no effect on the INTRC clock source frequency. 3.7.3.1 Compensating with the EUSART An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. 3.7.3.2 Compensating with the Timers This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. 3.7.3.3 Compensating with the CCP Module in Capture Mode A CCP module can use free running Timer1 or Timer3 clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is much less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. Manually tuning the HFINTOSC source requires knowing when to make the adjustment, in which direction it should be made and, in some cases, how large a change is needed. Three possible compensation techniques are discussed in the following sections. However, other techniques may be used.  2012-2014 Microchip Technology Inc. DS30000684B-page 39 PIC18(L)F2X/45K50 3.8 PLL Frequency Multiplier A Phase-Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from the crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 3.8.1 PLL IN EXTERNAL OSCILLATOR MODES The PLL can be enabled for any of the external oscillator modes using the OSC1/OSC2 pins. Mediumpower and low-power oscillator mode selections in CONFIG1H (FOSC) should not be used with the PLL. The PLL can be enabled using the CFGPLLEN/ PLLSEL configuration bits in the CONFIG1L register, or by software using the PLLEN/SPLLMULT special function register bits in OSCCON2 and OSCTUNE, respectively. A selectable 3x or 4x frequency multiplier circuit is provided. This gives greater flexibility in source clock frequencies that can be used. Source clock frequencies between 8 and 12 MHz may use the 4x frequency multiplier to achieve operating speeds of 32 through 48 MHz. A source clock frequency of 16 MHz may use the 3x frequency multiplier to achieve 48 MHz operating speed. 3.8.2 PLL IN HFINTOSC MODES The PLL can be enabled using the HFINTOSC internal oscillator block. The frequency select bits (IRCF in the OSCCON register) should be configured for 16 MHz when using the HFINTOSC with 3x frequency multiplier. The IRCF bits should be configured for 8 MHz when using HFINTOSC with 4x frequency multiplier. DS30000684B-page 40 3.9 Effects of Power-Managed Modes on the Various Clock Sources For more information about the modes discussed in this section see Section 4.0 “Power-Managed Modes”. A quick reference list is also available in Table 4-1. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the secondary oscillator (SOSC) is operating and providing the device clock. The secondary oscillator may also run in all powermanaged modes if required to clock Timer1 or Timer3. In internal oscillator modes (INTOSC_RUN and INTOSC_IDLE), the internal oscillator block provides the device clock source. The 31.25 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 26.3 “Watchdog Timer (WDT)”, Section 3.12 “TwoSpeed Clock Start-up Mode” and Section 3.13 “FailSafe Clock Monitor” for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). The HFINTOSC output may be used directly to clock the device or may be divided down by the postscaler. The HFINTOSC output is disabled when the clock is provided directly from the INTRC output. When the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. Other features may be operating that do not require a device clock source (i.e., SSP slave, INTn pins and others). Peripherals that may add significant current consumption are listed in Table 29-8.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.10 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.7 “Device Reset Timers”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up. It is enabled by clearing (= 0) the PWRTEN Configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval TCSD, following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIOSC modes are used as the primary clock source. When the HFINTOSC is selected as the primary clock, the main system clock can be delayed until the HFINTOSC is stable. This is user selectable by the HFOFST bit of the CONFIG3H Configuration register. When the HFOFST bit is cleared, the main system clock is delayed until the HFINTOSC is stable. When the HFOFST bit is set, the main system clock starts immediately. In either case, the HFIOFS bit of the OSCCON register can be read to determine whether the HFINTOSC is operating and stable. When the PLL is enabled with external oscillator modes, the device runs off of the base external oscillator for 2 ms, following the OST delay, so the PLL can lock to the incoming clock frequency. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTOSC with CLKO Floating, external resistor should pull high At logic low (clock/4 output) RC with IO Floating, external resistor should pull high Configured as PORTA, bit 6 INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6 EC with IO Floating, pulled by external clock Configured as PORTA, bit 6 EC with CLKO Floating, pulled by external clock At logic low (clock/4 output) LP, XT, HS Feedback inverter disabled at quiescent voltage level Feedback inverter disabled at quiescent voltage level Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.  2012-2014 Microchip Technology Inc. DS30000684B-page 41 PIC18(L)F2X/45K50 3.11 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. PIC18(L)F2X/45K50 devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 “Entering Power-Managed Modes”. 3.11.1 • When SCS = 00, the system clock source is determined by configuration of the FOSC bits in the CONFIG1H Configuration register. • When SCS = 10, the system clock source is chosen by the internal oscillator frequency selected by the INTSRC bit of the OSCCON2 register and the IRCF bits of the OSCCON register. • When SCS = 01, the system clock source is the 32.768 kHz secondary oscillator shared with Timer1 and Timer3. After a Reset, the SCS bits of the OSCCON register are always cleared. 3.11.2 Any automatic clock switch, which may occur from Two-Speed Start-up or FailSafe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the SOSCRUN and LFIOFS bits of the OSCCON2 register, and the HFIOFS and OSTS bits of the OSCCON register to determine the current system clock source. CLOCK SWITCH TIMING When switching between one oscillator and another, the new oscillator may not be operating which saves power (see Figure 3-8). If this is the case, there is a delay after the SCS bits of the OSCCON register are modified before the frequency change takes place. The OSTS and HFIOFR, LFIOFS bits of the OSCCON and OSCCON2 registers will reflect the current active status of the external and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals. Note: 3.11.3 4. 5. 6. 7. SCS bits of the OSCCON register are modified. The old clock continues to operate until the new clock is ready. Clock switch circuitry waits for two consecutive rising edges of the old clock after the new clock ready signal goes true. The system clock is held low starting at the next falling edge of the old clock. Clock switch circuitry waits for an additional two rising edges of the new clock. On the next falling edge of the new clock the low hold on the system clock is released and new clock is switched in as the system clock. Clock switch is complete. See Figure 3-1 for more details. If the HFINTOSC is the source of both the old and new frequency, there is no start-up delay before the new frequency is active. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Start-up delay specifications are located in Section 29.0 “Electrical Specifications”, under AC Specifications (Oscillator Module). OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC bits in the CONFIG1H Configuration register, or from the internal clock source. In particular, when the primary oscillator is the source of the primary clock, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. DS30000684B-page 42  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.12 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the HFINTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. When the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.5.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator. 3.12.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is enabled when all of the following settings are configured as noted: • Two-Speed Start-up mode is enabled when the IESO of the CONFIG1H Configuration register is set. • SCS (of the OSCCON register) = 00. • FOSC bits of the CONFIG1H Configuration register are configured for LP, XT or HS mode. Two-Speed Start-up mode becomes active after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep.  2012-2014 Microchip Technology Inc. DS30000684B-page 43 PIC18(L)F2X/45K50 3.12.2 1. 2. 3. 4. 5. 6. TWO-SPEED START-UP SEQUENCE 3.12.3 Wake-up from Power-on Reset or Sleep. Instructions begin executing by the internal oscillator at the frequency set in the IRCF bits of the OSCCON register. OST enabled to count 1024 external clock cycles. OST timed out. External clock is ready. OSTS is set. Clock switch finishes according to Figure 3-8 FIGURE 3-8: High Speed CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC bits in CONFIG1H Configuration register, or the internal oscillator. OSTS = 0 when the external oscillator is not ready, which indicates that the system is running from the internal oscillator. CLOCK SWITCH TIMING Low Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF Select Old Select New System Clock Low Speed High Speed Old Clock Start-up Time(1) Clock Sync Running New Clock New Clk Ready IRCF Select Old Select New System Clock Note 1: Start-up time includes TOST (1024 TOSC) for external clocks, plus TPLL (approx. 2 ms) for HSPLL mode. DS30000684B-page 44  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.13 3.13.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the CONFIG1H Configuration register. The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO). FIGURE 3-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock S INTRC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) R 3.13.1 Both of these conditions restart the OST. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock source. The Fail-Safe condition need not be cleared before the OSCFIF flag is cleared. RESET OR WAKE-UP FROM SLEEP Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed. Note: When the device is configured for FailSafe clock monitoring in either HS, XT, or LS oscillator modes then the IESO configuration bit should also be set so that the clock will automatically switch from the internal clock to the external oscillator when the OST times out. Clock Failure Detected FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the INTRC by 64 (see Figure 3-9). Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low. 3.13.2 • Any Reset • By toggling the SCS1 bit of the OSCCON register The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. Q Sample Clock The Fail-Safe condition is cleared by either one of the following: 3.13.4 Q FAIL-SAFE CONDITION CLEARING FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSCFIF of the PIR2 register. The OSCFIF flag will generate an interrupt if the OSCFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. An automatic transition back to the failed clock source will not occur. The internal clock source chosen by the FSCM is determined by the IRCF bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.  2012-2014 Microchip Technology Inc. DS30000684B-page 45 PIC18(L)F2X/45K50 FIGURE 3-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: TABLE 3-4: Name INTCON IPR2 OSCCON Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 OSTS HFIOFS SCS 33 SOSCGO PRISD HFIOFR LFIOFS 34 IDLEN OSCCON2 PLLRDY OSCTUNE SPLLMULT IRCF SOSCRUN INTSRC PLLEN TUN 38 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by clock sources. TABLE 3-5: Name CONFIGURATION REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 Bit 4 CONFIG1H IESO FCMEN PCLKEN — CONFIG2L — LPBOR — Bit 3 BORV Bit 2 Bit 1 Bit 0 FOSC BOREN Register on page 373 PWRTEN 374 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for clock sources. DS30000684B-page 46  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.14 3.14.1 Oscillator Settings for USB When the PIC18(L)F2X/45K50 family devices are used for USB connectivity, a 6 MHz or 48 MHz clock must be provided to the USB module for operation in either Low-Speed or Full-Speed modes, respectively. This may require some forethought in selecting an oscillator frequency and programming the device. LOW-SPEED OPERATION The USB clock for Low-Speed mode is derived from the primary oscillator or from the PLL. In order to operate the USB module in Low-Speed mode, a 6 MHz clock must be provided to the USB module. See Table 3-6 and Table 3-7 for possible combinations which can be used for low-speed USB operation. The full range of possible oscillator configurations compatible with USB operation is shown in Table 3-7. TABLE 3-6: CLOCK FOR LOW-SPEED USB System Clock CPUDIV Microcontroller Clock LS48MHZ USB Clock 48 11 48/6 = 8 MHz 1 48/8 = 6 MHz 48 10 48/3 = 16 MHz 1 48/8 = 6 MHz 48 01 48/2 = 24 MHz 1 48/8 = 6 MHz 48 00 48 MHz 1 48/8 = 6 MHz 24 11 24/6 = 4 MHz 0 24/4 = 6 MHz 24 10 24/3 = 8 MHz 0 24/4 = 6 MHz 24 01 24/2 = 12 MHz 0 24/4 = 6 MHz 24 00 24 MHz 0 24/4 = 6 MHz TABLE 3-7: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator Frequency Clock Mode (FOSC) 48 MHz 16 MHz 12 MHz EC EC, HS or INTOSC with 3xPLL EC or HS with 4xPLL 24 MHz Note EC or HS(1) MCU Clock Division (CPUDIV) Microcontroller Clock Frequency 6 (11) 8 MHz 3 (10) 16 MHz 2 (01) 24 MHz None (00) 48 MHz 6 (11) 8 MHz 3 (10) 16 MHz 2 (01) 24 MHz None (00) 48 MHz 6 (11) 8 MHz 3 (10) 16 MHz 2 (01) 24 MHz None (00) 48 MHz 6 (11) 4 MHz 3 (10) 8 MHz 2 (01) 12 MHz None (00) 24 MHz 1: The 24 MHz mode (without PLL) is only compatible with low-speed USB. Full-speed USB requires a 48 MHz system clock.  2012-2014 Microchip Technology Inc. DS30000684B-page 47 PIC18(L)F2X/45K50 3.15 Active Clock Tuning (ACT) Module The Active Clock Tuning (ACT) module continuously adjusts the 16 MHz internal oscillator, using an available external reference, to achieve ± 0.20% accuracy. This eliminates the need for a high-speed, high-accuracy external crystal when the system has an available lower speed, lower power, high-accuracy clock source available. Systems implementing a Real-Time Clock Calendar (RTCC) or a full-speed USB application can take full advantage of the ACT module. 3.16 Active Clock Tuning Operation The ACT module defaults to the disabled state after any Reset. When the ACT module is disabled, the user can write to the TUN bits in the OSCTUNE register to manually adjust the 16 MHz internal oscillator. The module is enabled by setting the ACTEN bit of the ACTCON register. When enabled, the ACT module takes control of the OSCTUNE register. The ACT module uses the selected ACT reference clock to tune the 16 MHz internal oscillator to an accuracy of 16 MHz ± 0.2%. The tuning automatically adjusts the OSCTUNE register every reference clock cycle. Note 1: When the ACT module is enabled, the OSCTUNE register is only updated by the module. Writes to the OSCTUNE register by the user are inhibited, but reading the register is permitted. 2: After disabling the ACT module, the user should wait three instructions before writing to the OSCTUNE register. FIGURE 3-11: 3.17 Active Clock Tuning Source Selection The ACT reference clock is selected with the ACTSRC bit of the ACTCON register. The reference clock sources are provided by the: • USB module in full-speed operation (ACT_clk) • Secondary clock at 32.768 kHz (SOSC_clk) 3.18 ACT Lock Status The ACTLOCK bit will be set to ‘1’, when the 16 MHz internal oscillator is successfully tuned. The bit will be cleared by the following conditions: • Out of Lock condition • Device Reset • Module is disabled 3.19 ACT Out-of-Range Status If the ACT module requires an OSCTUNE value outside the range to achieve ± 0.20% accuracy, then the ACT Out-of-Range (ACTORS) Status bit will be set to ‘1’. An out-of-range status can occur: • When the 16 MHZ internal oscillator is tuned to its lowest frequency and the next ACT_clk event requests a lower frequency. • When the 16 MHZ internal oscillator is tuned to its highest frequency and the next ACT_clk event requests a higher frequency. When the ACT out-of-range event occurs, the 16 MHz internal oscillator will continue to use the last written OSCTUNE value. When the OSCTUNE value moves back within the tunable range and ACTLOCK is established, the ACTORS bit is cleared to ‘0’. ACTIVE CLOCK TUNING BLOCK DIAGRAM ACTEN ACTSRC FSUSB_clk SOSC_clk 1 0 ACT_clk Enable Active Clock Tuning Module 16 MHz Internal OSC ACT data 7 ACTUD ACTEN DS30000684B-page 48 sfr data 7 OSCTUNE Write OSCTUNE ACTEN  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 3.20 Active Clock Tuning Update Disable When the ACT module is enabled, the OSCTUNE register is continuously updated every ACT_clk period. Setting the ACT Update Disable bit can be used to suspend updates to the OSCTUNE register, without disabling the module. If the 16 MHz internal oscillator drifts out of the accuracy range, the ACT Status bits will change and an interrupt can be generated to notify the application. Clearing the ACTUD bit will engage the ACT updates to OSCTUNE and an interrupt can be generated to notify the application. 3.21 Interrupts The ACT module will set the ACT module Interrupt Flag, (ACTIF) when either of the ACT module Status bits (ACTLOCK or ACTORS) change state, regardless if the interrupt is enabled, (ACTIE = 1). The ACTIF and ACTIE bits are in the PIR1 and PIE1 registers, respectively. When ACTIE = 1, an interrupt will be generated whenever the ACT module Status bits change. The ACTIF bit must be cleared in software, regardless of the interrupt enable setting. 3.22 Operation during Sleep This ACT module does not run during Sleep and will not generate interrupts during Sleep.  2012-2014 Microchip Technology Inc. DS30000684B-page 49 PIC18(L)F2X/45K50 3.23 Register Definitions: Active Clock Tuning Control REGISTER 3-4: ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER R/W-0/0 R/W-0/0 U-0 R/W-0/0 R-0/0 U-0 R-0/0 U-0 ACTEN ACTUD — ACTSRC(1) ACTLOCK — ACTORS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTEN: Active Clock Tuning Selection bit 1 = ACT module is enabled, updates to OSCTUNE are exclusive to the ACT module. 0 = ACT module is disabled bit 6 ACTUD: Active Clock Tuning Update Disable bit 1 = Updates to the OSCTUNE register from ACT module are disabled. 0 = Updates to the OSCTUNE register from ACT module are enabled. bit 5 Unimplemented: Read as ‘0’ bit 4 ACTSRC: Active Clock Tuning Source Selection bit 1 = The HFINTOSC Oscillator is tuned to approximately match the USB host clock tolerance 0 = The HFINTOSC Oscillator is tuned to approximately match the 32.768 kHz SOSC tolerance bit 3 ACTLOCK: Active Clock Tuning Lock Status bit 1 = Locked; 16 MHz internal oscillator is within ± 0.20%.Locked 0 = Not locked; 16 MHz internal oscillator tuning has not stabilized within ± 0.20% bit 2 Unimplemented: Read as ‘0’ bit 1 ACTORS: Active Clock Tuning Out-of-Range Status bit 1 = Out-of-range; oscillator frequency is outside of the OSCTUNE range 0 = In-range; oscillator frequency is within the OSCTUNE range bit 0 Unimplemented: Read as ‘0’ Note 1: The ACTSRC bit should only be changed when ACTEN = 0. DS30000684B-page 50  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH ACT SOURCES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ACTCON ACTEN ACTUD — ACTSRC ACTLOCK — ACTORS — 50 OSCCON IDLEN OSTS HFIOFS OSCTUNE SPLLMULT OSCCON2 PLLRDY Name IRCF SCS TUN SOSCRUN INTSRC PLLEN SOSCGO 33 38 PRISD HFIOFR LFIOFS 34 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 SOSCEN T1SYNC RD16 TMR1ON 165 TMR1CS T1CON Legend: T1CKPS — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 3-9: Name CONFIG1H SUMMARY OF CONFIGURATION WORD WITH ACT SOURCES Bit 7 Bit 6 Bit 5 Bit 4 IESO FCMEN PCLKEN —  2012-2014 Microchip Technology Inc. Bit 3 Bit 2 Bit 1 FOSC Bit 0 Register on page 373 DS30000684B-page 51 PIC18(L)F2X/45K50 4.0 4.1.1 POWER-MANAGED MODES The SCS bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18(L)F2X/45K50 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). • the primary clock, as defined by the FOSC Configuration bits • the secondary clock (the SOSC oscillator) • the internal oscillator block There are three categories of power-managed modes: 4.1.2 • Run modes • Idle modes • Sleep mode ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. Refer to Section 3.11 “Clock Switching” for more information. These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block). The Sleep mode does not use a clock source. The power-managed modes include several powersaving features offered on previous PIC® microcontroller devices. One of the clock switching features allows the controller to use the secondary oscillator (SOSC) in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC microcontroller devices, where all device clocks are stopped. 4.1 CLOCK SOURCES Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: • Whether or not the CPU is to be clocked • The selection of a clock source The IDLEN bit (OSCCON) controls CPU clocking, while the SCS bits (OSCCON) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1. TABLE 4-1: POWER-MANAGED MODES OSCCON Bits Mode (1) IDLEN Module Clocking Available Clock and Oscillator Source SCS CPU Peripherals 0 N/A Off Off PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, RC, EC and Internal Oscillator Block(2). This is the normal full-power execution mode. SEC_RUN N/A 01 Clocked Clocked Secondary – SOSC Oscillator RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – SOSC Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2) Sleep Note 1: 2: None – All clocks are disabled IDLEN reflects its value when the SLEEP instruction is executed. Includes HFINTOSC and HFINTOSC postscaler, as well as the INTRC source. DS30000684B-page 52  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 4.1.3 MULTIPLE FUNCTIONS OF THE SLEEP COMMAND The power-managed mode that is invoked with the SLEEP instruction is determined by the value of the IDLEN bit at the time the instruction is executed. If IDLEN = 0, when SLEEP is executed, the device enters the sleep mode and all clocks stop and minimum power is consumed. If IDLEN = 1, when SLEEP is executed, the device enters the IDLE mode and the system clock continues to supply a clock to the peripherals but is disconnected from the CPU. 4.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 4.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset, unless Two-Speed Start-up is enabled (see Section 3.12 “Two-Speed Clock Start-up Mode” for details). In this mode, the device is operated off the oscillator defined by the FOSC bits of the CONFIG1H Configuration register. 4.2.2 SEC_RUN MODE In SEC_RUN mode, the CPU and peripherals are clocked from the secondary external oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS bits to ‘01’. When SEC_RUN mode is active, all of the following are true: • The device clock source is switched to the SOSC oscillator (see Figure 4-1) • The primary oscillator is shut down • The SOSCRUN bit (OSCCON2) is set • The OSTS bit (OSCCON) is cleared Figure 4-2). When the clock switch is complete, the SOSCRUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up and the SOSC oscillator continues to run. 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block – either INTRC or HFINTOSC – there are no distinguishable differences between the PRI_RUN and RC_RUN modes during execution. Entering or exiting RC_RUN mode, however, causes a clock switch delay. Therefore, if the primary clock source is the internal oscillator block, using RC_RUN mode is not recommended. This mode is entered by setting the SCS1 bit to ‘1’. To maintain software compatibility with future devices, it is recommended that the SCS0 bit also be cleared, even though the bit is ignored. When the clock source is switched to the INTOSC multiplexer (see Figure 4-1), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits (OSCCON) may be modified at any time to immediately change the clock speed. When the IRCF bits and the INTSRC bit are all clear, the INTOSC output (HFINTOSC) is not enabled and the HFIOFS bit will remain clear. There will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output) or if INTSRC is set, then the HFIOFS bit is set after the INTOSC output becomes stable. For details, see Table 4-2. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. Note: The secondary external oscillator should already be running prior to entering SEC_RUN mode. If the SOSCGO bit or any of the SOSCEN bits are not set when the SCS bits are set to ‘01’, entry to SEC_RUN mode will not occur until the SOSCGO bit is set and secondary external oscillator is ready. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, then the HFIOFS bit will remain set. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the SOSC oscillator, while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see  2012-2014 Microchip Technology Inc. DS30000684B-page 53 PIC18(L)F2X/45K50 On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-3). When the clock switch is complete, the HFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 SOSCI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 Note 1: Clock transition typically occurs within 2-4 TOSC. FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 SOSC OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter SCS bits Changed PC + 2 PC PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC. DS30000684B-page 54  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 4-2: INTERNAL OSCILLATOR FREQUENCY STABILITY BITS IRCF INTSRC Selected Oscillator Selected Oscillator Stable when: 000 0 INTRC LFIOFS = 1 000 1 HFINTOSC HFIOFS = 1 001-111 x HFINTOSC HFIOFS = 1 FIGURE 4-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC + 2 PC SCS bits Changed PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC.  2012-2014 Microchip Technology Inc. DS30000684B-page 55 PIC18(L)F2X/45K50 4.3 4.3.1 Sleep Mode The Power-Managed Sleep mode in the PIC18(L)F2X/ 45K50 devices is identical to the legacy Sleep mode offered in all other PIC microcontroller devices. It is entered by clearing the IDLEN bit of the OSCCON register and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-4) and all clock source status bits are cleared. Entering the Sleep mode from either Run or Idle mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the SOSC oscillator is enabled, it will also continue to run. VOLTAGE REGULATOR POWER MODE On F devices, an internal voltage regulator provides power to the internal core logic of the chip. During Sleep mode, the internal voltage regulator can be put into a lower-power mode, in exchange for longer wake-up time. Similarly, the internal band gap voltage reference may be turned off during Sleep for lowerpower consumption. See Register 4-1. On LF devices, the internal core logic operates from VDD and the internal voltage regulator is bypassed. The VREGCON register is, thus, not implemented on LF devices. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS bits becomes ready (see Figure 4-5), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 26.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. VREGCON – VOLTAGE REGULATOR POWER CONTROL REGISTER(1) REGISTER 4-1: U-0 U-0 U-0 U-0 U-0 R-0 — — — — — — R/W-0/0 R/W-0/0 VREGPM bit 7 bit 0 Legend: R = Readable bit W = Writable bit x = Bit is unknown -n/n = Value at POR and BOR/Value at all other resets ‘0’ = Bit is cleared ‘1’ = bit is set U = Unimplemented bit, read as ‘0’ bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 VREGPM: Voltage Regulator Power mode bits 11 = Band gap not forced in Sleep; LDO off in Sleep; ULP Regulator active 10 = Band gap forced in Sleep; LDO off in Sleep; ULP Regulator active 01 = LDO in Low-Power mode in Sleep, if no peripherals require High-Power mode. 00 = LDO in High-Power mode – always Note 1: 2: Reset state depends on state of the IESO Configuration bit. Default output frequency of HFINTOSC on Reset. DS30000684B-page 56  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 4.4 Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out, or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected by the SCS bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS bits. If the WDT is selected, the INTRC source will continue to operate. If the SOSC oscillator is enabled, it will also continue to run. FIGURE 4-4: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 4-5: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 PLL Clock Output TOST(1) TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event PC + 2 PC + 4 PC + 6 OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue  2012-2014 Microchip Technology Inc. to be clocked from the primary clock source specified by the FOSC Configuration bits. The OSTS bit remains set (see Figure 4-6). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-7). DS30000684B-page 57 PIC18(L)F2X/45K50 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the SOSC oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS bits to ‘01’ and execute SLEEP. When the clock source is switched to the SOSC oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the SOSCRUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the SOSC oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the SOSC oscillator. The IDLEN and SCS bits are not affected by the wake-up; the SOSC oscillator continues to run (see Figure 4-7). Note: The SOSC oscillator should already be running prior to entering SEC_IDLE mode. At least one of the secondary oscillator enable bits (SOSCEN, T1CON or T3CON) must be set when the SLEEP instruction is executed. Otherwise, the main system clock will continue to operate in the previously selected mode and the corresponding IDLE mode will be entered (i.e., PRI_IDLE or RC_IDLE). FIGURE 4-6: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q3 Q2 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 4-7: PC + 2 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS30000684B-page 58  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block from the HFINTOSC multiplexer output. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. It is recommended that SCS0 also be cleared, although its value is ignored, to maintain software compatibility with future devices. The HFINTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the HFINTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC bits are set, the HFINTOSC output is enabled. The HFIOFS bit becomes set after the HFINTOSC output stabilizes after an interval of TIOBST. For information on the HFIOFS bit, see Table 4-2. Clocks to the peripherals continue while the HFINTOSC source stabilizes. The HFIOFS bit will remain set if the IRCF bits were previously set at a nonzero value or if INTSRC was set before the SLEEP instruction was executed and the HFINTOSC source was already stable. If the IRCF bits and INTSRC are all clear, the HFINTOSC output will not be enabled, the HFIOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the HFINTOSC multiplexer output. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the HFINTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 4.5 Exiting Idle and Sleep Modes An exit from Sleep mode or any of the Idle modes is triggered by any one of the following: • an interrupt • a Reset • a Watchdog Time-out This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 4.2 “Run Modes”, Section 4.3 “Sleep Mode” and Section 4.4 “Idle Modes”). 4.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. The instruction immediately following the SLEEP instruction is executed on all exits by interrupt from Idle or Sleep modes. Code execution then branches to the interrupt vector if the GIE/GIEH bit of the INTCON register is set, otherwise code execution continues without branching (see Section 10.0 “Interrupts”). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 “Run Modes” and Section 4.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 26.3 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by any one of the following: • executing a SLEEP instruction • executing a CLRWDT instruction • the loss of the currently selected clock source when the Fail-Safe Clock Monitor is enabled • modifying the IRCF bits in the OSCCON register when the internal oscillator block is the device clock source  2012-2014 Microchip Technology Inc. DS30000684B-page 59 PIC18(L)F2X/45K50 4.5.3 EXIT BY RESET Exiting Sleep and Idle modes by Reset causes code execution to restart at address 0. See Section 5.0 “Reset” for more details. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped and • the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC, INTOSC, and INTOSCIO modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. DS30000684B-page 60 4.6 Selective Peripheral Module Control Idle mode allows users to substantially reduce power consumption by stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what IDLE mode does not provide: the allocation of power resources to the CPU processing with minimal power consumption from the peripherals. PIC18(L)F2X/45K50 family devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with control bits in the Peripheral Module Disable (PMD) registers. These bits generically named XXXMD are located in control registers PMD0 or PMD1. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, power to the control and status registers associated with the peripheral is removed. Writes to these registers have no effect and read values are invalid. Clearing a set PMD bit restores power to the associated control and status registers, thereby setting those registers to their default values.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 4.7 Register Definitions: Peripheral Module Disable REGISTER 4-2: PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’. bit 6 UARTMD: UART Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 5 USBMD: USB Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 4 ACTMD: Active Clock Tuning Peripheral Module Disable Control bit 1 = Module is disabled and does not draw any digital power 0 = Module is enabled and available for use; will draw digital power bit 3 Unimplemented: Read as ‘0’. bit 2 TMR3MD: Timer3 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 1 TMR2MD: Timer2 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 0 TMR1MD: Timer1 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power  2012-2014 Microchip Technology Inc. DS30000684B-page 61 PIC18(L)F2X/45K50 REGISTER 4-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 MSSPMD: MSSP Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 5 CTMUMD: CTMU Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 4 CMP2MD: Comparator 2 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 3 CMP1MD: Comparator 1 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 2 ADCMD: Analog-to-Digital Converter Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 1 CCP2MD: CCP2 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power bit 0 CCP1MD: CCP1 Peripheral Module Disable Control bit 1 = Module is disabled, clock source is disconnected, module does not draw digital power 0 = Module is enabled, clock source is connected, module draws digital power DS30000684B-page 62  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 5.0 RESET The PIC18(L)F2X/45K50 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 6.2.1 “Stack Full and Underflow Resets”. WDT Resets are covered in Section 26.3 “Watchdog Timer (WDT)”. FIGURE 5-1: A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.8 “Reset State of Registers”. The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 10.0 “Interrupts”. BOR is covered in Section 5.5 “Brown-out Reset (BOR)”. SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Full/Underflow Reset Stack Pointer External Reset MCLRE MCLR Idle Sleep WDT Time-out VDD Detect POR VDD Brown-out Reset BOREN S OST/PWRT OST(2) 1024 Cycles 10-bit Ripple Counter OSC1 32 s INTRC Chip_Reset R Q PWRT(2) 65.5 ms 11-bit Ripple Counter Enable PWRT Enable OST(1) Note 1: 2: See Table 5-2 for time-out situations. PWRT and OST counters are reset by POR and BOR. See Sections 5.4 and 5.5.  2012-2014 Microchip Technology Inc. DS30000684B-page 63 PIC18(L)F2X/45K50 5.2 Register Definitions: Reset Control REGISTER 5-1: R/W-0/0 IPEN RCON: RESET CONTROL REGISTER R/W-q/u SBOREN (1) U-0 R/W-1/q — RI R-1/q R-1/q TO PD R/W-q/u (2) POR bit 7 R/W-0/q BOR bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets x = Bit is unknown u = unchanged q = depends on condition bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Software Enable bit(1) If BOREN = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN = 00, 10 or 11: Bit is disabled and read as ‘0’. bit 5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware or Power-on Reset) 0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a code-executed Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit(2) 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit(3) 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set by firmware after a POR or Brown-out Reset occurs) Note 1: 2: 3: When CONFIG2L[2:1] = 01, then the SBOREN Reset state is ‘1’; otherwise, it is ‘0’. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 5.8 “Reset State of Registers” for additional information. See Table 5-1. Note 1: Brown-out Reset is indicated when BOR is ‘0’ and POR is ‘1’ (assuming that both POR and BOR were set to ‘1’ by firmware immediately after POR). 2: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. DS30000684B-page 64  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 5.3 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. An internal weak pull-up is enabled when the pin is configured as the MCLR input. FIGURE 5-2: In PIC18(L)F2X/45K50 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 11.6 “PORTE Registers” for more information. 5.4 D To take advantage of the POR circuitry either leave the pin floating, or tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified. For a slow rise time, see Figure 5-2. PIC® MCU R R1 MCLR C Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: 15 k < R < 40 k is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1  1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Power-on Reset (POR) A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. VDD VDD The MCLR pin is not driven low by any internal Resets, including the WDT. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit of the RCON register. The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user must manually set the bit to ‘1’ by software following any POR.  2012-2014 Microchip Technology Inc. DS30000684B-page 65 PIC18(L)F2X/45K50 5.5 Brown-out Reset (BOR) PIC18(L)F2X/45K50 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV and BOREN bits of the CONFIG2L Configuration register. There are a total of four BOR configurations which are summarized in Table 5-1. The BOR threshold is set by the BORV bits. If BOR is enabled (any values of BOREN, except ‘00’), any drop of VDD below VBOR for greater than TBOR will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling BOR Reset does not automatically enable the PWRT. The BOR circuit has an output that feeds into the POR circuit and rearms the POR within the operating range of the BOR. This early rearming of the POR ensures that the device will remain in Reset in the event that VDD falls below the operating range of the BOR circuitry. 5.5.1 DETECTING BOR When BOR is enabled, the BOR bit always resets to ‘0’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘1’ by software immediately after any POR event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a BOR event has occurred. DS30000684B-page 66 5.5.2 SOFTWARE ENABLED BOR When BOREN = 01, the BOR can be enabled or disabled by the user in software. This is done with the SBOREN control bit of the RCON register. Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as ‘0’. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to the environment without having to reprogram the device to change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: 5.5.3 Even when BOR is under software control, the BOR Reset voltage level is still set by the BORV Configuration bits. It cannot be changed by software. DISABLING BOR IN SLEEP MODE When BOREN = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current. 5.5.4 MINIMUM BOR ENABLE TIME Enabling the BOR also enables the Fixed Voltage Reference (FVR) when no other peripheral requiring the FVR is active. The BOR becomes active only after the FVR stabilizes. Therefore, to ensure BOR protection, the FVR settling time must be considered when enabling the BOR in software or when the BOR is automatically enabled after waking from Sleep. If the BOR is disabled, in software or by reentering Sleep before the FVR stabilizes, the BOR circuit will not sense a BOR condition. The FVRST bit of the VREFCON0 register can be used to determine FVR stability.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 5-1: BOR CONFIGURATIONS BOR Configuration Status of SBOREN (RCON) BOR Operation BOREN1 BOREN0 0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits. 0 1 Available BOR enabled by software; operation controlled by SBOREN. 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits. 5.6 Low-Power BOR (LPBOR) PIC18(L)F2X/45K50 devices implement a low-power Brown-out Reset circuit (LPBOR). The LPBOR is used to monitor the external VDD pin. When low voltage is detected, the device is held in Reset. When this occurs, the RCON (BOR) bit is changed to indicate that a BOR reset has occurred. This is the same bit in the RCON register that is set for the traditional BOR. LPBOR provides the user with a lower power BOR option. In exchange for the lower power, the LPBOR circuit trips at a loose voltage range compared to the traditional BOR voltage trip point options. LPBOR is enabled by the Configuration bit CONFIG2L (LPBOR). The threshold of the LPBOR is not configurable and its range is specified as parameter D006. 5.7 Device Reset Timers PIC18(L)F2X/45K50 devices incorporate three separate on-chip timers that help regulate the Poweron Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 5.7.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18(L)F2X/45K50 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. 5.7.2 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset, or on exit from all power-managed modes that stop the external oscillator. 5.7.3 PLL LOCK TIME-OUT With the PLL enabled, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed timeout that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 5.7.4 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: 1. 2. After the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 5-3 through 5-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, on the other hand, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire, after which, bringing MCLR high will allow program execution to begin immediately (Figure 5-5). This is useful for testing purposes or to synchronize more than one PIC MCU device operating in parallel. The PWRT is enabled by clearing the PWRTEN Configuration bit.  2012-2014 Microchip Technology Inc. DS30000684B-page 67 PIC18(L)F2X/45K50 TABLE 5-2: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration HSPLL PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 66 ms (1) (2) + 1024 TOSC + 2 ms 66 ms(1) + 1024 TOSC HS, XT, LP 1024 TOSC 1024 TOSC (1) — — RC, RCIO 66 ms(1) — — INTOSC, INTOSCIO 66 ms(1) — — EC, ECIO 66 ms Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2: 2 ms is the nominal time required for the PLL to lock. FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30000684B-page 68  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2012-2014 Microchip Technology Inc. DS30000684B-page 69 PIC18(L)F2X/45K50 FIGURE 5-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL  2 ms max. First three stages of the PWRT timer. DS30000684B-page 70  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 5.8 Table 6-2 describes the Reset states for all of the Special Function Registers. The table identifies differences between Power-On Reset (POR)/BrownOut Reset (BOR) and all other Resets, (i.e., Master Clear, WDT Resets, STKFUL, STKUNF, etc.). Additionally, the table identifies register bits that are changed when the device receives a wake-up from WDT or other interrupts. Reset State of Registers Some registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 5-3. These bits are used by software to determine the nature of the Reset. TABLE 5-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter Condition RCON Register SBOREN RI TO PD STKPTR Register POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u(2) 0 u u u u u u 0000h u(2) 1 1 1 u 0 u u MCLR during Power-Managed Run Modes 0000h u(2) u 1 u u u u u MCLR during Power-Managed Idle Modes and Sleep Mode 0000h u(2) u 1 0 u u u u WDT Time-out during Full Power or Power-Managed Run Mode 0000h u(2) u 0 u u u u u MCLR during Full Power Execution 0000h u(2) u u u u u u u Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h (2) u u u u u u u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u(2) u u u u u u 1 WDT Time-out during PowerManaged Idle or Sleep Modes PC + 2 u(2) u 0 0 u u u u PC + 2(1) u(2) u u 0 u u u u Brown-out Reset Interrupt Exit from PowerManaged Modes Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is ‘1’ for SBOREN and unchanged for all other Resets when software BOR is enabled (BOREN Configuration bits = 01). Otherwise, the Reset state is ‘0’. TABLE 5-4: Name RCON STKPTR REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 IPEN SBOREN — RI TO STKFUL STKUNF — Bit 2 Bit 1 Bit 0 PD POR BOR STKPTR Register on page 64 76 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.  2012-2014 Microchip Technology Inc. DS30000684B-page 71 PIC18(L)F2X/45K50 TABLE 5-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 CONFIG2L — — LPBOR — — CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 CONFIG4L DEBUG XINST ICPRT — — LVP — STRVEN 377 CONFIG2H Bit 4 Bit 3 BORV WDTPS Bit 2 Bit 1 Bit 0 Register on page Name BOREN PWRTEN WDTEN 374 375 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets. DS30000684B-page 72  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 6.0 MEMORY ORGANIZATION 6.1 PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate buses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. This family of devices contain the following: • PIC18(L)F24K50: 16 Kbytes of Flash memory, up to 8,192 single-word instructions • PIC18(L)F25K50, PIC18(L)F45K50: 32 Kbytes of Flash memory, up to 16,384 single-word instructions Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 “Flash Program Memory”. Data EEPROM is discussed separately in Section 8.0 “Data EEPROM Memory”. FIGURE 6-1: Program Memory Organization PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory map for PIC18(L)F2X/45K50 devices is shown in Figure 6-1. Memory block details are shown in Figure 21-2. PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/45K50 DEVICES PC 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1    Stack Level 31 Reset Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory On-Chip Program Memory User Memory Space 3FFFh 4000h PIC18(L)F24K50 7FFFh 8000h PIC18(L)F25K50 PIC18(L)F45K50 Read ‘0’ Read ‘0’ 1FFFFFh 200000h  2012-2014 Microchip Technology Inc. DS30000684B-page 73 PIC18(L)F2X/45K50 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 6.2.3.1 “Computed GOTO”). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 6.1.2 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-2: The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack (TOS) Special File Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full or has overflowed or has underflowed. 6.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 6-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent inadvertent stack corruption. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah DS30000684B-page 74 STKPTR 00010 TOSL 34h Top-of-Stack Stack Pointer 001A34h 000D58h 00011 00010 00001 00000  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 6.1.2.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (stack full) Status bit and the STKUNF (Stack Underflow) Status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 26.1 “Configuration Bits” for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.  2012-2014 Microchip Technology Inc. DS30000684B-page 75 PIC18(L)F2X/45K50 6.1.2.3 PUSH and POP Instructions The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. 6.2 The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. Register Definitions: Stack Pointer REGISTER 6-1: R/C-0 STKPTR: STACK POINTER REGISTER R/C-0 (1) STKFUL STKUNF U-0 (1) R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 STKPTR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack Underflow occurred 0 = Stack Underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 STKPTR: Stack Pointer Location bits Note 1: 6.2.1 Bit 7 and bit 6 are cleared by user software or by a POR. STACK FULL AND UNDERFLOW RESETS Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a Power-on Reset. 6.2.2 FAST REGISTER STACK A fast register stack is provided for the Status, WREG and BSR registers, to provide a “fast return” option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. DS30000684B-page 76 If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers by software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. Example 6-1 shows a source code example that uses the fast register stack during a subroutine call and return.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 EXAMPLE 6-1: FAST REGISTER STACK CODE EXAMPLE CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK     RETURN, FAST SUB1 6.2.3 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK LOOK-UP TABLES IN PROGRAM MEMORY 6.2.3.2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 “Table Reads and Table Writes”. There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 6.2.3.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value ‘nn’ to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 6-2: ORG TABLE MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh  2012-2014 Microchip Technology Inc. DS30000684B-page 77 PIC18(L)F2X/45K50 6.3 6.3.2 PIC18 Instruction Cycle 6.3.1 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3). CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 6-3. FIGURE 6-3: INSTRUCTION FLOW/PIPELINING A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC – 2) Fetch INST (PC) EXAMPLE 6-3: 1. MOVLW 55h 4. BSF Execute INST (PC + 2) Fetch INST (PC + 4) INSTRUCTION PIPELINE FLOW TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 3. BRA Execute INST (PC) Fetch INST (PC + 2) SUB_1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30000684B-page 78  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 6.3.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSb will always read ‘0’ (see Section 6.1.1 “Program Counter”). Figure 6-4 shows an example of how instruction words are stored in the program memory. FIGURE 6-4: The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC, which accesses the desired byte address in program memory. Instruction #2 in Figure 6-4 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 27.0 “Instruction Set Summary” provides further details of the instruction set. INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations  6.3.4 Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instruction always has ‘1111’ as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the four MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence – immediately after the first word – the data in the second word is accessed EXAMPLE 6-4: Word Address  000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 shows how this works. Note: See Section 6.8 “PIC18 Instruction Execution and the Extended Instruction Set” for information on two-word instructions in the extended instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000  2012-2014 Microchip Technology Inc. DS30000684B-page 79 PIC18(L)F2X/45K50 6.4 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.7 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. Figures 6-5 through 6-7 show the data memory organization for the PIC18(L)F2X/45K50 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). Section 6.4.3 “Access Bank” provides a detailed description of the Access RAM. 6.4.1 USB RAM Banks 4 through 7 of the data memory are actually mapped to special dual port RAM. When the USB module is disabled, the GPRs in these banks are used like any other GPR in the data memory space. When the USB module is enabled, the memory in these banks is allocated as buffer RAM for USB operation. This area is shared between the microcontroller core and the USB Serial Interface Engine (SIE) and is used to transfer data directly between the two. It is theoretically possible to use the areas of USB RAM that are not allocated as USB buffers for normal scratchpad memory or other variable storage. In practice, the dynamic nature of buffer allocation makes this risky, at best. Additionally, Bank 4 is used for USB buffer descriptor tables when the module is enabled and should not be used for any other purposes during that time. Additional information on USB RAM and buffer operation is provided in Section 24.0 “Universal Serial Bus (USB)”. DS30000684B-page 80 6.4.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the four Most Significant bits of a location’s address; the instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are implemented (BSR). The upper four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is shown in Figures 6-5 through 6-7. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in Figures 6-5 through 6-7 indicate which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 6-5: DATA MEMORY MAP FOR PIC18(L)F2X/45K50 DEVICES BSR = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 The second 160 bytes are Special Function Registers (from Bank 15). 1FFh 200h FFh 00h GPR FFh 00h 2FFh 300h When ‘a’ = 1: The BSR specifies the Bank used by the instruction. GPR 3FFh 400h FFh 00h GPR(2) 4FFh 500h FFh 00h GPR(2) 5FFh 600h FFh 00h GPR(2) FFh 00h Access Bank 6FFh 700h Access RAM Low GPR(2) FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh Bank 13 00h Bank 14 The first 96 bytes are general purpose RAM (from Bank 0). GPR Bank 1 Bank 2 The BSR is ignored and the Access Bank is used. 000h 05Fh 060h 0FFh 100h FFh 00h FFh 00h Bank 15 Unimplemented. Read as 00h. Unimplemented. Read as 00h. Unimplemented. Read as 00h. Unimplemented. Read as 00h. Unimplemented. Read as 00h. Unimplemented. Read as 00h. Unimplemented. Read as 00h. Unimplemented SFR(1) 7FFh 800h 8FFh 900h 9FFh A00h AFFh B00h BFFh C00h CFFh D00h DFFh E00h  2012-2014 Microchip Technology Inc. Note 1: Addresses F53h through F5Fh are also used by SFRs, but are not part of the Access RAM. Users must always use the complete address or load the proper BSR value to access these registers. 2: These banks also serve as RAM buffer for USB operation. See Section 6.4.1 “USB RAM” for more information. F00h F52h F53h F5Fh F60h SFR FFh 00h 5Fh Access RAM High 60h (SFRs) FFh FFFh DS30000684B-page 81 PIC18(L)F2X/45K50 FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 Bank Select(2) 0 0 0 1 1 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. DS30000684B-page 82  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 6.4.3 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Block 15. The lower half is known as the “Access RAM” and is composed of GPRs. This upper half is also where the device’s SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figures 6-5 through 6-7). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 6.4.4 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 6.4.5 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top portion of Bank 15 (F53h to FFFh). A list of these registers is given in Table 6-1 and Table 6-2. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 6.7.3 “Mapping the Access Bank in Indexed Literal Offset Mode”.  2012-2014 Microchip Technology Inc. DS30000684B-page 83 PIC18(L)F2X/45K50 TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/45K50 DEVICES Address Name Address Name Address FFFh TOSU FD7h TMR0H FAFh FFEh TOSH FD6h TMR0L FFDh TOSL FD5h FFCh STKPTR FD4h Name Address Name Address Name SPBRG1 F87h IOCC F5Fh ANSELE(3) FAEh RCREG1 F86h IOCB F5Eh ANSELD(3) T0CON FADh TXREG1 F85h WPUB F5Dh ANSELC —(2) FACh TXSTA1 F84h PORTE F5Ch ANSELB F5Bh ANSELA F5Ah VREGCON(4) FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h PORTD(3) FFAh PCLATH FD2h OSCCON2 FAAh — F82h PORTC FF9h PCL FD1h WDTCON FA9h EEADR F81h PORTB F59h CCPTMRS FF8h TBLPTRU FD0h RCON FA8h EEDATA F80h PORTA F58h SRCON0 (1) FF7h TBLPTRH FCFh TMR1H FA7h F7Fh PMD1 F57h SRCON1 FF6h TBLPTRL FCEh TMR1L FA6h EECON1 F7Eh PMD0 F56h — FF5h TABLAT FCDh T1CON FA5h IPR3 F7Dh VREFCON0 F55h — FF4h PRODH FCCh T1GCON FA4h PIR3 F7Ch VREFCON1 F54h — FF3h PRODL FCBh SSP1CON3 FA3h PIE3 F7Bh VREFCON2 F53h — FF2h INTCON FCAh SSP1MSK FA2h IPR2 F7Ah SLRCON F52h FF1h INTCON2 FC9h SSP1BUF FA1h PIR2 F79h UEP15 F51h FF0h INTCON3 FC8h SSP1ADD FA0h PIE2 F78h UEP14 F50h FEFh INDF0(1) FC7h SSP1STAT F9Fh IPR1 F77h UEP13 F4Fh FEEh POSTINC0(1) FC6h SSP1CON1 F9Eh PIR1 F76h UEP12 F4Eh FEDh POSTDEC0(1) EECON2 FC5h SSP1CON2 F9Dh PIE1 F75h UEP11 F4Dh FECh PREINC0(1) FC4h F9Ch HLVDCON F74h UEP10 F4Ch FEBh PLUSW0 (1) FC3h ADRESL F9Bh OSCTUNE F73h UEP9 F4Bh FEAh FSR0H FC2h ADCON0 F9Ah CM2CON1 F72h UEP8 F4Ah FE9h FSR0L FC1h ADCON1 F99h CM2CON0 F71h UEP7 F49h FE8h WREG FC0h ADCON2 F98h CM1CON0 F70h UEP6 F48h F47h (1) ADRESH FBFh CCPR1H F97h CCP2CON F6Fh UEP5 FE6h POSTINC1(1) FBEh CCPR1L F96h TRISE(3) F6Eh UEP4 General F46h Purpose RAM FE5h POSTDEC1(1) FBDh CCP1CON F95h TRISD(3) F6Dh UEP3 F45h FBCh TMR2 F94h TRISC F6Ch UEP2 F44h FE7h INDF1 FE4h PREINC1(1) FE3h PLUSW1(1) FBBh PR2 F93h TRISB F6Bh UEP1 F43h FE2h FSR1H FBAh T2CON F92h TRISA F6Ah UEP0 F42h FE1h FSR1L FB9h PSTR1CON F91h CCPR2H F69h UFRMH F41h FE0h BSR FB8h BAUDCON1 F90h CCPR2L F68h UFRML F40h FDFh INDF2(1) FB7h PWM1CON F8Fh CTMUCONH F67h UEIR F3Fh FDEh POSTINC2(1) FB6h ECCP1AS F8Eh CTMUCONL F66h UEIE F3Eh FDDh POSTDEC2(1) FB5h STCON F8Dh LATE(3) F65h UIR F3Dh FB4h T3GCON F8Ch LATD(3) F64h UIE F3Ch FDCh PREINC2(1) (1) FDBh PLUSW2 FB3h TMR3H F8Bh LATC F63h UADDR F3Bh FDAh FSR2H FB2h TMR3L F8Ah LATB F62h UCNFG F3Ah FD9h FSR2L FB1h T3CON F89h LATA F61h USTAT F39h FD8h STATUS FB0h SPBRGH1 F60h UCTRL F38h Note 1: 2: 3: 4: F88h CTMUICONH This is not a physical register. Unimplemented registers are read as ‘0’. PIC18(L)F45K50 device only. F devices only. DS30000684B-page 84  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES Name Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack, Upper Byte (TOS) Value on POR, BOR FFFh TOSU FFEh TOSH Top-of-Stack, High Byte (TOS) FFDh TOSL Top-of-Stack, Low Byte (TOS) FFCh STKPTR STKFUL STKUNF — STKPTR 00-0 0000 FFBh PCLATU — — — Holding Register for PC ---0 0000 FFAh PCLATH Holding Register for PC FF9h PCL Holding Register for PC FF8h TBLPTRU FF7h TBLPTRH Program Memory Table Pointer High Byte (TBLPTR) 0000 0000 FF6h TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR) 0000 0000 FF5h TABLAT Program Memory Table Latch 0000 0000 FF4h PRODH Product Register, High Byte xxxx xxxx FF3h PRODL Product Register, Low Byte FF2h INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF FF1h INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 1111 -1-1 FF0h INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 — ---0 0000 0000 0000 0000 0000 0000 0000 0000 0000 — Program Memory Table Pointer Upper Byte (TBLPTR) --00 0000 xxxx xxxx 0000 000x FEFh INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) ---- ---- FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) ---- ---- FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) ---- ---- FECh PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) ---- ---- FEBh PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W ---- ---- FEAh FSR0H FE9h FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx FE8h WREG Working Register xxxx xxxx FE7h INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) ---- ---- FE6h POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE5h POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) ---- ---- FE4h PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) ---- ---- FE3h PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W ---- ---- FE2h FSR1H FE1h FSR1L FE0h BSR FDFh INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) ---- ---- FDEh POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) ---- ---- FDDh POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) ---- ---- FDCh PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) ---- ---- FDBh PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W ---- ---- FDAh FSR2H FD9h FSR2L FD8h STATUS FD7h TMR0H Timer0 Register, High Byte FD6h TMR0L Timer0 Register, Low Byte FD5h T0CON FD3h OSCCON IDLEN FD2h OSCCON2 PLLRDY FD1h WDTCON FD0h RCON Legend: Note 1: 2: — — — — — — — — Indirect Data Memory Address Pointer 0, High Byte Indirect Data Memory Address Pointer 1, High Byte Indirect Data Memory Address Pointer 1, Low Byte — — — — — — Bank Select Register ---- 0000 Indirect Data Memory Address Pointer 2, High Byte Indirect Data Memory Address Pointer 2, Low Byte — TMR0ON — T08BIT — N ---- 0000 xxxx xxxx OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS T0SE IRCF SOSCRUN ---- 0000 xxxx xxxx — — ---- 0000 INTSRC PLLEN PSA T0PS OSTS HFIOFS SOSCGO PRISD 1111 1111 SCS HFIOFR LFIOFS 0011 q000 0000 0100 — — — — — — — SWDTEN ---- ---0 IPEN SBOREN — RI TO PD POR BOR 01-1 1100 x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F45K50 devices only. PIC18(L)F2XK50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 85 PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR FCFh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCEh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx FCDh T1CON FCCh T1GCON SOSCEN T1SYNC TMR1GE TMR1CS T1GPOL T1GTM T1CKPS T1GSPM T1GGO/ DONE T1GVAL FCBh SSP1CON3 FCAh SSP1MSK SSP1 Mask Register bits ACKTIM PCIE SCIE BOEN SDAHT SBCDE 1111 1111 FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register xxxx xxxx FC8h SSP1ADD SSP1 Address Register in I2C™ Slave Mode. SSP1 Baud Rate Reload Register in I2C Master Mode FC7h SSP1STAT SMP FC6h SSP1CON1 FC5h SSP1CON2 FC4h ADRESH A/D Result, High Byte FC3h ADRESL A/D Result, Low Byt FC2h ADCON0 — CKE D/A WCOL SSPOV SSPEN CKP GCEN ACKSTAT ACKDT ACKEN P S R/W RCEN PEN RD16 TMR1ON T1GSS AHEN DHEN 0000 0000 0000 0x00 0000 0000 0000 0000 UA BF RSEN SEN SSPM 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CHS GO/DONE ADON -000 0000 FC1h ADCON1 TRIGSEL — FC0h ADCON2 ADFM — FBFh CCPR1H Capture/Compare/PWM Register 1, High Byte FBEh CCPR1L Capture/Compare/PWM Register 1, Low Byte FBDh CCP1CON FBCh TMR2 Timer2 Register FBBh PR2 Timer2 Period Register FBAh T2CON — FB9h PSTR1CON — — — STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 FB8h BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 FB7h PWM1CON P1RSEN FB6h ECCP1AS ECCP1ASE FB5h ACTCON ACTEN ACTUD — ACTSRC ACTLOCK — FB4h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ DONE T3GVAL FB3h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register FB2h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register FB1h T3CON FB0h SPBRGH1 EUSART Baud Rate Generator, High Byte 0000 0000 FAFh SPBRG1 EUSART Baud Rate Generator, Low Byte 0000 0000 FAEh RCREG1 EUSART Receive Register 0000 0000 FADh TXREG1 EUSART Transmit Register FACh TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 FABh RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x FA9h EEADR EEADR 0000 0000 FA8h EEDATA EEPROM Data Register 0000 0000 FA7h EECON2 EEPROM Control Register 2 (not a physical register) FA6h EECON1 FA5h — — PVCFG NVCFG ACQT P1M ADCS 0--- 0000 0-00 0000 xxxx xxxx xxxx xxxx DC1B CCP1M 0000 0000 0000 0000 1111 1111 T2OUTPS TMR2ON T2CKPS P1DC ECCP1AS TMR3CS 0000 0000 PSS1AC T3CKPS SOSCEN -000 0000 PSS1BD T3SYNC ACTORS — T3GSS 0000 0000 00-0 0-00000 0x00 xxxx xxxx xxxx xxxx RD16 TMR3ON 0000 0000 0000 0000 ---- ---- EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 0000 1111 FA4h PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 0000 0000 FA3h PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 0000 0000 FA2h IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 FA1h PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 FA0h PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 Legend: Note 1: 2: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F45K50 devices only. PIC18(L)F2XK50 devices only. DS30000684B-page 86  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F9Fh IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 F9Eh PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 F9Dh PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 F9Ch HLVDCON VDIRMAG BGVST IRVST HLVDEN F9Bh OSCTUNE SPLLMULT F9Ah CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS F99h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH F98h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH F97h CCP2CON — — F96h TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 1--- -111 F95h TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 F94h TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 1111 -111 F93h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 F92h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 F91h CCPR2H Capture/Compare/PWM Register 2, High Byte F90h CCPR2L Capture/Compare/PWM Register 2, Low Byte F8Fh CTMUCONH CTMUEN — F8Eh CTMUCONL EDG2POL EDG2SEL F8Dh LATE(1) — — — — — LATE2 LATE1 LATE0 F8Ch LATD(1) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx F8Bh LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xxxx -xxx F8Ah LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx F89h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx F88h CTMUICON F87h IOCC IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 0000 -000 F86h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- F85h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 PORTE(2) — — — — RE3 — — — ---- x--- PORTE(1) — — — — RE3 RE2 RE1 RE0 ---- xxxx F84h HLVDL 0000 0000 TUN 0000 0000 DC2B CTMUSIDL C1SYNC C2SYNC CCP2M 0000 0000 0000 1000 0000 1000 --00 0000 xxxx xxxx xxxx xxxx TGEN EDG1POL EDGEN EDGSEQEN EDG1SEL IDISSEN CTTRIG EDG2STAT EDG1STAT ITRIM IRNG 0-00 0000 0000 00xx ---- -xxx 0000 0000 F83h PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx F82h PORTC RC7 RC6 — — — RC2 RC1 RC0 xx-- -xxx F81h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx F80h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx F7Fh PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD -000 0000 F7Eh PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD -000 -000 F7Dh VREFCON0 FVREN FVRST — — — — 0001 00-- F7Ch VREFCON1 DACEN DACLPS DACOE — DACNSS 000- 00-0 FVRS — DACPSS F7Bh VREFCON2 — — — F7Ah SLRCON — — — SLRE SLRD SLRC SLRB SLRA ---1 1111 F79h UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F78h UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F77h UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F76h UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F75h UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F74h UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F73h UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F72h UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F71h UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F70h UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 Legend: Note 1: 2: DACR ---0 0000 x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F45K50 devices only. PIC18(L)F2XK50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 87 PIC18(L)F2X/45K50 TABLE 6-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/45K50 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F6Fh UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Eh UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Dh UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Ch UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Bh UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 F6Ah UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL F69h UFRMH — — — — — FRM ---0 0000 ---- -xxx F68h UFRML F67h UEIR BTSEF — — BTOEF FRM DFN8EF CRC16EF CRC5EF PIDEF F66h UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 F65h UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 F64h UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 F63h UADDR — F62h UCFG UTEYE F61h USTAT — F60h UCON — PPBRST SE0 PKTDIS F5Fh ANSELE — — — — F5Eh ANSELD ANSD7 ANSD6 ANSD5 F5Dh ANSELC ANSC7 ANSC6 — F5Ch ANSELB — — F5Bh ANSELA — F5Ah VREGCON — F59h CCPTMRS — F58h SRCON0 SRLEN F57h SRCON1 SRSPE SRSCKE SRSC2E xxxx xxxx ADDR UOEMON — UPUEN UTRDIS ENDP 0--0 0000 -000 0000 FSEN PPB 00-0 0000 DIR PPBI USBEN RESUME SUSPND — -0x0 000- — ANSE2 ANSE1 ANSE0 ---- -111 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 — — ANSC2 — — 11-- -1-- ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 — — — — — VREGPM ---- --01 — — — C2TSEL — — C1TSEL ---- 0--0 SRQEN SRNQEN SRPS SRPR 0000 0000 SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 SRCLK — -xxx xxx- F56h — — — — — — — — — ---- ---- F55h — — — — — — — — — ---- ---- F54h — — — — — — — — — ---- ---- F53h — — — — — — — — — ---- ---- Legend: Note 1: 2: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F45K50 devices only. PIC18(L)F2XK50 devices only. DS30000684B-page 88  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 6.4.6 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u u1uu’). 6.5 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Section 27.2 “Extended Instruction Set” and Table 27-3. Note: The C and DC bits operate as the Borrow and Digit Borrow bits, respectively, in subtraction. Register Definitions: Status REGISTER 6-2: STATUS: STATUS REGISTER U-0 U-0 U-0 — — — R/W-x N R/W-x OV R/W-x Z R/W-x R/W-x (1) DC bit 7 C(1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (two’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: For Digit Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.  2012-2014 Microchip Technology Inc. DS30000684B-page 89 PIC18(L)F2X/45K50 6.6 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.7 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: • • • • Inherent Literal Direct Indirect A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 6.6.3 An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 6.7.1 “Indexed Addressing with Literal Offset”. 6.6.1 The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.4.2 “Bank Select Register (BSR)”) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. Indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read or written. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for indirect addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 6-5. EXAMPLE 6-5: NEXT 6.6.2 INDIRECT ADDRESSING LFSR CLRF DIRECT ADDRESSING Direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. BTFSS BRA CONTINUE HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer FSR0H, 1 ; All done with ; Bank1? NEXT ; NO, clear next ; YES, continue In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 6.4.4 “General Purpose Register File”) or a location in the Access Bank (Section 6.4.3 “Access Bank”) as the data source for the instruction. DS30000684B-page 90  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 6.6.3.1 FSR Registers and the INDF Operand 6.6.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers which cannot be directly read or written. Accessing these registers actually accesses the location to which the associated FSR register pair points, and also performs a specific action on the FSR value. They are: • POSTDEC: accesses the location to which the FSR points, then automatically decrements the FSR by 1 afterwards • POSTINC: accesses the location to which the FSR points, then automatically increments the FSR by 1 afterwards • PREINC: automatically increments the FSR by 1, then uses the location to which the FSR points in the operation • PLUSW: adds the signed value of the W register (range of -128 to +127) to that of the FSR and uses the location to which the result points in the operation. Indirect addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as “virtual” registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer. Because indirect addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 6-7: FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In this context, accessing an INDF register uses the value in the associated FSR register without changing it. Similarly, accessing a PLUSW register gives the FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. INDIRECT ADDRESSING 000h Using an instruction with one of the indirect addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 Bank 2 Bank 3 through Bank 13 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory  2012-2014 Microchip Technology Inc. DS30000684B-page 91 PIC18(L)F2X/45K50 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.6.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by indirect addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 6.7 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. 6.7.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most bit-oriented and byte-oriented instructions – can invoke a form of indexed addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0) and • The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in direct addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 6.7.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use direct addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is shown in Figure 6-8. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 27.2.1 “Extended Instruction Syntax”. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. DS30000684B-page 92  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f  60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode. 000h 060h Bank 0 100h 00h Bank 1 through Bank 14 F00h 60h Valid range for ‘f’ Access RAM FFh Bank 15 F60h SFRs FFFh Data Memory When ‘a’ = 0 and f5Fh: The instruction executes in Indexed Literal Offset mode. ‘f’ is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where ‘k’ is the same as ‘f’. 000h 060h Bank 0 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F60h SFRs FFFh Data Memory When ‘a’ = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). ‘f’ is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. BSR 00000000 000h 060h Bank 0 100h Bank 1 through Bank 14 001001da ffffffff F00h Bank 15 F60h SFRs FFFh Data Memory  2012-2014 Microchip Technology Inc. DS30000684B-page 93 PIC18(L)F2X/45K50 6.7.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 6.4.3 “Access Bank”). An example of Access Bank remapping in this addressing mode is shown in Figure 6-9. 6.8 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 27.2 “Extended Instruction Set”. Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use direct addressing as before. FIGURE 6-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). 000h Bank 0 100h 120h 17Fh 200h Bank 1 Window Bank 1 00h Bank 1 “Window” 5Fh 60h Special File Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 2 through Bank 14 Bank 0 addresses below 5Fh can still be addressed by using the BSR. SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory DS30000684B-page 94  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the specified VDD ranges. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation cannot be issued from user code. • Table Read (TBLRD) • Table Write (TBLWT) Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The table read operation retrieves one byte of data directly from program memory and places it into the TABLAT register. Figure 7-1 shows the operation of a table read. The table write operation stores one byte of data from the TABLAT register into a write block holding register. The procedure to write the contents of the holding registers into program memory is detailed in Section 7.6 “Writing to Flash Program Memory”. Figure 7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory.  2012-2014 Microchip Technology Inc. DS30000684B-page 95 PIC18(L)F2X/45K50 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written. The process for writing the holding registers to the program memory array is discussed in Section 7.6 “Writing to Flash Program Memory”. 7.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • • • • EECON1 register EECON2 register TABLAT register TBLPTR registers 7.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When EEPGD is clear, any subsequent operations will operate on the data EEPROM memory. When EEPGD is set, any subsequent operations will operate on the program memory. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When CFGS is set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 26.0 “Special Features of the CPU”). When CFGS is clear, memory selection access is determined by EEPGD. DS30000684B-page 96 The FREE bit allows the program memory erase operation. When FREE is set, an erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. The WREN bit is clear on power-up. The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The WR bit cannot be cleared, only set, by firmware. The WR bit is cleared by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. The EEIF flag stays set until cleared by firmware.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 7.3 Register Definitions: Memory Control REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2012-2014 Microchip Technology Inc. DS30000684B-page 97 PIC18(L)F2X/45K50 7.3.1 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.3.2 When a TBLWT is executed the byte in the TABLAT register is written, not to Flash memory but, to a holding register in preparation for a program memory write. The holding registers constitute a write block which varies depending on the device (see Table 7-1).The six LSbs of the TBLPTRL register determine which specific address within the holding register block is written to. The MSBs of the Table Pointer have no effect during TBLWT operations. TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits. When a program memory write is executed (WR = 1), the entire holding register block is written to the Flash memory at the address determined by the MSbs of the TBLPTR. The six LSBs are ignored during Flash memory writes. For more detail, see Section 7.6 “Writing to Flash Program Memory”. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations on the TBLPTR affect only the low-order 21 bits. 7.3.3 When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR) are ignored. Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 7-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 TBLPTRH 15 8 TABLE ERASE/WRITE TBLPTR(1) 7 TBLPTRL 0 TABLE WRITE TBLPTR(1) TABLE READ – TBLPTR Note 1: n = 5 for block sizes of 64 bytes. DS30000684B-page 98  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 7.4 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 7-1: FETCH TBLRD TBLPTR = xxxxx0 TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD  2012-2014 Microchip Technology Inc. ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data DS30000684B-page 99 PIC18(L)F2X/45K50 7.5 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR point to the block being erased. The TBLPTR bits are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The write initiate sequence for EECON2, shown as steps 4 through 6 in Section 7.5.1 “Flash Program Memory Erase Sequence”, is used to guard against accidental writes. This is sometimes referred to as a long write. 7.5.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory is: 1. 2. 3. 4. 5. 6. 7. 8. Load Table Pointer register with address of block being erased. Set the EECON1 register for the erase operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN bit to enable writes; • set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the block erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. EXAMPLE 7-2: ERASING A FLASH PROGRAM MEMORY BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, ; ; ; ; ; ERASE_BLOCK Required Sequence DS30000684B-page 100 EEPGD CFGS WREN FREE GIE point to Flash program memory access Flash program memory enable write to memory enable block Erase operation disable interrupts ; write 55h WR GIE ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 The programming block size is 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted during a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are only as many holding registers as there are bytes in a write block (64 bytes). The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. 7.6 Writing to Flash Program Memory Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction needs to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. After all the holding registers have been written, the programming operation of that block of memory is started by configuring the EECON1 register for a program memory write and performing the long write sequence. FIGURE 7-5: Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a ‘0’ to a ‘1’. When modifying individual bytes, it is not necessary to load all holding registers before executing a long write operation. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxx00 TBLPTR = xxxx01 Holding Register 8 TBLPTR = xxxxYY(1) TBLPTR = xxxx02 Holding Register 8 Holding Register Holding Register Program Memory Note 1: YY = 3Fh for 64 byte write blocks. 7.6.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the block erase procedure. Load Table Pointer register with address of first byte being written. Write the 64-byte block into the holding registers with auto-increment (TBLWT*+ or TBLWT+*). Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable writes.  2012-2014 Microchip Technology Inc. 8. 9. 10. 11. 12. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Verify the memory (table read). This procedure will require about 6 ms to update each write block of memory. An example of the required code is given in Example 7-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the bytes in the holding registers. DS30000684B-page 101 PIC18(L)F2X/45K50 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64’ COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; load TBLPTR with the base ; address of the memory block MOVLW MOVWF MOVLW MOVWF BlockSize COUNTER D’64’/BlockSize COUNTER2 MOVF MOVWF TBLWT+* POSTINC0, W TABLAT ; point to buffer ; Load TBLPTR with the base ; address of the memory block READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat MODIFY_WORD ; update buffer word ERASE_BLOCK Required Sequence BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Erase operation disable interrupts ; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer WRITE_BUFFER_BACK ; number of bytes in holding register ; number of write blocks in 64 bytes WRITE_BYTE_TO_HREGS DS30000684B-page 102 ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; loop until holding registers are full BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DCFSZ BRA BSF BCF EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE EECON1, WREN ; ; ; ; PROGRAM_MEMORY Required Sequence 7.6.2 ; write 55h ; ; ; ; ; ; WRITE VERIFY UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. TABLE 7-2: Name TBLPTRU write 0AAh start program (CPU stall) repeat for remaining write blocks re-enable interrupts disable write to memory 7.6.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6.3 point to Flash program memory access Flash program memory enable write to memory disable interrupts PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 26.0 “Special Features of the CPU” for more detail. 7.7 Flash Program Operation During Code Protection See Section 26.5 “Program Verification and Code Protection” for details on code protection of Flash program memory. REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 Bit 6 — — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR) Register on page — TBPLTRH Program Memory Table Pointer High Byte (TBLPTR) — TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR) — TABLAT Program Memory Table Latch INTCON EECON2 GIE/GIEH PEIE/GIEL — TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 97 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIE2 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during Flash/EEPROM access.  2012-2014 Microchip Technology Inc. DS30000684B-page 103 PIC18(L)F2X/45K50 8.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the specified VDD range. Four SFRs are used to read and write to the data EEPROM as well as the program memory. They are: • • • • EECON1 EECON2 EEDATA EEADR The data EEPROM allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write, and the EEADR register holds the address of the EEPROM location being accessed. The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer; it will vary with voltage and temperature as well as from chipto-chip. Please refer to the Data EEPROM Memory parameters in Section 29.0 “Electrical Specifications” for limits. 8.1 EEADR Register The EEADR register is used to address the data EEPROM for read and write operations. The 8-bit range of the register can address a memory range of 256 bytes (00h to FFh). 8.2 EECON1 and EECON2 Registers Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. The EECON1 register (Register 8-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When the EEPGD bit is clear, operations will access the data EEPROM memory. When the EEPGD bit is set, program memory is accessed. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When the CFGS bit is set, subsequent operations access Configuration registers. When the CFGS bit is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR may read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit can be set but not cleared by software. It is cleared only by hardware at the completion of the write operation. Note: The EEIF interrupt flag bit of the PIR2 register is set when the write is complete. It must be cleared by software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 7.1 “Table Reads and Table Writes” regarding table reads. The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. DS30000684B-page 104  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 8-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row (Block) Erase Enable bit 1 = Erase the program memory block addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) by software.) 0 = Write cycle to the EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.  2012-2014 Microchip Technology Inc. DS30000684B-page 105 PIC18(L)F2X/45K50 8.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 8-1. 8.4 Writing to the Data EEPROM Memory Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared by hardware and the EEPROM Interrupt Flag bit, EEIF, is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 8-2 must be followed to initiate the write cycle. 8.5 The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. EXAMPLE 8-1: MOVLW MOVWF BCF BCF BSF MOVF DATA EEPROM READ DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W EXAMPLE 8-2: Required Sequence Write Verify ; ; ; ; ; ; Data Memory Address to read Point to DATA memory Access EEPROM EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF DATA_EE_ADDR_LOW EEADR DATA_EE_ADDR_HI EEADRH DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; BCF EECON1, WREN ; User code execution ; Disable writes on write complete (EEIF set) DS30000684B-page 106 Data Memory Address to write Data Memory Value to write Point to DATA memory Access EEPROM Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Enable Interrupts  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 8.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 26.0 “Special Features of the CPU” for additional information. 8.7 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT). The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 8.8 Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to the Data EEPROM Memory parameters in Section 29.0 “Electrical Specifications” for write cycle limits. If this is the case, then an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 8-3. Note: EXAMPLE 8-3: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification. DATA EEPROM REFRESH ROUTINE CLRF BCF BCF BCF BSF EEADR EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP BCF BSF EECON1, WREN INTCON, GIE CFGS EEPGD GIE WREN Loop  2012-2014 Microchip Technology Inc. ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write 0AAh Set WR bit to begin write Wait for write to complete ; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts DS30000684B-page 107 PIC18(L)F2X/45K50 TABLE 8-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL EEADR EEADR7 EEADR6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — EEDATA EEPROM Data Register — EECON2 EEPROM Control Register 2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 105 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 Legend: — = unimplemented, read as ‘0’. Shaded bits are not used during EEPROM access. DS30000684B-page 108  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 9-1. 9.2 EXAMPLE 9-1: MOVF MULWF ARG1, W ARG2 EXAMPLE 9-2: MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Operation Example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Time Cycles (Max) @ 48 MHz @ 40 MHz @ 10 MHz @ 4 MHz Multiply Method Program Memory (Words) Without hardware multiply 13 69 5.7 s 6.9 s 27.6 s 69 s Hardware multiply 1 1 83.3 ns 100 ns 400 ns 1 s Without hardware multiply 33 91 7.5 s 9.1 s 36.4 s 91 s Hardware multiply 6 6 500 ns 600 ns 2.4 s 6 s Without hardware multiply 21 242 20.1 s 24.2 s 96.8 s 242 s Hardware multiply 28 28 2.3 s 2.8 s 11.2 s 28 s Without hardware multiply 52 254 21.6 s 25.4 s 102.6 s 254 s Hardware multiply 35 40 3.3 s 4.0 s 16.0 s 40 s  2012-2014 Microchip Technology Inc. DS30000684B-page 109 PIC18(L)F2X/45K50 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES). EQUATION 9-1: RES3:RES0 = = 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L  ARG2H:ARG2L (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + (ARG1L  ARG2L) EXAMPLE 9-3: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers (RES). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. EQUATION 9-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L = (ARG1H  ARG2H  216) + (ARG1H  ARG2L  28) + (ARG1L  ARG2H  28) + (ARG1L  ARG2L) + (-1  ARG2H  ARG1H:ARG1L  216) + (-1  ARG1H  ARG2H:ARG2L  216) EXAMPLE 9-4: 16 x 16 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products CONT_CODE : DS30000684B-page 110  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 10.0 INTERRUPTS The PIC18(L)F2X/45K50 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low priority level (INT0 does not have a priority bit, it is always a high priority). The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress. There are 13 registers used to control interrupt operation. These registers are: • • • • • INTCON, INTCON2, INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 RCON It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: • Flag bit to indicate that an interrupt event occurred • Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set • Priority bit to select high priority or low priority 10.1 Mid-Range Compatibility When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC microcontroller mid-range devices. In Compatibility mode, the interrupt priority bits of the IPRx registers have no effect. The PEIE/GIEL bit of the INTCON register is the global interrupt enable for the peripherals. The PEIE/GIEL bit disables only the peripheral interrupt sources and enables the peripheral interrupt sources when the GIE/GIEH bit is also set. The GIE/GIEH bit of the INTCON register is the global interrupt enable which enables all non-peripheral interrupt sources and disables all interrupt sources, including the peripherals. All interrupts branch to address 0008h in Compatibility mode.  2012-2014 Microchip Technology Inc. 10.2 Interrupt Priority The interrupt priority feature is enabled by setting the IPEN bit of the RCON register. When interrupt priority is enabled the GIE/GIEH and PEIE/GIEL global interrupt enable bits of Compatibility mode are replaced by the GIEH high priority, and GIEL low priority, global interrupt enables. When set, the GIEH bit of the INTCON register enables all interrupts that have their associated IPRx register or INTCONx register priority bit set (high priority). When clear, the GIEH bit disables all interrupt sources including those selected as low priority. When clear, the GIEL bit of the INTCON register disables only the interrupts that have their associated priority bit cleared (low priority). When set, the GIEL bit enables the low priority sources when the GIEH bit is also set. When the interrupt flag, enable bit and appropriate Global Interrupt Enable (GIE) bit are all set, the interrupt will vector immediately to address 0008h for high priority, or 0018h for low priority, depending on level of the interrupting source’s priority bit. Individual interrupts can be disabled through their corresponding interrupt enable bits. 10.3 Interrupt Response When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. The GIE/GIEH bit is the global interrupt enable when the IPEN bit is cleared. When the IPEN bit is set, enabling interrupt priority levels, the GIEH bit is the high priority global interrupt enable and the GIEL bit is the low priority global interrupt enable. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits in the INTCONx and PIRx registers. The interrupt flag bits must be cleared by software before re-enabling interrupts to avoid repeating the same interrupt. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE/GIEH bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB interrupt-on-change, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit. DS30000684B-page 111 PIC18(L)F2X/45K50 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. FIGURE 10-1: PIC18 INTERRUPT LOGIC Wake-up if in Idle or Sleep modes INT0IF INT0IE PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 TMR0IF TMR0IE TMR0IP IOCIF IOCIE IOCIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP (1) Interrupt to CPU Vector to Location 0008h GIEH/GIE IPEN IPEN GIEL/PEIE IPEN High Priority Interrupt Generation Low Priority Interrupt Generation PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP IOCIF IOCIE IOCIP (1) GIEH/GIE GIEL/PEIE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Note 1: The IOCIF interrupt also requires the individual pin IOCB enables. DS30000684B-page 112  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 10.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. 10.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request Flag registers (PIR1, PIR2 and PIR3). 10.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE/GIEL bit must be set to enable any of these peripheral interrupts. 10.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.  2012-2014 Microchip Technology Inc. DS30000684B-page 113 PIC18(L)F2X/45K50 10.8 Register Definitions: Interrupt Control REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts including peripherals When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all interrupts including low priority bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority interrupts 0 = Disables all low priority interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 IOCIE: Interrupt-On-Change (IOCx) Interrupt Enable bit(2) 1 = Enables the IOCx port change interrupt 0 = Disables the IOCx port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared by software) 0 = The INT0 external interrupt did not occur bit 0 IOCIF: Interrupt-On-Change (IOCx) Interrupt Flag bit(1) 1 = At least one of the IOC pins changed state (must be cleared by software) 0 = None of the IOC pins have changed state Note 1: 2: Note: A mismatch condition will continue to set the IOCIF bit. Reading PORTB/PORTC will end the mismatch condition and allow the bit to be cleared. Port change interrupts also require the individual pins IOCBx/IOCCx enables. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30000684B-page 114  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 10-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding WPUB bit is set. bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 IOCIP: Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.  2012-2014 Microchip Technology Inc. DS30000684B-page 115 PIC18(L)F2X/45K50 REGISTER 10-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared by software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared by software) 0 = The INT1 external interrupt did not occur Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS30000684B-page 116  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ACTIF: Active Clock Tuning Interrupt Flag bit 1 = An Active Clock Tuning Event generated an interrupt (must be cleared in software) 0 = No Active Clock Tuning interrupt is pending bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared by software) 0 = The A/D conversion is not complete or has not been started bit 5 RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART receive buffer is empty bit 4 TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART transmit buffer is full bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared by software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared by software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared by software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared by software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared by software) 0 = TMR1 register did not overflow Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE/ GIEH of the INTCON register. 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.  2012-2014 Microchip Technology Inc. DS30000684B-page 117 PIC18(L)F2X/45K50 REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device clock operating bit 6 C1IF: Comparator C1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared by software) 0 = Comparator C1 output has not changed bit 5 C2IF: Comparator C2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared by software) 0 = Comparator C2 output has not changed bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared by software) 0 = The write operation is not complete or has not been started bit 3 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared by software) 0 = No bus collision occurred bit 2 HLVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred (direction determined by the VDIRMAG bit of the HLVDCON register) 0 = A low-voltage condition has not occurred bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared by software) 0 = TMR3 register did not overflow bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared by software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared by software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. DS30000684B-page 118  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUIF USBIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIF: CTMU Interrupt Flag bit 1 = CTMU interrupt occurred (must be cleared in software) 0 = No CTMU interrupt occurred bit 2 USBIF: USB Interrupt Flag bit 1 = USB requested an interrupt (must be cleared in software) 0 = No USB interrupt request bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bit 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate occurred  2012-2014 Microchip Technology Inc. x = Bit is unknown DS30000684B-page 119 PIC18(L)F2X/45K50 REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTIE: Active Clock Tuning Interrupt Enable bit 1 = Enables Active Clock Tuning interrupt 0 = Disables Active Clock Tuning interrupt bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt bit 4 TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS30000684B-page 120 x = Bit is unknown  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 HLVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled  2012-2014 Microchip Technology Inc. x = Bit is unknown DS30000684B-page 121 PIC18(L)F2X/45K50 REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUIE USBIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIE: CTMU Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 USBIE: USB Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled DS30000684B-page 122 x = Bit is unknown  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACTIP: Active Clock Tuning Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: EUSART Transmit Interrupt Priority bit x = Bit is unknown 1 = High priority 0 = Low priority bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority  2012-2014 Microchip Technology Inc. DS30000684B-page 123 PIC18(L)F2X/45K50 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 C2IP: Comparator C2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: MSSP Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority DS30000684B-page 124 x = Bit is unknown  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — CTMUIP USBIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUIP: CTMU Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 USBIP: USB Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority  2012-2014 Microchip Technology Inc. x = Bit is unknown DS30000684B-page 125 PIC18(L)F2X/45K50 10.9 INTn Pin Interrupts 10.10 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE. Flag bit, INTxF, must be cleared by software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wakeup the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global Interrupt Enable bit, GIE/GIEH, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP and INT2IP of the INTCON3 register. There is no priority bit associated with INT0. It is always a high priority interrupt source. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh  00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE of the INTCON register. Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP of the INTCON2 register. See Section 12.0 “Timer0 Module” for further details on the Timer0 module. 10.11 PORTB/PORTC Interrupt-onChange An input change on PORTB or PORTC sets flag bit, IOCIF of the INTCON register. The interrupt can be enabled/disabled by setting/clearing enable bit, IOCIE of the INTCON register. Pins must also be individually enabled with the IOCB/IOCC register. Interrupt priority for interrupt-on-change is determined by the value contained in the interrupt priority bit, IOCIP of the INTCON2 register. 10.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 6.2.2 “Fast Register Stack”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 10-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS DS30000684B-page 126 ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 10-1: Name ANSELB INTCON REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 — — GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP Bit 2 Bit 1 Bit 0 Register on page ANSB3 ANSB2 ANSB1 ANSB0 148 IOCIE TMR0IF INT0IF IOCIF 114 Bit 5 Bit 4 Bit 3 ANSB5 ANSB4 TMR0IE INT0IE INTEDG1 INTEDG2 — — TMR0IP — IOCIP 115 INT2IE INT1IE — INT2IF INT1IF 116 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 151 IOCC IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 151 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 IPR3 — — — — CTMUIP USBIP PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE PIE3 — — — — CTMUIE USBIE PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIR3 PORTB RCON Legend: TMR3GIP TMR1GIP 125 TMR2IE TMR1IE 120 TMR3IE CCP2IE 121 TMR3GIE TMR1GIE 122 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 146 IPEN SBOREN — RI TO PD POR BOR 64 — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts. TABLE 10-2: CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 CONFIG4L DEBUG XINST ICPRT — — LVP — STRVEN 377 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts.  2012-2014 Microchip Technology Inc. DS30000684B-page 127 PIC18(L)F2X/45K50 11.0 I/O PORTS 11.1 Depending on the device selected and features enabled, there are up to five ports available. All pins of the I/O ports are multiplexed with one or more alternate functions from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has five registers for its operation. These registers are: • TRIS register (data direction register) • PORT register (reads the levels on the pins of the device) • LAT register (output latch) • ANSEL register (analog input control) • SLRCON register (port slew rate control) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. FIGURE 11-1: GENERIC I/O PORT OPERATION TRISx RD LAT Data Bus D WR LAT or Port Q I/O pin(1) CK Data Latch D WR TRIS PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the PORT latch. The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RA4/T0CKI/C1OUT pin. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in the Configuration register (see Section 26.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs, and the comparator voltage reference output. The operation of pins RA and RA5 as analog is selected by setting the ANSELA bits in the ANSELA register which is the default setting after a Power-on Reset. Pins RA0 through RA5 may also be used as comparator inputs or outputs by setting the appropriate bits in the CM1CON0 and CM2CON0 registers. Note: Q ANSELx CK TRIS Latch Input Buffer RD TRIS Q D PORTA Registers On a Power-on Reset, RA5 and RA are configured as analog inputs and read as ‘0’. RA4 is configured as a digital input. The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the drivers of the PORTA pins, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. ENEN EXAMPLE 11-1: RD Port Note 1: I/O pins have diode protection to VDD and VSS. MOVLB CLRF CLRF MOVLW MOVWF DS30000684B-page 128 0xF LATA ; ; ; ; ANSELA ; ; 0CFh ; ; ; TRISA ; ; INITIALIZING PORTA Set BSR for banked SFRs Initialize PORTA by clearing output data latches Configure I/O for digital inputs Value used to initialize data direction Set RA as inputs RA as outputs  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 11-1: PORTA I/O SUMMARY Pin Name Function RA0/C12IN0-/AN0 RA0 RA1/C12IN1-/AN1 RA2/C2IN+/AN2/ DACOUT/VREF- RA3/C1IN+/AN3/ VREF+ RA4/C1OUT/SRQ/ T0CKI RA5/C2OUT/ SRNQ/SS1/ HLVDIN/AN4 RA6/CLKO/OSC2 Legend: TRIS ANSEL Setting Setting Pin Type Buffer Type Description 0 x O DIG LATA data output; not affected by analog input. 1 0 I TTL PORTA data input; disabled when analog input enabled. C12IN0- 1 1 I AN Comparators C1 and C2 inverting input. AN0 1 1 I AN Analog input 0. RA1 0 x O DIG LATA data output; not affected by analog input. 1 0 I TTL PORTA data input; disabled when analog input enabled. C12IN1- 1 1 I AN Comparators C1 and C2 inverting input. AN1 1 1 I AN Analog input 1. RA2 0 x O DIG LATA data output; not affected by analog input; disabled when DACOUT enabled. 1 0 I TTL PORTA data input; disabled when analog input enabled; disabled when DACOUT enabled. C2IN+ 1 1 I AN Comparator C2 non-inverting input. AN2 1 1 I AN Analog output 2. DACOUT x 1 O AN DAC Reference output. VREF- 1 1 I AN A/D reference voltage (low) input. RA3 0 x O DIG LATA data output; not affected by analog input. 1 0 I TTL PORTA data input; disabled when analog input enabled. C1IN+ 1 1 I AN Comparator C1 non-inverting input. AN3 1 1 I AN Analog input 3. VREF+ 1 1 I AN A/D reference voltage (high) input. RA4 0 — O DIG LATA data output. 1 — I ST PORTA data input; default configuration on POR. C1OUT 0 — O DIG Comparator C1 output. SR latch Q output; take priority over CCP 5 output. SRQ 0 — O DIG T0CKI 1 — I ST Timer0 external clock input. RA5 0 x O DIG LATA data output; not affected by analog input. 1 0 I TTL PORTA data input; disabled when analog input enabled. C2OUT 0 0 O DIG Comparator C2 output. SRNQ 0 0 O DIG SR latch Q output. SS1 1 0 I TTL SPI slave select input (MSSP). HLVDIN 1 1 I AN High/Low-Voltage Detect input. AN4 1 1 I AN A/D input 4. RA6 0 — O DIG LATA data output; enabled in INTOSC modes when CLKO is not enabled. 1 — I TTL PORTA data input; enabled in INTOSC modes when CLKO is not enabled. CLKO x — O DIG In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. OSC2 x — O XTAL Oscillator crystal output; connects to crystal or resonator in Crystal Oscillator mode. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C.  2012-2014 Microchip Technology Inc. DS30000684B-page 129 PIC18(L)F2X/45K50 TABLE 11-1: PORTA I/O SUMMARY (CONTINUED) Pin Name Function RA7/CLKI/OSC1 Legend: TRIS ANSEL Setting Setting RA7 Pin Type Buffer Type Description 0 — O DIG LATA data output; disabled in external oscillator modes. 1 — I TTL PORTA data input; disabled in external oscillator modes. CLKI x — I AN External clock source input; always associated with pin function OSC1. OSC1 x — I XTAL Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. TABLE 11-2: Name ANSELA CM1CON0 REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — C1ON C1OUT ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 C1OE C1POL C1SP C1R C2SP C2R CM2CON0 C2ON C2OUT C2OE C2POL VREFCON1 DACEN DACLPS DACOE — VREFCON2 HLVDCON PORTA — — — VDIRMAG BGVST IRVST DACPSS 147 C1CH 307 C2CH 307 — DACNSS DACR HLVDEN Register on page 334 335 HLVDL 364 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 146 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 150 SLRCON — — — SLRE SRCON0 SRLEN LATA SSP1CON1 SRCLK SLRD SLRC SLRB SLRA 152 SRQEN SRNQEN SRPS SRPR 328 WCOL SSPOV SSPEN CKP T0CON TMR0ON T08BIT T0CS T0SE PSA SSPM TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 252 T0PS TRISA2 TRISA1 153 TRISA0 149 Bit 0 Register on page Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA. TABLE 11-3: CONFIGURATION REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 Bit 5 Bit 4 CONFIG1H IESO FCMEN PCLKEN — Bit 3 Bit 2 Bit 1 FOSC 373 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTA. DS30000684B-page 130  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 11.1.1 PORTA OUTPUT PRIORITY Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 11-4 lists the PORTA pin functions from the highest to the lowest priority. Analog input functions, such as ADC and comparator, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below.  2012-2014 Microchip Technology Inc. DS30000684B-page 131 PIC18(L)F2X/45K50 TABLE 11-4: PORT PIN FUNCTION PRIORITY Port Function Priority by Port Pin Port bit 0 PORTA PORTB PORTC RA0 SDA SOSCO PORTD(2) PORTE(2) RD0 RE0 RB0 RC0 1 RA1 SCL SOSCI SCK CCP2(3) (1) RB1 2 DACOUT RA2 RE1 RD1 P1C RC1 CCP1 P1B(1) P1A RB2 CTPLS RD2 RE2 RC2 3 RA3 SDO(3) MCLR CCP2(4) RD3 VPP RE3 RB3 4 SRQ P1D(1) C1OUT RB4 DRD4 RA4 5 SRNQ D+ C2OUT P1B RD5 RA5 RB5 6 OSC2 PGC TX/CK CLKO ICDCK P1C RA6 RB6 RD6 OSC1 PGD RA7 ICDDT RC6 7 RB7 Note 1: 2: 3: 4: RX/DT P1D RC7 RD7 PIC18(L)F2XK50 devices. PIC18(L)F45K50 devices. Function default pin. Function alternate pin. DS30000684B-page 132  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 11.2 PORTB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 11-2: MOVLB CLRF MOVLW MOVWF MOVLW MOVWF 11.2.1 0xF LATB ; ; ; ; 0F0h ; ANSELB ; ; ; ; 0CFh ; ; ; TRISB ; ; ; INITIALIZING PORTB Set BSR for banked SFRs Initialize PORTB by clearing output data latches Value for init Enable RB for digital input pins (not required if config bit PBADEN is clear) Value used to initialize data direction Set RB as inputs RB as outputs RB as inputs PORTB OUTPUT PRIORITY Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 11-4 lists the PORTB pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below.  2012-2014 Microchip Technology Inc. 11.3 Additional PORTB Pin Functions PORTB pins RB have an interrupt-on-change option. All PORTB pins have a weak pull-up option. 11.3.1 WEAK PULL-UPS Each of the PORTB pins has an individually controlled weak internal pull-up. When set, each bit of the WPUB register enables the corresponding pin pull-up. When cleared, the RBPU bit of the INTCON2 register enables pull-ups on all pins which also have their corresponding WPUB bit set. When set, the RBPU bit disables all weak pull-ups. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, RB are configured as analog inputs by default and read as ‘0’; RB are configured as digital inputs. When the PBADEN Configuration bit is set to ‘0’, RB will alternatively be configured as digital inputs on POR. 11.3.2 INTERRUPT-ON-CHANGE Four of the PORTB pins (RB) are individually configurable as interrupt-on-change pins. Control bits in the IOCB register enable (when set) or disable (when clear) the interrupt function for each pin. When set, the IOCIE bit of the INTCON register enables interrupts on all pins which also have their corresponding IOCB bit set. When clear, the IOCIE bit disables all interrupt-on-changes. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupt-on-change comparison). For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTB. The ‘mismatch’ outputs of the last read are OR’d together to set the interrupt-on-change Interrupt flag bit (IOCIF) in the INTCON register. This interrupt can wake the device from the Sleep mode, or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB to clear the mismatch condition (except when PORTB is the source or destination of a MOVFF instruction). Execute at least one instruction after reading or writing PORTB, then clear the flag bit, IOCIF. DS30000684B-page 133 PIC18(L)F2X/45K50 11.3.3 A mismatch condition will continue to set the IOCIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the IOCIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the IOCIF flag will continue to be set if a mismatch is present. PORTB is multiplexed with several peripheral functions (Table 11-5). The pins have TTL input buffers. Some of these pin functions can be relocated to alternate pins using the Control fuse bits in CONFIG3H. RB3 is the default pin for SDO. Clearing the SDOMX bit moves the SDO pin function to RC7. If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the IOCIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-Change mode. Changes on one pin may not be seen while servicing changes on another pin. Note: ALTERNATE FUNCTIONS Two other pin functions, T3CKI and CCP2, can be relocated from their default pins to PORTB pins by clearing the control fuses in CONFIG3H. Clearing T3CMX and CCP2MX moves the pin functions to RB5 and RB3, respectively. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. TABLE 11-5: PORTB I/O SUMMARY Pin Function RB0/INT0/FLT0/ SRI/SDA/SDI/AN12 RB0 Buffer Type Description 0 x O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. INT0 1 0 I ST External interrupt 0. FLT0 1 0 I ST PWM Fault input for ECCP auto-shutdown. SRI 1 0 I ST SDA 1 0 I/O I2C™ SR latch input. I2C Data I/O (MSSP). SDI 1 0 I ST SPI Data in (MSSP). 1 1 I AN Analog input 12. RB1 0 x O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. INT1 1 0 I ST External Interrupt 1. P1C(3) 0 0 O DIG Enhanced CCP1 PWM output 3. SCK 0 0 O DIG MSSP SPI Clock output. 1 0 I ST MSSP SPI Clock input. 0 0 O DIG MSSP I2C Clock output. 2 SCL Note 1: 2: 3: Pin Type AN12 RB1/INT1/P1C/ SCK/SCL/C12IN3-/ AN10 Legend: TRIS ANSEL Setting Setting 1 0 I I C MSSP I2C Clock input. C12IN3- 1 1 I AN Comparators C1 and C2 inverting input. AN10 1 1 I AN Analog input 10. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for SDO when Configuration bit SDOMX is set. Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear. Function is on PORTD/PORTE for PIC18(L)F45K50 devices. DS30000684B-page 134  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 11-5: PORTB I/O SUMMARY (CONTINUED) Pin Function RB2/INT2/CTED1/ P1B/AN8 RB2 RB3/CTED2/CCP2/ SDO/C12IN2-/AN9 RB4/IOCB4/P1D/ AN11 RB5/IOCB5/T3CKI/ T1G/AN13 RB6/IOCB6/PGC RB7/IOCB7/PGD Legend: Note 1: 2: 3: TRIS ANSEL Setting Setting Pin Type Buffer Type Description 0 x O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. External interrupt 2. INT2 1 0 I ST CTED1 1 0 I ST CTMU Edge 1 input. P1B(3) 0 0 O DIG Enhanced CCP1 PWM output 2. AN8 1 1 I AN Analog input 8. RB3 0 x O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. CTED2 1 0 I ST CTMU Edge 2 input. CCP2(2) 0 0 O DIG Compare 2 output/PWM 2 output. 1 0 I ST Capture 2 input. SDO(1) 0 0 O DIG MSSP SPI data output. C12IN2- 1 1 I AN Comparators C1 and C2 inverting input. AN9 1 1 I AN Analog input 9. RB4 0 x O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. IOCB4 1 0 I TTL Interrupt-on-change pin. P1D(3) 0 0 O DIG Enhanced CCP1 PWM output 4. AN11 1 1 I AN Analog input 11. RB5 0 x O DIG LATB data output; not affected by analog input. 1 0 I TTL PORTB data input; disabled when analog input enabled. IOCB5 1 0 I TTL Interrupt-on-change pin 1. T3CKI(2) 1 0 I ST Timer3 clock input. T1G 1 0 I ST Timer1 external clock gate input. AN13 1 1 I AN Analog input 13. RB6 0 — O DIG LATB data output; not affected by analog input. 1 — I TTL PORTB data input; disabled when analog input enabled. IOCB6 1 — I TTL Interrupt-on-change pin. PGC x — I ST In-Circuit Debugger and ICSPTM programming clock input. RB7 0 — O DIG LATB data output; not affected by analog input. 1 — I TTL PORTB data input; disabled when analog input enabled. IOCB7 1 — I TTL Interrupt-on-change pin. PGD x — O DIG In-Circuit Debugger and ICSPTM programming data output. x — I ST In-Circuit Debugger and ICSPTM programming data input. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C. Default pin assignment for SDO when Configuration bit SDOMX is set. Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear. Function is on PORTD/PORTE for PIC18(L)F45K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 135 PIC18(L)F2X/45K50 TABLE 11-6: Name ANSELB ECCP1AS REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 — — ECCP1ASE CCP1CON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 ECCP1AS P1M PSS1AC PSS1BD DC1B CCP1M DC2B CCP2M Register on page 148 201 197 — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 115 INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 116 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 151 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 150 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 146 SLRC SLRB SLRA 152 CCP2CON PORTB SLRCON — — — T1GCON TMR1GE T1GPOL T1GTM T3CON TMR3CS TRISB WPUB Legend: Note 1: T1GSPM T3CKPS (1) SLRD T1GGO/DONE T1GVAL T1GSS SOSCEN T3SYNC RD16 TMR3ON 165 166 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 150 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Available on PIC18(L)F45K50 devices only. TABLE 11-7: Name CONFIGURATION REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 CONFIG3H MCLRE CONFIG4L DEBUG Legend: Note 1: SLRE (1) 197 Bit 5 Bit 4 Bit 3 SDOMX — T3CMX XINST ICPRT — Register on page Bit 2 Bit 1 Bit 0 — — PBADEN CCP2MX 376 — LVP(1) — STRVEN 377 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Can only be changed when in high voltage programming mode. DS30000684B-page 136  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 11.4 PORTC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 11-8). The pins have Schmitt Trigger input buffers. Some of these pin functions can be relocated to alternate pins using the Control fuse bits in CONFIG3H. RC0 is the default pin for T3CKI. Clearing the T3CMX bit moves the pin function to RB5. RC1 is the default pin for the CCP2 peripheral pin. Clearing the CCP2MX bit moves the pin function to the RB3 pin. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. The EUSART and MSSP peripherals override the TRIS bit to make a pin an output or an input, depending on the peripheral configuration. Refer to the corresponding peripheral section for additional information. Note: 11.4.1 PORTC OUTPUT PRIORITY Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 11-4 lists the PORTC pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. 11.4.2 INTERRUPT-ON-CHANGE All of the PORTC pins (RC and RC) are individually configurable as interrupt-on-change pins. Control bits in the IOCC register enable (when set) or disable (when clear) the interrupt function for each pin. See Section 11.3.2 “Interrupt-on-Change” for details on operation of interrupt-on-change. On a Power-on Reset, these pins are configured as analog inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 11-3: MOVLB CLRF MOVLW MOVWF MOVLW MOVWF 0xF LATC ; ; ; ; 0CFh ; ; ; TRISC ; ; ; 30h ; ; ANSELC ; ; ; INITIALIZING PORTC Set BSR for banked SFRs Initialize PORTC by clearing output data latches Value used to initialize data direction Set RC as inputs RC as outputs RC as inputs Value used to enable digital inputs RC dig input enable No ANSEL bits for RC RC dig input enable  2012-2014 Microchip Technology Inc. DS30000684B-page 137 PIC18(L)F2X/45K50 TABLE 11-8: PORTC I/O SUMMARY Pin Name RC0/IOCC0/T3CKI/ T3G/T1CKI/SOSCO Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC0 0 — O DIG LATC data output; not affected by analog input. 1 — I ST PORTC data input; disabled when analog input enabled. 1 — I TTL Interrupt-on-change pin. T3CKI(1) 1 — I ST Timer3 clock input. T3G 1 — I ST Timer3 external clock gate input. IOCC0 RC1/IOCC1/CCP2/ SOSCI T1CKI 1 — I ST SOSCO x — O XTAL RC1 0 — O DIG LATC data output; not affected by analog input. 1 — I ST PORTC data input; disabled when analog input enabled. 1 — I TTL Interrupt-on-change pin. 0 — O DIG Compare 2 output/PWM 2 output. 1 — I ST Capture 2 input. SOSCI x — I XTAL RC2 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. IOCC1 CCP2 RC2/CTPLS/P1A/ CCP1/IOCC2/AN14 (1) 0 0 O DIG CTMU pulse generator output. P1A 0 0 O DIG Enhanced CCP1 PWM output 1. CCP1 0 0 O DIG Compare 1 output/PWM 1 output. 1 0 I ST Capture 1 input. 1 — I TTL Interrupt-on-change pin. Analog input 14. AN14 1 1 I AN D- — — I XCVR USB bus differential minus line input. — — O XCVR USB bus differential minus line output. — — I ST — — I XCVR — — O XCVR — — I ST IOCC4 D+/IOCC5 D+ IOCC5 Legend: Note 1: 2: 3: Secondary oscillator input. CTPLS IOCC2 D-/IOCC4 Timer1 clock input. Secondary oscillator output. Interrupt-on-change pin. USB bus differential minus line input. USB bus differential minus line output. Interrupt-on-change pin. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. Default pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are set. Alternate pin assignment for SDO when Configuration bit SDOMX is clear. Function is on PORTD/PORTE for PIC18(L)F45K50 devices. DS30000684B-page 138  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 11-8: PORTC I/O SUMMARY (CONTINUED) Pin Name RC6/IOCC6/TX/CK/ AN18 Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC6 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. 1 0 I TTL Interrupt-on-change pin. IOCC6 RC7/IOCC7/SDO/RX/ DT/AN19 Legend: Note 1: 2: 3: TX 1 0 O DIG EUSART asynchronous transmit data output. CK 1 0 O DIG EUSART synchronous serial clock output. 1 0 I ST EUSART synchronous serial clock input. AN18 1 1 I AN Analog input 18. RC7 0 0 O DIG LATC data output; not affected by analog input. 1 0 I ST PORTC data input; disabled when analog input enabled. IOCC7 1 0 I TTL Interrupt-on-change pin. SDO(2) 1 0 O DIG Alternate MSSP SPI data output. RX 1 0 I ST EUSART asynchronous receive data in. DT 1 0 O DIG EUSART synchronous serial data output. 1 0 I ST EUSART synchronous serial data input. AN19 1 1 I AN Analog input 19. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. Default pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are set. Alternate pin assignment for SDO when Configuration bit SDOMX is clear. Function is on PORTD/PORTE for PIC18(L)F45K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 139 PIC18(L)F2X/45K50 TABLE 11-9: Name ANSELC ECCP1AS REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 ANSC7 ANSC6 ECCP1ASE CCP1CON Bit 5 Bit 4 Bit 3 Bit 2 — — — ANSC2 ECCP1AS P1M Bit 1 Bit 0 Register on page — — 148 PSS1AC PSS1BD DC1B CCP1M DC2B CCP2M 201 197 — — CTMUEN — CTMUSIDL TGEN EDGEN LATC7 LATC6 — — — PORTC RC7 RC6 — — — RC2 RC1 RC0 146 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 152 WCOL SSPOV SSPEN CKP CCP2CON CTMUCONH LATC SSP1CON1 197 EDGSEQEN IDISSEN LATC2 LATC1 CTTRIG 322 LATC0 150 SSPM 252 T1CON TMR1CS T1CKPS SOSCEN T1SYNC RD16 TMR1ON 165 T3CON TMR3CS T3CKPS SOSCEN T3SYNC RD16 TMR3ON 165 T3GCON TRISC TXSTA1 Legend: Note 1: TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 166 149 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. Available on PIC18(L)F45K50 devices only. TABLE 11-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC Name CONFIG3H Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC. DS30000684B-page 140  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 11.5 Note: PORTD Registers PORTD is only available on 40-pin and 44-pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., disable the output driver). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. 11.5.1 PORTD OUTPUT PRIORITY Each PORTD pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 11-4 lists the PORTD pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. All of the PORTD pins are multiplexed with analog and digital peripheral modules. See Table 11-11. Note: On a Power-on Reset, these pins are configured as analog inputs. EXAMPLE 11-4: MOVLB CLRF MOVLW MOVWF MOVLW MOVWF 0xF LATD ; ; ; ; 0CFh ; ; ; TRISD ; ; ; 30h ; ; ANSELD ; ; INITIALIZING PORTD Set BSR for banked SFRs Initialize PORTD by clearing output data latches Value used to initialize data direction Set RD as inputs RD as outputs RD as inputs Value used to enable digital inputs RD dig input enable RC dig input enable  2012-2014 Microchip Technology Inc. DS30000684B-page 141 PIC18(L)F2X/45K50 TABLE 11-11: PORTD I/O SUMMARY Pin Name RD0/AN20 RD0 RD1/AN21 RD2/AN22 RD3/AN23 RD4/AN24 RD5/P1B/AN25 RD6/P1C/AN26 RD7/P1D/AN27 Legend: Function TRIS ANSEL Pin Buffer Setting setting Type Type Description 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. AN20 1 1 I AN Analog input 20. RD1 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. AN21 1 1 I AN Analog input 21. RD2 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. AN22 1 1 I AN Analog input 22. RD3 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. AN23 1 1 I AN Analog input 23. RD4 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. AN24 1 1 I AN Analog input 24. RD5 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P1B 0 0 O DIG Enhanced CCP1 PWM output 2. AN25 1 1 I AN Analog input 25. RD6 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P1C 0 0 O DIG Enhanced CCP1 PWM output 3. AN26 1 1 I AN Analog input 26. RD7 0 0 O DIG LATD data output; not affected by analog input. 1 0 I ST PORTD data input; disabled when analog input enabled. P1D 0 0 O DIG Enhanced CCP1 PWM output 4. AN27 1 1 I AN Analog input 27. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. DS30000684B-page 142  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 11-12: REGISTERS ASSOCIATED WITH PORTD Name ANSELD(1) CCP1CON LATD(1) PORTD(1) (1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 148 P1M DC1B 197 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 150 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 146 SLRD SLRC SLRB SLRA — — — SLRE SSP1CON1 WCOL SSPOV SSPEN CKP TRISD(1) TRISD7 TRISD6 TRISD5 SLRCON CCP1M TRISD4 SSPM TRISD3 TRISD2 TRISD1 152 252 TRISD0 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTD. Note 1: Available on PIC18(L)F45K50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 143 PIC18(L)F2X/45K50 11.6 PORTE Registers Depending on the particular PIC18(L)F2X/45K50 device selected, PORTE is implemented in two different ways. 11.6.1 PORTE ON 40/44-PIN DEVICES For PIC18(L)F2X/45K50 devices, PORTE is a 4-bit wide port. Three pins (RE0/AN5, RE1/AN6 and RE2/ AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., disable the output driver). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). TRISE controls the direction of the REx pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. Note: On a Power-on Reset, RE are configured as analog inputs. The fourth pin of PORTE (MCLR/VPP/RE3) is an inputonly pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RE3 is enabled as a digital input-only if Master Clear functionality is disabled. EXAMPLE 11-5: CLRF CLRF MOVLW MOVWF LATE ; ; ; ANSELE ; ; 05h ; ; ; TRISE ; ; ; 11.6.2 PORTE ON 28-PIN DEVICES For PIC18(L)F2XK50 devices, PORTE is only available when Master Clear functionality is disabled (MCLR = 0). In these cases, PORTE is a single bit, input-only port comprised of RE3 only. The pin operates as previously described. 11.6.3 RE3 WEAK PULL-UP The port RE3 pin has an individually controlled weak internal pull-up. When set, the WPUE3 (TRISE) bit enables the RE3 pin pull-up. The RBPU bit of the INTCON2 register controls pull-ups on both PORTB and PORTE. When RBPU = 0, the weak pull-ups become active on all pins which have the WPUE3 or WPUBx bits set. When set, the RBPU bit disables all weak pullups. The pull-ups are disabled on a Power-on Reset. When the RE3 port pin is configured as MCLR, (CONFIG3H, MCLRE = 1 and CONFIG4L, LVP = 0), or configured for Low-Voltage Programming, (MCLRE = x and LVP = 1), the pull-up is always enabled and the WPUE3 bit has no effect. 11.6.4 PORTE OUTPUT PRIORITY Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 11-4 lists the PORTE pin functions from the highest to the lowest priority. Analog input functions, such as ADC, comparator and SR latch inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. INITIALIZING PORTE Initialize PORTE by clearing output data latches Configure analog pins for digital only Value used to initialize data direction Set RE as input RE as output RE as input DS30000684B-page 144  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 11-13: PORTE I/O SUMMARY Pin Function RE0/AN5 RE0 RE1/AN6 RE2/AN7 RE3/VPP/MCLR Legend: TRIS ANSEL Pin Setting Setting Type Buffer Type Description 0 0 O DIG LATE data output; not affected by analog input. 1 0 I ST PORTE data input; disabled when analog input enabled. AN5 1 1 I AN Analog input 5. RE1 0 0 O DIG LATE data output; not affected by analog input. 1 0 I ST PORTE data input; disabled when analog input enabled. AN6 1 1 I AN Analog input 6. RE2 0 0 O DIG LATE data output; not affected by analog input. 1 0 I ST PORTE data input; disabled when analog input enabled. AN7 1 1 I AN Analog input 7. RE3 — — I ST PORTE data input; enabled when Configuration bit MCLRE = 0. VPP — — P AN Programming voltage input; always available MCLR — — I ST Active-low Master Clear (device Reset) input; enabled when configuration bit MCLRE = 1. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C™ = Schmitt Trigger input with I2C. TABLE 11-14: REGISTERS ASSOCIATED WITH PORTE Name Bit 7 ANSELE(1) — INTCON2 RBPU Bit 6 Bit 5 — — INTEDG0 INTEDG1 Bit 2 Bit 1 Bit 0 Register on page — ANSE2 ANSE1 ANSE0 149 — TMR0IP — IOCIP 115 Bit 4 Bit 3 — INTEDG2 (1) LATE — — — — — LATE2 LATE1 LATE0 150 PORTE — — — — RE3 RE2(1) RE1(1) RE0(1) 147 SLRCON — — — SLRE(1) SLRD(1) SLRC SLRB SLRA 152 TRISE WPUE3 — — — — (1) TRISE2 TRISE1 (1) TRISE0 (1) 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTE. Note 1: Available on PIC18(L)F45K50 devices only. TABLE 11-15: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CONFIG3H MCLRE SDOMX — T3CMX — — CONFIG4L DEBUG XINST — — — (1) LVP Bit 1 Bit 0 PBADEN CCP2MX — STRVEN Register on page 376 377 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for interrupts. Note 1: Can only be changed when in high-voltage programming mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 145 PIC18(L)F2X/45K50 11.7 Port Analog Control 11.8 Most port pins are multiplexed with analog functions such as the Analog-to-Digital Converter and comparators. When these I/O pins are to be used as analog inputs it is necessary to disable the digital input buffer to avoid excessive current caused by improper biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSELA, ANSELB, ANSELC, ANSELD and ANSELE registers. Setting an ANSx bit high will disable the associated digital input buffer and cause all reads of that pin to return ‘0’ while allowing analog functions of that pin to operate correctly. Port Slew Rate Control The output slew rate of each port is programmable to select either the standard transition rate or a reduced transition rate of approximately 0.1 times the standard to minimize EMI. The reduced transition time is the default slew rate for all ports. The state of the ANSx bits has no affect on digital output functions. A pin with the associated TRISx bit clear and ANSx bit set will still operate as a digital output but the input mode will be analog. This can cause unexpected behavior when performing readmodify-write operations on the affected port. All ANSEL register bits default to ‘1’ upon POR and BOR, disabling digital inputs for their associated port pins. All TRIS register bits default to ‘1’ upon POR or BOR, disabling digital outputs for their associated port pins. As a result, all port pins that have an ANSEL register will default to analog inputs upon POR or BOR. 11.9 Register Definitions – Port Control PORTx(1): PORTx REGISTER REGISTER 11-1: R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x R/W-u/x Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Note 1: 2: Rx: PORTx I/O bit values(2) Register Description for PORTA, PORTB, PORTC and PORTD. Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. DS30000684B-page 146  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 11-2: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R/W-u/x R/W-u/x R/W-u/x R/W-u/x — — — — RE3(1) RE2(2), (3) RE1(2), (3) RE0(2), (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input bit value(1) bit 2-0 RE: PORTE I/O bit values(2), (3) Note 1: 2: 3: Port is available as input-only when MCLRE = 0. Writes to PORTx are written to corresponding LATx register. Reads from PORTx register is return of I/O pin values. Available on PIC18(L)F45K50 devices. REGISTER 11-3: ANSELA – PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: RA5 Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 ANSA: RA Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled  2012-2014 Microchip Technology Inc. x = Bit is unknown DS30000684B-page 147 PIC18(L)F2X/45K50 REGISTER 11-4: ANSELB – PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB: RB Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled REGISTER 11-5: x = Bit is unknown ANSELC – PORTC ANALOG SELECT REGISTER R/W-1 R/W-1 U-0 U-0 U-0 R/W-1 U-0 U-0 ANSC7 ANSC6 — — — ANSC2 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ANSC: RC Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 5-3 Unimplemented: Read as ‘0’ bit 2 ANSC: RC Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled bit 1-0 Unimplemented: Read as ‘0’ REGISTER 11-6: x = Bit is unknown ANSELD – PORTD ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ANSD: RD Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled DS30000684B-page 148  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 11-7: ANSELE – PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(1) ANSE1(1) ANSE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE: RE Analog Select bit(1) 1 = Digital input buffer disabled 0 = Digital input buffer enabled Note 1: x = Bit is unknown Available on PIC18(L)F45K50 devices only. REGISTER 11-8: TRISx: PORTx TRI-STATE REGISTER(1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISx7 TRISx6 TRISx5 TRISx4 TRISx3 TRISx2 TRISx1 TRISx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown TRISx: PORTx Tri-State Control bit 1 = PORTx pin configured as an input (tri-stated) 0 = PORTx pin configured as an output Register description for TRISA, TRISB, TRISC and TRISD. REGISTER 11-9: R/W-1 TRISE: PORTE TRI-STATE REGISTER U-0 WPUE3 U-0 — — U-0 — U-0 — R/W-1 TRISE2 (1) R/W-1 (1) TRISE1 R/W-1 TRISE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUE3: Weak Pull-up Register bits 1 = Pull-up enabled on PORT pin 0 = Pull-up disabled on PORT pin bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 TRISE: PORTE Tri-State Control bit(1) 1 = PORTE pin configured as an input (tri-stated) 0 = PORTE pin configured as an output Note 1: x = Bit is unknown Available on PIC18(L)F45K50 devices only.  2012-2014 Microchip Technology Inc. DS30000684B-page 149 PIC18(L)F2X/45K50 REGISTER 11-10: LATx: PORTx OUTPUT LATCH REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared LATx: PORTx Output Latch bit value(2) bit 7-0 Note 1: 2: x = Bit is unknown Register Description for LATA, LATB, LATC and LATD. Writes to PORTA are written to corresponding LATA register. Reads from PORTA register is return of I/O pin values. REGISTER 11-11: LATE: PORTE OUTPUT LATCH REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u — — — — — LATE2 LATE1 LATE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE: PORTE Output Latch bit value(2) Note 1: 2: x = Bit is unknown Available on PIC18(L)F45K50 devices only. Writes to PORTE are written to corresponding LATE register. Reads from PORTE register is return of I/O pin values. REGISTER 11-12: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown WPUB: Weak Pull-up Register bits 1 = Pull-up enabled on PORTB pin 0 = Pull-up disabled on PORTB pin DS30000684B-page 150  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 11-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCB: Interrupt-on-Change PORTB control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: x = Bit is unknown Interrupt-on-change requires that the IOCIE bit (INTCON) is set. REGISTER 11-14: IOCC: INTERRUPT-ON-CHANGE PORTC CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 IOCC7 IOCC6 IOCC5 IOCC4 — IOCC2 IOCC1 IOCC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCC: Interrupt-on-Change PORTC control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IOCC: Interrupt-on-Change PORTC control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Note 1: x = Bit is unknown Interrupt-on-change requires that the IOCIE bit (INTCON) is set.  2012-2014 Microchip Technology Inc. DS30000684B-page 151 PIC18(L)F2X/45K50 REGISTER 11-15: SLRCON: SLEW RATE CONTROL REGISTER U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — — SLRE(1) SLRD(1) SLRC SLRB SLRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 SLRE: PORTE Slew Rate Control bit(1) 1 = All outputs on PORTE slew at a limited rate 0 = All outputs on PORTE slew at the standard rate bit 3 SLRD: PORTD Slew Rate Control bit(1) 1 = All outputs on PORTD slew at a limited rate 0 = All outputs on PORTD slew at the standard rate bit 2 SLRC: PORTC Slew Rate Control bit 1 = All outputs on PORTC slew at a limited rate 0 = All outputs on PORTC slew at the standard rate bit 1 SLRB: PORTB Slew Rate Control bit 1 = All outputs on PORTB slew at a limited rate 0 = All outputs on PORTB slew at the standard rate bit 0 SLRA: PORTA Slew Rate Control bit 1 = All outputs on PORTA slew at a limited rate(2) 0 = All outputs on PORTA slew at the standard rate Note 1: 2: x = Bit is unknown These bits are available on PIC18(L)F45K50 devices. The slew rate of RA6 defaults to standard rate when the pin is used as CLKO. DS30000684B-page 152  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 12.0 The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable. TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow 12.1 A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1. Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. Register Definitions: Timer0 Control REGISTER 12-1: T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA R/W-1 R/W-1 R/W-1 TOPS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value  2012-2014 Microchip Technology Inc. DS30000684B-page 153 PIC18(L)F2X/45K50 12.2 Timer0 Operation 12.3 Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.4 “Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write. The user can work around this by adjusting the value written to the TMR0 register to compensate for the anticipated missing increments. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE of the T0CON register; clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0 which is neither directly readable nor writable (refer to Figure 12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without the need to verify that the read of the high and low byte were valid. Invalid reads could otherwise occur due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Writing to TMR0H does not directly affect Timer0. Instead, the high byte of Timer0 is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. An external clock source can be used to drive Timer0; however, it must meet certain requirements (see Table 29-22) to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 T0CKI pin T0SE T0CS T0PS PSA Note: Programmable Prescaler 0 Sync with Internal Clocks TMR0L Set TMR0IF on Overflow (2 TCY Delay) 8 3 8 Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS30000684B-page 154  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Internal Clocks 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: 12.4 Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 12.4.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable; its value is set by the PSA and T0PS bits of the T0CON register which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When the prescaler is assigned, prescale values from 1:2 through 1:256 in integer power-of-2 increments are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 12-1: Name INTCON INTCON2 T0CON The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 12.5 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit of the INTCON register. Before re-enabling the interrupt, the TMR0IF bit must be cleared by software in the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE RBPU TMR0ON T08BIT T0CS Timer0 Register, High Byte TMR0L Timer0 Register, Low Byte TRISA7 Bit 4 Bit 3 INT0IE INTEDG0 INTEDG1 INTEDG2 TMR0H TRISA SWITCHING PRESCALER ASSIGNMENT TRISA6 TRISA5 T0SE Bit 0 Register on page INT0IF IOCIF 114 — IOCIP 115 Bit 2 Bit 1 IOCIE TMR0IF — TMR0IP PSA T0PS 153 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0.  2012-2014 Microchip Technology Inc. DS30000684B-page 155 PIC18(L)F2X/45K50 13.0 • • • • • • TIMER1/3 MODULE WITH GATE CONTROL The Timer1/3 module is a 16-bit timer/counter with the following features: • • • • • • • • 16-bit timer/counter register pair (TMRxH:TMRxL) Programmable internal or external clock source 2-bit prescaler Dedicated Secondary 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1/3 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • 16-Bit Read/Write Operation • Time base for the Capture/Compare function FIGURE 13-1: Special Event Trigger (with CCP/ECCP) Selectable Gate Source Polarity Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 13-1 is a block diagram of the Timer1/3 module. TIMER1/3 BLOCK DIAGRAM TxGSS TxG 00 Timer2 Match PR2 01 TxGSPM 0 TxG_IN TxGVAL 0 sync_C1OUT(7) Single Pulse 10 sync_C2OUT(7) D Q CK R Q 11 TMRxON 1 Acq. Control 1 Q1 Data Bus D Q RD TXGCON EN Interrupt TxGGO/DONE Set TMRxGIF det TxGTM TxGPOL TMRxGE Set flag bit TMRxIF on Overflow TMRxON To Comparator Module TMRx(2),(4) TMRxH EN TMRxL Q D TxCLK Synchronized clock input 0 1 Secondary Oscillator Module See Figure 2-4 TMRxCS Reserved 1 (5) ,(6) TxCKI Note TxCLK_EXT_SRC (1) 0 SOSCEN TxSYNC SOSCOUT 11 Synchronize(3),(7) Prescaler 1, 2, 4, 8 det 10 2 TxCKPS FOSC Internal Clock 01 FOSC/4 Internal Clock 00 FOSC/2 Internal Clock Sleep input 1: 2: 3: 4: 5: 6: ST Buffer is high speed type when using TxCKI. Timer1/3 register increments on rising edge. Synchronize does not operate while in Sleep. See Figure 13-2 for 16-Bit Read/Write Mode Block Diagram. T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or SOSCEN = 1) T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1. 7: Synchronized comparator output should not be used in conjunction with synchronized TxCKI. DS30000684B-page 156  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 13.1 13.2.1 Timer1/3 Operation When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3 prescaler. The Timer1/3 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When the FOSC internal clock source is selected, the Timer1/3 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1/3 value. To utilize the full resolution of Timer1/3, an asynchronous input signal must be used to gate the Timer1/3 clock input. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. The following asynchronous sources may be used: Timer1/3 is enabled by configuring the TMRxON and TMRxGE bits in the TxCON and TxGCON registers, respectively. Table 13-1 displays the Timer1/3 enable selections. TABLE 13-1: 13.2.2 0 0 Off 0 1 Off 1 0 Always On 1 1 Count Enabled When enabled to count, Timer1/3 is incremented on the rising edge of the external clock input of the TxCKI pin. This external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit. Clock Source Selection Note: The TMRxCS and SOSCEN bits of the TxCON register are used to select the clock source for Timer1/3. The dedicated secondary oscillator circuit can be used as the clock source for Timer1 and Timer3, simultaneously. Any of the SOSCEN bits will enable the secondary oscillator circuit and select it as the clock source for that particular timer. Table 13-2 displays the clock source selections. TABLE 13-2: EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1/3 module may work as a timer or a counter. Timer1/3 Operation TMRxGE 13.2 • Asynchronous event on the TxG pin to Timer1/3 gate • C1 or C2 comparator input to Timer1/3 gate TIMER1/3 ENABLE SELECTIONS TMRxON INTERNAL CLOCK SOURCE In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • Timer1/3 enabled after POR Write to TMRxH or TMRxL Timer1/3 is disabled Timer1/3 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3 is enabled (TMRxON=1) when TxCKI is low. CLOCK SOURCE SELECTIONS TMRxCS1 TMRxCS0 SOSCEN 0 1 x System Clock (FOSC) 0 0 x Instruction Clock (FOSC/4) 1 0 0 External Clocking on TxCKI Pin 1 0 1 Oscillator Circuit on SOSCI/SOSCO Pins  2012-2014 Microchip Technology Inc. Clock Source DS30000684B-page 157 PIC18(L)F2X/45K50 13.3 Timer1/3 Prescaler Timer1/3 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 13.4 Secondary Oscillator A dedicated secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the SOSCEN bit of the TxCON register, the SOSCGO bit of the OSCCON2 register or by selecting the secondary oscillator as the system clock by setting SCS = 01 in the OSCCON register. The oscillator will continue to run during Sleep. Note: 13.5 The oscillator requires a start-up and stabilization time before use. Thus, SOSCEN should be set and a suitable delay observed prior to enabling Timer1/3. Timer1/3 Operation in Asynchronous Counter Mode If control bit TxSYNC of the TxCON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 13.5.1 “Reading and Writing Timer1/3 in Asynchronous Counter Mode”). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 13.5.1 READING AND WRITING TIMER1/3 IN ASYNCHRONOUS COUNTER MODE Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. 13.6 Timer1/3 16-Bit Read/Write Mode Timer1/3 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit of the TxCON register. To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read and write operations take place through the use of this TMRxH buffer register. When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1/3 value from a single instance in time. In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRxL:TMRxH register pair at the same time. Any requests to write to the TMRxH directly does not clear the Timer1/3 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. DS30000684B-page 158  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 13-2: TIMER1/3 16-BIT READ/WRITE MODE BLOCK DIAGRAM From Timer1/3 Circuitry Set TMR1IF on Overflow TMR1 High Byte TMR1L 8 Read TMR1L Write TMR1L 13.7.2 The Timer1/3 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register. TABLE 13-4: TxGSS 8 8 TMR1H 8 8 Timer1/3 Gate Timer1/3 gate can also be driven by multiple selectable sources. 13.7.1 TIMER1/3 GATE ENABLE The Timer1/3 Gate Enable mode is enabled by setting the TMRxGE bit of the TxGCON register. The polarity of the Timer1/3 Gate Enable mode is configured using the TxGPOL bit of the TxGCON register. When Timer1/3 Gate Enable mode is enabled, Timer1/3 will increment on the rising edge of the Timer1/3 clock source. When Timer1/3 Gate Enable mode is disabled, no incrementing will occur and Timer1/3 will hold the current count. See Figure 13-4 for timing details. TABLE 13-3: TIMER1/3 GATE ENABLE SELECTIONS Timer1/3 Operation TxCLK TxGPOL TxG  0 0 Counts  0 1 Holds Count  1 0 Holds Count  1 1 Counts  2012-2014 Microchip Technology Inc. Timer1/3 Gate Source Timer1/3 Gate Pin (TxG) 01 Timer2 Match to PR2 (TMR2 increments to match PR2) 10 Comparator 1 Output sync_C1OUT (optionally Timer1/3 synchronized output) 11 Comparator 2 Output sync_C2OUT (optionally Timer1/3 synchronized output) 13.7.2.1 Timer1/3 can be configured to count freely or the count can be enabled and disabled using Timer1/3 gate circuitry. This is also referred to as Timer1/3 Gate Enable. TIMER1/3 GATE SOURCES 00 Internal Data Bus 13.7 TIMER1/3 GATE SOURCE SELECTION TxG Pin Gate Operation The TxG pin is one source for Timer1/3 gate control. It can be used to supply an external source to the Timer1/3 gate circuitry. 13.7.2.2 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1/3 gate circuitry. See Section 13.7.2 “Timer1/3 Gate Source Selection” for more information. 13.7.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1/3 gate control. The Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1/3 clock or left asynchronous. For more information see Section 19.8.3 “Synchronizing Comparator Output to Timer1”. 13.7.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1/3 gate control. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1/3 clock or left asynchronous. For more information see Section 19.8.3 “Synchronizing Comparator Output to Timer1”. DS30000684B-page 159 PIC18(L)F2X/45K50 13.7.3 TIMER1/3 GATE TOGGLE MODE When Timer1/3 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1/3 gate signal, as opposed to the duration of a single level pulse. The Timer1/3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-5 for timing details. Timer1/3 Gate Toggle mode is enabled by setting the TxGTM bit of the TxGCON register. When the TxGTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. 13.7.4 TIMER1/3 GATE SINGLE-PULSE MODE When Timer1/3 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1/3 Gate Single-Pulse mode is first enabled by setting the TxGSPM bit in the TxGCON register. Next, the TxGGO/DONE bit in the TxGCON register must be set. The Timer1/3 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the TxGGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1/3 until the TxGGO/DONE bit is once again set in software. Clearing the TxGSPM bit of the TxGCON register will also clear the TxGGO/DONE bit. See Figure 13-6 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1/3 gate source to be measured. See Figure 13-7 for timing details. 13.7.5 TIMER1/3 GATE VALUE STATUS When Timer1/3 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the TxGVAL bit in the TxGCON register. The TxGVAL bit is valid even when the Timer1/3 gate is not enabled (TMRxGE bit is cleared). 13.7.6 TIMER1/3 GATE EVENT INTERRUPT When Timer1/3 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIR3 register will be set. If the TMRxGIE bit in the PIE3 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1/3 gate is not enabled (TMRxGE bit is cleared). For more information on selecting high or low priority status for the Timer1/3 Gate Event Interrupt see Section 10.0 “Interrupts”. DS30000684B-page 160  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 13.8 Timer1/3 Interrupt The Timer1/3 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1/3 rolls over, the Timer1/3 interrupt flag bit of the PIR1/2 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMRxON bit of the TxCON register TMRxIE bits of the PIE1 or PIE2 registers PEIE/GIEL bit of the INTCON register GIE/GIEH bit of the INTCON register The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. For more information on selecting high or low priority status for the Timer1/3 Overflow Interrupt, see Section 10.0 “Interrupts”. The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling interrupts. Note: 13.9 Timer1/3 Operation During Sleep Timer1/3 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • TMRxON bit of the TxCON register must be set TMRxIE bit of the PIE1/2 register must be set PEIE/GIEL bit of the INTCON register must be set TxSYNC bit of the TxCON register must be set TMRxCS bits of the TxCON register must be configured • SOSCEN bit of the TxCON register must be configured The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register is set, the device will call the Interrupt Service Routine. FIGURE 13-3: The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. 13.10 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value CCPRxH:CCPRxL register pair matches the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 15.0 13.11 ECCP/CCP Special Event Trigger When any of the CCP’s are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1/3 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1/3. Timer1/3 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1/3 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 18.2.8 “Special Event Trigger”. TIMER1/3 INCREMENTING EDGE TXCKI = 1 when TMRx Enabled TXCKI = 0 when TMRX Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2012-2014 Microchip Technology Inc. DS30000684B-page 161 PIC18(L)F2X/45K50 FIGURE 13-4: TIMER1/3 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3 N FIGURE 13-5: N+1 N+2 N+3 N+4 TIMER1/3 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL Timer1/3 N DS30000684B-page 162 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 13-6: TIMER1/3 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3 TMRxGIF N Cleared by software  2012-2014 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software DS30000684B-page 163 PIC18(L)F2X/45K50 FIGURE 13-7: TIMER1/3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL Timer1/3 TMRxGIF N N+1 Cleared by software N+2 N+3 Set by hardware on falling edge of TxGVAL N+4 Cleared by software 13.12 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD) and Timer3 (TMR3MD) are in the PMD0 Register. See Section 4.0 “Power-Managed Modes” for more information. DS30000684B-page 164  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 13.13 Register Definitions: Timer1/3 Control REGISTER 13-1: R/W-0/u TxCON: TIMER1/3 CONTROL REGISTER R/W-0/u R/W-0/u TMRxCS R/W-0/u TxCKPS R/W-0/u R/W-0/u R/W-0/0 R/W-0/u SOSCEN TxSYNC RD16 TMRxON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMRxCS: Timer1/3 Clock Source Select bits 11 = Reserved. Do not use. 10 = Timer1/3 clock source is pin or oscillator: If SOSCEN = 0: External clock from TxCKI pin (on the rising edge) If SOSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 = Timer1/3 clock source is system clock (FOSC) 00 = Timer1/3 clock source is instruction clock (FOSC/4) bit 5-4 TxCKPS: Timer1/3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 SOSCEN: Secondary Oscillator Enable Control bit 1 = Dedicated secondary oscillator circuit enabled 0 = Dedicated secondary oscillator circuit disabled bit 2 TxSYNC: Timer1/3 External Clock Input Synchronization Control bit TMRxCS = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMRxCS = 0X This bit is ignored. Timer1/3 uses the internal clock when TMRxCS = 0X. bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1/3 in one 16-bit operation 0 = Enables register read/write of Timer1/3 in two 8-bit operation bit 0 TMRxON: Timer1/3 On bit 1 = Enables Timer1/3 0 = Stops Timer1/3 Clears Timer1/3 Gate flip-flop  2012-2014 Microchip Technology Inc. DS30000684B-page 165 PIC18(L)F2X/45K50 REGISTER 13-2: TxGCON: TIMER1/3 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL R/W-0/u R/W-0/u TxGSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3 Gate Enable bit If TMRxON = 0: This bit is ignored If TMRxON = 1: 1 = Timer1/3 counting is controlled by the Timer1/3 gate function 0 = Timer1/3 counts regardless of Timer1/3 gate function bit 6 TxGPOL: Timer1/3 Gate Polarity bit 1 = Timer1/3 gate is active-high (Timer1/3 counts when gate is high) 0 = Timer1/3 gate is active-low (Timer1/3 counts when gate is low) bit 5 TxGTM: Timer1/3 Gate Toggle Mode bit 1 = Timer1/3 Gate Toggle mode is enabled 0 = Timer1/3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1/3 gate flip-flop toggles on every rising edge. bit 4 TxGSPM: Timer1/3 Gate Single-Pulse Mode bit 1 = Timer1/3 gate Single-Pulse mode is enabled and is controlling Timer1/3 gate 0 = Timer1/3 gate Single-Pulse mode is disabled bit 3 TxGGO/DONE: Timer1/3 Gate Single-Pulse Acquisition Status bit 1 = Timer1/3 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1/3 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared. bit 2 TxGVAL: Timer1/3 Gate Current State bit Indicates the current state of the Timer1/3 gate that could be provided to TMRxH:TMRxL. Unaffected by Timer1/3 Gate Enable (TMRxGE). bit 1-0 TxGSS: Timer1/3 Gate Source Select bits 00 = Timer1/3 Gate pin 01 = Timer2 Match PR2 output 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT) DS30000684B-page 166  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 13-5: Name REGISTERS ASSOCIATED WITH TIMER1/3 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 148 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 125 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 122 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 T1CON TMR1CS SOSCEN T1SYNC RD16 TMR1ON 165 T1GGO/DONE T1GVAL SOSCEN T3SYNC T3GGO/DONE T3GVAL T1GCON TMR1GE T3CON T3GCON T1GPOL T1CKPS T1GTM TMR3CS TMR3GE T3GPOL T1GSPM T3CKPS T3GTM TMRxH Timer1/3 Register, High Byte TMRxL Timer1/3 Register, Low Byte T3GSPM T1GSS RD16 TMR3ON T3GSS 166 165 166 — — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TABLE 13-6: CONFIGURATION REGISTERS ASSOCIATED WITH TIMER1/3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376  2012-2014 Microchip Technology Inc. DS30000684B-page 167 PIC18(L)F2X/45K50 14.0 TIMER2 MODULE The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module See Figure 14-1 for a block diagram of Timer2. FIGURE 14-1: TIMER2 BLOCK DIAGRAM TMRx Output FOSC/4 Prescaler 1:1, 1:4, 1:16 2 TMRx Comparator Sets Flag bit TMRxIF Reset EQ Postscaler 1:1 to 1:16 TxCKPS PRx 4 TxOUTPS DS30000684B-page 168  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 14.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 14.2 “Timer2 Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: TMR2 is not cleared when T2CON is written.  2012-2014 Microchip Technology Inc. 14.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. Interrupt Priority is selected with the TMR2IP bit in the IPR1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS, of the T2CON register. 14.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode by setting SSPM = 0011 in the SSPxCON1 register. Additional information is provided in Section 16.0 “Master Synchronous Serial Port (MSSP) Module”. 14.4 Timer2 Operation During Sleep The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode. 14.5 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bit for Timer2 (TMR2MD) is in the PMD0 register. See Section 4.0 “Power-Managed Modes” for more information. DS30000684B-page 169 PIC18(L)F2X/45K50 14.6 Register Definitions: Timer2 Control REGISTER 14-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0 — R/W-0 R/W-0 R/W-0 T2OUTPS R/W-0 R/W-0 TMR2ON bit 7 R/W-0 T2CKPS bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS: Timer2-type Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 DS30000684B-page 170  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 14-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 — UARTMD USBMD ACTMD — TMR1MD 61 PMD0 PR2 T2CON TMR2 GIE/GIEH PEIE/GIEL Bit 5 TMR3MD TMR2MD Timer2 Period Register — — T2OUTPS TMR2ON T2CKPS Timer2 Register 165 — Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer2.  2012-2014 Microchip Technology Inc. DS30000684B-page 171 PIC18(L)F2X/45K50 15.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains one Enhanced Capture/ Compare/PWM module (ECCP1) and one standard Capture/Compare/PWM module (CCP2). The Capture and Compare functions are identical for the CCP/ECCP modules. The difference between CCP and ECCP modules are in the Pulse-Width Modulation (PWM) function. In CCP modules, the standard PWM function is identical. In ECCP modules, the Enhanced PWM function has either full-bridge or half-bridge PWM output. Full-bridge ECCP modules have four available I/O pins while half-bridge ECCP modules only have two available I/O pins. ECCP PWM modules are backward compatible with CCP PWM modules and can be configured as standard PWM modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to ECCP1 and CCP2. Register names, module signals, I/O pins and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. DS30000684B-page 172 15.1 Capture Mode The Capture mode function described in this section is identical for all CCP and ECCP modules available on this device family. Capture mode makes use of the 16-bit Timer resources, Timer1 and Timer3. The timer resources for each CCP capture function are independent and are selected using the CCPTMRS register. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMRxH:TMRxL register pair, respectively. An event is defined as one of the following and is configured by the CCPxM bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the corresponding Interrupt Request Flag bit CCPxIF of the PIR1 and PIR2 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH:CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 15-1 shows a simplified diagram of the Capture operation. FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Prescaler  1, 4, 16 Set Flag bit CCPxIF (PIRx register) CCPx pin CCPRxH and Edge Detect CCPRxL Capture Enable TMRxH TMRxL CCPxM System Clock (FOSC)  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Some CCPx outputs are multiplexed on a couple of pins. Table 15-1 shows the CCP output pin multiplexing. Selection of the output pin is determined by the CCPxMX bits in Configuration register 3H (CONFIG3H). Refer to Register 26-5 for more details. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. TABLE 15-1: CCP PIN MULTIPLEXING CCP OUTPUT CONFIG 3H Control Bit CCP2 CCP2MX Bit Value I/O pin 0 RB3 1(*) RC1 Legend: * = Default 15.1.2 TIMER1 MODE RESOURCE The 16-bit Timer resource must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 13.0 “Timer1/3 Module with Gate Control” for more information on configuring the 16-bit Timers. 15.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: Clocking the 16-bit Timer resource from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, the Timer resource must be clocked from the instruction clock (FOSC/4) or from an external clock source.  2012-2014 Microchip Technology Inc. DS30000684B-page 173 PIC18(L)F2X/45K50 15.1.4 CCP PRESCALER There are four prescaler settings specified by the CCPxM bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 15-1 demonstrates the code to perform this function. EXAMPLE 15-1: CAPTURE DURING SLEEP Capture mode requires a 16-bit TimerX module for use as a time base. There are four options for driving the 16-bit TimerX module in Capture mode. It can be driven by the system clock (FOSC), the instruction clock (FOSC/ 4), or by the external clock sources, the Secondary Oscillator (SOSC), or the TxCKI clock input. When the 16-bit TimerX resource is clocked by FOSC or FOSC/4, TimerX will not increment during Sleep. When the device wakes from Sleep, TimerX will continue from its previous state. Capture mode will operate during Sleep when the 16-bit TimerX resource is clocked by one of the external clock sources (SOSC or the TxCKI pin). CHANGING BETWEEN CAPTURE PRESCALERS #define NEW_CAPT_PS 0x06 ... CCPxCON = 0; CCPxCON = NEW_CAPT_PS; DS30000684B-page 174 15.1.5 //Capture // Prescale 4th // rising edge // Turn the CCP // Module Off // Turn CCP module // on with new // prescale value  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 15-2: Name REGISTERS ASSOCIATED WITH CAPTURE Bit 7 CCP1CON Bit 6 Bit 5 P1M CCP2CON — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DC1B CCP1M 197 DC2B CCP2M 197 CCPR1H Capture/Compare/PWM Register 1, High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1, Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2, High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2, Low Byte (LSB) — — — — — C2TSEL — — C1TSEL GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 SOSCEN T1SYNC RD16 TMR1ON 165 CCPTMRS INTCON T1CON TMR1CS T1GCON TMR1GE T3CON T1GPOL T1CKPS T1GTM TMR3CS T3GCON TMR3GE T3GPOL T1GSPM T3CKPS T3GTM T3GSPM T1GGO/DONE T1GVAL SOSCEN T3SYNC T3GGO/DONE T3GVAL T1GSS RD16 TMR3ON T3GSS 200 166 165 166 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. TABLE 15-3: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 175 PIC18(L)F2X/45K50 15.2 15.2.1 Compare Mode The Compare mode function described in this section is identical for all CCP and ECCP modules available on this device family. Compare mode makes use of the 16-bit Timer resources, Timer1 and Timer3. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair. When a match occurs, one of the following events can occur: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt All Compare modes can generate an interrupt. Figure 15-2 shows a simplified diagram of the Compare operation. FIGURE 15-2: The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Some CCPx outputs are multiplexed on a couple of pins. Table 15-1 shows the CCP output pin multiplexing. Selection of the output pin is determined by the CCPxMX bits in Configuration register 3H (CONFIG3H). Refer to Register 26-5 for more details. Note: 15.2.2 The action on the pin is based on the value of the CCPxM control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. Q S R Output Logic Comparator Match TRIS Output Enable TMRxH TimerX MODE RESOURCE See Section 13.0 “Timer1/3 Module with Gate Control” for more information on configuring the 16-bit TimerX resources. Note: CCPxM Mode Select CCPx Pin Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. In Compare mode, 16-bit TimerX resource must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. COMPARE MODE OPERATION BLOCK DIAGRAM Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL CCP PIN CONFIGURATION 15.2.3 Clocking TimerX from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TimerX must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCPxM = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). TMRxL Special Event Trigger Special Event Trigger function on • ECCP1 and CCP2 will: - Reset TimerX – TMRxH:TMRxL = 0x0000 - TimerX Interrupt Flag, (TMRxIF) is not set Additional Function on • CCP2 will - Set ADCON0, GO/DONE bit to start an ADC Conversion if ADCON, ADON = 1, and if ADCON1, TRIGSEL = 0. DS30000684B-page 176  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.2.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is selected (CCPxM = 1011), and a match of the TMRxH:TMRxL and the CCPRxH:CCPRxL registers occurs, all CCPx and ECCPx modules will immediately: 15.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. • Set the CCP interrupt flag bit – CCPxIF • CCP2 will start an ADC conversion, if the ADC is enabled and TRIGSEL is configured for CCP2. On the next TimerX rising clock edge: • A Reset of TimerX register pair occurs – TMRxH:TMRxL = 0x0000, This Special Event Trigger mode does not: • Assert control over the CCPx or ECCPx pins. • Set the TMRxIF interrupt bit when the TMRxH:TMRxL register pair is reset. (TMRxIF gets set on a TimerX overflow.) If the value of the CCPRxH:CCPRxL registers are modified when a match occurs, the user should be aware that the automatic reset of TimerX occurs on the next rising edge of the clock. Therefore, modifying the CCPRxH:CCPRxL registers before this reset occurs will allow the TimerX to continue without being reset, inadvertently resulting in the next event being advanced or delayed. The Special Event Trigger mode allows the CCPRxH:CCPRxL register pair to effectively provide a 16-bit programmable period register for TimerX.  2012-2014 Microchip Technology Inc. DS30000684B-page 177 PIC18(L)F2X/45K50 TABLE 15-4: REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 CCP1CON Bit 6 Bit 5 P1M CCP2CON — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DC1B CCP1M 197 DC2B CCP2M 197 CCPR1H Capture/Compare/PWM Register 1, High Byte (MSB) — CCPR1L Capture/Compare/PWM Register 1, Low Byte (LSB) — CCPR2H Capture/Compare/PWM Register 2, High Byte (MSB) — CCPR2L Capture/Compare/PWM Register 2, Low Byte (LSB) — — — — — ADCON1 TRIGSEL — — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 CCPTMRS C2TSEL — — PVCFG C1TSEL NVCFG 200 295 114 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 RD16 TMR1ON 165 T1CON TMR1CS T1GCON TMR1GE T3CON T1CKPS T1GTM TMR3CS T3GCON TMR1H T1GPOL TMR3GE T3GPOL T1GSPM T3CKPS T3GTM T3GSPM SOSCEN T1SYNC T1GGO/DONE T1GVAL SOSCEN T3SYNC T3GGO/DONE T3GVAL T1GSS RD16 TMR3ON T3GSS 166 165 166 Holding Register for the Most Significant Byte of the 16-bit TMR1 Register — TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register — TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register — TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. TABLE 15-5: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. DS30000684B-page 178  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. FIGURE 15-3: Period Pulse Width TMR2 = 0 FIGURE 15-4: CCPRxH(2) (Slave) CCPx TMR2 Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2: Clearing the CCPxCON register will relinquish control of the CCPx pin.  2012-2014 Microchip Technology Inc. (1) Q S TRIS Comparator PR2 Note 1: The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: Figure 15-4 shows a simplified block diagram of PWM operation. R Comparator STANDARD PWM OPERATION PR2 register T2CON register CCPRxL registers CCPxCON registers CCPxCON CCPRxL Figure 15-3 shows a typical waveform of the PWM signal. • • • • SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The standard PWM function described in this section is available and identical for CCP and ECCP modules. TMR2 = PR2 TMR2 = CCPRxH:CCPxCON PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. 15.3.1 CCP PWM OUTPUT SIGNAL 2: 15.3.2 Clear Timer, toggle CCPx pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPRxH is a read-only register. SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. Disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register for Timer2 with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxB bits of the CCPxCON register, with the PWM duty cycle value. DS30000684B-page 179 PIC18(L)F2X/45K50 5. 6. Configure and start the 8-bit Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note 1 below. • Configure the T2CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note 1 below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 5 may be ignored. 15.3.3 PWM PERIOD The PWM period is specified by the PR2 register of 8-bit Timer2. The PWM period can be calculated using the formula of Equation 15-1. EQUATION 15-1: PWM PERIOD PWM Period =   PR2  + 1   4  T OSC  (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: 15.3.4 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 15-2 is used to calculate the PWM pulse width. Equation 15-3 is used to calculate the PWM duty cycle ratio. EQUATION 15-2: PULSE WIDTH Pulse Width =  CCPRxL:CCPxCON   T OSC  (TMR2 Prescale Value) EQUATION 15-3: DUTY CYCLE RATIO  CCPRxL:CCPxCON  Duty Cycle Ratio = ----------------------------------------------------------------------4  PR2 + 1  The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 15-4). The Timer postscaler (see Section 14.0 “Timer2 Module”) is not used in the determination of the PWM frequency. DS30000684B-page 180  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.3.5 PWM RESOLUTION EQUATION 15-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 15-4. TABLE 15-6: 1.95 kHz Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits) PR2 Value Maximum Resolution (bits) 7.81 kHz 31.25 kHz 125 kHz 250 kHz 333.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits) 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 15.3.7 If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. 0xFF 1.22 kHz Timer Prescale (1, 4, 16) 15.3.6 Note: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency TABLE 15-8: log  4  PR2 + 1   Resolution = ------------------------------------------ bits log  2  EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz) PWM Frequency TABLE 15-7: PWM RESOLUTION 15.3.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 3.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details.  2012-2014 Microchip Technology Inc. DS30000684B-page 181 PIC18(L)F2X/45K50 TABLE 15-9: Name REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 CCP1CON Bit 6 Bit 5 P1M Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page DC1B CCP1M 197 DC2B CCP2M 197 CCP2CON — — CCPTMRS — — — — C2TSEL — — C1TSEL 200 GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 INTCON PR2 T2CON TMR2 Timer2 Period Register — — T2OUTPS TMR2ON T2CKPS Timer2 Period Register 170 — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. TABLE 15-10: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. DS30000684B-page 182  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.4 To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. PWM (Enhanced Mode) The enhanced PWM function described in this section is available for CCP module ECCP1. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to four different output pins with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • Figure 15-5 shows an example of a simplified block diagram of the Enhanced PWM module. PR2 register T2CON register CCPRxL registers CCPxCON registers Table 15-11 shows the pin assignments for various Enhanced PWM modes. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. The ECCP modules have the following additional PWM registers which control Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering modes: 2: Clearing the CCPxCON register will relinquish control of the CCPx pin. • ECCPxAS registers • PSTRxCON registers • PWMxCON registers 3: Any pin not used in the enhanced PWM mode is available for alternate pin functions, if applicable. The enhanced PWM module can generate the following five PWM Output modes: • • • • • 4: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. Single PWM Half-Bridge PWM Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode Single PWM with PWM Steering mode FIGURE 15-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers DCxB CCPxM 4 PxM 2 CCPRxL CCPx/PxA CCPx/PxA TRISx CCPRxH (Slave) PxB R Comparator Q Output Controller PxB TRISx PxC TMR2 Comparator PR2 Note (1) PxC(2) TRISx S PxD Clear Timer, toggle PWM pin and latch duty cycle PxD(2) TRISx PWMxCON 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or two bits of the prescaler to create the 10-bit time base. 2: PxC and PxD are not available on half-bridge ECCP modules.  2012-2014 Microchip Technology Inc. DS30000684B-page 183 PIC18(L)F2X/45K50 TABLE 15-11: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM CCPx/PxA Yes PxC (1) Yes PxD (1) Yes(1) Single 00 Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Yes PxB (1) PWM Steering enables outputs in Single mode. FIGURE 15-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) PxM Signal PRX+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated Delay(1) Delay(1) PxA Modulated 10 (Half-Bridge) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 15.4.5 “Programmable Dead-Band Delay Mode”). DS30000684B-page 184  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 15-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal PxM PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMRx Prescale Value) • Delay = 4 * TOSC * (PWMxCON) Note 1: Dead-band delay is programmed using the PWMxCON register (Section 15.4.5 “Programmable Dead-Band Delay Mode”).  2012-2014 Microchip Technology Inc. DS30000684B-page 185 PIC18(L)F2X/45K50 15.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 15-9). This mode can be used for half-bridge applications, as shown in Figure 15-9, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in halfbridge power devices. The value of the PDC bits of the PWMxCON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 15.4.5 “Programmable Dead-Band Delay Mode” for more details of the dead-band delay operations. Since the PxA and PxB outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs. FIGURE 15-8: Period Period Pulse Width PxA(2) td td PxB(2) (1) (1) (1) td = Dead-Band Delay Note 1: 2: FIGURE 15-9: EXAMPLE OF HALFBRIDGE PWM OUTPUT At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + PxA Load FET Driver + PxB - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver FET Driver PxA FET Driver Load FET Driver PxB DS30000684B-page 186  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of full-bridge application is shown in Figure 15-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 15-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 15-11. PxA, PxB, PxC and PxD outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 15-10: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver PxA Load PxB FET Driver PxC FET Driver QD QB VPxD  2012-2014 Microchip Technology Inc. DS30000684B-page 187 PIC18(L)F2X/45K50 FIGURE 15-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. DS30000684B-page 188  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs four Timer cycles prior to the end of the current PWM period: • The modulated outputs (PxB and PxD) are placed in their inactive state. • The associated unmodulated outputs (PxA and PxC) are switched to drive in the opposite direction. • PWM modulation resumes at the beginning of the next period. See Figure 15-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn off time of the power switch, including the power device and driver circuit, is greater than the turn on time. Figure 15-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output PxA and PxD become inactive, while output PxC becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 15-10) for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 15-12: EXAMPLE OF PWM DIRECTION CHANGE Period(1) Signal Period PxA (Active-High) PxB (Active-High) Pulse Width PxC (Active-High) (2) PxD (Active-High) Pulse Width Note 1: 2: The direction bit PxM1 of the CCPxCON register is written any time during the PWM cycle. When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is (Timer2 Prescale)/FOSC.  2012-2014 Microchip Technology Inc. DS30000684B-page 189 PIC18(L)F2X/45K50 FIGURE 15-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 15.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver. ENHANCED PWM AUTOSHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPxAS register. A shutdown event may be generated by: • A logic ‘0’ on the FLTx pin • Comparator Cx (async_CxOUT) • Setting the ECCPxASE bit in firmware A shutdown condition is indicated by the ECCPxASE (Auto-Shutdown Event Status) bit of the ECCPxAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. of each pin pair is determined by the PSSxAC and PSSxBD bits of the ECCPxAS register. Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period. When a shutdown event occurs, two things happen: The ECCPxASE bit is set to ‘1’. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs (see Section 15.4.4 “Auto-Restart Mode”). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state DS30000684B-page 190  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 15-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (ECCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event ECCPxASE bit Shutdown Event Occurs 15.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the autoshutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register. FIGURE 15-15: Shutdown Event Clears PWM Resumes ECCPxASE Cleared by Firmware If auto-restart is enabled, the ECCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPxASE bit will be cleared via hardware and normal operation will resume. PWM AUTO-SHUTDOWN WITH AUTO-RESTART (PXRSEN = 1) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (ECCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event ECCPxASE bit PWM Resumes Shutdown Event Occurs Shutdown Event Clears  2012-2014 Microchip Technology Inc. ECCPxASE Cleared by Hardware DS30000684B-page 191 PIC18(L)F2X/45K50 15.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 15-16: In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shootthrough current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. Period Period Pulse Width PxA(2) td td PxB(2) (1) (1) (1) td = Dead-Band Delay Note 1: In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 15-16 for illustration. The lower seven bits of the associated PWMxCON register (Register 15-5) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). FIGURE 15-17: EXAMPLE OF HALFBRIDGE PWM OUTPUT 2: At this time, the TMRx register is equal to the PRx register. Output signals are shown as active-high. EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver + V - PxA Load FET Driver + V - PxB V- DS30000684B-page 192  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.4.6 PWM STEERING MODE In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCPxM = 11 and PxM = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate Steering Enable bits (STRxA, STRxB, STRxC and/or STRxD) of the PSTRxCON register, as shown in Table 15-12. Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCPxM bits of the CCPxCON register select the PWM output polarity for the PxD, PxC, PxB and PxA pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section 15.4.3 “Enhanced PWM Auto-Shutdown Mode”. An autoshutdown event will only affect pins that have PWM outputs enabled. FIGURE 15-18: SIMPLIFIED STEERING BLOCK DIAGRAM STRxA PxA Signal CCPxM1 1 PORT Data 0 PxA pin STRxB CCPxM0 1 PORT Data 0 STRxC CCPxM1 1 PORT Data 0 PORT Data PxB pin TRIS PxC pin TRIS STRxD CCPxM0 TRIS PxD pin 1 0 TRIS Note 1: Port outputs are configured as shown when the CCPxCON register bits PxM = 00 and CCPxM = 11. 2: Single PWM output requires setting at least one of the STRx bits. 15.4.6.1 Steering Synchronization The STRxSYNC bit of the PSTRxCON register gives the user two selections of when the steering event will happen. When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the PxA, PxB, PxC and PxD pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRxSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 15-19 and 15-20 illustrate the timing diagrams of the PWM steering depending on the STRxSYNC setting.  2012-2014 Microchip Technology Inc. DS30000684B-page 193 PIC18(L)F2X/45K50 15.4.7 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCPxM bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is not recommended since it may result in damage to the application circuits. modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM FIGURE 15-19: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRxSYNC = 0) PWM Period PWM STRx P1 PORT Data PORT Data P1n = PWM FIGURE 15-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRxSYNC = 1) PWM STRx P1 PORT Data PORT Data P1n = PWM DS30000684B-page 194  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.4.8 SETUP FOR ECCP PWM OPERATION USING ECCP1 AND TIMER2 The following steps should be taken when configuring the ECCP1 module for PWM operation using Timer2: 1. 2. 3. 4. 5. 6. 7. 8. Configure the PWM pins to be used (P1A, P1B, P1C, and P1D): • Configure PWM outputs to be used as inputs by setting the corresponding TRIS bits. This prevents spurious outputs during setup. • Set the PSTR1CON bits for each PWM output to be used. Set the PWM period by loading the PR2 register. Configure auto-shutdown as OFF or select the source with the CCP1AS bits of the ECCP1AS register. Configure the auto-shutdown sources as needed: • Configure each comparator used. • Configure the comparator inputs as analog. • Configure the FLT0 input pin and clear ANSB0. Force a shutdown condition (OFF included): • Configure safe starting output levels by setting the default shutdown drive states with the PSS1AC and PSS1BD bits of the ECCP1AS register. • Clear the P1RSEN bit of the PWM1CON register. • Set the CCP1AS bit of the ECCP1AS register. Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: • Select one of the available output configurations and direction with the P1M bits. • Select the polarities of the PWM output signals with the CCP1M bits. Set the 10-bit PWM duty cycle: • Load the eight MS bits into the CCPR1L register. • Load the two LS bits into the DC bits of the CCP1CON register. For Half-Bridge Output mode, set the deadband delay by loading P1DC bits of the PWM1CON register with the appropriate value.  2012-2014 Microchip Technology Inc. 9. Configure and start TMR2: • Set the TMR2 prescale value by loading the T2CKPS bits of the T2CON register. • Start Timer2 by setting the TMR2ON bit. 10. Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. 11. Start the PWM: • If shutdown auto-restart is used, then set the P1RSEN bit of the PWM1CON register. • If shutdown auto-restart is not used, then clear the CCP1ASE bit of the ECCP1AS register. DS30000684B-page 195 PIC18(L)F2X/45K50 TABLE 15-12: REGISTERS ASSOCIATED WITH ENHANCED PWM Name ECCP1AS Bit 7 ECCP1ASE CCP1CON CCPTMRS Bit 6 Bit 5 Bit 4 ECCP1AS P1M Bit 3 Bit 2 Bit 1 PSS1AC DC1B Bit 0 PSS1BD 201 — 200 CCP1M — — — — C2TSEL — Register on page 197 C1TSEL GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 — STR1SYNC STR1D STR1C STR1B STR1A 202 INTCON PR2 Timer2 Period Register PSTR1CON — PWM1CON P1RSEN T2CON TMR2 — — P1DC — T2OUTPS 202 TMR2ON T2CKPS Timer2 Period Register 170 — TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISC TRISC7 TRISC6 — — TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISB3 TRISB2 TRISB1 TRISB0 149 — TRISC2 TRISC1 TRISC0 149 TRISD3 TRISD2 TRISD1 TRISD0 149 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode. Note 1: These registers/bits are available on PIC18(L)F45K50 devices. DS30000684B-page 196  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 15.5 Register Definitions: ECCP Control REGISTER 15-1: CCPxCON: STANDARD CCPx CONTROL REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 DCxB R/W-0 R/W-0 R/W-0 CCPxM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unused bit 5-4 DCxB: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX (selected by CxTSEL bits) is reset ADON is set, starting A/D conversion if A/D module is enabled and TRIGSEL is clear(1) 11xx =: PWM mode Note 1: This feature is available on CCP2 only.  2012-2014 Microchip Technology Inc. DS30000684B-page 197 PIC18(L)F2X/45K50 REGISTER 15-2: R/x-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER R/W-0 PxM R/W-0 R/W-0 DCxB R/W-0 R/W-0 R/W-0 R/W-0 CCPxM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM: Enhanced PWM Output Configuration bits If CCPxM = 00, 01, 10: (Capture/Compare modes) xx = PxA assigned as Capture/Compare input; PxB, PxC, PxD assigned as port pins Half-Bridge ECCP Modules(1): If CCPxM = 11: (PWM modes) 0x = Single output; PxA modulated; PxB assigned as port pin 1x = Half-bridge output; PxA, PxB modulated with dead-band control Full-Bridge ECCP Modules(1): If CCPxM = 11: (PWM modes) 00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward; PxD modulated; PxA active; PxB, PxC inactive 10 = Half-bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins 11 = Full-bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive bit 5-4 Note 1: DCxB: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. See Table 15-1 to determine full-bridge and half-bridge ECCPs for the device being used. DS30000684B-page 198  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 15-2: bit 3-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER (CONTINUED) CCPxM: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set) 1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected, CCPxIF is set) 1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set) TimerX is reset Half-Bridge ECCP Modules(1): 1100 = PWM mode: PxA active-high; PxB active-high 1101 = PWM mode: PxA active-high; PxB active-low 1110 = PWM mode: PxA active-low; PxB active-high 1111 = PWM mode: PxA active-low; PxB active-low Full-Bridge ECCP Modules(1): 1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low Note 1: See Table 15-1 to determine full-bridge and half-bridge ECCPs for the device being used.  2012-2014 Microchip Technology Inc. DS30000684B-page 199 PIC18(L)F2X/45K50 REGISTER 15-3: CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 — — — — C2TSEL — — C1TSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 C2TSEL: CCP2 Timer Selection bit 0 = CCP2 – Capture/Compare modes use TMR1, PWM modes use TMR2 1 = CCP2 – Capture/Compare modes use TMR3, PWM modes use TMR2 bit 2-1 Unimplemented: Read as ‘0’ bit 0 C1TSEL: ECCP1 Timer Selection bit 0 = ECCP1 – Capture/Compare modes use TMR1, PWM modes use TMR2 1 = ECCP1 – Capture/Compare modes use TMR3, PWM modes use TMR2 DS30000684B-page 200  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 15-4: R/W-0 ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 ECCPxASE R/W-0 R/W-0 ECCPxAS R/W-0 R/W-0 R/W-0 PSSxAC R/W-0 PSSxBD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ECCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event occurred; ECCPxASE bit will automatically clear when event goes away; CCPx outputs in shutdown state 0 = CCPx outputs are operating if PxRSEN = 0; 1 = An Auto-shutdown event occurred; bit must be cleared in software to restart PWM; CCPx outputs in shutdown state 0 = CCPx outputs are operating bit 6-4 ECCPxAS: CCPx Auto-Shutdown Source Select bits (1) 000 = Auto-shutdown is disabled 001 = Comparator C1 (async_C1OUT) – output high will cause shutdown event 010 = Comparator C2 (async_C2OUT) – output high will cause shutdown event 011 = Either Comparator C1 or C2 – output high will cause shutdown event 100 = FLT0 pin - low level will cause shutdown event 101 = FLT0 pin or Comparator C1 (async_C1OUT) – low level will cause shutdown event 110 = FLT0 pin or Comparator C2 (async_C2OUT) – low level will cause shutdown event 111 = FLT0 pin or Comparators C1 or C2 – low level will cause shutdown event bit 3-2 PSSxAC: Pins PxA and PxC Shutdown State Control bits 00 = Drive pins PxA and PxC to ‘0’ 01 = Drive pins PxA and PxC to ‘1’ 1x = Pins PxA and PxC tri-state bit 1-0 PSSxBD: Pins PxB and PxD Shutdown State Control bits 00 = Drive pins PxB and PxD to ‘0’ 01 = Drive pins PxB and PxD to ‘1’ 1x = Pins PxB and PxD tri-state Note 1: If C1SYNC or C2SYNC bits in the CM2CON1 register are enabled, the shutdown will be delayed by Timer1.  2012-2014 Microchip Technology Inc. DS30000684B-page 201 PIC18(L)F2X/45K50 REGISTER 15-5: R/W-0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PxRSEN R/W-0 R/W-0 R/W-0 R/W-0 PxDC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared in software to restart the PWM bit 6-0 PxDC: PWM Delay Count bits PxDCx = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active PSTRxCON: PWM STEERING CONTROL REGISTER(1) REGISTER 15-6: U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 — — — STRxSYNC STRxD STRxC STRxB STRxA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 STRxSYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary bit 3 STRxD: Steering Enable bit D 1 = PxD pin has the PWM waveform with polarity control from CCPxM 0 = PxD pin is assigned to port pin bit 2 STRxC: Steering Enable bit C 1 = PxC pin has the PWM waveform with polarity control from CCPxM 0 = PxC pin is assigned to port pin bit 1 STRxB: Steering Enable bit B 1 = PxB pin has the PWM waveform with polarity control from CCPxM 0 = PxB pin is assigned to port pin bit 0 STRxA: Steering Enable bit A 1 = PxA pin has the PWM waveform with polarity control from CCPxM 0 = PxA pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCPxCON register bits CCPxM = 11 and PxM = 00. DS30000684B-page 202  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.0 16.1 The SPI interface supports the following modes and features: MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE • • • • • Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy chain connection of slave devices Figure 16-1 is a block diagram of the SPI interface module. • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) FIGURE 16-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDI SSPxSR Reg SDO bit 0 SS SS Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPxM 4 SCK Edge Select TRIS bit  2012-2014 Microchip Technology Inc. ( TMR22Output ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) DS30000684B-page 203 PIC18(L)F2X/45K50 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection Figure 16-2 is a block diagram of the I2C interface module in Master mode. Figure 16-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C™ MASTER MODE) Internal Data Bus Read [SSPxM 3:0] Write SSPxBUF Baud Rate Generator (SSPxADD) SDA Shift Clock SDA in Receive Enable (RCEN) SCL SCL in Bus Collision DS30000684B-page 204 LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Start bit Detect, Stop bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV Address Match Detect Clock Cntl SSPxSR MSb (Hold off clock source) FIGURE 16-2: General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Clock Arbitrate/BCOL Detect • • • • • • • • • • • • • Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSPIF, BCLIF  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 16-3: MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCL Shift Clock SSPxSR Reg SDA MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect  2012-2014 Microchip Technology Inc. Set, Reset S, P bits (SSPxSTAT Reg) DS30000684B-page 205 PIC18(L)F2X/45K50 16.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 16-1 shows the block diagram of the MSSP module when operating in SPI Mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 16-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. register and the master device is reading this bit from that same line and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Master sends useful data and slave sends dummy data. • Master sends useful data and slave sends useful data. • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure 16-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that at the same time, the slave device is sending out the MSb from its shift DS30000684B-page 206  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 16-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SCLK SPI Master SCLK SDO SDI SDI SDO General I/O General I/O SS General I/O SCLK SDI SDO SPI Slave #1 SPI Slave #2 SS SCLK SDI SDO SPI Slave #3 SS 16.2.1 SPI MODE REGISTERS 16.2.2 SPI MODE OPERATION The MSSP module has five registers for SPI mode operation. These are: When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1 and SSPxSTAT). These control bits allow the following to be specified: • • • • • • MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPxSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower six bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. • • • • and The The The In one SPI Master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 16.7 “Baud Rate Generator”. SSPxSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPxSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPxSR and SSPxBUF together create a buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR.  2012-2014 Microchip Technology Inc. Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) To enable the serial port, SSPx Enable bit, SSPxEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPxEN bit, re-initialize the SSPxCONx registers and then set the SSPxEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set DS30000684B-page 207 PIC18(L)F2X/45K50 Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. The MSSP consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL of the SSPxCON1 When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. FIGURE 16-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPxM = 00xx = 1010 SPI Slave SSPxM = 010x SDO SDI Serial Input Buffer (SSPx) SDI Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1 DS30000684B-page 208 SDO Serial Clock Slave Select (optional) Shift Register (SSPxSR) MSb LSb SCK SS Processor 2  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 16-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 16-6, Figure 16-8 and Figure 16-9, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 16-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. FIGURE 16-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPxSR to SSPxBUF  2012-2014 Microchip Technology Inc. DS30000684B-page 209 PIC18(L)F2X/45K50 16.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 16.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisychain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisychain feature only requires a single Slave Select line from the master device. Figure 16-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 16.2.5 SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPxCON1 = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPxCON1 = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPxEN bit. DS30000684B-page 210  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 16-7: SPI DAISY-CHAIN CONNECTION SCLK SCLK SPI Master SDO SDI SDI SPI Slave #1 SDO General I/O SS SCLK SDI SPI Slave #2 SDO SS SCLK SDI SPI Slave #3 SDO SS FIGURE 16-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF  2012-2014 Microchip Technology Inc. DS30000684B-page 211 PIC18(L)F2X/45K50 FIGURE 16-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 16-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active DS30000684B-page 212  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 16-1: REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 INTCON Name GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD1 — MSSPMD CMP1MD ADCMD CCP2MD CCP1MD 62 SSP1BUF CTMUMD CMP2MD SSP1 Receive Buffer/Transmit Register — SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SSP1STAT SSPM SDAHT SBCDE AHEN 252 DHEN 255 251 SMP CKE D/A P S R/W UA BF TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TRISC Legend: Shaded bits are not used by the MSSP in SPI mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 213 PIC18(L)F2X/45K50 16.3 I2C Mode Overview The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 16-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 16-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS30000684B-page 214 I2C™ MASTER/ SLAVE CONNECTION FIGURE 16-11: SCL VDD Master Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of data bits is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • Single message where a master writes data to a slave. • Single message where a master reads data from a slave. • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching give slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 16.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 16.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.  2012-2014 Microchip Technology Inc. DS30000684B-page 215 PIC18(L)F2X/45K50 16.4 I2C Mode Operation All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 16.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 16.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Phillips I2C specification. 16.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPxEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C™ mode is enabled. 16.4.4 SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS30000684B-page 216 TABLE 16-2: TERM I2C™ BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus holds SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.4.5 START CONDITION 16.4.7 RESTART CONDITION The I2C specification defines a Start condition as a transition of SDA from a high-to-low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an active state. Figure 16-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C specification that states no bus collision can occur on a Start. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. 16.4.6 STOP CONDITION A Stop condition is a transition of the SDA line from a low-to-high state while the SCL line is high. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. 16.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 16-12: I2C™ START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 16-13: Stop Condition I2C™ RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition  2012-2014 Microchip Technology Inc. DS30000684B-page 217 PIC18(L)F2X/45K50 I2C Slave Mode Operation 16.4.9 ACKNOWLEDGE SEQUENCE 16.5 The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The MSSP Slave mode operates in one of four modes selected in the SSPxM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. Modes with Start and Stop bit interrupts operated the same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop condition. 16.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 16-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the software that anything happened. The SSPx Mask register (Register 16-5) affects the address matching process. See Section 16.5.9 “SSPx Mask Register” for more information. 16.5.1.1 I2C Slave 7-Bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 16.5.1.2 I2C Slave 10-Bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS30000684B-page 218  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.5.2 SLAVE RECEPTION 16.5.2.2 7-Bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 16-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 16.2.3 “SPI Master Mode” for more detail. 16.5.2.1 7-Bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 16-13 and Figure 16-14 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPIF bit. Software clears the SSPIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPIF bit. Software clears SSPIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes Idle.  2012-2014 Microchip Technology Inc. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 16-15 displays a module using both address and data holding. Figure 16-16 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSPIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPIF. Note: SSPIF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPIF not set. 11. SSPIF set and CKP cleared after 8th falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. DS30000684B-page 219 DS30000684B-page 220 SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 8 D0 9 P SSPIF set on 9th falling edge of SCL ACK = 1 FIGURE 16-14: SCL SDA Receiving Address Bus Master sends Stop condition PIC18(L)F2X/45K50 I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to ‘1’ in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 SSPIF set on 9th falling edge of SCL P FIGURE 16-15: SDA Receive Address Bus Master sends Stop condition PIC18(L)F2X/45K50 I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS30000684B-page 221 DS30000684B-page 222 P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPIF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPxBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 16-16: SCL SDA Master Releases SDA to slave for ACK sequence PIC18(L)F2X/45K50 I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPxBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPxBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 16-17: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC18(L)F2X/45K50 I2C™ SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS30000684B-page 223 PIC18(L)F2X/45K50 16.5.3 SLAVE TRANSMISSION 16.5.3.2 7-Bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 16-17 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 16.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes Idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. 16.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software can use the BCLIF bit to handle a slave bus collision. DS30000684B-page 224 Master sends a Start condition on SDA and SCL. 2. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the slave setting SSPIF bit. 4. Slave hardware generates an ACK and sets SSPIF. 5. SSPIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed.  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. P S D/A R/W ACKSTAT CKP BF SSPIF S Receiving Address 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSPxBUF 4 When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 16-18: SCL SDA Master sends Stop condition PIC18(L)F2X/45K50 I2C™ SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS30000684B-page 225 PIC18(L)F2X/45K50 16.5.3.3 7-Bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 16-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS30000684B-page 226  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPxBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSPxSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 16-19: SCL SDA Master releases SDA to slave for ACK sequence PIC18(L)F2X/45K50 I2C™ SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS30000684B-page 227 PIC18(L)F2X/45K50 16.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 16.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 16-20 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 16-19 and is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPIF is set. Software clears the SSPIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. Figure 16-21 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS30000684B-page 228  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. CKP UA BF SSPIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPxBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 16-20: SCL SDA Master sends Stop condition PIC18(L)F2X/45K50 I2C™ SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS30000684B-page 229 DS30000684B-page 230 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCL SSPxBUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPxADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPxBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 16-21: SSPIF 1 SCL S 1 SDA Receive First Address Byte PIC18(L)F2X/45K50 I2C™ SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. D/A R/W ACKSTAT CKP UA BF SSPIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPxADD Received address is read from SSPxBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPxBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 16-22: SDA Master sends Restart event PIC18(L)F2X/45K50 I2C™ SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS30000684B-page 231 PIC18(L)F2X/45K50 16.5.6 CLOCK STRETCHING 16.5.6.2 10-Bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 16.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on whether the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 16-23: Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 16.5.6.3 Byte NACKing When the AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When the DHEN bit of SSPxCON3 is set; CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 16.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-22). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPxCON1 DS30000684B-page 232  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 16-23 shows a general call reception sequence. FIGURE 16-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPIF BF (SSPxSTAT) Cleared by software GCEN (SSPxCON2) SSPxBUF is read ’1’ 16.5.9 SSPx MASK REGISTER An SSPx Mask (SSPxMSK) register (Register 16-5) is available in I2C Slave mode as a mask for the value held in the SSPxSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSPx operation until written with a mask value. The SSPx Mask register is active during: • 7-bit Address mode: address compare of A. • 10-bit Address mode: address compare of A only. The SSPx mask has no effect during the reception of the first (high) byte of the address.  2012-2014 Microchip Technology Inc. DS30000684B-page 233 PIC18(L)F2X/45K50 16.6 I2C Master Mode Master mode is enabled by setting and clearing the appropriate SSPxM bits in the SSPxCON1 register and by setting the SSPxEN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSPx Interrupt Flag bit, SSPIF, to be set (SSPx interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 16.6.1 I2C MASTER MODE OPERATION The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 16.7 “Baud Rate Generator” for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS30000684B-page 234  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 16-25). FIGURE 16-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCLSCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 16.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete.  2012-2014 Microchip Technology Inc. DS30000684B-page 235 PIC18(L)F2X/45K50 16.6.4 I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN, of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIGURE 16-26: FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT) At completion of Start bit, hardware clears SEN bit and sets SSPIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 2nd bit 1st bit TBRG SCL S DS30000684B-page 236 TBRG  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA= 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. FIGURE 16-27: REPEAT START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start  2012-2014 Microchip Technology Inc. DS30000684B-page 237 PIC18(L)F2X/45K50 16.6.6 I2C MASTER MODE TRANSMISSION 16.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 16-27). In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 16.6.6.1 BF Status Flag ACKSTAT Status Flag 16.6.6.4 Typical Transmit Sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 16.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS30000684B-page 238  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. S R/W PEN SEN BF (SSPxSTAT) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSPx interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address P ACKSTAT in SSPxCON2 = 1 Cleared by software 9 ACK From slave, clear ACKSTAT bit SSPxCON2 FIGURE 16-28: SEN = 0 Write SSPxCON2 SEN = 1 Start condition begins PIC18(L)F2X/45K50 I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS30000684B-page 239 PIC18(L)F2X/45K50 16.6.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN, of the SSPxCON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/ low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN, of the SSPxCON2 register. 16.6.7.1 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 16.6.7.3 1. BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 16.6.7.2 16.6.7.4 Typical Receive Sequence: WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS30000684B-page 240 12. 13. 14. 15. The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. User sets the RCEN bit of the SSPxCON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCL, SSPIF and BF are set. Master clears SSPIF and reads the received byte from SSPxUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the slave and SSPIF is set. User clears SSPIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication.  2012-2014 Microchip Technology Inc.  2012-2014 Microchip Technology Inc. S RCEN ACKEN SSPOV BF (SSPxSTAT) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Set SSPIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT) and SSPIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF Cleared by software Set SSPIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSPxCON2 (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 FIGURE 16-29: RCEN cleared automatically Master configured as a receiver by programming SSPxCON2 (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Write to SSPxCON2(SEN = 1), begin Start condition Write to SSPxCON2 to start Acknowledge sequence SDA = ACKDT (SSPxCON2) = 0 PIC18(L)F2X/45K50 I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS30000684B-page 241 PIC18(L)F2X/45K50 16.6.8 ACKNOWLEDGE SEQUENCE TIMING 16.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN, of the SSPxCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 16-30). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN, of the SSPxCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 16-29). 16.6.8.1 16.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 16-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPIF SSPIF set at the end of receive Cleared in software Cleared in software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 16-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up Stop condition Note: TBRG = one Baud Rate Generator period. DS30000684B-page 242  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.6.10 SLEEP OPERATION 2 While in Sleep mode, the I C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 16.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 16.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • •  2012-2014 Microchip Technology Inc. Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition DS30000684B-page 243 PIC18(L)F2X/45K50 16.6.13 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF, and reset the I2C port to its Idle state (Figure 16-31). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. FIGURE 16-32: If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS30000684B-page 244  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 16-32). SCL is sampled low before SDA is asserted low (Figure 16-33). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 16-34). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCLIF flag is set and • the MSSP module is reset to its Idle state (Figure 16-32). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 16-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSPx module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software  2012-2014 Microchip Technology Inc. DS30000684B-page 245 PIC18(L)F2X/45K50 FIGURE 16-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 16-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA SCL TBRG SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG time-out SEN BCLIF Set SSPIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSPIF SDA = 0, SCL = 1, set SSPIF DS30000684B-page 246 Interrupts cleared by software  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 16-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 16-36. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 16-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 16-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN S ’0’ SSPIF  2012-2014 Microchip Technology Inc. DS30000684B-page 247 PIC18(L)F2X/45K50 16.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 16-37). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 16-38). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. FIGURE 16-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLIF SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 16-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLIF PEN BCLIF P ’0’ SSPIF ’0’ DS30000684B-page 248  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 16-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 INTCON Name GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD PMD1 SSP1ADD SSP1 Address Register in I2C™ Slave Mode. SSP1 Baud Rate Reload Register in I2C Master mode. SSP1BUF SSP1 Receive Buffer/Transmit Register 62 257 — SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 254 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 255 SSP1MSK SSP1STAT TRISB Legend: SSPM 252 SSP1 MASK Register bits 256 SMP CKE D/A P S R/W UA BF 251 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 2 Shaded bits are not used by the MSSP in I C mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 249 PIC18(L)F2X/45K50 16.7 Baud Rate Generator The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 16-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Table 16-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 16-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1   4  Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal “Reload” in Figure 16-39 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. FIGURE 16-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPxM SSPxM Reload SCL Control SSPxCLK SSPxADD Reload BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C™. This is an implementation limitation. TABLE 16-4: Note 1: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz(1) 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz(1) 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz 2 2 The I C™ interface does not conform to the 400 kHz I C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS30000684B-page 250  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 16.8 Register Definitions: MSSP Control REGISTER 16-1: SSPxSTAT: SSPx STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C™ mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPxEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPxEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty  2012-2014 Microchip Technology Inc. DS30000684B-page 251 PIC18(L)F2X/45K50 REGISTER 16-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP R/W-0 R/W-0 R/W-0 R/W-0 SSPM bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C™ conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Master mode: Unused in this mode DS30000684B-page 252  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 16-2: bit 3-0 SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) SSPM: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1)) 1011 = I2C firmware controlled Master mode (slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: 4: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDA and SCL pins must be configured as inputs. SSPxADD values of 0, 1 or 2 are not supported for I2C mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 253 PIC18(L)F2X/45K50 REGISTER 16-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/W/HC-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C™ Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN(1): Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN(1): Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN(1): Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN(1): Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN(1): Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS30000684B-page 254  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 16-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C™ mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 1 Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set.  2012-2014 Microchip Technology Inc. DS30000684B-page 255 PIC18(L)F2X/45K50 REGISTER 16-4: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED) DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCL is held low. 0 = Data holding is disabled bit 0 Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is active only when the AHEN bit or DHEN bit is set. REGISTER 16-5: SSPxMSK: SSPx MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK: Mask bits 1 = The received address bit n is compared to SSPxADD to detect I2C™ address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPxM = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored DS30000684B-page 256  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C™ MODE) REGISTER 16-6: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C™ specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.  2012-2014 Microchip Technology Inc. DS30000684B-page 257 PIC18(L)F2X/45K50 17.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. FIGURE 17-1: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock and data polarity The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 17-1 and Figure 17-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREGx Register 8 MSb LSb (8) 0 • • • TX/CK pin Pin Buffer and Control Transmit Shift Register (TSR) TXEN TRMT Baud Rate Generator FOSC TX9 n BRG16 +1 SPBRGHx ÷n SPBRGx DS30000684B-page 258 Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 TX9D  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 17-2: EUSART RECEIVE BLOCK DIAGRAM CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGHx SPBRGx Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREGx Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTAx) • Receive Status and Control (RCSTAx) • Baud Rate Control (BAUDCONx) These registers are detailed in Register 17-1, Register 17-2 and Register 17-3, respectively. For all modes of EUSART operation, the TRIS control bits corresponding to the RX/DT and TX/CK pins should be set to ‘1’. The EUSART control will automatically reconfigure the pin from input to output, as needed. When the receiver or transmitter section is not enabled then the corresponding RX/DT or TX/CK pin may be used for general purpose input and output.  2012-2014 Microchip Technology Inc. DS30000684B-page 259 PIC18(L)F2X/45K50 17.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 17-5 for examples of baud rate configurations. 17.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREGx register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREGx is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREGx until the Stop bit of the previous character has been transmitted. The pending character in the TXREGx is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREGx. 17.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the TXCKP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the TXCKP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The TXCKP bit controls transmit data polarity only in Asynchronous mode. In Synchronous mode the TXCKP bit has a different function. 17.1.1 17.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 17-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREGx register. 17.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTAx register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTAx register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTAx register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREGx. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREGx. The TXIF flag bit is not cleared immediately upon writing TXREGx. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREGx write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREGx is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREGx. The TXIF transmitter interrupt flag is set when the TXEN enable bit is set. DS30000684B-page 260  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.1.1.5 TSR Status 17.1.1.7 The TRMT bit of the TXSTAx register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREGx. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. 1. 2. 3. 4. The TSR register is not mapped in data memory, so it is not available to the user. Note: 17.1.1.6 Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTAx register is set the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTAx register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREGx. All nine bits of data will be transferred to the TSR shift register immediately after the TXREGx is written. 5. A special 9-bit Address mode is available for use with multiple receivers. See Section 17.1.2.8 “Address Detection” for more information on the Address mode. 8. FIGURE 17-3: Write to TXREGx BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 6. 7. 9. Asynchronous Transmission Setup Initialize the SPBRGHx:SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 17.4 “EUSART Baud Rate Generator (BRG)”). Set the RX/DT and TX/CK TRIS controls to ‘1’. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set the TXCKP control bit if inverted transmit data polarity is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit. An interrupt will occur immediately provided that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREGx register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg  2012-2014 Microchip Technology Inc. DS30000684B-page 261 PIC18(L)F2X/45K50 FIGURE 17-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 2 Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions. Note: TABLE 17-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 SREN CREN ADDEN FERR RCSTA1 SPEN UARTMD RX9 OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TXREG1 EUSART Transmit Register TXSTA1 Legend: CSRC TX9 — TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission. DS30000684B-page 262  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 17-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-InFirst-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREGx register. 17.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTAx register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTAx register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTAx register enables the EUSART. The RX/DT I/O pin must be configured as an input by setting the corresponding TRIS control bit. If the RX/DT pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit.  2012-2014 Microchip Technology Inc. 17.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 17.1.2.5 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREGx register. Note: 17.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 17.1.2.6 “Receive Overrun Error” for more information on overrun errors. Receive Data Polarity The polarity of the receive data can be controlled with the RXDTP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true receive Idle and data bits. Setting the RXDTP bit to ‘1’ will invert the receive data resulting in low true Idle and data bits. The RXDTP bit controls receive data polarity only in Asynchronous mode. In Synchronous mode the RXDTP bit has a different function. DS30000684B-page 263 PIC18(L)F2X/45K50 17.1.2.4 Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting the following bits: • RCIE interrupt enable bit of the PIE1 register • PEIE/GIEL peripheral interrupt enable bit of the INTCON register • GIE/GIEH global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 17.1.2.5 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTAx register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREGx. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. 17.1.2.7 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTAx register is set, the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTAx register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREGx. 17.1.2.8 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTAx register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTAx register which resets the EUSART. Clearing the CREN bit of the RCSTAx register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 17.1.2.6 If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREGx will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTAx register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTAx register or by resetting the EUSART by clearing the SPEN bit of the RCSTAx register. DS30000684B-page 264  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.1.2.9 Asynchronous Reception Setup: 1. Initialize the SPBRGHx:SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 17.4 “EUSART Baud Rate Generator (BRG)”). 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RX/DT pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE/GIEH and PEIE/GIEL bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Set the RXDTP if inverted receive polarity is desired. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTAx register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREGx register. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 17.1.2.10 This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.  2012-2014 Microchip Technology Inc. 9-Bit Address Detection Mode Setup Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 17.4 “EUSART Baud Rate Generator (BRG)”). Set the RX/DT and TX/CK TRIS controls to ‘1’. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE/GIEH and PEIE/GIEL bits of the INTCON register. Enable 9-bit reception by setting the RX9 bit. Enable address detection by setting the ADDEN bit. Set the RXDTP if inverted receive polarity is desired. Enable reception by setting the CREN bit. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. Read the RCSTAx register to get the error flags. The ninth data bit will always be set. Get the received eight Least Significant data bits from the receive buffer by reading the RCREGx register. Software determines if this is the device’s address. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. DS30000684B-page 265 PIC18(L)F2X/45K50 FIGURE 17-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx RCIDL bit 7/8 Stop bit Read Rcv Buffer Reg RCREGx RCIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RX/DT input. The RCREGx (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. Note: TABLE 17-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCREG1 RCSTA1 EUSART Receive Register SPEN RX9 — SREN CREN ADDEN FERR OERR RX9D 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TRISC TXSTA1 Legend: TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception. DS30000684B-page 266  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See 3.6 “Internal Clock Modes” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 17.4.1 “AutoBaud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.  2012-2014 Microchip Technology Inc. DS30000684B-page 267 PIC18(L)F2X/45K50 17.3 Register Definitions: EUSART Control REGISTER 17-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS30000684B-page 268  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 17-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.  2012-2014 Microchip Technology Inc. DS30000684B-page 269 PIC18(L)F2X/45K50 REGISTER 17-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been detected and the receiver is active Synchronous mode: Don’t care bit 5 RXDTP: Data/Receive Polarity Select bit Asynchronous mode: 1 = Receive data (RX) is inverted (active-low) 0 = Receive data (RX) is not inverted (active-high) Synchronous mode: 1 = Data (DT) is inverted (active-low) 0 = Data (DT) is not inverted (active-high) bit 4 TXCKP: Clock/Transmit Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is low 0 = Idle state for transmit (TX) is high Synchronous mode: 1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock 0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used (SPBRGHx:SPBRGx) 0 = 8-bit Baud Rate Generator is used (SPBRGx) bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on the falling edge. WUE will automatically clear on the rising edge. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS30000684B-page 270  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCONx register selects 16-bit mode. The SPBRGHx:SPBRGx register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTAx register and the BRG16 bit of the BAUDCONx register. In Synchronous mode, the BRGH bit is ignored. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock. EXAMPLE 17-1: For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -------------------------------------------------------------------------64  [SPBRGHx:SPBRGx] + 1  Solving for SPBRGHx:SPBRGx: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- – 1 64 Table 17-3 contains the formulas for determining the baud rate. Example 17-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various Asynchronous modes have been computed for your convenience and are shown in Table 17-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. 16000000 -----------------------9600 = ------------------------ – 1 64 =  25.042  = 25 16000000 Calculated Baud Rate = --------------------------64  25 + 1  Writing a new value to the SPBRGHx, SPBRGx register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 17-3: CALCULATING BAUD RATE ERROR = 9615 Calc. Baud Rate – Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate  9615 – 9600  = ---------------------------------- = 0.16% 9600 BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 1 0 16-bit/Asynchronous SYNC BRG16 BRGH 0 0 0 0 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous 1 Legend: FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGHx, SPBRGx register pair.  2012-2014 Microchip Technology Inc. DS30000684B-page 271 PIC18(L)F2X/45K50 TABLE 17-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 — UARTMD USBMD ACTMD — SPEN RX9 SREN CREN ADDEN PMD0 RCSTA1 SPBRG1 EUSART Baud Rate Generator, Low Byte SPBRGH1 EUSART Baud Rate Generator, High Byte PIR1 TXSTA1 Legend: TMR3MD TMR2MD TMR1MD FERR OERR 61 RX9D 269 — — ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented, read as ‘0’. Shaded bits are not used by the BRG. TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE 300 FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRxG value (decimal) — — — — — — — — — — — — — 1200 0.00 239 1202 0.16 207 1200 0.00 143 Actual Rate % Error SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 1200 — — 2400 — — — 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9615 0.16 77 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 71 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.23k 0.16 38 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k 57.69k 0.16 12 57.60k 0.00 7 — — — 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 4.000 MHz Actual Rate FOSC = 3.6864 MHz % Error SPBRGx value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — DS30000684B-page 272  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 48.000 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 16.000 MHz Actual Rate % Error FOSC = 11.0592 MHz SPBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 — — — 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 — — — 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.97k 0.16 51 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 115.39k 0.16 25 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error FOSC = 4.000 MHz SPBRGx value (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPBRGx value (decimal) Actual Rate % Error FOSC = 1.000 MHz SxBRGx value (decimal) Actual Rate % Error SPBRGx value (decimal) 207 300 — — — — — — — — — 300 0.16 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 48.000 MHz Actual Rate % Error FOSC = 18.432 MHz SPBRGHx: SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) FOSC = 16.000 MHz Actual Rate FOSC = 11.0592 MHz % Error SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 300 300.0 0.00 9999 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 0.00 2499 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2400 0.00 1249 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9585 -0.16 312 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 287 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 155 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 57.69k 0.16 51 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 115.39k 0.16 25 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5  2012-2014 Microchip Technology Inc. DS30000684B-page 273 PIC18(L)F2X/45K50 TABLE 17-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz Actual Rate % Error SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 1.000 MHz SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 207 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 48.000 MHz Actual Rate % Error SPBRGHx: SPBRGx (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRGHx: SPBRGx (decimal) FOSC = 16.000 MHz Actual Rate FOSC = 11.0592 MHz % Error SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 300 300 0.00 39999 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 0.00 9999 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.00 4999 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9600 0.00 1249 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 1151 10425 0.08 441 10417 0.00 383 10433 0.16 264 143 19.2k 19.2k 0.00 624 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 57.6k 57.69k 0.16 207 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 115.39k 0.16 103 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRGHx: SPBRGx (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRGHx: SPBRGx (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 832 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0.00 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS30000684B-page 274  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGx registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 17.4.3 “Auto-Wake-up on Break”). In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCONx register starts the auto-baud calibration sequence (Section 17.4.2 “Auto-Baud Overflow”). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRGx begins counting up using the BRG counter clock as shown in Table 17-6. The fifth rising edge will occur on the RX/ DT pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGHx:SPBRGx register pair, the ABDEN bit is automatically cleared, and the RCIF interrupt flag is set. A read operation on the RCREGx needs to be performed to clear the RCIF interrupt. RCREGx content should be discarded. When calibrating for modes that do not use the SPBRGHx register the user can verify that the SPBRGx register did not overflow by checking for 00h in the SPBRGHx register. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the autobaud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGHx:SPBRGx register pair. TABLE 17-6: The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 17-6. During ABD, both the SPBRGHx and SPBRGx registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGHx FIGURE 17-6: BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 FOSC/4 FOSC/32 1 Note: During the ABD sequence, SPBRGx and SPBRGHx registers are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value BRG COUNTER CLOCK RATES 0000h RX/DT pin 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREGx SPBRGx XXh 1Ch SPBRGHx XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.  2012-2014 Microchip Technology Inc. DS30000684B-page 275 PIC18(L)F2X/45K50 17.4.2 AUTO-BAUD OVERFLOW 17.4.3.1 Special Considerations During the course of automatic baud detection, the ABDOVF bit of the BAUDCONx register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGHx:SPBRGx register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX/DT pin. Upon detecting the fifth RX/DT edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCONx register. The RCIF flag can be subsequently cleared by reading the RCREGx. The ABDOVF flag can be cleared by software directly. Break Character To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. Therefore, the initial character in the transmission must be all ‘0’s. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. 17.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCONx register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wakeup event consists of a high-to-low transition on the RX/ DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 17-7), and asynchronously if the device is in Sleep mode (Figure 17-8). The interrupt condition is cleared by reading the RCREGx register. To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Oscillator Startup Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared by hardware by a rising edge on RX/DT. The interrupt condition is then cleared by software by reading the RCREGx register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS30000684B-page 276  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 17-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREGx The EUSART remains in Idle while the WUE bit is set. FIGURE 17-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREGx If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.  2012-2014 Microchip Technology Inc. DS30000684B-page 277 PIC18(L)F2X/45K50 17.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTAx register. The Break character transmission is then initiated by a write to the TXREGx. The value of data written to TXREGx will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTAx register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 17-9 for the timing of the Break character sequence. 17.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 17.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTAx register and the Received data as indicated by RCREGx. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; • RCIF bit is set • FERR bit is set • RCREGx = 00h The second method uses the Auto-Wake-up feature described in Section 17.4.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCONx register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREGx becomes empty, as indicated by the TXIF, the next data byte can be written to TXREGx. FIGURE 17-9: Write to TXREGx SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX/CK (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB (send Break control bit) DS30000684B-page 278 SENDB Sampled Here Auto Cleared  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 17.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 17.5.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART for Synchronous Master operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Setting the CSRC bit of the TXSTAx register configures the device as a master. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTAx register enables the EUSART. If the RX/DT or TX/CK pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits. 17.5.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the TXCKP bit of the BAUDCONx register. Setting the TXCKP bit sets the clock Idle state as high. When the TXCKP bit is set, the data changes on the falling edge of each clock and is sampled on the rising edge of each clock. Clearing the TXCKP bit sets the Idle state as low. When the TXCKP bit is cleared, the data changes on the rising edge of each clock and is sampled on the falling edge of each clock. 17.5.1.3 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREGx register. If the TSR still contains all or part of a previous character the new character data is held in the TXREGx until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREGx is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREGx. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: 17.5.1.4 The TSR register is not mapped in data memory, so it is not available to the user. Data Polarity The polarity of the transmit and receive data can be controlled with the RXDTP bit of the BAUDCONx register. The default state of this bit is ‘0’ which selects high true transmit and receive data. Setting the RXDTP bit to ‘1’ will invert the data resulting in low true transmit and receive data. The TRIS bits corresponding to the RX/DT and TX/ CK pins should be set. 17.5.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.  2012-2014 Microchip Technology Inc. DS30000684B-page 279 PIC18(L)F2X/45K50 17.5.1.5 1. 2. 3. Synchronous Master Transmission Setup 4. Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 17.4 “EUSART Baud Rate Generator (BRG)”). Set the RX/DT and TX/CK TRIS controls to ‘1’. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RX/DT and TX/ CK I/O pins. 5. 6. 7. FIGURE 17-10: 8. 9. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE, GIE/GIEH and PEIE/GIEL interrupt enable bits. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREGx register. SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREGx Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode, SPBRGx = 0, continuous transmission of two 8-bit words. FIGURE 17-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREGx reg TXIF bit TRMT bit TXEN bit DS30000684B-page 280  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 17-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — SPEN RX9 SREN CREN ADDEN RCSTA1 TMR3MD TMR2MD TMR1MD FERR OERR RX9D 61 269 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TRISC TXREG1 TXSTA1 Legend: TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 EUSART Transmit Register CSRC TX9 149 — TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission.  2012-2014 Microchip Technology Inc. DS30000684B-page 281 PIC18(L)F2X/45K50 17.5.1.6 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTAx register) or the Continuous Receive Enable bit (CREN of the RCSTAx register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREGx. The RCIF bit remains set as long as there are un-read characters in the receive FIFO. 17.5.1.7 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/ CK pin output driver must be disabled by setting the associated TRIS bit when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. 17.5.1.8 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREGx is read to access the FIFO. When this happens the OERR bit of the RCSTAx register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREGx. DS30000684B-page 282 If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. 17.5.1.9 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTAx register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTAx register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREGx. 17.5.1.10 Synchronous Master Reception Setup 1. Initialize the SPBRGHx, SPBRGx register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable RX/DT and TX/CK output drivers by setting the corresponding TRIS bits. 4. Ensure bits CREN and SREN are clear. 5. If using interrupts, set the GIE/GIEH and PEIE/ GIEL bits of the INTCON register and set RCIE. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTAx register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREGx register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 17-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 17-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 BAUDCON1 ABDOVF RCIDL INTCON GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page RXDTP TXCKP BRG16 — WUE ABDEN 270 TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 CREN ADDEN FERR OERR RX9D 269 PMD0 RCREG1 RCSTA1 EUSART Receive Register SPEN RX9 — SREN SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TXSTA1 Legend: CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.  2012-2014 Microchip Technology Inc. DS30000684B-page 283 PIC18(L)F2X/45K50 17.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTAx register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTAx register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTAx register enables the EUSART. If the RX/DT or TX/CK pins are shared with an analog peripheral the analog I/O functions must be disabled by clearing the corresponding ANSEL bits. 17.5.2.1 The operation of the Synchronous Master and Slave modes are identical (see Section 17.5.1.3 “Synchronous Master Transmission”), except in the case of the Sleep mode. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. RX/DT and TX/CK pin output drivers must be disabled by setting the corresponding TRIS bits. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREGx register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREGx register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE/GIEL and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE/GIEH bit is also set, the program will call the Interrupt Service Routine. 17.5.2.2 1. 2. 3. 4. 5. 6. 7. 8. DS30000684B-page 284 EUSART Synchronous Slave Transmit Synchronous Slave Transmission Setup: Set the SYNC and SPEN bits and clear the CSRC bit. Set the RX/DT and TX/CK TRIS controls to ‘1’. Clear the CREN and SREN bits. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the TXIE bit. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXREGx register.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 17-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSP1F CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 269 RCSTA1 SPBRG1 EUSART Baud Rate Generator, Low Byte — SPBRGH1 EUSART Baud Rate Generator, High Byte — TRISC TXREG1 TXSTA1 Legend: TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 EUSART Transmit Register CSRC TX9 — TXEN SYNC SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission.  2012-2014 Microchip Technology Inc. DS30000684B-page 285 PIC18(L)F2X/45K50 17.5.2.3 EUSART Synchronous Slave Reception 17.5.2.4 1. The operation of the Synchronous Master and Slave modes is identical (Section 17.5.1.6 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREGx register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE/GIEH bit is also set, the program will branch to the interrupt vector. Synchronous Slave Reception Setup Set the SYNC and SPEN bits and clear the CSRC bit. Set the RX/DT and TX/CK TRIS controls to ‘1’. If using interrupts, ensure that the GIE/GIEH and PEIE/GIEL bits of the INTCON register are set and set the RCIE bit. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTAx register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREGx register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTAx register or by clearing the SPEN bit which resets the EUSART. 2. 3. 4. 5. 6. 7. 8. 9. TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page BAUDCON1 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 270 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61 RCREG1 RCSTA1 EUSART Receive Register SPEN RX9 — SREN CREN SPBRG1 EUSART Baud Rate Generator, Low Byte SPBRGH1 EUSART Baud Rate Generator, High Byte TXSTA1 Legend: CSRC TX9 TXEN SYNC ADDEN FERR OERR RX9D 269 — — SENDB BRGH TRMT TX9D 268 — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception. DS30000684B-page 286  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 18.0 The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). FIGURE 18-1: The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 18-1 shows the block diagram of the ADC. ADC BLOCK DIAGRAM 5 FVR BUF2 11111 DAC 11110 CTMU 11101 Temperature Diode AN27(1) CHS 11100 11011 ADCMD AN5(1) 00101 AN4 00100 AN3 00011 AN2 AN1 AN0 ADON 10-Bit ADC GO/DONE 10 00010 ADFM 00001 0 = Left Justify 1 = Right Justify 00000 10 2 PVCFG ADRESH AVDD VREF+/AN3 01 FVR BUF2 10 Reserved 11 2 AVSS VREF-/AN2 ADRESL 00 NVCFG 00 01 Reserved 10 Reserved 11 Note: Additional ADC channels AN5-AN7 and AN20-AN27 are only available on PIC18(L)F45K50 devices.  2012-2014 Microchip Technology Inc. DS30000684B-page 287 PIC18(L)F2X/45K50 18.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 18.1.1 PORT CONFIGURATION The ANSELx and TRISx registers configure the A/D port pins. Any port pin needed as an analog input should have its corresponding ANSx bit set to disable the digital input buffer and TRISx bit set to disable the digital output driver. If the TRISx bit is cleared, the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the ANSx bits and the TRIS bits. Note 1: When reading the PORT register, all pins with their corresponding ANSx bit set read as cleared (a low level). However, analog conversion of pins configured as digital inputs (ANSx bit cleared and TRISx bit set) will be accurately converted. 2: Analog levels on any pin with the corresponding ANSx bit cleared may cause the digital input buffer to consume current out of the device’s specification limits. 3: The PBADEN bit in Configuration Register 3H configures PORTB pins to reset as analog or digital pins by controlling how the bits in ANSELB are reset. 18.1.2 CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 18.2 “ADC Operation” for more information. DS30000684B-page 288 18.1.3 ADC VOLTAGE REFERENCE The PVCFG and NVCFG bits of the ADCON1 register provide independent control of the positive and negative voltage references. The positive voltage reference can be: • VDD • the fixed voltage reference (FVR BUF2) • an external voltage source (VREF+) The negative voltage reference can be: • VSS • an external voltage source (VREF-) 18.1.4 SELECTING AND CONFIGURING ACQUISITION TIME The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. Acquisition time is set with the ACQT bits of the ADCON2 register. Acquisition delays cover a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there is no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Manual acquisition is selected when ACQT = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. When an acquisition time is programmed, there is no indication of when the acquisition time ends and the conversion begins.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 18.1.5 CONVERSION CLOCK 18.1.6 The source of the conversion clock is software selectable via the ADCS bits of the ADCON2 register. There are seven possible clock options: • • • • • • • The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt enable is the ADIE bit in the PIE1 register and the interrupt priority is the ADIP bit in the IPR1 register. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADIF bit must be cleared by software. FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator) Note: For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Table 29-33 for more information. Table 18-1 gives examples of appropriate ADC clock selections. Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. TABLE 18-1: ADC CLOCK PERIOD (TAD) vs. DEVICE OPERATING FREQUENCIES AD Clock Period (TAD) ADC Clock Source FOSC/2 FOSC/4 ADCS 000 100 Device Frequency (FOSC) 48 MHz 41.17 ns(2) 83.3 ns(2) ns(2) FOSC/8 001 166.7 FOSC/16 101 333.3 ns(2) FOSC/32 010 ns(2) FOSC/64 110 FRC Legend: Note 1: 2: 3: 4: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 18-3. Note: INTERRUPTS 011 666.7 1.3 s 1-4 s(1,4) 16 MHz 4 MHz 1 MHz 2.0 s 125 ns(2) 250 ns(2) 1.0 s 4.0 s(3) 500 ns(2) 2.0 s 8.0 s(3) 1.0 s 4.0 s(3) 16.0 s(3) 2.0 s s(3) 32.0 s(3) 16.0 s(3) 64.0 s(3) s(1,4) 1-4 s(1,4) 4.0 s(3) 1-4 s(1,4) 500 8.0 1-4 ns(2) Shaded cells are outside the recommended range. The FRC source has a typical TAD time of 1.7 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep.  2012-2014 Microchip Technology Inc. DS30000684B-page 289 PIC18(L)F2X/45K50 18.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure 18-2 shows the two output formats. FIGURE 18-2: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ DS30000684B-page 290 bit 0 LSB bit 0 bit 7 bit 0 10-bit A/D Result  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 18.2 Figure 18-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT bits are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the conversion begins. ADC Operation 18.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will, depending on the ACQT bits of the ADCON2 register, either immediately start the Analog-to-Digital conversion or start an acquisition delay followed by the Analog-toDigital conversion. FIGURE 18-3: Figure 18-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT bits are set to ‘010’ which selects a 4 TAD acquisition time before the conversion starts. The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 18.2.10 “A/D Conversion Procedure”. Note: A/D CONVERSION TAD CYCLES (ACQT = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 2 TAD b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Discharge Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. FIGURE 18-4: A/D CONVERSION TAD CYCLES (ACQT = 010, TACQ = 4 TAD) TAD Cycles TACQT Cycles 1 2 3 Automatic Acquisition Time 4 1 2 3 4 5 6 7 8 9 10 11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts (Holding capacitor is disconnected from analog input) Set GO bit (Holding capacitor continues acquiring input)  2012-2014 Microchip Technology Inc. 2 TAD Discharge On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS30000684B-page 291 PIC18(L)F2X/45K50 18.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 18.2.3 DISCHARGE The discharge phase is used to initialize the value of the capacitor array. The array is discharged after every sample. This feature helps to optimize the unity-gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. 18.2.4 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared by software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Note: 18.2.5 A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. DELAY BETWEEN CONVERSIONS After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, the currently selected channel is reconnected to the charge holding capacitor commencing the next acquisition. 18.2.6 ADC OPERATION IN POWERMANAGED MODES The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT and ADCS bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D FRC clock source should be selected. DS30000684B-page 292 18.2.7 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 18.2.8 SPECIAL EVENT TRIGGER Two Special Event Triggers are available to start an A/D conversion: CTMU and CCP2. The Special Event Trigger source is selected using the TRIGSEL bit in ADCON1. When TRIGSEL = 0, the CCP2 module is selected as the Special Event Trigger source. To enable the Special Event Trigger in the CCP module, set CCP2M = 1011, in the CCP2CON register. When TRIGSEL = 1, the CTMU module is selected. The CTMU module requires that the CTTRIG bit in CTMUCONH is set to enable the Special Event Trigger. In addition to the TRIGSEL bit, the following steps are required to start an A/D conversion: • The A/D module must be enabled (ADON = 1) • The appropriate analog input channel selected • The minimum acquisition period set one of these ways: - Timing provided by the user - Selection made of an appropriate TACQ time With these conditions met, the trigger sets the GO/DONE bit and the A/D acquisition starts. If the A/D module is not enabled (ADON = 0), the module ignores the Special Event Trigger. 18.2.9 PERIPHERAL MODULE DISABLE When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bit for the ADC module is ADCMD in the PMD1 Register. See Section 4.0 “Power-Managed Modes” for more information.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 18.2.10 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (See TRIS register) • Configure pin as analog Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Select result format • Select acquisition delay • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 18-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; MOVLW B’10101111’ ;right justify, Frc, MOVWF ADCON2 ; & 12 TAD ACQ time MOVLW B’00000000’ ;ADC ref = Vdd,Vss MOVWF ADCON1 ; BSF TRISA,0 ;Set RA0 to input BSF ANSEL,0 ;Set RA0 to analog MOVLW B’00000001’ ;AN0, ADC on MOVWF ADCON0 ; BSF ADCON0,GO ;Start conversion ADCPoll: BTFSC ADCON0,GO ;Is conversion done? BRA ADCPoll ;No, test again ; Result is complete - store 2 MSbits in ; RESULTHI and 8 LSbits in RESULTLO MOVFF ADRESH,RESULTHI MOVFF ADRESL,RESULTLO Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Software delay required if ACQT bits are set to zero delay. See Section 18.4 “A/D Acquisition Requirements”.  2012-2014 Microchip Technology Inc. DS30000684B-page 293 PIC18(L)F2X/45K50 18.3 Register Definitions: ADC Control Note: Analog pin control is determined by the ANSELx registers (see Register 11-2) REGISTER 18-1: U-0 ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 CHS R/W-0 R/W-0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4 00101 = AN5(1) 00110 = AN6(1) 00111 = AN7(1) 01000 = AN8 01001 = AN9 01010 = AN10 01011 = AN11 01100 = AN12 01101 = AN13 01110 = AN14 01111 = AN15 10000 = AN16 10001 = AN17 10010 = AN18 10011 = AN19 10100 = AN20(1) 10101 = AN21(1) 10110 = AN22(1) 10111 = AN23(1) 11000 = AN24(1) 11001 = AN25(1) 11010 = AN26(1) 11011 = AN27(1) 11100 = Temperature Diode 11101 = CTMU 11110 = DAC 11111 = FVR BUF2 (1.024V/2.048V/4.096V Fixed Voltage Reference)(2) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: Available on PIC18(L)F45K50 devices only. Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference. DS30000684B-page 294  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 18-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 TRIGSEL — — — R/W-0 R/W-0 R/W-0 PVCFG R/W-0 NVCFG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TRIGSEL: Special Trigger Select bit 1 = Selects the special trigger from CTMU 0 = Selects the special trigger from CCP2 bit 6-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG: Positive Voltage Reference Configuration bits 00 = A/D VREF+ connected to internal signal, AVDD 01 = A/D VREF+ connected to external pin, VREF+ 10 = A/D VREF+ connected to internal signal, FVR BUF2 11 = Reserved bit 1-0 NVCFG: Negative Voltage Reference Configuration bits 00 = A/D VREF- connected to internal signal, AVSS 01 = A/D VREF- connected to external pin, VREF10 = Reserved 11 = Reserved  2012-2014 Microchip Technology Inc. x = Bit is unknown DS30000684B-page 295 PIC18(L)F2X/45K50 REGISTER 18-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 ADFM — R/W-0 R/W-0 R/W-0 R/W-0 ACQT R/W-0 R/W-0 ADCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge holding capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conversions begins. 000 = 0(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) Note 1: When the A/D clock source is selected as FRC then the start of conversion is delayed by one instruction cycle after the GO/DONE bit is set to allow the SLEEP instruction to be executed. DS30000684B-page 296  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 REGISTER 18-4: R/W-x ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 18-5: R/W-x ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x r r r r r r ADRES bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 18-6: x = Bit is unknown ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x r r r r r r R/W-x R/W-x ADRES bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 18-7: R/W-x x = Bit is unknown ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES: ADC Result Register bits Lower eight bits of 10-bit conversion result  2012-2014 Microchip Technology Inc. DS30000684B-page 297 PIC18(L)F2X/45K50 18.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 18-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 18-5. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), EQUATION 18-1: an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 18-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k  3.0V V DD Assumptions: T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 5µs + T C +   Temperature - 25°C   0.05µs/°C   The value for TC can be approximated with the following equations: 1 V AP PLIE D  1 – ------------ = V CHOLD  2047 ;[1] VCHOLD charged to within 1/2 lsb –TC ----------  RC V AP P LI ED  1 – e  = V CHOLD   ;[2] VCHOLD charge response to VAPPLIED – Tc ---------  1 RC V AP P LIED  1 – e  = V A P PLIE D  1 – ------------  2047   ;combining [1] and [2] Solving for TC: T C = – C HOLD  R IC + R SS + R S  ln(1/2047) = – 13.5pF  1k  + 700  + 10k   ln(0.0004885) = 1.20 µs Therefore: T ACQ = 5µs + 1.20µs +   50°C- 25°C   0.05  s/ °C   = 7.45µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS30000684B-page 298  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 18-5: ANALOG INPUT MODEL VDD Rs VA ANx RIC  1k CPIN 5 pF I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 13.5 pF Legend: CPIN = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: VDD Discharge Switch VSS/VREF- 3.5V 3.0V 2.5V 2.0V 1.5V .1 1 10 Rss (k) 100 See Section 29.0 “Electrical Specifications”. FIGURE 18-6: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 1/2 LSB ideal 3FBh Full-Scale Transition 004h 003h 002h 001h 000h Analog Input Voltage 1/2 LSB ideal VSS/VREF-  2012-2014 Microchip Technology Inc. Zero-Scale Transition VDD/VREF+ DS30000684B-page 299 PIC18(L)F2X/45K50 TABLE 18-2: Name REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 — ADCON0 — ADCON1 TRIGSEL — ADFM — ADCON2 A/D Result, High Byte ADRESL A/D Result, Low Byte — Bit 3 Bit 2 CHS ADRESH ANSELA Bit 4 — PVCFG Bit 1 Bit 0 GO/DONE ADON NVCFG ACQT ADCS Register on page 294 295 296 297 297 — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 148 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 ANSELC ANSC7 ANSC6 — — — ANSC2 — — 148 ANSELD(1) ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 148 ANSELE(1) — — — — — ANSE2 ANSE1 ANSE0 149 322 CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123 PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120 PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117 PMD1 — MSSPMD CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149 TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 149 TRISE WPUE3 — — — — TRISE2(1) TRISE1(1) TRISE0(1) 149 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by this module. Available on PIC18(L)F45K50 devices. Note 1: TABLE 18-3: Name CONFIG3H Legend: CONFIGURATION REGISTERS ASSOCIATED WITH THE ADC MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376 — = unimplemented locations, read as ‘0’. Shaded bits are not used by the ADC module. DS30000684B-page 300  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 19.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference 19.1 Comparator Overview FIGURE 19-1: SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 19-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level.  2012-2014 Microchip Technology Inc. DS30000684B-page 301 PIC18(L)F2X/45K50 FIGURE 19-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM CxCH 2 C12IN0- 0 C12IN1- 1 C12IN2- CxON(1) CxSP D CxVIN- 2 C12IN3- CxVIN+ 3 Q1 - (2),(3) EN Cx + D Q3(2) DAC Output Read or Write of CMxCON0 0 FVR BUF1 1 To Interrupts (CxIF) Reset 0 1 Q EN CL CxR CxIN+ Q To CMxCON0 (CxOUT) CM2CON1 (MCxOUT) async_CXOUT CxPOL CxSYNC CXVREF to PWM Logic CxOE TRIS bit 0 CXRSEL D Q 1 CxOUT Timer1 Clock sync_CxOUT - to SR Latch - to TxG MUX(4) Note 1: 2: 3: 4: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode. Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI. DS30000684B-page 302  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 19.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs. The CM1CON0 and CM2CON0 registers (see Register 19-1) contain the control and status bits for the following: • • • • • • Enable Input selection Reference selection Output selection Output polarity Speed selection 19.2.1 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 19.2.2 COMPARATOR INPUT SELECTION The CxCH bits of the CMxCON0 register direct one of four analog input pins to the comparator inverting input. Note: 19.2.3 To use CxIN+ and C12INx- pins as analog inputs, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. COMPARATOR REFERENCE SELECTION Setting the CxR bit of the CMxCON0 register directs an internal voltage reference or an analog input pin to the non-inverting input of the comparator. See Section 22.0 “Fixed Voltage Reference (FVR)” for more information on the Internal Voltage Reference module. 19.2.4 COMPARATOR OUTPUT SELECTION The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CM2CON1 register. In order to make the output available for an external connection, the following conditions must be true: Note 1: The CxOE bit overrides the PORT data latch. Setting the CxON has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 19.2.5 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 19-1 shows the output state versus input conditions, including polarity control. TABLE 19-1: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVIN- > CxVIN+ 0 0 CxVIN- < CxVIN+ 0 1 CxVIN- > CxVIN+ 1 1 CxVIN- < CxVIN+ 1 0 19.2.6 COMPARATOR SPEED SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. 19.3 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 29.0 “Electrical Specifications” for more details. • CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set  2012-2014 Microchip Technology Inc. DS30000684B-page 303 PIC18(L)F2X/45K50 19.4 Comparator Interrupt Operation The comparator interrupt flag will be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 19-2). The first latch is updated with the comparator output value, when the CMxCON0 register is read or written. The value is latched on the third cycle of the system clock, also known as Q3. This first latch retains the comparator value until another read or write of the CMxCON0 register occurs or a Reset takes place. The second latch is updated with the comparator output value on every first cycle of the system clock, also known as Q1. When the output value of the comparator changes, the second latch is updated and the output values of both latches no longer match one another, resulting in a mismatch condition. The latch outputs are fed directly into the inputs of an exclusive-or gate. This mismatch condition is detected by the exclusive-or gate and sent to the interrupt circuitry. The mismatch condition will persist until the first latch value is updated by performing a read of the CMxCON0 register or the comparator output returns to the previous state. Note 1: A write operation to the CMxCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. 2: Comparator interrupts will operate correctly regardless of the state of CxOE. When the mismatch condition occurs, the comparator interrupt flag is set. The interrupt flag is triggered by the edge of the changing value coming from the exclusiveor gate. This means that the interrupt flag can be reset once it is triggered without the additional step of reading or writing the CMxCON0 register to clear the mismatch latches. When the mismatch registers are cleared, an interrupt will occur upon the comparator’s return to the previous state, otherwise no interrupt will be generated. Software will need to maintain information about the status of the comparator output, as read from the CMxCON0 register, or CM2CON1 register, to determine the actual change that has occurred. See Figures 19-3 and 19-4. The CxIF bit of the PIR2 register is the comparator interrupt flag. This bit must be reset by software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, an interrupt can be generated. In mid-range Compatibility mode the CxIE bit of the PIE2 register and the PEIE/GIEL and GIE/GIEH bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CxIF bit of the PIR2 register will still be set if an interrupt condition occurs. DS30000684B-page 304 19.4.1 PRESETTING THE MISMATCH LATCHES The comparator mismatch latches can be preset to the desired state before the comparators are enabled. When the comparator is off the CxPOL bit controls the CxOUT level. Set the CxPOL bit to the desired CxOUT non-interrupt level while the CxON bit is cleared. Then, configure the desired CxPOL level in the same instruction that the CxON bit is set. Since all register writes are performed as a read-modify-write, the mismatch latches will be cleared during the instruction read phase and the actual configuration of the CxON and CxPOL bits will be occur in the final write phase. FIGURE 19-3: COMPARATOR INTERRUPT TIMING W/O CMxCON0 READ Q1 Q3 CxIN+ TRT CxIN Set CxIF (edge) CxIF Reset by Software FIGURE 19-4: COMPARATOR INTERRUPT TIMING WITH CMxCON0 READ Q1 Q3 CxIN+ TRT CxOUT Set CxIF (edge) CxIF Cleared by CMxCON0 Read Reset by Software Note 1: If a change in the CMxCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF interrupt flag of the PIR2 register may not get set. 2: When either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 19.5 Operation During Sleep 19.7 The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 29.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CxIE bit of the PIE2 register and the PEIE/GIEL bit of the INTCON register must be set. The instruction following the SLEEP instruction always executes following a wake from Sleep. If the GIE/GIEH bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 19.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their Off states.Comparator Control Registers. FIGURE 19-5: Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-5. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. ANALOG INPUT MODEL VDD VT  0.6V Rs < 10K RIC To Comparator AIN VA CPIN 5 pF VT  0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC RS = Source Impedance = Analog Voltage VA = Threshold Voltage VT Note 1: See Section 29.0 “Electrical Specifications”.  2012-2014 Microchip Technology Inc. DS30000684B-page 305 PIC18(L)F2X/45K50 19.8 Additional Comparator Features There are four additional comparator features: • • • • Simultaneous read of comparator outputs Internal reference selection Hysteresis selection Output Synchronization 19.8.1 SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. Note 1: Obtaining the status of C1OUT or C2OUT by reading CM2CON1 does not affect the comparator interrupt mismatch registers. 19.8.2 INTERNAL REFERENCE SELECTION 19.8.3 SYNCHRONIZING COMPARATOR OUTPUT TO TIMER1 The Comparator Cx output can be synchronized with Timer1 by setting the CxSYNC bit of the CM2CON1 register. When enabled, the Cx output is latched on the falling edge of the Timer1 source clock. To prevent a race condition when gating Timer1 clock with the comparator output, Timer1 increments on the rising edge of its clock source, and the falling edge latches the comparator output. See the Comparator Block Diagram (Figure 19-2) and the Timer1 Block Diagram (Figure 13-1) for more information. Note 1: The comparator synchronized output should not be used to gate the external Timer1 clock when the Timer1 synchronizer is enabled. 2: The Timer1 prescale should be set to 1:1 when synchronizing the comparator output as unexpected results may occur with other prescale values. There are two internal voltage references available to the non-inverting input of each comparator. One of these is the Fixed Voltage Reference (FVR) and the other is the variable Digital-to-Analog Converter (DAC). The CxRSEL bit of the CM2CON1 register determines which of these references is routed to the Comparator Voltage reference output (CXVREF). Further routing to the comparator is accomplished by the CxR bit of the CMxCON0 register. See Section 22.0 “Fixed Voltage Reference (FVR)” and Figure 19-2 for more detail. DS30000684B-page 306  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 19.9 Register Definitions: Comparator Control REGISTER 19-1: CMxCON0: COMPARATOR x CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 CxON CxOUT CxOE CxPOL CxSP CxR R/W-0 R/W-0 CxCH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Cx Enable bit 1 = Comparator Cx is enabled 0 = Comparator Cx is disabled bit 6 CxOUT: Comparator Cx Output bit If CxPOL = 1 (inverted polarity): CxOUT = 0 when CxVIN+ > CxVINCxOUT = 1 when CxVIN+ < CxVINIf CxPOL = 0 (non-inverted polarity): CxOUT = 1 when CxVIN+ > CxVINCxOUT = 0 when CxVIN+ < CxVIN- bit 5 CxOE: Comparator Cx Output Enable bit 1 = CxOUT is present on the CxOUT pin(1) 0 = CxOUT is internal only bit 4 CxPOL: Comparator Cx Output Polarity Select bit 1 = CxOUT logic is inverted 0 = CxOUT logic is not inverted bit 3 CxSP: Comparator Cx Speed/Power Select bit 1 = Cx operates in normal power, higher speed mode 0 = Cx operates in low-power, low-speed mode bit 2 CxR: Comparator Cx Reference Select bit (non-inverting input) 1 = CxVIN+ connects to CXVREF output 0 = CxVIN+ connects to C12IN+ pin bit 1-0 CxCH: Comparator Cx Channel Select bit 00 = C12IN0- pin of Cx connects to CxVIN01 = C12IN1- pin of Cx connects to CXVIN10 = C12IN2- pin of Cx connects to CxVIN11 = C12IN3- pin of Cx connects to CxVIN- Note 1: x = Bit is unknown Comparator output requires the following three conditions: CxOE = 1, CxON = 1 and corresponding port TRIS bit = 0.  2012-2014 Microchip Technology Inc. DS30000684B-page 307 PIC18(L)F2X/45K50 REGISTER 19-2: CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL — — C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR BUF1 routed to C1VREF input 0 = DAC routed to C1VREF input bit 4 C2RSEL: Comparator C2 Reference Select bit 1 = FVR BUF1 routed to C2VREF input 0 = DAC routed to C2VREF input bit 3-2 Reserved: Maintain these bits clear bit 1 C1SYNC: C1 Output Synchronous Mode bit 1 = C1 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C1 output is asynchronous bit 0 C2SYNC: C2 Output Synchronous Mode bit 1 = C2 output is synchronized to rising edge of TMR1 clock (T1CLK) 0 = C2 output is asynchronous DS30000684B-page 308  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 19-2: Name ANSELA ANSELB REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 147 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 308 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH 307 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH 307 — VREFCON1 DACEN DACLPS DACOE VREFCON2 — — — FVREN FVRST VREFCON0 INTCON GIE/GIEH PEIE/GIEL DACPSS — DACNSS DACR FVRS 334 335 — — — — 331 TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114 IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124 PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121 PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118 PMD1 — MSSPMD TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149 CTMUMD CMP2MD CMP1MD ADCMD CCP2MD CCP1MD 62 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by the comparator module.  2012-2014 Microchip Technology Inc. DS30000684B-page 309 PIC18(L)F2X/45K50 20.0 CHARGE TIME MEASUREMENT UNIT (CTMU) The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. By working with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. The module includes the following key features: • Up to 28(1) channels available for capacitive or time measurement input • On-chip precision current source • Four-edge input trigger sources • Polarity control for each edge source • Control of edge sequence • Control of response to edges FIGURE 20-1: • High precision time measurement • Time delay of external or internal signal asynchronous to system clock • Accurate current source suitable for capacitive measurement The CTMU works in conjunction with the A/D Converter to provide up to 28(1) channels for time or charge measurement, depending on the specific device and the number of A/D channels available. When configured for time delay, the CTMU is connected to the C12IN1- input of Comparator 2. The level-sensitive input edge sources can be selected from four sources: two external input pins (CTED1/CTED2) or the ECCP1/ CCP2 Special Event Triggers. Figure 20-1 provides a block diagram of the CTMU. Note 1: PIC18(L)F2XK50 devices have up to 17 channels available. CTMU BLOCK DIAGRAM CTMUCONH/CTMUCONL EDGEN EDGSEQEN EDG1SELx EDG1POL EDG2SELx EDG2POL CTED1 CTED2 CCP2 ECCP1 CTMUICON ITRIM IRNG EDG1STAT EDG2STAT Edge Control Logic Current Source Current Control TGEN IDISSEN CTTRIG CTMU Control Logic Pulse Generator CTPLS Comparator 2 Output Comparator C1/C2 Input A/D Converter A/D Special Event Trigger DS30000684B-page 310  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 20.1 CTMU Operation The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed. In this case, the voltage read by the A/D is then representative of the amount of time elapsed from the time the current source starts and stops charging the circuit. 20.1.2 CURRENT SOURCE At the heart of the CTMU is a precision current source, designed to provide a constant reference for measurements. The level of current is user selectable across three ranges or a total of two orders of magnitude, with the ability to trim the output in ±2% increments (nominal). The current range is selected by the IRNG bits (CTMUICON), with a value of ‘01’ representing the lowest range. If the CTMU is being used as a time delay, both capacitance and current source are fixed, as well as the voltage supplied to the comparator circuit. The delay of a signal is determined by the amount of time it takes the voltage to charge to the comparator threshold voltage. Current trim is provided by the ITRIM bits (CTMUICON). These six bits allow trimming of the current source in steps of approximately 2% per step. Note that half of the range adjusts the current source positively and the other half reduces the current source. A value of ‘000000’ is the neutral position (no change). A value of ‘100001’ is the maximum negative adjustment (approximately -62%) and ‘011111’ is the maximum positive adjustment (approximately +62%). 20.1.1 20.1.3 THEORY OF OPERATION The operation of the CTMU is based on the following equation for charge: I=C• dV dT More simply, the amount of charge measured in coulombs in a circuit is defined as current in amperes (I) multiplied by the amount of time in seconds that the current flows (t). Charge is also defined as the capacitance in farads (C) multiplied by the voltage of the circuit (V). It follows that: I  t = C  V. The CTMU module provides a constant, known current source. The A/D Converter is used to measure (V) in the equation, leaving two unknowns: capacitance (C) and time (t). The above equation can be used to calculate capacitance or time, by either the relationship using the known fixed capacitance of the circuit: EDGE SELECTION AND CONTROL CTMU measurements are controlled by edge events occurring on the module’s two input channels. Each channel, referred to as Edge 1 and Edge 2, can be configured to receive input pulses from one of the edge input pins (CTED1 and CTED2), Timer1 or Output Compare Module 1. The input channels are levelsensitive, responding to the instantaneous level on the channel rather than a transition between levels. The inputs are selected using the EDG1SEL and EDG2SEL bit pairs (CTMUCONL and ). In addition to source, each channel can be configured for event polarity using the EDGE2POL and EDGE1POL bits (CTMUCONL). The input channels can also be filtered for an edge event sequence (Edge 1 occurring before Edge 2) by setting the EDGSEQEN bit (CTMUCONH). t = C  V  I or by: C = I  t  V using a fixed time that the current source is applied to the circuit.  2012-2014 Microchip Technology Inc. DS30000684B-page 311 PIC18(L)F2X/45K50 20.1.4 EDGE STATUS The CTMUCONL register also contains two status bits: EDG2STAT and EDG1STAT (CTMUCONL). Their primary function is to show if an edge response has occurred on the corresponding channel. The CTMU automatically sets a particular bit when an edge response is detected on its channel. The level-sensitive nature of the input channels also means that the status bits become set immediately if the channel’s configuration is changed and is the same as the channel’s current state. The module uses the edge status bits to control the current source output to external analog modules (such as the A/D Converter). Current is only supplied to external modules when only one (but not both) of the status bits is set, and shuts current off when both bits are either set or cleared. This allows the CTMU to measure current only during the interval between edges. After both status bits are set, it is necessary to clear them before another measurement is taken. Both bits should be cleared simultaneously, if possible, to avoid re-enabling the CTMU current source. In addition to being set by the CTMU hardware, the edge status bits can also be set by software. This is also the user’s application to manually enable or disable the current source. Setting either one (but not both) of the bits enables the current source. Setting or clearing both bits at once disables the source. 20.1.5 INTERRUPTS The CTMU sets its interrupt flag (PIR3) whenever the current source is enabled, then disabled. An interrupt is generated only if the corresponding interrupt enable bit (PIE3) is also set. If edge sequencing is not enabled (i.e., Edge 1 must occur before Edge 2), it is necessary to monitor the edge Status bits and determine which edge occurred last and caused the interrupt. 20.2 CTMU Module Initialization The following sequence is a general guideline used to initialize the CTMU module: 1. Select the current source range using the IRNG bits (CTMUICON). 2. Adjust the current source trim using the ITRIM bits (CTMUICON). 3. Configure the edge input sources for Edge 1 and Edge 2 by setting the EDG1SEL and EDG2SEL bits (CTMUCONL). 4. Configure the input polarities for the edge inputs using the EDG1POL and EDG2POL bits (CTMUCONL). The default configuration is for negative edge polarity (high-to-low transitions). 5. Enable edge sequencing using the EDGSEQEN bit (CTMUCONH). By default, edge sequencing is disabled. 6. Select the operating mode (Measurement or Time Delay) with the TGEN bit. The default mode is Time/Capacitance Measurement. 7. Discharge the connected circuit by setting the IDISSEN bit (CTMUCONH); after waiting a sufficient time for the circuit to discharge, clear IDISSEN. 8. Disable the module by clearing the CTMUEN bit (CTMUCONH). 9. Enable the module by setting the CTMUEN bit. 10. Clear the Edge Status bits: EDG2STAT and EDG1STAT (CTMUCONL). 11. Enable both edge inputs by setting the EDGEN bit (CTMUCONH). Depending on the type of measurement or pulse generation being performed, one or more additional modules may also need to be initialized and configured with the CTMU module: • Edge Source Generation: In addition to the external edge input pins, both Timer1 and the Output Compare/PWM1 module can be used as edge sources for the CTMU. • Capacitance or Time Measurement: The CTMU module uses the A/D Converter to measure the voltage across a capacitor that is connected to one of the analog input channels. • Pulse Generation: When generating system clock independent output pulses, the CTMU module uses Comparator 2 and the associated comparator voltage reference. DS30000684B-page 312  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 20.3 Calibrating the CTMU Module FIGURE 20-2: The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary. An example of this type of application would include a capacitive touch switch, in which the touch circuit has a baseline capacitance, and the added capacitance of the human body changes the overall capacitance of a circuit. If actual capacitance or time measurement is required, two hardware calibrations must take place: the current source needs calibration to set it to a precise current, and the circuit being measured needs calibration to measure and/or nullify all other capacitance other than that to be measured. 20.3.1 4. 5. 6. PIC18(L)FXXK50 Device CTMU Current Source A/D Converter ANx RCAL A/D MUX CURRENT SOURCE CALIBRATION The current source on the CTMU module is trimmable. Therefore, for precise measurements, it is possible to measure and adjust this current source by placing a high precision resistor, RCAL, onto an unused analog channel. An example circuit is shown in Figure 20-2. The current source measurement is performed using the following steps: 1. 2. 3. CTMU CURRENT SOURCE CALIBRATION CIRCUIT Initialize the A/D Converter. Initialize the CTMU. Enable the current source by setting EDG1STAT (CTMUCONL). Issue settling time delay. Perform A/D conversion. Calculate the current source current using I = V/ RCAL, where RCAL is a high precision resistance and V is measured by performing an A/D conversion. A value of 70% of full-scale voltage is chosen to make sure that the A/D Converter was in a range that is well above the noise floor. Keep in mind that if an exact current is chosen, that is to incorporate the trimming bits from CTMUICON, the resistor value of RCAL may need to be adjusted accordingly. RCAL may also be adjusted to allow for available resistor values. RCAL should be of the highest precision available, keeping in mind the amount of precision needed for the circuit that the CTMU will be used to measure. A recommended minimum would be 0.1% tolerance. The following examples show one typical method for performing a CTMU current calibration. Example 20-1 demonstrates how to initialize the A/D Converter and the CTMU; this routine is typical for applications using both modules. Example 20-2 demonstrates one method for the actual calibration routine. The CTMU current source may be trimmed with the trim bits in CTMUICON using an iterative process to get an exact desired current. Alternatively, the nominal value without adjustment may be used; it may be stored by the software for use in all subsequent capacitive or time measurements. To calculate the value for RCAL, the nominal current must be chosen, and then the resistance can be calculated. For example, if the A/D Converter reference voltage is 3.3V, use 70% of full scale, or 2.31V as the desired approximate voltage to be read by the A/D Converter. If the range of the CTMU current source is selected to be 0.55 A, the resistor value needed is calculated as RCAL = 2.31V/0.55 A, for a value of 4.2 MΩ. Similarly, if the current source is chosen to be 5.5 A, RCAL would be 420,000Ω, and 42,000Ω if the current source is set to 55 A.  2012-2014 Microchip Technology Inc. DS30000684B-page 313 PIC18(L)F2X/45K50 EXAMPLE 20-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.h" /**************************************************************************/ /*Set up CTMU *****************************************************************/ /**************************************************************************/ void setup(void) { //CTMUCONH/1 - CTMU Control registers CTMUCONH = 0x00; //make sure CTMU is disabled CTMUCONL = 0x90; //CTMU continues to run when emulator is stopped,CTMU continues //to run in idle mode,Time Generation mode disabled, Edges are blocked //No edge sequence order, Analog current source not grounded, trigger //output disabled, Edge2 polarity = positive level, Edge2 source = //source 0, Edge1 polarity = positive level, Edge1 source = source 0, //CTMUICON - CTMU Current Control Register CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment /**************************************************************************/ //Set up AD converter; /**************************************************************************/ TRISA=0x04; //set channel 2 as an input // Configure AN2 as an analog channel ANSELAbits.ANSA2=1; TRISAbits.TRISA2=1; // ADCON2 ADCON2bits.ADFM=1; ADCON2bits.ACQT=1; ADCON2bits.ADCS=2; // ADCON1 ADCON1bits.PVCFG0 =0; ADCON1bits.NVCFG1 =0; // ADCON0 ADCON0bits.CHS=2; ADCON0bits.ADON=1; // Results format 1= Right justified // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD // Clock conversion bits 6= FOSC/64 2=FOSC/32 // Vref+ = AVdd // Vref- = AVss // Select ADC channel // Turn on ADC } DS30000684B-page 314  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 EXAMPLE 20-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i VDD)(4)  20 mA Maximum output current sunk by any I/O pin ...............................................................................................................................25 mA sourced by any I/O pin ..........................................................................................................................25 mA Maximum current sunk byall ports (-40°C to +125°C) ................................................................................................... 110 mA sourced by all ports (-40°C to +125°C) .................................................................................................70 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RE3 pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP/ RE3 pin, rather than pulling this pin directly to VSS. 3: VUSB3V3 must always be VDD + 0.3V. VUSB3V3 must also be maintained VDD – 0.3V on PIC18LF2X/ 45K50 devices. 4: Stress rating only. For proper functional operation, I/O pins should be maintained within the -0.3V to (VDD + 0.3V) range, which will not result in injected current. See TB3013 technical brief (DS93013) for details. 5: The original Universal Serial Bus Specification Revision 2.0 indicated that USB devices should withstand 24-hour short circuits of D+ or D- to VBUS voltages. This requirement was later removed in an Engineering Change Notice (ECN) supplement to the USB specifications, which supersedes the original specifications. PIC18F2X/45K50 family devices will typically be able to survive this short-circuit test, but it is recommended to adhere to the absolute maximum specified here to avoid damaging the device. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. DS30000684B-page 444  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 29.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage PIC18LF2X/45K50 VDDMIN (Fosc  4 MHz, Industrial Temperature)...................................................................... +1.8V VDDMIN (Fosc  48 MHz) ......................................................................................................... +2.7V VDDMAX .................................................................................................................................... +3.6V PIC18F2X/45K50 VDDMIN (Fosc  20 MHz, Industrial Temperature).................................................................... +2.3V VDDMIN (Fosc  16 MHz, Extended Temperature) ................................................................... +2.3V VDDMIN (Fosc  48 MHz) ......................................................................................................... +2.7V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Extended Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................. +125°C  2012-2014 Microchip Technology Inc. DS30000684B-page 445 PIC18(L)F2X/45K50 FIGURE 29-1: PIC18LF2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL AND EXTENDED TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 4 16 20 48 Frequency (MHz) Note 1: Maximum Frequency 4 MHz, 1.8V to 2.7V, -40°C to +85°C 2: Maximum Frequency 48 MHz, 2.7V to 3.6V, -40°C to +85°C FIGURE 29-2: PIC18F2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 20 30 40 48 Frequency (MHz) Note 1: Maximum Frequency 20 MHz, 2.3V to 2.7V, -40°C to +85°C 2: Maximum Frequency 48 MHz, 2.7V to 5.5V, -40°C to +85°C DS30000684B-page 446  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 29-3: PIC18F2X/45K50 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 5.5V Voltage 5.0V 4.0V 3.6V 3.0V 2.7V 2.3V 1.8V 10 16 20 30 40 48 60 64 Frequency (MHz) Note 1: Maximum Frequency 16 MHz, 2.3V to 2.7V, +85°C to +125°C 2: Maximum Frequency 48 MHz, 2.7V to 5.5V, +85°C to +125°C  2012-2014 Microchip Technology Inc. DS30000684B-page 447 PIC18(L)F2X/45K50 29.3 DC Characteristics TABLE 29-1: SUPPLY VOLTAGE, PIC18(L)F2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18(L)F2X/45K50 Param. Symbol No. D001 VDD Characteristic Supply Voltage Min. Typ. Max. Units Conditions PIC18LF2X/45K50 1.8 — 3.6 V Regulator disabled PIC18F2X/45K50 2.3 — 5.5 V Regulator enabled 3.0 3.3 3.6 V USB module enabled D001B VUSB3V3 USB Supply Voltage VUSB3V3 Capacitor Charging (PIC18F2X/45K50) D001C D001D Charging current — 200 — mA Note 4, 5 Source/sink capability when charging is complete — 0.0 — mA Note 4 D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — — 0.7 V D004 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — D005 VBOR Brown-out Reset Voltage BORV = 11(2) 1.75 1.9 2.05 V BORV = 10 2.05 2.2 2.35 V BORV = 01 2.35 2.5 2.65 V 2.65 2.85 3.05 V 1.8V V BORV = 00 D006 VLPBOR Note 1: 2: 3: 4: 5: (3) Low-Power Brown-out Reset (LPBOR) Voltage — 2.1 See section on Power-on Reset for details V/ms See section on Power-on Reset for details This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. On LF devices with BOR enabled, operation is supported until a BOR occurs. This is valid although VDD may be below the minimum rated supply voltage. With BOR enabled, full-speed operation (FOSC = 48 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency. This is the inrush current associated with initial charging of the VUSB3V3 capacitor during a fast VDD ramp. The microcontroller can still start-up from VDD power sources that are limited to significantly less than this value. The VUSB3V3 regulator is only designed to supply the current requirements of the microcontroller and USB transceiver. It is not intended to supply external loads. DS30000684B-page 448  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-2: POWER-DOWN CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Typ. Typ. Max. Max. Units +25°C +60°C +85°C +125°C Device Characteristics Power-down Base Current D006 Conditions VDD Notes WDT, BOR, FVR and SOSC disabled, all Peripherals inactive (IPD)(1) Sleep mode 0.01 0.04 2 10 A 1.8V 0.01 0.06 2 40 A 3.0V 12 13 25 35 A 2.3V 13 14 30 40 A 3.0V 13 14 35 50 A 5.0V 2.5 2.5 A 1.8V Power-down Module Differential Current (delta IPD) D007 Watchdog Timer Brown-out Reset(2) D008 High/Low Voltage Detect(2) D010 D011 Secondary Oscillator Note 1: 2: 3: 0.3 0.3 0.5 0.5 2.5 5 A 3.0V 0.35 0.35 5.0 5.0 A 2.3V 0.5 0.5 5.0 5.0 A 3.0V 0.5 0.5 5.0 5.0 A 5.0V 8 8.5 15 16 A 2.0V 9 9.5 15 16 A 3.0V 3.4 3.4 15 16 A 2.3V 3.8 3.8 15 16 A 3.0V 5.2 5.2 15 16 A 5.0V 6.5 6.7 15 15 A 2.0V 7 7.5 15 15 A 3.0V 2.1 2.1 15 15 A 2.3V 2.4 2.4 15 15 A 3.0V 3.2 3.2 15 15 A 5.0V 0.5 1 3 10 A 1.8V 0.6 1.1 4 10 A 3.0V 0.5 1 3 10 A 2.3V 0.6 1.1 4 10 A 3.0V 0.6 1.1 5 10 A 5.0V 32 kHz on SOSC The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). On LF devices, the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On F devices, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete.  2012-2014 Microchip Technology Inc. DS30000684B-page 449 PIC18(L)F2X/45K50 TABLE 29-2: POWER-DOWN CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Typ. Typ. Max. Max. Units +25°C +60°C +85°C +125°C D015 Device Characteristics Comparators D16 Comparators D017 DAC FVR(2) D018 D013 A/D Note 1: 2: 3: Converter(3) 7 7 18 18 Conditions VDD A 1.8V 7 7 18 18 A 3.0V 7 7 18 18 A 2.3V 7 7 18 18 A 3.0V 8 8 20 20 A 5.0V 38 38 95 95 A 1.8V 40 40 105 105 A 3.0V 39 39 95 95 A 2.3V 40 40 105 105 A 3.0V 40 40 105 105 A 5.0V 12 12 22 25 A 1.8V 20 20 35 35 A 3.0V 15 15 30 30 A 2.3V 20 20 35 35 A 3.0V 32 32 60 60 A 5.0V 15 16 25 25 A 1.8V 15 16 25 25 A 3.0V 28 28 45 45 A 2.3V 31 31 55 55 A 3.0V 66 66 100 100 A 5.0V 185 185 370 370 A 1.8V 210 210 400 400 A 3.0V 200 200 380 380 A 2.3V 210 210 400 400 A 3.0V 250 250 450 450 A 5.0V Notes LP mode HP mode A/D on, not converting The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). On LF devices, the BOR, HLVD and FVR enable internal band gap reference. With more than one of these modules enabled, the current consumption will be less than the sum of the specifications. On F devices, the internal band gap reference is always enabled and its current consumption is included in the Power-down Base Current (IPD). A/D converter differential currents apply only in Run mode. In Sleep or Idle mode both the ADC and the FRC turn off as soon as conversion (if any) is complete. DS30000684B-page 450  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-3: RC RUN SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics No. Typ. Max. Units Supply Current (IDD)(1),(2) D020 D021 D022 D023 D024 Note 1: 2: Conditions 3.6 23 A -40°C 3.9 25 A +25°C 3.9 — A +60°C 3.9 28 A +85°C 4.0 30 A +125°C 8.1 26 A -40°C 8.4 30 A +25°C 8.6 — A +60°C 8.7 35 A +85°C 10.7 40 A +125°C 16 35 A -40°C 17 35 A +25°C 18 35 A +85°C 19 50 A +125°C 18 50 A -40°C 20 50 A +25°C 21 50 A +85°C 22 60 A +125°C 19 55 A -40°C 21 55 A +25°C 22 55 A +85°C 23 70 A +125°C VDD = 1.8V FOSC = 31 kHz (RC_RUN mode, INTRC source) VDD = 3.0V VDD = 2.3V FOSC = 31 kHz (RC_RUN mode, INTRC source) VDD = 3.0V VDD = 5.0V The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2012-2014 Microchip Technology Inc. DS30000684B-page 451 PIC18(L)F2X/45K50 TABLE 29-3: RC RUN SUPPLY CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. Device Characteristics No. Typ. Max. Units D030 0.35 0.50 mA -40°C to +125°C VDD = 1.8V D031 0.45 0.65 mA -40°C to +125°C VDD = 3.0V D032 0.40 0.60 mA -40°C to +125°C VDD = 2.3V D033 0.50 0.65 mA -40°C to +125°C VDD = 3.0V D034 0.55 0.75 mA -40°C to +125°C VDD = 5.0V Conditions FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) FOSC = 1 MHz (RC_RUN mode, HFINTOSC source) D035 1.3 2.0 mA -40°C to +125°C VDD = 1.8V D036 2.2 3.0 mA -40°C to +125°C VDD = 3.0V D037 1.7 2.0 mA -40°C to +125°C VDD = 2.3V D038 2.2 3.0 mA -40°C to +125°C VDD = 3.0V D039 2.5 3.5 mA -40°C to +125°C VDD = 5.0V D041 6.2 8.5 mA -40°C to +125°C VDD = 3.0V FOSC = 48 MHz (RC_RUN mode, HFINTOSC + PLL source) D043 6.2 8.5 mA -40°C to +125°C VDD = 3.0V D044 6.8 9.5 mA -40°C to +125°C VDD = 5.0V FOSC = 48 MHz (RC_RUN mode, HFINTOSC + PLL source) Note 1: 2: FOSC = 16 MHz (RC_RUN mode, HFINTOSC source) FOSC = 16 MHz (RC_RUN mode, HFINTOSC source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS30000684B-page 452  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-4: RC IDLE SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Typ. Supply Current (IDD)(1),(2) 0.5 18 A -40°C 0.6 18 A +25°C 0.7 — A +60°C 0.75 20 A +85°C 2.3 22 A +125°C 1.1 20 A -40°C 1.2 20 A +25°C 1.3 — A +60°C 1.4 22 A +85°C 3.2 25 A +125°C 17 30 A -40°C 13 30 A +25°C 14 30 A +85°C 15 45 A +125°C 19 35 A -40°C 15 35 A +25°C 16 35 A +85°C 17 50 A +125°C 21 40 A -40°C 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C D045 D046 D047 D048 D049 Note 1: 2: Max. Units Conditions VDD = 1.8V FOSC = 31 kHz (RC_IDLE mode, INTRC source) VDD = 3.0V VDD = 2.3V FOSC = 31 kHz (RC_IDLE mode, INTRC source) VDD = 3.0V VDD = 5.0V The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2012-2014 Microchip Technology Inc. DS30000684B-page 453 PIC18(L)F2X/45K50 TABLE 29-4: RC IDLE SUPPLY CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Typ. Max. Units D055 0.25 0.40 mA -40°C to +125°C VDD = 1.8V D056 0.35 0.50 mA -40°C to +125°C VDD = 3.0V D057 0.30 0.45 mA -40°C to +125°C VDD = 2.3V D058 0.40 0.50 mA -40°C to +125°C VDD = 3.0V D059 0.45 0.60 mA -40°C to +125°C VDD = 5.0V D060 0.50 0.7 mA -40°C to +125°C VDD = 1.8V D061 0.80 1.1 mA -40°C to +125°C VDD = 3.0V D062 0.65 1.0 mA -40°C to +125°C VDD = 2.3V D063 0.80 1.1 mA -40°C to +125°C VDD = 3.0V D064 0.95 1.2 mA -40°C to +125°C VDD = 5.0V D066 2.5 3.5 mA -40°C to +125°C VDD = 3.0V FOSC = 48 MHz (RC_IDLE mode, HFINTOSC + PLL source) D068 2.5 3.5 mA -40°C to +125°C VDD = 3.0V D069 3.0 4.5 mA -40°C to +125°C VDD = 5.0V FOSC = 48 MHz (RC_IDLE mode, HFINTOSC + PLL source) Note 1: 2: Device Characteristics Conditions FOSC = 1 MHz (RC_IDLE mode, HFINTOSC source) FOSC = 1 MHz (RC_IDLE mode, HFINTOSC source) FOSC = 16 MHz (RC_IDLE mode, HFINTOSC source) FOSC = 16 MHz (RC_IDLE mode, HFINTOSC source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS30000684B-page 454  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-5: PRIMARY RUN SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Typ. Max. Units Supply Current (IDD)(1),(2) 0.11 0.20 mA -40°C to +125°C VDD = 1.8V D071 0.17 0.25 mA -40°C to +125°C VDD = 3.0V D072 0.15 0.25 mA -40°C to +125°C VDD = 2.3V D073 0.20 0.30 mA -40°C to +125°C VDD = 3.0V D074 0.25 0.35 mA -40°C to +125°C VDD = 5.0V D075 1.45 2.0 mA -40°C to +125°C VDD = 1.8V D076 2.60 3.5 mA -40°C to +125°C VDD = 3.0V D077 1.95 2.5 mA -40°C to +125°C VDD = 2.3V D078 2.65 3.5 mA -40°C to +125°C VDD = 3.0V D079 2.95 4.5 mA -40°C to +125°C VDD = 5.0V D080 7.5 10 mA -40°C to +125°C VDD = 3.0V FOSC = 48 MHz (PRI_RUN, ECH oscillator) D081 7.5 10 mA -40°C to +125°C VDD = 3.0V D082 8.5 11.5 mA -40°C to +125°C VDD = 5.0V FOSC = 48 MHz (PRI_RUN mode, ECH source) D083 1.0 1.5 mA -40°C to +125°C VDD = 1.8V D084 1.8 3.0 mA -40°C to +125°C VDD = 3.0V D085 1.4 2.0 mA -40°C to +125°C VDD = 2.3V D086 1.85 2.5 mA -40°C to +125°C VDD = 3.0V D087 2.1 3.0 mA -40°C to +125°C VDD = 5.0V D088 6.35 9.0 mA -40°C to +125°C VDD = 3.0V FOSC = 16 MHz 48 MHz Internal (PRI_RUN mode, ECH + PLL source) D089 6.35 9.0 mA -40°C to +125°C VDD = 3.0V D090 7.0 10 mA -40°C to +125°C VDD = 5.0V FOSC = 16 MHz 48 MHz Internal (PRI_RUN mode, ECH + PLL source) D070 Note 1: 2: Conditions FOSC = 1 MHz (PRI_RUN mode, ECM source) FOSC = 1 MHz (PRI_RUN mode, ECM source) FOSC = 20 MHz (PRI_RUN mode, ECH source) FOSC = 20 MHz (PRI_RUN mode, ECH source) FOSC = 4 MHz 16 MHz Internal (PRI_RUN mode, ECM + PLL source) FOSC = 4 MHz 16 MHz Internal (PRI_RUN mode, ECM + PLL source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only).  2012-2014 Microchip Technology Inc. DS30000684B-page 455 PIC18(L)F2X/45K50 TABLE 29-6: PRIMARY IDLE SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Typ. Device Characteristics Supply Current (IDD)(1),(2) D100 Max. Units Conditions 0.030 0.050 mA -40°C to +125°C VDD = 1.8V D101 0.045 0.065 mA -40°C to +125°C VDD = 3.0V D102 0.06 0.12 mA -40°C to +125°C VDD = 2.3V D103 0.08 0.15 mA -40°C to +125°C VDD = 3.0V D104 0.13 0.20 mA -40°C to +125°C VDD = 5.0V D105 0.45 0.8 mA -40°C to +125°C VDD = 1.8V D106 0.70 1.0 mA -40°C to +125°C VDD = 3.0V D107 0.55 0.8 mA -40°C to +125°C VDD = 2.3V D108 0.75 1.0 mA -40°C to +125°C VDD = 3.0V D109 0.90 1.2 mA -40°C to +125°C VDD = 5.0V D110 2.25 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 48 MHz (PRI_IDLE mode, ECH source) D111 2.25 3.0 mA -40°C to +125°C VDD = 3.0V D112 2.60 3.5 mA -40°C to +125°C VDD = 5.0V Fosc = 48 MHz (PRI_IDLE mode, ECH source) D113 0.35 0.6 mA -40°C to +125°C VDD = 1.8V D114 0.55 0.8 mA -40°C to +125°C VDD = 3.0V D115 0.45 0.6 mA -40°C to +125°C VDD = 2.3V D116 0.60 0.9 mA -40°C to +125°C VDD = 3.0V D117 0.70 1.0 mA -40°C to +125°C VDD = 5.0V D118 2.2 3.0 mA -40°C to +125°C VDD = 3.0V Fosc = 16 MHz 48 MHz Internal (PRI_IDLE mode, ECH + PLL source) D119 2.2 3.0 mA -40°C to +125°C VDD = 3.0V D120 2.5 3.5 mA -40°C to +125°C VDD = 5.0V Fosc = 16 MHz 48 MHz Internal (PRI_IDLE mode, ECH + PLL source) Note 1: 2: Fosc = 1 MHz (PRI_IDLE mode, ECM source) Fosc = 1 MHz (PRI_IDLE mode, ECM source) Fosc = 20 MHz (PRI_IDLE mode, ECH source) Fosc = 20 MHz (PRI_IDLE mode, ECH source) Fosc = 4 MHz 16 MHz Internal (PRI_IDLE mode, ECM + PLL source) Fosc = 4 MHz 16 MHz Internal (PRI_IDLE mode, ECM + PLL source) The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; OSC1 = external square wave, from rail-to-rail (PRI_RUN and PRI_IDLE only). DS30000684B-page 456  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-7: SECONDARY OSCILLATOR SUPPLY CURRENT, PIC18(L)F2X/45K50 PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Typ. Supply Current (IDD)(1),(2) 3.5 23 A -40°C 3.7 25 A +25°C 3.8 — A +60°C 4.0 28 A +85°C 5.1 30 A +125°C 6.2 26 A -40°C 6.4 30 A +25°C 6.5 — A +60°C 6.8 35 A +85°C 7.8 40 A +125°C 15 35 A -40°C 16 35 A +25°C 17 35 A +85°C 19 50 A +125°C 18 50 A -40°C 19 50 A +25°C 21 50 A +85°C 22 60 A +125°C 19 55 A -40°C 20 55 A +25°C 22 55 A +85°C 23 70 A +125°C D130 D131 D132 D133 D134 Note 1: 2: Max. Units Conditions VDD = 1.8V Fosc = 32 kHz (SEC_RUN mode, SOSC source) VDD = 3.0V VDD = 2.3V Fosc = 32 kHz (SEC_RUN mode, SOSC source) VDD = 3.0V VDD = 5.0V The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail.  2012-2014 Microchip Technology Inc. DS30000684B-page 457 PIC18(L)F2X/45K50 TABLE 29-7: SECONDARY OSCILLATOR SUPPLY CURRENT, PIC18(L)F2X/45K50 (CONTINUED) PIC18LF2X/45K50 Standard Operating Conditions (unless otherwise stated) PIC18F2X/45K50 Standard Operating Conditions (unless otherwise stated) Param. No. Typ. Device Characteristics D135 D136 D137 D138 D139 Note 1: 2: Max. Units Conditions 0.9 18 A -40°C 1.0 18 A +25°C 1.1 — A +60°C 1.3 20 A +85°C 2.3 22 A +125°C 1.3 20 A -40°C 1.4 20 A +25°C 1.5 — A +60°C 1.8 22 A +85°C 2.9 25 A +125°C 12 30 A -40°C 13 30 A +25°C 14 30 A +85°C 16 45 A +125°C 13 35 A -40°C 14 35 A +25°C 16 35 A +85°C 18 50 A +125°C 14 40 A -40°C 15 40 A +25°C 16 40 A +85°C 18 60 A +125°C VDD = 1.8V Fosc = 32 kHz (SEC_IDLE mode, SOSC source) VDD = 3.0V VDD = 2.3V Fosc = 32 kHz (SEC_IDLE mode, SOSC source) VDD = 3.0V VDD = 5.0V The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/ O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. Test condition: All Peripheral Module Control bits in PMD0 and PMD1 set to ‘1’. The test conditions for all IDD measurements in active operation mode are: All I/O pins set as outputs driven to Vss; MCLR = VDD; SOSCI / SOSCO = complementary external square wave, from rail-to-rail. DS30000684B-page 458  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-8: INPUT/OUTPUT CHARACTERISTICS, PIC18(L)F2X/45K50 DC CHARACTERISTICS Param. Symbol No. VIL Standard Operating Conditions (unless otherwise stated) Characteristic Min. Typ.† Max. Units Conditions — — 0.8 V 4.5V  VDD  5.5V — — 0.15 VDD V 1.8V  VDD  4.5V 2.0V  VDD  5.5V Input Low Voltage I/O PORT: D140 with TTL buffer D140A D141 D142 with Schmitt Trigger buffer — — 0.2 VDD V with I2C™ levels — — 0.3 VDD V with SMBus levels — — 0.8 V — — 0.2 VDD V — — 0.3 VDD V MCLR, OSC1 (RC D142A mode)(1) OSC1 (HS mode) VIH 2.7V  VDD  5.5V Input High Voltage I/O ports: D147 with TTL buffer D147A with Schmitt Trigger buffer D148 with I2C levels with SMBus levels 2.0 — — V 4.5V  VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V  VDD  4.5V 0.8 VDD — — V 2.0V  VDD  5.5V 0.7 VDD — — V 2.1 — — V D149 MCLR 0.8 VDD — — V D150A OSC1 (HS mode) 0.7 VDD — — V D150B OSC1 (RC mode)(1) 0.9 VDD — — V IIL D155 D158 Note 1: 2: 3: 4: VSS VPIN VDD, Pin at high-impedance Input Leakage I/O and MCLR(2),(3) I/O ports and MCLR IPU Weak Pull-up Current(4) IPURB PORTB weak pull-up current 2.7V  VDD  5.5V — — — 0.1 0.7 4 50 100 200 nA nA nA +25°C(4) +60°C +85°C 25 85 200 A VDD = 3.3V, VPIN = VSS 25 130 300 A VDD = 5.0V, VPIN = VSS In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested.  2012-2014 Microchip Technology Inc. DS30000684B-page 459 PIC18(L)F2X/45K50 TABLE 29-8: INPUT/OUTPUT CHARACTERISTICS, PIC18(L)F2X/45K50 (CONTINUED) DC CHARACTERISTICS Param. Symbol No. VOL D159 Standard Operating Conditions (unless otherwise stated) Characteristic IPUMCLR MCLR and ICRST weak pull-up current VOH D161 2: 3: 4: Max. Units Conditions — — 0.6 V IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V 25 85 200 A VDD = 3.3V, VPIN = VSS 25 130 300 A VDD = 5.0V, VPIN = VSS VDD - 0.7 — — V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V (3) Output High Voltage I/O ports Note 1: Typ.† Output Low Voltage I/O ports D160 Min. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC® device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. DS30000684B-page 460  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-9: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions Internal Program Memory Programming Specifications(1) D170 VPP Voltage on MCLR/VPP pin 8 — 9 V D171 IDDP Supply Current during Programming — — 10 mA 100K — — E/W VDDMIN — VDDMAX V (Note 3), (Note 4) Data EEPROM Memory D172 ED Byte Endurance D173 VDRW VDD for Read/Write D175 TDEW Erase/Write Cycle Time — 3 4 ms D176 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D177 TREF 1M 10M — E/W -40°C to +85°C -40C to +85C (Note 5) Number of Total Erase/Write Cycles before Refresh(2) -40C to +85C Using EECON to read/ write Program Flash Memory D178 EP Cell Endurance D179 VPR VDD for Read D181 VIW VDD for Row Erase or Write D182 VIW D183 TIW D184 TRETD Characteristic Retention Self-timed Write Cycle Time 10K — — E/W VDDMIN — VDDMAX V 2.2 — VDDMAX V PIC18LF2X/45K50 VDDMIN — VDDMAX V PIC18F2X/45K50 — 2 — ms — 40 — Year Provided no other specifications are violated † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Refer to Section 8.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. 5: Self-write and Block Erase.  2012-2014 Microchip Technology Inc. DS30000684B-page 461 PIC18(L)F2X/45K50 TABLE 29-10: USB MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. D313 Sym. Characteristic Min. Typ. Max. Units VUSB USB Voltage 3.0 — 3.6 V Input Leakage on pin Conditions Voltage on VUSB3V3 pin must be in this range for proper USB operation D314 IIL — — ±1 A VSS VPIN VDD pin athighimpedance D315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V For VUSB3V3 range D316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V For VUSB3V3 range D318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between D+ and D- must exceed this value while VCM is met D319 VCM Differential Common Mode Range 0.8 — 2.5 V D320 ZOUT Driver Output Impedance(1) 28 — 44  D321 VOL Voltage Output Low 0.0 — 0.3 V 1.5 kload connected to 3.6V D322 VOH Voltage Output High 2.8 — 3.6 V 1.5 kload connected to ground D323 CUSB VUSB Capacitor Value 0.33 0.47 8 µF Note 1: The D+ and D- signal lines have been built-in impedance matching resistors. No external resistors, capacitors or magnetic components are necessary on the D+/D- signal paths between the PIC18(L)F2X/ 45K50 family device and USB cable. DS30000684B-page 462  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 29.4 Analog Characteristics TABLE 29-11: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. CM01 Input Common-mode Voltage VICM CM04* TRESP TMC2OV CM05* * Note 1: Input Offset Voltage VIOFF CM02 Characteristics Response Time (1) Comparator Mode Change to Output Valid Min. Typ. Max. Units Comments — 3 30 mV High-Power mode VREF = VDD/2 — 4 40 mV Low-Power mode VREF = VDD/2 VSS — VDD V — 200 400 ns High-Power mode — 600 3500 ns Low-Power mode — — 10 s These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. TABLE 29-12: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) 2.0V < VDD < 5.5V, -40°C < TA < +125°C Param. No. Sym. Characteristics Min. Typ. Max. Units CV01* CLSB Step Size(2) — VDD/32 — V CV02* CACC Absolute Accuracy — — 1/2 LSb CV03* CR Unit Resistor Value (R) — 5k —  CV04* CST Time(1) — — 10 s CV05* VSRC+ DAC Positive Reference CV06* VSRC- CV07* VSRC DAC Reference Range (VSRC+ - VSRC-) * Note 1: 2: Settling DAC Negative Reference VSRC- + 2 — VDD V VSS — VSRC+ – 2 V 2 — VDD V Comments VSRC 2.0V These parameters are characterized but not tested. Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from ‘0000’ to ‘1111’. See Section 23.0 “Digital-to-Analog Converter (DAC) Module” for more information.  2012-2014 Microchip Technology Inc. DS30000684B-page 463 PIC18(L)F2X/45K50 TABLE 29-13: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. VR01 Sym. VROUT VR02 VROUT VR04* TSTABLE * Characteristics VR voltage output to ADC VR voltage output all other modules Settling Time Min. Typ. Max. Units Comments 0.973 1.024 1.085 V 1x output, VDD 2.5V 1.946 2.048 2.171 V 2x output, VDD 2.5V 3.891 4.096 4.342 V 4x output, VDD 4.75V (PIC18F2X/45K50) 0.942 1.024 1.096 V 1x output, VDD 2.5V 1.884 2.048 2.191 V 2x output, VDD 2.5V 3.768 4.096 4.383 V 4x output, VDD 4.75V (PIC18F2X/45K50) — 25 100 s 0 to 85°C These parameters are characterized but not tested. TABLE 29-14: CHARGE TIME MEASUREMENT UNIT (CTMU) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristics Min. Typ.(1) Max. Units Comments CT01 IOUT1 CTMU Current Source, Base Range — 0.55 — A IRNG = 01 CT02 IOUT2 CTMU Current Source, 10X Range — 5.5 — A IRNG = 10 CT03 IOUT3 CTMU Current Source, 100X Range — 55 — A IRNG = 11 VDD  3.0V Note 1: Nominal value at center point of current trim range (CTMUICON = 000000). FIGURE 29-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD VHLVD (HLVDIF set by hardware) (HLVDIF can be cleared by software) HLVDIF DS30000684B-page 464  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-15: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. Symbol No. D420 — Characteristic HLVDL Min. Typ.† Max. Units HLVD Voltage on VDD Transition High-to-Low 0000 1.69 1.84 1.99 V 0001 1.92 2.07 2.22 V 0010 2.08 2.28 2.48 V 0011 2.24 2.44 2.64 V 0100 2.34 2.54 2.74 V 0101 2.54 2.74 2.94 V 0110 2.62 2.87 3.12 V 0111 2.76 3.01 3.26 V 1000 3.00 3.30 3.60 V 1001 3.18 3.48 3.78 V 1010 3.44 3.69 3.94 V 1011 3.66 3.91 4.16 V 1100 3.90 4.15 4.40 V 1101 4.11 4.41 4.71 V 1110 4.39 4.74 5.09 V 1111 V(HLVDIN pin) Conditions v † Production tested at TAMB = +25°C. Specifications over temperature limits ensured by characterization.  2012-2014 Microchip Technology Inc. DS30000684B-page 465 PIC18(L)F2X/45K50 29.5 AC (Timing) Characteristics 29.5.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C™ specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T13CKI WR Fall High Invalid (High-impedance) Low P R V Z Period Rise Valid High-impedance output access Bus free High Low High Low Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F H I L I2C only AA BUF TCC:ST (I2C specifications only) CC HD Hold SU Setup DAT STA DATA input hold Start condition STO Stop condition ST DS30000684B-page 466  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 29.5.2 TIMING CONDITIONS The temperature and voltages specified in Table 29-16 apply to all timing specifications unless otherwise noted. Figure 29-5 specifies the Load conditions for the timing specifications. TABLE 29-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 29-5: Standard Operating Conditions (unless otherwise stated) Operating voltage VDD range as described in Table 29-1 and Table 29-9. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin VSS CL Pin VSS  2012-2014 Microchip Technology Inc. Legend: RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports DS30000684B-page 467 PIC18(L)F2X/45K50 29.5.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 29-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. Symbol 1A FOSC 1 TOSC Characteristic Min. Max. Units Conditions External CLKIN Frequency(1) DC DC DC 4 16 48 MHz MHz MHz EC, ECIO Oscillator mode (low power) EC, ECIO Oscillator mode (medium power) EC, ECIO Oscillator mode (high power) Oscillator Frequency(1) DC 4 MHz RC Oscillator mode 5 200 kHz LP Oscillator mode 0.1 4 MHz XT Oscillator mode 4 4 MHz HS Oscillator mode, VDD < 2.7V 4 16 MHz HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 4 20 MHz HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) External CLKIN Period(1) 0.25 62.5 20.8 — — — s ns ns EC, ECIO Oscillator mode (low power) EC, ECIO Oscillator mode (medium power) EC, ECIO Oscillator mode (high power) Oscillator Period(1) 250 — ns RC Oscillator mode 5 200 s LP Oscillator mode 0.25 250 10 250 s ns XT Oscillator mode HS Oscillator mode, VDD < 2.7V 62.5 250 ns HS Oscillator mode, VDD 2.7V, Medium-Power mode (HSMP) 50 250 ns HS Oscillator mode, VDD 2.7V, High-Power mode (HSHP) 2 TCY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC 3 TOSL, TOSH External Clock in (OSC1) High or Low Time 2.5 — s LP Oscillator mode 4 Note 1: TOSR, TOSF External Clock in (OSC1) Rise or Fall Time 30 — ns XT Oscillator mode 10 — ns HS Oscillator mode — 50 ns LP Oscillator mode — 20 ns XT Oscillator mode — 7.5 ns HS Oscillator mode Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. DS30000684B-page 468  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS Param. Sym. No. F10 Characteristic Min. Max. Units 4 5 MHz VDD < 2.7V, -40°C to +85°C 4 12 MHz 2.7V  VDD, -40°C to +85°C FOSC 4xPLL Oscillator Frequency Range Conditions F10B FOSC 3xPLL Oscillator Frequency Range 4 4 MHz 2.7V  VDD, -40°C to +85°C F11 FSYS 16 20 MHz VDD < 2.7V, -40°C to +85°C 16 48 MHz 2.7V  VDD, -40°C to +85°C — 2 ms F12 trc On-Chip VCO System Frequency PLL Start-up Time (Lock Time) TABLE 29-19: INTERNAL OSCILLATORS ACCURACY (PIC18(L)F2X/45K50) Standard Operating Conditions (unless otherwise stated) Param. No. OA1 OA1B Characteristic Min. Typ. Units -2 -3 -5 Conditions ±1 +2 % +0°C to +70°C — +2 % +70°C to +85°C — +5 % -40°C to +125°C -40°C to +85°C(2), Active Clock Tune is enabled and locked. HF-INTOSC Accuracy(1) HF-INTOSC Accuracy with Active Clock Tuning (ACT) -0.20 ±0.05 +0.20 % — 0.1 — % 26.5625 — 35.9375 kHz -40°C to +85°C 25 — 37.2 kHz +85°C to +125°C OA1C OSCTUNE Step Size OA2 INTRC Accuracy @ Freq = 31.25 kHz Note 1: 2: Max. Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. Accuracy measured with respect to reference source.  2012-2014 Microchip Technology Inc. DS30000684B-page 469 PIC18(L)F2X/45K50 FIGURE 29-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: New Value Old Value 20, 21 Refer to Figure 29-5 for Load conditions. TABLE 29-20: CLKO AND I/O TIMING REQUIREMENTS Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions 10 TOSH2CKL OSC1  to CLKO  — 75 200 ns Note 1 11 TOSH2CKH OSC1  to CLKO  — 75 200 ns Note 1 12 TCKR CLKO Rise Time — 35 100 ns Note 1 13 TCKF CLKO Fall Time — 35 100 ns Note 1 14 TCKL2IOV CLKO  to Port Out Valid 15 TIOV2CKH Port In Valid before CLKO  16 TCKH2IOI 17 — — 0.5 TCY + 20 ns Note 1 0.25 TCY + 25 — — ns Note 1 Port In Hold after CLKO  0 — — ns Note 1 TOSH2IOV OSC1  (Q1 cycle) to Port Out Valid — 50 150 ns 18 TOSH2IOI OSC1  (Q2 cycle) to Port Input Invalid (I/O in hold time) 100 — — ns 19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 — — ns 20 TIOR Port Output Rise Time — — 40 15 72 32 ns ns VDD = 1.8V VDD = 3.3V – 5.0V 21 TIOF Port Output Fall Time — — 28 15 55 30 ns ns VDD = 1.8V VDD = 3.3V – 5.0V 22† TINP INTx pin High or Low Time 20 — — ns 23† TRBP RB Change KBIx High or Low Time TCY — — ns † These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. DS30000684B-page 470  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 29-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 29-5 for Load conditions. FIGURE 29-9: BROWN-OUT RESET TIMING VDD BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable  2012-2014 Microchip Technology Inc. 36 DS30000684B-page 471 PIC18(L)F2X/45K50 TABLE 29-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min. Typ. Max. Units 2 — — s 4.1 4.7 ms 1:1 prescaler TOSC = OSC1 period 30 TMCL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (no postscaler) 3.5 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — 33 TPWRT Power-up Timer Period 54.8 64.4 74.1 ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset — 2 — s 35 TBOR Brown-out Reset Pulse Width 36 TIVRST Internal Reference Voltage Stable 37 THLVD High/Low-Voltage Detect Pulse Width 38 TCSD CPU Start-up Time 39 TIOBST Time for HF-INTOSC to Stabilize Note 1: 200(1) — — s — 25 35 s 200(1) — — s 5 — 10 s — 0.25 1 ms Conditions VDD  BVDD (see D005) VDD  VHLVD Minimum pulse width that will consistently trigger a Reset or interrupt. Shorter pulses may intermittently trigger a response. FIGURE 29-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1CKI/T3CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 29-5 for Load conditions. DS30000684B-page 472  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-22: TIMER0 AND TIMER1/3 EXTERNAL CLOCK REQUIREMENTS Param. No. Symbol Characteristic 40 TT0H T0CKI High Pulse Width No prescaler 41 TT0L T0CKI Low Pulse Width No prescaler Min. Max. 0.5 TCY + 20 — With prescaler TT0P 10 — ns — ns 10 — ns TCY + 10 — ns Greater of: 20 ns or (TCY + 40)/N — ns TxCKI High Synchronous, no prescaler Time Synchronous, with prescaler 0.5 TCY + 20 — ns 10 — ns Asynchronous 30 — ns TxCKI Low Synchronous, no prescaler Time Synchronous, with prescaler 0.5 TCY + 5 — ns 10 — ns Asynchronous 30 — ns Synchronous Greater of: 20 ns or (TCY + 40)/N — ns Asynchronous 60 — ns DC 50 kHz 2 TOSC 7 TOSC — T0CKI Period No prescaler With prescaler 45 46 47 TT1H TT1L TT1P FT 1 48 TxCKI Input Period TxCKI Clock Input Frequency Range TCKE2TMRL Delay from External TxCKI Clock Edge to Timer Increment FIGURE 29-11: ns 0.5 TCY + 20 With prescaler 42 Units Conditions N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 29-5 for Load conditions.  2012-2014 Microchip Technology Inc. DS30000684B-page 473 PIC18(L)F2X/45K50 TABLE 29-23: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol No. Characteristic 50 TCCL CCPx Input Low Time 51 TCCH CCPx Input High Time No prescaler No prescaler Min. Max. Units 0.5 TCY + 20 — ns With prescaler 10 — ns 0.5 TCY + 20 — ns 10 — ns 3 TCY + 40 N — ns With prescaler 52 TCCP CCPx Input Period 53 TCCR CCPx Output Fall Time — 25 ns 54 TCCF CCPx Output Fall Time — 25 ns FIGURE 29-12: Conditions N = prescale value (1, 4 or 16) EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 29-5 for Load conditions. DS30000684B-page 474  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-24: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0 OR 1) Param. No. Symbol Characteristic Min. Max. Units Conditions 73 TDIV2SCH, TDIV2SCL Setup Time of SDI Data Input to SCK Edge 25 — ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDI Data Input to SCK Edge 25 — ns 75 TDOR SDO Data Output Rise Time — 30 ns Note 1 76 TDOF SDO Data Output Fall Time — 20 ns Note 1 78 TSCR SCK Output Rise Time (Master mode) — 30 ns Note 1 79 TSCF SCK Output Fall Time (Master mode) — 20 ns Note 1 80 TSCH2DOV, SDO Data Output Valid after SCK Edge TSCL2DOV — 20 ns 81 TDOV2SCH, SDO Data Output Setup to SCK Edge TDOV2SCL TCY — ns Note 1: When the slew rate control limiting I/O port feature is disabled. FIGURE 29-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb bit 6 - - - - - -1 LSb bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 29-5 for Load conditions.  2012-2014 Microchip Technology Inc. DS30000684B-page 475 PIC18(L)F2X/45K50 FIGURE 29-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 77 75, 76 MSb In SDI 73 Note: bit 6 - - - -1 LSb In 74 Refer to Figure 29-5 for Load conditions. TABLE 29-25: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0 OR 1) Param. No. Symbol Characteristic 70 TSSL2SCH, SS  to SCK  or SCK  Input TSSL2SCL 71 TSCH SCK Input High Time 72 TSCL SCK Input Low Time 73 Min. Max. Units Conditions TCY — ns Continuous 25 — ns Continuous 30 — ns TDIV2SCH, Setup Time of SDI Data Input to SCK Edge TDIV2SCL 25 — ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDI Data Input to SCK Edge 25 — ns 75 TDOR SDO Data Output Rise Time — 30 ns Note 1 76 TDOF SDO Data Output Fall Time — 20 ns Note 1 77 TSSH2DOZ SS to SDO Output High-Impedance 10 50 ns 80 TSCH2DOV, SDO Data Output Valid after SCK Edge TSCL2DOV — 60 ns Note 1 82 TSSL2DOV SDO Data Output Valid after SS  Edge — 60 ns Note 1 83 TSCH2SSH, SS  after SCK edge TSCL2SSH 1.5 TCY + 40 — ns Note 1: When the slew rate control limiting I/O port feature is disabled. DS30000684B-page 476  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 FIGURE 29-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS 70 SCK (CKP = 0) 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI Note: MSb In 77 bit 6 - - - -1 LSb In 74 Refer to Figure 29-5 for Load conditions. I2C™ BUS START/STOP BITS TIMING FIGURE 29-16: SCL 91 90 93 92 SDA Start Condition Note: Stop Condition Refer to Figure 29-5 for Load conditions.  2012-2014 Microchip Technology Inc. DS30000684B-page 477 PIC18(L)F2X/45K50 TABLE 29-26: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. 90 TSU:STA 91 THD:STA Characteristic Start Condition 100 kHz mode Min. Max. Units Conditions 4700 — ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Setup Time 400 kHz mode 600 — Start Condition 100 kHz mode 4000 — Hold Time 400 kHz mode 600 — Stop Condition 100 kHz mode 4700 — 92 TSU:STO 93 THD:STO Stop Condition Setup Time Hold Time FIGURE 29-17: 400 kHz mode 600 — 100 kHz mode 4000 — 400 kHz mode 600 — ns ns I2C™ BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 29-5 for Load conditions. DS30000684B-page 478  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-27: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 THIGH Characteristic Clock High Time TLOW Clock Low Time TR 103 TF — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz 1.5 TCY — — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 100 kHz mode SDA and SCL Rise Time 100 kHz mode SDA and SCL Fall Time — 300 ns ns CB is specified to be from 10 to 400 pF s Only relevant for Repeated Start condition TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — 400 kHz mode 0.6 — s 91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s 400 kHz mode 0.6 — s 106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 s 107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns 400 kHz mode 100 — ns — s 92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 400 kHz mode 0.6 — s 109 TAA 100 kHz mode — 3500 ns 400 kHz mode — — ns 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF 110 TBUF D102 CB Note 1: 2: Bus Free Time Bus Capacitive Loading CB is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 CB 300 90 Output Valid from Clock Conditions 4.0 SSP Module 102 Max. Units 100 kHz mode SSP Module 101 Min. After this period, the first clock pulse is generated Note 2 Note 1 Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A fast mode I2C™ bus device can be used in a standard mode I2C bus system but the requirement, TSU:DAT  250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line is released.  2012-2014 Microchip Technology Inc. DS30000684B-page 479 PIC18(L)F2X/45K50 MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS FIGURE 29-18: SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 29-5 for Load conditions. TABLE 29-28: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated 2(TOSC)(BRG + 1) — Setup Time 400 kHz mode 2(TOSC)(BRG + 1) — (1) 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — THD:STA Start Condition TSU:STO Stop Condition Setup Time 93 Units 100 kHz mode Hold Time 92 Max. Start Condition 1 MHz mode 91 Min. THD:STO Stop Condition Hold Time 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — (1) 2(TOSC)(BRG + 1) — 1 MHz mode Conditions ns ns Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins. MASTER SSP I2C™ BUS DATA TIMING FIGURE 29-19: 103 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure 29-5 for Load conditions. DS30000684B-page 480  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-29: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min. Max. Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns — 300 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 100 ns 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 1 MHz mode 102 TR SDA and SCL Rise Time (1) 1 MHz mode 103 90 91 TF TSU:STA SDA and SCL Fall Time Start Condition Setup Time THD:STA Start Condition Hold Time 2(TOSC)(BRG + 1) — ms THD:DAT Data Input Hold Time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 ms 107 TSU:DAT 100 kHz mode 250 — ns 92 TSU:STO Stop Condition Setup Time 1 MHz mode 106 Data Input Setup Time 400 kHz mode 100 — ns 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 3500 ns 400 kHz mode — 1000 ns (1) 1 MHz mode — — ns 100 kHz mode 4.7 — ms 400 kHz mode 1.3 — ms — 400 pF 1 MHz mode 109 110 D102 Note 1: 2: TAA TBUF CB Output Valid from Clock Bus Free Time Bus Capacitive Loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated Note 2 Time the bus must be free before a new transmission can start I2C™ Maximum pin capacitance = 10 pF for all pins. A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter 107  250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter 102 + parameter 107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCL line is released.  2012-2014 Microchip Technology Inc. DS30000684B-page 481 PIC18(L)F2X/45K50 FIGURE 29-20: TX/CK RX/DT EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING pin 121 121 pin 120 122 Refer to Figure 29-5 for Load conditions. Note: TABLE 29-30: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No. Symbol 120 Characteristic TCKH2DTV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid Min. Max. Units — 40 ns Conditions 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns Note 1 122 TDTRF Data Out Rise Time and Fall Time — 20 ns Note 1 Note 1: When the slew rate control limiting I/O port feature is disabled. FIGURE 29-21: TX/CK RX/DT EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING pin 125 pin 126 Note: Refer to Figure 29-5 for Load conditions. TABLE 29-31: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. Symbol Characteristic 125 TDTV2CKL SYNC RCV (MASTER & SLAVE) Data Setup before CK  (DT setup time) 126 TCKL2DTL Data Hold after CK  (DT hold time) DS30000684B-page 482 Min. Max. Units 10 — ns 15 — ns Conditions  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 TABLE 29-32: A/D CONVERTER CHARACTERISTICS (PIC18(L)F2X/45K50)(1) Standard Operating Conditions (unless otherwise stated) Operating temperature: Tested at +25°C PIC18(L)F2X/45K50 Param. Symbol No. Characteristic Min. Typ. Max. Units Conditions A01 NR Resolution — — 10 bits VREF  3.0V A03 EIL Integral Linearity Error — ±0.5 ±1 LSb VREF = 3.0V A04 EDL Differential Linearity Error — ±0.5 ±1 LSb VREF  3.0V A06 EOFF Offset Error — ±0.7 ±2 LSb VREF  3.0V A07 EGN Gain Error — ±0.7 ±2 LSb VREF  3.0V A08 ETOTL Total Error — ±0.8 ±3 LSb VREF  3.0V A20 VREF Reference Voltage Range (VREFH – VREFL) 2 — VDD V A21 VREFH Reference Voltage High VDD/2 — VDD + 0.3 V A22 VREFL Reference Voltage Low VSS – 0.3V — VDD/2 V A25 VAIN Analog Input Voltage VREFL — VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source — — 10 k Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. FIGURE 29-22: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK 130 132 9 A/D DATA 8 7 .. . ... 2 OLD_DATA ADRES 1 0 NEW_DATA TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.  2012-2014 Microchip Technology Inc. DS30000684B-page 483 PIC18(L)F2X/45K50 TABLE 29-33: A/D CONVERSION REQUIREMENTS (PIC18(L)F2X/45K50) Standard Operating Conditions (unless otherwise stated) Operating temperature: Tested at +25°C Param. Symbol No. Characteristic Min. Typ. Max. Units 130 TAD A/D Clock Period 1 — 25 s 131 TCNV Conversion Time (not including acquisition time)(1) 12 — 12 TAD 132 TACQ Acquisition Time(2) 1.4 — — s 135 TSWC Switching Time from Convert  Sample — — (Note 3) — 136 TDIS Discharge Time 2 — 2 TAD Note 1: 2: 3: Conditions -40C to +85C VDD = 3V, Rs = 50 ADRES register may be read on the following TCY cycle. The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50 . On the following cycle of the device clock. DS30000684B-page 484  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time.  2012-2014 Microchip Technology Inc. DS30000684B-page 485 PIC18(L)F2X/45K50 31.0 PACKAGING INFORMATION 31.1 Package Marking Information 28-Lead SPDIP (.300”) Example PIC18F25K50 -E/SP e3 1407017 28-Lead SOIC (7.50 mm) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC18F25K50 -E/SO e3 1407017 Example PIC18F25K50 -E/SS e3 1407017 Legend: XX...X Y YY WW NNN e3 * Note: DS30000684B-page 486 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) PIN 1 XXXXXXXX XXXXXXXX YYWWNNN Example PIN 1 18F25K50 -E/ML e3 1407017 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC18F45K50 -E/P e3 1401017 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 PIC18F 45K50 -E/MV e 1407017 3 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2014 Microchip Technology Inc. DS30000684B-page 487 PIC18(L)F2X/45K50 Package Marking Information (Continued) 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS30000684B-page 488 Example 18F45K50 -E/PT e3 1407017 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 31.2 Package Details The following sections give the technical details of the packages.                 !" 3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6&! '! 9'&! 7"')  %! 7,8. 7 7 7: ; < &  & &  = =   ##4 4!!   -  1!& &   = =  "# &  "# >#& .  - --  ##4>#& .  #& 9 * 9#>#& :   *+ 1, - !"   !"#$%&" '  ()"&'"!&) &#*&&&#   +%&, & !& - '! !#.#  &"#' #%!  & "! ! #%!  & "! !! &$#/ !#  '! #&   .0 1,2 1!'!   &$& "! **& "&&  !       * ,1  2012-2014 Microchip Technology Inc. DS30000684B-page 489 PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30000684B-page 490  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS30000684B-page 491 PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30000684B-page 492  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50   #$   %     &'    % !" 3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 6&! '! 9'&! 7"')  %! 99. . 7 7 7: ; < &  :  8&  = ?1, =   ##4 4!!  ?  #& .  #& . 1,  ##49&  1, @ -@ @ 9# 4!!   =  9#>#& ) - -   # %&   @ @ -@  # %&1 && '  @ @ -@ !"   !"#$%&" '  ()"&'"!&) &#*&&&#   ,'% !&  !  & V!W'   - '! !#.#  &"#' #%!  & "! ! #%!  & "! !! &$#'' !#  '! #&   .0 1,2 1!'!   &$& "! **& "&&  ! .32 % '! ("!"*& "&&  (% % '& "  !!        * ,?1 DS30000684B-page 500  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2012-2014 Microchip Technology Inc. DS30000684B-page 501 PIC18(L)F2X/45K50 NOTES: DS30000684B-page 502  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 APPENDIX A: REVISION HISTORY Revision A (08/2012) Initial release. Revision B (07/2014) Updated Figures 2, 4 and 3-1; Updated Section 1.2 (Other Special Features), Section 2.4 (Voltage Regulator Pins (VUSB3V3)) and Section 26.9.1 (Dedicated ICD/ICSP Port); Added note to Section 24.4.1.1 (Buffer Ownership), Updated Tables 3-6 and 3-7; Updated Chapter 29.0 (Electrical Specifications), Chapter 31 (Packaging Information) and the Product Identification System page; Other minor corrections.  2012-2014 Microchip Technology Inc. DS30000684B-page 503 PIC18(L)F2X/45K50 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F24K50 PIC18LF24K50 PIC18F25K50 PIC18LF25K50 PIC18F45K50 PIC18LF45K50 16384 16384 32768 32768 32768 32768 VDD Range 2.3V to 5.5V 1.8V to 3.6V 2.3V to 5.5V 1.8V to 3.6V 2.3V to 5.5V 1.8V to 3.6V I/O Ports Ports A, B, C, (E) Program Memory (Bytes) 10-Bit Analog-to-Digital Module Packages DS30000684B-page 504 Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, Ports A, B, C, D, D, E E 14 input channels 14 input channels 14 input channels 14 input channels 25 input channels 25 input channels 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 40-pin PDIP 40-pin UQFN 44-pin TQFP 40-pin PDIP 40-pin UQFN 44-pin TQFP  2012-2014 Microchip Technology Inc. PIC18(L)F2X/45K50 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2012-2014 Microchip Technology Inc. DS30000684B-page 505 PIC18(L)F2X/45K50 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device: [X](2) - Tape and Reel Option X /XX XXX Temperature Range Package Pattern Blank = standard packaging (tube or tray) T = Tape and Reel(1), (2) Temperature Range: I E Package: ML MV P PT SO SP SS Pattern: b) d) Tape and Reel Option: = = = = = = = a) c) PIC18F45K50, PIC18LF45K50 PIC18F25K50, PIC18LF25K50 PIC18F24K50, PIC18LF24K50 = -40C to +85C = -40C to +125C Examples: PIC18F45K50-E/P 301 = Extended temp., PDIP package, QTP pattern #301. PIC18LF25K50-E/SO = Extended temp., SOIC package. PIC18F45K50-E/P = Extended temp., PDIP package. PIC18F24K50T-E/ML = Tape and reel, Extended temp., QFN package. (Industrial) (Extended) QFN UQFN PDIP TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP SSOP Note 1: 2: Tape and Reel option is available for ML, MV, PT, SO and SS packages with industrial Temperature Range only. Tape and Reel identifier only appears in catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. QTP, SQTP, Code or Special Requirements (blank otherwise) DS30000684B-page 506  2012-2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2012-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-360-0 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2012-2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS30000684B-page 507 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 DS30000684B-page 508 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Dusseldorf Tel: 49-2129-3766400 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Germany - Pforzheim Tel: 49-7231-424750 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Italy - Venice Tel: 39-049-7625286 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Poland - Warsaw Tel: 48-22-3325737 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 03/25/14  2012-2014 Microchip Technology Inc.