SAMA5D2-PTC-EK
SAMA5D2-PTC-EK User's Guide
Scope
This user's guide describes how to use the SAMA5D2 PTC Evaluation Kit (SAMA5D2-PTC-EK).
The SAMA5D2-PTC-EK is used to evaluate the capabilities of the Peripheral Touch Controller (PTC)
designed for the SAMA5D2 series of embedded MPUs. Refer to the Configuration Summary table in the
SAMA5D2 Series Datasheet for the list of MPUs featuring PTC.
© 2017 Microchip Technology Inc.
DS50002709A-page 1
SAMA5D2-PTC-EK
Table of Contents
Scope.............................................................................................................................. 1
1. Introduction................................................................................................................3
1.1.
1.2.
Document Layout......................................................................................................................... 3
Recommended Reading...............................................................................................................3
2. Product Overview...................................................................................................... 4
2.1.
2.2.
2.3.
2.4.
SAMA5D2-PTC-EK Features....................................................................................................... 4
SAMA5D2-PTC-EK Content.........................................................................................................5
Evaluation Kit Specifications........................................................................................................ 5
Power Sources............................................................................................................................. 5
3. Board Components....................................................................................................6
3.1.
3.2.
3.3.
3.4.
3.5.
Board Overview............................................................................................................................6
Function Blocks............................................................................................................................ 9
External Interfaces..................................................................................................................... 31
Debugging Capabilities.............................................................................................................. 35
PIO Usage on Expansion Connectors........................................................................................40
4. Installation and Operation........................................................................................48
4.1.
4.2.
System and Configuration Requirements...................................................................................48
Board Setup............................................................................................................................... 48
5. Appendix A. Schematics and Layouts..................................................................... 49
6. Revision History.......................................................................................................62
6.1.
Rev. A - 12/2017.........................................................................................................................62
The Microchip Web Site................................................................................................ 63
Customer Change Notification Service..........................................................................63
Customer Support......................................................................................................... 63
Microchip Devices Code Protection Feature................................................................. 63
Legal Notice...................................................................................................................64
Trademarks................................................................................................................... 64
Quality Management System Certified by DNV.............................................................65
Worldwide Sales and Service........................................................................................66
© 2017 Microchip Technology Inc.
DS50002709A-page 2
SAMA5D2-PTC-EK
Introduction
1.
Introduction
1.1
Document Layout
The document is organized as follows:
Chapter 1. "Introduction"
•
•
Chapter 2. "Product Overview" – Important information about the SAMA5D2-PTC-EK board
•
Chapter 3. "Board Components" – Specifications of the SAMA5D2-PTC-EK and high-level
description of the major components and interfaces
•
Chapter 4. "Installation and Operation" – Instructions on how to get started with the SAMA5D2PTC-EK
•
Appendix A. "Schematics and Layouts" – SAMA5D2-PTC-EK schematics and layout diagrams
1.2
Recommended Reading
The following Microchip document is available and recommended as a supplemental reference resource:
•
SAMA5D2 Series Datasheet. Lit. Number DS60001476
© 2017 Microchip Technology Inc.
DS50002709A-page 3
SAMA5D2-PTC-EK
Product Overview
2.
Product Overview
2.1
SAMA5D2-PTC-EK Features
The SAMA5D2-PTC-EK follows the Microchip MPU strategy for low cost evaluation kits with maximum
reuse capability, and is built on the SAMA5D2 Xplained Ultra (XULT) hardware and software ecosystem.
This board is mainly dedicated to evaluating the Peripheral Touch Controller capabilities.
Table 2-1. SAMA5D2-PTC-EK Features
Characteristics
Specifications
Components
Processor
SAMA5D27-CU (289-ball BGA) 14x14mm
body, 0.8mm pitch
–
Clock speed
MPU: 24 MHz, 32.768 KHz
PHY: Crystal 25 MHz
–
Memory
Two 16-bit, 2-Gbit DDR2
One 4-Gbit Nand Flash
Winbond W972GG6KB-25
Micron MT29F4G08
One QSPI Flash
Microchip SST26VF064B
One Serial Data Flash (optional)
Microchip SST26VF032B
One EEPROM
Microchip 24AA02E48
Display
One LCD interface connector
RGB, 18 bits
SD/MMC
One standard SD card interface
One microSD card interface
With 3.3V/1.8V power switch
–
USB
One USB host type A
One USB device type MicroAB
With 5V power switch
–
One USB HSIC
Connector not mounted
Ethernet
One ETH PHY
Micrel KSZ8081RN
Debug Port
One JLINK-OB/ JLINK-CDC
One JTAG interface
Embedded JLINK-OB and JLINKCDC (ATSAM3U4C TFBGA100)
Board Monitor
One RGB (Red, Green, Blue) LED
Four push button switches
–
DisableBoot, Reset, WakeUp, User
Free
Expansion
One set of XPRO WINGS connectors
One ITO FLEX connector
Dedicated PTC QTouch
Optional
One Port B connector
Optional
One PIOBU connector
Optional
One mikroBUS connector
–
© 2017 Microchip Technology Inc.
DS50002709A-page 4
SAMA5D2-PTC-EK
Product Overview
Characteristics
Specifications
Components
Board Supply
From USB A and USB JLINK-OB
5VDC
Backup Power Supply SuperCap
2.2
ELNA DSK-3R3H204T614-H2L
SAMA5D2-PTC-EK Content
The SAMA5D2-PTC-EK evaluation kit includes the following:
The SAMA5D2-PTC-EK board
•
•
A USB cable
2.3
Evaluation Kit Specifications
Table 2-2. Evaluation Kit Specifications
2.4
Characteristic
Specification
Board
SAMA5D2-PTC-EK
Board supply voltage
USB-powered
Temperature
Operating: 0°C to +70°C
Storage: –40°C to +85°C
Relative humidity
0 to 90% (non-condensing)
Main board dimensions
135 × 90 × 20 mm
RoHS status
Compliant
Board identification
SAMA5D2 Peripheral Touch Controller Evaluation Kit
Power Sources
Several options are available to power up the SAMA5D2-PTC-EK board:
USB powering through the USB Micro-AB connector (J4 - default configuration)
•
•
Powering through the USB Micro-AB connector on the JLlink-OB Embedded Debugger interface
(J9)
Table 2-3. Electrical Characteristics
Electrical Parameter
Value
Input voltage
5VCC
Maximum input voltage
6VCC
Maximum 3.3VDC current available
1.2A
I/O voltage
3.3V only
© 2017 Microchip Technology Inc.
DS50002709A-page 5
SAMA5D2-PTC-EK
Board Components
3.
Board Components
This section covers the specifications of the SAMA5D2-PTC-EK and provides a high-level description of
the board's major components and interfaces. This document is not intended to provide a detailed
documentation about the processor or about any other component used on the board. It is expected that
the user will refer to the appropriate documents of these devices to access detailed information.
3.1
Board Overview
The fully-featured SAMA5D2-PTC-EK board integrates multiple peripherals and interface connectors, as
shown in the figure below.
3.1.1
Default Jumper Settings
The figure below shows the default jumper settings. Jumpers in red are configuration items and current
measurement points. Jumpers in blue are not populated.
© 2017 Microchip Technology Inc.
DS50002709A-page 6
SAMA5D2-PTC-EK
Board Components
Figure 3-1. Default Jumper Settings
The following table describes the functionality of the jumpers.
Table 3-1. SAMA5D2-PTC-EK Jumper Settings
Jumper Default Function
JP1
Closed VDD_MAIN_5V current measurement
JP2
Closed VDDOSC, VDDUTMII, VDDANA, VDDAUDIOPLL current measurement
JP3
Closed VDDISC + VDDIOP0/1/2 current measurement
JP4
Closed VDDIODDR_MPU current measurement
JP5
Closed VDDCORE current measurement
JP6
Closed VDDBU current measurement
JP7
Open
JP8
Closed Disables NAND_CS (open=disable)
JP9
Open
Enables JTAG-CDC (closed=disable)
JP10
Open
Enables JTAG-OB (closed=disable)
JP11
Open
Erases SAM3U Flash Code (closed = erase)
PIOBU1, PIOBU7
© 2017 Microchip Technology Inc.
DS50002709A-page 7
SAMA5D2-PTC-EK
Board Components
Jumper Default Function
WARNING
3.1.2
Warning: This jumper is reserved for factory configuration and should
never be used by the end user.
JP12
Closed Powers mikroBUS extension (3.3V)
JP13
Open
Disables QSPI
JP14
1-2
Enables 3.3V JLINK-OB, connected to shutdown circuitry
2-3
Enables 3.3V JLINK-OB, always ON
Connectors on Board
The following table describes the interface connectors on the SAMA5D2-PTC-EK.
Table 3-2. SAMA5D2-PTC-EK Board Interface Connectors
Connector
Interfaces to
J1
PIOBU, tamper and analog comparator connector (not populated)
J2
JTAG, 10-pin IDC connector
J3
USB Host B. Supports USB host using a type A connector
J4
USB A Device. Supports USB device using a type Micro-AB connector
J5
USB-C HSIC header (not populated)
J6
Standard SDMMC connector
J7
microSD connector
J8
Ethernet 10/100 RJ45
J9
USB-A MicroAB, JLink-OB port
J10
PCB connector for factory-programming the JLINK-OB/SAM3U
J11, J12
Xplained Pro expansion connectors (PTC-dedicated add-on boards)
J13
PIOs PortB connector
J14
ITO connector
J15 A&B
mikroBUS connector
J16
Expansion TFT LCD connector for display module
© 2017 Microchip Technology Inc.
DS50002709A-page 8
SAMA5D2-PTC-EK
Board Components
3.2
Function Blocks
Figure 3-2. SAMA5D2-PTC-EK Block Diagram
USB A&B
USB-B
Connector
DDR2
SDRAM
System Supplies
Power
Switch
5v
POWER
REGULATORS
USB-A
5v
Connector
USB
Detection
5v
SAMA5D2-PTC-EK
3v3, 2v5,1v8, 1v2
DDR2
SDRAM
Serial
EEprom
SPI
Flash
PortB[0-7]
VBUS
USB
Connector
Nand
Flash
QSPI
Flash
GPIO
Power
Cap
PIOBU Connector
POWER
MONITOR
Leds
JLINK-OB
JLINK-CDC
Tri
State
SHDN
DEBUG
Interface
ETH
PHY
UART
SAMA5D27
RJ45
LCD (18bits)
JTAG
TWI/SPI
JTAG
Switch
JLINK Power
5v/3v3
VDDBU
RGB
Leds
FPC Connector
PTC
ITO Connector
GPIO
Push
Button
3.2.1
Reset, Wkup
DisBoot, User
JLINK-OB
JTAG Interface
Function Select
MPU JTAG
Interface
SDHC0
MikroBUS
Interface
SD Card
Connector
SDHC1
uSD
Connector
XPRO (1&2)
PTC Interface
Processor
®
The SAMA5D2 Series is a high-performance, power-efficient embedded MPU based on the ARM
®
Cortex -A5 processor.
Please refer to the SAMA5D2 Series datasheet for more information.
3.2.2
3.2.2.1
Power Supply Topology and Power Distribution
Input Power Options
Two options are available to power the SAMA5D2-PTC-EK board. The USB-powered operation is the
default configuration and comes from the USB device ports (J4-J9) connected to a PC or a 5VDC supply.
Such USB power source is sufficient to supply the board in most applications. It is important to note that
when the USB-powered operation is used, the USB port down the way has a limited powering capability.
If the USB-B Host port (J3) is required to provide full powering capabilities to the target application, it is
recommended to use an external DC supply instead of a USB power source.
The following figure is a schematic of the power options.
© 2017 Microchip Technology Inc.
DS50002709A-page 9
SAMA5D2-PTC-EK
Board Components
Figure 3-3. Input Powering
JPR1
Jumper
7
6
7
6
2
R1
10K
R0402
1
VDD_MAIN_5V
C12
100nF
C0402
2
1
C1
100nF
C0402
JP1
Header 1X2
U4A
DMP2160UFD
1
2
U1A
DMP2160UFD
VBUS_JLINK
R5
100K
R0402
GND_POWER
GND_POWER
U1B
DMP2160UFD
C2
100nF
C0402
R2
100K
R0402
8
3
8
3
5
4
U4B
DMP2160UFD
4
5
VBUS_USBA
GND_POWER
R6
DNP
R0402
GND_POWER
GND_POWER
Note: USB-powered operation eliminates additional wires and batteries. It is the preferred mode of
operation for any project that requires only a 5V source at up to 500 mA.
Jumper JP1 is used to perform MAIN_5V current measurements on the SAMA5D2-PTC-EK board.
3.2.2.2
Power Supply Requirements and Restrictions
Detailed information on the device power supplies is provided in tables “SAMA5D2 Power Supplies” and
“Power Supply Connections” in the SAMA5D2 Series datasheet.
3.2.2.3
Power-up and Power-down Considerations
Power-up and power-down considerations are described in section “Power Considerations” of the
SAMA5D2 Series datasheet.
CAUTION
3.2.2.4
Caution: The power-up and power-down sequences provided in the SAMA5D2 Series
datasheet must be respected for reliable operation of the device.
Power Management
The board power management uses three types of regulators:
•
•
•
One dual synchronous step-down DC-DC regulator (U2 MIC2230) generates the 3.3V/800mA and
1.8V/800mA power lines and utilizes a high-efficiency, fixed-frequency (2.5 MHz), current-mode
PWM control architecture that requires a minimum number of external components.
One ultra low-dropout linear regulator (U3 MIC47053) generates the 1.25V/500mA from the 1.8V
source.
One high-performance single 2.5V/150mA is used as a VDDFUSE generator (U5 MIC5366).
The main regulators are enabled through a Field Effect Transistor (FET) scheme. The processor can
assert SHDN (a VDDBU-powered I/O) to shut down the regulators to enter Backup mode. All regulators
on the board are also shut down by the action of the SHDN signal.
A 3.3V battery (supercap) is implemented to permanently maintain VDDBU voltage (note: jumper JP6
must be in place). The board can be woken up by action on the PB4 button, which drives the WKUP
signal (also a VDDBU-powered I/O).
The figure below shows the power management scheme.
© 2017 Microchip Technology Inc.
DS50002709A-page 10
SAMA5D2-PTC-EK
Board Components
Figure 3-4. Board Power Management
VDD_MAIN_5V
C3
10uF
C0603
C5
1uF
C0603
R8
100K
R0402
U2
3
EN_1
FPWM#
VDD_1V8
L1
11
7
AVIN
VIN
EN1
EN2
FPWM#
LQH43CN2R2M03L8
L1812
12
EN_VDD_1V25
10
L2
1
OUT2
AGND
VDD_MAIN_5V
4
SW2
OUT1
5
390pF
C0402
VDD_3V3
R9
100K
R0402
LQH43CN2R2M03L
L1812
C11
10uF
C0603
6
PGND
C13
4.7nF
C0402
FPWM#
R10
DNP
R0402
VDD_3V3
GND_POWER
VDD_MAIN_5V
C10
MIC2230-GSYML
MLF3x3mm
13
C4
10uF
C0603
9
2
PGOOD
SW1
EPAD
GND_POWER
GND_POWER
1
2
VDD_1V8
3
4
C6
10uF
C0603
U3
BIAS
EN
GND
PGOOD
IN1
ADJ
IN2
EPAD
C7
100nF
C0402
9
OUT
R248
20K
R0402
8
EN_VDD_1V25
7
6
R249
5
R251
10K
R0402
VDD_3V3
4.7K
R0402
VDD_1V25
R250
3.3K
R0402
GND_POWER
R11
100K
R0402
C9
1uF
C0603
MIC47053YMT
NRST
VDD_MAIN_5V
GND_POWER
GND_POWER
GND_POWER
GND_POWER
3
VDD_3V3
Q4
SOT-23
BC847C
VDD_MAIN_5V
EN_1
R3
100K
R0402
C8
100nF
C0402
SHDN
3
Q1
BSS138
SOT23_123
1
2
GND_POWER
STARTB
Q3
BSS138
SOT23_123
1
Q2
BSS138
SOT23_123
1
R12
220K
R0402
D1
PMEG6010CEGWX
sod123
3
STARTB
3
1
2
R4
10K
R0402
C14
2.2uF
C0603
2
R13
39K
R0402
2
GND_POWER
GND_POWER
3.2.2.5
GND_POWER
Supply Group Configuration
The main regulators provide all power supplies required by the SAMA5D2 device:
•
•
•
•
•
•
1.25V VDDCORE, VDDPLLA, VDDUTMIC, VDDHSIC
1.8V VDDIODDR, VDDSDHC1V8
2.5V VDDFUSE
3.3V VDDIOP0, VDDIOP1, VDDIOP2, VDDISC
3.3V VDDOSC, VDDUTMI, VDDANA, VDDAUDIOPLL
3.3V VDDBU
© 2017 Microchip Technology Inc.
DS50002709A-page 11
SAMA5D2-PTC-EK
Board Components
Figure 3-5. Power Lines Distribution
JP3
Header 1X2
VDD_3V3
1
2
VDDIOP2
L3 1
JP4
Header 1X2
2
VDD_1V8
VDDIODDR
BLM18PG181SN1D VDDIOP0
R0603
2
L5 1
For DDR2
For MPU
BLM18PG181SN1D
JP5
Header 1X2
VDD_1V25
VDDOSC
1
2
R16
2R2
R0603
L8
MLZ1608N100L
R17
0R
R0603
L12 1
VDDCORE
VDDPLLA
VDDUTMII
L0603
R15
2
VDDANA
BLM18PG181SN1D
R0603
2
L13 1
R19
2R2
R0603
1
2
BLM18PG181SN1D
R0603
R18
0R
R0603
2
L14 1
BLM18PG181SN1D VDDISC
R0603
2
L6 1
JP2
Header 1X2
VDDSDHC1V8
1
2
BLM18PG181SN1D VDDIOP1
R0603
2
L4 1
L7
MLZ1608N100L
L0603
2R2
R0603
VDDUTMIC
2
L10 1
BLM18PG181SN1D
VDDAUDIOPLL
R0603
BLM18PG181SN1D
R0603
L9
MLZ1608N100L
L0603
L11 1
VDDHSIC
2
BLM18PG181SN1D
R0603
Figure 3-6. Processor Power Lines Supplies
VDDCORE
(1V2)
C19
10uF
C0603
C27
10uF
C0603
VDDCORE
C31
100nF
C0402
C33
100nF
C0402
C35
100nF
C0402
C43
100nF
C0402
C47
100nF
C0402
C49
100nF
C0402
C58
1nF
C0402
C51
1nF
C0402
C60
1nF
C0402
U6G
(1V2)
VDDIODDR
(1V8) D11
D12
D15
E15
H15
J15
L15
VDDBU
(3V3)
N7
VDDANA
(3V3)
K3
GND_POWER
VDDBU
VDDANA
(3V3)
(3V3)
VDDBU
C21
100nF
C0402
VDDANA
C45
100nF
C0402
C37
100nF
C0402
GND_POWER
GND_POWER
VDDIOP0
VDDIOP1
(3 V3)
C22
100nF
C0402
C29
100nF
C0402
GND_POWER
VDDHSIC
( 1V2)
VDDIOP2
(3V3)
VDDIOP0
C46
100nF
C0402
GND_POWER
VDDHSIC
VDDFUSE
(2V5)
VDDFUSE
C39
100nF
C0402
C53
100nF
C0402
L5
GND_POWER
(3V3)
VDDAUDIOPLL
(3V3)
VDDIOP1
(3V3) N13
R14
VDDIOP2
(3V3) F10
VDDHSIC
(1V2)
VDDFUSE
(2V5) M12
VDDAUDIOPLL
C57
100nF
C0402
GND_POWER
VDDAUDIOPLL (3V3)
VDDUTMIC
(1V2)
C24
4.7uF
C0805
VDDUTMIC
C30
100nF
C0402
GND_POWER
C40
100nF
C0402
C26
100nF
C0402
GND_POWER
(3V3)
C56
100nF
C0402
VDDISC
T3
VDDUTMIC
(1V2)
P7
VDDUTMII
(3V3)
P8
VDDPLLA
(1V2)
U4
VDDOSC
(3V3)
T7
VDDISC
(3V3)
F4
VDDCORE_1
VDDCORE_2
VDDCORE_3
VDDCORE_4
VDDCORE_5
VDDCORE_6
VDDDDR_1
VDDDDR_2
VDDDDR_3
VDDDDR_4
VDDDDR_5
VDDDDR_6
VDDDDR_7
GNDCORE_1
GNDCORE_2
GNDCORE_3
GNDCORE_4
GNDCORE_5
GNDCORE_6
GNDDDR_1
GNDDDR_2
GNDDDR_3
GNDDDR_4
GNDDDR_5
GNDDDR_6
GNDDDR_7
VDDBU
GNDBU
VDDANA
GNDANA
VDDADC
GNDADC
VDDIOP0_1
VDDIOP0_2
GNDIOP0_1
GNDIOP0_2
VDDIOP1_1
VDDIOP1_2
GNDIOP1_1
GNDIOP1_2
VDDIOP2
GNDIOP2
E7
E9
H4
K12
M5
M9
D14
E11
E12
E14
H14
J14
L14
N6
L3
K5
F6
G7
M13
P14
F9
VDDHSIC
VDDFUSE
GNDDPLL
VDDAUDIOPLL
GNDAUDIOPLL
VDDUTMIC
GNDUTMIC
VDDUTMII
GNDUTMII
VDDSDMMC
GNDSDMMC
VDDPLLA
GNDPLLA
VDDOSC
GNDOSC
VDDISC
GNDISC
ATSAMA5D27C-CN
bga289p8
T5
T4
R7
P9
R11
GNDUTMII
U5
T6
G4
GND_POWER
VDDIODDR
VDDIODDR
(1V8)
C20
10uF
C0603
GND_POWER
R9
VDDSDHC (3V3 or 1V8)P11
VDDISC
VDDOSC
C42
100nF
C0402
C41
4.7uF
C0805
VDDSDHC
GND_POWER
(3V3)
R21
1R-1%
R0603
VDDSDHC
(3V3 or 1V8)
C55
100nF
C0402
VDDOSC
VDDPLLA
C25
4.7uF
C0805
3.2.2.6
VDDUTMII
GND_POWER
VDDPLLA
( 1V2 )
R20
1R-1%
R0603
VDDUTMII
(3V3)
E6
F7
VDDIOP0
C54
4.7uF
C0805
GND_POWER
GND_POWER
(3V3)VDDIOP2
VDDIOP1
C38
100nF
C0402
C23
100nF
C0402
D7
D9
H3
K13
N5
N9
VDDCORE
GND_POWER
C28
10uF
C0603
C32
100nF
C0402
C34
100nF
C0402
C36
100nF
C0402
C44
100nF
C0402
C48
100nF
C0402
C50
100nF
C0402
C52
1nF
C0402
C59
1nF
C0402
C61
1nF
C0402
GND_POWER
VDDFUSE
The SAMA5D2-PTC-EK board embeds a 2.5V regulator for fuse box programming.
© 2017 Microchip Technology Inc.
DS50002709A-page 12
SAMA5D2-PTC-EK
Board Components
Figure 3-7. VDDFUSE Regulator
VDDFUSE
VDD_3V3
2
VOUT
VIN
GND
5
C15
1uF
C0603
U5
EPAD
4
EN
1
3
EN_1
12
C16
1uF
C0603
MIC5366-2.5YMT
MLF1x1mm
GND_POWER
3.2.2.7
Backup Power Supply
The SAMA5D2-PTC-EK board requires a power source in order to permanently power the backup part of
the SAMA5D2 device (refer to SAMA5D2 Series datasheet). The super capacitor C17 sustains such
permanent power to VDDBU when all system power sources are off.
Figure 3-8. VDDBU Powering Options
JP6
Header 1X2
VDD_3V3
D2
R14
2
100R-1%
R0402
PMEG6010CEGWX
sod123
VDDBU
1
2
1
D3
BAT54C
3
SOT23_123
C18
100nF
C0402
+ C17
0.2F/3.3V
c117x68
GND_POWER
GND_POWER
(Super)-Capacitor
energy storage
3.2.3
Reset Circuitry
The reset sources for the SAMA5D2-PTC-EK board are:
•
•
•
Power-on reset from the power management unit,
Push button reset BP3,
JTAG or JLINK-OB reset from an in-circuit emulator.
Figure 3-9. Main Reset Control
VDD_3V3
R11
100K
R0402
NRST
PowerGood VDD_1V25
3
VDD_MAIN_5V
1
R12
220K
R0402
2
Q4
SOT-23
BC847C
D1
PMEG6010CEGWX
sod123
3
STARTB
Q3
BSS138
SOT23_123
1
2
C14
2.2uF
C0603
R13
39K
R0402
GND_POWER
3.2.4
Shutdown Circuitry
The SHDN signal, output of Shutdown Controller (SHDN), drives the shutdown request to the power
supply. This output signal is supplied by VDDBU, which is present in Backup mode.
The Shutdown Controller manages the main power supply and is connected to the ENABLE input pin of
the DC/DC converter providing the main power supplies of the system.
© 2017 Microchip Technology Inc.
DS50002709A-page 13
SAMA5D2-PTC-EK
Board Components
Figure 3-10. Shutdown Controller
VDD_3V3
R4
10K
R0402
VDD_MAIN_5V
EN_1
R3
100K
R0402
C8
100nF
C0402
STARTB
3
1
SHDN
3
Q1
BSS138
SOT23_123
2
2
GND_POWER
3.2.5
GND_POWER
Q2
BSS138
SOT23_123
1
GND_POWER
Push Button Switches
The SAMA5D2-PTC-EK features four push buttons:
•
One board reset push button (BP3). When pressed and released, it causes a power-on reset of the
board.
•
One wakeup push button (BP4) connected to the SAMA5D2 WKUP pin, used to exit the processor
from low-power mode.
One disable boot push button (BP2) used to devalidate the boot memories (refer to CS Disable).
Figure 3-11. System Push Buttons
•
BP2
DIS BOOT
R145
DISABLE_BOOT
Tact Switch
100R-1%
FSM2JSML
r0402
BP3
RESET
NRST
R146
WKUP
R147
Tact Switch
100R-1%
r0402
FSM2JSML
BP4
WAKE UP
Tact Switch
100R-1%
r0402
FSM2JSML
VDDBU
R238
GND_POWER
10K
R0402
•
One user push button (BP1) connected to PIO PB10.
Figure 3-12. User Push Button
BP1
PA10_USER_BT
USER BUTTON
R144
Tact Switch
0R
R0402
FSM2JSML
GND_POWER
3.2.6
Clock Circuitry
The embedded microcontroller generates its necessary clocks based on two crystal oscillators: one slow
clock (SLCK) oscillator running at 32.768 KHz and one main clock oscillator running at 24 MHz.
The SAMA5D2-PTC-EK board includes four clock sources:
•
The two clocks mentioned above are alternatives for the SAMA5D2 processor (24 MHz, 32.768
kHz)
•
One crystal oscillator for the Ethernet RMII chip (25 MHz)
One crystal oscillator for the JLink-OB microcontroller (12 MHz)
•
© 2017 Microchip Technology Inc.
DS50002709A-page 14
SAMA5D2-PTC-EK
Board Components
Figure 3-13. MPU Clock Circuitry
XIN
XOUT32
R123
1
2
C96
20pF
C0402
GND_POWER
3.2.7
Memory
3.2.7.1
Memory Organization
DNP
R0402
Y1
XOUT
R122
4
XIN32
32.768KHz CL=12.5pF
4
3
24MHz CL=10pF
x4s32x25
DNP
R0402
C98
20pF
C0402
GND_POWER
C97
20pF
C0402
3
GND_POWER
1
2
Y2
X4S70X15
C99
20pF
C0402
GND_POWER
The SAMA5D2 features a DDR/SDR memory interface and an External Bus Interface (EBI) to enable
interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
This section describes the memory devices mounted on the SAMA5D2-PTC-EK board:
•
•
•
•
•
Two DDR2 SDRAMs
One NAND Flash
One QSPI Flash
One SPI Flash (optional)
One serial EEPROM
Additional memory can be added to the board by:
•
•
Installing an SD or MMC card in the SD/MMC0 or SD/MMC1 slot,
Using the USB-B port.
Support is dependent upon driver support in the OS.
3.2.7.2
DDR2/SDRAMs
Two DDR2/SDRAMs (W972GG6KB-25-2 Gbits = 16 Mbits x 16 x 8 banks) are used as main system
memory, totalling 4 Gbits of SDRAM on the board. The memory bus is 32 bits wide and operates with a
frequency of up to 166 MHz.
The figure below illustrates the implementation for the DDR2 memories.
© 2017 Microchip Technology Inc.
DS50002709A-page 15
SAMA5D2-PTC-EK
Board Components
Figure 3-14. DDR2 SDRAMs
U7
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_CKE
DDR_CLK+
DDR_CLK-
K2
J8
K8
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
K7
L7
K3
L8
R7
R3
E2
A2
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
U8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS_P
NU/LDQS_N
UDQS_P
NU/UDQS_N
LDM
UDM
RAS
CAS
WE
CS
VSS1
VSS2
VSS3
VSS4
VSS5
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
F7
E8
B7
A8
DDR_DQS0+
DDR_DQS0DDR_DQS1+
DDR_DQS1-
F3
B3
DDR_DQM0
DDR_DQM1
VDD_1V8
K9
ODT
NC4
NC3
NC2
NC1
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
A1
E1
J9
M9
R1
VDD1
VDD2
VDD3
VDD4
VDD5
R29
DNP
R0402
R30
0R
R0402
VDD_1V8
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_CKE
DDR_CLK+
DDR_CLK-
K2
J8
K8
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
K7
L7
K3
L8
R7
R3
E2
A2
GND_POWER
A3
E3
J3
N1
P9
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
J1
J2
VDDL
VREF
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
DDR_VREF
J7
VSSDL
C72
100nF
C0402
W972GG6KB-25
bga84-32-1509e
C75
1nF
C0402
GND_POWER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
CKE
CK_P
CK_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS_P
NU/LDQS_N
UDQS_P
NU/UDQS_N
LDM
UDM
RAS
CAS
WE
CS
ODT
NC4
NC3
NC2
NC1
VSS1
VSS2
VSS3
VSS4
VSS5
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDL
VREF
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
F7
E8
B7
A8
DDR_DQS2+
DDR_DQS2DDR_DQS3+
DDR_DQS3-
F3
B3
DDR_DQM2
DDR_DQM3
VDD_1V8
K9
A1
E1
J9
M9
R1
VDD_1V8
R31
DNP
R0402
R32
0R
R0402
GND_POWER
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
J2
DDR_VREF
VSSDL
W972GG6KB-25
bga84-32-1509e
C94
100nF
C0402
C95
1nF
C0402
GND_POWER
GND_POWER
3.2.7.3
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
GND_POWER
DDR_CAL Analog Input
One specific analog input, DDR_CAL, is used to calibrate all DDR I/Os.
Table 3-3. Calibration Cell DDR_CAL Value
Memory
Resistor value
LPDDR2/LPDDR3
24K
DDR3L
23K
DDR3
22K
DDR2/LPDDR1
21K
© 2017 Microchip Technology Inc.
DS50002709A-page 16
SAMA5D2-PTC-EK
Board Components
Figure 3-15. DDR Signals and CAL Analog Input
U6E
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
F12
C17
B17
B16
C16
G14
F14
F11
C14
D13
C15
A16
A17
G11
DDR_BA0
DDR_BA1
DDR_BA2
H12
H13
F17
DDR_RAS
DDR_CAS
F13
G12
DDR_CLK+
DDR_CLKDDR_CKE
E17
D17
F16
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_BA0
DDR_BA1
DDR_BA2
DDR_RAS
DDR_CAS
DDR_CLK
DDR_CLKN
DDR_CKE
R25
100K
R0402
GND_POWER
DDR_CS
G13
DDR_WE
F15
E13
VDDIODDR
21K-1%
R24
R0402
R23
100K
R0402
GND_POWER
DDR_RESETN
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_CAL
22pF
C64
C0402
DDR_DQS0
DDR_DQSN0
DDR_DQS1
DDR_DQSN1
E16
DDR_VREF
H16
D16
C62
100nF
C0402
DDR_CS
DDR_WE
C63
100nF
C0402
DDR_DQS2
DDR_DQSN2
DDR_RESETN
DDR_VREFB0
DDR_VREFCM
DDR_DQS3
DDR_DQSN3
B12
A12
C12
A13
A14
C13
A15
B15
G17
G16
H17
K17
K16
J13
K14
K15
B8
B9
C9
A9
A10
D10
B11
A11
J12
H10
J11
K11
L13
L11
L12
M17
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
C11
G15
C8
H11
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
B13
B14
DDR_DQS0+
DDR_DQS0-
J17
J16
DDR_DQS1+
DDR_DQS1-
C10
B10
DDR_DQS2+
DDR_DQS2-
L17
L16
DDR_DQS3+
DDR_DQS3-
ATSAMA5D27C-CN
bga289p8
GND_POWER
NAND FLASH
The SAMA5D2-PTC-EK has native support for NAND Flash memory through its NAND Flash Controller.
The board implements one MT29F4G08ABA 4Gb x 16 NAND Flash connected to chip select three
(NCS3) of the microcontroller.
CAUTION
Caution: The NAND Flash interface is shared with the SDMMC1 and QSPI interfaces.
The figure below illustrates the NAND Flash memory implementation.
Figure 3-16. NAND Flash
3V3_NAND
R175
100K
R176
10K
R180
100K
16
17
8
18
9
NAND_CLE_PB1
NAND_ALE_PB0
NAND_REn_PB2
NAND_WEn_PA30
NAND_CS_PA31
R179
NAND_RDY_PC8
NAND_WPn
2
1
3.2.7.4
R177
DNP
JP8
Header 1X2
VDD_3V3
3V3_NAND
R174
C112
100nF
0R
C113
100nF
C114
100nF
C115
100nF
0R
7
19
1
2
3
4
5
6
10
11
14
15
22
23
24
26
27
28
33
40
U13
CLE
ALE
RE#
WE#
CE#
R/B#
WP#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NC19
NC20
NC21
DNU4
DNU3
DNU2
DNU1
VCC_1
VCC_2
VCC_3
VCC_4
VSS_1
VSS_2
VSS_3
VSS_4
29
30
31
32
41
42
43
44
NAND_IO0_PA22
NAND_IO1_PA23
NAND_IO2_PA24
NAND_IO3_PA25
NAND_IO4_PA26
NAND_IO5_PA27
NAND_IO6_PA28
NAND_IO7_PA29
45
46
47
38
35
20
21
3V3_NAND
12
34
37
39
13
25
36
48
MT29F4G08ABADAWP
© 2017 Microchip Technology Inc.
DS50002709A-page 17
SAMA5D2-PTC-EK
Board Components
Table 3-4. NAND Flash Signal Descriptions
3.2.7.5
PIO
Mnemonic
Shared PIO
Signal Description
PA22
NAND_D0
SDMMC1-QSPI
Data 0
PA23
NAND_D1
QSPI
Data 1
PA24
NAND_D2
QSPI
Data 2
PA25
NAND_D3
QSPI
Data 3
PA26
NAND_D4
QSPI
Data 4
PA27
NAND_D5
QSPI
Data 5
PA28
NAND_D6
SDMMC1
Data 6
PA29
NAND_D7
–
Data 7
PA30
NANDWE
SDMMC1
–
PA31
NCS3
–
Chip Select
PB00
NANDALE
–
–
PB01
NANDCLE
–
–
PB02
NANDOE
–
–
PC08
NANRDY
–
–
NAND Flash CS Disable
On-board jumper JP8 controls the selection (CS#) of the NAND Flash memory.
3.2.8
Additional Memories
3.2.8.1
Serial Flash
The SAMA5D2 includes two high-speed Serial Peripheral Interface (SPI) controllers. The SPI is a full
duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of
the following items:
•
a serial clock line (generated by the master)
•
a data output line from the master
a data input line to the master
one or more active low chip select signals (output from the master)
•
•
One SPI port is used to interface with the on-board serial Flash.
The following figure illustrates the implementation of an SPI Flash memory.
Figure 3-17. Serial Flash
VDD_3V3
5
2
6
SPI0_MOSI_PA15
SPI0_MISO_PA16
SPI0_SPCK_PA14
SPI0_CS0_PA17
1
U16
SI
SO
SCK
CS
VCC
WP
HOLD
GND
8
3
7
4
C119
100nF
C0402
SST26VF032B-104I/SM
soic8jg
GND_POWER
© 2017 Microchip Technology Inc.
DS50002709A-page 18
SAMA5D2-PTC-EK
Board Components
Note: The serial Flash is optional and not mounted on board.
QSPI Serial Flash
The SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI).
A QSPI is a synchronous serial data link that provides communication with external devices in Master
mode.
The QSPI can be used in SPI mode to interface with serial peripherals (such as ADCs, DACs, LCD
controllers, CAN controllers and sensors), or in Serial Memory mode to interface with serial Flash
memories.
The QSPI allows the system to execute code directly from a serial Flash memory (XIP, or Execute In
place, technology) without code shadowing to RAM. The serial Flash memory mapping is seen in the
system as other memories (ROM, SRAM, DRAM, etc.).
With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serial
Flash memories which are small and inexpensive, instead of larger and more expensive parallel Flash
memories.
The figure below illustrates the implementation of a QSPI Flash memory.
Figure 3-18. QSPI Serial Flash
VDD_3V3
R242
10K
JP13
Header 1X2
1
2
3.2.8.2
VDD_3V3
QSPI0_CS_PA23
VDD_3V3
R186
10K
R0402
R187
10K
R0402
5
2
3
7
QSPI0_IO0_PA24
QSPI0_IO1_PA25
QSPI0_IO2_PA26
QSPI0_IO3_PA27
U14
SI/SIO0
SO/SIO1
SIO2
SIO3
VCC
GND
CS#
SCLK
8
4
1
6
C120
100nF
C0402
QSPI0_SCK_PA22
GND_POWER
SST26VF064B-104I/SM
soic8jg
A jumper (JP13) is used to disable the QSPI Flash.
Table 3-5. SPI and QSPI Signal Descriptions
PIO
Mnemonic
PIO Shared
Signal Description
PA14
SPI0_SPCK
_
SPI clock
PA15
SPI0_MOSI
_
Master out - Slave in
PA16
SPI0_MISO
_
Master in - Slave out
PA17
SPI0_NPCS0
_
Chip select
_
_
_
PA22
QSPI0_SCK
SDMMC1-Nand Flash
QSPI clock
PA23
QSPI0_CS
Nand Flash
Chip select
PA24
QSPI0_IO0
Nand Flash
Data0
PA25
QSPI0_IO1
Nand Flash
Data1
_
© 2017 Microchip Technology Inc.
DS50002709A-page 19
SAMA5D2-PTC-EK
Board Components
3.2.8.3
PIO
Mnemonic
PIO Shared
Signal Description
PA26
QSPI0_IO2
Nand Flash
Data2
PA27
QSPI0_IO3
Nand Flash
Data3
CS Disable
On-board push button PB2 controls the selection (CS#) of the bootable memory components (QSPI and
serial Flash) using a non-inverting 3-state buffer.
Figure 3-19. CS Disable
VDD_3V3
C117
100nF
R178
10K
QSPI0_NPCS_PA23
VCC
2
3
BOOT_DIS
R184
10K
U11
1
GND_POWER
5
4
GND
QSPI0_CS_PA23
QSPI Flash CS
NL17SZ126DFT2G
DISABLE_BOOT
C116
100nF
1
SPI0_NPCS0_PA17
U12
VCC
2
3
5
4
GND
R185
10K
SPI0_CS0_PA17
SPI Flash CS
NL17SZ126DFT2G
GND_POWER
The rule of operation is:
•
PB2 (DISABLE_BOOT) and PB3 (RESET) pressed = booting from QSPI or optional serial Flash is
disabled.
Refer to the SAMA5D2 Series datasheet for more information on standard boot strategies and
sequencing.
3.2.8.4
Serial EEPROM with Unique MAC Address
The SAMA5D2-PTC-EK board embeds one Microchip 24AA02E48 I²C serial EEPROM connected on the
TWI1 interface.
The TWI interface is I2C-compatible and similarly uses only two lines, namely serial data (SDA) and serial
clock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in Fast mode and 100
kHz in Normal mode, but configurable baud rate generator permits the output data rate to be adapted to a
wide range of core clock frequencies. The TWI is used in Master mode.
The 24AA02E48 features 2048 bits of Serial Electrically-Erasable Programmable Read-Only Memory
(EEPROM) organized as 256 words of eight bits each and is accessed via an I2C-compatible (2-wire)
serial interface. In addition, the 24AA02E48 incorporates an easy and inexpensive method to obtain a
globally unique MAC or EUI address (EUI-48).
The EUI-48 addresses can be assigned as the actual physical address of a system hardware device or
node, or it can be assigned to a software instance. These addresses are factory-programmed by
Microchip and guaranteed unique. They are permanently write-protected in an extended memory block
located outside the standard 2-Kbit memory array.
CAUTION
Caution: The EEPROM device is used as a “software label” to store board information such as
chip type, manufacturer name and production date, using the last two 16-byte blocks in
memory. The information contained in these blocks should not be modified.
© 2017 Microchip Technology Inc.
DS50002709A-page 20
SAMA5D2-PTC-EK
Board Components
Table 3-6. EEPROM PIOs Signal Descriptions
PIO
Mnemonic
Shared
Signal Description
PC6
TWD1
XPRO
TWI Data
PC7
TWCL1
XPRO
TWI Clock
The figure below illustrates the implementation for the EEPROM.
Figure 3-20. EEPROM 24AA02E48
VDD_3V3
1
2
3
5
6
7
TWD1
TWCK1
TWD1_PC6
TWCK1_PC7
R188
10K
R0402
U15
A0
A1
A2
VCC
8
C118
100nF
C0402
SDA
SCL
WP
GND
4
24AA02E48
8MA2
GND_POWER
GND_POWER
3.2.9
Secure Digital Multimedia Card (SDMMC) Interface
The SD (Secure Digital) Card is a non-volatile memory card format used as a mass storage memory in
mobile devices.
3.2.9.1
Secure Digital Multimedia Card (SDMMC) Controller
The SAMA5D2-PTC-EK board has two Secure Digital Multimedia Card (SDMMC) interfaces that support
the MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the
SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 Specification.
•
•
3.2.9.2
The SDMMC0 interface is connected to a standard SD card interface.
The SDMMC1 interface is connected to a microSD card interface.
SDMMC0 Card Connector
A standard MMC/SD card connector, connected to SDMMC0, is mounted on the top side of the board.
The SDMMC0 communication is based on a 12-pin interface (clock, command, data (8) and power lines
(2)). A card detection switch is included.
The figure below illustrates the implementation for the SDMMC0 interface.
Figure 3-21. SDMMC0 Standard SD Socket
VDD_3V3
VDDSDHC
R171
0R
R0402
R154
0R
R0402
R155
68k
R0603
SDMMC0_WP_PA12
SDMMC0_CD_PA13
(MCI0_WP)
(MCI0_CD)
SDMMC0_DAT1_PA3
SDMMC0_DAT0_PA2
(MCI0_DA1)
(MCI0_DA0)
SDMMC0_CK_PA0
(MCI0_CK)
SDMMC0_CMD_PA1
SDMMC0_DAT3_PA5
SDMMC0_DAT2_PA4
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
SDMMC0_DAT4_PA6
SDMMC0_DAT5_PA7
SDMMC0_DAT6_PA8
SDMMC0_DAT7_PA9
(MCI0_DA4)
(MCI0_DA5)
(MCI0_DA6)
(MCI0_DA7)
© 2017 Microchip Technology Inc.
R157
68k
R0603
R158
68k
R0603
R159
68k
R0603
R161
68k
R0603
R163
68k
R0603
R165
68k
R0603
R167
68k
R0603
R169
10k
R0402
R172
10k
R0402
R173
10k
R0402
8
7
6
5
4
3
2
1
9
C110 10uF
C0603
C111 100nF
C0402
GND_POWER
16
15
14
J6
13
12
11
10
GND_POWER
7SDMM-B0-2211
con_kingconn_7sdmm_2211
DS50002709A-page 21
SAMA5D2-PTC-EK
Board Components
Figure 3-22. Standard SD Socket J6 Location
The table below describes the pin assignment of SD/MMC connector J6.
Table 3-7. Standard SD Socket J6 Pin Assignment
Pin No
Mnemonic
Signal Description
1
MCI0_DA3
SDMMC0_DAT3_PA5
2
MCI0_CDA
SDMMC0_CMD_PA1
3
GND
GND
4
VCC
VDDSDHC (3.3V or 1.8V)
5
MCI0_CK
SDMMC0_CK_PA0
6
MCI0_CD
SDMMC0_CD_PA13 (card detect)
7
MCI0_DA0
SDMMC0_DAT0_PA2
8
MCI0_DA1
SDMMC0_DAT1_PA3
9
MCI0_DA2
SDMMC0_DAT2_PA4
10
MCI0_DA4
SDMMC0_DAT4_PA6
11
MCI0_DA5
SDMMC0_DAT5_PA7
12
MCI0_DA6
SDMMC0_DAT6_PA8
13
MCI0_DA7
SDMMC0_DAT7_PA9
© 2017 Microchip Technology Inc.
DS50002709A-page 22
SAMA5D2-PTC-EK
Board Components
3.2.9.3
Pin No
Mnemonic
Signal Description
14
MCI0_WP
SDMMC0_WP_PA12
15
GND
GND
16
GND
GND
SDMMC0 VDDHC Voltage Switching
The board uses an ADG849 to switch the power line VDDSDHC_3V3 or VDDSDHC_1V8 through the
command line SDMMC0_VDDSEL_PA11.
Figure 3-23. SDMMC0 VDDSDHC Voltage Switching
VDD_3V3
VDDSDHC1V8
R151
VDDSDHC
DNP
R0402
DNP
R0402
R152
VDD_3V3
2
GND_POWER
IN
D
R150
10k
R0402
5
GND
1
SDMMC0_VDDSEL_PA11
S2
S1
3
4
VDD
U9
6
C107
100nF
C0402
ADG849YKSZ-REEL
SC70
GND_POWER
Table 3-8. SDMMC1 Power Command
Mnemonic
Signal Description
PA11
SDMMC0_VDDSEL
Selects 3.3V or 1.8V
SDMMC1 Card Connector
A microSD card connector, connected to SDMMC1, is mounted on the top side of the board. The
SDMMC1 communication is based on a 9-pin interface (clock, command, card detect, four data and
power lines). A card detection switch is included. The microSD connector can be used to connect any
microSD card for mass storage.
Figure 3-24. SDMMC1 microSD Socket
VDD_3V3
R160
10k
R0402
SDMMC1_CD_PA30
SDMMC1_DAT1_PA19
SDMMC1_DAT0_PA18
SDMMC1_CK_PA22
SDMMC1_CMD_PA28
SDMMC1_DAT3_PA21
SDMMC1_DAT2_PA20
R162
68k
R0603
R164
68k
R0603
R166
68k
R0603
R168
68k
R0603
R170
10k
R0402
(MCI1_CD)
J7
10
SW2
8
7
6
5
4
3
2
1
(MCI1_DA1)
(MCI1_DA0)
(MCI1_CK)
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
SW1
3.2.9.4
PIO
C108
10uF
C0603
C109
100nF
C0402
9
11
12
13
14
PJS008-2120-0 GND_POWER
Micro_SD_PJS008
GND_POWER
© 2017 Microchip Technology Inc.
DS50002709A-page 23
SAMA5D2-PTC-EK
Board Components
Figure 3-25. microSD Socket J7 Location
The table below describes the pin assignment of microSD connector J7.
Table 3-9. microSD Socket J7 Pin Assignment
Pin No
Mnemonic
PIO
Shared
Signal Description
1
SDMMC1_DAT2
PA20
–
Data bit 2
2
SDMMC1_DAT3
PA21
–
Data bit 3
3
SDMMC1_CDA
PA28
–
Command
4
VCC
–
–
3.3V supply voltage
5
SDMMC1_CK
PA22
–
Clock
6
GND
–
–
Common ground
7
SDMMC1_DAT0
PA18
–
Data bit 0
8
SDMMC1_DAT1
PA19
–
Data bit 1
9
SW1
GND
–
Not used
10
SDMMC1_CD
PA30
–
Card detection switch
11
GND
–
–
Common ground
© 2017 Microchip Technology Inc.
DS50002709A-page 24
SAMA5D2-PTC-EK
Board Components
Pin No
3.2.10
Mnemonic
PIO
Shared
Signal Description
12
GND
–
–
Common ground
13
GND
–
–
Common ground
14
GND
–
–
Common ground
Communication Interfaces
The SAMA5D2-PTC-EK board is equipped with Ethernet and USB host/device communication interfaces.
This section describes the signals and connectors related to the ETH and USB communication interfaces.
3.2.10.1 Ethernet 10/100 (GMAC) Port
The SAMA5D2-PTC-EK board features a Micrel PHY device (KSZ8081) operating at 10/100 Mb/s. The
board supports RMII interface modes. The Ethernet interface consists of two pairs of low-voltage
differential pair signals designated from GRX± and GTX± plus control signals for link activity indicators.
These signals can be used to connect to a 10/100 Base-T RJ45 connector integrated on the SAMA5D2PTC-EK board.
An individual 48-bit MAC address (Ethernet hardware address) is allocated to each product. This number
is stored in the Microchip 24AA02E48 I2C serial EEPROM (refer to Serial EEPROM with Unique MAC
Address).
Additionally, for monitoring and control purposes, a LED functionality is carried on the RJ45 connectors to
indicate activity, link, and speed status.
For more information about the Ethernet controller device, refer to the Micrel KSZ8081RN controller
manufacturer's datasheet.
Figure 3-26. Ethernet Interface
VDD_3V3
R197
1K
R0402
R194
VDD_3V3 GND_POWER
ETH_LED0
ETH_LED1
R192
10K
R0402
R193
10K
R0402
2.2uF
C0603
100nF
C0402
6.49K 1%
R0402
4
2
1
33
22
26
27
10
ETH_XO
8
ETH_XI
9
30
31
RXP
RXM
VDD_1V2
GND
PADDLE
TXC
TXD2
TXD3
REXT
TXD1
TXD0
TXEN
RXD3/PHYAD0
RXD2/PHYAD1
RXD1/PHYAD2
RXD0/DUPLEX
RXDV/CONFIG2
RXER/ISO
CRS/CONFIG1
COL/CONFIG0
MDC
MDIO
INTRP/NAND
19
ETH_GTXCK_PB14
25
24
23
13
14
15
16
18
20
29
28
ETH_GTX1_PB21
ETH_GTX0_PB20
ETH_GTXEN_PB15
ETH_GRX1_PB19
ETH_GRX0_PB18
ETH_GRXDV_PB16
ETH_GRXER_PB17
12
11
21
VDDA_3V3
VDDA_3V3
3
C127
10uF
C0603
L19
BLM18PG181SN1D
1
2
R0603
C129
100nF
C0402
GND_POWER
XO
XI
ETH_GMDC_PB22
ETH_GMDIO_PB23
ETH_INT_PB24
VDD_3V3
R0402 10K
R206
C124
top/bot
5
TXM
RXC/B-CAST_OFF
R0402 10K
R204
RXC123
top/bot
6
TXP
R203
10K
R0402
R0402 10K
R205
RX+
top/bot
7
R200
10K
R0402
R0402 10K
R201
TX-
top/bot
R199
10K
R0402
R0402 10K
R202
U17
TX+
R198
1K
R0402
VDDIO
17
GND_POWER
C128
10uF
C0603
LED0/NWAYEN
LED1/SPEED
C130
100nF
C0402
GND_POWER
RESET
32
R196
0R
R0402
NRST
KSZ8081RNB
qfn32_1p5h
© 2017 Microchip Technology Inc.
DS50002709A-page 25
SAMA5D2-PTC-EK
Board Components
Table 3-10. Ethernet PHY 10/100 Signal Descriptions
PIO
Mnemonic
Shared
Signal Description
PB14
ETH_GTXCK
_
Transmit clock
PB15
ETH_GTXEN
_
Transmit enable
PB16
ETH_GRXDV
_
Receive data valid
PB17
ETH_GRXER
_
Receive error
PB18
ETH_GRX0
_
Receive data 0
PB19
ETH_GRX1
_
Receive data 1
PB20
ETH_GTX0
_
Transmit data 0
PB21
ETH_GTX1
_
Transmit data 1
PB22
ETH_GMDC
_
Management data clock
PB23
ETH_GMDIO
_
Management data in/out
PB24
ETH_GTX_INT
_
Interrupt (open drain)
Figure 3-27. Ethernet PHY Connector J8
J8
13F-64GYD2PL2NL
1
TX+
TD+
1
CT
4
TX+
2
TX-
TD-
2
TX-
3
RX+
RD+
3
RX+
CT
5
RD-
6
6
RX-
75
75
4
75
NC
7
RXC121
100nF
C0402
C122
100nF
C0402
5
GND_ETH
8
Right yellow LED
9
Left Green LED
EARTH_ETH
rj45_13f-64gy_P12_4
ACT ETH_LED1
LINK ETH_LED0
VDD_3V3
© 2017 Microchip Technology Inc.
8
10
15
16
12
EARTH_ETH
75
7
11
13
14
1nF
R189
510R
R0402
R190
510R
R0402
DS50002709A-page 26
SAMA5D2-PTC-EK
Board Components
Figure 3-28. Ethernet RJ45 Connector J8 Location
The table below describes the pin assignment of Ethernet connector J8.
Table 3-11. Ethernet RJ45 Connector J8 Pin Assignment
Pin No
Mnemonic
Signal Description
1
TX+
Transmit
2
TX-
Transmit
3
RX+
Receive
4
Decoupling capacitor
–
5
Decoupling capacitor
–
6
RX-
Receive
7
NC
–
8
EARTH / GND
Common ground
9
ACT LED
LED activity
10
ACT LED
LED activity
11
LINK LED
LED link connection
12
LINK LED
LED link connection
13
EARTH / GND
Common ground
© 2017 Microchip Technology Inc.
DS50002709A-page 27
SAMA5D2-PTC-EK
Board Components
Pin No
Mnemonic
Signal Description
14
EARTH / GND
Common ground
15
NC
–
16
NC
–
3.2.10.2 USB Host/Device A, B
The USB (Universal Serial Bus) is a hot-pluggable general-purpose high-speed I/O standard for computer
peripherals. The standard defines connector types, cabling, and communication protocols for
interconnecting a wide variety of electronic devices. The USB 2.0 Specification defines data transfer rates
as high as 480 Mbps (also known as High Speed USB). A USB host bus connector uses 4 pins: a power
supply pin (5V), a differential pair (D+ and D- pins) and a ground pin.
The SAMA5D2-PTC-EK board features three USB communication ports named USB-A to USB-C:
•
•
•
USB-A device interface
– One USB device standard micro-AB connector.
– This port has a VBUS detection function made through the R148-R149 resistor bridge.
– The USB-A port is used as a primary power source and as a communication link for the
board, and derives power from the PC over the USB cable. In most cases, this port is limited
to 500 mA.
USB-B (host port B high- and full-speed interface)
– One USB host type A connector.
– The USB-B host port is equipped with a 500 mA high-side power switch to enable powering
devices connected to it.
UBC-C (High-Speed Inter-Chip/HSIC port)
– One USB high-speed host port with an HSIC interface.
– The port is connected to a single 2-pin jumper.
3.2.10.3 USB-A Interface
© 2017 Microchip Technology Inc.
DS50002709A-page 28
SAMA5D2-PTC-EK
Board Components
Figure 3-29. USB-A Type microAB Connector J4 Location
3.2.10.4 USB-A VBUS Detection
The USB-A port (J4) features a VBUS detection function provided by the R148-R149 resistor bridge.
The figure below shows the USB implementation on the USBA port.
Figure 3-30. USB-A Power and VBUS Detection
VBUS_USBA
7
11
SHD
9
10
C103
20pF
C0402
6
8
R148
VBUS
DM
DP
ID
GND
J4
1
2
3
4
5
100K
R0402
USBA_VBUS_5V_PB11
R149
200K
R0402
GND_POWER
USBA_DM
USBA_DP
GND_POWER
GND_POWER
USBMICRO5_6A
MicroUSB AB Connector
EARTH_USB_A
Table 3-12. USB-A PIO Signal Descriptions
PIO
PB11
Mnemonic
Shared
Signal Description
USBA_VBUS_5V
-
VBUS insertion detection
3.2.10.5 USB-B Interface
The figure below shows the USB implementation on the USB-B port.
© 2017 Microchip Technology Inc.
DS50002709A-page 29
SAMA5D2-PTC-EK
Board Components
Figure 3-31. USB-B Interface
5
SH1
VBUS
DM
DP
GND
A
USBB_DM
USBB_DP
GND_POWER
SH2
6
USBB_VBUS_5V
1
2
3
4
J3
Single USB Type A
USB4_2AL
EARTH_USB_B
Figure 3-32. USB-B Type A Connector J3 Location
Table 3-13. USB-B PIO Signal Descriptions
PIO
Mnemonic
Shared
Signal Description
PB12
USBB_EN_5V
–
Power switch enable (active high)
PB13
USBB_OVCUR
–
Indicates overcurrent (open drain)
USB-B Power Switch
The USB-B Host port is equipped with a 500 mA high-side power switch for self-powered and buspowered applications. If the client device is bus-powered, the carrier can supply a 5V, 500mA power to
the client device. The USBB_EN_5V_PB12 signal controls the power switch and current limiter, the Micrel
MIC2025, which in turn supplies power to a bus-powered client device. Per the USB specification, buspowered USB 2.0 devices are limited to a maximum of 500 mA. The MIC2025 limits the current and
indicates an overcurrent with the USBB_OVCUR_PB13 signal.
© 2017 Microchip Technology Inc.
DS50002709A-page 30
SAMA5D2-PTC-EK
Board Components
The table below describes the pin assignment of the USB-A and USB-B connectors.
Table 3-14. USB-A and USB-B Connector Signal Descriptions
Pin No
Mnemonic
Signal Description
1
VBUS
5V power
2
DM
Data minus
3
DP
Data plus
4
ID
On-the-go identification
5
GND
Common ground
3.2.10.6 HSIC
High-Speed Inter-Chip (HSIC) is a standard for USB chip-to-chip interconnect with a 2-signal (strobe,
data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed 480
Mbps data rate.
The interface operates at high speed, 480 Mbps, and is fully compatible with existing USB software
stacks. It meets all data transfer needs through a single unified USB software stack.
The HSIC interface is not used on the board and is connected to two-point jumper J5 (not mounted).
Figure 3-33. HSIC Interface
DNP
J5
1
2
HSIC_DATA
HSIC_STRB
3.3
External Interfaces
3.3.1
LCD TFT Interface
This section describes the signals and connectors related to the LCD interface.
3.3.1.1
LCD Interface
The SAMA5D2-PTC-EK board provides a connector with 18 bits of data and control signals to the LCD
interface. Other signals are used to control the LCD and are available on connector J16: TWI, SPI, two
GPIOs for interrupt, 1-wire and power supply lines.
This connector is used to connect LCD display series 43xx or 70xx from PDA.
3.3.1.2
LCD Expansion Header
J16 is a 1.27-mm pitch, 50-pin header. It gives access to the LCD signals.
© 2017 Microchip Technology Inc.
DS50002709A-page 31
SAMA5D2-PTC-EK
Board Components
Figure 3-34. LCD Expansion Header Interface
J16
SPI_CS_PB31
R234
100R-1%
R0402
R230
ID
GND1
D0
D1
D2
D3
GND2
D4
D5
D6
D7
GND3
D8
D9
D10
D11
GND4
D12
D13
D14
D15
GND5
D16
D17
D18
D19
GND6
D20
D21
D22
D23
GND7
PCLK/CMD
VSYNC/CS
HSYNC/WE
DE/RE
SPI_SCK
SPI_MOSI
SPI_MISO
SPI_CS
ENABLE
TWI_SDA
TWI_SCL
IRQ1
IRQ2
PWM
RESET
VCC1
VCC2
GND8
DNP
R0603
XF2M-5015-1A
FPC50-0p5mm
LCD_D2_PC10
LCD_D3_PC11
LCD_D4_PC12
LCD_D5_PC13
LCD_D6_PC14
LCD_D7_PC15
LCD_D10_PC16
LCD_D11_PC17
LCD_D12_PC18
LCD_D13_PC19
LCD_D14_PC20
LCD_D15_PC21
LCD_D18_PC22
LCD_D19_PC23
LCD_D20_PC24
LCD_D21_PC25
LCD_D22_PC26
LCD_D23_PC27
VDD_MAIN_5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD_3V3
LCD_PCLK_PD0
LCD_VSYNC_PC30
LCD_HSYNC_PC31
LCD_DE_PD1
SPI_SCK_PB30
SPI_MOSI_PB28
SPI_MISO_PB29
SPI_CS_PB31
LCD_EN_PC29
TWI_SDA_PB28
TWI_SCL_PB29
LCD_IRQ1_PC9
LCD_IRQ2_PD2
LCD_PWM_PC28
NRST
R231
0R
R0603
GND_POWER
3.3.1.3
LCD Power
In order to operate correctly with various LCD modules, two voltage lines are available: 3.3V and 5VCC
(default). The selection is made with 0R resistors R230 and R231.
© 2017 Microchip Technology Inc.
DS50002709A-page 32
SAMA5D2-PTC-EK
Board Components
3.3.1.4
LCD Connector JX
Figure 3-35. LCD Connector J16 Location
The table below describes the pin assignment of LCD FPC connector J16.
Table 3-15. LCD Connector J16 Signal Descriptions
Pin No
Signal
PIO
Signal
1
ID
PB31
_
2
GND
_
GND
3
LCDDAT0
–
D0
–
4
LCDDAT1
–
D1
–
5
LCDDAT2
PC10
D2
Data line
6
LCDDAT3
PC11
D3
Data line
7
GND
_
GND
8
LCDDAT4
PC12
D4
Data line
9
LCDDAT5
PC13
D5
Data line
10
LCDDAT6
PC14
D6
Data line
© 2017 Microchip Technology Inc.
RGB Interface Function
ID LCD module
GND
GND
DS50002709A-page 33
SAMA5D2-PTC-EK
Board Components
Pin No
Signal
PIO
Signal
11
LCDDAT7
PC15
D7
12
GND
_
GND
13
LCDDAT8
–
D8
–
14
LCDDAT9
–
D9
–
15
LCDDAT10
PC16
D10
Data line
16
LCDDAT11
PC17
D11
Data line
17
GND
GND
GND
GND
18
LCDDAT12
PC18
D12
Data line
19
LCDDAT13
PC19
D13
Data line
20
LCDDAT14
PC20
D14
Data line
21
LCDDAT15
PC21
D15
Data line
22
GND
_
GND
GND
23
LCDDAT16
–
D16
–
24
LCDDAT17
–
D17
–
25
LCDDAT18
PC22
D18
Data line
26
LCDDAT19
PC23
D19
Data line
27
GND
_
GND
GND
28
LCDDAT20
PC24
D20
Data line
29
LCDDAT21
PC25
D21
Data line
30
LCDDAT22
PC26
D22
Data line
31
LCDDAT23
PC27
D23
Data line
32
GND
_
GND
GND
33
LCDPCK
PD0
PCLK
Pixel clock
34
LCDVSYNC
PC30
VSYNC/CS
Vertical sync
35
LCDHSYNC
PC31
HSYNC/WE
Horizontal sync
36
LCDDEN
PD1
DATA_ENABLE
37
SPI_SPCK
PB30
SPI_SCK
–
38
SPI_MOSI
PB28
SPI_MOSI
(Shared with TWI)
39
SPI_MISO
PB29
SPI_MISO
(Shared with TWI)
40
SPI_NPCS0
PB31
SPI_CS
–
41
LCDDISP
PC29
ENABLE
Display enable signal
42
TWD
PB28
TWI_SDA
I2C data line (maXTouch)
© 2017 Microchip Technology Inc.
RGB Interface Function
Data line
GND
Data enable
DS50002709A-page 34
SAMA5D2-PTC-EK
Board Components
Pin No
3.3.2
Signal
PIO
Signal
RGB Interface Function
43
TWCK
PB29
TWI_SCL
I2C clock line (maXTouch)
44
GPIO
PC9
IRQ1
maXTouch interrupt line
45
GPIO
PD2
IRQ2
Interrupt line for other I2C devices
46
LCDPWM
PC28
PWM
Backlight control
47
RESET
–
RESET
48
Main_5V/3V3
VCC
VCC
3.3V or 5V supply (0R)
49
Main_5V/3V3
VCC
VCC
3.3V or 5V supply (0R)
50
GND
_
GND
GND
Reset for both display and maXTouch
RGB LED
The SAMA5D2-PTC-EK board features one RGB LED which can be controlled by the user. The three
LED cathodes are controlled via GPIO PWM or timer/counter pins.
Figure 3-36. RGB LED Indicators
3
LED_RED_PB10
R181
LED
Q5
BSS138
SOT23_123
1
100R-1%
R0402
D4
2
2.2K-1%
R0402
1
R240
1K
R0402
4
R241
1K
R0402
3
R239
GND_POWER
R182
LED_GREEN_PB8
3
Q7
BSS138
SOT23_123
1
100R-1%
R0402
2
R243
10K
VDD_3V3
Red
Green
Anode
2
Blue
CLV1A-FKB-CJ1M1F1BB7R4S3
GND_POWER
3
GND_POWER
R183
LED_BLUE_PB6
100R-1%
R0402
Q6
BSS138
SOT23_123
1
2
R244
10K
GND_POWER
GND_POWER
Table 3-16. RGB LED PIOS
3.4
Signal
PIO
Function
LED_RED
PB10
TIOB3
LED_GREEN
PB8
PWML3
LED_BLUE
PB6
PWML2
Debugging Capabilities
The SAMA5D2-PTC-EK includes two main debugging interfaces to provide debug-level access to the
SAMA5D2:
•
•
One UART through USB JLINK-CDC
Two JTAG interfaces, one connected directly to the MPU using connector J2 and one through the
JLINK-OB interface USB port J9
© 2017 Microchip Technology Inc.
DS50002709A-page 35
SAMA5D2-PTC-EK
Board Components
3.4.1
Debug JTAG
This section describes the signals and connectors related to the JTAG interface.
A 10-pin JTAG header is provided on the SAMA5D2-PTC-EK board to facilitate software development
and debugging using various JTAG emulators. The interface signals have a voltage level of 3.3V.
Figure 3-37. JTAG Interface
VDD_3V3
R140
100K
R0402
R141
100K
R0402
R142
100K
R0402
VDD_3V3
R138
RTCKIN
R236
10K
R0402
1
3
5
7
9
DNP
R0402
J2
2
4
6
8
10
R143
100R-1% R0402
CON_JTAG_Pin2
CON_JTAG_Pin4
CON_JTAG_Pin6
CON_JTAG_Pin8
NRST
Header 2X5
FTSH-105-01-F-DV-P-TR
GND_POWER
GND_POWER
Figure 3-38. JTAG Connector J2 Location
The table below describes the pin assignment of JTAG connector J2.
© 2017 Microchip Technology Inc.
DS50002709A-page 36
SAMA5D2-PTC-EK
Board Components
Table 3-17. JTAG/ICE Connector J2 Pin Assignment
Pin No Mnemonic
3.4.2
Signal Description
1
VTref. 3.3V power
This is the target reference voltage (main 3.3V).
2
TMS TEST MODE SELECT
JTAG mode set input into target CPU
3
GND
Common ground
4
TCK TEST CLOCK - Output timing signal,
for synchronizing test logic and control
register access
JTAG clock signal into target CPU
5
GND
Common ground
6
TDO JTAG TEST DATA OUTPUT - Serial
data input from the target
JTAG data output from target CPU
7
RTCK - Input return test clock signal from
the target
Some targets with a slow system clock must
synchronize the JTAG inputs to internal clocks. In
the present case, such synchronization is
unneeded and TCK is merely looped back into
RTCK.
8
TDI TEST DATA INPUT - Serial data output
line, sampled on the rising edge of the TCK JTAG data input into target CPU
signal
9
GND
Common ground
10
nRST RESET
Active-low reset signal. Target CPU reset signal.
Embedded Debugger (JLINK-OB) Interface
The SAMA5D2-PTC-EK includes a built-in SEGGER J-Link-On-Board device. The functionality is
implemented with an ATSAM3U4C microcontroller in an LFBGA100 package. The ATSAM3U4C provides
the functions of JTAG and a bridge USB/Serial debug port (CDC). One two-colored LED (D6) mounted
near the SAM3 chip (U20) shows the status of the J-Link-On-Board device.
J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, low-cost, on-board alternative to
the standard J-Link.
The USB JLINK-OB port is used as a secondary power source and as a communication link for the
board, and derives power from the PC over the USB cable. This port is limited in most cases to 500 mA.
A single PC USB port is sufficient to power the board.
© 2017 Microchip Technology Inc.
DS50002709A-page 37
SAMA5D2-PTC-EK
Board Components
Figure 3-39. JLINK-OB Interface
U20
R208
R209
10K
R0402
D5
PMEG6010CEGWX
sod123
C132 10nF
C0402
R210
100R-1%
R0402
VDD_3V3_3U
VDD_3V3_3U
4
2
ERASE_3U
D6
VDD_3V3_3U
J3
K4
Y4
VCC
Out
GND
NC
3
1
C8
C136 10nF
C0402
D7
C9
R213
DNP
R0402
R214
6.8K-1%
R0402
C137 10pF
C0402
A1
A10
B10
EDBG_XIN
R245
0R
VDD_3V3_3U
ASE-12.000MHz-LC-T
B7
100R-1%
R0402
GND_POWER
GND_POWER
C156
100nF
C0402
B9
B8
A7
C7
NRST_3U
VDD_3V3_3U
GND_POWER
TDI_3U
TDO_3U
TCK_3U
TMS_3U
R215
A2
A3
D8
100K
R0402
TDI
TDO/TRACESWO
TCK/SWCLK
TMS/SWDIO
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
G3
F1
G2
J5
K5
H2
J1
K1
J2
E4
B4
G1
F2
G4
C4
G7
F7
A4
B5
C5
D5
A5
C6
A6
B6
ENSPI
ERASE
ADVREF
AD12BVREF
NRST
NRSTB
TST
JTAGSEL
VBG
XIN32
XOUT32
XIN
XOUT
FWUP
PA0/PGMNCMD
PA1/PGMRDY
PA2/PGMNOE
PA3/PGMNVALID
PA4/PGMM0
PA5/PGMM1
PA6/PGMM2
PA7/PGMM3
PA8/PGMD0
PA9/PGMD1
PA10/PGMD2
PA11/PGMD3
PA12/PGMD4
PA13/PGMD5
PA14/PGMD6
PA15/PGMD7
PA16/PGMD8
PA17/PGMD9
PA18/PGMD10
PA19/PGMD11
PA20/PGMD12
PA21/PGMD13
PA22/PGMD14
PA23/PGMD15
PA24
PA25
PA26
PA27
ID
GND
VDDIO_1
VDDIO_2
VDDIO_3
GNDBU
GNDANA
GNDUTMI
GNDPLL
GND_1
GND_2
GND_3
PA29
E5
K3
B2
C3
E2
F6
G6
F3
F5
E6
VDDCORE_1
VDDCORE_2
VDDCORE_3
VDDCORE_4
VDDCORE_5
VDDCORE_6
VDDPLL
B1
D4
E7
H1
G5
F9
D3
A9
VDDIN
A8
EDBG_USB_DM
EDBG_USB_DP
VDDBU
VDDANA
VDDUTMI
1
2
3
4
5
DHSDM
DFSDM
DFSDP
DHSDP
C10
K2
B3
VBUS
DM
DP
PA30
PA31
TRSTIN
TRSTOUT
E3
LED1_3U
E1
LED2_3U
TRESIN
TRESOUT
RX_3U
TX_3U
TDIIN
TMSIN
TCKOUT
TMSOUT
TDIOUT
TDOIN
TCKIN
ENSPI
TCKOUT
PA25_3U
PA26_3U
J4
F4
RTCKIN
ATSAM3U4CA-CU
TFBGA100
VDD_3V3_3U
VDD_OUT_3U
VDD_3V3_3U
7
11
SHD
9
10
39R R0402
39R R0402
6
8
VBUS_JLINK
R211
R212
VDDOUT
PA28
D2
D1
C1
C2
GND_POWER
J10
H9
H10
G8
G10
G9
F8
F10
E10
E9
E8
D9
D10
H5
K6
H6
J6
K7
H7
J7
K8
J8
H4
K9
H8
K10
J9
H3
J9
MicroUSB AB Connector
USBMICRO5_6A
EARTH_USB_EDBG
GND_POWER
VDD_3V3_3U
D6
JP11
Header 1X2
1
2
VDD_3V3_3U
ERASE_3U
LED1_3U
R216
150R-1% 2
R0402
RED
1
LED2_3U
R217
150R-1% 4
R0402
Green
3
1
3
KPTB-1615
Disabling JLINK-OB (ATSAM3U4C)
Jumper JP10 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, it
grounds pin 26 of the ATSAM3U4C that is normally pulled high. A quad analog switch is used to select
the JTAG interface.
•
•
Jumper JP10 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.
Jumper JP10 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG controller can be
used through the 10-pin JTAG port J2.
Jumper JP10 disables only the J-Link functionality. The debug serial com port that is emulated through a
Communication Device Class (CDC) of the same USB connector remains operational (if JP9 is open).
Figure 3-40. Enabling/Disabling JLINK-OB and JLINK-CDC
VDD_3V3_3U
1
2
JP9
Header 1X2
R224
10K
R0402
PA25_3U
JTAG-CDC disable
GND_POWER
VDD_3V3_3U
JP10
Header 1X2
1
2
3.4.2.1
R225
10K
R0402
PA26_3U
JTAG-OB disable
GND_POWER
© 2017 Microchip Technology Inc.
DS50002709A-page 38
SAMA5D2-PTC-EK
Board Components
Figure 3-41. JTAG Switch
14
VDD_3V3_3U
16
1
CON_JTAG_Pin8
PA26_3U
2
TDOIN
3
4
JTAG_TDO_PD29
5
CON_JTAG_Pin6
NCD
NOA
COMA
COMD
NCA
NOD
CDIN
ABIN
NOB
NCC
COMC
COMB
NCB
GND
JTAG_TDI_PD28
15
NLAS3899BMNTWG
WQFN-16
6
150R-1%
R0402
VCC
U22
TDIOUT R218
TDIIN
NOC
13
12
CON_JTAG_Pin4
JTAG_TCK_PD27
11
R222
10
PA26_3U
9
8
150R-1% TCKOUT
R0402
TCKIN
CON_JTAG_Pin2
JTAG_TMS_PD30
7
R223
150R-1% TMSOUT
R0402
TMSIN
GND_POWER
3.4.3
Hardware UART via CDC
In addition to the J-Link-OB functionality, the ATSAM3U4C microcontroller provides a bridge to a debug
serial port (UART DBGU) of the SOM's processor. The port is made accessible over the same USB
connection used by JTAG by implementing Communication Device Class (CDC), which allows terminal
communication with the target device.
This feature is enabled only if the SAM3U/PA25 (pin K10) is not grounded. The pin is normally pulled high
and controlled by jumper JP9.
•
•
Jumper JP9 not installed: the J-Link-CDC is enabled and fully functional.
Jumper JP9 installed: the J-Link-CDC device is disabled.
The USB Communications Device Class (CDC) enables to convert the USB device into a serial
communication device. The target device running USB-Device CDC is recognized by the host as a serial
interface (USB2COM, virtual COM port) without the need to install a special host driver (since the CDC is
standard). All PC software using a COM port work without modifications with this virtual COM port. Under
Windows, the device shows up as a COM port; under Linux, as a /dev/ACMx device. This enables the
user to use host software which was not designed to be used with USB, such as a terminal program.
Table 3-18. Debug COM Port PIOs Signal Descriptions
PIO
Mnemonic
Shared
Signal Description
PB26
URXD0
-
Receive data
PB27
UTXD0
-
Transmit data
© 2017 Microchip Technology Inc.
DS50002709A-page 39
SAMA5D2-PTC-EK
Board Components
Figure 3-42. JLINK-OB and CDC USB Connector J9 Location
The table below describes the pin assignment of USB connector J9.
Table 3-19. USB Connector J9 Pin Assignment
Pin No
3.4.3.1
Mnemonic
Signal Description
1
VBUS
5V power
2
DM
Data minus
3
DP
Data plus
4
ID
Not used
5
GND
Common ground
Board Edge Connector
This connector is used to upgrade or download code to the ATSAM3U4C microcontroller JLINK-OB.
3.5
PIO Usage on Expansion Connectors
3.5.1
PIOBU Interface
The SAMA5D2-PTC-EK board features eight tamper pins for static or dynamic intrusion detection, UART
reception, and two analog pins for comparison.
© 2017 Microchip Technology Inc.
DS50002709A-page 40
SAMA5D2-PTC-EK
Board Components
For a description of intrusion detection, refer to the SAMA5D2 datasheet, chapter "Security Module".
Figure 3-43. PIOBU Connector
J1
DNP
PIOBU0
PIOBU2
PIOBU4
PIOBU6
ACP
R124
R125
R126
R127
R128
330R
330R
330R
330R
0R
R0402
R0402
R0402
R0402
R0402
1
3
5
7
9
2
4
6
8
10
R129
R130
R131
R132
330R
330R
0R
0R
R0402
R0402
R0402
R0402
PIOBU3
PIOBU5
RXD
ACN
FTSH-105-01-F-DV-P-TR
GND_POWER
Figure 3-44. PIOBU Connector J1 Location
The table below describes the pin assignment of PIOBU connector J1.
Table 3-20. PIOBU Connector J1 Pin Assignment
Signal
3.5.2
Pin No.
Signal
PIOBU0
1
2
PIOBU3
PIOBU2
3
4
PIOBU5
PIOBU4
5
6
RXD
PIOBU6
7
8
ACN
ACP
9
10
GND
mikroBUS Interface
The SAMA5D2-PTC-EK hosts a pair of 8-pin female headers as mikroBus interface. The mikroBUS
interface defines the main board sockets and add-on boards used for interfacing microprocessors with
© 2017 Microchip Technology Inc.
DS50002709A-page 41
SAMA5D2-PTC-EK
Board Components
integrated modules with proprietary pin configuration and silkscreen markings. The pinout consists of
three groups of communication pins (SPI, UART and TWI), four additional pins (PWM, interrupt, analog
input and reset) and two power groups (+3.3V and GND on the left, and 5V and GND on the right 1x8
header).
Figure 3-45. mikroBUS Interface
1
2
3
4
5
6
7
8
PD25
RST
NPCS0
SPCK
MISO
MOSI
3V3
2
1
AN-AD6
MBUS_RST_PC05
NPCS0_PC04
SPCK_PC01
MISO_PC03
MOSI_PC02
VDD_3V3
J15B
J15A
SSQ-108-01-G-S
1
2
3
4
5
6
7
8
PWM
INT
RX
TX
SCL
SDA
+5v R229
PWM_PD20
INT_PD19
RX_PD23
TX_PD24
TWCK0_PD22
TWD0_PD21
DNP VDD_MAIN_5V
R0402
SSQ-108-01-G-S
JP12
Header 1X2
GND_POWER
Figure 3-46. mikroBUS Connector J15 Location
The table below describes the pin assignment of mikroBUS1 connector J15.
Table 3-21. mikroBUS Connector J15 Pin Assignment
SAMA5D27
SAMA5D27
Function
PIO
MBUS Signal
Analog input
PD25
AN
1
Reset
PC05
RST
SPI chip select
PC04
SPI_NPCS
© 2017 Microchip Technology Inc.
Pin No.
MBUS Signal
PIO
Function
1
PWM
PD20
PWM
2
2
INT
PD19
Interrupt
3
3
UART_RX
PD23
UART receive
DS50002709A-page 42
SAMA5D2-PTC-EK
Board Components
SAMA5D27
3.5.3
SAMA5D27
Function
PIO
MBUS Signal
Pin No.
MBUS Signal
PIO
Function
SPI clock
PC01
SPI_SPCK
4
4
UART_TX
PD24
UART transmit
SPI MISO
PC03
SPI_MISO
5
5
TWI_SCL
PD22
TWI clock
SPI MOSI
PC02
SPI_MOSI
6
6
TWI_SDA
PD21
TWI data
3.3VCC
–
3V3 Supply
7
7
5V Supply
_
5VDD
GROUND
–
GND
8
8
GND
_
GROUND
XPRO Interface
The SAMA5D2-PTC-EK board hosts two connectors to interface XPRO QT boards. The QTouch Xplained
Pro are extension boards that enable evaluation of Self-capacitance and Mutual capacitance modes
using the Peripheral Touch Controller (PTC). The boards show how easy it is to design a capacitive touch
board solution using the PTC without the need for any external components.
Nevertheless, the PTC IO pins available on XPRO connectors can be used as GPIO pins. Each of these
can be configured as an input or output pin according to the PIO peripheral functions.
The GPIO voltage levels depend on the VDDIOP level supported by the SAMA5D2, 3.3V in this case.
Figure 3-47. XPRO EXT1 Connector
PD11
PD13
PB9
PD15
PC 6
PTC_YLINE0
PTC_YLINE2
XPRO1_GPIO_PB9
PTC_YLINE4
XPRO_PC6
PTC_YLINE6
XPRO1_GPIO_PD26
R226
0R
PD17
PD26
1
3
5
7
9
11
13
15
17
19
J11
2
4
6
8
10
12
14
16
18
20
Header 2X10
GND_POWER
© 2017 Microchip Technology Inc.
PD12
PD14
PC0
PD16
PC 7
PTC_YLINE1
PTC_YLINE3
XPRO1_GPIO_PC0
PTC_YLINE5
XPRO_PC7
PD18
PD17
R227
DNP
R235
0R
PTC_YLINE7
PTC_YLINE6
VDD_3V3
XPRO2_GPIO_PD31
DS50002709A-page 43
SAMA5D2-PTC-EK
Board Components
Figure 3-48. XPRO EXT1 Connector J11 Location
The table below describes the pin assignment of XPRO EXT1 connector J11.
Table 3-22. XPRO EXT1 Connector J11 Pin Assignment
SAMA5D27
SAMA5D27
Function
Pin
XPRO Signal
Pin
Function
_
Not used
ID
1
2
GND
–
GROUND
PTC_YLINE0
PD11
ADC(+)
3
4
ADC(-)
PD12
PTC_YLINE1
PTC_YLINE2
PD13
GPIO
5
6
GPIO
PD14
PTC_YLINE3
GPIO
PA10
PWM(+)
7
8
PWM(-)
PC0
GPIO
PTC_YLINE4
PD15
IRQ/GPIO
9
10
SPI_SS_B/GPIO
PD16
PTC_YLINE5
XPRO_TWD
PC6
TWI_SDA
11
12
TWI_SCL
PC7
XPRO_TWCK
_
_
UART_RX
13
14
UART_TX
_
–
PTC_YLINE6
PD17
SPI_SS_A
15
16
SPI_MOSI
PD18
PTC_YLINE7
GPIO
PD26
SPI_MISO
17
18
SPI_SCK
PD31 or PD17
PTC_YLINE6
GROUND
–
GND
19
20
VCC 3V3
–
3.3V Supply
© 2017 Microchip Technology Inc.
XPRO Signal Pin No.
DS50002709A-page 44
SAMA5D2-PTC-EK
Board Components
Figure 3-49. XPRO EXT2 Connector
XPRO1
1
3
5
7
9
11
13
15
17
19
PD3
PD5
PD7
PD9
PTC_XLINE0
PTC_XLINE2
PTC_XLINE4
PTC_XLINE6
PB25
XPRO2_GPIO_PB25
J12
2
4
6
8
10
12
14
16
18
20
PD4
PD6
PD8
PD10
PD31
R235
R228
0R
0R
PTC_XLINE1
PTC_XLINE3
PTC_XLINE5
PTC_XLINE7
XPRO2_GPIO_PD31
VDD_3V3
Header 2X10
GND_POWER
Figure 3-50. XPRO EXT2 Connector J12 Location
The table below describes the pin assignment of XPRO EXT2 connector J12.
Table 3-23. XPRO EXT2 Connector J12 Pin Assignment
SAMA5D27
SAMA5D27
Function
Pio
XPRO
Signal
_
Not used
ID
1
2
GND
–
GROUND
PTC_XLIN
E0
PD3
ADC(+)
3
4
ADC(-)
PD4
PTC_XLIN
E1
PTC_XLIN
E2
PD5
GPIO
5
6
GPIO
PD6
PTC_XLIN
E3
© 2017 Microchip Technology Inc.
Pin No.
XPRO
Signal
Pio
Function
DS50002709A-page 45
SAMA5D2-PTC-EK
Board Components
SAMA5D27
3.5.4
SAMA5D27
Function
Pio
XPRO
Signal
PTC_XLIN
E4
PD7
PWM(+)
7
8
PWM(-)
PD8
PTC_XLIN
E5
PTC_XLIN
E6
PD9
IRQ/GPIO
9
10
SPI_SS_B/
GPIO
PD10
PTC_XLIN
E7
–
–
TWI_SDA
11
12
TWI_SCL
PD31
GPIO
–
–
UART_RX
13
14
UART_TX
–
–
GPIO
PB25
SPI_SS_A
15
16
SPI_MOSI
–
–
–
–
SPI_MISO
17
18
SPI_SCK
–
–
GROUND
–
GND
19
20
VCC 3V3
–
3.3V
Supply
Pin No.
XPRO
Signal
Pio
Function
Miscellaneous PIOB[0-7]
PIOs PB00 to PB07 are available on connector J13 and can be used as GPIO pins. Each of these can be
configured as an input or output pin according to the PIO peripheral functions.
Figure 3-51. PIOs PB[0-7] Connector
VDD_3V3
1
2
3
4
5
6
7
8
9
10
PB_PORT_0
PB_PORT_1
PB_PORT_2
PB_PORT_3
PB_PORT_4
PB_PORT_5
PB_PORT_6
PB_PORT_7
J13
PIOB[0-7] connector
GND_POWER
© 2017 Microchip Technology Inc.
DS50002709A-page 46
SAMA5D2-PTC-EK
Board Components
Figure 3-52. PIOB[0-7] Connector J13 Location
The table below describes the pin assignment of PIOs PB[0-7] connector J13.
Table 3-24. PIOs PB[0-7] Connector J13 Pin Assignment
Pin No
PIO
Mnemonic
Shared
Signal Description
1
_
VDD_3V3
_
Main 3.3V
2
PB0
GPIO
NAND Flash
PIO port B
3
PB1
GPIO
NAND Flash
PIO port B
4
PB2
GPIO
NAND Flash
PIO port B
5
PB3
GPIO
_
PIO port B
6
PB4
GPIO
_
PIO port B
7
PB5
GPIO
_
PIO port B
8
PB6
GPIO
LED_BLUE
PIO port B
9
PB7
GPIO
_
PIO port B
10
_
GND
_
Common ground
© 2017 Microchip Technology Inc.
DS50002709A-page 47
SAMA5D2-PTC-EK
Installation and Operation
4.
Installation and Operation
4.1
System and Configuration Requirements
The SAMA5D2-PTC-EK requires the following:
•
•
4.2
Personal Computer
USB cable
Board Setup
Follow these steps before using the SAMA5D2-PTC-EK:
1.
2.
3.
4.
5.
6.
Unpack the board, taking care to avoid electrostatic discharge.
Check the default jumper settings.
Connect the USB Micro-AB cable to connector J9.
Connect the other end of the cable to a free port of your PC.
Open a terminal (console 115200, N, 8, 1) on your Personal Computer.
Reset the board. A startup message appears on the console.
© 2017 Microchip Technology Inc.
DS50002709A-page 48
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
5.
Appendix A. Schematics and Layouts
This appendix contains the following schematics and layouts for the SAMA5D2-PTC-EK board:
•
Title and Revision History
•
Block Diagram
•
Power Domains
•
MPU Power
•
DDR2-SDRAM
•
PIOA & PIOB
•
PIOC & PIOD
•
System
•
USB & TF
•
Memories & RGB LED
•
Ethernet 10/100M
•
JLINK-OB
•
EXT Connectors
Figure 5-1. Title and Revision History
4
5
Schematic: A5D2-PTC-EK
SHEET
D
C
2
3
1
Revision History
SHEET NAME
DATE
REVISI ON
DESCRIPT ION
01
Title & Revision History
06 Jan 2017
RevA-20160107
02
Block Diagram
07-MAR-17
RevA
RevA release
03
Power domains
03-OCT-17
RevB
RevB release
04
MPU_POWER
05
DDR2-SDRAM
06
PIOA&PIOB
07
PIOC&PIOD
08
SYSTEM
09
USB&TF
10
MEMORIES&RGBLED
11
Ethernet_10/100M
12
JLINK-OB
13
EXT_CONNECTORS
Init edit
D
C
B
B
A
A
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
01) Title & Revision History
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
1
13
1
DS50002709A-page 49
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-2. Block Diagram
5
Push
Buttons
4
2
3
5V INPUT
Reset
Force PwrOn
Sheet 9
POWER
D
Sheet 8
5V & 3V3
Sheet 3
USB A,B,C
Power rails
User LEDs
QSPI Flash
NAND Flash
XPRO Connectors
B
Sheet 13
4:
5:
6:
7:
8:
MPU_POWER
DDR2-SDRAM
PIOA & PIOB
PIOC & PIOD
SYSTEM
USB
DEVICE
Sheet 12
JLINK-OB
JTAG
PIO
Sheet
Sheet
Sheet
Sheet
Sheet
USB B
Host
USB C
HSIC
Atmel
SAMA5D27
Cortex(R)-A5 Processor
Sheet 10
D
USB A
OTG
USB TO UART
5V INPUT
C
1
Sheet 5
JTAG
Connector
2Gb
DDR2
SDRAM
EBI
C
Sheet 8
ANALOG Reference
B
PIO A,B,C,D
QSPI Flash
SPI
Data
Flash
Sheet 10
She et 1 0
Ethernet
10/100M bps
24AA02E48
S heet 11
S heet 10
A
LCD CON
Sheet 13
SDCARD
CON
PTC PORT
Sheet 13
Sheet 09
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
02) Block Diagram
5
DATE
A
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
2
13
1
DS50002709A-page 50
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-3. Power Domains
4
Switching Power lines
R1
10K
R0402
7
6
1
VDDBU Power Supply
JP6
Header 1X2
VDD_3V3
1
D2
C12
100nF
C0402
2
2
C1
100nF
C0402
D
7
6
VDD_MAIN_5V
1
2
1
1
POWER SUPPLY
JP1
Header 1X2
U4A
DMP2160UFD
U1A
DMP2160UFD
VBUS_JLINK
2
3
JPR1
Jumper
R5
R14
2
100R-1%
R0402
PMEG6010CEGWX
sod123
D3
BAT54C
VDDBU
3
SOT23_123
+ C17
0.2F/3.3V
c117x68
100K
R0402
GND_POWER
GND_POWER
U1B
DMP2160UFD
8
3
R8
GND
FPWM#
LQH43CN2R2M03L8
L1812
12
EPAD
L2
1
OUT2
AGND
C10
390pF
C0402
VDD_1V25
13
3
4
EN
GND
PGOOD
IN1
ADJ
IN2
OUT
EPAD
2
VDD_1V8
BIAS
C6
10uF
C0603
LQH43CN2R2M03L
L1812
C11
10uF
C0603
9
8
C13
4.7nF
C0402
FPWM#
JP3
Header 1X2
VDD_3V3
R249
BLM18PG181SN1D VDDIOP0
R0603
2
L5 1
5
R251
10K
R0402
MIC47053YMT
VDD_1V25
R250
3.3K
R0402
BLM18PG181SN1D
R0603
GND_POWER
R11
100K
R0402
GND_POWER
C9
1uF
C0603
VDDOSC
NRST
JP2
Header 1X2
8,11,12,13
3
Q4
SOT-23
BC847C
EN_1
R3
100K
R0402
C8
100nF
C0402
SHDN
3
Q1
BSS138
SOT23_123
1
1
2
R12
220K
R0402
L8
MLZ1608N100L
R17
0R
R0603
L12 1
R18
0R
R0603
GND_POWER
Q2
BSS138
SOT23_123
D1
PMEG6010CEGWX
sod123
3
STARTB
3
1
2
R4
10K
R0402
VDD_MAIN_5V
A
R16
2R2
R0603
GND_POWER
1
2
GND_POWER
STARTB
Q3
BSS138
SOT23_123
1
R19
2R2
R0603
C14
2.2uF
C0603
© 2017 Microchip Technology Inc.
2
BLM18PG181SN1D
R0603
2
L13 1
VDDANA
BLM18PG181SN1D
VDDAUDIOPLL
R0603
L9
MLZ1608N100L
L0603
A
R13
39K
R0402
2
B
A
A
2
REV
SAMA5D2-PTC-EK
5
VDDUTMII
L0603
GND_POWER
GND_POWER
B
BLM18PG181SN1D VDDISC
R0603
2
L6 1
VDD_3V3
4.7K
R0402
2
BLM18PG181SN1D VDDIOP1
R0603
2
L4 1
EN_VDD_1V25
VDD_3V3
8
VDDIOP2
L3 1
7
6
VDDHSIC
2
BLM18PG181SN1D
R0603
R10
DNP
R0402
R248
20K
R0402
GND_POWER
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03/10/17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
3
2
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
VER.
DATE
REV.
SHEET
B
03) Power domains
4
C
VDDUTMIC
2
L11 1
VDD_MAIN_5V
GND_POWER
L10 1
R9
100K
R0402
GND_POWER
1
L7
MLZ1608N100L
L0603
2R2
R0603
VDD_3V3
U3
VDDCORE
BLM18PG181SN1D
R0603
VDD_3V3
MIC2230-GSYML
MLF3x3mm
Fixed output 1V2
C7
100nF
C0402
2
VDDPLLA
6
PGND
GND_POWER
VDD_MAIN_5V
C16
1uF
C0603
VDD_MAIN_5V
EN_VDD_1V25
4
SW2
OUT1
5
12
2
10
PGOOD
SW1
C4
10uF
C0603
EN_1
R15
9
VIN
EN2
EN1
7
3
GND_POWER
AVIN
11
EN
MIC5366-2.5YMT
MLF1x1mm
1
2
3
EN_1
FPWM#
VDD_1V8
L1
L14 1
BLM18PG181SN1D
JP5
R0603
Header 1X2
1
100K
R0402
U2
GND_POWER
VOUT
VIN
2
C15
1uF
C0603
GND_POWER
For MPU
VDDFUSE
U5
4
DNP
R0402
Fixed output 1V8, 3v3,
C5
1uF
C0603
VDDSDHC1V8
1
2
VDD_3V3
5
5
For DDR2
GND_POWER
C3
10uF
C0603
VDDIODDR
4
R6
VDD_MAIN_5V
JP4
Header 1X2
VDD_1V8
1
2
8
3
R2
100K
R0402
(Super)-Capacitor
energy storage
EPAD
4
C2
100nF
C0402
GND_POWER
GND_POWER
U4B
DMP2160UFD
5
VBUS_USBA
B
D
C18
100nF
C0402
GND_POWER
C
1
2
5
3
13
1
DS50002709A-page 51
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-4. MPU Power
5
4
VDDCORE
(1V2)
C19
10uF
C0603
D
2
3
C27
10uF
C0603
1
VDDCORE
C31
100nF
C0402
C33
100nF
C0402
C35
100nF
C0402
C43
100nF
C0402
C47
100nF
C0402
C49
100nF
C0402
C51
1nF
C0402
C58
1nF
C0402
C60
1nF
C0402
C32
100nF
C0402
C34
100nF
C0402
C36
100nF
C0402
C44
100nF
C0402
C48
100nF
C0402
C50
100nF
C0402
C52
1nF
C0402
C59
1nF
C0402
C61
1nF
C0402
D
GND_POWER
U6G
VDDIODDR
(1V8)
POWER TEST POINTS
VDD_MAIN_5V
C
TP1 SMD
VDD_1V8
TP2 SMD
VDD_1V25
TP3 SMD
VDD_3V3
TP4 SMD
VDDFUSE
TP5 SMD
VDDSDHC1V8
TP6 SMD
C20
10uF
C0603
GND_POWER
VDDBU
TP7 SMD
TP8 SMD
VDDBU
TP9 SMD
VDDHSIC
TP10 SMD
VDDFUSE
TP11 SMD
VDDUTMIC
TP12 SMD
VDDUTMII
TP13 SMD
VDDSDHC
TP14 SMD
VDDOSC
TP15 SMD
VDDPLLA
TP16 SMD
(3V3)
VDDBU
C21
100nF
C0402
GND_POWER
GND_POWER
VDDIOP0
VDDIOP1
VDDIOP0
C22
100nF
C0402
C45
100nF
C0402
GND_POWER
VDDIOP2
C46
100nF
C0402
GND_POWER
VDDHSIC
( 1V2)
VDDBU
(3V3)
N7
VDDANA
(3V3)
K3
VDDHSIC
C53
100nF
C0402
VDDFUSE
C39
100nF
C0402
C57
100nF
C0402
C54
4.7uF
C0805
GND_POWER
VDDUTMIC
C24
4.7uF
C0805
(3V3) N13
R14
VDDIOP2
(3V3) F10
VDDHSIC
(1V2)
VDDFUSE
(2V5) M12
VDDUTMIC
(1V2)
VDDUTMII
(3V3)
VDDUTMII
VDDSDHC
(3V3 or 1V8)
R9
T3
P7
P8
VDDSDHC (3V3 or 1V8)P11
VDDPLLA
(1V2)
U4
VDDOSC
(3V3)
T7
VDDISC
(3V3)
F4
GND_POWER
VDDUTMII
(3V3)
C30
100nF
C0402
VDDIOP1
VDDAUDIOPLL
TP18 SMD
VDDUTMIC
(1V2)
(3V3)
VDDAUDIOPLL (3V3)
VDDAUDIOPLL
(3V3)
E6
F7
VDDIOP0
GND_POWER
VDDFUSE
(2V5)
C23
100nF
C0402
GND_POWER
(1V8) D11
D12
D15
E15
H15
J15
L15
(3V3)VDDIOP2
VDDIOP1
C38
100nF
C0402
TP17 SMD
TP19 SMD
VDDIODDR
L5
(3V3)
C29
100nF
C0402
GND_POWER
B
(1V2)
VDDANA
C37
100nF
C0402
D7
D9
H3
K13
N5
N9
VDDCORE
VDDANA
(3V3)
( 3V3)
VDDCORE
VDDIODDR
VDDIODDR
C28
10uF
C0603
GND_POWER
R0603
VDDOSC
VDDPLLA
(1V 2)
VDDPLLA
C26
100nF
C0402
C41
4.7uF
C0805
C25
4.7uF
C0805
N6
GNDBU
VDDANA
L3
GNDANA
K5
GNDADC
VDDADC
VDDIOP0_1
VDDIOP0_2
GNDIOP0_1
GNDIOP0_2
VDDIOP1_1
VDDIOP1_2
GNDIOP1_1
GNDIOP1_2
VDDIOP2
C
F6
G7
M13
P14
F9
GNDIOP2
VDDHSIC
VDDFUSE
T5
GNDDPLL
VDDAUDIOPLL
T4
GNDAUDIOPLL
VDDUTMIC
R7
GNDUTMIC
VDDUTMII
P9
GNDUTMII
R11
GNDSDMMC
VDDSDMMC
VDDPLLA
GNDPLLA
VDDOSC
GNDOSC
VDDISC
GNDISC
GNDUTMII
U5
T6
B
G4
GND_POWER
A copper plan
for GNDUTMII cover
all USB compoments
GNDUTMII
VDDISC
(3 V 3 )
R21
1R-1%
R0603
VDDBU
0R
GND_POWER
GND_POWER
R20
1R-1%
R0603
D14
E11
E12
E14
H14
J14
L14
GNDDDR_1
GNDDDR_2
GNDDDR_3
GNDDDR_4
GNDDDR_5
GNDDDR_6
GNDDDR_7
ATSAMA5D27C-CN
bga289p8
R22
GND_POWER
VDDDDR_1
VDDDDR_2
VDDDDR_3
VDDDDR_4
VDDDDR_5
VDDDDR_6
VDDDDR_7
VDDSDHC
C55
100nF
C0402
C40
100nF
C0402
E7
E9
H4
K12
M5
M9
GNDCORE_1
GNDCORE_2
GNDCORE_3
GNDCORE_4
GNDCORE_5
GNDCORE_6
VDDCORE_1
VDDCORE_2
VDDCORE_3
VDDCORE_4
VDDCORE_5
VDDCORE_6
VDDOSC
C42
100nF
C0402
(3V3)
VDDISC
C56
100nF
C0402
All 100nF 0402 capacitors close to the the Pin of VDD***.
A
A
GND_POWER
GND_POWER
GND_POWER
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
04) MPU_POWER
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
4
13
1
DS50002709A-page 52
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-5. DDR2-SDRAM
5
4
2
3
1
2 x W972GG6KB-25, DDR2-800, 16 Meg x 16 x 8
U6E
D
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
F12
C17
B17
B16
C16
G14
F14
F11
C14
D13
C15
A16
A17
G11
DDR_BA0
DDR_BA1
DDR_BA2
H12
H13
F17
DDR_RAS
DDR_CAS
F13
G12
DDR_CLK+
DDR_CLKDDR_CKE
E17
D17
F16
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_BA0
DDR_BA1
DDR_BA2
DDR_RAS
DDR_CAS
DDR_CLK
DDR_CLKN
DDR_CKE
R25
100K
R0402
GND_POWER
DDR_CS
G13
DDR_WE
F15
C
E13
VDDIODDR
21K-1%
R24
R0402
R23
100K
R0402
GND_POWER
DDR_RESETN
DDR_CAL
22pF
C64
C0402
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQSN0
DDR_DQS1
DDR_DQSN1
E16
DDR_VREF
C62
100nF
C0402
DDR_CS
DDR_WE
U7
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
H16
D16
C63
100nF
C0402
DDR_RESETN
DDR_DQS2
DDR_DQSN2
DDR_VREFB0
DDR_VREFCM
DDR_DQS3
DDR_DQSN3
B12
A12
C12
A13
A14
C13
A15
B15
G17
G16
H17
K17
K16
J13
K14
K15
B8
B9
C9
A9
A10
D10
B11
A11
J12
H10
J11
K11
L13
L11
L12
M17
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
C11
G15
C8
H11
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
B13
B14
DDR_DQS0+
DDR_DQS0-
J17
J16
DDR_DQS1+
DDR_DQS1-
C10
B10
DDR_DQS2+
DDR_DQS2-
L17
L16
DDR_DQS3+
DDR_DQS3-
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_CKE
DDR_CLK+
DDR_CLK-
K2
J8
K8
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
K7
L7
K3
L8
R7
R3
E2
A2
A3
E3
J3
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
ATSAMA5D27C-CN
bga289p8
J7
GND_POWER
U8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
BA0
BA1
BA2
LDQS_P
NU/LDQS_N
UDQS_P
NU/UDQS_N
CKE
CK_P
CK_N
LDM
UDM
RAS
CAS
WE
CS
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
F7
E8
B7
A8
DDR_DQS0+
DDR_DQS0DDR_DQS1+
DDR_DQS1-
F3
B3
DDR_DQM0
DDR_DQM1
A1
E1
J9
M9
R1
VDD1
VDD2
VDD3
VDD4
VDD5
VSS1
VSS2
VSS3
VSS4
VSS5
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
VDD_1V8
K9
ODT
NC4
NC3
NC2
NC1
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
R29
DNP
R0402
R30
0R
R0402
VDD_1V8
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_CKE
DDR_CLK+
DDR_CLK-
K2
J8
K8
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
K7
L7
K3
L8
R7
R3
E2
A2
GND_POWER
A3
E3
J3
N1
P9
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
J1
J2
VDDL
VREF
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
DDR_VREF
J7
VSSDL
C72
100nF
C0402
W972GG6KB-25
bga84-32-1509e
C75
1nF
C0402
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
BA0
BA1
BA2
LDQS_P
NU/LDQS_N
UDQS_P
NU/UDQS_N
CKE
CK_P
CK_N
LDM
UDM
RAS
CAS
WE
CS
ODT
NC4
NC3
NC2
NC1
VDD1
VDD2
VDD3
VDD4
VDD5
VSS1
VSS2
VSS3
VSS4
VSS5
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDL
VREF
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
F7
E8
B7
A8
DDR_DQS2+
DDR_DQS2DDR_DQS3+
DDR_DQS3-
F3
B3
DDR_DQM2
DDR_DQM3
VDD_1V8
K9
A1
E1
J9
M9
R1
R31
DNP
R0402
R32
0R
R0402
VDD_1V8
GND_POWER
C
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
J2
DDR_VREF
VSSDL
C94
100nF
C0402
W972GG6KB-25
bga84-32-1509e
GND_POWER
D
C95
1nF
C0402
GND_POWER
GND_POWER
B
GND_POWER
B
VDDIODDR
VDD_1V8
C65
4.7uF
C0805
GND_POWER
C66
100nF
C0402
R26
2.2K-1%
R0402
DDR_VREF
C67
100nF
C0402
R27
2.2K-1%
R0402
DDR_CLK+
R28
DNP
DDR_CLK-
GND_POWER
C70
1uF
C0603
C73
1uF
C0603
C76
100nF
C0402
C78
100nF
C0402
C80
100nF
C0402
C82
100nF
C0402
C84
100nF
C0402
C86
100nF
C0402
C88
1nF
C0402
C90
1nF
C0402
C92
1nF
C0402
C71
1uF
C0603
C74
1uF
C0603
C77
100nF
C0402
C79
100nF
C0402
C81
100nF
C0402
C83
100nF
C0402
C85
100nF
C0402
C87
100nF
C0402
C89
1nF
C0402
C91
1nF
C0402
C93
1nF
C0402
GND_POWER
VDD_1V8
Keep nets as short as possible, therefore, DDR devices have to be placed close as possible of SAMA5D27
The layout DDR should use controlled impedance traces of ZO= 50ohm characteristic impedance.
A
C68
10uF
C0603
Address, control and data traces may not exceed 1.3 inches (33.0 mm).
Address, control and data traces must be length-matched to within 0.1 inch (2.54mm).
Address, control and data traces must match the data group trace lengths to within 0.25 inches (6.35mm).
C69
10uF
C0603
A
GND_POWER
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
05) DDR2-SDRAM
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
5
13
1
DS50002709A-page 53
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-6. PIOA & PIOB
5
4
U6A
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
D
U11
P10
T11
R10
U12
T12
R12
T13
N10
N11
U13
P15
N15
P16
M14
N16
M10
N17
U14
T14
P12
R13
U15
U16
T15
U17
P13
T16
R16
T17
R15
R17
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA11
PA12
PA13
R33
39R
R0402
SDMMC0_CK_PA0
PA1
R34
22R
R0402
SDMMC0_CMD_PA1
1
PA22
9
9
R35
22R
R0402
SDMMC0_DAT0_PA2
9
PA23
PA10_USER_BT
8
SPI0_NPCS0_PA17 10
SDMMC1_DAT0_PA18 9
SDMMC1_DAT1_PA19 9
SDMMC1_DAT2_PA20 9
SDMMC1_DAT3_PA21 9
PA3
R36
22R
R0402
SDMMC0_DAT1_PA3
9
PA4
R37
22R
R0402
SDMMC0_DAT2_PA4
9
PA5
R38
22R
R0402
SDMMC0_DAT3_PA5
9
PA6
R39
22R
R0402
SDMMC0_DAT4_PA6
9
PA7
R40
22R
R0402
PA8
R41
22R
R0402
SDMMC0_DAT6_PA8
9
PA9
R42
22R
R0402
SDMMC0_DAT7_PA9
9
SDMMC0_DAT5_PA7
NAND_IO7_PA29
NAND_CS_PA31
10
PA11
R44
22R
SDMMC0_VDDSEL_PA11
QSPI0_NPCS_PA23
R0402
NAND_IO1_PA23
10
NAND_IO2_PA24
10
R67
22R
R0402
PA25
R68
22R
R0402
R69
22R
R0402
QSPI0_IO1_PA25
PA26
R70
22R
R0402
QSPI0_IO2_PA26
R71
22R
R0402
NAND_IO4_PA26
10
PA27
R72
22R
R0402
NAND_IO5_PA27
10
R73
22R
R0402
R74
22R
R0402
NAND_IO6_PA28
R75
22R
R0402
SDMMC1_CMD_PA28
R76
22R
R0402
SDMMC1_CD_PA30
9
R77
22R
R0402
NAND_WEn_PA30
10
PA12
R45
22R
R0402
SDMMC0_WP_PA12
PA13
R46
22R
R0402
SDMMC0_CD_PA13
PA14
R47
39R
R0402
SPI0_SPCK_PA14
10
A
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB28
PB29
PB30
PB31
QSPI0_IO0_PA24
NAND_IO3_PA25
10
LED_RED_PB10 10
USBA_VBUS_5V_PB11 9
USBB_EN_5V_PB12 9
USBB_OVCUR_PB13 9
PA15
R48
22R
R0402
SPI0_MOSI_PA15
10
PA16
R49
22R
R0402
SPI0_MISO_PA16
10
10
10
QSPI0_IO3_PA27
PB2
R50
39R
R0402
ETH_GTXCK_PB14
11
PB15
R51
22R
R0402
ETH_GTXEN_PB15
11
R52
22R
R0402
ETH_GRXDV_PB16
PB17
R53
22R
R0402
ETH_GRXER_PB17
PB18
R54
22R
R0402
ETH_GRX0_PB18
11
PB19
R55
22R
R0402
ETH_GRX1_PB19
11
R0402
ETH_GTX0_PB20
11
ETH_GTX1_PB21
11
PB16
XPRO2_GPIO_PB25 13
DBGU_URXD0_PB26 12
DBGU_UTXD0_PB27 12
R56
22R
PB21
R57
22R
R0402
PB22
R58
22R
R0402
PB23
R59
22R
R0402
PB24
R60
22R
R0402
22R
R80
100R-1% R0402
R81
22R
R82
100R-1% R0402
R83
22R
PB_PORT_0
R0402
10
10
9
R0402
PB_PORT_2
100R-1% R0402
PB_PORT_3
13
R85
100R-1% R0402
PB_PORT_4
13
PB_PORT_5
13
PB_PORT_6
13
R86
100R-1% R0402
R87
100R-1% R0402
22R
10
13
NAND_REn_PB2
R84
R88
10
13
NAND_CLE_PB1
R0402
R0402
LED_BLUE_PB6
10
B
10
PB7
R89
100R-1% R0402
PB_PORT_7
PB9
R43
22R
R0402
XPRO1_GPIO_PB9
PB28
R90
DNP
R0402
SPI_MOSI_PB28
R91
22R
13
13
13
R0402
TWI_SDA_PB28
R92
DNP
R0402
SPI_MISO_PB29
R93
22R
R0402
TWI_SCL_PB29
13
PB30
R94
DNP
R0402
SPI_SCK_PB30
13
PB31
R95
DNP
R0402
SPI_CS_PB31
13
13
13
11
11
A
ETH_INT_PB24
11
B
A
A
REV
SAMA5D2-PTC-EK
3
13
NAND_ALE_PB0
PB_PORT_1
PB4
PB29
11
ETH_GMDIO_PB23
100R-1% R0402
R79
PB3
11
ETH_GMDC_PB22
R78
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
2
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
VER.
DATE
REV.
SHEET
B
06) PIOA&PIOB
© 2017 Microchip Technology Inc.
10
C
PB14
PB20
4
D
10
9
ATSAMA5D27C-CN
bga289p8
5
10
9
PB6
LED_GREEN_PB8
9
10
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB9
10
10
R0402
9
22R
QSPI0_SCK_PA22
R0402
PB5
J8
A8
A7
A6
B6
B7
C7
C6
A5
A4
H8
B5
D6
B4
C5
H7
D5
C4
A3
D4
B3
A2
C3
A1
E5
B2
E4
B1
C2
D3
D2
C1
NAND_IO0_PA22
22R
PA28
All resistors on this page connected to PIOs populated close to MPU
PB00
PB01
PB02
PB03
PB04
PB05
PB06
PB07
PB08
PB09
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
SDMMC1_CK_PA22
R0402
22R
PB1
U6B
R0402
R0402
22R
R66
PB0
B
39R
39R
R63
R65
9
R0402
R61
R62
R64
PA24
PA30
PA30
ATSAMA5D27C-CN
bga289p8
C
PA0
PA2
PA14
PA15
PA16
PA22
PA23
PA24
PA25
PA26
PA27
PA28
2
3
6
13
1
DS50002709A-page 54
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-7. PIOC & PIOD
5
4
2
3
1
All resistors on this page connected to PIOs populated close to MPU
VDD_3V3
U6C
PC00
PC01
PC02
PC03
PC04
PC05
PC06
PC07
PC08
PC09
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
D
C
P17
N12
N14
M15
M11
L10
K10
M16
J10
D1
E3
E2
E1
F3
F5
F2
G6
F1
H6
G2
G3
G1
H2
G5
H1
H5
J9
H9
E8
G8
F8
D8
XPRO1_GPIO_PC0 13
SPCK_PC01 13
MOSI_PC02 13
MISO_PC03 13
NPCS0_PC04 13
MBUS_RST_PC05 13
PC6
PC7
NAND_RDY_PC8
10
LCD_IRQ1_PC9 13
LCD_D2_PC10 13
LCD_D3_PC11 13
LCD_D4_PC12 13
LCD_D5_PC13 13
LCD_D6_PC14 13
LCD_D7_PC15 13
LCD_D10_PC16 13
LCD_D11_PC17 13
LCD_D12_PC18 13
LCD_D13_PC19 13
LCD_D14_PC20 13
LCD_D15_PC21 13
LCD_D18_PC22 13
LCD_D19_PC23 13
LCD_D20_PC24 13
LCD_D21_PC25 13
LCD_D22_PC26 13
LCD_D23_PC27 13
LCD_PWM_PC28 13
LCD_EN_PC29 13
LCD_VSYNC_PC30
13
LCD_HSYNC_PC31
13
R97
R99
2.2K-1% 2.2K-1%
R0402
R0402
PC6
R118
R119
PC7
R120
R121
PD00
PD01
PD02
PD03
PD04
PD05
PD06
PD07
PD08
PD09
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
B
G10
E10
G9
K1
J6
J4
J2
J7
J1
K9
J3
M1
K8
L2
K4
K7
L1
K2
J5
K6
M2
N1
L4
M3
L7
L6
N2
L8
M4
N3
L9
M7
MPU_PD3
MPU_PD4
MPU_PD5
MPU_PD6
MPU_PD7
MPU_PD8
MPU_PD9
MPU_PD10
MPU_PD11
MPU_PD12
MPU_PD13
MPU_PD14
MPU_PD15
MPU_PD16
MPU_PD17
MPU_PD18
PD21
PD22
LCD_PCLK_PD0 13
LCD_DE_PD1 13
LCD_IRQ2_PD2 13
INT_PD19 13
PWM_PD20 13
RX_PD23 13
TX_PD24 13
AN-AD6 13
XPRO1_GPIO_PD26 13
JTAG_TCK_PD27 12
JTAG_TDI_PD28 12
JTAG_TDO_PD29 12
JTAG_TMS_PD30 12
XPRO2_GPIO_PD31 13
ATSAMA5D27C-CN
bga289p8
TWD1_PC6
22R
R0402
22R
R0402
TWCK1_PC7
10
XPRO_PC6
XPRO_PC7
13
10
13
VDD_3V3
R96
2.2K-1%
R0402
R98
2.2K-1%
R0402
TWI0
C
PD21
R100
22R
R0402
TWD0_PD21
PD22
R101
22R
R0402
TWCK0_PD22
MPU_PD3
R102
0R
PTC_XLINE0
MPU_PD4
R103
0R
PTC_XLINE1
13
MPU_PD5
R104
0R
PTC_XLINE2
13
MPU_PD6
R105
0R
PTC_XLINE3
13
MPU_PD7
R106
0R
PTC_XLINE4
13
ATSAMA5D27C-CN
bga289p8
U6D
D
TWI1
22R
R0402
22R
R0402
13
13
13
MPU_PD8
R107
0R
PTC_XLINE5
13
MPU_PD9
R108
0R
PTC_XLINE6
13
13
MPU_PD10
R109
0R
PTC_XLINE7
MPU_PD11
R110
0R
PTC_YLINE0
13
MPU_PD12
R111
0R
PTC_YLINE1
13
MPU_PD13
R112
0R
PTC_YLINE2
13
MPU_PD14
R113
0R
PTC_YLINE3
13
MPU_PD15
R114
0R
PTC_YLINE4
13
MPU_PD16
R115
0R
PTC_YLINE5
13
MPU_PD17
R116
0R
PTC_YLINE6
13
MPU_PD18
R117
0R
PTC_YLINE7
13
B
A
A
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
07) PIOC&PIOD
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
7
13
1
DS50002709A-page 55
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-8. System
5
4
2
3
1
D
D
Clock sources
Y1
1
C96
20pF
C0402
4
Routing top or bottom
3
C98
20pF
C0402
24MHz CL=10pF
x4s32x25
GND_POWER
3
8
3,8,11,12,13
NRST
2
Y2
X4S70X15
GND_POWER
R134
R135
R136
C100
C0402
1
3
P1
P2
DNP
R0402
0R
R0402
10K
R0402
XIN32
32.768KHz CL=12.5pF
C97
20pF
C0402
U7
U6
R1
P4
VDDBU R133
XOUT32
DNP
R0402
4
XIN
XOUT
XIN32
XOUT32
SHDN
WKUP
GND_POWER
R122
C
Max trace-length mismatch
between USB signals pairs
should be no greater than 3.8mm
XOUT
DNP
R0402
2
Routing USB
SAMA5D2 System Pins
XIN
R123
C99
20pF
C0402
20K-1%
R0402
22pF
RXD
T2
U2
P3
T10
N4
U3
VDDANA
R137
0R
R0402
M6
U6F
XIN
XOUT
HHSDPA
HHSDMA
XIN32
XOUT32
HHSDPB
HHSDMB
SHDN
WKUP
HSIC_DATA
HSIC_STRB
VBG
JTAGSEL
NRST
ACP
ACN
TST
SDCAL
PIOBU0
PIOBU1
PIOBU2
PIOBU3
PIOBU4
PIOBU5
PIOBU6
PIOBU7
RXD
CLK_AUDIO
ADVREFP
T8
R8
Top/Bot
Top/Bot
USBA_DP
USBA_DM
9
9
U8
U9
Top/Bot
Top/Bot
USBB_DP
USBB_DM
9
9
90 ohms differential trace
impedance
BP1
T9
U10
HSIC_DATA
HSIC_STRB
9
9
6
R6
U1
T1
PA10_USER_BT
USER BUTTON
C102
10pF
C0402
ACP
ACN
FSM2JSML
BP2
R139
5.62K-1%
R0402
DIS BOOT
10
DISABLE_BOOT
R145
PIOBU0
PIOBU1
PIOBU2
PIOBU3
PIOBU4
PIOBU5
PIOBU6
PIOBU7
FSM2JSML
BP3
GNDUTMII
R&C
as close as possible
RESET
3,8,11,12,13
NRST
R146
8
WKUP
R147
C
Tact Switch
100R-1%
FSM2JSML
r0402
BP4
WAKE UP
Tact Switch
100R-1%
r0402
R3
N8
R2
R5
R4
P5
P6
M8
Tact Switch
0R
R0402
Tact Switch
100R-1%
FSM2JSML
r0402
C101
100nF ATSAMA5D27C-CN
C0402 bga289p8
GND_POWER
R144
GND_POWER
VDDBU
R238
GND_POWER
10K
R0402
VDD_3V3
JTAG
J1
DNP
B
PIOBU0
PIOBU2
PIOBU4
PIOBU6
ACP
R124
R125
R126
R127
R128
330R
330R
330R
330R
0R
R0402
R0402
R0402
R0402
R0402
2
4
6
8
10
1
3
5
7
9
R129
R130
R131
R132
330R R0402
330R R0402
0R
R0402
0R
R0402
R140
100K
R0402
PIOBU3
PIOBU5
RXD
ACN
1
3
5
7
9
GND_POWER
12
2
1
RTCKIN
R138
R236
10K
R0402
PIOBU7
PIOBU1
B
R142
100K
R0402
VDD_3V3
FTSH-105-01-F-DV-P-TR
JP7
DNP
R141
100K
R0402
DNP
R0402
J2
2
4
6
8
10
R143
100R-1% R0402
CON_JTAG_Pin2 12
CON_JTAG_Pin4 12
CON_JTAG_Pin6 12
CON_JTAG_Pin8 12
NRST 3,8,11,12,13
Header 2X5
FTSH-105-01-F-DV-P-TR
GND_POWER
GND_POWER
A
A
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
08) SYSTEM
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
8
13
1
DS50002709A-page 56
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-9. USB & TF
5
4
2
3
1
VDD_3V3
VDDSDHC
R171
0R
R0402
R154
0R
R0402
USB A
R148
100K
R0402
USBA_VBUS_5V_PB11
C103
20pF
C0402
6
8
D
1
VBUS
DM 2
3
DP
4
ID
5
GND
SHD
9
10
MCI0
VBUS_USBA
6
R155
68k
R0603
R149
200K
R0402
6
6
GND_POWER
USBA_DM
USBA_DP
8
8
GND_POWER
7
11
J4
R159
68k
R0603
R161
68k
R0603
R165
68k
R0603
R167
68k
R0603
R169
10k
R0402
R172
10k
R0402
6 SDMMC0_CMD_PA1
6 SDMMC0_DAT3_PA5
6 SDMMC0_DAT2_PA4
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
6
6
6
6
(MCI0_DA4)
(MCI0_DA5)
(MCI0_DA6)
(MCI0_DA7)
SDMMC0_DAT4_PA6
SDMMC0_DAT5_PA7
SDMMC0_DAT6_PA8
SDMMC0_DAT7_PA9
D
GND_POWER
16
15
14
J6
13
12
11
10
GND_POWER
7SDMM-B0-2211
con_kingconn_7sdmm_2211
USB B
SD/MMCPlus CARD INTERFACE - MCI0
C
VDDSDHC1V8
DNP
R0402
DNP
R0402
R151
SH1
R152
USBB_VBUS_5V
1
2
3
4
USBB_DM
USBB_DP
8
8
4
1
SDMMC0_VDDSEL_PA11
EARTH_USB_B
6
IN
R150
10k
R0402
SDMMC1_CD_PA30
R162
68k
R0603
R164
68k
R0603
R166
68k
R0603
R168
68k
R0603
R170
10k
R0402
Micro SD
(MCI1_CD)
J7
10
SW2
8
7
6
5
4
3
2
1
GND_POWER
D
3
6
S2
S1
6
6
5
SDMMC1_DAT1_PA19
SDMMC1_DAT0_PA18
6
GND
6
J3
Single USB Type A
USB4_2AL
C107
100nF
C0402
VDD
U9
GND_POWER
SH2
R160
10k
R0402
VDD_3V3
2
VBUS
DM
DP
GND
SDMMC1_CK_PA22
6 SDMMC1_CMD_PA28
6 SDMMC1_DAT3_PA21
6 SDMMC1_DAT2_PA20
ADG849YKSZ-REEL
SC70
C
VDD_3V3
MCI1
VDDSDHC
(MCI1_DA1)
(MCI1_DA0)
(MCI1_CK)
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
SW1
VDD_3V3
5
6
C110 10uF
C0603
C111 100nF
C0402
R173
10k
R0402
8
7
6
5
4
3
2
1
9
(MCI0_CK)
SDMMC0_CK_PA0
GND_POWER
USBMICRO5_6A
MicroUSB AB Connector
EARTH_USB_A
A
R163
68k
R0603
(MCI0_DA1)
(MCI0_DA0)
SDMMC0_DAT1_PA3
SDMMC0_DAT0_PA2
6
R158
68k
R0603
(MCI0_WP)
(MCI0_CD)
SDMMC0_WP_PA12
SDMMC0_CD_PA13
6
6
R157
68k
R0603
C108
10uF
C0603
B
9
C109
100nF
C0402
11
12
13
14
PJS008-2120-0 GND_POWER
Micro_SD_PJS008
B
GND_POWER
USB C
GND_POWER
VDD_3V3
8
8
MHC50D30 MHC50D30 MHC50D30 MHC50D30
MH1
MH3
MH4
MH2
PTH
PTH
PTH
PTH
R153
10K
R0402
USBB_VBUS_5V
GND_POWER
A
1
C104
100nF
C0402
R0603
EARTH_USB_A
L16
BLM18PG181SN1D
1
2
GND_POWER
C105
10uF
C0603
2
R0603
VDD_MAIN_5V
1
L17
BLM18PG181SN1D
L15
BLM18PG181SN1D
1
2
8
6
7
5
GND_POWER
C106
100nF
C0402
U10
OUT_2
EN
OUT_1
FLG
IN_2
GND
IN_1
EN: Active High
1
USBB_EN_5V_PB12
2
USBB_OVCUR_PB13
3
Through Holes
6
GND_POWER
6
R156
10K
R0402
4
NC
1
HSIC_DATA
HSIC_STRB
1
1
2
1
DNP
J5
A
MIC2025-1YM-TR
soic8ja
R0603
GND_POWER
GND_POWER
GND_POWER
B
A
A
GND_POWER
EARTH_USB_B
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
09) USB&TF
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
9
13
1
DS50002709A-page 57
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-10. Memories & RGB LED
5
4
2
3
1
QSPI Flash & SPI Flash CS
VDD_3V3
C117
100nF
R178
10K
VCC
2
QSPI0_NPCS_PA23
GND_POWER
BOOT_DIS
8
QSPI0_CS_PA23
4
3
QSPI Flash
5
GND
NL17SZ126DFT2G
D
JP13
Header 1X2
R242
10K
QSPI Flash CS
1
2
6
VDD_3V3
R184
10K
U11
1
D
QSPI0_CS_PA23
VDD_3V3
DISABLE_BOOT
VDD_3V3
C116
100nF
U12
1
6
VCC
2
SPI0_NPCS0_PA17
R185
10K
5
6
6
6
6
SPI0_CS0_PA17
4
3
R186
10K
R0402
SPI Flash CS
GND
R187
10K
R0402
5
2
3
7
QSPI0_IO0_PA24
QSPI0_IO1_PA25
QSPI0_IO2_PA26
QSPI0_IO3_PA27
U14
SI/SIO0
SO/SIO1
SIO2
SIO3
VCC
GND
CS#
SCLK
8
4
1
6
C120
100nF
C0402
QSPI0_SCK_PA22
6
GND_POWER
SST26VF064B-104I/SM
soic8jg
NL17SZ126DFT2G
GND_POWER
C
C
3
6
LED_RED_PB10
R181
1
100R-1%
R0402
SPI Flash
LED
Q5
BSS138
SOT23_123
D4
2
GND_POWER
6
R182
LED_GREEN_PB8
VDD_3V3
Q7
BSS138
SOT23_123
1
100R-1%
R0402
R239
2.2K-1%
R0402
1
R240
1K
R0402
4
3
R241
2
R243
10K
VDD_3V3
Red
Green
Anode
5
2
6
6 SPI0_MOSI_PA15
6 SPI0_MISO_PA16
6 SPI0_SPCK_PA14
2
SPI0_CS0_PA17
3
1K
R0402
1
Blue
U16
SI
SO
SCK
CS
VCC
WP
HOLD
GND
8
3
7
C119
100nF
C0402
4
SST26VF032B-104I/SM
soic8jg
CLV1A-FKB-CJ1M1F1BB7R4S3
GND_POWER
6
R183
LED_BLUE_PB6
GND_POWER
3
GND_POWER
100R-1%
R0402
Q6
BSS138
SOT23_123
1
EEPROM+MAC
NAND Flash
2
B
R244
10K
B
3V3_NAND
GND_POWER
VDD_3V3
GND_POWER
R175
100K
6
6
6
6
6
R176
10K
R180
100K
16
17
8
18
9
NAND_CLE_PB1
NAND_ALE_PB0
NAND_REn_PB2
NAND_WEn_PA30
NAND_CS_PA31
7
R179
NAND_RDY_PC8
2
1
NAND_WPn
R177
DNP
JP8
Header 1X2
A
VDD_3V3
3V3_NAND
R174
C112
100nF
0R
C113
100nF
C114
100nF
C115
100nF
0R
7
19
1
2
3
4
5
6
10
11
14
15
22
23
24
26
27
28
33
40
U13
CLE
ALE
RE#
WE#
CE#
R/B#
WP#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
NC19
NC20
NC21
DNU4
DNU3
DNU2
DNU1
VCC_1
VCC_2
VCC_3
VCC_4
VSS_1
VSS_2
VSS_3
VSS_4
29
30
31
32
41
42
43
44
NAND_IO0_PA22
NAND_IO1_PA23
NAND_IO2_PA24
NAND_IO3_PA25
NAND_IO4_PA26
NAND_IO5_PA27
NAND_IO6_PA28
NAND_IO7_PA29
6
6
6
6
6
6
6
6
1
2
3
7
7
TWD1
TWCK1
TWD1_PC6
TWCK1_PC7
R188
10K
R0402
45
46
47
5
6
7
U15
A0
A1
A2
SDA
SCL
WP
VCC
8
C118
100nF
C0402
GND
4
24AA02E48
8MA2
GND_POWER
GND_POWER
38
35
20
21
3V3_NAND
A
12
34
37
39
B
A
A
13
25
36
48
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
10) MEMORIES&RGBLED
MT29F4G08ABADAWP
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
10
13
1
DS50002709A-page 58
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-11. Ethernet 10/100M
4
5
2
3
1
D
D
Ethernet
10Base-T/100Base-TX
R197
1K
R0402
CT
4
TD-
2
TX+
TX+
TXTX-
3
RX+
6
RX-
RD+
3
CT
5
RD-
6
NC
7
RX+
RX+
RXRX-
C
75
75
4
75
C121
100nF
C0402
C122
100nF
C0402
C123
C124
5
13
14
EARTH_ETH
15
16
1nF
75
7
8
top/bot
top/bot
top/bot
top/bot
2.2uF
C0603
100nF
C0402
GND_ETH
8
Right yellow LED
R194
Left Green LED
EARTH_ETH
9
10
11
12
VDD_3V3 GND_POWER
rj45_13f-64gy_P12_4
ACT ETH_LED1
LINK ETH_LED0
VDD_3V3
R189
510R
R0402
R190
510R
R0402
ETH_LED0
ETH_LED1
R192
10K
R0402
R193
10K
R0402
6.49K 1%
R0402
ETH_XO
ETH_XI
7
6
5
4
2
1
33
22
26
27
10
8
9
30
31
RXC/B-CAST_OFF
TXP
TXD1
TXD0
TXEN
RXD3/PHYAD0
RXD2/PHYAD1
RXD1/PHYAD2
RXD0/DUPLEX
RXDV/CONFIG2
RXER/ISO
CRS/CONFIG1
COL/CONFIG0
TXM
RXP
RXM
MDC
MDIO
INTRP/NAND
VDD_1V2
GND
PADDLE
TXC
TXD2
TXD3
REXT
19
ETH_GTXCK_PB14
25
24
23
13
14
15
16
18
20
29
28
6
ETH_GTX1_PB21 6
ETH_GTX0_PB20 6
ETH_GTXEN_PB15 6
ETH_GRX1_PB19 6
ETH_GRX0_PB18 6
ETH_GRXDV_PB16 6
ETH_GRXER_PB17 6
C
12
11
21
VDDA_3V3
VDDA_3V3
R203
10K
R0402
3
ETH_GMDC_PB22 6
ETH_GMDIO_PB23 6
ETH_INT_PB24 6
VDD_3V3
L19
BLM18PG181SN1D
1
2
R0603
C127
10uF
C0603
C129
100nF
C0402
C128
10uF
C0603
C130
100nF
C0402
R0402 10K
R206
TD+
TX-
R200
10K
R0402
R0402 10K
R202
TX+
2
R199
10K
R0402
R0402 10K
R205
1
1
R198
1K
R0402
R0402 10K
R201
U17
GND_POWER
XO
VDDIO
XI
17
LED0/NWAYEN
LED1/SPEED
GND_POWER
GND_POWER
RESET
32
R196
0R
R0402
NRST
3,8,12,13
KSZ8081RNB
qfn32_1p5h
B
R191
R0603
GND_POWER
At the De-Assertion of Reset:
Y3
GND_ETH
3
EARTH_ETH
ETH_XI
C125 22pF
C0402
0R
R0603
2
L18
BLM18PG181SN1D
1
2
B
1
13F-64GYD2PL2NL
C126 22pF
C0402
4
J8
R0402 10K
R204
100 ohms differential trace
impedance
Routing top or bottom
VDD_3V3
25MHz CL=20pF
x4s32x25
R195
DNP
R0402
PHY ADD[2:0]-pin15/14/13: 001 = 1
CONFIG[2:0]-pin18/29/28:001,RMII mode
Duplex Mode-pin16: 1,Half Duplex
Isolate Mode-pin20: 0,Disable
Speed Mode-pin31: 1,100Mbps
Nway Auto-Negotiation-p30: 1,Enable
ETH_XO
GND_POWER
A
A
B
A
A
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
11) Ethernet_10/100M
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
11
13
1
DS50002709A-page 59
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-12. JLINK-OB
4
2
3
VDD_MAIN_5V
U21
DBGU function switches
6
C152
2.2uF
C0603
VDD_3V3_3U
VCC
OE
VDD_3V3_3U
5
GND
OUT
RX_3U
4
C142
100nF
C0402
NL17SZ125DFT2SC-88A
C147
100nF
C0402
VDD_3V3_3U
C154
100nF
C0402
C153
2.2uF
C0603
5
7
NC
EP
GND
EN
C155
100nF
C0402
MIC5528-3.3YMTDFN6
GND_POWER
R247
IN
3
Max 500mA @ 3.3V
1
2
VOUT1
VOUT2
0R
EN_1
3
JP14
3
GND
OUT
4
U20
NL17SZ125DFT2SC-88A
TDI_3U
TDO_3U
TCK_3U
TMS_3U
B9
B8
A7
C7
C
ERASE_3U
D6
VDD_3V3_3U
J3
K4
NRST_3U
VDD_3V3_3U
R208
R209
10K
R0402
D5
PMEG6010CEGWX
sod123
C132 10nF
C0402
GND_POWER
R210
100R-1%
R0402
VDD_3V3_3U
GND_POWER
VDD_3V3_3U
4
C156
100nF
C0402
2
Y4
VCC
Out
GND
NC
3
1
C8
C136 10nF
C0402
D7
C9
R213
DNP
R0402
R214
6.8K-1%
R0402
C137 10pF
C0402
A1
A10
B10
EDBG_XIN
R245
0R
VDD_3V3_3U
ASE-12.000MHz-LC-T
B7
100R-1%
R0402
GND_POWER
A2
A3
R215
D8
100K
R0402
JLINK-OB
G3
F1
G2
J5
K5
H2
J1
K1
J2
E4
B4
G1
F2
G4
C4
G7
F7
A4
B5
C5
D5
A5
C6
A6
B6
IN
GND_POWER
TDI
TDO/TRACESWO
TCK/SWCLK
TMS/SWDIO
ERASE
ADVREF
AD12BVREF
NRST
NRSTB
TST
JTAGSEL
VBG
XIN32
XOUT32
XIN
XOUT
FWUP
PA0/PGMNCMD
PA1/PGMRDY
PA2/PGMNOE
PA3/PGMNVALID
PA4/PGMM0
PA5/PGMM1
PA6/PGMM2
PA7/PGMM3
PA8/PGMD0
PA9/PGMD1
PA10/PGMD2
PA11/PGMD3
PA12/PGMD4
PA13/PGMD5
PA14/PGMD6
PA15/PGMD7
PA16/PGMD8
PA17/PGMD9
PA18/PGMD10
PA19/PGMD11
PA20/PGMD12
PA21/PGMD13
PA22/PGMD14
PA23/PGMD15
PA24
PA25
PA26
PA27
E5
K3
B2
C3
E2
F6
G6
VDDIO_1
VDDIO_2
VDDIO_3
GNDBU
GNDANA
GNDUTMI
GNDPLL
GND_1
GND_2
GND_3
PA29
F3
F5
E6
VDDPLL
VDDOUT
VDDCORE_1
VDDCORE_2
VDDCORE_3
VDDCORE_4
VDDCORE_5
VDDCORE_6
B1
D4
E7
H1
G5
F9
D3
VDDIN
DHSDM
DFSDM
DFSDP
DHSDP
C10
K2
B3
39R R0402
39R R0402
A9
R211
R212
A8
D2
D1
C1
C2
GND_POWER
VDDBU
VDDANA
VDDUTMI
PA28
B
CON_JTAG_Pin8
PA30
PA31
J10
H9
H10
G8
G10
G9
F8
F10
E10
E9
E8
D9
D10
H5
K6
H6
J6
K7
H7
J7
K8
J8
H4
K9
H8
K10
J9
H3
TRSTIN
TRSTOUT
7
1
PA26_3U
2
TDOIN
3
4
JTAG_TDO_PD29
8
TRESIN
TRESOUT
16
5
CON_JTAG_Pin6
NOA
NCD
COMA
COMD
NCA
NOD
ABIN
CDIN
NOB
NCC
COMB
COMC
NCB
NOC
NLAS3899BMNTWG
WQFN-16
RX_3U
TX_3U
TDIIN
13
8
JTAG_TCK_PD27
R222
10
PA26_3U
9
CON_JTAG_Pin2
8
7
150R-1% TCKOUT
R0402
TCKIN
8
JTAG_TMS_PD30
7
7
R223
150R-1% TMSOUT
R0402
TMSIN
C
GND_POWER
TRESOUT
R219
150R-1%
R0402
R220
0R
TMSIN
TRESIN
R221
100R-1% NRST
R0402
TCKOUT
TMSOUT
TRSTOUT
TDIOUT
TDOIN
TCKIN
ENSPI
TCKOUT
PA25_3U
PA26_3U
E3
LED1_3U
E1
LED2_3U
3,8,11,13
TRSTIN
VDD_3V3_3U
VDD_3V3_3U
D6
J4
F4
CON_JTAG_Pin4
12
11
R216
150R-1% 2
R0402
R217
150R-1% 4
R0402
RTCKIN
RED
1
Green
3
1
JP9
Header 1X2
1
2
5
JTAG_TDI_PD28
8
15
R224
10K
R0402
PA25_3U
JTAG-CDC disable
3
B
GND_POWER
VDD_3V3_3U
KPTB-1615
8
JP10
Header 1X2
ATSAM3U4CA-CU
TFBGA100
1
2
VCC
7
ENSPI
6
150R-1%
R0402
TDIIN
GND
OE
2
DBGU_URXD0_PB26
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
1
TX_3U
GND_POWER
VCC
U22
TDIOUT R218
GND_POWER
U19
D
VDD_3V3_3U
JPR2
Jumper
14
U18
2
R246
10K
R0402
3
2
1
1
DBGU_UTXD0_PB27
6
VIN
3
4
PA25_3U
D
1
VDD_3V3_3U
6
5
R225
10K
R0402
PA26_3U
JTAG-OB disable
VDD_3V3_3U
(3V3)
6
SHD
10
1
VBUS
DM 2
3
DP
4
ID
5
GND
C134
2.2uF
C0603
EDBG_USB_DM
EDBG_USB_DP
GND_POWER
C138
2.2uF
C0603
C140
100nF
C0402
C143
100nF
C0402
C145
100nF
C0402
C148
100nF
C0402
C150
100nF
C0402
7
11
GND_POWER
A
J9
MicroUSB AB Connector
USBMICRO5_6A
EARTH_USB_EDBG
VDD_3V3_3U
PCB connector for SAMTEC MEC1-108-02
1
3
GND_POWER
VDD_OUT_3U
C135
2.2uF
C0603
L20
BLM18PG181SN1D
1
2
C139
2.2uF
C0603
C141
100nF
C0402
C144
100nF
C0402
C146
100nF
C0402
C149
100nF
C0402
7
9
11
13
15
C151
100nF
C0402
J10
TGTPOWER
GND1
GND2
NRST
TRACE D3
TDI
TRACE D2
TDO/SWO
TRACE D1 SWCLK/TCK
TRACE D0 SDWIO/TMS
TRACE_CK
VCC
2
4
8
10
12
14
16
NRST_3U
JP11
Header 1X2
1
2
8
VBUS_JLINK
9
GND_POWER
VDD_3V3_3U
VDD_OUT_3U
VDD_3V3_3U
TDI_3U
TDO_3U
TCK_3U
TMS_3U
A
VDD_3V3_3U
B
A
A
PADS ON PCB
Pin-16
REV
R0603
SAMA5D2-PTC-EK
GND_POWER
EARTH_USB_EDBG
© 2017 Microchip Technology Inc.
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
4
3
2
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
VER.
DATE
REV.
SHEET
B
12) JLINK-OB
GND_POWER
5
ERASE_3U
GND_POWER
12
13
1
DS50002709A-page 60
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
Figure 5-13. EXT Connectors
4
5
2
3
PIOB[0-7] Connector
MikroBUS
1
LCD-50PIN
VDD_3V3
6
6
6
6
6
6
6
6
1
2
3
4
5
6
7
8
9
10
PB_PORT_0
PB_PORT_1
PB_PORT_2
PB_PORT_3
PB_PORT_4
PB_PORT_5
PB_PORT_6
PB_PORT_7
J13
7 AN-AD6
MBUS_RST_PC05
7 NPCS0_PC04
7 SPCK_PC01
7 MISO_PC03
7 MOSI_PC02
VDD_3V3
7
1
2
3
4
5
6
7
8
PD25
RST
NPCS0
SPCK
MISO
MOSI
3V3
2
1
D
J15B
J15A
SSQ-108-01-G-S
1
2
3
4
5
6
7
8
PWM
INT
RX
TX
SCL
SDA
+5v R229
J16
PWM_PD20 7
INT_PD19 7
RX_PD23 7
TX_PD24 7
TWCK0_PD22 7
TWD0_PD21 7
DNP VDD_MAIN_5V
R0402
13
SPI_CS_PB31
7
7
LCD_D2_PC10
LCD_D3_PC11
7
7
7
7
LCD_D4_PC12
LCD_D5_PC13
LCD_D6_PC14
LCD_D7_PC15
100R-1%
R0402
DNP
R0603
XF2M-5015-1A
FPC50-0p5mm
GND_POWER
XPRO EXT1
6
C
7
PD11
PD13
PB9
PD15
PC 6
7,13 PTC_YLINE0
7,13 PTC_YLINE2
XPRO1_GPIO_PB9
7,13 PTC_YLINE4
7 XPRO_PC6
7,13 PTC_YLINE6
XPRO1_GPIO_PD26
R226
0R
PD17
PD26
J11
2
4
6
8
10
12
14
16
18
20
PD12
PD14
PC0
PD16
PC 7
PTC_YLINE1 7,13
PTC_YLINE3 7,13
XPRO1_GPIO_PC0
PTC_YLINE5 7,13
XPRO_PC7 7
PD18
PD17
PTC_YLINE7
PTC_YLINE6
R227
DNP
7
7,13
7,13
VDD_3V3
Header 2X10
GND_POWER
R235
0R
R228
0R
XPRO EXT2
7,13
7,13
7,13
7,13
6
PD3
PD5
PD7
PD9
PTC_XLINE0
PTC_XLINE2
PTC_XLINE4
PTC_XLINE6
PB25
XPRO2_GPIO_PB25
1
3
5
7
9
11
13
15
17
19
J12
2
4
6
8
10
12
14
16
18
20
PD4
PD6
PD8
PD10
PD31
PTC_XLINE1 7,13
PTC_XLINE3 7,13
PTC_XLINE5 7,13
PTC_XLINE7 7,13
XPRO2_GPIO_PD31
VDD_MAIN_5V
7
VDD_3V3
D
R230
SSQ-108-01-G-S
GND_POWER
1
3
5
7
9
11
13
15
17
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ID
GND1
D0
D1
D2
D3
GND2
D4
D5
D6
D7
GND3
D8
D9
D10
D11
GND4
D12
D13
D14
D15
GND5
D16
D17
D18
D19
GND6
D20
D21
D22
D23
GND7
PCLK/CMD
VSYNC/CS
HSYNC/WE
DE/RE
SPI_SCK
SPI_MOSI
SPI_MISO
SPI_CS
ENABLE
TWI_SDA
TWI_SCL
IRQ1
IRQ2
PWM
RESET
VCC1
VCC2
GND8
JP12
Header 1X2
PIOB[0-7] connector
R234
VDD_3V3
7
7
LCD_D10_PC16
LCD_D11_PC17
7
7
7
7
LCD_D12_PC18
LCD_D13_PC19
LCD_D14_PC20
LCD_D15_PC21
7
7
LCD_D18_PC22
LCD_D19_PC23
7
7
7
7
LCD_D20_PC24
LCD_D21_PC25
LCD_D22_PC26
LCD_D23_PC27
7 LCD_PCLK_PD0
7 LCD_VSYNC_PC30
7 LCD_HSYNC_PC31
7 LCD_DE_PD1
6 SPI_SCK_PB30
6 SPI_MOSI_PB28
6 SPI_MISO_PB29
6 SPI_CS_PB31
7 LCD_EN_PC29
6 TWI_SDA_PB28
6 TWI_SCL_PB29
7 LCD_IRQ1_PC9
7 LCD_IRQ2_PD2
7 LCD_PWM_PC28
3,8,11,12 NRST
C
Header 2X10
GND_POWER
B
R231
0R
R0603
XPRO Connectors
7,13
7,13
7,13
7,13
7,13
7,13
7,13
7,13
PTC_YLINE7
PTC_YLINE6
PTC_YLINE5
PTC_YLINE4
PTC_YLINE3
PTC_YLINE2
PTC_YLINE1
PTC_YLINE0
7,13
7,13
7,13
7,13
7,13
7,13
7,13
7,13
PTC_XLINE0
PTC_XLINE1
PTC_XLINE2
PTC_XLINE3
PTC_XLINE4
PTC_XLINE5
PTC_XLINE6
PTC_XLINE7
B
GND_POWER
J14
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VDD_3V3
R232
R233 close to connecter
2.2K-1% 2.2K-1%
PTC Connector
TWI_SDA_PB28
TWI_SCL_PB29
A
046288026000846
B
A
A
GND_POWER
REV
SAMA5D2-PTC-EK
RevB
RevA
INIT EDIT
MODIF.
SCALE
THR 03-OCT-17
ZhouB 07-MAR-17
ZhouB 06-JAN-17
DES.
1/1
© 2017 Microchip Technology Inc.
4
3
2
VER.
DATE
REV.
SHEET
B
13) EXT_CONNECTORS
5
DATE
XXX XX-XXX-XX
XXX XX-XXX-XX
XXX XX-XXX-XX
13
13
1
DS50002709A-page 61
SAMA5D2-PTC-EK
Revision History
6.
Revision History
6.1
Rev. A - 12/2017
This is the initial released version of this user's guide.
© 2017 Microchip Technology Inc.
DS50002709A-page 62
SAMA5D2-PTC-EK
The Microchip Web Site
Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as
a means to make files and information easily available to customers. Accessible by using your favorite
Internet browser, the web site contains the following information:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support documents, latest software releases and archived
software
General Technical Support – Frequently Asked Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory
representatives
Customer Change Notification Service
Microchip’s customer notification service helps keep customers current on Microchip products.
Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata
related to a specified product family or development tool of interest.
To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on
“Customer Change Notification” and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included
in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
© 2017 Microchip Technology Inc.
DS50002709A-page 63
SAMA5D2-PTC-EK
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the
code protection features of our products. Attempts to break Microchip’s code protection feature may be a
violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software
or other copyrighted work, you may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,
BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,
SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL
ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2017 Microchip Technology Inc.
DS50002709A-page 64
SAMA5D2-PTC-EK
©
2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-2416-1
Quality Management System Certified by DNV
ISO/TS 16949
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer
fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
®
®
and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC
®
DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.
© 2017 Microchip Technology Inc.
DS50002709A-page 65
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