DN3525
N-Channel Depletion-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
The DN3525 is a low-threshold Depletion-mode
(normally-on) transistor that uses an advanced vertical
DMOS structure and a well-proven silicon gate
manufacturing process. This combination produces a
device with the power handling capabilities of bipolar
transistors and the high input impedance and positive
temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally induced
secondary breakdown.
High Input Impedance
Low Input Capacitance
Fast Switching Speeds
Low On-Resistance
Free from Secondary Breakdown
Low Input and Output Leakage
Applications
•
•
•
•
•
•
Normally-On Switches
Solid-State Relays
Converters
Constant-Current Sources
Power Supply Circuits
Telecommunication Switches
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where high breakdown voltage, high input impedance,
low input capacitance and fast switching speeds are
desired.
Package Type
3-lead SOT-89
(Top view)
DRAIN
SOURCE
DRAIN
GATE
See Table 3-1 for pin information.
2018 Microchip Technology Inc.
DS20005705A-page 1
DN3525
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ....................................................................................................................................... BVDSX
Drain-to-Gate Voltage .......................................................................................................................................... BVDGX
Gate-to-Source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, TA .................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless
otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle
Parameter
Sym.
Min.
Typ.
Max.
Unit
Drain-to-Source Breakdown
Voltage
BVDSX
250
—
—
V
VGS = –5V, ID = 100 µA
Gate-to-Source Off Voltage
VGS(OFF)
–1.5
—
–3.5
V
VDS = 15V, ID = 1 mA
∆VGS(OFF)
—
—
–4.5
IGSS
—
—
100
nA
VGS = ±20 V, VDS = 0V
—
—
1
µA
VDS = Maximum rating,
VGS = –5V
—
—
1
mA
VDS = 0.8 Maximum rating,
VGS = –5V, TA = 125°C (Note 1)
IDSS
300
—
—
mA
VGS = 0V, VDS = 15V
RDS(ON)
—
—
6
Ω
∆RDS(ON)
—
—
1.1
%/°C
Change in VGS(OFF) with
Temperature
Gate Body Leakage Current
Drain-to-Source Leakage Current
Saturated Drain-to-Source Current
Static Drain-to-Source On-State
Resistance
Change in RDS(ON) with
Temperature
Note 1:
Conditions
mV/°C VDS = 15V, ID = 1 mA (Note 1)
ID(OFF)
VGS = 0V, ID = 200 mA
VGS = 0V, ID = 200 mA (Note 1)
Specification is obtained by characterization and is not 100% tested.
DS20005705A-page 2
2018 Microchip Technology Inc.
DN3525
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. Specification is obtained by characterization and is
not 100% tested.
Parameter
Sym.
Min.
Typ.
Max.
Forward Transconductance
GFS
225
—
—
Input Capacitance
CISS
—
270
350
pF
Common Source Output
Capacitance
COSS
—
20
60
pF
Reverse Transfer Capacitance
CRSS
—
5
20
pF
Turn-On Delay Time
td(ON)
—
—
20
ns
tr
—
—
25
ns
td(OFF)
—
—
25
ns
tf
—
—
40
ns
VSD
—
—
1.8
V
VGS = –5V, ISD = 150 mA
(Note 1)
trr
—
800
—
ns
VGS = –5V, ISD = 150 mA
Rise Time
Turn-Off Delay Time
Fall Time
Unit
Conditions
mmho VDS = 10V, ID = 150 mA
VGS = –5V,
VDS = 25V,
f = 1 MHz
VDD = 25V,
ID = 150 mA,
RGEN = 25Ω,
VGS = 0V to –10V
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
Unless otherwise stated, all DC parameters are 100% tested at 25°C. Pulse test: 300 µs pulse, 2% duty
cycle
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
133
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
3-lead SOT-89
THERMAL CHARACTERISTICS
Package
3-lead SOT-89
Note 1:
2:
ID (Note 1)
(Continuous)
(mA)
ID
(Pulsed)
(A)
Power Dissipation at
TA = 25°C
(Note 2)
(W)
IDR (Note 1)
(mA)
IDRM
(A)
360
1
1.6
360
1
ID (continuous) is limited by maximum TJ.
Mounted on an FR4 board, 25 mm x 25 mm x 1.57 mm
2018 Microchip Technology Inc.
DS20005705A-page 3
DN3525
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
1.4
1.4
VGS = +2V
VGS = +2V
1.2
1.2
0V
ID (Amperes)
ID (Amperes)
0V
1.0
1.0
-0.5V
0.8
-0.8V
0.6
-1V
0.4
-0.5V
0.8
-0.8V
0.6
-1V
0.4
-1.5V
-1.5V
0.2
0.2
-2V
-2V
0.0
0
50
100
150
200
0.0
250
0
2
4
VDS (Volts)
FIGURE 2-1:
6
8
10
VDS (Volts)
Output Characteristics.
FIGURE 2-4:
1.0
Saturation Characteristics.
2.0
VDS=10V
TA = -55OC
SOT-89
0.8
1.6
0.6
PD (Watts)
GFS (Siemens)
TA = 25OC
TA = 125OC
0.4
0.2
0.8
0.4
0.0
0.0
0.2
0.4
0.6
0.8
0.0
1.0
0
ID (Milliamperes)
FIGURE 2-2:
Current.
Transconductance vs. Drain
Thermal Resistance (normalized)
SOT-89 (Pulsed)
SOT-89 (DC)
0.1
0.01
100
DS20005705A-page 4
100
125
150
1000
0.8
0.6
Maximum Rated Safe
SOT-89
TA = 25OC
PD = 1.6W
0.4
0.2
0
0.001
VDS (Volts)
FIGURE 2-3:
Operating Area.
75
1.0
1.0
10
50
FIGURE 2-5:
Power Dissipation vs.
Ambient Temperature.
TA = 25OC
0.001
1
25
TA (OC)
10
ID (Amperes)
1.2
0.01
0.1
1
10
tp (Seconds)
FIGURE 2-6:
Characteristics.
Thermal Response
2018 Microchip Technology Inc.
DN3525
25
1.2
Tj = 25OC
ID = 100A
VGS = -5V
20
VGS = 0V
RDS(ON) (Ohms)
BVDSV (Normalized)
1.1
1.0
15
10
0.9
5
0
50
100
0
0.0
150
0.2
0.4
O
Tj ( C)
FIGURE 2-7:
Temperature.
FIGURE 2-10:
Current.
BVDSV Variation with
2000
VDS = 10V
TA = -55OC
0.8
1.0
1.2
On-Resistance vs. Drain
VGS(OFF) and RDS(ON) w/ Temperature
1.3
2.4
2.2
1.2
VGS(OFF) (Normalized)
1600
ID (Milliamperes)
0.6
ID (Amperes)
TA = 25OC
1200
TA = 125OC
800
2.0
1.1
VGS(OFF) @ 1mA, 15V
1.0
1.8
0.9
1.6
0.8
1.4
0.7
1.2
1.0
0.6
400
RDS(ON) @ 0V, 200mA
0.8
0.5
0
RDS(ON) (Normalized)
0.8
-50
0.6
0.4
-3
-2
-1
0
1
-50
2
-25
0
25
VGS (Volts)
FIGURE 2-8:
50
75
100
125
150
O
Tj ( C)
Transfer Characteristics.
FIGURE 2-11:
Temperature.
VGS(OFF) and RDS(ON) with
3
350
ID = 200mA
VGS = -5V
2
300
1
VGS (Volts)
C (Picofarads)
250
200
150
CISS
0
VDS = 30V
-1
-2
100
-3
COSS
50
-4
CRSS
0
-5
0
10
20
30
40
0
FIGURE 2-9:
Capacitance vs.
Drain-to-Source Voltage.
2018 Microchip Technology Inc.
1000
2000
3000
4000
5000
QG (Picocoulombs)
VDS (Volts)
FIGURE 2-12:
Characteristics.
Gate Drive Dynamic
DS20005705A-page 5
DN3525
3.0
PIN DESCRIPTION
Table 3-1 shows the description of pins in DN3525.
Refer to Package Type for the location of pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
Gate
Gate
2, 4
Drain
Drain
3
Source
DS20005705A-page 6
Description
Source
2018 Microchip Technology Inc.
DN3525
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for DN3525.
0V
VDD
90%
INPUT
-10V
Pulse
Generator
10%
t(ON)
td(ON)
VDD
tr
td(OFF)
RGEN
10%
90%
0V
FIGURE 4-1:
OUTPUT
tf
10%
OUTPUT
TABLE 4-1:
t(OFF)
RL
INPUT
D.U.T.
90%
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSX/BVDGX
(mA)
RDS(ON)
(Maximum)
(Ω)
IDSS
(Minimum)
(mA)
250
6
300
2018 Microchip Technology Inc.
DS20005705A-page 7
DN3525
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
3-lead SOT-89
XXXXYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005705A-page 8
Example
DN5C815
452
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2018 Microchip Technology Inc.
DN3525
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
C
E H
L
1
2
E1
3
b
b1
e
A
e1
Side View
Top View
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
A
MIN
Dimensions
(mm)
1.40
b
0.44
b1
0.36
C
0.35
D
4.40
D1
1.62
E
2.29
E1
2.00
e
e1
1.50
BSC
3.00
BSC
†
NOM
-
-
-
-
-
-
-
-
MAX
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
H
L
3.94
0.73†
-
-
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
2018 Microchip Technology Inc.
DS20005705A-page 9
DN3525
NOTES:
DS20005705A-page 10
2018 Microchip Technology Inc.
DN3525
APPENDIX A:
REVISION HISTORY
Revision A (May 2018)
• Converted Supertex Doc# DSFP-DN3525 to
Microchip DS20005705A
• Added a pin function table
• Changed the package marking format
• Made minor text changes throughout the document
2018 Microchip Technology Inc.
DS20005705A-page 11
DN3525
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
DN3525
=
N-Channel Depletion-Mode Vertical DMOS
FET
Package:
N8
=
3-lead SOT-89
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
2000/Reel for an N8 Package
DS20005705A-page 12
Example:
a) DN3525N8-G:
N-Channel Depletion-Mode Vertical
DMOS FET, 3-lead SOT-89,
2000/Reel
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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OTHERWISE, RELATED TO THE INFORMATION,
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3117-6
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005705A-page 13
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DS20005705A-page 14
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2018 Microchip Technology Inc.
10/25/17
