dsPIC30F1010/202X
28/44-Pin dsPIC30F1010/202X Enhanced Flash
SMPS 16-Bit Digital Signal Controller
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• 83 base instructions with flexible addressing
modes
• 24-bit wide instructions, 16-bit wide data path
• 12 Kbytes on-chip Flash program space
• 512 bytes on-chip data RAM
• 16 x 16-bit working register array
• Up to 30 MIPS operation:
- Dual Internal RC
- 9.7 and 14.55 MHz (±1%) Industrial Temp
- 6.4 and 9.7 MHz (±1%) Extended Temp
- 32X PLL with 480 MHz VCO
- PLL inputs ±3%
- External EC clock 6.0 to 14.55 MHz
- HS Crystal mode 6.0 to 14.55 MHz
• 32 interrupt sources
• Three external interrupt sources
• 8 user-selectable priority levels for each interrupt
• 4 processor exceptions and software traps
DSP Engine Features:
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• Single-cycle Multiply-Accumulate (MAC)
operation
• 40-stage Barrel Shifter
• Dual data fetch
2006-2014 Microchip Technology Inc.
Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Three 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
• One 16-bit Capture input functions
• Two 16-bit Compare/PWM output functions
- Dual Compare mode available
• 3-wire SPI modules (supports 4 Frame modes)
• I2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• UART Module:
- Supports RS-232, RS-485 and LIN 1.2
- Supports IrDA® with on-chip hardware endec
- Auto wake-up on Start bit
- Auto-Baud Detect
- 4-level FIFO buffer
Power Supply PWM Module Features:
• Four PWM generators with 8 outputs
• Each PWM generator has independent time base
and duty cycle
• Duty cycle resolution of 1.1 ns at 30 MIPS
• Individual dead time for each PWM generator:
- Dead-time resolution 4.2 ns at 30 MIPS
- Dead time for rising and falling edges
• Phase-shift resolution of 4.2 ns @ 30 MIPS
• Frequency resolution of 8.4 ns @ 30 MIPS
• PWM modes supported:
- Complementary
- Push-Pull
- Multi-Phase
- Variable Phase
- Current Reset
- Current-Limit
• Independent Current-Limit and Fault Inputs
• Output Override Control
• Special Event Trigger
• PWM generated ADC Trigger
DS70000178D-page 1
dsPIC30F1010/202X
Analog Features:
Special Microcontroller Features:
ADC
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100k (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip low
power RC oscillator for reliable operation
• Fail-Safe clock monitor operation
• Detects clock failure and switches to on-chip low
power RC oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes
- Sleep, Idle and Alternate Clock modes
•
•
•
•
10-bit resolution
2000 Ksps conversion rate
Up to 12 input channels
“Conversion pairing” allows simultaneous conversion of two inputs (i.e., current and voltage) with a
single trigger
• PWM control loop:
- Up to six conversion pairs available
- Each conversion pair has up to four PWM
and seven other selectable trigger sources
• Interrupt hardware supports up to 1M interrupts
per second
COMPARATOR
• Four Analog Comparators:
- 20 ns response time
- 10-bit DAC reference generator
- Programmable output polarity
- Selectable input source
- ADC sample and convert capable
• PWM module interface
- PWM Duty Cycle Control
- PWM Period Control
- PWM Fault Detect
• Special Event Trigger
• PWM-generated ADC Trigger
CMOS Technology:
•
•
•
•
Low-power, high-speed Flash technology
3.3V and 5.0V operation (±10%)
Industrial and Extended temperature ranges
Low power consumption
Product
Pins
Packaging
Program
Memory
(Bytes)
Data SRAM
(Bytes)
Timers
Capture
Compare
UART
SPI
I2C™
PWM
ADCs
S&H
A/D
Inputs
Analog
Comparators
GPIO
dsPIC30F SWITCH MODE POWER SUPPLY FAMILY
dsPIC30F1010
28
SDIP
6K
256
2
0
1
1
1
1
2x2
1
3
6 ch
2
21
dsPIC30F1010
28
SOIC
6K
256
2
0
1
1
1
1
2x2
1
3
6 ch
2
21
dsPIC30F1010
28
QFN-S
6K
256
2
0
1
1
1
1
2x2
1
3
6 ch
2
21
dsPIC30F2020
28
SDIP
12K
512
3
1
2
1
1
1
4x2
1
5
8 ch
4
21
dsPIC30F2020
28
SOIC
12K
512
3
1
2
1
1
1
4x2
1
5
8 ch
4
21
dsPIC30F2020
28
QFN-S
12K
512
3
1
2
1
1
1
4x2
1
5
8 ch
4
21
dsPIC30F2023
44
QFN
12K
512
3
1
2
1
1
1
4x2
1
5
12 ch
4
35
dsPIC30F2023
44
TQFP
12K
512
3
1
2
1
1
1
4x2
1
5
12 ch
4
35
DS70000178D-page 2
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
VSS
OSC1/CLKI/RB6
OSC2/CLKO/RB7
PGD1/EMUD1/T2CK/U1ATX/CN1/RE7
PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6
VDD
PGD2/EMUD2/SCK1/SFLT3/INT2/RF6
dsPIC30F1010
28-Pin SDIP and SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
RE5
VDD
VSS
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/SFLT1/INT1/RD0
AN1/CMP1B/CN3/RB1
AN0/CMP1A/CN2/RB0
MCLR
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
28-Pin QFN-S
28 27 26 25 24 23 22
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
VSS
OSC1/CLKI/RB6
OSC2/CLKO/RB7
1
2
3
4
5
6
7
dsPIC30F1010
21
20
19
18
17
16
15
PWM2L/RE2
PWM2H/RE3
RE4
RE5
VDD
VSS
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD1/EMUD1/T2CK/U1ATX/CN1/RE7
PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6
VDD
PGD2/EMUD2/SCK1/SFLT3/INT2/RF6
PGC2/EMUC2/OC1/SFLT1/INT1/RD0
SFLT2/INT0/OCFLTA/RA9
PGD/EMUD/SDO1/SCL/U1TX/RF8
8 9 10 11 12 13 14
2006-2014 Microchip Technology Inc.
DS70000178D-page 3
dsPIC30F1010/202X
Pin Diagrams
MCLR
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
VSS
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6
VDD
PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SDO1/SCL/U1TX/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0
AN1/CMP1B/CN3/RB1
AN0/CMP1A/CN2/RB0
MCLR
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
28-Pin QFN-S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC30F2020
28-Pin SDIP and SOIC
28 27 26 25 24 23 22
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
VSS
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
1
2
3
4
5
6
7
dsPIC30F2020
21
20
19
18
17
16
15
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6
VDD
PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6
PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0
SFLT2/INT0/OCFLTA/RA9
PGD/EMUD/SDO1/SCL/U1TX/RF8
8 9 10 11 12 13 14
DS70000178D-page 4
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
Pin Diagrams
PGD/EMUD/SDO1/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/IC1/INT1/RD0
PGD2/EMUD2/SCK1/INT2/RF6
VDD
VSS
OC2/RD1
SFLT1/RA8
AN9/EXTREF/CMP4D/RB9
PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
44-PIN QFN
44 43 42 41 40 39 38 37 36 35 34
PGC/EMUC/SDI1/RF7
SYNCO/SS1/RF15
SFLT3/RA10
SFLT4/RA11
SDA/RG3
VSS
VDD
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F2023
33
32
31
30
29
28
27
26
25
24
23
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN8/CMP4C/RB8
VSS
VDD
AN10/IFLT4/RB10
AN11/IFLT2/RB11
AN5/CMP2D/CMP3B/CN7/RB5
AN4/CMP2C/CMP3A/CN6/RB4
AN3/CMP1D/CMP2B/CN5/RB3
AN2/CMP1C/CMP2A/CN4/RB2
PWM1H/RE1
PWM1L/RE0
SYNCI/RF14
U1RX/RF2
AVSS
AVDD
MCLR
SCL/ RG2
U1TX/RF3
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
12 13 14 15 16 17 18 19 20 21 22
2006-2014 Microchip Technology Inc.
DS70000178D-page 5
dsPIC30F1010/202X
PGD/EMUD/SDO1/RF8
SFLT2/INT0/OCFLTA/RA9
PGC2/EMUC2/OC1/IC1/INT1/RD0
PGD2/EMUD2/SCK1/INT2/RF6
VDD
VSS
OC2/RD1
SFLT1/RA8
AN9/EXTREF/CMP4D/RB9
PGC1/EMUC1/PWM4L/T1CK/U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7
Pin Diagrams
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F2023
33
32
31
30
29
28
27
26
25
24
23
AN7/CMP3D/CMP4B/OSC2/CLKO/RB7
AN6/CMP3C/CMP4A/OSC1/CLKI/RB6
AN8/CMP4C/RB8
VSS
VDD
AN10/IFLT4/RB10
AN11/IFLT2/RB11
AN5/CMP2D/CMP3B/CN7/RB5
AN4/CMP2C/CMP3A/CN6/RB4
AN3/CMP1D/CMP2B/CN5/RB3
AN2/CMP1C/CMP2A/CN4/RB2
PWM1H/RE1
PWM1L/RE0
SYNCI/RF14
U1RX/RF2
AVSS
AVDD
MCLR
SCL/RG2
U1TX/RF3
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
22
21
20
19
18
17
16
15
14
13
12
PGC/EMUC/SDI1/RF7
SYNCO/SS1/RF15
SFLT3/RA10
SFLT4/RA11
SDA/RG3
VSS
VDD
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
DS70000178D-page 6
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 19
3.0 Memory Organization ................................................................................................................................................................. 29
4.0 Address Generator Units............................................................................................................................................................ 41
5.0 Interrupts .................................................................................................................................................................................... 47
6.0 I/O Ports ..................................................................................................................................................................................... 77
7.0 Flash Program Memory.............................................................................................................................................................. 81
8.0 Timer1 Module ........................................................................................................................................................................... 87
9.0 Timer2/3 Module ........................................................................................................................................................................ 91
10.0 Input Capture Module................................................................................................................................................................. 97
11.0 Output Compare Module .......................................................................................................................................................... 101
12.0 Power Supply PWM ................................................................................................................................................................. 107
13.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 145
14.0 I2C™ Module ........................................................................................................................................................................... 153
15.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 161
16.0 10-bit 2 Msps Analog-to-Digital Converter (ADC) Module........................................................................................................ 169
17.0 SMPS Comparator Module ...................................................................................................................................................... 191
18.0 System Integration ................................................................................................................................................................... 197
19.0 Instruction Set Summary .......................................................................................................................................................... 219
20.0 Development Support............................................................................................................................................................... 227
21.0 Electrical Characteristics .......................................................................................................................................................... 231
22.0 Package Marking Information................................................................................................................................................... 267
Appendix A: Revision History............................................................................................................................................................. 275
Index ................................................................................................................................................................................................. 277
2006-2014 Microchip Technology Inc.
DS70000178D-page 7
dsPIC30F1010/202X
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DS70000178D-page 8
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
1.0
DEVICE OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
2006-2014 Microchip Technology Inc.
This document contains device specific information for
the dsPIC30F1010/202X SMPS devices. These devices
contain extensive Digital Signal Processor (DSP) functionality within a high-performance 16-bit microcontroller
(MCU) architecture, as reflected in the following block
diagrams. Figure 1-1 and Table 1-1 describe the
dsPIC30F1010 SMPS device, Figure 1-2 and Table 1-2
describe the dsPIC30F2020 device and Figure 1-3 and
Table 1-3 describe the dsPIC30F2023 SMPS device.
DS70000178D-page 9
dsPIC30F1010/202X
FIGURE 1-1:
dsPIC30F1010 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
16
Data Latch
Y Data
RAM
(256 bytes)
Address
Latch
16
24
24
16
SFLT2/INT0/OCFLTA/RA9
PORTA
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Data Latch
X Data
RAM
(256 bytes)
Address
Latch
16
16
Address Latch
16
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CN6/RB4
AN5/CMP2D/CN7/RB5
OSC1/CLKI/RB6
OSC2/CLKO/RB7
Program Memory
(12 Kbytes)
Effective Address
16
Data Latch
ROM Latch
PORTB
16
24
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
OSC1/CLK1
Power-up
Timer
DSP
Engine
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
PGC2/EMUC2/OC1/SFLT1/
INT1/RD0
ALU
POR
Reset
Watchdog
Timer
MCLR
Comparator
Module
10-bit ADC
SPI1
Timers
Input
Change
Notification
16
PORTD
16
Output
Compare
Module
I2C™
SMPS
PWM
UART1
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
RE4
RE5
PGC1/EMUC1/EXTREF/T1CK/
U1ARX/CN0/RE6
PGD1/EMUD1/T2CK/U1ATX/
CN1/RE7
PORTE
PGD2/EMUD2/SCK1/SFLT3/
INT2/RF6
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
PORTF
DS70000178D-page 10
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
Table 1-1 provides a brief description of device I/O pinouts for the dsPIC30F1010 and the functions that may
be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010
Pin
Type
Buffer
Type
AN0-AN5
I
Analog
Pin Name
Description
Analog input channels.
AVDD
P
P
Positive supply for analog module.
AVSS
P
P
Ground reference for analog module.
CLKI
CLKO
I
O
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
PWM1L
PWM1H
PWM2L
PWM2H
I
I
I
O
O
O
O
ST
ST
ST
—
—
—
—
Shared Fault Pin 1
Shared Fault Pin 2
Shared Fault Pin 3
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1
O
—
Compare outputs.
OCFLTA
I
ST
Output Compare Fault Pin
OSC1
OSC2
I
I/O
CMOS
—
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/0
I
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
RB0-RB7
I/O
ST
PORTB is a bidirectional I/O port.
RA9
I/O
ST
PORTA is a bidirectional I/O port.
RD0
I/O
ST
PORTD is a bidirectional I/O port.
Legend: CMOS
ST
I
=
=
=
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
2006-2014 Microchip Technology Inc.
Analog =
O
=
P
=
Analog input
Output
Power
DS70000178D-page 11
dsPIC30F1010/202X
TABLE 1-1:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F1010 (CONTINUED)
Pin
Type
Buffer
Type
RE0-RE7
I/O
ST
PORTE is a bidirectional I/O port.
RF6, RF7, RF8
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
CN0-CN7
I
ST
Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
Ground reference for logic and I/O pins.
EXTREF
I
Analog
External reference to Comparator DAC
Pin Name
Legend: CMOS
ST
I
=
=
=
DS70000178D-page 12
Description
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog =
O
=
P
=
Analog input
Output
Power
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 1-2:
dsPIC30F2020 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
16
Data Latch
Y Data
RAM
(256 bytes)
Address
Latch
16
24
24
16
SFLT2/INT0/OCFLTA/RA9
PORTA
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Data Latch
X Data
RAM
(256 bytes)
Address
Latch
16
16
Address Latch
16
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/
OSC1/CLKI/RB6
Program Memory
(12 Kbytes)
Effective Address
16
Data Latch
AN7/CMP3D/CMP4B/
OSC2/CLKO/RB7
ROM Latch
PORTB
16
24
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
OSC1/CLK1
Power-up
Timer
DSP
Engine
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
PGC2/EMUC2/OC1/SFLT1/IC1/
INT1/RD0
ALU
POR
Reset
Watchdog
Timer
MCLR
16
PORTD
16
Comparator
Module
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
SPI1
Timers
Input
Change
Notification
SMPS
PWM
UART1
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PGC1/EMUC1/EXTREF/PWM4L/
T1CK/ U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/
U1ATX/CN1/RE7
PORTE
PGD2/EMUD2/SCK1/SFLT3/OC2/
INT2/RF6
PGC/EMUC/SDI1/SDA/U1RX/RF7
PGD/EMUD/SD01/SCL/U1TX/RF8
PORTF
2006-2014 Microchip Technology Inc.
DS70000178D-page 13
dsPIC30F1010/202X
Table 1-2 provides a brief description of device I/O pinouts for the dsPIC30F2020 and the functions that may
be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-2:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020
Pin
Type
Buffer
Type
AN0-AN7
I
Analog
AVDD
P
P
Positive supply for analog module.
AVSS
P
P
Ground reference for analog module.
CLKI
CLKO
I
O
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
IC1
I
ST
Capture input.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
I
O
O
O
O
O
O
O
O
ST
ST
ST
—
—
—
—
—
—
—
—
Shared Fault Pin 1
Shared Fault Pin 2
Shared Fault Pin 3
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
PWM 3 Low output
PWM 3 High output
PWM 4 Low output
PWM 4 High output
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1-OC2
OCFLTA
O
I
—
Compare outputs.
Output Compare Fault pin
OSC1
OSC2
I
I/O
CMOS
—
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Legend: CMOS
ST
I
=
=
=
Pin Name
DS70000178D-page 14
Description
Analog input channels.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 1-2:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020 (CONTINUED)
Pin
Type
Buffer
Type
RB0-RB7
I/O
ST
PORTB is a bidirectional I/O port.
RA9
I/O
ST
PORTA is a bidirectional I/O port.
RD0
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE7
I/O
ST
PORTE is a bidirectional I/O port.
RF6, RF7, RF8
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
—
ST
O
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
CN0-CN7
I
ST
Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
Ground reference for logic and I/O pins.
EXTREF
I
Analog
External reference to Comparator DAC
Pin Name
Legend: CMOS
ST
I
=
=
=
Description
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
2006-2014 Microchip Technology Inc.
Analog
O
P
=
=
=
Analog input
Output
Power
DS70000178D-page 15
dsPIC30F1010/202X
FIGURE 1-3:
dsPIC30F2023 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
16
Data Latch
Y Data
RAM
(256 bytes)
Address
Latch
16
24
16
SFLT1/RA8
SFLT2/INT0/OCFLTA/RA9
SFLT3/RA10
SFLT4/RA11
PORTA
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
Data Latch
X Data
RAM
(256 bytes)
Address
Latch
16
16
24
Address Latch
16
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/
OSC1/CLKI/RB6
Program Memory
(12 Kbytes)
Effective Address
16
Data Latch
ROM Latch
AN7/CMP3D/CMP4B/
OSC2/CLKO/RB7
AN8/CMP4C/RB8
AN9/EXTREF/CMP4D/RB9
AN10/IFLT4/RB10
AN11/IFLT2/RB11
16
24
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
16 16
Control Signals
to Various Blocks
OSC1/CLK1
Power-up
Timer
PORTB
DSP
Engine
PGC2/EMUC2/OC1/IC1/INT1/
RD0
OC2/RD1
PORTD
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
ALU
POR
Reset
Watchdog
Timer
MCLR
16
16
PORTE
Comparator
Module
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
SPI1
Timers
Input
Change
Notification
Power Supply
PWM
UART1
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PGC1/EMUC1/PWM4L/T1CK/
U1ARX/CN0/RE6
PGD1/EMUD1/PWM4H/T2CK/
U1ATX/CN1/RE7
U1RX/RF2
U1TX/RF3
PGD2/EMUD2/SCK1/INT2/RF6
PGC/EMUC/SDI1/RF7
PGD/EMUD/SD01/RF8
SYNCI/RF14
SYNCO/SSI/RF15
PORTF
SCL/RG2
SDA/RG3
PORTG
DS70000178D-page 16
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
Table 1-3 provides a brief description of device I/O pinouts for the dsPIC30F2023 and the functions that may
be multiplexed to a port pin. Multiple functions may
exist on one port pin. When multiplexing occurs, the
peripheral module’s functional requirements may force
an override of the data direction of the port pin.
TABLE 1-3:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023
Pin
Type
Buffer
Type
AN0-AN11
I
Analog
AVDD
P
P
Positive supply for analog module.
AVSS
P
P
Ground reference for analog module.
CLKI
CLKO
I
O
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
IC1
I
ST
Capture input.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0
External interrupt 1
External interrupt 2
SFLT1
SFLT2
SFLT3
SFLT4
IFLT2
IFLT4
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
I
I
I
I
O
O
O
O
O
O
O
O
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
Shared Fault 1
Shared Fault 2
Shared Fault 3
Shared Fault 4
Independent Fault 2
Independent Fault 4
PWM 1 Low output
PWM 1 High output
PWM 2 Low output
PWM 2 High output
PWM 3 Low output
PWM 3 High output
PWM 4 Low output
PWM 4 High output
SYNCO
SYNCI
O
I
—
ST
PWM SYNC output
PWM SYNC input
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active low Reset to the device.
OC1-OC2
OCFLTA
O
I
—
ST
Compare outputs.
Output Compare Fault condition.
OSC1
OSC2
I
I/O
CMOS
—
Legend: CMOS
ST
I
=
=
=
Pin Name
Description
Analog input channels.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
Oscillator crystal input.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in FRC and EC modes.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
2006-2014 Microchip Technology Inc.
Analog
O
P
=
=
=
Analog input
Output
Power
DS70000178D-page 17
dsPIC30F1010/202X
TABLE 1-3:
PINOUT I/O DESCRIPTIONS FOR dsPIC30F2023 (CONTINUED)
Pin
Type
Buffer
Type
PGD
PGC
PGD1
PGC1
PGD2
PGC2
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
In-Circuit Serial Programming data input/output pin 1.
In-Circuit Serial Programming clock input pin 1.
In-Circuit Serial Programming data input/output pin 2.
In-Circuit Serial Programming clock input pin 2.
RA8-RA11
I/O
ST
PORTA is a bidirectional I/O port.
Pin Name
Description
RB0-RB11
I/O
ST
PORTB is a bidirectional I/O port.
RD0,RD1
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE7
I/O
ST
PORTE is a bidirectional I/O port.
RF2, RF3,
RF6-RF8, RF14,
RF15
I/O
ST
PORTF is a bidirectional I/O port.
RG2, RG3
I/O
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
—
ST
Synchronous serial clock input/output for SPI #1.
SPI #1 Data In.
SPI #1 Data Out.
SPI #1 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C.
Synchronous serial data input/output for I2C.
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
Alternate UART1 Receive.
Alternate UART1 Transmit
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
CN0-CN7
I
ST
Input Change notification inputs
Can be software programmed for internal weak pull-ups on all inputs.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
Ground reference for logic and I/O pins.
Analog
External reference to Comparator DAC
EXTREF
Legend: CMOS
ST
I
I
=
=
=
DS70000178D-page 18
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
Comparator 4 Channel C
Comparator 4 Channel D
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog
O
P
=
=
=
Analog input
Output
Power
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
2.0
CPU ARCHITECTURE
OVERVIEW
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
2.1
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are supported using the DO and REPEAT instructions, both of
which are interruptible at any point.
The working register array consists of 16x16-bit registers, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device-specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can be
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined
by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction access
program space as if it were data space, with a limitation that the access requires an additional cycle.
Moreover, only the lower 16 bits of each instruction
word can be accessed using this method.
2006-2014 Microchip Technology Inc.
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing
mode on destination effective addresses, to greatly
simplify input or output data reordering for radix-2 FFT
algorithms. Refer to Section 4.0 “Address Generator
Units” for details on modulo and Bit-Reversed
Addressing.
The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined Addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits
right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by
dedicating certain working registers to each address
space for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
DS70000178D-page 19
dsPIC30F1010/202X
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
When a byte operation is performed on a working register, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes (MSBs) can be manipulated
through byte wide data memory space accesses.
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated software Stack Pointer (SP), and
will be automatically modified by exception processing
and subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
Note:
In order to protect against misaligned
stack accesses, W15 is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS Register
(SR), the LSB of which is referred to as the SR Low
Byte (SRL) and the MSB as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Priority Level Status bits, IPL, and the REPEAT active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value, which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3
PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
DS70000178D-page 20
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 2-1:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
AD39
Stack Pointer Limit Register
AD15
AD31
AD0
ACCA
DSP
Accumulators
ACCB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
Data Table Page Address
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
2006-2014 Microchip Technology Inc.
DC IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70000178D-page 21
dsPIC30F1010/202X
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1.
2.
3.
4.
5.
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.sw – 16/16 signed divide
DIV.uw – 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT.
The divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly
and correctly specified in the REPEAT instruction, as
shown in Table 2-1 (REPEAT will execute the target
instruction {operand value + 1} times). The REPEAT
loop count must be set up for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Note:
The Divide flow is interruptible. However,
the user needs to save the context as
appropriate.
DIVIDE INSTRUCTIONS
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd
Signed divide: (Wm + 1:Wm)/Wn W0; Rem W1
DIV.ud
Unsigned divide: (Wm + 1:Wm)/Wn W0; Rem W1
DIV.sw
Signed divide: Wm/Wn W0; Rem W1
DIV.uw
Unsigned divide: Wm/Wn W0; Rem W1
DS70000178D-page 22
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
2.4
DSP Engine
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/subtracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration Register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for ACCA (SATA).
Automatic saturation on/off for ACCB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection
(ACCSAT).
7.
Note:
For CORCON layout, see Table 3-3.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2:
DSP INSTRUCTION SUMMARY
Instruction
Algebraic Operation
CLR
A=0
ED
A = (x – y)2
ACC WB?
Yes
No
y)2
EDAC
A = A + (x –
MAC
A = A + (x * y)
MAC
A = A + x2
No
MOVSAC
No change in A
Yes
MPY
A=x*y
No
MPY.N
A=–x*y
No
MSC
A=A–x*y
Yes
2006-2014 Microchip Technology Inc.
No
Yes
DS70000178D-page 23
dsPIC30F1010/202X
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70000178D-page 24
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
2.4.1
MULTIPLIER
The 17x17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/
scaler is a 33-bit value, which is sign-extended to 40
bits. Integer data is inherently represented as a signed
two’s complement value, where the MSB is defined as
a sign bit. Generally speaking, the range of an N-bit
two’s complement integer is -2N-1 to 2N-1 – 1. For a 16bit integer, the data range is -32768 (0x8000) to 32767
(0x7FFF), including 0. For a 32-bit integer, the data
range
is
-2,147,483,648
(0x8000 0000)
to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1-21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF), including 0, and has a precision of 3.01518x10-5. In Fractional mode, a 16x16 multiply operation generates a 1.31 product, which has a
precision of 4.65661x10-10.
The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
2.4.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow Status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow Status bits
described above, and the SATA/B (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
3.
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
2006-2014 Microchip Technology Inc.
Adder/Subtracter, Overflow and
Saturation
4.
5.
6.
OA:
ACCA overflowed into guard bits
OB:
ACCB overflowed into guard bits
SA:
ACCA saturated (bit 31 overflow and saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
ACCB saturated (bit 31 overflow and saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 5.0 “Interrupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
DS70000178D-page 25
dsPIC30F1010/202X
The SA and SB bits are modified each time data passes
through the adder/subtracter, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit saturation, or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not
enabled, SA and SB default to bit 39 overflow and thus
indicate that a catastrophic overflow has occurred. If the
COVTE bit in the INTCON1 register is set, SA and SB
bits will generate an arithmetic warning trap when
saturation is disabled.
The overflow and saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS Register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This is useful for
complex number arithmetic, which typically uses both
the accumulators.
The device supports three Saturation and Overflow
modes.
1.
2.
3.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erroneous data or unexpected algorithm problems
(e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. When this Saturation
mode is in effect, the guard bits are not used (so
the OA, OB or OAB bits are never set).
Bit 39 Catastrophic Overflow
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
DS70000178D-page 26
2.4.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
2.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
[W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.15 data value is stored and the least
significant word (lsw) is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this
algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb (bit
16 of the accumulator) of ACCxH is examined. If it is ‘1’,
ACCxH is incremented. If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
2.4.2.4
Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MSb of the
source (bit 39) is used to determine the sign of the
operand being tested.
2.4.3
BARREL SHIFTER
The barrel shifter is capable of performing up to 15-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 15 for left shifts.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2006-2014 Microchip Technology Inc.
DS70000178D-page 27
dsPIC30F1010/202X
NOTES:
DS70000178D-page 28
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
3.0
MEMORY ORGANIZATION
FIGURE 3-1:
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
Reset – GOTO Instruction
Reset – Target Address
Reserved
Ext. Osc. Fail Trap
Address Error Trap
Stack Error Trap
Arithmetic Warn. Trap
Reserved
Reserved
Reserved
Vector 0
Vector 1
Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space, as defined by Table 3-1. Note that the program
space address is incremented by two between successive program words, in order to provide compatibility
with data space addressing.
Vector 52
Vector 53
User Memory
Space
3.1
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG to determine user or configuration space access. In Table 3-1, Read/Write instructions, bit 23 allows access to the Device ID, the User ID
and the Configuration bits. Otherwise, bit 23 is always
clear.
Note:
PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F1010/202X
Alternate Vector Table
000000
000002
000004
Vector Tables
000014
00007E
000080
0000FE
000100
User Flash
Program Memory
(4K instructions)
001FFE
002000
Reserved
(Read 0’s)
7FFFFE
800000
The address map shown in Figure 3-1 is
conceptual, and the actual memory configuration may vary across individual
devices depending on available memory.
Configuration Memory
Space
Reserved
8005BE
8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
2006-2014 Microchip Technology Inc.
FEFFFE
FF0000
FFFFFE
DS70000178D-page 29
dsPIC30F1010/202X
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Instruction Access
TBLRD/TBLWT
TBLRD/TBLWT
Program Space Visibility
FIGURE 3-2:
User
User
(TBLPAG = 0)
Configuration
(TBLPAG = 1)
User
Program Space Address
0
PC
TBLPAG
Data EA
TBLPAG
0
0
Data EA
PSVPAG
Data EA
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
Select
Using
Program
Space
Visibility
0
1
0
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 bits
User/
Configuration
Space
Select
16 bits
24-bit EA
Byte
Select
Note: Program Space Visibility cannot be used to access bits of a word in program memory.
DS70000178D-page 30
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
A set of Table Instructions is provided to move byte or
word sized data to and from program space.
1.
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can
also be present in program space.
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the least
significant word (lsw) of any address within program
space, without going through data space. The TBLRDH
and TBLWTH instructions are the only method whereby
the upper 8 bits of a program space word can be
accessed as data.
2.
3.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the Least Significant
Data Word, and TBLRDH and TBLWTH access the
space which contains the Most Significant Data Byte.
4.
TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P maps to D.
Byte: Read one of the LSBs of the program
address;
P maps to the destination byte when byte
select = 0;
P maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 7.0
“Flash Program Memory” for details on Flash
Programming).
TBLRDH: Table Read High
Word: Read the most significant word of the
program address;
P maps to D; D always
be = 0.
Byte: Read one of the MSBs of the program
address;
P maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 7.0
“Flash Program Memory” for details on Flash
Programming).
Figure 3-2 shows how the EA is created for table operations and data space accesses (PSV = 1). Here,
P refers to a program space word, whereas
D refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(Read as ‘0’).
2006-2014 Microchip Technology Inc.
TBLRDL.W
TBLRDL.B (Wn = 0)
TBLRDL.B (Wn = 1)
DS70000178D-page 31
dsPIC30F1010/202X
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
TBLRDH.W
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDH.B (Wn = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
3.1.2
TBLRDH.B (Wn = 1)
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16-bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the “dsPIC30F/33F Programmer’s Reference Manual”
(DS70157) for details on instruction encoding.
DS70000178D-page 32
Note that by incrementing the PC by 2 for each program memory word, the Least Significant 15 bits of
data space addresses directly map to the Least Significant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG, as
shown in Figure 3-5.
Note:
PSV access is temporarily disabled during
Table Reads/Writes.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions will require one instruction cycle in addition to the specified execution
time:
- MAC class of instructions with data operand
prefetch
- MOV instructions
- MOV.D instructions
• All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Data Space
Program Space
0x100100
0x0000
PSVPAG(1)
0x00
8
15
EA = 0
Data
Space
EA
16
15
EA = 1
0x8000
Address
15 Concatenation 23
23
15
0
0x001200
Upper half of Data
Space is mapped
into Program Space
0x001FFE
0xFFFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note: PSVPAG is an 8-bit register, containing bits of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
2006-2014 Microchip Technology Inc.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
256 byte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 256 bytes data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in Figure 3-6.
DS70000178D-page 33
dsPIC30F1010/202X
FIGURE 3-6:
DATA SPACE MEMORY MAP
MSB
Address
MSB
SFR Space
(Note)
0x0001
LSB
Address
16 bits
LSB
0x0000
SFR Space
0x07FE
0x0800
0x07FF
0x0801
2560 bytes
Near
Data
Space
X Data RAM (X)
256 bytes
512 bytes
SRAM Space
0x08FF
0x0901
0x08FE
0x0900
Y Data RAM (Y)
256 bytes
0x09FF
0x09FE
0x0A00
(See Note)
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
Note:
0xFFFE
Unimplemented SFR or SRAM locations read as ‘0’.
DS70000178D-page 34
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-7:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write)
MAC Class Ops (Write)
Indirect EA using any W
2006-2014 Microchip Technology Inc.
MAC Class Ops Read-Only
Indirect EA using W10, W11
Indirect EA using W8, W9
DS70000178D-page 35
dsPIC30F1010/202X
3.2.2
DATA SPACES
3.2.3
The X data space is used by all instructions and supports all Addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restrictions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. No writes occur
across the Y bus. This class of instructions dedicates
two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path, as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user programmable. Should an EA point to data outside its own
assigned address space, or to a location outside physical memory, an all-zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data
space in a MAC instruction
0x0000
W10 or W11 used to access X
data space in a MAC instruction
0x0000
DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to examine the machine state prior to execution of the address
fault.
FIGURE 3-8:
15
DATA ALIGNMENT
MSB
87
LSB
0
0001
Byte 1
Byte 0
0000
0003
Byte 3
Byte 2
0002
0005
Byte 5
Byte 4
0004
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70000178D-page 36
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6
SOFTWARE STACK
The dsPIC DSC device contains a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM
is forced to ‘0’, because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
2006-2014 Microchip Technology Inc.
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap will not occur.
The stack error trap will occur on a subsequent push
operation. Thus, for example, if it is desirable to cause
a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarly, a Stack Pointer Underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
CALL STACK FRAME
0x0000 15
Stack Grows Towards
Higher Address
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP: [--W15]
PUSH: [W15++]
3.2.7
DATA RAM PROTECTION
The dsPIC30F1010/202X devices support data RAM
protection features which enable segments of RAM to
be protected when used in conjunction with Boot Code
Segment Security. BSRAM (Secure RAM segment for
BS) is accessible only from the Boot Segment Flash
code when enabled. See Table 3-3 for the BSRAM
SFR.
DS70000178D-page 37
SFR Name
Addr.
CORE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
W0
0000
W0/WREG
0000 0000 0000 0000
W1
0002
W1
0000 0000 0000 0000
W2
0004
W2
0000 0000 0000 0000
W3
0006
W3
0000 0000 0000 0000
W4
0008
W4
0000 0000 0000 0000
W5
000A
W5
0000 0000 0000 0000
W6
000C
W6
0000 0000 0000 0000
W7
000E
W7
0000 0000 0000 0000
W8
0010
W8
0000 0000 0000 0000
W9
0012
W9
0000 0000 0000 0000
W10
0014
W10
0000 0000 0000 0000
W11
0016
W11
0000 0000 0000 0000
W12
0018
W12
0000 0000 0000 0000
W13
001A
W13
0000 0000 0000 0000
W14
001C
W14
0000 0000 0000 0000
W15
001E
W15
0000 1000 0000 0000
SPLIM
0020
SPLIM
0000 0000 0000 0000
ACCAL
0022
ACCAL
0000 0000 0000 0000
ACCAH
0024
ACCAH
ACCAU
0026
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
PCL
002E
0000 0000 0000 0000
Sign-Extension (ACCA)
ACCAU
0000 0000 0000 0000
0000 0000 0000 0000
Sign-Extension (ACCB)
ACCBU
0000 0000 0000 0000
2006-2014 Microchip Technology Inc.
PCH
0030
—
—
—
—
—
—
—
—
0032
—
—
—
—
—
—
—
—
TBLPAG
PSVPAG
0034
—
—
—
—
—
—
—
—
PSVPAG
RCOUNT
0036
DCOUNT
0038
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
0000 0000 0000 0000
PCL
TBLPAG
DOSTARTL
0000 0000 0000 0000
—
PCH
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
RCOUNT
uuuu uuuu uuuu uuuu
DCOUNT
uuuu uuuu uuuu uuuu
DOSTARTL
—
0
—
—
—
—
—
—
—
—
DOSTARTH
0040
—
—
—
—
—
—
—
—
DOENDH
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
CORCON
0044
—
—
—
US
EDT
DL2
DL1
DL0
SATA
SATB
DOENDL
Legend: u = uninitialized bit
—
0
IPL0
RA
SATDW ACCSAT
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
N
OV
Z
C
0000 0000 0000 0000
IPL3
PSV
RND
IF
0000 0000 0010 0000
dsPIC30F1010/202X
DS70000178D-page 38
TABLE 3-3:
2006-2014 Microchip Technology Inc.
TABLE 3-3:
SFR Name
CORE REGISTER MAP (CONTINUED)
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
MODCON
0046
XMODEN
YMODEN
—
—
XMODSRT
0048
XS
0
uuuu uuuu uuuu uuu0
XMODEND
004A
XE
1
uuuu uuuu uuuu uuu1
YMODSRT
004C
YS
0
uuuu uuuu uuuu uuu0
YMODEND
004E
YE
1
uuuu uuuu uuuu uuu1
XBREV
0050
BREN
DISICNT
0052
—
—
BSRAM
0750
—
—
BWM
Bit 5
Bit 4
Bit 3
YWM
Bit 2
Bit 1
Bit 0
XWM
0000 0000 0000 0000
XB
uuuu uuuu uuuu uuuu
DISICNT
—
—
—
—
—
—
—
Reset State
—
0000 0000 0000 0000
—
—
—
IW_BSR
IR_BSR
RL_BSR
0000 0000 0000 0000
Legend: u = uninitialized bit
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
DS70000178D-page 39
dsPIC30F1010/202X
NOTES:
DS70000178D-page 40
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
4.0
ADDRESS GENERATOR UNITS
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
TABLE 4-1:
4.1
Instruction Addressing Modes
The Addressing modes in Table 4-1 form the basis of
the Addressing modes optimized to support the specific
features of individual instructions. The Addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.1.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
2006-2014 Microchip Technology Inc.
The sum of Wn and a literal forms the EA.
DS70000178D-page 41
dsPIC30F1010/202X
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a working register (i.e., the
Addressing mode can only be register direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following Addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
5-bit or 10-bit Literal
Note:
4.1.3
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instructions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA. However, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).
4.1.4
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
Note:
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
In summary, the following Addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
In summary, the following Addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
DS70000178D-page 42
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
4.2
Modulo Addressing
Modulo addressing is a method of providing an automated means to support circular data buffers using
hardware. The objective is to remove the need for software to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo
addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for modulo
addressing, since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode, (i.e., address boundary checks will be performed on both the lower and
upper address boundaries).
4.2.1
START AND END ADDRESS
The modulo addressing scheme requires that a
starting and an end address be specified and loaded
into the 16-bit modulo buffer address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
Note:
Y-space modulo addressing EA calculations assume word sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.2.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control register MODCON contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X RAGU
and X WAGU modulo addressing are disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.
The X Address Space Pointer W register (XWM) to
which modulo addressing is to be applied, is stored in
MODCON (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM) to
which modulo addressing is to be applied, is stored in
MODCON. Modulo addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON.
2006-2014 Microchip Technology Inc.
DS70000178D-page 43
dsPIC30F1010/202X
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DO
MOV
AGAIN:
0x1100
#0x1100,W0
W0, XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
#0x0000,W0
#0x1110,W1
AGAIN,#0x31
W0, [W1++]
INC
W0,W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
;fill the 50 buffer locations
;fill the next location
;increment the fill value
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
DS70000178D-page 44
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo addressing can be applied to the Effective
Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than or greater than the
upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
4.3
The modulo corrected effective address is
written back to the register only when PreModify or Post-Modify Addressing mode is
used to compute the Effective Address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is performed, but the contents of the register
remains unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
2.
3.
XB is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
BWM (W register selection) in the MODCON
register is any value other than 15 (the stack can
not be accessed using Bit-Reversed
Addressing) and
the BREN bit is set in the XBREV register and
the Addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
All Bit-Reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other Addressing mode or for
byte sized data, and normal addresses will be generated instead. When Bit-Reversed Addressing is active,
the W Address Pointer will always be added to the
address modifier (XB) and the offset associated with
the register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the
LSb of the EA is ignored (and always clear).
Note:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
Modulo addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed Addressing will assume priority when active for the
X WAGU, and X WAGU modulo addressing will be disabled. However, modulo
addressing will continue to function in the
X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b1
b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16 word Bit-Reversed Buffer
2006-2014 Microchip Technology Inc.
DS70000178D-page 45
dsPIC30F1010/202X
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal
Address
A3
A2
A1
A0
Bit-Reversed
Address
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
TABLE 4-3:
Note 1:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Buffer Size (Words)
XB Bit-Reversed Address Modifier Value(1)
32768
0x4000
16384
0x2000
8192
0x1000
4096
0x0800
2048
0x0400
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
8
0x0004
4
0x0002
2
0x0001
Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010/202X device
DS70000178D-page 46
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
5.0
INTERRUPTS
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
• The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt priority level, which are latched into vector
number (VECNUM) and Interrupt level
(ILR) bit fields in the INTTREG register. The
new interrupt priority level is the priority of the
pending interrupt.
Note:
The dsPIC30F1010/202X device has up to 35 interrupt
sources and 4 processor exceptions (traps), which
must be arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained
in the interrupt vector to the Program Counter (PC).
The interrupt vector is transferred from the program
data bus into the Program Counter, via a 24-bit wide
multiplexer on the input of the Program Counter.
The Interrupt Vector Table and Alternate Interrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.
The interrupt controller is responsible for preprocessing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled, prioritized and controlled using centralized special function
registers:
• IFS0, IFS1, IFS2
All interrupt request flags are maintained in these
three registers. The flags are set by their respective peripherals or external signals, and they are
cleared via software.
• IEC0, IEC1, IEC2
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
• IPC0... IPC11
The user-assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
• IPL The current CPU priority level is explicitly stored in the IPL bits. IPL is present in the
CORCON register, whereas IPL are present
in the STATUS Register (SR) in the processor
core.
• INTCON1, INTCON2
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control and status flags for the processor exceptions.
The INTCON2 register controls the external interrupt request signal behavior and the use of the
alternate vector table.
2006-2014 Microchip Technology Inc.
Interrupt flag bits get set when an Interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers.
Each interrupt source is associated with an interrupt
vector, as shown in Figure 5-1. Levels 7 and 1 represent the highest and lowest maskable priorities,
respectively.
Note:
Assigning a priority level of 0 to an interrupt source is equivalent to disabling that
interrupt.
If the NSTDIS bit (INTCON1) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, interrupt-on-change, etc. Control of these features remains
within the peripheral module that generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in Program Memory that corresponds to the interrupt. There are 63 different vectors within the IVT (refer to Figure 5-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Figure 5-1).
These locations contain 24-bit addresses, and, in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execution of random data as a result of accidentally decrementing a PC into vector space, accidentally mapping
a data space address into vector space, or the PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
DS70000178D-page 47
dsPIC30F1010/202X
5.1
Interrupt Priority
The user-assignable Interrupt Priority (IP) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble, within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned to
a particular interrupt by the user.
Note:
The user selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural order priority is determined by the position of an
interrupt in the vector table, and only affects interrupt
operation when multiple interrupts with the same userassigned priority become pending at the same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. The INT0 (external interrupt
0) may be assigned to priority level 1, thus giving it a
very low effective priority.
DS70000178D-page 48
TABLE 5-1:
INT
Number
dsPIC30F1010/202X
INTERRUPT VECTOR TABLE
Vector
Number
Interrupt Source
Highest Natural Order Priority
0
8
INT0 – External Interrupt 0
1
9
IC1 – Input Capture 1
2
10
OC1 – Output Compare 1
3
11
T1 – Timer 1
4
12
Reserved
5
13
OC2 – Output Compare 2
6
14
T2 – Timer 2
7
15
T3 – Timer 3
8
16
SPI1
9
17
U1RX – UART1 Receiver
10
18
U1TX – UART1 Transmitter
11
19
ADC – ADC Convert Done
12
20
NVM – NVM Write Complete
13
21
SI2C – I2C™ Slave Event
14
22
MI2C – I2C Master Event
15
23
Reserved
16
24
INT1 – External Interrupt 1
17
25
INT2 – External Interrupt 2
18
26
PWM Special Event Trigger
19
27
PWM Gen#1
20
28
PWM Gen#2
21
29
PWM Gen#3
22
30
PWM Gen#4
23
31
Reserved
24
32
Reserved
25
33
Reserved
26
34
Reserved
27
35
CN – Input Change Notification
28
36
Reserved
29
37
Analog Comparator 1
30
38
Analog Comparator 2
31
39
Analog Comparator 3
32
40
Analog Comparator 4
33
41
Reserved
34
42
Reserved
35
43
Reserved
36
44
Reserved
37
45
ADC Pair 0 Conversion Done
38
46
ADC Pair 1 Conversion Done
39
47
ADC Pair 2 Conversion Done
40
48
ADC Pair 3 Conversion Done
41
49
ADC Pair 4 Conversion Done
42
50
ADC Pair 5 Conversion Done
43
51
Reserved
44
52
Reserved
45-53
53-61 Reserved
Lowest Natural Order Priority
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
5.2
Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The processor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory location, immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
5.3
Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
RESET SOURCES
In addition to External Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Trap Lockout:
Occurrence of multiple Trap conditions
simultaneously will cause a Reset.
If the user does not intend to take corrective action in the event of a Trap Error condition, these vectors must be loaded with
the address of a default handler that simply contains the RESET instruction. If, on
the other hand, one of the vectors containing an invalid address is called, an
address error trap is generated.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing priority. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The Math Error trap executes under the following four
circumstances:
1.
2.
3.
4.
2006-2014 Microchip Technology Inc.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
DS70000178D-page 49
dsPIC30F1010/202X
Address Error Trap:
5.3.2
This trap is initiated when any of the following
circumstances occurs:
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-1 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
1.
2.
3.
4.
A misaligned data word access is attempted.
A data fetch from our unimplemented data
memory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
Note:
5.
6.
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
Stack Error Trap:
HARD AND SOFT TRAPS
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 5-1:
TRAP VECTORS
1.
2.
The Stack Pointer is loaded with a value which
is greater than the (user-programmable) limit
value written into the SPLIM register (stack
overflow).
The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
Decreasing
Priority
This trap is initiated under the following conditions:
IVT
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
AIVT
DS70000178D-page 50
Reset - GOTO Instruction
Reset - GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
5.4
Interrupt Sequence
5.5
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current Program
Counter and the low byte of the processor STATUS
Register (SRL), as shown in Figure 5-2. The low byte
of the STATUS register contains the processor priority
level at the time, prior to the beginning of the interrupt
cycle. The processor then loads the priority level for
this interrupt into the STATUS register. This action will
disable all lower priority interrupts until the completion
of the Interrupt Service Routine (ISR).
FIGURE 5-2:
INTERRUPT STACK
FRAME
Stack Grows Towards
Higher Address
0x0000 15
0
Alternate Vector Table
In Program Memory, the IVT is followed by the AIVT, as
shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of
the default vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a support environment, without requiring the interrupt vectors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
If the AIVT is not required, the program memory allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using shadow registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
PC
SRL IPL3 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON) is always
clear when interrupts are being processed. It is set only during execution of
traps.
The RETFIE (Return from Interrupt) instruction will
unstack the Program Counter and status registers to
return the processor to its state prior to the interrupt
sequence.
2006-2014 Microchip Technology Inc.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instructions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
5.7
External Interrupt Requests
The interrupt controller supports three external interrupt request signals, INT0-INT2. These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to generate an interrupt request. The INTCON2 register has three bits, INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine needed to process the interrupt request.
DS70000178D-page 51
dsPIC30F1010/202X
REGISTER 5-1:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SFTACERR
DIV0ERR
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12
COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
bit 9
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divided by zero
0 = Math error trap was not caused by an invalid accumulator shift
bit 5
Unimplemented: Read as ‘0’
bit 4
MATHERR: Arithmetic Error Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
DS70000178D-page 52
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-1:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as ‘0’
2006-2014 Microchip Technology Inc.
DS70000178D-page 53
dsPIC30F1010/202X
REGISTER 5-2:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ALTIVT
DISI
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use alternate vector table
0 = Use standard (default) vector table
bit 14
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3
Unimplemented: Read as ‘0’
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
DS70000178D-page 54
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-3:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MI2CIF
SI2CIF
NVMIF
ADIF
U1TXIF
U1RXIF
SPI1IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IF
T2IF
OC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
MI2CIF: I2C Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
SI2CIF: I2C Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
NVMIF: Nonvolatile Memory Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
ADIF: ADC Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
Unimplemented: Read as ‘0’
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 55
dsPIC30F1010/202X
REGISTER 5-3:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000178D-page 56
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-4:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
AC3IF
AC2IF
AC1IF
—
CNIF
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PWM4IF
PWM3IF
PWM2IF
PWM1IF
PSEMIF
INT2IF
INT1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
AC3IF: Analog Comparator #3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14
AC2IF: Analog Comparator #2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13
AC1IF: Analog Comparator #1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
Unimplemented: Read as ‘0’
bit 11
CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10-7
Unimplemented: Read as ‘0’
bit 6
PWM4IF: Pulse Width Modulation Generator #4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
PWM3IF: Pulse Width Modulation Generator #3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
PWM2IF: Pulse Width Modulation Generator #2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
PWM1IF: Pulse Width Modulation Generator #1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
PSEMIF: PWM Special Event Match Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 57
dsPIC30F1010/202X
REGISTER 5-5:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-00
R/W-0
—
—
—
—
—
ADCP5IF
ADCP4IF
ADCP3IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
ADCP2IF
ADCP1IF
ADCP0IF
—
—
—
—
AC4IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
ADCP5IF: ADC Pair 5 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
ADCP4IF: ADC Pair 4 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
ADCP3IF: ADC Pair 3 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
ADCP2IF: ADC Pair 2 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
ADCP0IF: ADC Pair 0 Conversion Done Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-1
Unimplemented: Read as ‘0’
bit 0
AC4IF: Analog Comparator #4 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000178D-page 58
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-6:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MI2CIE
SI2CIE
NVMIE
ADIE
U1TXIE
U1RXIE
SPI1IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
T2IE
OC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14
MI2CIE: I2C Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13
SI2CIE: I2C Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12
NVMIE: Nonvolatile Memory Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 11
ADIE: ADC Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8
SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 59
dsPIC30F1010/202X
REGISTER 5-6:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DS70000178D-page 60
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-7:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
AC3IE
AC2IE
AC1IE
—
CNIE
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PWM4IE
PWM3IE
PWM2IE
PWM1IE
PSEMIE
INT2IE
INT1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
AC3IE: Analog Comparator #3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 14
AC2IE: Analog Comparator #2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13
AC1IE: Analog Comparator #1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12
Unimplemented: Read as ‘0’
bit 11
CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10-7
Unimplemented: Read as ‘0’
bit 6
PWM4IE: Pulse Width Modulation Generator #4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5
PWM3IE: Pulse Width Modulation Generator #3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4
PWM2IE: Pulse Width Modulation Generator #2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 3
PWM1IE: Pulse Width Modulation Generator #1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2
PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1
INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 61
dsPIC30F1010/202X
REGISTER 5-8:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
ADCP5IE
ADCP4IE
ADCP3IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
ADCP2IE
ADCP1IE
ADCP0IE
—
—
—
—
AC4IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
ADCP5IE: ADC Pair 5 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9
ADCP4IE: ADC Pair 4 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8
ADCP3IE: ADC Pair 3 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7
ADCP2IE: ADC Pair 2 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6
ADCP1IE: ADC Pair 1 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5
ADCP0IE: ADC Pair 0 Conversion done Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4-1
Unimplemented: Read as ‘0’
bit 0
AC4IE: Analog Comparator #4 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DS70000178D-page 62
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-9:
U-0
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
R/W-1
—
R/W-0
R/W-0
T1IP
U-0
R/W-1
—
R/W-0
R/W-0
OC1IP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
IC1IP
R/W-0
U-0
R/W-1
—
R/W-0
R/W-0
INT0IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T1IP: Timer1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP: External Interrupt 0 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 63
dsPIC30F1010/202X
REGISTER 5-10:
U-0
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
R/W-1
—
R/W-0
R/W-0
T3IP
U-0
R/W-1
—
R/W-0
R/W-0
T2IP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
OC2IP
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T3IP: Timer3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
T2IP: Timer2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC2IP: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70000178D-page 64
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-11:
U-0
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
R/W-1
—
R/W-0
R/W-0
ADIP
U-0
R/W-1
—
R/W-0
R/W-0
U1TXIP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
U1RXIP
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
SPI1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADIP: ADC Conversion Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U1TXIP: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1RXIP: UART1 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI1IP: SPI1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 65
dsPIC30F1010/202X
REGISTER 5-12:
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-1
R/W-0
R/W-0
MI2CIP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
SI2CIP
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
NVMIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
MI2CIP: I2C Master Events Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2CIP: I2C Slave Events Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
NVMIP: Nonvolatile Memory Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS70000178D-page 66
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-13:
U-0
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
R/W-1
—
R/W-0
R/W-0
PWM1IP
U-0
R/W-1
—
R/W-0
R/W-0
PSEMIP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
INT2IP
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
INT1IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
PWM1IP: PWM Generator #1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
PSEMIP: PWM Special Event Match Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP: External Interrupt 2 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP: External Interrupt 1 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 67
dsPIC30F1010/202X
REGISTER 5-14:
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-1
R/W-0
R/W-0
PWM4IP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
PWM3IP
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
PWM2IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
PWM4IP: PWM Generator #4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PWM3IP: PWM Generator #3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PWM2IP: PWM Generator #2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS70000178D-page 68
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-15:
U-0
IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
R/W-1
—
R/W-0
R/W-0
CNIP
U-0
U-0
U-0
U-0
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP: Change Notification Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 69
dsPIC30F1010/202X
REGISTER 5-16:
U-0
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
R/W-1
—
R/W-0
R/W-0
AC3IP
U-0
R/W-1
—
R/W-0
R/W-0
AC2IP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
AC1IP
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
AC3IP: Analog Comparator 3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
AC2IP: Analog Comparator 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AC1IP: Analog Comparator 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70000178D-page 70
x = Bit is unknown
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-17:
IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-1
R/W-0
R/W-0
AC4IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
AC4IP: Analog Comparator 4 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 71
dsPIC30F1010/202X
REGISTER 5-18:
U-0
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
R/W-1
—
R/W-0
R/W-0
ADCP2IP
U-0
R/W-1
—
R/W-0
R/W-0
ADCP1IP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
ADCP0IP
R/W-0
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
ADCP2IP: ADC Pair 2 Conversion Done Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
ADCP1IP: ADC Pair 1 Conversion Done Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCP0IP: ADC Pair 0 Conversion Done Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70000178D-page 72
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
REGISTER 5-19:
IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-1
R/W-0
R/W-0
ADCP5IP
bit 15
bit 8
U-0
R/W-1
—
R/W-0
ADCP4IP
R/W-0
U-0
R/W-1
—
R/W-0
R/W-0
ADCP3IP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10 - 8
ADCP5IP: ADC Pair 5 Conversion Done Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCP4IP: ADC Pair 4 Conversion Done Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ADCP3IP: ADC Pair 3 Conversion Done Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
2006-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000178D-page 73
dsPIC30F1010/202X
REGISTER 5-20:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R-0
R-0
R-0
R-0
ILR
bit 15
bit 8
U-0
R-0
R-0
R-0
—
R-0
R-0
R-0
R-0
VECNUM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
ILR: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM: Vector Number of Pending Interrupt bits
0111111 = Interrupt Vector pending is number 135
•
•
•
0000001 = Interrupt Vector pending is number 9
0000000 = Interrupt Vector pending is number 8
DS70000178D-page 74
x = Bit is unknown
2006-2014 Microchip Technology Inc.
2006-2014 Microchip Technology Inc.
TABLE 5-2:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1
0080
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
0000 0000 0000 0000
INTCON2
0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
—
—
INT2EP
INT1EP
INT0EP
0000 0000 0000 0000
IFS0
0084
—
MI2CIF
SI2CIF
NVMIF
ADIF
U1TXIF
U1RXIF
SPI1IF
T3IF
T2IF
OC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000 0000 0000 0000
IFS1
0086
AC3IF
AC2IF
AC1IF
—
CNIF
—
—
—
—
PWM4IF
PWM3IF
PWM2IF
PWM1IF
PSEMIF
INT2IF
INT1IF
0000 0000 0000 0000
IFS2
0088
—
—
—
—
—
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
ADCP1IF
ADCP0IF
—
—
—
—
AC4IF
0000 0000 0000 0000
IEC0
0094
—
MI2CIE
SI2CIE
NVMIE
ADIE
U1TXIE
U1RXIE
SPI1IE
T3IE
T2IE
OC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000 0000 0000 0000
IEC1
0096
AC3IE
AC2IE
AC1IE
—
CNIE
—
—
—
—
PWM4IE
PWM3IE
PWM2IE
PWM1IE
PSEMIE
INT2IE
INT1IE
0000 0000 0000 0000
IEC2
0098
—
—
—
—
—
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
ADCP1IE
ADCP0IE
—
—
—
—
AC4IE
0000 0000 0000 0000
IPC0
00A4
—
T1IP
—
OC1IP
—
IC1IP
—
IPC1
00A6
—
T31P
—
T2IP
—
OC2IP
—
IPC2
00A8
—
ADIP
—
U1TXIP
—
U1RXIP
—
SPI1IP
0100 0100 0100 0100
IPC3
00AA
—
—
MI2CIP
—
SI2CIP
—
NVMIP
0000 0100 0100 0100
IPC4
00AC
—
—
PSEMIP
—
INT2IP
—
INT1IP
0100 0100 0100 0100
IPC5
00AE
—
—
PWM4IP
—
PWM3IP
—
PWM2IP
IPC6
00B0
—
CNIP
—
IPC7
00B2
—
AC3IP
—
IPC8
00B4
—
IPC9
00B6
—
IPC10
00B8
—
—
—
—
00E0
—
—
—
—
Note:
—
—
PWM1IP
—
—
—
—
—
—
ADCP2IP
—
—
—
—
AC2IP
—
—
—
—
—
—
—
—
—
AC1IP
—
—
—
0000 0100 0100 0100
—
—
0100 0000 0000 0000
—
—
—
—
0100 0100 0100 0000
—
—
ADCP0IP
—
—
ADCP5IP
—
ADCP4IP
—
VECNUM
Refer to the “dsPIC30F/33F Family Reference Manual” (DS70157) for descriptions of register bit fields.
0100 0100 0100 0000
—
ADCP1IP
—
—
—
—
ILR
—
0000 0000 0000 0100
AC4IP
—
—
ADCP3IP
—
0100 0100 0100 0000
0000 0100 0100 0100
0000 0000 0000 0000
DS70000178D-page 75
dsPIC30F1010/202X
INTTREG
—
0100 0100 0100 0100
INT0IP
—
Reset State
dsPIC30F1010/202X
NOTES:
DS70000178D-page 76
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
6.0
I/O PORTS
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared between the peripherals and
the parallel I/O ports.
All I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
6.1
Parallel I/O (PIO) Ports
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with the operation of the port pin. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
FIGURE 6-1:
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch (LATx). Reads from
the port (PORTx), read the port pins, and writes to the
port pins, write the latch (LATx).
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs.
A Parallel I/O (PIO) port that shares a pin with a peripheral is, in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pad cell. Figure 6-1 shows how ports are shared
with other peripherals, and the associated I/O cell (pad)
to which they are connected. Table 6-1 and Table 6-2
show the register formats for the shared ports, PORTA
through PORTF, for the dsPIC30F1010/2020 and
PORTA through PORTG for the dsPIC30F2023 device,
respectively.
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O Cell
Peripheral Output Enable
Peripheral Output Data
1
0
1
PIO Module
Output Enable
Output Data
0
Read TRIS
I/O Pad
Data Bus
D
WR TRIS
CK
Q
TRIS Latch
D
WR LAT +
WR Port
Q
CK
Data Latch
Read LAT
Input Data
Read Port
2006-2014 Microchip Technology Inc.
DS70000178D-page 77
dsPIC30F1010/202X
6.2
Configuring Analog Port Pins
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
6.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 6-1:
PORT WRITE/READ
EXAMPLE
MOV 0xFF00, W0; Configure PORTB
; as inputs
MOV W0, TRISBB; and PORTB as outputs
NOP
; Delay 1 cycle
BTSS PORTB, #13; Next Instruction
DS70000178D-page 78
6.3
Input Change Notification
The input change notification function of the I/O ports
allows the dsPIC30F1010/202X devices to generate
interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature is
capable of detecting input change-of-states even in
Sleep mode, when the clocks are disabled. There are
8 external signals (CN0 through CN7) that can be
selected (enabled) for generating an interrupt request
on a change-of-state.
There are two control registers associated with the CN
module. The CNEN1 register contain the CN interrupt
enable (CNxIE) control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source that is connected
to the pin and eliminate the need for external resistors
when push button or keypad devices are connected.
The pull-ups are enabled separately using the CNPU1
register, which contain the weak pull-up enable (CNxPUE) bits for each of the CN pins. Setting any of the
control bits enables the weak pull-ups for the
corresponding pins.
Note: Pull-ups on change notification pins should
always be disabled whenever the port pin is
configured as a digital output.
2006-2014 Microchip Technology Inc.
2006-2014 Microchip Technology Inc.
TABLE 6-1:
dsPIC30F1010/2020 PORT REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit
12
Bit
11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
TRISA
02C0
—
—
—
—
—
—
TRISA9
—
—
—
—
—
—
—
—
—
0000 0010 0000 0000
PORTA
02C2
—
—
—
—
—
—
RA9
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
LATA
02C4
—
—
—
—
—
—
LAT9
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
TRISB
02C6
—
—
—
—
—
—
—
—
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
0000 0000 0011 1111
PORTB
02C8
—
—
—
—
—
—
—
—
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
0000 0000 0000 0000
LATB
02CA
—
—
—
—
—
—
—
—
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
0000 0000 0000 0000
TRISD
02D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD0
0000 0000 0000 0001
PORTD
02D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD0
0000 0000 0000 0000
LATD
02D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATD0
0000 0000 0000 0000
TRISE
02D8
—
—
—
—
—
—
—
—
TRSE7
TRSE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
0000 0000 1111 1111
PORTE
02DA
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
0000 0000 0000 0000
LATE
02DC
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
0000 0000 0000 0000
TRISF
02DE
—
—
—
—
—
—
—
TRISF8
TRISF7
TRISF6
—
—
—
—
—
—
0000 0001 1100 0000
PORTF
02E0
—
—
—
—
—
—
—
RF8
RF7
RF6
—
—
—
—
—
—
0000 0000 0000 0000
LATF
02E2
—
—
—
—
—
—
—
LATF8
LATF7
LATF6
—
—
—
—
—
—
0000 0000 0000 0000
SFR Name
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
DS70000178D-page 79
SFR
Name
dsPIC30F2023 PORT REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit
12
02C0
—
—
—
—
PORTA
02C2
—
—
—
—
RA11
RA10
LATA
02C4
—
—
—
—
LATA11
LATA10
TRISB11 TRISB10 TRISB9
TRISA
Bit 11
Bit 10
TRISA11 TRISA10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
TRIS9
TRISA8
—
—
—
—
—
—
—
—
0000 1111 0000 0000
RA9
RA8
—
—
—
—
—
—
—
—
0000 0000 0000 0000
LATA9
LATA8
—
—
—
—
—
—
—
—
0000 0000 0000 0000
TRISB
02C6
—
—
—
—
TRISB8
TRISB7
TRIS6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
0000 1111 1111 1111
PORTB
02C8
—
—
—
—
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
0000 0000 0000 0000
LATB
02CA
—
—
—
—
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
0000 0000 0000 0000
TRISD
02D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD1
TRISD0
0000 0000 0000 0011
PORTD
02D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD1
RD0
0000 0000 0000 0000
LATD
02D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LATD1
LATD0
0000 0000 0000 0000
TRISE
02D8
—
—
—
—
—
—
—
—
TRSE7
TRSE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
0000 0000 1111 1111
PORTE
02DA
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
0000 0000 0000 0000
LATE
02DC
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
0000 0000 0000 0000
TRISF
02DE
TRISF15
TRISF14
—
—
—
—
—
TRISF8
TRISF7
TRISF6
—
—
TRISF3
TRISF2
—
—
1100 0001 1100 1100
PORTF
02E0
RF15
RF14
—
—
—
—
—
RF8
RF7
RF6
—
—
RF3
RF2
—
—
0000 0000 0000 0000
LATF
02E2
LATF15
LATF14
—
—
—
—
—
LATF8
LATF7
LATF6
—
—
LATF3
LATF2
—
—
0000 0000 0000 0000
TRISG
02E4
—
—
—
—
—
—
—
—
—
—
—
—
TRISG3 TRISG2
—
—
0000 0000 0000 1100
PORTG
02E6
—
—
—
—
—
—
—
—
—
—
—
—
RG3
RG2
—
—
0000 0000 0000 0000
LATG
02E8
—
—
—
—
—
—
—
—
—
—
—
—
LATG3
LATG2
—
—
0000 0000 0000 0000
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
TABLE 6-3:
2006-2014 Microchip Technology Inc.
SFR
Name
dsPIC30F1010/202X INPUT CHANGE NOTIFICATION REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit
12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
CNEN1
0060
—
—
—
—
—
—
—
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000 0000 0000 0000
CNPU1
0064
—
—
—
—
—
—
—
—
CN2PUE
CN1PUE
CN0PUE
0000 0000 0000 0000
CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE
Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F1010/202X
DS70000178D-page 80
TABLE 6-2:
dsPIC30F1010/202X
7.0
FLASH PROGRAM MEMORY
7.2
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.
With RTSP, the user may erase program memory 32
instructions (96 bytes) at a time and can write program
memory data 32 instructions (96 bytes) at a time.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
1.
2.
7.1
7.3
Table Instruction Operation Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
In-Circuit Serial Programming™ (ICSP™)
programming capability
Run-Time Self-Programming (RTSP)
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
In-Circuit Serial Programming
(ICSP)
A 24-bit program memory address is formed using bits
of the TBLPAG register and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 7-1.
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 7-1:
Run-Time Self-Programming
(RTSP)
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
2006-2014 Microchip Technology Inc.
1/0
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
DS70000178D-page 81
dsPIC30F1010/202X
7.4
RTSP Operation
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program 32
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction ‘0’, instruction
‘1’, etc. The instruction words loaded must always be
from a group of 32 boundary.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire VDD
range.
7.5
The four SFRs used to read and write the program
Flash memory are:
•
•
•
•
NVMCON
NVMADR
NVMADRU
NVMKEY
7.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
7.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA of the last table instruction that
has been executed and selects the row to write.
7.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register captures the EA of the last table instruction that
has been executed.
7.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 7.6
“Programming Operations” for further details.
Note:
DS70000178D-page 82
Control Registers
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
7.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
7.6.1
4.
5.
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase and program one row of program
Flash memory at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a) Setup NVMCON register for multi-word,
program Flash, erase and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write ‘55’ to NVMKEY.
d) Write ‘AA’ to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 7-1:
6.
Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a) Setup NVMCON register for multi-word,
program Flash, program and set WREN bit.
b) Write ‘55’ to NVMKEY.
c) Write ‘AA’ to NVMKEY.
d) Set the WR bit. This will begin program
cycle.
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
7.6.2
ERASING A ROW OF PROGRAM
MEMORY
Example 7-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word
; program memory selected, and writes enabled
MOV
#0x4041,W0
;
;
MOV
W0,NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR),W0
;
;
MOV
W0,NVMADRU
MOV
#tbloffset(PROG_ADDR),W0
;
MOV
W0, NVMADR
;
DISI
#5
;
;
MOV
#0x55,W0
;
MOV
W0,NVMKEY
MOV
#0xAA,W1
;
;
MOV
W1,NVMKEY
BSET
NVMCON,#WR
;
NOP
;
NOP
;
2006-2014 Microchip Technology Inc.
write
Init NVMCON SFR
Initialize PM Page Boundary SFR
Initialize in-page EA pointer
Initialize NVMADR SFR
Block all interrupts with priority
1
1
None
(2 or 3)
23
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, skip if <
1
1
None
(2 or 3)
24
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, skip if
1
1
None
(2 or 3)
25
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
26
DEC
DEC
f
f = f –1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f –1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f = f –2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
27
DEC2
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C,DC,N,OV,Z
28
DISI
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
29
DIV
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C, OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C, OV
Signed 16/16-bit Fractional Divide
1
18
N,Z,C, OV
30
DIVF
DIVF
31
DO
DO
#lit14,Expr
Do code to PC + Expr, lit14 + 1 times
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
2
2
None
Wm,Wn
32
ED
ED
Wm * Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
33
EDAC
EDAC
Wm * Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
2006-2014 Microchip Technology Inc.
DS70000178D-page 223
dsPIC30F1010/202X
TABLE 19-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
34
EXCH
EXCH
Wns,Wnd
35
FBCL
FBCL
Ws,Wnd
36
FF1L
FF1L
37
FF1R
38
GOTO
39
INC
40
41
INC2
IOR
# of
word
s
# of
cycles
Swap Wns with Wnd
1
1
Find Bit Change from Left (MSb) Side
1
1
C
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
GOTO
Expr
Go to address
2
2
None
GOTO
Wn
Go to indirect
1
2
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
Assembly Syntax
Description
Status Flags
Affected
None
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
42
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
43
LNK
LNK
#lit14
Link frame pointer
1
1
None
44
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
MAC
Wm *
Wn,Acc,Wx,Wxd,Wy,Wyd,
AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm *
Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
N,Z
MOV
f,WREG
Move f to WREG
1
1
N,Z
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
N,Z
None
45
46
MAC
MOV
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
Prefetch and store accumulator
1
1
None
47
MOVSAC
MOVSAC
48
MPY
MPY
Wm *
Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm *
Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
Acc,Wx,Wxd,Wy,Wyd,AWB
49
MPY.N
MPY.N
Wm *
Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
50
MSC
MSC
Wm *
Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
51
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
DS70000178D-page 224
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 19-2:
Base
Instr
#
Assembly
Mnemonic
52
NEG
53
54
NOP
POP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
NEG
Negate Accumulator
Acc
PUSH
# of
word
s
# of
cycles
1
1
Status Flags
Affected
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
1
2
None
Push Shadow Registers
1
1
None
Go into Sleep or Idle mode
1
1
WDTO,Sleep
Expr
Relative Call
1
2
None
None
POP.S
55
Description
PUSH.S
56
PWRSAV
PWRSAV
57
RCALL
RCALL
RCALL
Wn
Computed Call
1
2
58
REPEAT
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
None
#lit1
59
RESET
RESET
Software device Reset
1
1
60
RETFIE
RETFIE
Return from interrupt
1
3 (2)
None
61
RETLW
RETLW
Return with literal in Wn
1
3 (2)
None
62
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
63
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
64
65
66
RLNC
RRC
RRNC
#lit10,Wn
67
SAC
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
68
SE
SE
Ws,Wnd
Wnd = sign extended Ws
1
1
C,N,Z
69
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
70
71
SFTAC
SL
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
2006-2014 Microchip Technology Inc.
DS70000178D-page 225
dsPIC30F1010/202X
TABLE 19-2:
Base
Instr
#
Assembly
Mnemonic
72
SUB
73
74
75
76
SUBB
SUBR
SUBBR
SWAP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
Description
# of
word
s
# of
cycles
1
1
Status Flags
Affected
SUB
Acc
Subtract Accumulators
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
SUBB
f
f = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C,DC,N,OV,Z
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
1
1
None
SWAP
Wn
Wn = byte swap Wn
1
1
None
None
77
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
78
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
79
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
80
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
81
ULNK
ULNK
Unlink frame pointer
1
1
None
82
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C,Z,N
83
ZE
DS70000178D-page 226
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
20.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
20.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2006-2014 Microchip Technology Inc.
DS70000178D-page 227
dsPIC30F1010/202X
20.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
20.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
20.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
20.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS70000178D-page 228
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
20.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
20.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2006-2014 Microchip Technology Inc.
20.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
20.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
20.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS70000178D-page 229
dsPIC30F1010/202X
20.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
20.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70000178D-page 230
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
21.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to “dsPIC30F Family Reference Manual”
(DS70046).
Absolute maximum ratings for the device family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)(1) ................................................ -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS(1) ......................................................................................... -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................300 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ...................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
2: Maximum allowable current is a function of device maximum power dissipation. See Table 21-2.
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
21.1
DC Characteristics
TABLE 21-1:
OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
Temp Range
dsPIC30FXXX-30I
dsPIC30FXXX-20E
4.5-5.5V
-40°C to +85°C
30
—
4.5-5.5V
-40°C to +125°C
—
20
3.0-3.6V
-40°C to +85°C
20
—
3.0-3.6V
-40°C to +125°C
—
15
2006-2014 Microchip Technology Inc.
DS70000178D-page 231
dsPIC30F1010/202X
TABLE 21-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+150
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
dsPIC30F1010/202X-30I
dsPIC30F1010/202X-20E
Power Dissipation:
Internal Chip Power Dissipation:
P INT = V D D I D D – I O H
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
P I/O = V D D – V O H I OH + V O L I O L
Maximum Allowed Power Dissipation
TABLE 21-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
JA
JA
JA
JA
JA
Package Thermal Resistance, 28-pin SOIC (SO)
Package Thermal Resistance, 28-pin QFN
Package Thermal Resistance, 28-pin SPDIP (SP)
Package Thermal Resistance, 44-pin QFN
Package Thermal Resistance, 44-pin TQFP
Note 1:
2:
Max
Unit
Notes
48.3
—
°C/W
1, 2
33.7
—
°C/W
1, 2
42
—
°C/W
1, 2
28
—
°C/W
1, 2
39.3
—
°C/W
1, 2
Junction to ambient thermal resistance, Theta-ja (JA) numbers are achieved by package simulations.
Depending on operating conditions, air flow may be required for improved thermal performance.
TABLE 21-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Typ
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
Operating Voltage(2)
DC10
VDD
Supply Voltage
3.0
—
5.5
V
Industrial temperature
DC11
VDD
Supply Voltage
3.0
—
5.5
V
Extended temperature
DC12
VDR
RAM Data Retention Voltage(3)
—
1.5
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset signal
—
VSS
—
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset signal
0.05
—
—
Note 1:
2:
3:
V/ms 0-5V in 0.1 sec,
0-3.3V in 60 ms
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
These parameters are characterized but not tested in manufacturing.
This is the limit to which VDD can be lowered without losing RAM data.
DS70000178D-page 232
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC20a
DC20b
13
14
16
16
mA
mA
+25°C
+85°C
DC20c
DC20d
14
22
17
26
mA
mA
+125°C
+25°C
DC20e
DC20f
22
22
26
27
mA
mA
+85°C
+125°C
DC22a
DC22b
19
19
22
23
mA
mA
+25°C
+85°C
DC22c
DC22d
19
30
23
36
mA
mA
+125°C
+25°C
DC22e
DC22f
30
31
37
37
mA
mA
+85°C
+125°C
DC23a
DC23b
27
28
33
33
mA
mA
+25°C
+85°C
DC23c
DC23d
28
44
34
53
mA
mA
+125°C
+25°C
DC23e
DC23f
45
45
53
54
mA
mA
+85°C
+125°C
DC24a
DC24b
66
67
79
80
mA
mA
+25°C
+85°C
DC24c
DC24d
68
108
81
129
mA
mA
+125°C
+25°C
DC24e
DC24f
109
110
130
131
mA
mA
+85°C
+125°C
DC26a
DC26b
98
99
118
118
mA
mA
+25°C
+85°C
DC26d
DC26e
159
160
191
192
mA
mA
+25°C
+85°C
DC26f
DC27d
161
222
193
267
mA
mA
+125°C
+25°C
DC27e
Note 1:
2:
3.3V
FRC 3.2 MIPS, PLL disabled
5V
3.3V
FRC, 4.9 MIPS, PLL disabled
5V
3.3V
FRC, 7.3 MIPS, PLL disabled
5V
3.3V
FRC 13 MIPS, PLL enabled
5V
3.3V
FRC 20 MIPS, PLL enabled
5V
5V
FRC, 30 MIPS, PLL enabled
223
267
mA
+85°C
Data in “Typical” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows:
- All I/O pins are configured as Outputs and pulled to VSS.
- MCLR = VDD, WDT and FSCM are disabled.
- CPU, SRAM, Program Memory and Data Memory are operational.
- No peripheral modules are operating.
2006-2014 Microchip Technology Inc.
DS70000178D-page 233
dsPIC30F1010/202X
TABLE 21-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC28a
DC28b
96
97
116
116
mA
mA
+25°C
+85°C
DC28d
DC28e
157
158
188
189
mA
mA
+25°C
+85°C
DE28f
DC29d
159
227
191
273
mA
mA
+125°C
+25°C
DC29e
Note 1:
2:
3.3V
EC, 20 MIPS, PLL enabled
5V
5V
EC, 30 MIPS, PLL enabled
228
273
mA
+85°C
Data in “Typical” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows:
- All I/O pins are configured as Outputs and pulled to VSS.
- MCLR = VDD, WDT and FSCM are disabled.
- CPU, SRAM, Program Memory and Data Memory are operational.
- No peripheral modules are operating.
DS70000178D-page 234
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off Clock On Base Current(2)
DC40a
8
9
mA
DC40b
DC40c
+25°C
8
9
mA
+85°C
8
10
mA
+125°C
DC40d
12
15
mA
+25°C
DC40e
13
15
mA
+85°C
DC40f
13
16
mA
+125°C
DC42a
10
12
mA
+25°C
DC42b
11
13
mA
+85°C
DC42c
11
13
mA
+125°C
DC42d
17
20
mA
+25°C
DC42e
17
21
mA
+85°C
DC42f
18
21
mA
+125°C
DC43a
15
18
mA
+25°C
DC43b
15
18
mA
+85°C
DC43c
15
18
mA
+125°C
DC43d
24
29
mA
+25°C
DC43e
24
29
mA
+85°C
DC43f
25
30
mA
+125°C
DC44a
44
53
mA
+25°C
DC44b
45
54
mA
+85°C
DC44c
46
55
mA
+125°C
DC44d
72
87
mA
+25°C
DC44e
73
88
mA
+85°C
DC44f
74
89
mA
+125°C
DC46a
66
79
mA
+25°C
DC46b
67
80
mA
+85°C
DC46d
108
129
mA
+25°C
DC46e
109
131
mA
+85°C
DC45f
110
132
mA
+125°C
DC47d
152
182
mA
+25°C
DC47e
153
183
mA
+85°C
Note 1:
2:
3.3V
FRC, 3.2 MIPS, PLL disabled
5V
3.3V
FRC, 4.9 MIPS, PLL disabled
5V
3.3V
FRC, 7.3 MIPS, PLL disabled
5V
3.3V
FRC, 13 MIPS, PLL enabled
5V
3.3V
FRC 20 MIPS, PLL enabled
5V
5V
FRC, 30 MIPS, PLL enabled
Data in “Typical” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IIDLE current is measured with core off, clock on and all modules turned off. All I/Os are configured
as inputs and pulled high. WDT, etc. are all switched off.
2006-2014 Microchip Technology Inc.
DS70000178D-page 235
dsPIC30F1010/202X
TABLE 21-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off Clock On Base Current(2)
DC48a
65
78
mA
+25°C
DC48b
66
79
mA
+85°C
DC48d
105
127
mA
+25°C
DC48e
107
128
mA
+85°C
DC48f
108
130
mA
+125°C
DC49d
155
186
mA
+25°C
DC49e
156
187
mA
+85°C
Note 1:
2:
3.3V
EC, 20 MIPS, PLL enabled
5V
5V
EC, 30 MIPS, PLL enabled
Data in “Typical” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IIDLE current is measured with core off, clock on and all modules turned off. All I/Os are configured
as inputs and pulled high. WDT, etc. are all switched off.
DS70000178D-page 236
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
2.4
mA
Conditions
Power-Down Current (IPD)
DC60a
1.2
+25°C
DC60b
1.2
2.4
mA
+85°C
DC60c
1.3
2.6
mA
+125°C
DC60e
2.1
4.2
mA
+25°C
DC60f
2.1
4.2
mA
+85°C
DC60g
2.3
4.6
mA
+125°C
DC61a
15
30
A
+25°C
DC61b
14
30
A
+85°C
DC61c
14
30
A
+125°C
DC61e
30
60
A
+25°C
DC61f
29
60
A
+85°C
30
60
A
+125°C
DC61g
Note 1:
2:
3:
3.3V
Base Power-Down Current(2)
5V
3.3V
Watchdog Timer Current: IWDT(3)
5V
Data in the Typical column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shutdown. All I/Os are configured as inputs and
pulled high. WDT, etc., are all switched off.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
2006-2014 Microchip Technology Inc.
DS70000178D-page 237
dsPIC30F1010/202X
TABLE 21-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(2)
DI10
I/O Pins:
with Schmitt Trigger Buffer
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSC1 (in HS mode)
VSS
—
0.2 VDD
V
DI18
SDA, SCL
VSS
—
0.3 VDD
V
SMbus disabled
SDA, SCL
VSS
—
0.2 VDD
V
SMbus enabled
I/O Pins:
with Schmitt Trigger Buffer
0.8 VDD
—
VDD
V
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSC1 (in HS mode)
0.7 VDD
—
VDD
V
DI28
SDA, SCL
0.7 VDD
—
VDD
V
SMbus disabled
SDA, SCL
0.8 VDD
—
VDD
V
SMbus enabled
DI19
VIH
DI20
DI29
IIL
Input High Voltage(2)
Input Leakage Current(2,3,4)
DI50
I/O Ports
—
0.01
±1
A
VSS VPIN VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
0.50
—
A
VSS VPIN VDD,
Pin at high-impedance
DI55
MCLR
—
0.05
±5
A
VSS VPIN VDD
DI56
OSC1
—
0.05
±5
A
VSS VPIN VDD,
HS Oscillator mode
Note 1:
2:
3:
4:
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
These parameters are characterized but not tested in manufacturing.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
DS70000178D-page 238
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VOL
Characteristic
Min
Typ(1)
Max
Units
—
0.6
V
Conditions
Output Low Voltage(2)
DO10
I/O Ports
—
—
—
TBD
V
IOL = 2.0 mA, VDD = 3.3V
DO16
OSC2/CLKO
—
—
0.6
V
IOL = 1.6 mA, VDD = 5V
(RC or EC Oscillator mode)
—
—
TBD
V
IOL = 2.0 mA, VDD = 3.3V
VOH
DO20
Output High Voltage(2)
I/O Ports
DO26
IOL = 8.5 mA, VDD = 5V
OSC2/CLKO
(RC or EC Oscillator mode)
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 5V
TBD
—
—
V
IOH = -2.0 mA, VDD = 3.3V
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 5V
TBD
—
—
V
IOH = -2.0 mA, VDD = 3.3V
Capacitive Loading Specs
on Output Pins(2)
DO50
COSC2
OSC2 Pin
—
—
15
pF
In HS mode when external
clock is used to drive OSC1
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
RC or EC Oscillator mode
DO58
CB
SCL, SDA
—
—
400
pF
In I2C mode
Legend: TBD = To Be Determined
Note 1: Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: These parameters are characterized but not tested in manufacturing.
TABLE 21-10: DC CHARACTERISTICS: PROGRAM AND EEPROM
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory(2)
D130
EP
Cell Endurance
10K
100K
—
E/W
D131
VPR
VDD for Read
VMIN
—
5.5
V
D132
VEB
VDD for Bulk Erase
4.5
—
5.5
V
D133
VPEW
VDD for Erase/Write
3.0
—
5.5
V
D134
TPEW
Erase/Write Cycle Time
—
2
—
ms
D135
TRETD
Characteristic Retention
40
100
—
Year
D136
TEB
ICSP Block Erase Time
—
4
—
ms
D137
IPEW
IDD During Programming
—
10
30
mA
Row erase
D138
IEB
IDD During Programming
—
10
30
mA
Bulk erase
Note 1:
2:
VMIN = Minimum operating voltage
Provided no other specifications
are violated
Data in “Typ” column is at 5V, +25°C unless otherwise stated.
These parameters are characterized but not tested in manufacturing.
2006-2014 Microchip Technology Inc.
DS70000178D-page 239
dsPIC30F1010/202X
21.2
AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 21-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in DC Spec Section 21.0.
AC CHARACTERISTICS
FIGURE 21-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
5 pF for OSC2 output
VSS
FIGURE 21-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS31
OS31
OS25
CLKO
OS40
DS70000178D-page 240
OS41
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-12: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
OS10
FIN
OS20
TOSC
Characteristic
Min
Typ(1)
Max
Units
External CLKI Frequency(2)
(External clocks allowed only
in EC mode)
6
6
—
—
15.00
15.00
MHz
MHz
EC
EC with 32x PLL
Oscillator Frequency(2)
6
6
—
—
15.00
15.00
MHz
MHz
HS
FRC internal
16.5
—
DC
ns
33
—
DC
ns
TOSC = 1/FOSC(3)
(2,4)
Conditions
OS25
TCY
Instruction Cycle Time
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time(2)
.45 x TOSC
—
—
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time(2)
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(2,5)
—
6
10
ns
—
6
10
ns
OS41
TckF
Note 1:
2:
3:
4:
5:
(2,5)
CLKO Fall Time
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
The oscillator frequency (FOSC) is equal to FIN when the PLL is disabled. FOSC is equal to 4 x FIN when the
PLL is enabled.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSC1/CLK1 pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
2006-2014 Microchip Technology Inc.
DS70000178D-page 241
dsPIC30F1010/202X
TABLE 21-13: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0 AND 5.0V )
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
Conditions
6
—
15
MHz
EC, HS modes with
PLL x32
192
—
480
MHz
EC, HS modes with
PLL x32
OS50
FPLLI
PLL Input Frequency Range(2)
OS51
FSYS
On-Chip PLL Output(2)
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
20
50
s
OS53
DCLK
CLKO Stability (Jitter)
—
—
1
%
Note 1:
2:
Measured over 100 ms
period
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 21-14: INTERNAL CLOCK TIMING EXAMPLES
Clock
Oscillator
Mode
FIN (MHz)(1)
TCY (sec)(2)
MIPS(3)
w/o PLL
MIPS(4)
w/PLL x32
EC
10
0.2
5.0
20
15
0.133
7.5
30
HS
10
0.2
5.0
20
15
0.133
7.5
30
Note 1:
2:
3:
4:
Assumption: Oscillator Postscaler is divide-by-1.
Instruction Execution Cycle Time: TCY = 1/MIPS.
Instruction Execution Frequency without PLL: MIPS = FIN/2 (since there are 2 Q clocks per instruction
cycle).
Instruction Execution Frequency with PLL: MIPS = (FIN * 2).
DS70000178D-page 242
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.3V and 5.0V (± 10%)
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Freq = 6.4 MHz(1)
FRC
-0.06
—
+0.06
%
-0.06
—
+0.06
-1
—
+1
-1
—
+1
%
-1
—
+1
%
-40°C TA +125°C
VDD = 4.5-5.5V
+25°C
VDD = 3.0-3.6V
Internal FRC Accuracy @ FRC Freq = 9.7 MHz
FRC
-0.06
+25°C
VDD = 3.0-3.6V
%
+25°C
VDD = 4.5-5.5V
%
-40°C TA +85°C
VDD = 3.0-3.6V
-40°C TA +85°C
VDD = 4.5-5.5V
(1)
—
+0.06
%
-0.06
—
+0.06
%
+25°C
VDD = 4.5-5.5V
-1
—
+1
%
-40°C TA +85°C
VDD = 3.0-3.6V
-1
—
+1
%
-1
—
+1
%
-40°C TA +125°C
VDD = 4.5-5.5V
-40°C TA +85°C
VDD = 4.5-5.5V
Internal FRC Accuracy @ FRC Freq = 14.55 MHz(1)
FRC
Note 1:
-0.06
—
+0.06
%
+25°C
VDD = 3.0-3.6V
-0.06
—
+0.06
%
+25°C
VDD = 4.5-5.5V
-1
—
+1
%
-1
—
+1
%
-1
—
+1
%
-40°C TA +85°C
-40°C TA +85°C
-40°C TA +125°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
Frequency calibrated at +25°C and 5V. TUN bits can be used to compensate for temperature drift.
2006-2014 Microchip Technology Inc.
DS70000178D-page 243
dsPIC30F1010/202X
TABLE 21-16: AC CHARACTERISTICS: INTERNAL RC JITTER
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
+1
%
Conditions
Internal FRC Jitter @ FRC Freq = 6.4 MHz(1)
FRC
-1
—
VDD = 3.0-3.6V
-1
—
+1
%
+25°C
VDD = 4.5-5.5V
-1
—
+1
%
-40°C TA +85°C
VDD = 3.0-3.6V
-1
—
+1
%
-1
—
+1
%
-40°C TA +125°C
VDD = 4.5-5.5V
+1
%
+25°C
VDD = 3.0-3.6V
Internal FRC Jitter @ FRC Freq = 9.7 MHz
FRC
+25°C
-1
—
-40°C TA +85°C
VDD = 4.5-5.5V
(1)
-1
—
+1
%
+25°C
VDD = 4.5-5.5V
-1
—
+1
%
-40°C TA +85°C
VDD = 3.0-3.6V
-1
—
+1
%
-1
—
+1
%
-40°C TA +125°C
VDD = 4.5-5.5V
-40°C TA +85°C
VDD = 4.5-5.5V
Internal FRC Jitter @ FRC Freq = 14.55 MHz(1)
FRC
Note 1:
-1
—
+1
%
+25°C
VDD = 3.0-3.6V
-1
—
+1
%
+25°C
VDD = 4.5-5.5V
-1
—
+1
%
-1
—
+1
%
-1
—
+1
%
-40°C TA +85°C
-40°C TA +85°C
-40°C TA +125°C
VDD = 3.0-3.6V
VDD = 4.5-5.5V
VDD = 4.5-5.5V
Frequency calibrated at +25°C and 5V. TUN bits can be used to compensate for temperature drift.
DS70000178D-page 244
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-17: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1,2)
Min
Typ(3)
Max
Units
—
10
25
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Pin High or Low Time (output)
20
—
—
ns
TRBP
CNx High or Low Time (input)
2 TCY
—
—
ns
DI40
Note 1:
2:
3:
Port Output Rise Time
Conditions
These parameters are asynchronous events not related to any internal clock edges.
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated.
2006-2014 Microchip Technology Inc.
DS70000178D-page 245
dsPIC30F1010/202X
FIGURE 21-4:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
Oscillator
Time-out
SY30
Internal
Reset
Watchdog
Timer Reset
SY13
SY20
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 21-1 for load conditions.
DS70000178D-page 246
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-18: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
2
—
—
s
-40°C to +125°C
0.75
1.5
3
6
12
24
48
96
1
2
4
8
16
32
64
128
1.25
2.5
5
10
20
40
80
160
ms
-40°C to +125°C,
user programmable
-40°C to +125°C
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (low)
SY11
TPWRT
Power-up Timer Period
SY12
TPOR
Power-on Reset Delay
3
10
30
s
SY13
TIOZ
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
—
0.8
1.0
s
SY20
TWDT1
Watchdog Timer Time-out Period
(No Prescaler)
1.4
2.1
2.8
ms
VDD = 5V,
-40°C to +125°C
1.4
2.1
2.8
ms
VDD = 3.3V,
-40°C to +125°C
TWDT2
SY30
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
SY35
TFSCM
Fail-Safe Clock Monitor Delay
—
500
—
s
-40°C to +125°C
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated.
2006-2014 Microchip Technology Inc.
DS70000178D-page 247
dsPIC30F1010/202X
FIGURE 21-5:
BAND GAP START-UP TIME CHARACTERISTICS
VBGAP
0V
Enable Band Gap
(see Note)
Band Gap
Stable
SY40
TABLE 21-19: BAND GAP START-UP TIME REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SY40
Note 1:
2:
Characteristic(1)
Min
Typ(2)
Max
Units
Band Gap Start-up Time
—
40
65
µs
Symbol
TBGAP
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Conditions
Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON status bit.
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated.
DS70000178D-page 248
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-6:
TIMERx EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: “x” refers to Timer Type A or Timer Type B.
Refer to Figure 21-1 for load conditions.
TABLE 21-20: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristic
T1CK High Time
T1CK Low Time
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Must also meet
Parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
ns
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
ns
TCY + 10
—
—
ns
Greater of:
20 ns or
(TCY + 40)/N
—
—
—
T1CK Input Period Synchronous,
no prescaler
Synchronous,
with prescaler
Asynchronous
OS60
Ft1
SOSC1/T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON))
TA20
TCKEXTMRL Delay from External T1CK Clock
Edge to Timer Increment
2006-2014 Microchip Technology Inc.
20
—
—
ns
DC
—
50
kHz
0.5 TCY
—
1.5 TCY
—
Must also meet
Parameter TA15
N = Prescale
value
(1, 8, 64, 256)
DS70000178D-page 249
dsPIC30F1010/202X
TABLE 21-21: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TB10
TB11
TB15
Symbol
TTXH
TTXL
TTXP
Characteristic
T2CK High Time
T2CK Low Time
Min
Typ
Max
Units
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
TCY + 10
—
—
ns
Greater of:
20 ns or
(TCY + 40)/N
—
—
—
0.5 TCY
—
1.5 TCY
—
T2CK Input Period Synchronous,
no prescaler
Synchronous,
with prescaler
TB20
TCKEXTMRL Delay from External T2CK Clock
Edge to Timer Increment
Conditions
Must also meet
Parameter TB15
Must also meet
Parameter TB15
N = Prescale
value (1, 8, 64, 256)
TABLE 21-22: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
TC10
TTXH
T3CK High Time
Synchronous
0.5 TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TTXL
T3CK Low Time
Synchronous
0.5 TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TTXP
T3CK Input Period Synchronous,
no prescaler
TCY + 10
—
—
ns
Greater of:
20 ns or
(TCY + 40)/N
—
—
—
N = Prescale
value (1, 8, 64,
256)
0.5 TCY
—
1.5 TCY
—
Synchronous,
with prescaler
TC20
TCKEXTMRL Delay from External T3CK Clock
Edge to Timer Increment
DS70000178D-page 250
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-7:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICX
IC10
IC11
IC15
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-23: INPUT CAPTURE x TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
IC10
TccL
ICx Input Low Time
IC11
TccH
ICx Input High Time
IC15
TccP
ICx Input Period
Characteristic(1)
No Prescaler
Min
Max
Units
0.5 TCY + 20
—
ns
With Prescaler
No Prescaler
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(2 TCY + 40)/N
—
ns
With Prescaler
Note 1:
Conditions
N = Prescale
value (1, 4, 16)
These parameters are characterized but not tested in manufacturing.
FIGURE 21-8:
OUTPUT COMPARE x (OCx) MODULE TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-24: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ(2)
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See Parameter D032
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See Parameter D031
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2006-2014 Microchip Technology Inc.
DS70000178D-page 251
dsPIC30F1010/202X
FIGURE 21-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
TABLE 21-25: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
OC15
OC20
TFD
TFLT
Characteristic(1)
Min
Typ(2)
Fault Input to PWM I/O
Change
—
—
Fault Input Pulse Width
—
—
Max
Units
Conditions
25
ns
VDD = 3.3V
TBD
ns
VDD = 5V
50
ns
VDD = 3.3V
TBD
ns
VDD = 5V
-40°C to +85°C
-40°C to +85°C
Legend: TBD = To Be Determined
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS70000178D-page 252
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dsPIC30F1010/202X
FIGURE 21-10:
POWER SUPPLY PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA/B
MP20
PWMx
FIGURE 21-11:
POWER SUPPLY PWM MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-26: POWER SUPPLY PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
MP10
TFPWM
PWM Output Fall Time
—
10
25
ns
VDD = 5V
MP11
TRPWM
PWM Output Rise Time
—
10
25
ns
VDD = 5V
MP12
TFPWM
PWM Output Fall Time
—
TBD
TBD
ns
VDD = 3.3V
MP13
TRPWM
PWM Output Rise Time
—
TBD
TBD
ns
VDD = 3.3V
TFD
Fault Input to PWM
I/O Change
—
—
TBD
ns
VDD = 3.3V
25
ns
VDD = 5V
TFH
Minimum Pulse Width
—
—
TBD
ns
VDD = 3.3V
50
ns
VDD = 5V
MP20
MP30
Legend: TBD = To Be Determined
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2006-2014 Microchip Technology Inc.
DS70000178D-page 253
dsPIC30F1010/202X
FIGURE 21-12:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SDOx
Bit 14 - - - - - -1
MSb
SP31
SDIx
LSb
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-27: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Para
m
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
—
—
ns
Conditions
SP10 TscL
SCKx Output Low Time(3)
TCY/2
SP11 TscH
SCKx Output High
Time(3)
TCY/2
—
—
ns
SP20 TscF
SCKx Output Fall Time(4)
—
—
—
ns
See Parameter D032
(4)
SP21 TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter D031
SP30 TdoF
SDOx Data Output Fall Time(4)
—
—
—
ns
See Parameter D032
See Parameter D031
(4)
SP31 TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35 TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
—
30
ns
SP40 TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
SP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70000178D-page 254
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dsPIC30F1010/202X
FIGURE 21-13:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP11
SP21
SP10
SP20
SCKx
(CKP = 1)
SP35
SP21
SP20
SDOx
SP30, SP31
SP40
SDIx
LSb
Bit 14 - - - - - -1
MSb
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-28: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
TscL
SCKx Output Low Time(3)
TCY/2
—
—
ns
SP11
TscH
SCKx Output High
Time(3)
TCY/2
—
—
ns
SP20
TscF
SCKx Output Fall Time(4)
—
—
—
ns
See Parameter D032
—
—
—
ns
See Parameter D031
—
—
—
ns
See Parameter D032
See Parameter D031
SP10
(4)
SP21
TscR
SCKx Output Rise Time
SP30
TdoF
SDOx Data Output Fall Time(4)
(4)
SP31
TdoR
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
30
ns
SP36
TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
20
—
—
ns
Note 1:
2:
3:
4:
SDOx Data Output Rise Time
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2006-2014 Microchip Technology Inc.
DS70000178D-page 255
dsPIC30F1010/202X
FIGURE 21-14:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
LSb
BIT14 - - - - - -1
SP51
SP30,SP31
SDIx
SDI
MSb IN
BIT14 - - - -1
LSb IN
SP41
Note: Refer to Figure 21-1 for load conditions.
SP40
TABLE 21-29: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
SP70
TscL
SCKx Input Low Time
30
—
—
ns
SP71
TscH
SCKx Input High Time
30
—
—
ns
SP72
TscF
SCKx Input Fall Time(3)
—
10
25
ns
SP73
TscR
SCKx Input Rise Time(3)
—
10
25
ns
(3)
Conditions
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter D032
SP31
TdoR
SDOx Data Output Rise Time(3)
—
—
—
ns
See Parameter D031
SP35
TscH2doV SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
ns
SP41
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
20
—
—
ns
SP50
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
120
—
—
ns
SP51
TssH2doZ SSx to SDOx Output High-Impedance(3)
10
—
50
ns
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
Note 1:
2:
3:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
Assumes 50 pF load on all SPIx pins.
DS70000178D-page 256
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-15:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 21-1 for load conditions.
2006-2014 Microchip Technology Inc.
DS70000178D-page 257
dsPIC30F1010/202X
TABLE 21-30: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
Conditions
SP70
TscL
SCKx Input Low Time
30
—
—
ns
SP71
TscH
SCKx Input High Time
30
—
—
ns
—
10
25
ns
—
10
25
ns
—
—
—
ns
See Parameter D032
—
—
—
ns
See Parameter D031
Time(3)
SP72
TscF
SCKx Input Fall
SP73
TscR
SCKx Input Rise Time(3)
(3)
SP30
TdoF
SDOx Data Output Fall Time
SP31
TdoR
SDOx Data Output Rise Time(3)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
20
—
—
ns
SP50
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance(4)
10
—
50
ns
SP52
TscH2ssH
TscL2ssH
SSx after SCKx Edge
1.5 TCY + 40
—
—
ns
SP60
TssL2doV
SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, +25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70000178D-page 258
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dsPIC30F1010/202X
FIGURE 21-16:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL
IM31
IM34
IM30
IM33
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 21-1 for load conditions.
FIGURE 21-17:
I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM25
IM33
SDA
In
IM40
IM40
IM45
SDA
Out
Note: Refer to Figure 21-1 for load conditions.
2006-2014 Microchip Technology Inc.
DS70000178D-page 259
dsPIC30F1010/202X
TABLE 21-31: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
Min(1)
Max
Units
TLO:SCL Clock Low Time 100 kHz mode
TCY/2 (BRG + 1)
—
µs
400 kHz mode
TCY/2 (BRG + 1)
—
µs
(2)
TCY/2 (BRG + 1)
—
µs
Clock High Time 100 kHz mode
TCY/2 (BRG + 1)
—
µs
400 kHz mode
TCY/2 (BRG + 1)
—
µs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
µs
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
Characteristic
1 MHz mode
IM11
IM20
IM21
IM25
THI:SCL
TF:SCL
TR:SCL
SDA and SCL
Fall Time
SDA and SCL
Rise Time
TSU:DAT Data Input
Setup Time
1 MHz mode(2)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
(2)
TBD
—
ns
0
—
ns
400 kHz mode
0
0.9
µs
1 MHz mode(2)
TBD
—
ns
1 MHz mode
IM26
IM30
IM31
IM33
THD:DAT Data Input
Hold Time
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
100 kHz mode
100 kHz mode
TCY/2 (BRG + 1)
—
µs
400 kHz mode
TCY/2 (BRG + 1)
—
µs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
µs
100 kHz mode
TCY/2 (BRG + 1)
—
µs
400 kHz mode
TCY/2 (BRG + 1)
—
µs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
µs
100 kHz mode
TCY/2 (BRG + 1)
—
µs
400 kHz mode
TCY/2 (BRG + 1)
—
µs
(2)
TCY/2 (BRG + 1)
—
µs
100 kHz mode
TCY/2 (BRG + 1)
—
ns
400 kHz mode
TCY/2 (BRG + 1)
—
ns
1 MHz mode(2)
TCY/2 (BRG + 1)
—
ns
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
(2)
—
—
ns
100 kHz mode
4.7
—
µs
1 MHz mode
IM34
IM40
THD:STO Stop Condition
Hold Time
TAA:SCL
Output Valid
from Clock
1 MHz mode
IM45
IM50
TBF:SDA Bus Free Time
CB
400 kHz mode
1.3
—
µs
1 MHz mode(2)
TBD
—
µs
—
400
pF
Bus Capacitive Loading
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
Legend: TBD = To Be Determined
Note 1: BRG is the value of the I2C™ Baud Rate Generator. Refer to the “Inter-Integrated Circuit™ (I2C)”
section in the “dsPIC30F Family Reference Manual” (DS70046).
2: Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS70000178D-page 260
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
FIGURE 21-18:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL
IS34
IS31
IS30
IS33
SDA
Stop
Condition
Start
Condition
FIGURE 21-19:
I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS25
IS33
SDA
In
IS40
IS40
IS45
SDA
Out
2006-2014 Microchip Technology Inc.
DS70000178D-page 261
dsPIC30F1010/202X
TABLE 21-32: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
IS10
IS11
IS20
IS21
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
Characteristic
Min
Max
Units
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(1)
100 kHz mode
0.5
4.0
—
—
s
s
400 kHz mode
0.6
—
s
SDA and SCL
Fall Time
1 MHz mode(1)
100 kHz mode
400 kHz mode
0.5
—
20 + 0.1 CB
—
300
300
s
ns
ns
CB is specified to be from
10 to 400 pF
SDA and SCL
Rise Time
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
—
20 + 0.1 CB
100
1000
300
ns
ns
ns
CB is specified to be from
10 to 400 pF
—
250
100
100
0
0
0
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
300
—
—
—
—
0.9
0.3
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
Clock Low Time
Clock High Time
IS25
TSU:DAT
Data Input
Setup Time
IS26
THD:DAT
Data Input
Hold Time
IS30
TSU:STA
Start Condition
Setup Time
IS31
THD:STA
Start Condition
Hold Time
IS33
TSU:STO
Stop Condition
Setup Time
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
Stop Condition
Hold Time
1 MHz mode(1)
100 kHz mode
400 kHz mode
0.6
4000
600
—
—
—
s
ns
ns
1 MHz mode(1)
Output Valid from 100 kHz mode
Clock
400 kHz mode
250
0
0
3500
1000
ns
ns
ns
1 MHz mode(1)
Bus Free Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
Bus Capacitive Loading
0
4.7
1.3
0.5
—
350
—
—
—
400
ns
s
s
s
pF
IS34
IS40
THD:STO
TAA:SCL
IS45
TBF:SDA
IS50
CB
Note 1:
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2C™ pins (for 1 MHz mode only).
DS70000178D-page 262
2006-2014 Microchip Technology Inc.
dsPIC30F1010/202X
TABLE 21-33: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 3.3V and 5.0V (±10%)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 2.7
Lesser of:
VDD + 0.3
or 5.5
V
AD02
AVSS
Module VSS Supply
Vss – 0.3
VSS + 0.3
V
VSS
VDD
V
AVSS – 0.3
AVDD + 0.3
V
Analog Input
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AD12
—
Leakage Current
—
±0.001
±0.244
A
VINL = AVSS = 0V,
AVDD = 5V,
Source Impedance = 1 k
AD13
—
Leakage Current
—
±0.001
±0.244
A
VINL = AVSS = 0V,
AVDD = 3.3V,
Source Impedance = 1 k
AD17
RIN
Recommended Impedance
of Analog Voltage Source
—
1K
AD20
Nr
Resolution
AD21
INL
Integral Nonlinearity
—
±0.5
< ±1
LSb VINL = AVSS = 0V,
AVDD = 5V
AD21A INL
Integral Nonlinearity
—
±0.5
< ±1
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD22
DNL
Differential Nonlinearity
—
±0.5
< ±1
LSb VINL = AVSS = 0V,
AVDD = 5V
AD22A DNL
Differential Nonlinearity
—
±0.5
< ±1
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD23
GERR
Gain Error
—
±0.75
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