dsPIC30F3014/4013
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
2010 Microchip Technology Inc.
DS70138G
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-666-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70138G-page 2
2010 Microchip Technology Inc.
dsPIC30F3014/4013
High-Performance, 16-Bit Digital Signal Controllers
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
High-Performance Modified RISC CPU:
•
•
•
•
•
•
•
•
•
•
Modified Harvard Architecture
C Compiler Optimized Instruction Set Architecture
Flexible Addressing modes
83 Base Instructions
24-Bit Wide Instructions, 16-Bit Wide Data Path
Up to 48 Kbytes On-Chip Flash Program Space
2 Kbytes of On-Chip Data RAM
1 Kbyte of Nonvolatile Data EEPROM
16 x 16-Bit Working Register Array
Up to 30 MIPS Operation:
- DC to 40 MHz External Clock Input
- 4 MHz-10 MHz Oscillator Input with
PLL Active (4x, 8x, 16x)
• Up to 33 Interrupt Sources:
- 8 user-selectable priority levels
- 3 external interrupt sources
- 4 processor traps
DSP Features:
• Dual Data Fetch
• Modulo and Bit-Reversed modes
• Two 40-Bit Wide Accumulators with Optional
saturation Logic
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• All DSP Instructions are Single Cycle
- Multiply-Accumulate (MAC) Operation
• Single-Cycle ±16 Shift
2010 Microchip Technology Inc.
Peripheral Features:
• High-Current Sink/Source I/O Pins: 25 mA/25 mA
• Up to Five 16-Bit Timers/Counters; Optionally Pair
Up
16-Bit Timers into 32-Bit Timer modules
• Up to Four 16-Bit Capture Input Functions
• Up to Four 16-Bit Compare/PWM Output Functions
• Data Converter Interface (DCI) Supports Common
Audio Codec Protocols, Including I2S and AC’97
• 3-Wire SPI module (supports 4 Frame modes)
• I2C™ module Supports Multi-Master/Slave mode
and 7-Bit/10-Bit Addressing
• Up to Two Addressable UART modules with FIFO
Buffers
• CAN bus module Compliant with CAN 2.0B
Standard
Analog Features:
• 12-Bit Analog-to-Digital Converter (ADC) with:
- 200 ksps conversion rate
- Up to 13 input channels
- Conversion available during Sleep and Idle
• Programmable Low-Voltage Detection (PLVD)
• Programmable Brown-out Reset
Special Microcontroller Features:
• Enhanced Flash Program Memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM Memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-Reprogrammable under Software Control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with On-Chip
Low-Power RC Oscillator for Reliable Operation
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip
low-power RC oscillator
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes:
- Sleep, Idle and Alternate Clock modes
DS70138G-page 3
dsPIC30F3014/4013
CMOS Technology:
•
•
•
•
Low-Power, High-Speed Flash Technology
Wide Operating Voltage Range (2.5V to 5.5V)
Industrial and Extended Temperature Ranges
Low-Power Consumption
dsPIC30F3014/4013 Controller Family
Program Memory
48K
8K
16K
2048
2048
1024
3
1024
2
5
4
CAN
dsPIC30F4013 40/44
24K
I2C™
dsPIC30F3014 40/44
SPI
Output
SRAM EEPROM Timer Input
Codec A/D 12-Bit
Comp/
Bytes
Bytes
16-Bit
Cap
Interface 200 Ksps
Bytes Instructions
Std PWM
Pins
UART
Device
2
—
13 ch
2
1
1
0
4
AC’97, I2S
13 ch
2
1
1
1
Pin Diagrams
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
VDD
Vss
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
INT0/RA11
IC2/INT2/RD9
RD3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
INT0/RA11
IC2/INT2/RD9
OC4/RD3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
dsPIC30F3014
40-Pin PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AVDD
AVss
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
Vss
RF0
RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
RD2
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AVDD
AVSS
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
AN12/COFS/RB12
EMUC2/OC1/RD0
EMUD2/OC2/RD1
VDD
VSS
C1RX/RF0
C1TX/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VDD
DS70138G-page 4
dsPIC30F4013
40-Pin PDIP
2010 Microchip Technology Inc.
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/NT1/RD8
RD2
VDD
VSS
RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
44-Pin TQFP
dsPIC30F3014
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/CN7/RB5
AN4/CN6/RB4
NC
NC
AN10/RB10
AN9/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
RF1
RF0
VSS
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/RB12
AN11/RB11
2010 Microchip Technology Inc.
DS70138G-page 5
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
RD2
VDD
VSS
RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
44-Pin QFN(1)
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F3014
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VSS
VDD
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/CN7/RB5
AN4/CN6/RB4
AN11/RB11
NC
AN10/RB10
AN9/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
12
13
14
15
16
17
18
19
20
21
22
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
RF1
RF0
VSS
VDD
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/RB12
Note
1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70138G-page 6
2010 Microchip Technology Inc.
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/INT1/RD8
OC3/RD2
VDD
VSS
OC4/RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
44-Pin TQFP
dsPIC30F4013
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
NC
NC
AN10/CSDI/RB10
AN9/CSCK/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
C1TX/RF1
C1RX/RF0
VSS
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/COFS/RB12
AN11/CSDO/RB11
2010 Microchip Technology Inc.
DS70138G-page 7
dsPIC30F3014/4013
Pin Diagrams (Continued)
44
43
42
41
40
39
38
37
36
35
34
EMUD3/U1TX/SDO1/SCL/RF3
EMUC3/SCK1/RF6
IC1/NT1/RD8
OC3/RD2
VDD
VSS
OC4/RD3
IC2/INT2/RD9
INT0/RA11
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
44-Pin QFN(1)
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F4013
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VSS
VDD
VDD
AN8/RB8
PGD/EMUD/AN7/RB7
PGC/EMUC/AN6/OCFA/RB6
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN11/CSDO/RB11
NC
AN10/CSDI/RB10
AN9/CSCK/RB9
AVSS
AVDD
MCLR
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
12
13
14
15
16
17
18
19
20
21
22
U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
C1TX/RF1
C1RX/RF0
VSS
VDD
VDD
EMUD2/OC2/RD1
EMUC2/OC1/RD0
AN12/COFS/RB12
Note
1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70138G-page 8
2010 Microchip Technology Inc.
dsPIC30F3014/4013
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 CPU Architecture Overview........................................................................................................................................................ 15
3.0 Memory Organization ................................................................................................................................................................. 25
4.0 Address Generator Units............................................................................................................................................................ 37
5.0 Flash Program Memory.............................................................................................................................................................. 43
6.0 Data EEPROM Memory ............................................................................................................................................................. 49
7.0 I/O Ports ..................................................................................................................................................................................... 53
8.0 Interrupts .................................................................................................................................................................................... 59
9.0 Timer1 Module ........................................................................................................................................................................... 67
10.0 Timer2/3 Module ........................................................................................................................................................................ 71
11.0 Timer4/5 Module ....................................................................................................................................................................... 77
12.0 Input Capture Module................................................................................................................................................................. 81
13.0 Output Compare Module ............................................................................................................................................................ 85
14.0 I2C™ Module ............................................................................................................................................................................. 91
15.0 SPI Module................................................................................................................................................................................. 99
16.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 103
17.0 CAN Module ............................................................................................................................................................................. 111
18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 121
19.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 131
20.0 System Integration ................................................................................................................................................................... 141
21.0 Instruction Set Summary .......................................................................................................................................................... 159
22.0 Development Support............................................................................................................................................................... 167
23.0 Electrical Characteristics .......................................................................................................................................................... 171
24.0 Packaging Information.............................................................................................................................................................. 211
Index ................................................................................................................................................................................................. 219
The Microchip Web Site ..................................................................................................................................................................... 225
Customer Change Notification Service .............................................................................................................................................. 225
Customer Support .............................................................................................................................................................................. 225
Reader Response .............................................................................................................................................................................. 226
Product Identification System ............................................................................................................................................................ 227
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
2010 Microchip Technology Inc.
DS70138G-page 9
dsPIC30F3014/4013
NOTES:
DS70138G-page 10
2010 Microchip Technology Inc.
dsPIC30F3014/4013
1.0
DEVICE OVERVIEW
Note:
This document contains specific information for the
dsPIC30F3014/4013 Digital Signal Controller (DSC)
devices. The dsPIC30F3014/4013 devices contain
extensive Digital Signal Processor (DSP) functionality
within a high-performance, 16-bit microcontroller
(MCU) architecture. Figure 1-1 and Figure 1-2 show
device block diagrams for dsPIC30F3014 and
dsPIC30F4013, respectively.
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
FIGURE 1-1:
dsPIC30F3014 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block 8
Data Latch
Y Data
RAM
(1 Kbyte)
Address
Latch
16
24
Program Memory
(24 Kbytes)
INT0/RA11
PORTA
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Data Latch
X Data
RAM
(1 Kbyte)
Address
Latch
16
16
24
Address Latch
16
16
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
16
Data EEPROM
(1 Kbyte)
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
IR
16
16
Decode
Instruction
Decode and
Control
Control Signals
to Various Blocks
OSC1/CLKI
PORTC
DSP
Engine
VDD, VSS
AVDD, AVSS
Watchdog
Timer
Low-Voltage
Detect
12-Bit ADC
2010 Microchip Technology Inc.
Divide
Unit
Oscillator
Start-up Timer
EMUC2/OC1/RD0
EMUD2/OC2/RD1
RD2
RD3
IC1/INT1/RD8
IC2/INT2/RD9
ALU
POR/BOR
Reset
MCLR
EMUC1/SOSCO/T1CK/U1ARX/
CN0/RC14
OSC2/CLKO/RC15
16 16
Power-up
Timer
Timing
Generation
EMUD1/SOSCI/T2CK/U1ATX/
CN1/RC13
16 x 16
W Reg Array
16
16
PORTD
Input
Capture
Module
Output
Compare
Module
I2C™
Timers
SPI1
UART1,
UART2
RF0
RF1
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/RF6
PORTF
DS70138G-page 11
dsPIC30F3014/4013
FIGURE 1-2:
dsPIC30F4013 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
Data Latch
Y Data
RAM
(1 Kbyte)
Address
Latch
16
24
Program Memory
(48 Kbytes)
INT0/RA11
PORTA
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Data Latch
X Data
RAM
(1 Kbyte)
Address
Latch
16
16
24
Address Latch
16
16
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/CSCK/RB9
AN10/CSDI/RB10
AN11/CSDO/RB11
AN12/COFS/RB12
16
Data EEPROM
(1 Kbyte)
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
IR
16
16
Decode
Instruction
Decode &
Control
PORTC
Power-up
Timer
DSP
Engine
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
ALU
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
DS70138G-page 12
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
CAN1
EMUC1/SOSCO/T1CK/U1ARX/
CN0/RC14
OSC2/CLKO/RC15
16 16
Control Signals
to Various Blocks
OSC1/CLKI
EMUD1/SOSCI/T2CK/U1ATX/
CN1/RC13
16 x 16
W Reg Array
Watchdog
Timer
Low-Voltage
Detect
IC1/INT1/RD8
IC2/INT2/RD9
16
16
PORTD
12-Bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
Timers
DCI
SPI1
UART1,
UART2
C1RX/RF0
C1TX/RF1
U1RX/SDI1/SDA/RF2
EMUD3/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/RF6
PORTF
2010 Microchip Technology Inc.
dsPIC30F3014/4013
Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN12
I
Analog
Analog input channels. AN6 and AN7 are also used for device programming
data and clock inputs, respectively.
AVDD
P
P
Positive supply for analog module. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog module. This pin must be connected at all times.
CLKI
I
CLKO
O
CN0-CN7,
CN17-CN18
I
ST
Input change notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
—
Data Converter Interface Frame Synchronization pin.
Data Converter Interface Serial Clock input/output pin.
Data Converter Interface Serial data input pin.
Data Converter Interface Serial data output pin.
C1RX
C1TX
I
O
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1, IC2, IC7,
IC8
I
ST
Capture inputs 1,2, 7 and 8.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
LVDIN
I
Analog
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA
OC1-OC4
I
O
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare outputs 1 through 4.
OSC1
I
OSC2
I/O
PGD
PGC
I/O
I
Pin Name
Description
ST/CMOS External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
—
Always associated with OSC2 pin function.
Low-Voltage Detect Reference Voltage Input pin.
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
ST
ST
In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.
Legend: CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
I
= Input
2010 Microchip Technology Inc.
Analog = Analog input
O
= Output
P
= Power
DS70138G-page 13
dsPIC30F3014/4013
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
RA11
I/O
ST
PORTA is a bidirectional I/O port.
RB0-RB12
I/O
ST
PORTB is a bidirectional I/O port.
RC13-RC15
I/O
ST
PORTC is a bidirectional I/O port.
RD0-RD3,
RD8, RD9
I/O
ST
PORTD is a bidirectional I/O port.
Pin Name
Description
RF0-RF5
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
—
ST
—
UART1 receive.
UART1 transmit.
UART1 alternate receive.
UART1 alternate transmit.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
I
= Input
DS70138G-page 14
Analog = Analog input
O
= Output
P
= Power
2010 Microchip Technology Inc.
dsPIC30F3014/4013
2.0
Note:
2.1
CPU ARCHITECTURE
OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
Core Overview
This section contains a brief overview of the CPU
architecture of the dsPIC30F.
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (refer to Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are
supported using the DO and REPEAT instructions, both
of which are interruptible at any point.
The working register array consists of 16-bit x 16-bit
registers, each of which can act as data, address or offset registers. One working register (W15) operates as
a Software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely
through the X memory, AGU, which provides the
appearance of a single, unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device-specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
2010 Microchip Technology Inc.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can
be mapped into the lower half (user space) of program space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (Modulo Addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing on
destination effective addresses to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 “Address Generator Units” for
details on Modulo and Bit-Reversed Addressing.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
addressing modes, depending upon their functional
requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A+B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput. It
features a high-speed, 17-bit x 17-bit multiplier, a 40-bit
ALU, two 40-bit saturating accumulators and a 40-bit
bidirectional barrel shifter. Data in the accumulator, or
any working register, can be shifted up to 15 bits right, or
16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been
designed for optimal real-time performance. The MAC
class of instructions can concurrently fetch two data
operands from memory while multiplying two W
registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear is for all others. This has been
achieved in a transparent and flexible manner by
dedicating certain working registers to each address
space for the MAC class of instructions.
DS70138G-page 15
dsPIC30F3014/4013
The core does not support a multi-stage instruction
pipeline. However, a single-stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities ranging from 8 to 15.
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start and popped on loop end.
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated Software Stack Pointer (SP) and
is automatically modified by exception processing and
subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
Stack Frames).
Note:
In order to protect against misaligned
stack accesses, W15 is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer, as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS register
(SR), the Least Significant Byte (LSB) of which is
referred to as the SR Low byte (SRL) and the Most
Significant Byte (MSB) as the SR High byte (SRH). See
Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Priority Level Status bits, IPL and the Repeat Active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP adder/subtracter Status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3
PROGRAM COUNTER
The program counter is 23 bits wide; bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte-wide data memory space accesses.
DS70138G-page 16
2010 Microchip Technology Inc.
dsPIC30F3014/4013
FIGURE 2-1:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
AD39
Stack Pointer Limit Register
AD15
AD31
AD0
AccA
DSP
Accumulators
AccB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
Data Table Page Address
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
2010 Microchip Technology Inc.
DC IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70138G-page 17
dsPIC30F3014/4013
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
1.
2.
3.
4.
5.
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.s – 16/16 signed divide
DIV.u – 16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruction, as shown in Table 2-1 (REPEAT will execute the
target instruction {operand value+1} times). The
REPEAT loop count must be setup for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
TABLE 2-1:
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
DIVIDE INSTRUCTIONS
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn W0; Rem W1
DIV.sd
Signed divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.s
Signed divide: Wm/Wn W0; Rem W1
DIV.ud
Unsigned divide: (Wm+1:Wm)/Wn W0; Rem W1
DIV.u
Unsigned divide: Wm/Wn W0; Rem W1
DS70138G-page 18
2010 Microchip Technology Inc.
dsPIC30F3014/4013
2.4
DSP Engine
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform
inherent
accumulator-to-accumulator
operations,
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow architecture, therefore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction (e.g.,
ED, EDAC). (See Table 2-2 for DSP instructions.)
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection
(ACCSAT).
7.
Note:
For CORCON layout, see Table 3-3.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2:
Instruction
CLR
Algebraic
Operation
ACC WB?
A=0
Yes
2
A = (x – y)
No
EDAC
A = A + (x – y)2
No
MAC
A = A + (x * y)
Yes
MAC
A = A + x2
No
No change in A
Yes
A=x*y
No
ED
MOVSAC
MPY
MPY.N
MSC
2010 Microchip Technology Inc.
DSP INSTRUCTION
SUMMARY
A=–x*y
No
A=A–x*y
Yes
DS70138G-page 19
dsPIC30F3014/4013
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-Bit Accumulator A
40-Bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-Bit
Multiplier/Scaler
16
16
To/From W Array
DS70138G-page 20
2010 Microchip Technology Inc.
dsPIC30F3014/4013
2.4.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value, which is signextended to 40 bits. Integer data is inherently
represented as a signed two’s complement value,
where the MSB is defined as a sign bit. Generally
speaking, the range of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. For a 16-bit integer, the data
range is -32768 (0x8000) to 32767 (0x7FFF) including
‘0’. For a 32-bit integer, the data range is 2,147,483,648 (0x8000 0000) to 2,147,483,645
(0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1 – 21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518x10-5. In Fractional mode, the 16x16
multiply operation generates a 1.31 product, which has
a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU multiply instructions, which includes integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified register(s) in the W array.
2.4.2
2.4.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active-low and the
other input is complemented. The adder/subtracter
generates overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation if selected. It uses
the result of the adder, the overflow Status bits
described above, and the SATA/B (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow. They are:
1.
2.
3.
4.
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
via the barrel shifter prior to accumulation.
2010 Microchip Technology Inc.
Adder/Subtracter, Overflow and
Saturation
5.
6.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 8.0 “Interrupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
DS70138G-page 21
dsPIC30F3014/4013
The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation or bit 39 for 40-bit saturation) and
will be saturated if saturation is enabled. When
saturation is not enabled, SA and SB default to bit 39
overflow and, thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1
register is set, SA and SB bits generate an arithmetic
warning trap when saturation is disabled.
The overflow and saturation Status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three saturation and overflow
modes:
1.
2.
3.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erroneous data or unexpected algorithm problems
(e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF), or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
Bit 39 Catastrophic Overflow:
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
DS70138G-page 22
2.4.2.2
Accumulator ‘Write-Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
2.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
[W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block which performs
a conventional (biased) or convergent (unbiased) round
function during an accumulator write (store). The Round
mode is determined by the state of the RND bit in the
CORCON register. It generates a 16-bit, 1.15 data value,
which is passed to the data space write saturation logic.
If rounding is not indicated by the instruction, a truncated
1.15 data value is stored and the least significant word
(lsw) is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding
operations, the value tends to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the Least Significant bit (LSb) (bit 16 of the accumulator) of ACCxH
is examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,
ACCxH is not modified. Assuming that bit 16 is
effectively random in nature, this scheme removes any
rounding bias that may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write-back operation
functions in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
2010 Microchip Technology Inc.
dsPIC30F3014/4013
2.4.2.4
Data Space Write Saturation
2.4.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space may also be saturated but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit,
1.15 fractional value from the round logic block as its
input, together with overflow status from the original
source (accumulator) and the 16-bit round adder.
These are combined and used to select the appropriate
1.15 fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the
maximum positive 1.15 value, 0x7FFF. For input data
less than 0xFF8000, data written to memory is forced
to the maximum negative 1.15 value, 0x8000. The
Most Significant bit (MSb) of the source (bit 39) is used
to determine the sign of the operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
to 31 for right shifts, and bit positions 0 to 16 for left
shifts.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2010 Microchip Technology Inc.
DS70138G-page 23
dsPIC30F3014/4013
NOTES:
DS70138G-page 24
2010 Microchip Technology Inc.
dsPIC30F3014/4013
Note:
MEMORY ORGANIZATION
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG to determine user or configuration space access. In Table 3-1, bit 23 allows access to
the Device ID, the User ID and the Configuration bits;
otherwise, bit 23 is always clear.
FIGURE 3-2:
dsPIC30F4013 PROGRAM
SPACE MEMORY MAP
Reset – GOTO Instruction
Reset – Target Address
000000
000002
000004
Interrupt Vector Table
Program Address Space
Reset – GOTO Instruction
Reset – Target Address
Interrupt Vector Table
Reserved
00007E
000080
User Memory
Space
000084
Alternate Vector Table
0000FE
000100
User Flash
Program Memory
(8K instructions)
Reserved
(Read ‘0’s)
Data EEPROM
(1 Kbyte)
003FFE
004000
000084
0000FE
000100
User Flash
Program Memory
(16K instructions)
Data EEPROM
(1 Kbyte)
000000
000002
000004
00007E
000080
Alternate Vector Table
Reserved
(Read ‘0’s)
dsPIC30F3014 PROGRAM
SPACE MEMORY MAP
Vector Tables
FIGURE 3-1:
Reserved
User Memory
Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA) or data
space EA, when program space is mapped into data
space as defined by Table 3-1. Note that the program
space address is incremented by two between successive program words in order to provide compatibility
with data space addressing.
007FFE
008000
7FFBFE
7FFC00
7FFFFE
800000
Reserved
8005BE
8005C0
Configuration Memory
Space
3.1
Vector Tables
3.0
UNITID (32 instr.)
8005FE
800600
Reserved
Device Configuration
Registers
7FFBFE
7FFC00
F7FFFE
F80000
F8000E
F80010
Reserved
7FFFFE
800000
Reserved
DEVID (2)
FEFFFE
FF0000
FF0002
Configuration Memory
Space
8005BE
8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
2010 Microchip Technology Inc.
FEFFFE
FF0000
FF0002
DS70138G-page 25
dsPIC30F3014/4013
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
Instruction Access
User
TBLRD/TBLWT
User
(TBLPAG = 0)
TBLPAG
Data EA
TBLRD/TBLWT
Configuration
(TBLPAG = 1)
TBLPAG
Data EA
Program Space Visibility
User
FIGURE 3-3:
PC
0
0
PSVPAG
0
Data EA
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
Select
Using
Program
Space
Visibility
0
1
0
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0 TBLPAG Reg
User/
Configuration
Space
Select
Note:
DS70138G-page 26
8 bits
16 bits
24-bit EA
Byte
Select
Program space visibility cannot be used to access bits of a word in program memory.
2010 Microchip Technology Inc.
dsPIC30F3014/4013
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
A set of table instructions are provided to move byte or
word-sized data to and from program space. (See
Figure 3-4 and Figure 3-5.)
1.
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lsw
of any address within program space, without going
through data space. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8 bits of a
program space word can be accessed as data.
2.
3.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the MS Data Byte.
4.
TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P maps to D.
Byte: Read one of the LSBs of the program
address;
P maps to the destination byte when byte
select = 0;
P maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 5.0
“Flash Program Memory” for details on Flash
programming)
TBLRDH: Table Read High
Word: Read the most significant word (msw) of
the program address; P maps to D;
D will always be = 0.
Byte: Read one of the MSBs of the program
address;
P maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 5.0
“Flash Program Memory” for details on Flash
Programming)
Figure 3-3 shows how the EA is created for table operations and data space accesses (PSV = 1). Here,
P refers to a program space word, whereas
D refers to a data space word.
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
PC Address
0x000000
0x000002
0x000004
0x000006
Program Memory
‘Phantom’ Byte
(read as ‘0’)
2010 Microchip Technology Inc.
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDL.W
TBLRDL.B (Wn = 0)
TBLRDL.B (Wn = 1)
DS70138G-page 27
dsPIC30F3014/4013
FIGURE 3-5:
PROGRAM DATA TABLE ACCESS (MSB)
TBLRDH.W
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDH.B (Wn = 0)
Program Memory
‘Phantom’ Byte
(read as ‘0’)
3.1.2
TBLRDH.B (Wn = 1)
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space, EA, is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-6), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the “16-bit MCU and DSC Programmer’s Reference
Manual” (DS70157) for details on instruction encoding.
DS70138G-page 28
Note that by incrementing the PC by 2 for each
program memory word, the 15 LSbs of data space
addresses directly map to the 15 LSbs in the corresponding program space addresses. The remaining
bits are provided by the Program Space Visibility Page
register, PSVPAG, as shown in Figure 3-6.
Note:
PSV access is temporarily disabled during
table reads/writes.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions require one instruction
cycle in addition to the specified execution time:
- MAC class of instructions with data operand
prefetch
- MOV instructions
- MOV.D instructions
• All other instructions require two instruction cycles
in addition to the specified execution time of the
instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop allows the
instruction accessing data, using PSV, to execute
in a single cycle.
2010 Microchip Technology Inc.
dsPIC30F3014/4013
FIGURE 3-6:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Data Space
Program Space
0x0000
0x000100
PSVPAG(1)
0x00
8
15
EA = 0
Data 16
Space
15
EA
EA = 1
0x8000
15
Address
Concatenation 23
23
15
0
0x000200
Upper Half of Data
Space is Mapped
into Program Space
0x007FFF
0xFFFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x00, W0
W0, PSVPAG
0x8200, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note:
PSVPAG is an 8-bit register, containing bits of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
The memory map shown here is for a dsPIC30F4013 device.
2010 Microchip Technology Inc.
DS70138G-page 29
dsPIC30F3014/4013
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions),
or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address
Generation Units (AGUs) and separate data paths.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent Linear
Addressing space, X and Y spaces have contiguous
addresses.
FIGURE 3-7:
When executing any instruction other than one of
the MAC class of instructions, the X block consists of the
64-Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions, the
X block consists of the 64-Kbyte data address space
excluding the Y address block (for data reads only). In
other words, all other instructions regard the entire data
memory as one composite address space. The MAC
class instructions extract the Y address space from data
space and address it using EAs sourced from W10 and
W11. The remaining X data space is addressed using W8
and W9. Both address spaces are concurrently accessed
only with the MAC class instructions.
The data space memory map is shown in Figure 3-7.
dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP
MSB
Address
MSB
2 Kbyte
SFR Space
LSB
Address
16 bits
LSB
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
2 Kbyte
SRAM Space
Y Data RAM (Y)
0x0FFF
0x1001
0x0FFE
0x1000
0x1FFF
0x1FFE
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70138G-page 30
0x0BFE
0x0C00
0x0BFF
0x0C01
8 Kbyte
Near
Data
Space
0xFFFE
2010 Microchip Technology Inc.
dsPIC30F3014/4013
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-8:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write)
MAC Class Ops (Write)
Indirect EA using any W
2010 Microchip Technology Inc.
MAC Class Ops (Read)
Indirect EA using W8, W9
Indirect EA using W10, W11
DS70138G-page 31
dsPIC30F3014/4013
3.2.2
DATA SPACES
3.2.3
The X data space is used by all instructions and supports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports Modulo Addressing for
all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write-back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-7 and is not userprogrammable. Should an EA point to data outside its
own assigned address space, or to a location outside
physical memory, an all zero word/byte is returned. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X Space Pointers) returns
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data
space in a MAC instruction
0x0000
W10 or W11 used to access X
data space in a MAC instruction
0x0000
DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads read the complete
word which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations which are restricted to word-sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. Should
a misaligned read or write be attempted, an address
error trap is generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then executed, allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
FIGURE 3-9:
15
DATA ALIGNMENT
MSB
87
LSB
0
0001
Byte 1
Byte 0
0000
0003
Byte 3
Byte 2
0002
0005
Byte 5
Byte 4
0004
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70138G-page 32
2010 Microchip Technology Inc.
dsPIC30F3014/4013
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
Zero-Extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8-Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM
is forced to ‘0’ because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
generated, using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap does not
occur. The stack error trap occurs on a subsequent
push operation. Thus, for example, if it is desirable to
cause a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-10:
3.2.6
SOFTWARE STACK
0x0000
CALL STACK FRAME
15
0
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes as shown in
Figure 3-10. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
2010 Microchip Technology Inc.
Stack Grows Towards
Higher Address
The dsPIC DSC devices contain a software stack. W15
is used as the Stack Pointer.
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
DS70138G-page 33
SFR Name
CORE REGISTER MAP(1)
Address
(Home)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
2010 Microchip Technology Inc.
W0
0000
W0/WREG
0000 0000 0000 0000
W1
0002
W1
0000 0000 0000 0000
W2
0004
W2
0000 0000 0000 0000
W3
0006
W3
0000 0000 0000 0000
W4
0008
W4
0000 0000 0000 0000
W5
000A
W5
0000 0000 0000 0000
W6
000C
W6
0000 0000 0000 0000
W7
000E
W7
0000 0000 0000 0000
W8
0010
W8
0000 0000 0000 0000
W9
0012
W9
0000 0000 0000 0000
W10
0014
W10
0000 0000 0000 0000
W11
0016
W11
0000 0000 0000 0000
W12
0018
W12
0000 0000 0000 0000
W13
001A
W13
0000 0000 0000 0000
W14
001C
W14
0000 0000 0000 0000
W15
001E
W15
0000 1000 0000 0000
SPLIM
0020
SPLIM
0000 0000 0000 0000
ACCAL
0022
ACCAL
0000 0000 0000 0000
ACCAH
0024
ACCAH
ACCAU
0026
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
PCL
002E
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
—
TBLPAG
0000 0000 0000 0000
PSVPAG
0034
—
—
—
—
—
—
—
—
PSVPAG
0000 0000 0000 0000
RCOUNT
0036
RCOUNT
DCOUNT
0038
DCOUNT
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
SR
Legend:
1:
0000 0000 0000 0000
Sign Extension (ACCA)
ACCAU
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Sign Extension (ACCB)
ACCBU
0000 0000 0000 0000
PCL
0000 0000 0000 0000
—
PCH
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
DOSTARTL
—
—
—
—
—
—
—
0040
—
—
—
—
—
—
—
0042
OA
OB
SA
SB
OAB
SAB
DA
—
0
—
DOSTARTH
—
—
DOENDH
DC
IPL2
DOENDL
0
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
IPL1
IPL0
RA
N
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
OV
Z
C
0000 0000 0000 0000
dsPIC30F3014/4013
DS70138G-page 34
TABLE 3-3:
2010 Microchip Technology Inc.
TABLE 3-3:
SFR Name
CORE REGISTER MAP(1) (CONTINUED)
Address
(Home)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
EDT
DL2
DL1
DL0
SATA
SATB
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Reset State
IPL3
PSV
RND
IF
0000 0000 0010 0000
CORCON
0044
—
—
—
US
MODCON
0046
XMODEN
YMODEN
—
—
XMODSRT
0048
XS
0
uuuu uuuu uuuu uuu0
XMODEND
004A
XE
1
uuuu uuuu uuuu uuu1
YMODSRT
004C
YS
0
uuuu uuuu uuuu uuu0
YMODEND
004E
YE
1
XBREV
0050
BREN
0052
—
DISICNT
Legend:
1:
BWM
YWM
XB
—
SATDW ACCSAT
Bit 3
DISICNT
XWM
0000 0000 0000 0000
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F3014/4013
DS70138G-page 35
dsPIC30F3014/4013
NOTES:
DS70138G-page 36
2010 Microchip Technology Inc.
dsPIC30F3014/4013
4.0
Note:
ADDRESS GENERATOR UNITS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word-sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
Instruction Addressing Modes
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
TABLE 4-1:
4.1.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the File register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
2010 Microchip Technology Inc.
The sum of Wn and a literal forms the EA.
DS70138G-page 37
dsPIC30F3014/4013
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instructions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.1.4
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the Data Pointers through register indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 is always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
4.2
Modulo Addressing
Modulo Addressing is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or
program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces.
Modulo Addressing can operate on any W register
pointer. However, it is not advisable to use W14 or W15
for Modulo Addressing since these two registers are
used as the Stack Frame Pointer and Stack Pointer,
respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks are performed on both the lower and upper
address boundaries).
Register Indirect with Register Offset
addressing is only available for W9 (in X
space) and W11 (in Y space).
DS70138G-page 38
2010 Microchip Technology Inc.
dsPIC30F3014/4013
4.2.1
START AND END ADDRESS
4.2.2
The Modulo Addressing scheme requires that a starting and an ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
Note:
Y space Modulo Addressing EA calculations assume word-sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control register MODCON contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers operate with Modulo Addressing. If XWM = 15, X RAGU
and X WAGU Modulo Addressing is disabled. Similarly,
if YWM = 15, Y AGU Modulo Addressing is disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON (see Table 3-3). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM), to
which Modulo Addressing is to be applied, is stored in
MODCON. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON.
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x0800
MOV
MOV
MOV
MOV
MOV
MOV
#0x800,W0
W0,XMODSRT
#0x863,W0
W0,MODEND
#0x8001,W0
W0,MODCON
MOV
MOV
#0x0000,W0
#0x800,W1
DO
AGAIN,#0x31
MOV
W0,[W1++]
AGAIN: INC W0,W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
;fill the 50 buffer locations
;fill the next location
;increment the fill value
0x0863
Start Addr = 0x0800
End Addr = 0x0863
Length = 0x0032 words
2010 Microchip Technology Inc.
DS70138G-page 39
dsPIC30F3014/4013
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the upper (for incrementing buffers) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
Note:
4.3
The modulo corrected effective address is
written back to the register only when PreModify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7+W2])
is used, Modulo Addressing correction is
performed but the contents of the register
remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.3.1
2.
3.
XB is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing) and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is only
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It does not function for any other addressing
mode or for byte sized data. Normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
Note:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed Addressing assumes priority when active for the X
WAGU, and X WAGU Modulo Addressing
is disabled. However, Modulo Addressing
continues to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b1
b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
DS70138G-page 40
2010 Microchip Technology Inc.
dsPIC30F3014/4013
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
TABLE 4-3:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Buffer Size (Words)
XB Bit-Reversed Address Modifier Value
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
8
0x0004
4
0x0002
2
0x0001
2010 Microchip Technology Inc.
DS70138G-page 41
dsPIC30F3014/4013
NOTES:
DS70138G-page 42
2010 Microchip Technology Inc.
dsPIC30F3014/4013
5.0
FLASH PROGRAM MEMORY
Note:
5.2
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.
With RTSP, the user may erase program memory,
32 instructions (96 bytes) at a time and can write
program memory data, 32 instructions (96 bytes) at a
time.
5.3
5.1
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
Run-Time Self-Programming (RTSP)
In-Circuit Serial Programming™ (ICSP™)
A 24-bit program memory address is formed using
bits of the TBLPAG register and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 5-1.
In-Circuit Serial Programming
(ICSP)
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 5-1:
Table Instruction Operation
Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
1.
2.
Run-Time Self-Programming
(RTSP)
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0 NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
2010 Microchip Technology Inc.
1/0 TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
DS70138G-page 43
dsPIC30F3014/4013
5.4
RTSP Operation
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the Table Pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a 32 address boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register.
32 TBLWTL and four TBLWTH instructions are
required to load the 32 instructions. If multiple panel
programming is required, the Table Pointer needs to be
changed and the next set of multiple write latches
written.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
DS70138G-page 44
5.5
Control Registers
The four SFRs used to read and write the program
Flash memory are:
•
•
•
•
NVMCON
NVMADR
NVMADRU
NVMKEY
5.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
5.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA of the last table instruction that
has been executed and selects the row to write.
5.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register captures the EA of the last table instruction that
has been executed.
5.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 5.6
“Programming Operations” for further details.
Note:
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
2010 Microchip Technology Inc.
dsPIC30F3014/4013
5.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON)
starts the operation and the WR bit is automatically
cleared when the operation is finished.
5.6.1
4.
5.
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase or program one row of program
Flash memory at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a) Set up NVMCON register for multi-word,
program Flash, erase, and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This begins erase cycle.
f) CPU stalls for the duration of the erase cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 5-1:
6.
Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a) Set up NVMCON register for multi-word,
program Flash, program, and set WREN
bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. This begins program cycle.
e) CPU stalls for duration of the program cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
5.6.2
ERASING A ROW OF PROGRAM
MEMORY
Example 5-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word
; program memory selected, and writes enabled
MOV
#0x4041,W0
;
;
MOV
W0,NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR),W0
;
;
MOV
W0,NVMADRU
MOV
#tbloffset(PROG_ADDR),W0
;
MOV
W0, NVMADR
;
DISI
#5
;
;
MOV
#0x55,W0
;
MOV
W0,NVMKEY
MOV
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;
MOV
W1,NVMKEY
;
BSET
NVMCON,#WR
;
NOP
;
NOP
;
2010 Microchip Technology Inc.
write
Init NVMCON SFR
Initialize PM Page Boundary SFR
Intialize in-page EA[15:0] pointer
Initialize NVMADR SFR
Block all interrupts with priority 3',3@
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DS70138G-page 216
2010 Microchip Technology Inc.
dsPIC30F3014/4013
APPENDIX A:
REVISION HISTORY
Revision D (June 2006)
Previous versions of this data sheet contained
Advance or Preliminary Information. They were
distributed with incomplete characterization data.
This revision reflects these changes:
• Revised I2C Slave Addresses
(see Table 14-1)
• Updated example for ADC Conversion Clock
selection (see Section 19.0 “12-bit Analog-toDigital Converter (ADC) Module”)
• Base instruction CP1 eliminated from instruction
set (seeTable 21-2)
• Revised electrical characteristics:
- Operating Current (IDD) Specifications
(see Table 23-5)
- Idle Current (IIDLE) Specifications
(see Table 23-6)
- Power-down Current (IPD) Specifications
(see Table 23-7)
- I/O pin Input Specifications
(see Table 23-8)
- Brown Out Reset (BOR) Specifications
(see Table 23-11)
- Watchdog Timer time-out limits
(see Table 23-20)
Revision E (January 2007)
This revision includes updates to the packaging
diagrams.
Revision F (April 2008)
This revision reflects these updates:
• Added FUSE Configuration Register (FICD)
details (see Section 20.8 “Device Configuration
Registers” and Table 20-8)
• Added Note 2 in Device Configuration Registers
table (Table 20-8)
• Removed erroneous statement regarding generation of CAN receive errors (see Section 17.4.5
“Receive Errors”)
• Updated ADC Conversion Clock and Sampling
Rate Calculation (see Example 19-1). Minimum
TAD is 334 nsec.
• Updated details related to the Input Change
Notification module:
- Updated last sentence in the first paragraph
of Section 7.3 “Input Change Notification
Module”
- Updated Table 7-2
- Removed Table 7-3, Table 7-4, and Table 7-5
2010 Microchip Technology Inc.
• Electrical Specifications:
- Resolved TBD values for parameters DO10,
DO16, DO20, and DO26 (see Table 23-9)
- 10-bit High-Speed ADC tPDU timing parameter (time to stabilize) has been updated from
20 µs typical to 20 µs maximum (see
Table 23-38)
- Parameter OS65 (Internal RC Accuracy) has
been expanded to reflect multiple Min and
Max values for different temperatures (see
Table 23-18)
- Parameter DC12 (RAM Data Retention Voltage) has been updated to include a Min value
(see Table 23-4)
- Parameter D134 (Erase/Write Cycle Time)
has been updated to include Min and Max
values and the Typ value has been removed
(see Table 23-12)
- Removed parameters OS62 (Internal FRC
Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table 23-17)
- Parameter OS63 (Internal FRC Accuracy)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 23-17)
- Removed parameters DC27a, DC27b,
DC47a, and DC47b (references to IDD,
20 MIPs @ 3.3V) in Table 23-5 and
Table 23-6
- Removed parameters CS77 and CS78
(references to TRACL and TFACL @ 3.3V) in
Table 23-29
- Updated Min and Max values and Conditions
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for
parameter SY20 (see Table 23-20)
• Additional minor corrections throughout the
document
DS70138G-page 217
dsPIC30F3014/4013
Revision G (November 2010)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in Table A-1.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit Digital
Signal Controllers”
Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”).
Section 1.0 “Device Overview”
Removed the “DCI” peripheral block from the dsPIC30F3014 Block Diagram
(see Figure 1-1).
Section 20.0 “System Integration”
Added a note on OSCTUN functionality in Section 20.2.5 “Fast RC
Oscillator (FRC)”.
Updated the Pinout I/O Descriptions for AVDD and AVSS (see Table 1-1).
Updated the operating frequencies for the following Oscillator Operating
Modes (see Table 20-1):
•
•
•
•
•
Section 23.0 “Electrical
Characteristics”
XTL
XT w/PLL 16x
HS/2 w/PLL 4x, 8x, and 16x
HS/3 w/PLL 4x, 8x, and 16x
EC w/PLL 4x, 8x, and 16x
Updated the maximum value for parameter DI19 and the minimum value for
parameter DI29 in the I/O Pin Input Specifications (see Table 23-8).
Removed parameter D136 and updated the minimum, typical, maximum,
and conditions for parameters D122 and D134 in the Program and
EEPROM specifications (see Table 23-12).
DS70138G-page 218
2010 Microchip Technology Inc.
dsPIC30F3014/4013
INDEX
Numerics
12-Bit Analog-to-Digital Converter (A/D) Module .............. 131
A
A/D .................................................................................... 131
Aborting a Conversion .............................................. 133
ADCHS Register ....................................................... 131
ADCON1 Register..................................................... 131
ADCON2 Register..................................................... 131
ADCON3 Register..................................................... 131
ADCSSL Register ..................................................... 131
ADPCFG Register..................................................... 131
Configuring Analog Port Pins.............................. 54, 138
Connection Considerations....................................... 138
Conversion Operation ............................................... 132
Effects of a Reset...................................................... 137
Operation During CPU Idle Mode ............................. 137
Operation During CPU Sleep Mode.......................... 137
Output Formats ......................................................... 137
Power-Down Modes.................................................. 137
Programming the Sample Trigger............................. 133
Register Map............................................................. 139
Result Buffer ............................................................. 132
Sampling Requirements............................................ 136
Selecting the Conversion Sequence......................... 132
AC Characteristics ............................................................ 180
Load Conditions ........................................................ 181
AC Temperature and Voltage Specifications .................... 181
AC-Link Mode Operation .................................................. 128
16-Bit Mode............................................................... 128
20-Bit Mode............................................................... 129
ADC
Selecting the Conversion Clock ................................ 133
ADC Conversion Speeds .................................................. 134
Address Generator Units .................................................... 37
Alternate Vector Table ........................................................ 64
Analog-to-Digital Converter. See A/D.
Assembler
MPASM Assembler................................................... 168
Automatic Clock Stretch...................................................... 94
During 10-Bit Addressing (STREN = 1) ...................... 94
During 7-Bit Addressing (STREN = 1) ........................ 94
Receive Mode ............................................................. 94
Transmit Mode ............................................................ 94
B
Band Gap Start-up Time
Requirements............................................................ 187
Barrel Shifter ....................................................................... 23
Bit-Reversed Addressing .................................................... 40
Example ...................................................................... 40
Implementation ........................................................... 40
Modifier Values Table ................................................. 41
Sequence Table (16-Entry)......................................... 41
Block Diagrams
12-Bit A/D Functional ................................................ 131
16-Bit Timer1 Module.................................................. 67
16-Bit Timer2 .............................................................. 73
16-Bit Timer3 .............................................................. 73
16-Bit Timer4 .............................................................. 78
16-Bit Timer5 .............................................................. 78
32-Bit Timer2/3 ........................................................... 72
32-Bit Timer4/5 ........................................................... 77
2010 Microchip Technology Inc.
CAN Buffers and Protocol Engine ............................ 112
DCI Module............................................................... 122
Dedicated Port Structure ............................................ 53
DSP Engine ................................................................ 20
dsPIC30F3014............................................................ 11
dsPIC30F4013............................................................ 12
External Power-on Reset Circuit .............................. 153
I2C .............................................................................. 92
Input Capture Mode.................................................... 81
Oscillator System...................................................... 143
Output Compare Mode ............................................... 85
Reset System ........................................................... 151
Shared Port Structure................................................. 54
SPI............................................................................ 100
SPI Master/Slave Connection................................... 100
UART Receiver......................................................... 104
UART Transmitter..................................................... 103
BOR Characteristics ......................................................... 180
BOR. See Brown-out Reset.
Brown-out Reset
Timing Requirements ............................................... 187
C
C Compilers
MPLAB C18.............................................................. 168
CAN Module ..................................................................... 111
Baud Rate Setting .................................................... 116
CAN1 Register Map.................................................. 118
Frame Types ............................................................ 111
I/O Timing Requirements.......................................... 205
Message Reception.................................................. 114
Message Transmission............................................. 115
Modes of Operation .................................................. 113
Overview................................................................... 111
CLKOUT and I/O Timing
Requirements ........................................................... 185
Code Examples
Data EEPROM Block Erase ....................................... 50
Data EEPROM Block Write ........................................ 52
Data EEPROM Read.................................................. 49
Data EEPROM Word Erase ....................................... 50
Data EEPROM Word Write ........................................ 51
Erasing a Row of Program Memory ........................... 45
Initiating a Programming Sequence ........................... 46
Loading Write Latches ................................................ 46
Port Write/Read .......................................................... 54
Code Protection ................................................................ 141
Control Registers ................................................................ 44
NVMADR .................................................................... 44
NVMADRU ................................................................. 44
NVMCON.................................................................... 44
NVMKEY .................................................................... 44
Core Architecture
Overview..................................................................... 15
CPU Architecture Overview ................................................ 15
Customer Change Notification Service............................. 225
Customer Notification Service .......................................... 225
Customer Support............................................................. 225
D
Data Accumulators and Adder/Subtracter .......................... 21
Data Accumulators and Adder/Subtractor
Data Space Write Saturation ...................................... 23
Overflow and Saturation ............................................. 21
DS70138G-page 219
dsPIC30F3014/4013
Round Logic ................................................................ 22
Write-Back .................................................................. 22
Data Address Space ........................................................... 30
Alignment .................................................................... 32
Alignment (Figure) ...................................................... 32
Effect of Invalid Memory Accesses (Table)................. 32
MCU and DSP (MAC Class) Instructions Example..... 31
Memory Map ............................................................... 30
Near Data Space ........................................................ 33
Software Stack ............................................................ 33
Spaces ........................................................................ 32
Width ........................................................................... 32
Data Converter Interface (DCI) Module ............................ 121
Data EEPROM Memory ...................................................... 49
Erasing ........................................................................ 50
Erasing, Block ............................................................. 50
Erasing, Word ............................................................. 50
Protection Against Spurious Write .............................. 52
Reading....................................................................... 49
Write Verify ................................................................. 52
Writing ......................................................................... 51
Writing, Block .............................................................. 51
Writing, Word .............................................................. 51
DC Characteristics ............................................................ 172
BOR .......................................................................... 180
I/O Pin Input Specifications ....................................... 178
I/O Pin Output Specifications .................................... 178
Idle Current (IIDLE) .................................................... 175
LVDL ......................................................................... 179
Operating Current (IDD)............................................. 174
Power-Down Current (IPD) ........................................ 176
Program and EEPROM............................................. 180
Temperature and Voltage Specifications .................. 172
DCI Module
Bit Clock Generator................................................... 125
Buffer Alignment with Data Frames .......................... 127
Buffer Control ............................................................ 121
Buffer Data Alignment ............................................... 121
Buffer Length Control ................................................ 127
COFS Pin .................................................................. 121
CSCK Pin .................................................................. 121
CSDI Pin ................................................................... 121
CSDO Mode Bit ........................................................ 128
CSDO Pin ................................................................. 121
Data Justification Control Bit ..................................... 126
Device Frequencies for Common Codec CSCK Frequencies (Table) ....................................................... 125
Digital Loopback Mode ............................................. 128
Enable ....................................................................... 123
Frame Sync Generator ............................................. 123
Frame Sync Mode Control Bits ................................. 123
I/O Pins ..................................................................... 121
Interrupts ................................................................... 128
Introduction ............................................................... 121
Master Frame Sync Operation .................................. 123
Operation .................................................................. 123
Operation During CPU Idle Mode ............................. 128
Operation During CPU Sleep Mode .......................... 128
Receive Slot Enable Bits........................................... 126
Receive Status Bits ................................................... 127
Register Map............................................................. 130
Sample Clock Edge Control Bit................................. 126
Slave Frame Sync Operation .................................... 124
Slot Enable Bits Operation with Frame Sync ............ 126
Slot Status Bits.......................................................... 128
DS70138G-page 220
Synchronous Data Transfers .................................... 126
Timing Requirements
AC-Link Mode................................................... 195
Multichannel, I2S Modes................................... 193
Transmit Slot Enable Bits ......................................... 126
Transmit Status Bits.................................................. 127
Transmit/Receive Shift Register ............................... 121
Underflow Mode Control Bit...................................... 128
Word-Size Selection Bits .......................................... 123
Development Support ....................................................... 167
Device Configuration
Register Map ............................................................ 158
Device Configuration Registers
FBORPOR ................................................................ 156
FGS .......................................................................... 156
FOSC........................................................................ 156
FWDT ....................................................................... 156
Device Overview................................................................. 11
Disabling the UART .......................................................... 105
Divide Support .................................................................... 18
Instructions (Table) ..................................................... 18
DSP Engine ........................................................................ 19
Multiplier ..................................................................... 21
Dual Output Compare Match Mode .................................... 86
Continuous Pulse Mode.............................................. 86
Single Pulse Mode...................................................... 86
E
Electrical Characteristics .................................................. 171
AC............................................................................. 180
DC ............................................................................ 172
Enabling and Setting Up UART
Alternate I/O ............................................................. 105
Enabling and Setting up UART
Setting up Data, Parity and Stop Bit Selections........ 105
Enabling the UART ........................................................... 105
Equations
ADC Conversion Clock ............................................. 133
Baud Rate................................................................. 107
Bit Clock Frequency.................................................. 125
COFSG Period.......................................................... 123
Serial Clock Rate ........................................................ 96
Time Quantum for Clock Generation ........................ 117
Errata .................................................................................... 9
Exception Sequence
Trap Sources .............................................................. 62
External Clock Timing Requirements ............................... 182
Type A Timer ............................................................ 188
Type B Timer ............................................................ 189
Type C Timer ............................................................ 189
External Interrupt Requests ................................................ 64
F
Fast Context Saving ........................................................... 64
Flash Program Memory ...................................................... 43
I
I/0 Ports
Register Map .............................................................. 55
I/O Pin Specifications
Input.......................................................................... 178
Output ....................................................................... 178
I/O Ports.............................................................................. 53
Parallel (PIO) .............................................................. 53
I2C 10-Bit Slave Mode Operation ....................................... 93
Reception ................................................................... 94
2010 Microchip Technology Inc.
dsPIC30F3014/4013
Transmission............................................................... 93
I2C 7-Bit Slave Mode Operation.......................................... 93
Reception.................................................................... 93
Transmission............................................................... 93
I2C Master Mode Operation ................................................ 95
Baud Rate Generator.................................................. 96
Clock Arbitration.......................................................... 96
Multi-Master Communication,
Bus Collision and Bus Arbitration ....................... 96
Reception.................................................................... 96
Transmission............................................................... 95
I2C Master Mode Support ................................................... 95
I2C Module .......................................................................... 91
Addresses ................................................................... 93
Bus Data Timing Requirements
Master Mode ..................................................... 201
Slave Mode ....................................................... 204
General Call Address Support .................................... 95
Interrupts..................................................................... 95
IPMI Support ............................................................... 95
Operating Function Description .................................. 91
Operation During CPU Sleep and Idle Modes ............ 96
Pin Configuration ........................................................ 91
Programmer’s Model................................................... 91
Register Map............................................................... 97
Registers..................................................................... 91
Slope Control .............................................................. 95
Software Controlled Clock Stretching (STREN = 1).... 94
Various Modes ............................................................ 91
I2S Mode Operation .......................................................... 129
Data Justification....................................................... 129
Frame and Data Word Length Selection................... 129
Idle Current (IIDLE) ............................................................ 175
In-Circuit Serial Programming (ICSP) ......................... 43, 141
Input Capture Module ......................................................... 81
Interrupts..................................................................... 82
Register Map............................................................... 83
Input Capture Operation During Sleep and Idle Modes ...... 82
CPU Idle Mode............................................................ 82
CPU Sleep Mode ........................................................ 82
Input Capture Timing Requirements ................................. 190
Input Change Notification Module ....................................... 56
Register Map............................................................... 57
Instruction Addressing Modes............................................. 37
File Register Instructions ............................................ 37
Fundamental Modes Supported.................................. 37
MAC Instructions......................................................... 38
MCU Instructions ........................................................ 37
Move and Accumulator Instructions............................ 38
Other Instructions........................................................ 38
Instruction Set
Overview ................................................................... 162
Summary................................................................... 159
Internal Clock Timing Examples ....................................... 183
Internet Address................................................................ 225
Interrupt Controller
Register Map............................................................... 66
Interrupt Priority .................................................................. 60
Traps........................................................................... 62
Interrupt Sequence ............................................................. 63
Interrupt Stack Frame ................................................. 63
Interrupts ............................................................................. 59
L
Load Conditions ................................................................ 181
Low-Voltage Detect (LVD) ................................................ 155
2010 Microchip Technology Inc.
LVDL Characteristics ........................................................ 179
M
Memory Organization ......................................................... 25
Core Register Map ..................................................... 33
Microchip Internet Web Site.............................................. 225
Modes of Operation
Disable...................................................................... 113
Initialization............................................................... 113
Listen All Messages.................................................. 113
Listen Only................................................................ 113
Loopback .................................................................. 113
Normal Operation ..................................................... 113
Modulo Addressing ............................................................. 38
Applicability................................................................. 40
Incrementing Buffer Operation Example .................... 39
Start and End Address ............................................... 39
W Address Register Selection.................................... 39
MPLAB ASM30 Assembler, Linker, Librarian ................... 168
MPLAB Integrated Development Environment Software.. 167
MPLAB PM3 Device Programmer .................................... 170
MPLAB REAL ICE In-Circuit Emulator System ................ 169
MPLINK Object Linker/MPLIB Object Librarian ................ 168
N
NVM
Register Map .............................................................. 47
O
Operating Current (IDD) .................................................... 174
Operating Frequency vs Voltage
dsPIC30FXXXX-20 (Extended) ................................ 172
Oscillator
Configurations .......................................................... 144
Fail-Safe Clock Monitor .................................... 146
Fast RC (FRC).................................................. 145
Initial Clock Source Selection ........................... 144
Low-Power RC (LPRC) .................................... 145
LP Oscillator Control......................................... 145
Phase Locked Loop (PLL) ................................ 145
Start-up Timer (OST)........................................ 144
Control Registers...................................................... 147
Operating Modes (Table).......................................... 142
System Overview...................................................... 141
Oscillator Selection ........................................................... 141
Oscillator Start-up Timer
Timing Requirements ............................................... 187
Output Compare Interrupts ................................................. 88
Output Compare Module .................................................... 85
Register Map dsPIC30F3014 ..................................... 89
Register Map dsPIC30F4013 ..................................... 89
Timing Requirements ............................................... 190
Output Compare Operation During CPU Idle Mode ........... 88
Output Compare Sleep Mode Operation ............................ 88
P
Packaging Information ...................................................... 211
Marking..................................................................... 211
Peripheral Module Disable (PMD) Registers .................... 157
Pinout Descriptions............................................................. 13
POR. See Power-on Reset.
Power Saving Modes
Sleep and Idle........................................................... 141
Power-Down Current (IPD)................................................ 176
Power-Saving Modes........................................................ 155
Idle............................................................................ 156
DS70138G-page 221
dsPIC30F3014/4013
Sleep ......................................................................... 155
Power-up Timer
Timing Requirements ................................................ 187
Program Address Space ..................................................... 25
Construction ................................................................ 26
Data Access from Program Memory
Using Program Space Visibility........................... 28
Data Access From Program Memory
Using Table Instructions ..................................... 27
Data Access from, Address Generation...................... 26
Data Space Window into Operation ............................ 29
Data Table Access (lsw) ............................................. 27
Data Table Access (MSB)........................................... 28
dsPIC30F3014 Memory Map ...................................... 25
dsPIC30F4013 Memory Map ...................................... 25
Table Instructions
TBLRDH.............................................................. 27
TBLRDL .............................................................. 27
TBLWTH ............................................................. 27
TBLWTL.............................................................. 27
Program and EEPROM Characteristics ............................ 180
Program Counter................................................................. 16
Programmable................................................................... 141
Programmer’s Model........................................................... 16
Diagram ...................................................................... 17
Programming Operations .................................................... 45
Algorithm for Program Flash ....................................... 45
Erasing a Row of Program Memory ............................ 45
Initiating the Programming Sequence ......................... 46
Loading Write Latches ................................................ 46
Protection Against Accidental Writes to OSCCON ........... 146
R
Reader Response ............................................................. 226
Registers
OSCCON (Oscillator Control) ................................... 147
OSCTUN (Oscillator Tuning) .................................... 149
Reset......................................................................... 141, 151
BOR, Programmable................................................. 153
Brown-out Reset (BOR) ............................................ 141
Oscillator Start-up Timer (OST) ................................ 141
POR
Operating without FSCM and PWRT ................ 153
With Long Crystal Start-up Time....................... 153
POR (Power-on Reset) ............................................. 151
Power-on Reset (POR) ............................................. 141
Power-up Timer (PWRT) .......................................... 141
Reset Sequence.................................................................. 61
Reset Sources ............................................................ 61
Reset Sources
Brown-out Reset (BOR) .............................................. 61
Illegal Instruction Trap................................................. 61
Trap Lockout ............................................................... 61
Uninitialized W Register Trap ..................................... 61
Watchdog Time-out..................................................... 61
Reset Timing Requirements.............................................. 187
Revision History ................................................................ 217
Run-Time Self-Programming (RTSP) ................................. 43
S
Simple Capture Event Mode ............................................... 81
Buffer Operation.......................................................... 82
Hall Sensor Mode ....................................................... 82
Prescaler ..................................................................... 81
Timer2 and Timer3 Selection Mode ............................ 82
Simple OCx/PWM Mode Timing Requirements ................ 191
DS70138G-page 222
Simple Output Compare Match Mode ................................ 86
Simple PWM Mode ............................................................. 86
Input Pin Fault Protection ........................................... 86
Period ......................................................................... 87
Software Simulator (MPLAB SIM) .................................... 169
Software Stack Pointer, Frame Pointer .............................. 16
CALL Stack Frame ..................................................... 33
SPI Module ......................................................................... 99
Framed SPI Support ................................................. 100
Operating Function Description .................................. 99
Operation During CPU Idle Mode ............................. 101
Operation During CPU Sleep Mode.......................... 101
SDOx Disable ............................................................. 99
Slave Select Synchronization ................................... 101
SPI1 Register Map.................................................... 102
Timing Requirements
Master Mode (CKE = 0).................................... 196
Master Mode (CKE = 1).................................... 197
Slave Mode (CKE = 0)...................................... 198
Slave Mode (CKE = 1)...................................... 200
Word and Byte Communication .................................. 99
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 1 ...................................... 154
Status Bits, Their Significance and the Initialization Condition
for RCON Register, Case 2 ...................................... 154
STATUS Register ............................................................... 16
Symbols Used in Opcode Descriptions ............................ 160
System Integration............................................................ 141
Register Map ............................................................ 158
T
Table Instruction Operation Summary ................................ 43
Temperature and Voltage Specifications
AC............................................................................. 181
DC ............................................................................ 172
Timer1 Module.................................................................... 67
16-Bit Asynchronous Counter Mode........................... 67
16-Bit Synchronous Counter Mode............................. 67
16-Bit Timer Mode ...................................................... 67
Gate Operation ........................................................... 68
Interrupt ...................................................................... 68
Operation During Sleep Mode .................................... 68
Prescaler .................................................................... 68
Real-Time Clock ......................................................... 68
Interrupts ............................................................ 68
Oscillator Operation............................................ 68
Register Map .............................................................. 69
Timer2 and Timer3 Selection Mode.................................... 85
Timer2/3 Module................................................................. 71
16-Bit Timer Mode ...................................................... 71
32-Bit Synchronous Counter Mode............................. 71
32-Bit Timer Mode ...................................................... 71
ADC Event Trigger...................................................... 74
Gate Operation ........................................................... 74
Interrupt ...................................................................... 74
Operation During Sleep Mode .................................... 74
Register Map .............................................................. 75
Timer Prescaler .......................................................... 74
Timer4/5 Module................................................................. 77
Register Map .............................................................. 79
Timing Diagrams
A/D Conversion
Low-Speed (ASAM = 0, SSRC = 000).............. 208
Band Gap Start-up Time........................................... 187
Brown-out Reset Characteristics .............................. 179
CAN Bit ..................................................................... 116
2010 Microchip Technology Inc.
dsPIC30F3014/4013
CAN Module I/O........................................................ 205
CLKOUT and I/O....................................................... 185
DCI Module
AC-Link Mode ................................................... 194
Multichannel, I2S Modes ................................... 192
External Clock........................................................... 181
Frame Sync, AC-Link Start-Of-Frame....................... 124
Frame Sync, Multichannel Mode .............................. 124
I2C Bus Data
Master Mode ..................................................... 201
Slave Mode ....................................................... 203
I2C Bus Start/Stop Bits
Master Mode ..................................................... 201
Slave Mode ....................................................... 203
I2S Interface Frame Sync.......................................... 124
Input Capture (CAPx)................................................ 190
Low-Voltage Detect................................................... 178
OCx/PWM Module .................................................... 191
Oscillator Start-up Timer ........................................... 186
Output Compare Module........................................... 190
Power-up Timer ........................................................ 186
PWM Output ............................................................... 87
Reset......................................................................... 186
SPI Module
Master Mode (CKE = 0) .................................... 195
Master Mode (CKE = 1) .................................... 196
Slave Mode (CKE = 0) ...................................... 197
Slave Mode (CKE = 1) ...................................... 199
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1...................... 152
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2...................... 152
Time-out Sequence on Power-up
(MCLR Tied to VDD).......................................... 152
Type A, B and C Timer External Clock ..................... 188
Watchdog Timer........................................................ 186
Timing Diagrams and Specifications
DC Characteristics - Internal RC Accuracy............... 183
Timing Diagrams.See Timing Characteristics
Timing Requirements
A/D Conversion
Low-Speed........................................................ 209
Band Gap Start-up Time ........................................... 187
Brown-out Reset ....................................................... 187
CAN Module I/O........................................................ 205
CLKOUT and I/O....................................................... 185
DCI Module
AC-Link Mode ................................................... 195
Multichannel, I2S Modes ................................... 193
External Clock........................................................... 182
I2C Bus Data (Master Mode)..................................... 201
I2C Bus Data (Slave Mode)....................................... 204
Input Capture ............................................................ 190
Oscillator Start-up Timer ........................................... 187
Output Compare Module........................................... 190
Power-up Timer ........................................................ 187
Reset......................................................................... 187
Simple OCx/PWM Mode ........................................... 191
SPI Module
Master Mode (CKE = 0) .................................... 196
Master Mode (CKE = 1) .................................... 197
Slave Mode (CKE = 0) ...................................... 198
Slave Mode (CKE = 1) ...................................... 200
Type A Timer External Clock .................................... 188
Type B Timer External Clock .................................... 189
2010 Microchip Technology Inc.
Type C Timer External Clock.................................... 189
Watchdog Timer ....................................................... 187
Trap Vectors ....................................................................... 63
U
UART Module
Address Detect Mode ............................................... 107
Auto-Baud Support ................................................... 108
Baud Rate Generator ............................................... 107
Enabling and Setting Up........................................... 105
Framing Error (FERR) .............................................. 107
Idle Status................................................................. 107
Loopback Mode ........................................................ 107
Operation During CPU Sleep and Idle Modes.......... 108
Overview................................................................... 103
Parity Error (PERR) .................................................. 107
Receive Break .......................................................... 107
Receive Buffer (UxRXB)........................................... 106
Receive Buffer Overrun Error (OERR Bit) ................ 106
Receive Interrupt ...................................................... 106
Receiving Data ......................................................... 106
Receiving in 8-Bit or 9-Bit Data Mode ...................... 106
Reception Error Handling ......................................... 106
Transmit Break ......................................................... 106
Transmit Buffer (UxTXB) .......................................... 105
Transmit Interrupt ..................................................... 106
Transmitting Data ..................................................... 105
Transmitting in 8-Bit Data Mode ............................... 105
Transmitting in 9-Bit Data Mode ............................... 105
UART1 Register Map ............................................... 109
UART2 Register Map ............................................... 109
UART Operation
Idle Mode.................................................................. 108
Sleep Mode .............................................................. 108
Unit ID Locations .............................................................. 141
Universal Asynchronous Receiver Transmitter
(UART) Module......................................................... 103
W
Wake-up from Sleep ......................................................... 141
Wake-up from Sleep and Idle ............................................. 64
Watchdog Timer
Timing Requirements ............................................... 187
Watchdog Timer (WDT)............................................ 141, 155
Enabling and Disabling............................................. 155
Operation.................................................................. 155
WWW Address ................................................................. 225
WWW, On-Line Support ....................................................... 9
DS70138G-page 223
dsPIC30F3014/4013
NOTES:
DS70138G-page 224
2010 Microchip Technology Inc.
dsPIC30F3014/4013
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2010 Microchip Technology Inc.
DS70138G-page 225
dsPIC30F3014/4013
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Device: dsPIC30F3014/4013
Literature Number: DS70138G
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70138G-page 226
2010 Microchip Technology Inc.
dsPIC30F3014/4013
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
d s P I C 3 0 F 4 0 1 3 AT - 3 0 I / P T- E S
Custom ID (3 digits) or
Engineering Sample (ES)
Trademark
Architecture
Package
P = 40-pin PDIP
PT = 44-pin TQFP (10x10)
ML = 44-pin QFN (8x8)
S = Die (Waffle Pack)
W = Die (Wafers)
Flash
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Temperature
I = Industrial -40°C to +85°C
E = Extended High Temp -40°C to +125°C
Device ID
Speed
20 = 20 MIPS
30 = 30 MIPS
T = Tape and Reel
A,B,C… = Revision Level
Example:
dsPIC30F4013AT-30I/PT = 30 MIPS, Industrial temp., TQFP package, Rev. A
2010 Microchip Technology Inc.
DS70138G-page 227
Worldwide Sales and Service
AMERICAS
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EUROPE
Corporate Office
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Tel: 480-792-7200
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Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Suites 3707-14, 37th Floor
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Tel: 852-2401-1200
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Mississauga, Ontario,
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Tel: 905-673-0699
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Australia - Sydney
Tel: 61-2-9868-6733
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Tel: 86-10-8528-2100
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Tel: 86-28-8665-5511
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Tel: 886-3-6578-300
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Tel: 886-2-2500-6610
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UK - Wokingham
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Tel: 86-592-2388138
Fax: 86-592-2388130
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Tel: 86-756-3210040
Fax: 86-756-3210049
08/04/10
DS70138G-page 228
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