dsPIC30F4011/4012
Data Sheet
High-Performance,
16-Bit Digital Signal Controllers
© 2010 Microchip Technology Inc.
DS70135G
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
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hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-713-2
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70135G-page 2
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
High-Performance, 16-Bit Digital Signal Controllers
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
High-Performance, Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
with flexible addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• 48 Kbytes on-chip Flash program space
(16K instruction words)
• 2 Kbytes of on-chip data RAM
• 1 Kbyte of nonvolatile data EEPROM
• Up to 30 MIPS operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• 30 interrupt sources:
- Three external interrupt sources
- Eight user-selectable priority levels for each
interrupt source
- Four processor trap sources
• 16 x 16-bit working register array
DSP Engine Features:
•
•
•
•
Dual data fetch
Accumulator write-back for DSP operations
Modulo and Bit-Reversed Addressing modes
Two, 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware
fractional/integer multiplier
• All DSP instructions are single cycle
• ±16-bit, single-cycle shift
© 2010 Microchip Technology Inc.
Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler:
- Five 16-bit timers/counters; optionally pair
16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• 3-wire SPI modules (supports 4 Frame modes)
• I2C™ module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Two UART modules with FIFO Buffers
• CAN module, 2.0B compliant
Motor Control PWM Module Features:
• Six PWM output channels:
- Complementary or Independent Output
modes
- Edge and Center-Aligned modes
• Three duty cycle generators
• Dedicated time base
• Programmable output polarity
• Dead-time control for Complementary mode
• Manual output control
• Trigger for A/D conversions
Quadrature Encoder Interface Module
Features:
•
•
•
•
•
•
•
Phase A, Phase B and Index Pulse input
16-bit up/down position counter
Count direction status
Position Measurement (x2 and x4) mode
Programmable digital noise filters on inputs
Alternate 16-bit Timer/Counter mode
Interrupt on position counter rollover/underflow
Analog Features:
• 10-bit Analog-to-Digital Converter (ADC) with
four Sample and Holde (S&H) inputs:
- 1 Msps conversion rate
- Nine input channels
- Conversion available during Sleep and Idle
• Programmable Brown-out Reset
DS70135G-page 3
dsPIC30F4011/4012
Special Digital Signal Controller
Features:
CMOS Technology:
•
•
•
•
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip,
low-power RC oscillator for reliable operation
• Fail-Safe Clock Monitor operation detects clock
failure and switches to on-chip, low-power
RC oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes:
- Sleep, Idle and Alternate Clock modes
Low-power, high-speed Flash technology
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low-power consumption
dsPIC30F Motor Control and Power Conversion Family
DS70135G-page 4
I C™
CAN
dsPIC30F4011 40/44
SPI
28
2
dsPIC30F4012
Motor
Output
Program
10-bit A/D Quad
SRAM EEPROM Timer Input
Comp/Std Control
Pins Mem. Bytes/
1 Msps
Enc
Bytes
Bytes
16-bit Cap
PWM
PWM
Instructions
UART
Device
48K/16K
2048
1024
5
4
2
6 ch
6 ch
Yes
1
1
1
1
48K/16K
2048
1024
5
4
4
6 ch
9 ch
Yes
2
1
1
1
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
Pin Diagrams
40-Pin PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
dsPIC30F4011
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
FLTA/INT0/RE8
EMUD2/OC2/IC2/INT2/RD1
OC4/RD3
VSS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
C1RX/RF0
C1TX/RF1
U2RX/CN17/RF4
U2TX/CN18/RF5
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
44
43
42
41
40
39
38
37
36
35
34
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
VSS
OC4/RD3
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
NC
44-Pin TQFP
dsPIC30F4011
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VDD
AN8/RB8
AN7/RB7
AN6/OCFA/RB6
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
NC
NC
PWM1H/RE1
PWM1L/RE0
AVSS
AVDD
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
PGC/EMUC/U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
C1TX/RF1
C1RX/RF0
VSS
VDD
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
© 2010 Microchip Technology Inc.
DS70135G-page 5
dsPIC30F4011/4012
Pin Diagrams (Continued)
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F4011
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VSS
VDD
VDD
AN8/RB8
AN7/RB7
AN6/OCFA/RB6
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
PWM2L/RE2
NC
PWM1H/RE1
PWM1L/RE0
AVSS
AVDD
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
12
13
14
15
16
17
18
19
20
21
22
PGC/EMUC/U1RX/SDI1/SDA/RF2
U2TX/CN18/RF5
U2RX/CN17/RF4
C1TX/RF1
C1RX/RF0
VSS
VDD
VDD
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
39
38
37
36
35
34
44
43
42
41
40
PGD/EMUD/U1TX/SDO1/SCL/RF3
SCK1/RF6
EMUC2/OC1/IC1/INT1/RD0
OC3/RD2
VDD
VSS
OC4/RD3
EMUD2/OC2/IC2/INT2/RD1
FLTA/INT0/RE8
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
44-Pin QFN(1)
Note
1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70135G-page 6
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
Pin Diagrams (Continued)
28-Pin SPDIP and SOIC
dsPIC30F4012
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
VSS
OSC1/CLKI
OSC2/CLKO/RC15
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
VDD
EMUD2/OC2/IC2/INT2/RD1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
VDD
VSS
PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2
PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
FLTA/INT0/SCK1/OCFA/RE8
EMUC2/OC1/IC1/INT1/RD0
44
43
42
41
40
39
38
37
36
35
34
PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
FLTA/INT0/SCK1/OCFA/RE8
EMUC2/OC1/IC1/INT1/RD0
NC
VDD
VSS
NC
EMUD2/OC2/IC2/INT2/RD1
VDD
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
44-Pin QFN(1)
1
2
3
4
5
6
7
8
9
10
11
dsPIC30F4012
33
32
31
30
29
28
27
26
25
24
23
OSC2/CLKO/RC15
OSC1/CLKI
VSS
VSS
VDD
VDD
NC
NC
NC
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
PWM2L/RE2
NC
PWM1H/RE1
PWM1L/RE0
AVSS
AVDD
MCLR
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
12
13
14
15
16
17
18
19
20
21
22
PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2
NC
NC
NC
NC
VSS
VDD
VDD
PWM3H/RE5
PWM3L/RE4
PWM2H/RE3
Note
1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
© 2010 Microchip Technology Inc.
DS70135G-page 7
dsPIC30F4011/4012
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 17
3.0 Memory Organization ................................................................................................................................................................. 25
4.0 Address Generator Units ............................................................................................................................................................ 37
5.0 Interrupts .................................................................................................................................................................................... 43
6.0 Flash Program Memory .............................................................................................................................................................. 49
7.0 Data EEPROM Memory ............................................................................................................................................................. 55
8.0 I/O Ports ..................................................................................................................................................................................... 61
9.0 Timer1 Module ........................................................................................................................................................................... 67
10.0 Timer2/3 Module ........................................................................................................................................................................ 71
11.0 Timer4/5 Module ....................................................................................................................................................................... 77
12.0 Input Capture Module................................................................................................................................................................. 81
13.0 Output Compare Module ............................................................................................................................................................ 85
14.0 Quadrature Encoder Interface (QEI) Module ............................................................................................................................. 91
15.0 Motor Control PWM Module ....................................................................................................................................................... 97
16.0 SPI™ Module ........................................................................................................................................................................... 109
17.0 I2C™ Module ........................................................................................................................................................................... 113
18.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 121
19.0 CAN Module ............................................................................................................................................................................. 129
20.0 10-bit, High-Speed Analog-to-Digital Converter (ADC) Module ............................................................................................... 139
21.0 System Integration ................................................................................................................................................................... 151
22.0 Instruction Set Summary .......................................................................................................................................................... 165
23.0 Development Support............................................................................................................................................................... 173
24.0 Electrical Characteristics .......................................................................................................................................................... 177
25.0 Packaging Information.............................................................................................................................................................. 219
The Microchip Web Site ..................................................................................................................................................................... 235
Customer Change Notification Service .............................................................................................................................................. 235
Customer Support .............................................................................................................................................................................. 235
Reader Response .............................................................................................................................................................................. 236
Product Identification System............................................................................................................................................................. 237
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70135G-page 8
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
This document contains device-specific information for
the dsPIC30F4011/4012 devices. The dsPIC30F
devices contain extensive Digital Signal Processor
(DSP) functionality within a high-performance, 16-bit
microcontroller (MCU) architecture. Figure 1-1 and
Figure 1-2 illustrate device block diagrams for the
dsPIC30F4011 and dsPIC30F4012 devices.
© 2010 Microchip Technology Inc.
DS70135G-page 9
dsPIC30F4011/4012
FIGURE 1-1:
dsPIC30F4011 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
16
Data Latch
Y Data
RAM
(1 Kbyte)
Address
Latch
16
24
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Address Latch
Program Memory
(48 Kbytes)
Data EEPROM
(1 Kbyte)
16
Data Latch
X Data
RAM
(1 Kbyte)
Address
Latch
16
16
X RAGU
X WAGU
16
24
16
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
Effective Address
16
Data Latch
PORTB
ROM Latch
16
24
IR
16 x 16
W Reg Array
Decode
Instruction
Decode and
Control
Power-up
Timer
Timing
Generation
PORTC
16 16
Control Signals
to Various
Blocks
OSC1/CLKI
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
16
16
DSP
Engine
Divide
Unit
EMUC2/OC1/IC1/INT1/RD0
EMUD2/OC2/IC2/INT2/RD1
OC3/RD2
OC4/RD3
Oscillator
Start-up Timer
ALU
POR/BOR
Reset
MCLR
PORTD
16
VDD, VSS
AVDD, AVSS
16
Watchdog
Timer
CAN
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
SPI1
Timers
QEI
Motor Control
PWM
UART1,
UART2
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
FLTA/INT0/RE8
PORTE
C1RX/RF0
C1TX/RF1
PGC/EMUC/U1RX/SDI1/SDA/RF2
PGD/EMUD/U1TX/SDO1/SCL/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
SCK1/RF6
PORTF
DS70135G-page 10
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 1-2:
dsPIC30F4012 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
Data Latch
Y Data
RAM
(1 Kbyte)
Address
Latch
16
24
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Address Latch
Program Memory
(48 Kbytes)
Data EEPROM
(1 Kbyte)
16
16
16
X RAGU
X WAGU
16
24
16
Data Latch
X Data
RAM
(1 Kbyte)
Address
Latch
EMUD3/AN0/VREF+/CN2/RB0
EMUC3/AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
PORTB
Effective Address
16
Data Latch
ROM Latch
16
24
IR
16 x 16
W Reg Array
Decode
Instruction
Decode and
Control
Power-up
Timer
Timing
Generation
PORTC
16 16
Control Signals
to Various
Blocks
OSC1/CLKI
EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13
EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14
OSC2/CLKO/RC15
16
16
DSP
Engine
Divide
Unit
EMUC2/OC1/IC1/INT1RD0
EMUD2/OC2/IC2/INT2/RD1
Oscillator
Start-up Timer
ALU
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
PORTD
16
16
Watchdog
Timer
CAN
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
SPI1,
SPI2
Timers
QEI
Motor Control
PWM
UART1,
UART2
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
FLTA/INT0/SCK1/OCFA/RE8
PORTE
PGC/EMUC/U1RX/SDI1/SDA/C1RX/RF2
PGD/EMUD/U1TX/SDO1/SCL/C1TX/RF3
PORTF
© 2010 Microchip Technology Inc.
DS70135G-page 11
dsPIC30F4011/4012
Table 1-1 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1:
dsPIC30F4011 I/O PIN DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN8
I
Analog
Analog input channels. AN0 and AN1 are also used for device programming
data and clock inputs, respectively.
Pin Name
Description
AVDD
P
P
Positive supply for analog module. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog module. This pin must be connected at all times.
CLKI
CLKO
I
O
CN0-CN7
CN17-CN18
I
ST
Input change notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
C1RX
C1TX
I
O
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1, IC2, IC7,
IC8
I
ST
Capture inputs 1, 2, 7 and 8.
INDX
QEA
I
I
ST
ST
QEB
I
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase B input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
FLTA
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
I
O
O
O
O
O
O
ST
—
—
—
—
—
—
PWM Fault A input.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM3 low output.
PWM3 high output.
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA
OC1-OC4
I
O
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare outputs 1 through 4.
Legend: CMOS =
ST
=
I
=
DS70135G-page 12
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog =
O
=
P
=
Analog input
Output
Power
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 1-1:
Pin Name
dsPIC30F4011 I/O PIN DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
Description
OSC1
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
OSC2
I/O
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
RB0-RB8
I/O
ST
PORTB is a bidirectional I/O port.
RC13-RC15
I/O
ST
PORTC is a bidirectional I/O port.
RD0-RD3
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE5,
RE8
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF6
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
—
ST
—
ST
—
UART1 receive.
UART1 transmit.
UART1 alternate receive.
UART1 alternate transmit.
UART2 receive.
UART2 transmit.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
Ground reference for logic and I/O pins.
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Legend: CMOS =
ST
=
I
=
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
© 2010 Microchip Technology Inc.
Analog =
O
=
P
=
Analog input
Output
Power
DS70135G-page 13
dsPIC30F4011/4012
Table 1-2 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-2:
dsPIC30F4012 I/O PIN DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN5
I
Analog
Analog input channels. AN0 and AN1 are also used for device programming
data and clock inputs, respectively.
Pin Name
Description
AVDD
P
P
Positive supply for analog module. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog module. This pin must be connected at all times.
CLKI
CLKO
I
O
CN0-CN7
I
ST
Input change notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
C1RX
C1TX
I
O
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1, IC2, IC7,
IC8
I
ST
Capture inputs 1, 2, 7 and 8.
INDX
QEA
I
I
ST
ST
QEB
I
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase B input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
INT0
INT1
INT2
I
I
I
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
FLTA
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
I
O
O
O
O
O
O
ST
—
—
—
—
—
—
PWM Fault A input.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM3 low output.
PWM3 high output.
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA
OC1, OC2
I
O
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare outputs 1 and 2.
Legend: CMOS =
ST
=
I
=
DS70135G-page 14
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog =
O
=
P
=
Analog input
Output
Power
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 1-2:
Pin Name
dsPIC30F4012 I/O PIN DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
Description
OSC1
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
OSC2
I/O
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
RB0-RB5
I/O
ST
PORTB is a bidirectional I/O port.
RC13-RC15
I/O
ST
PORTC is a bidirectional I/O port.
RD0-RD1
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE5,
RE8
I/O
ST
PORTE is a bidirectional I/O port.
RF2-RF3
I/O
ST
PORTF is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
T1CK
T2CK
I
I
ST
ST
Timer1 external clock input.
Timer2 external clock input.
U1RX
U1TX
U1ARX
U1ATX
I
O
I
O
ST
—
ST
—
UART1 receive.
UART1 transmit.
UART1 alternate receive.
UART1 alternate transmit.
VDD
P
—
Positive supply for logic and I/O pins.
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
VSS
P
—
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Legend: CMOS =
ST
=
I
=
Ground reference for logic and I/O pins.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
© 2010 Microchip Technology Inc.
Analog =
O
=
P
=
Analog input
Output
Power
DS70135G-page 15
dsPIC30F4011/4012
NOTES:
DS70135G-page 16
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
2.0
Note:
2.1
CPU ARCHITECTURE
OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are
supported using the DO and REPEAT instructions, both
of which are interruptible at any point.
The working register array consists of 16x16-bit
registers, each of which can act as data, address or offset registers. One working register (W15) operates as
a software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split into
two blocks, referred to as X and Y data memory. Each
block has its own independent Address Generation Unit
(AGU). Most instructions operate solely through the X
memory, AGU, which provides the appearance of a single, unified data space. The Multiply-Accumulate (MAC)
class of dual source DSP instructions operate through
both the X and Y AGUs, splitting the data address space
into two parts (see Section 3.2 “Data Address
Space”). The X and Y data space boundary is devicespecific and cannot be altered by the user. Each data
word consists of 2 bytes, and most instructions can
address data either as words or bytes.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can be
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined
by the 8-bit Program Space Visibility Page (PSVPAG) register. This lets any instruction access program space as if it were data space, with a
limitation that the access requires an additional
cycle. Moreover, only the lower 16 bits of each
instruction word can be accessed using this
method.
© 2010 Microchip Technology Inc.
• SWWLinear indirect access of 32K word pages
within program space is also possible, using any
working register via table read and write instructions. Table read and write instructions can be
used to access all 24 bits of an instruction word.
Overhead-free circular buffers (Modulo Addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing on
destination effective addresses, to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 “Address Generator Units” for
details on Modulo and Bit-Reversed Addressing.
The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed, 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumulator, or any working register, can be shifted up to 16 bits
right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and is linear for all others. This has been
achieved in a transparent and flexible manner by
dedicating certain working registers to each address
space for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single-stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution in order
to maximize available execution time. Most instructions
execute in a single cycle with certain exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
DS70135G-page 17
dsPIC30F4011/4012
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start and popped on loop end.
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte wide data memory space accesses.
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC Digital Signal Controllers contain a software
stack. W15 is the dedicated software Stack Pointer
(SP) and is automatically modified by exception processing and subroutine calls and returns. However,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies the
reading, writing and manipulation of the Stack Pointer
(e.g., creating stack frames).
Note:
In order to protect against misaligned
stack accesses, W15 is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS register (SR),
the Least Significant Byte of which is referred to as the
SR Low Byte (SRL) and the Most Significant Byte as the
SR High Byte (SRH). See Figure 2-1 for SR layout.
SRL contains all the DSP ALU operation Status flags
(including the Z bit), as well as the CPU Interrupt Priority Level Status bits, IPL, and the Repeat Active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the SR register contains the DSP
Adder/Subtracter Status bits, the DO Loop Active bit
(DA) and the Digit Carry (DC) Status bit.
2.2.3
PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear; therefore, the PC can address up to 4M
instruction words.
DS70135G-page 18
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 2-1:
dsPIC30F4011/4012 PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
ACCA
DSP
Accumulators
ACCB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
Data Table Page Address
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
© 2010 Microchip Technology Inc.
DC IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70135G-page 19
dsPIC30F4011/4012
2.3
Divide Support
The dsPIC DSCs feature a 16/16-bit signed fractional
divide operation, as well as 32/16-bit and 16/16-bit
signed and unsigned integer divide operations, in the
form of single instruction iterative divides. The following
instructions and data sizes are supported:
1.
2.
3.
4.
5.
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.s – 16/16 signed divide
DIV.u – 16/16 unsigned divide
TABLE 2-1:
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value and it must, therefore, be explicitly and
correctly specified in the REPEAT instruction, as shown in
Table 2-1 (REPEAT executes the target instruction
{operand value + 1} times). The REPEAT loop count must
be set up for 18 iterations of the DIV/DIVF instruction.
Thus, a complete divide operation requires 19 cycles.
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
DIVIDE INSTRUCTIONS
Instruction
Function
DIVF
Signed fractional divide: Wm/Wn →W0; Rem →W1
DIV.sd
Signed divide: (Wm + 1:Wm)/Wn →W0; Rem →W1
DIV.s
Signed divide: Wm/Wn →W0; Rem →W1
DIV.ud
Unsigned divide: (Wm + 1:Wm)/Wn →W0; Rem →W1
DIV.u
Unsigned divide: Wm/Wn →W0; Rem →W1
2.4
DSP Engine
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUB and NEG.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2:
Instruction
DSP INSTRUCTION
SUMMARY
Algebraic Operation
CLR
A=0
ED
A = (x – y)2
EDAC
MAC
MOVSAC
MPY
MPY.N
MSC
A = A + (x – y)2
A = A + (x * y)
No change in A
A=x*y
A=–x*y
A=A–x*y
The DS0 engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for ACCA (SATA).
Automatic saturation on/off for ACCB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator Saturation mode selection
(ACCSAT).
Note:
For CORCON layout, see Table 3-3.
DS70135G-page 20
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
Barrel
Shifter
16
X Data Bus
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
© 2010 Microchip Technology Inc.
DS70135G-page 21
dsPIC30F4011/4012
2.4.1
MULTIPLIER
The 17x17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/
scaler is a 33-bit value, which is sign-extended to
40 bits. Integer data is inherently represented as a
signed two’s complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF), including 0. For a 32-bit integer, the
data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit
(QX format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1-21-N).
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF), including 0, and
has a precision of 3.01518x10-5. In Fractional mode, a
16x16 multiply operation generates a 1.31 product,
which has a precision of 4.65661x10-10.
The same multiplier is used to support the DSC multiply
instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified register(s) in the W array.
2.4.2
2.4.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active-low and the
other input is complemented. The adder/subtracter
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above, and the SATA/B (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
3.
4.
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
DS70135G-page 22
Adder/Subtracter, Overflow and
Saturation
5.
6.
OA: ACCA overflowed into guard bits.
OB: ACCB overflowed into guard bits.
SA: ACCA saturated (bit 31 overflow and
saturation).
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation).
SB: ACCB saturated (bit 31 overflow and
saturation).
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation).
OAB: Logical OR of OA and OB.
SAB: Logical OR of SA and SB.
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
Also, the OA and OB bits can optionally generate an
arithmetic warning trap when set and the
corresponding Overflow Trap Flag Enable bit (OVATE,
OVBTE) in the INTCON1 register (refer to Section 5.0
“Interrupts”) is set. This allows the user to take
immediate action, for example, to correct system gain.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
The SA and SB bits are modified each time data passes
through the adder/subtracter but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit
saturation or bit 39 for 40-bit saturation) and is saturated
(if saturation is enabled). When saturation is not
enabled, SA and SB default to bit 39 overflow and thus
indicate that a catastrophic overflow has occurred. If the
COVTE bit in the INTCON1 register is set, SA and SB
bits generate an arithmetic warning trap when saturation
is disabled.
The overflow and saturation Status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three Saturation and Overflow
modes:
1.
2.
3.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target
accumulator. The SA or SB bit is set and
remains set until cleared by the user. This is
referred to as ‘super saturation’ and provides
protection against erroneous data or unexpected
algorithm problems (e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are not
used (so the OA, OB or OAB bits are never set).
Bit 39 Catastrophic Overflow
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
© 2010 Microchip Technology Inc.
2.4.2.2
Accumulator ‘Write-Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
2.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
[W13]+ = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.15 data value is stored and the least
significant word is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding
operations, the value tends to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb
(bit 16 of the accumulator) of ACCxH is examined. If it
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme removes any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write-back operation
functions in the same manner, addressing combined
DSC (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
DS70135G-page 23
dsPIC30F4011/4012
2.4.2.4
Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space write
saturation logic block accepts a 16-bit, 1.15 fractional
value from the round logic block as its input, together with
overflow status from the original source (accumulator)
and the 16-bit round adder. These are combined and
used to select the appropriate 1.15 fractional value as
output to write to data space memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MSb of the
source (bit 39) is used to determine the sign of the
operand being tested.
2.4.3
BARREL SHIFTER
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
to 31 for right shifts, and bit positions 0 to 15 for left
shifts.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
DS70135G-page 24
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
Note:
3.1
MEMORY ORGANIZATION
FIGURE 3-1:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F4011/4012
Reset – GOTO Instruction
Reset – Target Address
Vector Tables
Program Address Space
The program address space is 4M instruction words. It
is addressable by the 23-bit PC, table instruction
Effective Address (EA) or data space EA, when
program space is mapped into data space as defined
by Table 3-1. Note that the program space address is
incremented by two between successive program
words in order to provide compatibility with data space
addressing.
000000
000002
000004
Interrupt Vector Table
User Memory
Space
3.0
Reserved
Alternate Vector Table
User Flash
Program Memory
(16K instructions)
Reserved
(Read ‘0’s)
00007E
000080
000084
0000FE
000100
007FFE
008000
7FFBFE
7FFC00
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG to determine user or configuration space access. In Table 3-1, read/write instructions,
bit 23 allows access to the Device ID, the User ID and
the Configuration bits; otherwise, bit 23 is always clear.
Data EEPROM
(1 Kbyte)
7FFFFE
800000
Configuration Memory
Space
Reserved
UNITID (32 instr.)
8005BE
8005C0
8005FE
800600
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
© 2010 Microchip Technology Inc.
FEFFFE
FF0000
FFFFFE
DS70135G-page 25
dsPIC30F4011/4012
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
Instruction Access
User
TBLRD/TBLWT
User
(TBLPAG = 0)
TBLPAG
Data EA
TBLRD/TBLWT
Configuration
(TBLPAG = 1)
TBLPAG
Data EA
Program Space Visibility
User
FIGURE 3-2:
PC
0
0
PSVPAG
0
Data EA
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
Select
Using
Program
Space
Visibility
0
1
0
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0 TBLPAG Reg
8 bits
User/
Configuration
Space
Select
16 bits
24-bit EA
Byte
Select
Note: Program Space Visibility cannot be used to access bits of a word in program memory.
DS70135G-page 26
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can
also be present in program space.
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access From Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the least
significant word (lsw) of any address within program
space, without going through data space. The TBLRDH
and TBLWTH instructions are the only method whereby
the upper 8 bits of a program space word can be
accessed as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the Most Significant Byte of data.
A set of table instructions is provided to move byte or
word-sized data to and from program space (see
Figure 3-3 and Figure 3-4).
1.
2.
3.
4.
TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P maps to D.
Byte: Read one of the LSBs of the program
address;
P maps to the destination byte when byte
select = 0;
P maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 6.0
“Flash Program Memory” for details on Flash
programming).
TBLRDH: Table Read High
Word: Read the msw of the program address;
P maps to D; D will always
be = 0.
Byte: Read one of the MSBs of the program
address;
P maps to the destination byte when
byte select = 0;
The destination byte will always be ‘0’ when byte
select = 1.
TBLWTH: Table Write High (refer to Section 6.0
“Flash Program Memory” for details on Flash
programming).
Figure 3-2 illustrates how the EA is created for table
operations and data space accesses (PSV = 1). Here,
P refers to a program space word, whereas
D refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
PC Address
0x000000
0x000002
0x000004
0x000006
Program Memory
‘Phantom’ Byte
(read as ‘0’).
© 2010 Microchip Technology Inc.
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDL.W
TBLRDL.B (Wn = 0)
TBLRDL.B (Wn = 1)
DS70135G-page 27
dsPIC30F4011/4012
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
TBLRDH.W
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDH.B (Wn = 0)
Program Memory
‘Phantom’ Byte
(read as ‘0’)
3.1.2
TBLRDH.B (Wn = 1)
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. For
information on instruction encoding, refer to the “16-bit
MCU and DSC Programmer’s Reference Manual”
(DS70157).
DS70135G-page 28
Note that by incrementing the PC by 2 for each
program memory word, the Least Significant 15 bits of
data space addresses directly map to the Least
Significant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the
Program Space Visibility Page register, PSVPAG,
as shown in Figure 3-5.
Note:
PSV access is temporarily disabled during
table reads/writes.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions require one instruction
cycle in addition to the specified execution time:
- MAC class of instructions with data operand
prefetch
- MOV instructions
- MOV.D instructions
• All other instructions require two instruction cycles
in addition to the specified execution time of the
instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop allows the
instruction, accessing data using PSV, to execute
in a single cycle.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Data Space
Program Space
0x000100
0x0000
EA = 0
Data
Space
EA
PSVPAG(1)
0x00
8
15
16
0x8000
15
EA = 1
15
Address
Concatenation 23
23
15
0
0x001200
Upper Half of Data
Space is Mapped
into Program Space
0x007FFE
0xFFFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note: PSVPAG is an 8-bit register containing bits of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
© 2010 Microchip Technology Inc.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
64-Kbyte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 64-Kbyte data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y address
space from data space and address it using EAs
sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in Figure 3-6.
Figure 3-7 illustrates a graphical summary of how X
and Y data spaces are accessed for MCU and DSP
instructions.
DS70135G-page 29
dsPIC30F4011/4012
FIGURE 3-6:
dsPIC30F4011/4012 DATA SPACE MEMORY MAP
MSB
Address
MSB
2-Kbyte
SFR Space
0x0001
LSB
Address
16 bits
LSB
0x0000
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
2-Kbyte
SRAM Space
0x0BFF
0x0C01
0x0BFE
0x0C00
4096 Bytes
Near Data
Space
Y Data RAM (Y)
0x0FFF
0x0FFE
0x1001
0x1000
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70135G-page 30
0xFFFE
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-7:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write)
MAC Class Ops (Write)
Indirect EA using any W
© 2010 Microchip Technology Inc.
MAC Class Ops Read-Only
Indirect EA using W8, W9
Indirect EA using W10, W11
DS70135G-page 31
dsPIC30F4011/4012
3.2.2
DATA SPACES
3.2.3
The X data space is used by all instructions and supports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports Modulo Addressing for
all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. No writes occur
across the Y bus. This class of instructions dedicates
two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write-back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path, as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not userprogrammable. Should an EA point to data outside its
own assigned address space, or to a location outside
physical memory, an all-zero word/byte is returned. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X Space Pointers), returns
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data
space in a MAC instruction
0x0000
W10 or W11 used to access X
data space in a MAC instruction
0x0000
DATA SPACE WIDTH
The core data width is 16-bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
devices and improve data space memory usage efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instructions can only fetch words). That is, data
memory and registers are organized as two parallel
byte-wide entities, with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all Effective
Address calculations (including those generated by the
DSP operations, which are restricted to word-sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a
misaligned read or write be attempted, an address
error trap is generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write does not occur. In either case, a trap is then
executed, allowing the system and/or user to examine
the machine state prior to execution of the address
Fault.
FIGURE 3-8:
15
DATA ALIGNMENT
MSB
87
LSB
0
0001
Byte 1
Byte 0
0000
0003
Byte 3
Byte 2
0002
0005
Byte 5
Byte 4
0004
All Effective Addresses (EA) are 16 bits wide and point
to bytes within the data space. Therefore, the data
space address range is 64 Kbytes or 32K words.
DS70135G-page 32
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
All byte loads into any W register are loaded into the
LSB; the MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8-Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support Memory Direct Addressing with a 16-bit
address field.
There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM
is forced to ‘0’, because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
generated, using W15 as a source or destination
pointer, the address thus generated is compared with
the value in the SPLIM register. If the contents of the
Stack Pointer (W15) and the SPLIM register are equal,
and a push operation is performed, a stack error trap
will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows
beyond address 0x2000 in RAM, initialize the SPLIM
with the value, 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
The dsPIC DSC contains a software stack. W15 is used
as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
CALL STACK FRAME
SOFTWARE STACK
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
© 2010 Microchip Technology Inc.
0x0000 15
Stack Grows Towards
Higher Address
3.2.6
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP: [--W15]
PUSH: [W15++]
DS70135G-page 33
SFR Name
CORE REGISTER MAP(1)
Address
(Home)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
W0
0000
W0/WREG
0000 0000 0000 0000
W1
0002
W1
0000 0000 0000 0000
W2
0004
W2
0000 0000 0000 0000
W3
0006
W3
0000 0000 0000 0000
W4
0008
W4
0000 0000 0000 0000
W5
000A
W5
0000 0000 0000 0000
W6
000C
W6
0000 0000 0000 0000
W7
000E
W7
0000 0000 0000 0000
W8
0010
W8
0000 0000 0000 0000
W9
0012
W9
0000 0000 0000 0000
W10
0014
W10
0000 0000 0000 0000
W11
0016
W11
0000 0000 0000 0000
W12
0018
W12
0000 0000 0000 0000
W13
001A
W13
0000 0000 0000 0000
0000 0000 0000 0000
W14
001C
W14
W15
001E
W15
0000 1000 0000 0000
SPLIM
0020
SPLIM
0000 0000 0000 0000
ACCAL
0022
ACCAL
0000 0000 0000 0000
ACCAH
0024
ACCAH
0000 0000 0000 0000
ACCAU
0026
ACCBL
0028
Sign Extension (ACCA)
ACCAU
0000 0000 0000 0000
ACCBL
0000 0000 0000 0000
© 2010 Microchip Technology Inc.
ACCBH
002A
ACCBU
002C
ACCBH
PCL
002E
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
—
TBLPAG
0000 0000 0000 0000
PSVPAG
0034
—
—
—
—
—
—
—
—
PSVPAG
0000 0000 0000 0000
RCOUNT
0036
RCOUNT
DCOUNT
0038
DCOUNT
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
0000 0000 0000 0000
Sign Extension (ACCB)
ACCBU
0000 0000 0000 0000
—
PCH
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
DOSTARTL
—
—
—
—
—
—
—
—
—
0040
—
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
CORCON
0044
—
—
—
US
EDT
DL2
DL1
DL0
SATA
SATB
MODCON
0046
XMODEN
YMODEN
—
—
XMODSRT
0048
BWM
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
uuuu uuuu uuuu uuu0
0
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
DOENDH
IPL0
RA
SATDW ACCSAT
YWM
XS
0
DOSTARTH
DOENDL
DOENDH
Legend:
Note 1:
0000 0000 0000 0000
PCL
0000 0000 0uuu uuuu
N
OV
Z
C
0000 0000 0000 0000
IPL3
PSV
RND
IF
0000 0000 0010 0000
0
uuuu uuuu uuuu uuu0
XWM
0000 0000 0000 0000
dsPIC30F4011/4012
DS70135G-page 34
TABLE 3-3:
© 2010 Microchip Technology Inc.
TABLE 3-3:
SFR Name
CORE REGISTER MAP(1) (CONTINUED)
Address
(Home)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
XMODEND
004A
XE
1
uuuu uuuu uuuu uuu1
YMODSRT
004C
YS
0
uuuu uuuu uuuu uuu0
YMODEND
004E
YE
1
uuuu uuuu uuuu uuu1
XBREV
0050
BREN
DISICNT
0052
—
Legend:
Note 1:
XB
—
DISICNT
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
DS70135G-page 35
dsPIC30F4011/4012
NOTES:
DS70135G-page 36
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
4.0
Note:
ADDRESS GENERATOR UNITS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word-sized data reads for the DSP MAC
class of instructions only. The dsPIC Digital Signal
Controller AGUs support three types of data
addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing is only applicable to data space addresses.
4.1
Instruction Addressing Modes
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
TABLE 4-1:
4.1.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory or a 5-bit literal. The result
location can either be a W register or an address
location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
© 2010 Microchip Technology Inc.
The sum of Wn and a literal forms the EA.
DS70135G-page 37
dsPIC30F4011/4012
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instructions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset) field
is shared between both source and
destination (but typically only used by one).
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.1.4
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the Data Pointers through register indirect
tables.
The two source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU, and W10 and W11 will always be directed to the
Y AGU. The Effective Addresses (EA) generated
(before and after modification) must, therefore, be valid
addresses within X data space for W8 and W9, and Y
data space for W10 and W11.
Note:
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
4.2
Modulo Addressing
Modulo Addressing is a method of providing an automated means to support circular data buffers using
hardware. The objective is to remove the need for software to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo Addressing can operate in either data or program space (since the Data Pointer mechanism is
essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo
Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo
Addressing, since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buffers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks will be performed on both the lower and upper
address boundaries).
Register Indirect with Register Offset
Addressing is only available for W9 (in X
data space) and W11 (in Y data space).
DS70135G-page 38
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
4.2.1
START AND END ADDRESS
4.2.2
The Modulo Addressing scheme requires that a start and
end address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND,
YMODSRT and YMODEND (see Table 3-3).
Note:
Y space Modulo Addressing EA calculations assume word-sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control register, MODCON, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select which registers operate with Modulo Addressing. If XWM = 15, X RAGU and
X WAGU Modulo Addressing are disabled. Similarly, if
YWM = 15, Y AGU Modulo Addressing is disabled.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON (see Table 3-3). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM), to
which Modulo Addressing is to be applied, is stored in
MODCON. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON.
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DO
MOV
AGAIN:
0x1100
#0x1100,W0
W0, XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
#0x0000,W0
#0x1110,W1
AGAIN,#0x31
W0, [W1++]
INC W0,W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
;fill the 50 buffer locations
;fill the next location
;increment the fill value
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
© 2010 Microchip Technology Inc.
DS70135G-page 39
dsPIC30F4011/4012
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W register.
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to). Address
changes may, therefore, jump beyond boundaries and
still be adjusted correctly.
Note:
4.3
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (e.g.,
[W7+W2]) is used, Modulo Addressing
correction is performed, but the contents
of the register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
reordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ’N’ bits of the data buffer start address
must be zeros.
XB is the Bit-Reversed Addressing modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
When enabled, Bit-Reversed Addressing is only
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing mode and word-sized data
writes. It will not function for any other addressing
mode or for byte-sized data, and normal addresses will
be generated instead. When Bit-Reversed Addressing
is active, the W Address Pointer will always be added
to the address modifier (XB) and the offset associated
with the Register Indirect Addressing mode will be
ignored. In addition, as word-sized data is a
requirement, the LSb of the EA is ignored (and always
clear).
Note:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1.
2.
3.
BWM (W register selection) in the MODCON register is any value other than 15 (the stack can not
be accessed using Bit-Reversed Addressing)
and
The BREN bit is set in the XBREV register and
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed
Addressing will assume priority when
active for the X WAGU, and X WAGU
Modulo Addressing will be disabled.
However,
Modulo
Addressing
will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN bit (XBREV), then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b1
b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
DS70135G-page 40
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
TABLE 4-3:
Note 1:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Buffer Size (Words)
XB Bit-Reversed Address Modifier Value(1)
32768
0x4000
16384
0x2000
8192
0x1000
4096
0x0800
2048
0x0400
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
8
0x0004
4
0x0002
2
0x0001
Modifier values for buffer sizes greater than 1024 words will exceed the available data memory on the
dsPIC30F4011/4012 devices.
© 2010 Microchip Technology Inc.
DS70135G-page 41
dsPIC30F4011/4012
NOTES:
DS70135G-page 42
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
5.0
Note:
INTERRUPTS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
The dsPIC30F4011/4012 has 30 interrupt sources and
4 processor exceptions (traps), which must be
arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The interrupt vector is transferred from the program data bus
into the program counter via a 24-bit wide multiplexer
on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 5-1.
The interrupt controller is responsible for preprocessing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers:
• IFS0, IFS1, IFS2
All interrupt request flags are maintained in these
three registers. The flags are set by their respective peripherals or external signals, and they are
cleared via software.
• IEC0, IEC1, IEC2
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
• IPC0... IPC11
The user-assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
• IPL
The current CPU priority level is explicitly stored
in the IPL bits. IPL is present in the CORCON
register, whereas IPL are present in the
STATUS register (SR) in the processor core.
© 2010 Microchip Technology Inc.
• INTCON1, INTCON2
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the AIVT.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
All interrupt sources can be user-assigned to one of
seven priority levels, 1 through 7, via the IPCx
registers. Each interrupt source is associated with an
interrupt vector, as shown in Table 5-1. Levels 7 and 1
represent the highest and lowest maskable priorities,
respectively.
Note:
Assigning a priority level of 0 to an
interrupt source is equivalent to disabling
that interrupt.
If the NSTDIS bit (INTCON1) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupton-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program memory
that corresponds to the interrupt. There are 63 different
vectors within the IVT (refer to Figure 5-2). These vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Figure 5-2).
These locations contain 24-bit addresses, and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these words
during normal execution. This prevents execution of
random data as a result of accidentally decrementing a
PC into vector space, accidentally mapping a data space
address into vector space or the PC rolling over to
0x000000 after reaching the end of implemented
program memory space. Execution of a GOTO instruction
to this vector space will also generate an address error
trap.
DS70135G-page 43
dsPIC30F4011/4012
5.1
Interrupt Priority
The user-assignable Interrupt Priority (IP) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a
‘0’. These bits define the priority level assigned to a
particular interrupt by the user.
Note:
The user-assignable priority levels start at
0 as the lowest priority, and level 7 as the
highest priority.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority”.
Natural order priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSCs and their associated
vector numbers.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (LowVoltage Detect) can be given a priority of 7. The INT0
(External Interrupt 0) may be assigned to priority
level 1, thus giving it a very low effective priority.
TABLE 5-1:
INT
Vector
Number Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45-53
DS70135G-page 44
INTERRUPT VECTOR TABLE
Interrupt Source
Highest Natural Order Priority
8
INT0 – External Interrupt 0
9
IC1 – Input Capture 1
10
OC1 – Output Compare 1
11
T1 – Timer1
12
IC2 – Input Capture 2
13
OC2 – Output Compare 2
14
T2 – Timer2
15
T3 – Timer3
16
SPI1
17
U1RX – UART1 Receiver
18
U1TX – UART1 Transmitter
19
ADC – ADC Convert Done
20
NVM – NVM Write Complete
21
SI2C – I2C™ Slave Interrupt
22
MI2C – I2C Master Interrupt
23
Input Change Interrupt
24
INT1 – External Interrupt 1
25
IC7 – Input Capture 7
26
IC8 – Input Capture 8
27
OC3 – Output Compare 3
28
OC4 – Output Compare 4
29
T4 – Timer4
30
T5 – Timer5
31
INT2 – External Interrupt 2
32
U2RX – UART2 Receiver
33
U2TX – UART2 Transmitter
34
Reserved
35
C1 – Combined IRQ for CAN1
36
Reserved
37
Reserved
38
Reserved
39
Reserved
40
Reserved
41
Reserved
42
Reserved
43
Reserved
44
Reserved
45
Reserved
46
Reserved
47
PWM – PWM Period Match
48
QEI – QEI Interrupt
49
Reserved
50
Reserved
51
FLTA – PWM Fault A
52
Reserved
53-61 Reserved
Lowest Natural Order Priority
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
5.2
Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The processor initializes its registers in response to a Reset,
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory location, immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
5.3
Traps
Traps can be considered as non-maskable interrupts,
indicating a software or hardware error which adhere to
a predefined priority, as shown in Figure 5-1. They are
intended to provide the user a means to correct erroneous operation during debug and when operating within
the application.
Note:
RESET SOURCES
There are 5 sources of error which will cause a device
reset.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
If the user does not intend to take corrective action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps, Level 8
through Level 15, which means that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap and he sets
the IPL bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing
priority. However, since all traps can be nested, priority
has little effect.
5.3.1.1
Math Error Trap
The math error trap executes under the following four
circumstances:
1.
2.
3.
4.
© 2010 Microchip Technology Inc.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
If enabled, a math error trap will be taken when
an arithmetic operation on either accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
DS70135G-page 45
dsPIC30F4011/4012
5.3.1.2
Address Error Trap
This trap is initiated when any of the following
circumstances occurs:
1.
2.
3.
4.
A misaligned data word access is attempted.
A data fetch from an unimplemented data
memory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
Note:
5.
6.
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space and unimplemented Y
space includes all of X space.
Execution of a “BRA #literal” instruction, or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
5.3.1.3
Stack Error Trap
5.3.2
HARD AND SOFT TRAPS
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending in order to completely correct the Fault.
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged or is being processed, a
hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR status bit (RCON) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 5-1:
This trap is initiated under the following conditions:
2.
The Stack Pointer is loaded with a value which
is greater than the (user-programmable) limit
value written into the SPLIM register (stack
overflow).
The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
5.3.1.4
Oscillator Fail Trap
Reset – GOTO Instruction
Decreasing
Priority
1.
TRAP VECTORS
IVT
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
AIVT
Reset – GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
DS70135G-page 46
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
0x0000FE
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
5.4
Interrupt Sequence
5.5
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the interrupt
enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 5-2. The low byte of the
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this interrupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine (ISR).
FIGURE 5-2:
Stack Grows Towards
Higher Address
0x0000 15
INTERRUPT STACK
FRAME
0
PC
SRL IPL3 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON) is always
clear when interrupts are being processed. It is set only during execution of
traps.
The RETFIE (return from interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.
© 2010 Microchip Technology Inc.
Alternate Interrupt Vector Table
In program memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 5-1. Access to the Alternate Interrupt Vector Table is provided by the ALTIVT bit in the
INTCON2 register. If the ALTIVT bit is set, all interrupt
and exception processes will use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application
and a support environment, without requiring the interrupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time.
If the AIVT is not required, the program memory
allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using shadow registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one-level deep. The
shadow registers are accessible using the PUSH.S and
POP.S instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instructions. Users must save the key registers in software
during a lower priority interrupt if the higher priority ISR
uses fast context saving.
5.7
External Interrupt Requests
The interrupt controller supports three external interrupt request signals, INT0-INT2. These inputs are edge
sensitive; they require a low-to-high, or a high-to-low
transition, to generate an interrupt request. The
INTCON2 register has three bits, INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes if Sleep or
Idle modes are active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the ISR needed to process
the interrupt request.
DS70135G-page 47
SFR
Name
ADR
INTERRUPT CONTROLLER REGISTER MAP(1)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
—
0000 0000 0000 0000
INTCON1
0080 NSTDIS
—
—
—
—
OVATE
OVBTE
COVTE
—
—
—
MATHERR
ADDRERR
INTCON2
0082 ALTIVT
DISI
—
—
—
—
—
—
—
—
—
—
—
INT2EP
INT1EP
IFS0
0084
CNIF
MI2CIF
SI2CIF
NVMIF
ADIF
SPI1IF
T3IF
T2IF
OC2IF
IC2IF
T1IF
OC1IF
IC1IF
INT0IF
IFS1
0086
—
—
—
—
C1IF
—
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
IC8IF
IC7IF
INT1IF
0000 0000 0000 0000
IFS2
0088
—
—
—
—
FLTAIF
—
—
QEIIF
PWMIF
—
—
—
—
—
—
—
0000 0000 0000 0000
IEC0
008C
CNIE
MI2CIE
SI2CIE
NVMIE
ADIE
SPI1IE
T3IE
T2IE
OC2IE
IC2IE
T1IE
OC1IE
IC1IE
INT0IE
0000 0000 0000 0000
IEC1
008E
—
—
—
—
C1IE
—
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
IC8IE
IC7IE
INT1IE
0000 0000 0000 0000
IEC2
0090
—
—
—
—
FLTAIE
—
—
QEIIE
PWMIE
—
—
—
—
—
—
—
0000 0000 0000 0000
IPC0
0094
—
T1IP
—
OC1IP
—
IC1IP
—
INT0IP
0100 0100 0100 0100
IPC1
0096
—
T31P
—
T2IP
—
OC2IP
—
IC2IP
0100 0100 0100 0100
IPC2
0098
—
ADIP
—
U1TXIP
—
U1RXIP
—
SPI1IP
0100 0100 0100 0100
IPC3
009A
—
CNIP
—
MI2CIP
—
SI2CIP
—
NVMIP
0100 0100 0100 0100
IPC4
009C
—
OC3IP
—
IC8IP
—
IC7IP
—
INT1IP
0100 0100 0100 0100
IPC5
009E
—
INT2IP
—
T5IP
—
T4IP
—
OC4IP
0100 0100 0100 0100
IPC6
00A0
—
C1IP
—
—
—
—
—
U2TXIP
—
U2RXIP
IPC7
00A2
—
—
IPC8
00A4
—
—
IPC9
00A6
—
PWMIP
IPC10
00A8
—
FLTAIP
IPC11
00AA
—
Legend:
Note 1:
—
U1TXIF U1RXIF
U1TXIE U1RXIE
STKERR OSCFAIL
INT0EP 0000 0000 0000 0000
0000 0000 0000 0000
0100 0000 0100 0100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
0100 0000 0100 0100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 0000 0000 0000
—
—
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
QEIIP
—
—
0100 0000 0000 0100
dsPIC30F4011/4012
DS70135G-page 48
TABLE 5-2:
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
6.0
FLASH PROGRAM MEMORY
Note:
6.2
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.
With RTSP, the user may erase program memory,
32 instructions (96 bytes) at a time, and can write
program memory data, 32 instructions (96 bytes) at a
time.
6.3
6.1
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
In-Circuit Serial Programming™ (ICSP™)
Run-Time Self-Programming (RTSP)
A 24-bit program memory address is formed using
bits of the TBLPAG register and the Effective
Address (EA) from a W register, specified in the table
instruction, as shown in Figure 6-1.
In-Circuit Serial Programming
(ICSP)
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices, and then
program the digital signal controller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
FIGURE 6-1:
Table Instruction Operation Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
1.
2.
Run-Time Self-Programming
(RTSP)
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
© 2010 Microchip Technology Inc.
1/0
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
DS70135G-page 49
dsPIC30F4011/4012
6.4
RTSP Operation
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instructions or 96 bytes. Each panel consists of 128 rows or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program
32 instructions at one time.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches: instruction 0, instruction 1,
etc. The addresses loaded must always be from a
32 address boundary.
6.5
RTSP Control Registers
The four SFRs used to read and write the program
Flash memory are:
•
•
•
•
NVMCON
NVMADR
NVMADRU
NVMKEY
6.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
6.5.2
NVMADR REGISTER
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register.
32 TBLWTL and 32 TBLWTH instructions are required
to load the 32 instructions.
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA of the last table instruction that
has been executed and selects the row to write.
All of the table write operations are single-word writes
(2 instruction cycles) because only the table latches are
written.
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register captures the EA of the last table instruction that
has been executed.
After the latches are written, a programming operation
needs to be initiated to program the data.
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
6.5.3
6.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
“Programming Operations” for further details.
Note:
DS70135G-page 50
NVMADRU REGISTER
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
6.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
6.6.1
4.
5.
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase or program one row of program
Flash memory at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a) Set up NVMCON register for multi-word,
program Flash, erase and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 6-1:
6.
Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a) Set up NVMCON register for multi-word,
program Flash, program and set WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. This will begin program
cycle.
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
6.6.2
ERASING A ROW OF PROGRAM
MEMORY
Example 6-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word
; program memory selected, and writes enabled
MOV
#0x4041,W0
;
MOV
W0,NVMCON
;
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR),W0
;
MOV
W0,NVMADRU
;
MOV
#tbloffset(PROG_ADDR),W0
;
MOV
W0, NVMADR
;
DISI
#5
;
;
MOV
#0x55,W0
MOV
W0,NVMKEY
;
MOV
#0xAA,W1
;
MOV
W1,NVMKEY
;
BSET
NVMCON,#WR
;
NOP
;
NOP
;
© 2010 Microchip Technology Inc.
write
Init NVMCON SFR
Initialize PM Page Boundary SFR
Intialize in-page EA[15:0] pointer
Intialize NVMADR SFR
Block all interrupts with priority < 7
for next 5 instructions
Write the 0x55 key
Write the 0xAA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
DS70135G-page 51
dsPIC30F4011/4012
6.6.3
LOADING WRITE LATCHES
Example 6-2 shows a sequence of instructions that
can be used to load the 96 bytes of write latches.
32 TBLWTL and 32 TBLWTH instructions are needed to
load the write latches selected by the Table Pointer.
EXAMPLE 6-2:
LOADING WRITE LATCHES
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
#0x0000,W0
;
MOV
W0,TBLPAG
; Initialize PM Page Boundary SFR
MOV
#0x6000,W0
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
#LOW_WORD_0,W2
;
MOV
#HIGH_BYTE_0,W3
;
TBLWTL W2,[W0]
; Write PM low word into program latch
TBLWTH W3,[W0++]
; Write PM high byte into program latch
; 1st_program_word
MOV
#LOW_WORD_1,W2
;
MOV
#HIGH_BYTE_1,W3
;
TBLWTL W2,[W0]
; Write PM low word into program latch
TBLWTH W3,[W0++]
; Write PM high byte into program latch
; 2nd_program_word
MOV
#LOW_WORD_2,W2
;
MOV
#HIGH_BYTE_2,W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
•
•
•
; 31st_program_word
MOV
#LOW_WORD_31,W2
;
MOV
#HIGH_BYTE_31,W3
;
TBLWTL W2, [W0]
; Write PM low word into program latch
TBLWTH W3, [W0++]
; Write PM high byte into program latch
Note: In Example 6-2, the contents of the upper byte of W3 have no effect.
6.6.4
INITIATING THE PROGRAMMING
SEQUENCE
For protection, the write initiate sequence for NVMKEY
must be used to allow any erase or program operation
to proceed. After the programming command has been
executed, the user must wait for the programming time
until programming is complete. The two instructions
following the start of the programming sequence
should be NOPs.
EXAMPLE 6-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55,W0
W0,NVMKEY
#0xAA,W1
W1,NVMKEY
NVMCON,#WR
DS70135G-page 52
; Block all interrupts with priority < 7
; for next 5 instructions
;
;
;
;
;
;
Write the 0x55 key
Write the 0xAA key
Start the erase sequence
Insert two NOPs after the erase
command is asserted
© 2010 Microchip Technology Inc.
© 2010 Microchip Technology Inc.
NVM REGISTER MAP(1)
TABLE 6-1:
File Name
Addr.
Bit 15
Bit 14
Bit 13
NVMCON
0760
WR
WREN
WRERR
NVMADR
0762
NVMADRU
0764
—
—
—
—
—
—
—
—
NVMKEY
0766
—
—
—
—
—
—
—
—
Legend:
Note 1:
Bit 12 Bit 11 Bit 10
—
—
—
Bit 9
—
Bit 8
Bit 7
TWRI
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PROGOP
NVMADR
—
Bit 1
Bit 0
All Resets
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
NVMADR
0000 0000 uuuu uuuu
KEY
0000 0000 0000 0000
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F4011/4012
DS70135G-page 53
dsPIC30F4011/4012
NOTES:
DS70135G-page 54
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
7.0
Note:
DATA EEPROM MEMORY
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
The data EEPROM memory is readable and writable
during normal operation over the entire VDD range. The
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 6.0 “Flash
Program Memory”, these registers are:
•
•
•
•
NVMCON
NVMADR
NVMADRU
NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU register, is used to address the EEPROM
location being accessed. TBLRDL and TBLWTL instructions are used to read and write data EEPROM. The
dsPIC30F4011/4012 devices have 1 Kbyte (512 words)
of data EEPROM, with an address range from
0x7FFC00 to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.
© 2010 Microchip Technology Inc.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is responsible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
Control bit, WR, initiates write operations, similar to
program Flash writes. This bit cannot be cleared, only
set, in software. This bit is cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal operation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register, NVMADR, remains unchanged.
Note:
7.1
Interrupt flag bit, NVMIF in the IFS0
register, is set when write is complete. It
must be cleared in software.
Reading the Data EEPROM
A TBLRD instruction reads a word at the current program word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4, as shown in Example 7-1.
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL
DATA EEPROM READ
#LOW_ADDR_WORD,W0 ; Init Pointer
#HIGH_ADDR_WORD,W1
W1,TBLPAG
[ W0 ], W4
; read data EEPROM
DS70135G-page 55
dsPIC30F4011/4012
7.2
7.2.1
Erasing Data EEPROM
ERASING A BLOCK OF DATA
EEPROM
In order to erase a block of data EEPROM, the
NVMADRU and NVMADR registers must initially
point to the block of memory to be erased. Configure
NVMCON for erasing a block of data EEPROM and
set the WR and WREN bits in the NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 7-2.
EXAMPLE 7-2:
DATA EEPROM BLOCK ERASE
; Select data EEPROM block, WR, WREN bits
MOV
#0x4045,W0
MOV
W0,NVMCON
; Initialize NVMCON SFR
; Start erase cycle by setting WR after writing key sequence
DISI
#5
; Block all interrupts with priority < 7
; for next 5 instructions
MOV
#0x55,W0
;
MOV
W0,NVMKEY
; Write the 0x55 key
MOV
#0xAA,W1
;
MOV
W1,NVMKEY
; Write the 0xAA key
BSET
NVMCON,#WR
; Initiate erase sequence
NOP
NOP
; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete
7.2.2
ERASING A WORD OF DATA
EEPROM
The TBLPAG and NVMADR registers must point to
the block. Select erase a block of data Flash and set
the WR and WREN bits in the NVMCON register.
Setting the WR bit initiates the erase, as shown in
Example 7-3.
EXAMPLE 7-3:
DATA EEPROM WORD ERASE
; Select data EEPROM word, WR, WREN bits
MOV
#0x4044,W0
MOV
W0,NVMCON
; Start erase cycle by setting WR after writing key sequence
DISI
#5
; Block all interrupts with priority Synchronization Jump Width
© 2010 Microchip Technology Inc.
DS70135G-page 135
CAN1 REGISTER MAP(1)
SFR Name
Addr.
Bit 15
Bit 14
Bit 13
C1RXF0SID
0300
—
—
—
—
—
—
C1RXF0EIDH
0302
C1RXF0EIDL
0304
C1RXF1SID
0308
—
—
—
—
—
—
C1RXF1EIDH
030A
030C
C1RXF2SID
0310
—
—
—
—
—
—
C1RXF2EIDH
0312
0314
C1RXF3SID
0318
—
—
—
—
—
—
C1RXF3EIDH
031A
031C
C1RXF4SID
0320
—
—
—
—
—
—
—
C1RXF4EIDH
0322
0324
C1RXF5SID
0328
—
—
—
—
—
—
C1RXF5EIDH
032A
032C
C1RXM0SID
0330
—
—
—
C1RXM0EIDH 0332
—
—
—
0334
C1RXM1SID
0338
—
—
—
C1RXM1EIDH 033A
—
—
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
—
Bit 0
—
—
—
—
—
—
—
—
—
—
—
0000 uuuu uuuu uuuu
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000 uuuu uuuu uuuu
—
Receive Acceptance Filter 3 Standard Identifier
—
—
—
—
—
—
—
—
—
—
0000 uuuu uuuu uuuu
—
Receive Acceptance Filter 4 Standard Identifier
—
—
—
—
—
—
—
—
—
—
0000 uuuu uuuu uuuu
—
Receive Acceptance Filter 5 Standard Identifier
—
—
—
—
—
—
—
—
—
—
0000 uuuu uuuu uuuu
—
Receive Acceptance Mask 0 Standard Identifier
—
—
—
uuuu uu00 0000 0000
—
MIDE
000u uuuu uuuu uu0u
—
—
uuuu uu00 0000 0000
—
MIDE
000u uuuu uuuu uu0u
—
—
Receive Acceptance Mask 0 Extended Identifier
Receive Acceptance Mask 0 Extended Identifier
—
—
—
—
—
—
—
0000 uuuu uuuu uuuu
—
Receive Acceptance Mask 1 Standard Identifier
—
Receive Acceptance Mask 1 Extended Identifier
Receive Acceptance Mask 1 Extended Identifier
Transmit Buffer 2 Standard Identifier
—
—
—
—
—
—
—
—
—
—
—
—
—
—
uuuu uu00 0000 0000
EXIDE 000u uuuu uuuu uu0u
Receive Acceptance Filter 5 Extended Identifier
—
uuuu uu00 0000 0000
EXIDE 000u uuuu uuuu uu0u
Receive Acceptance Filter 4 Extended Identifier
—
uuuu uu00 0000 0000
EXIDE 000u uuuu uuuu uu0u
Receive Acceptance Filter 3 Extended Identifier
—
uuuu uu00 0000 0000
EXIDE 000u uuuu uuuu uu0u
Receive Acceptance Filter 2 Extended Identifier
—
uuuu uu00 0000 0000
EXIDE 000u uuuu uuuu uu0u
0000 uuuu uuuu uuuu
—
Receive Acceptance Filter 2 Standard Identifier
—
Reset State
EXIDE 000u uuuu uuuu uu0u
Receive Acceptance Filter 1 Extended Identifier
Receive Acceptance Filter 5 Extended Identifier
C1RXM0EIDL
Bit 7
Receive Acceptance Filter 1 Standard Identifier
Receive Acceptance Filter 4 Extended Identifier
C1RXF5EIDL
Bit 8
Receive Acceptance Filter 0 Extended Identifier
Receive Acceptance Filter 3 Extended Identifier
C1RXF4EIDL
Bit 9
Receive Acceptance Filter 0 Standard Identifier
Receive Acceptance Filter 2 Extended Identifier
C1RXF3EIDL
0340
Bit 10
Receive Acceptance Filter 1 Extended Identifier
C1RXF2EIDL
C1TX2SID
Bit 11
Receive Acceptance Filter 0 Extended Identifier
C1RXF1EIDL
C1RXM1EIDL 033C
Bit 12
0000 uuuu uuuu uuuu
—
Transmit Buffer 2 Standard Identifier
SRR
uuuu uu00 0000 0000
TXIDE uuuu u000 uuuu uuuu
Transmit Buffer 2 Extended Identifier
© 2010 Microchip Technology Inc.
C1TX2EID
0342 Transmit Buffer 2 Extended Identifier
C1TX2DLC
0344
Transmit Buffer 2 Extended Identifier
C1TX2B1
0346
Transmit Buffer 2 Byte 1
Transmit Buffer 2 Byte 0
uuuu uuuu uuuu uuuu
C1TX2B2
0348
Transmit Buffer 2 Byte 3
Transmit Buffer 2 Byte 2
uuuu uuuu uuuu uuuu
C1TX2B3
034A
Transmit Buffer 2 Byte 5
Transmit Buffer 2 Byte 4
uuuu uuuu uuuu uuuu
C1TX2B4
034C
Transmit Buffer 2 Byte 7
Transmit Buffer 2 Byte 6
C1TX2CON
034E
—
—
—
—
—
C1TX1SID
0350
C1TX1EID
0352 Transmit Buffer 1 Extended Identifier
C1TX1DLC
0354
Transmit Buffer 1 Extended Identifier
C1TX1B1
0356
Transmit Buffer 1 Byte 1
Legend:
Note 1:
Transmit Buffer 1 Standard Identifier
—
TXRTR TXRB1
—
—
—
—
—
—
—
—
—
TXRTR TXRB1
TXRB0
—
—
DLC
TXABT TXLARB TXERR
TXREQ
uuuu 0000 uuuu uuuu
—
—
uuuu uuuu uuuu uuuu
—
Transmit Buffer 1 Standard Identifier
TXPRI
SRR
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
DLC
Transmit Buffer 1 Byte 0
—
0000 0000 0000 0000
TXIDE uuuu u000 uuuu uuuu
Transmit Buffer 1 Extended Identifier
TXRB0
uuuu uuuu uuuu u000
uuuu 0000 uuuu uuuu
—
—
uuuu uuuu uuuu u000
uuuu uuuu uuuu uuuu
dsPIC30F4011/4012
DS70135G-page 136
TABLE 19-1:
© 2010 Microchip Technology Inc.
TABLE 19-1:
SFR Name
C1TX1B2
Addr.
CAN1 REGISTER MAP(1) (CONTINUED)
Bit 15
Bit 14
Bit 13
0358
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 0
Reset State
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
035A
Transmit Buffer 1 Byte 5
Transmit Buffer 1 Byte 4
C1TX1B4
035C
Transmit Buffer 1 Byte 7
Transmit Buffer 1 Byte 6
C1TX1CON
035E
C1TX0SID
0360
—
Bit 1
Transmit Buffer 1 Byte 2
C1TX1B3
—
Bit 2
Transmit Buffer 1 Byte 3
—
—
—
Transmit Buffer 0 Standard Identifier
—
—
—
—
—
—
—
—
—
—
—
TXABT TXLARB TXERR
uuuu uuuu uuuu uuuu
TXREQ
—
TXPRI
Transmit Buffer 0 Standard Identifier
SRR
0000 0000 0000 0000
TXIDE uuuu u000 uuuu uuuu
Transmit Buffer 0 Extended Identifier
C1TX0EID
0362 Transmit Buffer 0 Extended Identifier
C1TX0DLC
0364
Transmit Buffer 0 Extended Identifier
C1TX0B1
0366
Transmit Buffer 0 Byte 1
Transmit Buffer 0 Byte 0
uuuu uuuu uuuu uuuu
C1TX0B2
0368
Transmit Buffer 0 Byte 3
Transmit Buffer 0 Byte 2
uuuu uuuu uuuu uuuu
C1TX0B3
036A
Transmit Buffer 0 Byte 5
Transmit Buffer 0 Byte 4
uuuu uuuu uuuu uuuu
C1TX0B4
036C
Transmit Buffer 0 Byte 7
Transmit Buffer 0 Byte 6
C1TX0CON
036E
—
—
—
—
—
TXRTR TXRB1
—
—
TXRB0
—
—
—
DLC
TXABT TXLARB TXERR
uuuu 0000 uuuu uuuu
—
—
uuuu uuuu uuuu u000
uuuu uuuu uuuu uuuu
TXREQ
—
TXPRI
Receive Buffer 1 Standard Identifier
C1RX1SID
0370
—
—
—
C1RX1EID
0372
—
—
—
C1RX1DLC
0374
Receive Buffer 1 Extended Identifier
C1RX1B1
0376
Receive Buffer 1 Byte 1
Receive Buffer 1 Byte 0
uuuu uuuu uuuu uuuu
C1RX1B2
0378
Receive Buffer 1 Byte 3
Receive Buffer 1 Byte 2
uuuu uuuu uuuu uuuu
C1RX1B3
037A
Receive Buffer 1 Byte 5
Receive Buffer 1 Byte 4
uuuu uuuu uuuu uuuu
C1RX1B4
037C
Receive Buffer 1 Byte 7
Receive Buffer 1 Byte 6
C1RX1CON
037E
—
—
—
C1RX0SID
0380
—
—
—
—
—
—
—
—
SRR
0000 0000 0000 0000
RXIDE 000u uuuu uuuu uuuu
Receive Buffer 1 Extended Identifier
—
RXRTR RXRB1
—
—
—
—
—
RXFUL
—
—
—
0000 uuuu uuuu uuuu
RXRB0
—
DLC
uuuu uuuu uuuu uuuu
RXRTRRO
FILHIT
SRR
0000 0000 0000 0000
RXIDE 000u uuuu uuuu uuuu
Receive Buffer 0 Extended Identifier
C1RX0EID
0382
C1RX0DLC
0384
Receive Buffer 0 Extended Identifier
C1RX0B1
0386
Receive Buffer 0 Byte 1
Receive Buffer 0 Byte 0
uuuu uuuu uuuu uuuu
C1RX0B2
0388
Receive Buffer 0 Byte 3
Receive Buffer 0 Byte 2
uuuu uuuu uuuu uuuu
C1RX0B3
038A
Receive Buffer 0 Byte 5
Receive Buffer 0 Byte 4
uuuu uuuu uuuu uuuu
C1RX0B4
038C
Receive Buffer 0 Byte 7
Receive Buffer 0 Byte 6
uuuu uuuu uuuu uuuu
C1RX0CON
038E
C1CTRL
0390 CANCAP
C1CFG1
0392
—
C1CFG2
0394
—
WAKFIL
C1INTF
0396 RX0OVR RX1OVR
DS70135G-page 137
C1INTE
0398
C1EC
039A
Legend:
Note 1:
—
—
—
—
—
—
—
CSIDL
ABAT
CANCKS
—
—
—
—
—
RXRTR RXRB1
—
—
—
—
RXFUL
REQOP
—
—
—
—
—
—
OPMODE
—
—
—
SEG2PH
SEG2PHTS
SAM
TXEP
RXEP
TXWAR RXWAR EWARN
IVRIF
WAKIF
ERRIF
—
—
IVRIE
WAKIE
ERRIE
—
—
TERRCNT
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
uuuu uuuu 000u uuuu
RXRTRRO DBEN JTOFF FILHIT0 0000 0000 0000 0000
—
ICODE
—
BRP
—
—
—
DLC
SJW
TXBO
—
0000 uuuu uuuu uuuu
RXRB0
SEG1PH
0000 0100 1000 0000
0000 0000 0000 0000
PRSEG
0u00 0uuu uuuu uuuu
TX2IF
TX1IF
TX0IF RX1IF
RX0IF 0000 0000 0000 0000
TX2IE
TX1IE
TX0IE RX1IE
RX0IE 0000 0000 0000 0000
RERRCNT
0000 0000 0000 0000
dsPIC30F4011/4012
Receive Buffer 0 Standard Identifier
—
uuuu uuuu 000u uuuu
dsPIC30F4011/4012
NOTES:
DS70135G-page 138
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
20.0
Note:
10-BIT, HIGH-SPEED ANALOGTO-DIGITAL CONVERTER
(ADC) MODULE
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
The 10-bit, high-speed Analog-to-Digital Converter
(ADC) allows conversion of an analog input signal to a
10-bit digital number. This module is based on a
Successive Approximation Register (SAR) architecture
and provides a maximum sampling rate of 1 Msps. The
ADC module has 16 analog inputs which are multiplexed into four sample and hold amplifiers. The output
of the sample and hold is the input into the converter
which generates the result. The analog reference
voltages are software selectable to either the device
supply voltage (AVDD/AVSS) or the voltage level on the
(VREF+/VREF-) pins. The ADC module has a unique
feature of being able to operate while the device is in
Sleep mode.
© 2010 Microchip Technology Inc.
The ADC module has six 16-bit registers:
•
•
•
•
•
•
A/D Control Register 1 (ADCON1)
A/D Control Register 2 (ADCON2)
A/D Control Register 3 (ADCON3)
A/D Input Select Register (ADCHS)
A/D Port Configuration Register (ADPCFG)
A/D Input Scan Selection Register (ADCSSL)
The ADCON1, ADCON2 and ADCON3 registers
control the operation of the ADC module. The ADCHS
register selects the input channels to be converted. The
ADPCFG register configures the port pins as analog
inputs or as digital I/O. The ADCSSL register selects
inputs for scanning.
Note:
The SSRC, ASAM, SIMSAM,
SMPI, BUFM and ALTS bits, as well
as the ADCON3 and ADCSSL registers,
must not be written to while ADON = 1.
This would lead to indeterminate results.
The block diagram of the ADC module is shown in
Figure 20-1.
DS70135G-page 139
dsPIC30F4011/4012
FIGURE 20-1:
10-BIT, HIGH-SPEED ADC FUNCTIONAL BLOCK DIAGRAM
AVDD
VREF+
AVSS
VREF-
AN2
+
AN6
-
AN1
AN4
+
AN7
-
S/H
CH1
ADC
10-bit Result
S/H
Conversion Logic
CH2
16-word, 10-bit
Dual Port
Buffer
AN2
AN5
+
AN8
-
S/H
CH3
CH1,CH2,
CH3,CH0
Sample
AN3
AN0
AN1
AN2
AN3
AN4
AN4
AN5
AN5
AN6(1)
AN6
AN7(1)
AN7
AN8(1)
AN8
+
AN1
-
Input
Switches
S/H
Sample/Sequence
Control
Bus Interface
AN1
AN0
AN3
Data
Format
AN0
Input MUX
Control
CH0
Note 1: Not available on dsPIC30F4012 devices.
DS70135G-page 140
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
20.1
A/D Result Buffer
The module contains a 16-word, dual port, read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D
results. The RAM is 10 bits wide, but is read into different
format 16-bit words. The contents of the sixteen A/D
Conversion Result Buffer registers, ADCBUF0 through
ADCBUFF, cannot be written by user software.
20.2
Conversion Operation
After the ADC module has been configured, the sample
acquisition is started by setting the SAMP bit. Various
sources, such as a programmable bit, timer time-outs
and external events, terminate acquisition and start a
conversion. When the A/D conversion is complete, the
result is loaded into ADCBUF0...ADCBUFF, and the A/D
Interrupt Flag, ADIF, and the DONE bit are set after the
number of samples specified by the SMPI bits.
The following steps should be followed for doing an
A/D conversion:
1.
2.
3.
4.
5.
6.
7.
Configure the ADC module:
- Configure analog pins, voltage reference
and digital I/O
- Select A/D input channels
- Select A/D conversion clock
- Select A/D conversion trigger
- Turn on ADC module
Configure the A/D interrupt (if required):
- Clear ADIF bit
- Select A/D interrupt priority
Start sampling.
Wait the required acquisition time.
Trigger acquisition end, start conversion.
Wait for A/D conversion to complete by either:
- Waiting for the A/D interrupt
- Waiting for the DONE bit to get set
Read A/D result buffer, clear ADIF if required.
20.3
Selecting the Conversion
Sequence
Several groups of control bits select the sequence in
which the A/D connects inputs to the sample/hold
channels, converts channels, writes the buffer memory
and generates interrupts. The sequence is controlled
by the sampling clocks.
The SIMSAM bit controls the acquire/convert
sequence for multiple channels. If the SIMSAM bit is
‘0’, the two or four selected channels are acquired and
converted sequentially with two or four sample clocks.
If the SIMSAM bit is ‘1’, two or four selected channels
are acquired simultaneously with one sample clock.
The channels are then converted sequentially.
Obviously, if there is only 1 channel selected, the
SIMSAM bit is not applicable.
© 2010 Microchip Technology Inc.
The CHPS bits select how many channels are
sampled. This selection can vary from 1, 2 or 4 channels.
If the CHPS bits select 1 channel, the CH0 channel is
sampled at the sample clock and converted. The result is
stored in the buffer. If the CHPS bits select 2 channels,
the CH0 and CH1 channels are sampled and converted.
If the CHPS bits select 4 channels, the CH0, CH1, CH2
and CH3 channels are sampled and converted.
The SMPI bits select the number of acquisition/
conversion sequences that would be performed before
an interrupt occurs. This can vary from 1 sample per
interrupt to 16 samples per interrupt.
The user cannot program a combination of CHPS and
SMPI bits that specifies more than 16 conversions per
interrupt, or 8 conversions per interrupt, depending
on the BUFM bit. The BUFM bit, when set, splits the
16-word results buffer (ADCBUF0 to ADCBUFF) into
two, 8-word groups. Writing to the 8-word buffers is
alternated on each interrupt event. Use of the BUFM bit
depends on how much time is available for moving data
out of the buffers after the interrupt, as determined by
the application.
If the processor can quickly unload a full buffer within
the time it takes to acquire and convert one channel,
the BUFM bit can be ‘0’ and up to 16 conversions
may be done per interrupt. The processor has one
sample-and-conversion time to move the sixteen
conversions.
If the processor cannot unload the buffer within the
acquisition and conversion time, the BUFM bit should be
‘1’. For example, if SMPI (ADCON2) = 0111,
then eight conversions are loaded into half of the buffer,
following which an interrupt occurs. The next eight
conversions are loaded into the other half of the buffer.
The processor has the entire time between interrupts to
move the eight conversions.
The ALTS bit can be used to alternate the inputs
selected during the sampling sequence. The input
multiplexer has two sets of sample inputs: MUX A and
MUX B. If the ALTS bit is ‘0’, only the MUX A inputs are
selected for sampling. If the ALTS bit is ‘1’ and
SMPI = 0000, on the first sample/convert
sequence, the MUX A inputs are selected, and on the
next acquire/convert sequence, the MUX B inputs are
selected.
The CSCNA bit (ADCON2) allows the CH0
channel inputs to be alternately scanned across a
selected number of analog inputs for the MUX A group.
The inputs are selected by the ADCSSL register. If a
particular bit in the ADCSSL register is ‘1’, the corresponding input is selected. The inputs are always
scanned from lower to higher numbered inputs, starting
after each interrupt. If the number of inputs selected is
greater than the number of samples taken per interrupt,
the higher numbered inputs are unused.
DS70135G-page 141
dsPIC30F4011/4012
20.4
Programming the Start of the
Conversion Trigger
The conversion trigger terminates acquisition and starts
the requested conversions.
The SSRC bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC = 000, the conversion trigger is
under software control. Clearing the SAMP bit causes
the conversion trigger.
When SSRC = 111 (Auto-Start mode), the conversion trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least one clock cycle.
Other trigger sources can come from timer modules,
motor control PWM module or external interrupts.
Note:
To operate the ADC at the maximum
specified conversion speed, the autoconvert trigger option should be selected
(SSRC = 111) and the auto-sample
time bits should be set to ‘1’ TAD
(SAMC = 00001). This configuration gives
a total conversion period (sample +
convert) of 13 TAD.
The use of any other conversion trigger
results in additional TAD cycles to
synchronize the external event to the
ADC.
20.5
Aborting a Conversion
Clearing the ADON bit during a conversion aborts the
current conversion and stops the sampling sequencing.
The ADCBUFx is not updated with the partially completed A/D conversion sample. That is, the ADCBUFx
will continue to contain the value of the last completed
conversion (or the last value written to the ADCBUFx
register).
20.6
Selecting the A/D Conversion
Clock
The A/D conversion requires 12 TAD. The source of the
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for TAD.
EQUATION 20-1:
A/D CONVERSION CLOCK
TAD = TCY * (0.5 * (ADCS + 1))
TAD
ADCS = 2
–1
TCY
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 83.33 nsec (for VDD = 5V). Refer to Section 24.0
“Electrical Characteristics” for minimum TAD under
other operating conditions.
Example 20-1 shows a sample calculation for the
ADCS bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 20-1:
A/D CONVERSION CLOCK
CALCULATION
TAD = 154 nsec
TCY = 33 nsec (30 MIPS)
TAD
–1
TCY
154 nsec
=2•
–1
33 nsec
= 8.33
ADCS = 2
Therefore,
Set ADCS = 9
TCY
(ADCS + 1)
2
33 nsec
=
(9 + 1)
2
Actual TAD =
= 165 nsec
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 TAD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D continues at
the next sample pulse, which corresponds with the next
channel converted. If simultaneous sampling is specified, the A/D continues with the next multichannel
group conversion sequence.
DS70135G-page 142
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
20.7
A/D Conversion Speeds
The dsPIC30F 10-bit ADC specifications permit
a maximum 1 Msps sampling rate. Table 20-1
summarizes the conversion speeds for the dsPIC30F
10-bit ADC and the required operating conditions.
TABLE 20-1:
10-BIT A/D CONVERSION RATE PARAMETERS
dsPIC30F 10-bit A/D Converter Conversion Rates
A/D
Speed
Up to
1 Msps(1)
TAD
Sampling
RS Max.
Minimum Time Min.
83.33 ns
12 TAD
500Ω
VDD
Temperature
4.5V
to
5.5V
-40°C to +85°C
A/D Channels Configuration
VREF- VREF+
ANx
CH1, 2 or 3
S/H
ADC
CH0
S/H
Up to
750
ksps(1)
95.24 ns
2 TAD
500Ω
4.5V
to
5.5V
-40°C to +85°C
VREF- VREF+
ANx
Up to
600
ksps(1)
138.89 ns
12 TAD
500Ω
3.0V
to
5.5V
CHX
S/H
ADC
-40°C to +125°C
VREF- VREF+
ANx
CH1, 2 or 3
S/H
ADC
CH0
S/H
Up to
500 ksps
153.85 ns
1 TAD
5.0 kΩ
4.5V
to
5.5V
-40°C to +125°C
VREF- VREF+
or
or
AVSS AVDD
ANx
CHX
S/H
ADC
ANx or VREF-
Up to
300 ksps
256.41 ns
1 TAD
5.0 kΩ
3.0V
to
5.5V
-40°C to +125°C
VREF- VREF+
or
or
AVSS AVDD
ANx
CHX
S/H
ADC
ANx or VREF-
Note 1:
External VREF- and VREF+ pins must be used for correct operation. See Figure 20-2 for recommended
circuit.
© 2010 Microchip Technology Inc.
DS70135G-page 143
dsPIC30F4011/4012
The configuration guidelines give the required setup
values for the conversion speeds above 500 ksps,
since they require external VREF pins usage and there
are some differences in the configuration procedure.
Configuration details that are not critical to the
conversion speed have been omitted.
Figure 20-2 illustrates the recommended circuit for the
conversion rates above 500 ksps.
FIGURE 20-2:
A/D CONVERTER VOLTAGE REFERENCE SCHEMATIC
1
VDD
VSS
VDD
34
VDD
VSS
44
VDD
33
dsPIC30F4011
VSS
VDD
VDD
VREF+
VREF-
23
22
AVSS
AVDD
11
12
VDD
VDD
VDD
R2
10
VDD
C2
0.1 μF
20.7.1
1 Msps CONFIGURATION
GUIDELINE
Single Analog Input
For conversions at 1 Msps for a single analog input, at
least two sample and hold channels must be enabled.
The analog input multiplexer must be configured so
that the same input pin is connected to both sample
and hold channels. The A/D converts the value held on
one S&H channel while the second S&H channel
acquires a new input sample.
DS70135G-page 144
R1
10
VDD
C7
0.1 μF
VDD
C5
1 μF
C6
0.01 μF
VDD
C4
0.1 μF
C3
0.01 μF
C1
0.01 μF
The configuration for 1 Msps operation is dependent on
whether a single input pin is to be sampled or whether
multiple pins are to be sampled.
20.7.1.1
VDD
C8
1 μF
20.7.1.2
Multiple Analog Inputs
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 1 Msps conversion rate is divided among
the different input signals. For example, four inputs can
be sampled at a rate of 250 ksps for each signal, or two
inputs could be sampled at a rate of 500 ksps for each
signal. Sequential sampling must be used in this
configuration to allow adequate sampling time on each
input.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
20.7.1.3
1 Msps Configuration Items
The following configuration items are required to
achieve a 1 Msps conversion rate.
• Comply with conditions provided in Table 20-2
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 20-2
• Set SSRC = 111 in the ADCON1 register to
enable the auto-convert option
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Enable sequential sampling by clearing the
SIMSAM bit in the ADCON1 register
• Enable at least two sample and hold channels by
writing the CHPS control bits in the
ADCON2 register
• Write the SMPI control bits in the ADCON2
register for the desired number of conversions
between interrupts. At a minimum, set SMPI
= 0001 since at least two sample and hold channels should be enabled
• Configure the A/D clock period to be:
1
= 83.33 ns
12 x 1,000,000
by writing to the ADCS control bits in the
ADCON3 register
• Configure the sampling time to be 2 TAD by
writing: SAMC = 00010
• Select at least two channels per analog input pin
by writing to the ADCHS register
20.7.2
750 ksps CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 750 ksps conversion rate. This configuration
assumes that a single analog input is to be sampled.
• Comply with conditions provided in Table 20-2
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 20-2
• Set SSRC = 111 in the ADCON1 register to
enable the auto-convert option
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Enable one sample and hold channel by setting
CHPS = 00 in the ADCON2 register
• Write the SMPI control bits in the ADCON2
register for the desired number of conversions
between interrupts
• Configure the A/D clock period to be:
1
= 95.24 ns
(12 + 2) x 750,000
by writing to the ADCS control bits in the
ADCON3 register
• Configure the sampling time to be 2 TAD by
writing: SAMC = 00010
© 2010 Microchip Technology Inc.
20.7.3
600 ksps CONFIGURATION
GUIDELINE
The configuration for 600 ksps operation is dependent
on whether a single input pin is to be sampled or
whether multiple pins are to be sampled.
20.7.3.1
Single Analog Input
When performing conversions at 600 ksps for a single
analog input, at least two sample and hold channels
must be enabled. The analog input multiplexer must be
configured so that the same input pin is connected to
both sample and hold channels. The ADC converts the
value held on one S/H channel, while the second S/H
channel acquires a new input sample.
20.7.3.2
Multiple Analog Input
The ADC can also be used to sample multiple analog
inputs using multiple sample and hold channels. In this
case, the total 600 ksps conversion rate is divided
among the different input signals. For example, four
inputs can be sampled at a rate of 150 ksps for each
signal or two inputs can be sampled at a rate of
300 ksps for each signal. Sequential sampling must be
used in this configuration to allow adequate sampling
time on each input.
20.7.3.3
600 ksps Configuration Items
The following configuration items are required to
achieve a 600 ksps conversion rate.
• Comply with conditions provided in Table 20-2
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 20-2
• Set SSRC = 111 in the ADCON1 register to
enable the auto-convert option
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register
• Enable sequential sampling by clearing the
SIMSAM bit in the ADCON1 register
• Enable at least two sample and hold channels by
writing the CHPS control bits in the
ADCON2 register
• Write the SMPI control bits in the ADCON2
register for the desired number of conversions
between interrupts. At a minimum, set
SMPI = 0001 since at least two sample and
hold channels should be enabled
• Configure the A/D clock period to be:
1
= 138.89 ns
12 x 600,000
by writing to the ADCS control bits in the
ADCON3 register
• Configure the sampling time to be 2 TAD by
writing: SAMC = 00010
Select at least two channels per analog input pin by
writing to the ADCHS register.
DS70135G-page 145
dsPIC30F4011/4012
20.8
A/D Acquisition Requirements
The analog input model of the 10-bit ADC is shown in
Figure 20-3. The total sampling time for the ADC is a
function of the internal amplifier settling time, device
VDD and the holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
source impedance (RS), the interconnect impedance
(RIC) and the internal sampling switch (RSS) impedance
combine to directly affect the time required to charge the
capacitor CHOLD. The combined impedance of the analog sources must therefore be small enough to fully
charge the holding capacitor within the chosen sample
time. To minimize the effects of pin leakage currents on
the accuracy of the ADC, the maximum recommended
source impedance, RS, is 5 kΩ. After the analog input
channel is selected (changed), this sampling function
must be completed prior to starting the conversion. The
internal holding capacitor will be in a discharged state
prior to each sample operation.
FIGURE 20-3:
The user must allow at least 1 TAD period of sampling
time, TSAMP, between conversions to allow each sample to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the ADC. In an
automatic configuration, the user must allow enough
time between conversion triggers so that the minimum
sample time can be satisfied. Refer to Section 24.0
“Electrical Characteristics” for TAD and sample time
requirements.
A/D CONVERTER ANALOG INPUT MODEL
VDD
Rs
VA
ANx
CPIN
RIC ≤250Ω
VT = 0.6V
Sampling
Switch
RSS ≤3 kΩ
RSS
VT = 0.6V
ILEAKAGE
±500 nA
CHOLD
= DAC Capacitance
= 4.4 pF
VSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
I leakage = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Sampling Switch Resistance
RSS
= Sample/Hold Capacitance (from DAC)
CHOLD
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤5 kΩ.
DS70135G-page 146
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
20.9
Module Power-Down Modes
If the A/D interrupt is enabled, the device wakes up
from Sleep. If the A/D interrupt is not enabled, the ADC
module is then turned off, although the ADON bit
remains set.
The module has 3 internal power modes. When the
ADON bit is ‘1’, the module is in Active mode; it is fully
powered and functional. When ADON is ‘0’, the module
is in Off mode. The digital and analog portions of the
circuit are disabled for maximum current savings. In
order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
20.10.2
The ADSIDL bit selects if the module stops on Idle or
continues on Idle. If ADSIDL = 0, the module continues
operation on assertion of Idle mode. If ADSIDL = 1, the
module stops on Idle.
20.10 A/D Operation During CPU Sleep
and Idle Modes
20.10.1
20.11 Effects of a Reset
A/D OPERATION DURING CPU
SLEEP MODE
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and acquisition sequence is aborted. The
values that are in the ADCBUFx registers are not
modified. The A/D Result register contains unknown
data after a Power-on Reset.
When the device enters Sleep mode, all clock sources
to the module are shut down and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the
conversion is aborted. The converter will not continue
with a partially completed conversion on exit from
Sleep mode.
20.12 Output Formats
Register contents are not affected by the device
entering or leaving Sleep mode.
The A/D result is 10 bits wide. The data buffer RAM is
also 10 bits wide. The 10-bit data can be read in one of
four different formats. The FORM bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
The ADC module can operate during Sleep mode if the
A/D clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits
one instruction cycle before starting the conversion.
This allows the SLEEP instruction to be executed,
which eliminates all digital switching noise from the
conversion. When the conversion is complete, the
DONE bit is set and the result is loaded into the
ADCBUFx register.
FIGURE 20-4:
A/D OPERATION DURING CPU IDLE
MODE
Write data will always be in right justified (integer)
format.
A/D OUTPUT DATA FORMATS
RAM Contents:
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
Read to Bus:
Signed Fractional (1.15)
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
Fractional (1.15)
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
Signed Integer
Integer
© 2010 Microchip Technology Inc.
d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
DS70135G-page 147
dsPIC30F4011/4012
20.13 Configuring Analog Port Pins
20.14 Connection Considerations
The use of the ADPCFG and TRIS registers control the
operation of the ADC port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bit set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) is converted.
The analog inputs have diodes to VDD and VSS as ESD
protection. This requires that the analog input be
between VDD and VSS. If the input voltage exceeds this
range by greater than 0.3V (either direction), one of the
diodes becomes forward biased and it may damage the
device if the input current specification is exceeded.
The A/D operation is independent of the state of the
CH0SA/CH0SB bits and the TRIS bits.
When reading the PORT register, all pins configured as
analog input channels are read as cleared.
Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
DS70135G-page 148
An external RC filter is sometimes added for antialiasing of the input signal. The R component should be
selected to ensure that the sampling time requirements
are satisfied. Any external components connected (via
high-impedance) to an analog input pin (capacitor,
zener diode, etc.) should have very little leakage
current at the pin.
© 2010 Microchip Technology Inc.
© 2010 Microchip Technology Inc.
TABLE 20-2:
SFR Name
ADC REGISTER MAP(1)
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
ADCBUF0
0280
—
—
—
—
—
—
ADC Data Buffer 0
0000 00uu uuuu uuuu
ADCBUF1
0282
—
—
—
—
—
—
ADC Data Buffer 1
0000 00uu uuuu uuuu
ADCBUF2
0284
—
—
—
—
—
—
ADC Data Buffer 2
0000 00uu uuuu uuuu
ADCBUF3
0286
—
—
—
—
—
—
ADC Data Buffer 3
0000 00uu uuuu uuuu
ADCBUF4
0288
—
—
—
—
—
—
ADC Data Buffer 4
0000 00uu uuuu uuuu
ADCBUF5
028A
—
—
—
—
—
—
ADC Data Buffer 5
0000 00uu uuuu uuuu
ADCBUF6
028C
—
—
—
—
—
—
ADC Data Buffer 6
0000 00uu uuuu uuuu
ADCBUF7
028E
—
—
—
—
—
—
ADC Data Buffer 7
0000 00uu uuuu uuuu
ADCBUF8
0290
—
—
—
—
—
—
ADC Data Buffer 8
0000 00uu uuuu uuuu
ADCBUF9
0292
—
—
—
—
—
—
ADC Data Buffer 9
0000 00uu uuuu uuuu
ADCBUFA
0294
—
—
—
—
—
—
ADC Data Buffer 10
0000 00uu uuuu uuuu
ADCBUFB
0296
—
—
—
—
—
—
ADC Data Buffer 11
0000 00uu uuuu uuuu
ADCBUFC
0298
—
—
—
—
—
—
ADC Data Buffer 12
0000 00uu uuuu uuuu
ADCBUFD
029A
—
—
—
—
—
—
ADC Data Buffer 13
0000 00uu uuuu uuuu
ADCBUFE
029C
—
—
—
—
—
—
ADC Data Buffer 14
0000 00uu uuuu uuuu
ADCBUFF
029E
—
—
—
—
—
—
ADC Data Buffer 15
ADCON1
02A0
ADON
—
ADSIDL
—
—
—
FORM
ADCON2
02A2
—
—
CSCNA
CHPS
VCFG
SSRC
BUFS
—
ADRC
—
02A4
ADCHS
02A6
ADPCFG
02A8
—
ADCSSL
02AA
—
Legend:
Note 1:
2:
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
These bits are not available on dsPIC30F4012 devices.
—
—
CH123NB
—
SAMC
CH123SB
CH0NB
CH0SB
—
—
—
—
—
—
—
—
—
—
—
—
CH123NA
0000 00uu uuuu uuuu
SIMSAM
ASAM
SMPI
SAMP
DONE
0000 0000 0000 0000
BUFM
ALTS
0000 0000 0000 0000
ADCS
0000 0000 0000 0000
CH123SA
CH0NA
CH0SA
PCFG8(2) PCFG7(2) PCFG6(2)
PCFG5
PCFG4
PCFG3
PCFG2 PCFG1 PCFG0
0000 0000 0000 0000
CSSL8(2) CSSL7(2) CSSL6(2)
CSSL5
CSSL4
CSSL3
CSSL2
0000 0000 0000 0000
CSSL1
0000 0000 0000 0000
CSSL0
DS70135G-page 149
dsPIC30F4011/4012
ADCON3
—
dsPIC30F4011/4012
NOTES:
DS70135G-page 150
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
21.0
Note:
SYSTEM INTEGRATION
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
There are several features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Programmable Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• Power-Saving Modes (Sleep and Idle)
• Code Protection
• Unit ID Locations
• In-Circuit Serial Programming (ICSP)
21.1
Oscillator System Overview
The dsPIC30F oscillator system has the following
modules and features:
• Various external and internal oscillator options as
clock sources
• An on-chip PLL to boost internal operating
frequency
• A clock switching mechanism between various
clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• Oscillator Control register (OSCCON)
• Configuration bits for main oscillator selection
Table 21-1 provides a summary of the dsPIC30F
oscillator operating modes. A simplified diagram of the
oscillator system is shown in Figure 21-1.
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, the clock source can be changed between
permissible clock sources. The OSCCON register
controls the clock switching and reflects system clock
related status bits.
dsPIC30F devices have a Watchdog Timer which is
permanently enabled via the Configuration bits, or can
be software controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in Reset until the
crystal oscillator is stable. The other is the Power-up
Timer (PWRT), which provides a delay on power-up
only, designed to keep the part in Reset while the power
supply stabilizes. With these two timers on-chip, most
applications need no external Reset circuitry.
Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit a wide variety of
applications. In the Idle mode, the clock sources are
still active, but the CPU is shut off. The RC oscillator
option saves system cost, while the LP crystal option
saves power.
© 2010 Microchip Technology Inc.
DS70135G-page 151
dsPIC30F4011/4012
TABLE 21-1:
OSCILLATOR OPERATING MODES
Oscillator Mode
XTL
Description
200 kHz-4 MHz crystal on OSC1:OSC2
XT
4 MHz-10 MHz crystal on OSC1:OSC2
XT w/PLL 4x
4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled
XT w/PLL 8x
4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled
XT w/PLL 16x
4 MHz-10 MHz crystal on OSC1:OSC2, 16x PLL enabled(1)
LP
32 kHz crystal on SOSCO:SOSCI(2)
HS
10 MHz-25 MHz crystal
EC
External clock input (0-40 MHz)
ECIO
External clock input (0-40 MHz), OSC2 pin is I/O
EC w/PLL 4x
External clock input (0-40 MHz), OSC2 pin is I/O, 4x PLL enabled(1)
EC w/PLL 8x
External clock input (0-40 MHz), OSC2 pin is I/O, 8x PLL enabled(1)
EC w/PLL 16x
External clock input (0-40 MHz), OSC2 pin is I/O, 16x PLL enabled(1)
ERC
External RC oscillator, OSC2 pin is FOSC/4 output(3)
ERCIO
External RC oscillator, OSC2 pin is I/O(3)
FRC
8 MHz internal RC oscillator
FRC w/PLL 4x
7.37 MHz Internal RC oscillator, 4x PLL enabled
FRC w/PLL 8x
7.37 MHz Internal RC oscillator, 8x PLL enabled
FRC w/PLL 16x
7.37 MHz Internal RC oscillator, 16x PLL enabled
LPRC
512 kHz internal RC oscillator
Note 1:
2:
3:
The dsPIC30F maximum operating frequency of 120 MHz must be met.
LP oscillator can be conveniently shared as a system clock, as well as a Real-Time Clock for Timer1.
Requires external R and C. Frequency operation up to 4 MHz.
DS70135G-page 152
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 21-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
Oscillator Configuration bits
PWRSAV Instruction
Wake-up Request
FPLL
OSC1
OSC2
Primary
Oscillator
PLL
x4, x8, x16
PLL
Lock
COSC
Primary Osc
NOSC
Primary
Oscillator
Stability Detector
POR Done
OSWEN
Oscillator
Start-up
Timer
Clock
Secondary Osc
Switching
and Control
Block
SOSCO
SOSCI
32 kHz LP
Oscillator
Secondary
Oscillator
Stability Detector
Programmable
Clock Divider System
Clock
2
POST
FRC
Internal Fast RC
Oscillator (FRC)
Internal
Low-Power RC
Oscillator (LPRC)
FCKSM
2
LPRC
Fail-Safe Clock
Monitor (FSCM)
CF
Oscillator Trap
to Timer1
© 2010 Microchip Technology Inc.
DS70135G-page 153
dsPIC30F4011/4012
21.2
Oscillator Configurations
21.2.1
21.2.2
INITIAL CLOCK SOURCE
SELECTION
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an Oscillator
Start-up Timer (OST) is included. It is a simple, 10-bit
counter that counts 1024 TOSC cycles before releasing
the oscillator clock to the rest of the system. The timeout period is designated as TOST. The TOST time is
involved every time the oscillator has to restart (i.e., on
POR, BOR and wake-up from Sleep). The Oscillator
Start-up Timer is applied to the LP, XT, XTL and HS
modes (upon wake-up from Sleep, POR and BOR) for
the primary oscillator.
While coming out of Power-on Reset or Brown-out
Reset, the device selects its clock source based on:
a)
The FOS Configuration bits that select one
of four oscillator groups.
The FPR Configuration bits that select one
of 13 oscillator choices within the primary group.
b)
The selection is as shown in Table 21-2.
TABLE 21-2:
OSCILLATOR START-UP TIMER
(OST)
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator
Source
FOS1
FOS0
FPR3
FPR2
FPR1
FPR0
OSC2
Function
EC
Primary
1
1
1
0
1
1
CLKO
ECIO
Primary
1
1
1
1
0
0
I/O
EC w/PLL 4x
Primary
1
1
1
1
0
1
I/O
EC w/PLL 8x
Primary
1
1
1
1
1
0
I/O
EC w/PLL 16x
Primary
1
1
1
1
1
1
I/O
ERC
Primary
1
1
1
0
0
1
CLKO
ERCIO
Primary
1
1
1
0
0
0
I/O
XT
Primary
1
1
0
1
0
0
OSC2
XT w/PLL 4x
Primary
1
1
0
1
0
1
OSC2
XT w/PLL 8x
Primary
1
1
0
1
1
0
OSC2
XT w/PLL 16x
Primary
1
1
0
1
1
1
OSC2
XTL
Primary
1
1
0
0
0
0
OSC2
HS
Primary
1
1
0
0
1
0
OSC2
FRC w/PLL 4x
Primary
1
1
0
0
0
1
I/O
FRC w/PLL 8x
Primary
1
1
1
0
1
0
I/O
FRC w/PLL 16x
Primary
1
1
0
0
1
1
I/O
LP
Secondary
0
0
—
—
—
—
(Notes 1, 2)
FRC
Internal FRC
0
1
—
—
—
—
(Notes 1, 2)
LPRC
Internal LPRC
1
0
—
—
—
—
(Notes 1, 2)
Note 1:
2:
OSC2 pin function is determined by the Primary Oscillator mode selection (FPR).
Note that the OSC1 pin cannot be used as an I/O pin, even if the secondary oscillator or an internal clock
source is selected at all times.
DS70135G-page 154
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
21.2.3
LP OSCILLATOR CONTROL
Enabling the LP oscillator is controlled with two
elements:
• Current oscillator group bits, COSC
• LPOSCEN bit (OSCCON)
The LP oscillator is on (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if:
• COSC = 00 (LP selected as main osc.) and
• LPOSCEN = 1
Keeping the LP oscillator on at all times allows for a
fast switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator still
requires a start-up time.
21.2.4
PHASE LOCKED LOOP (PLL)
The PLL multiplies the clock which is generated by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8 or x16. Input and output frequency
ranges are summarized in Table 21-3.
TABLE 21-3:
FIN
4 MHz-10 MHz
4 MHz-10 MHz
4 MHz-7.5 MHz
PLL FREQUENCY RANGE
PLL
Multiplier
x4
x8
x16
FOUT
16 MHz-40 MHz
32 MHz-80 MHz
64 MHz-120 MHz
The PLL features a lock output which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal is
rescinded. The state of this signal is reflected in the
read-only LOCK bit in the OSCCON register.
21.2.5
FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (7.37 MHz, ±2% nominal),
internal RC oscillator. This oscillator is intended to
provide reasonable device operating speeds without
the use of an external crystal, ceramic resonator or RC
network. Using the x4, x8 and x16 PLL options, higher
operational frequencies can be generated.
The dsPIC30F operates from the FRC oscillator whenever the Current Oscillator Selection (COSC)
control
bits
in
the
OSCCON
register
(OSCCON) are set to ‘01’.
There are four tuning bits (TUN) for the FRC
oscillator in the OSCCON register. These tuning bits
allow the FRC oscillator frequency to be adjusted as
close to 7.37 MHz as possible, depending on the
device operating conditions. The FRC oscillator
frequency has been calibrated during factory testing.
Table 21-4 describes the adjustment range of the
TUN bits.
Note:
TABLE 21-4:
TUN
Bits
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
21.2.6
FRC TUNING
FRC Frequency
+10.5%
+9.0%
+7.5%
+6.0%
+4.5%
+3.0%
+1.5%
Center Frequency (oscillator is
running at calibrated frequency)
-1.5%
-3.0%
-4.5%
-6.0%
-7.5%
-9.0%
-10.5%
-12.0%
LOW-POWER RC OSCILLATOR (LPRC)
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT and clock
monitor circuits. It may also be used to provide a lowfrequency clock source option for applications where
power consumption is critical and timing accuracy is
not required.
The LPRC oscillator is always enabled at a POR
because it is the clock source for the PWRT. After the
PWRT expires, the LPRC oscillator remains on if one
of the following is true:
• The Fail-Safe Clock Monitor is enabled
• The WDT is enabled
• The LPRC oscillator is selected as the system
clock via the COSC control bits in the
OSCCON register
If one of the above conditions is not true, the LPRC
shuts off after the PWRT expires.
Note 1: OSC2 pin function is determined by the
Primary Oscillator mode selection
(FPR).
2: Note that OSC1 pin cannot be used as an
I/O pin, even if the secondary oscillator or
an internal clock source is selected at all
times.
OSCTUN functionality has been provided
to help customers compensate for
temperature effects on the FRC frequency
over a wide range of temperatures. The
tuning step size is an approximation and is
neither characterized nor tested.
© 2010 Microchip Technology Inc.
DS70135G-page 155
dsPIC30F4011/4012
21.2.7
FAIL-SAFE CLOCK MONITOR
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by appropriately
programming the FCKSM Configuration bits
(Clock Switch and Monitor Selection bits) in the FOSC
device Configuration register. If the FSCM function is
enabled, the LPRC internal oscillator runs at all times
(except during Sleep mode) and is not subject to
control by the SWDTEN bit.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. The user then
has the option to either attempt to restart the oscillator
or execute a controlled shutdown. The user may decide
to treat the trap as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector. In this
event, the CF (Clock Fail) status bit (OSCCON) is
also set whenever a clock failure is recognized.
In the event of a clock failure, the WDT is unaffected
and continues to run on the LPRC clock.
If the oscillator has a very slow start-up time coming
out of POR, BOR or Sleep, it is possible that the
PWRT timer will expire before the oscillator has
started. In such cases, the FSCM is activated. The
FSCM initiates a clock failure trap, and the
COSC bits are loaded with the Fast RC (FRC)
oscillator selection. This effectively shuts off the
original oscillator that was trying to start.
The OSCCON register holds the control and status bits
related to clock switching.
• COSC: Read-only status bits always reflect
the current oscillator group in effect.
• NOSC: Control bits which are written to
indicate the new oscillator group of choice.
- On POR and BOR, COSC and
NOSC are both loaded with the
Configuration bit values, FOS.
• LOCK: The LOCK status bit indicates a PLL lock.
• CF: Read-only status bit indicating if a clock fail
detect has occurred.
• OSWEN: Control bit changes from a ‘0’ to a ‘1’
when a clock transition sequence is initiated.
Clearing the OSWEN control bit aborts a clock
transition in progress (used for hang-up
situations).
If Configuration bits, FCKSM = 1x, then the clock
switching and Fail-Safe Clock Monitor functions are
disabled. This is the default Configuration bit setting.
If clock switching is disabled, then the FOS and
FPR bits directly control the oscillator selection,
and the COSC bits do not control the clock
selection. However, these bits do reflect the clock
source selection.
Note:
The user may detect this situation and restart the
oscillator in the clock fail trap Interrupt Service Routine
(ISR).
Upon a clock failure detection, the FSCM module
initiates a clock switch to the FRC oscillator as follows:
1.
2.
3.
The COSC bits (OSCCON) are
loaded with the FRC oscillator selection value.
CF bit is set (OSCCON).
OSWEN control bit (OSCCON) is cleared.
For the purpose of clock switching, the clock sources
are sectioned into four groups:
•
•
•
•
Primary
Secondary
Internal FRC
Internal LPRC
The user can switch between these functional groups
but cannot switch between options within a group. If the
primary group is selected, then the choice within the
group is always determined by the FPR
Configuration bits.
21.2.8
The application should not attempt to
switch to a clock of frequency lower than
100 kHz when the Fail-Safe Clock Monitor
is enabled. If such clock switching is
performed, the device may generate an
oscillator fail trap and switch to the Fast
RC (FRC) oscillator.
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
Byte Write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte Write 0x78 to OSCCON high
Byte Write 0x9A to OSCCON high
Byte Write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
DS70135G-page 156
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
21.3
Reset
21.3.1
The dsPIC30F4011/4012 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lock-up (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 21-5. These bits
are used in software to determine the nature of the
Reset.
POR: POWER-ON RESET
A power-on event generates an internal POR pulse
when a VDD rise is detected. The Reset pulse occurs at
the POR circuit threshold voltage (VPOR) which is nominally 1.85V. The device supply voltage characteristics
must meet specified starting voltage and rise rate
requirements. The POR pulse resets a POR timer and
places the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator Configuration fuses.
The POR circuit inserts a small delay, TPOR, which is
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (TPWRT) is applied. The TPWRT
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up, TPOR + TPWRT. When
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock and the PC jumps
to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
A block diagram of the on-chip Reset circuit is shown in
Figure 21-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
FIGURE 21-2:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Digital
Glitch Filter
MCLR
Sleep or Idle
WDT
Module
POR
VDD Rise
Detect
S
VDD
Brown-out
Reset
BOR
BOREN
R
Q
SYSRST
Trap Conflict
Illegal Opcode/
Uninitialized W Register
© 2010 Microchip Technology Inc.
DS70135G-page 157
dsPIC30F4011/4012
FIGURE 21-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL RESET
FIGURE 21-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 21-5:
VDD
MCLR
INTERNAL POR
TOST
OST TIME-OUT
TPWRT
PWRT TIME-OUT
INTERNAL RESET
DS70135G-page 158
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
21.3.1.1
POR with Long Crystal Start-up Time
(with FSCM Enabled)
The oscillator start-up circuitry is not linked to the POR
circuitry. Some crystal circuits (especially lowfrequency crystals) have a relatively long start-up time.
Therefore, one or more of the following conditions is
possible after the POR timer and the PWRT have
expired:
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FOS and
FPR). Furthermore, if an oscillator mode is
selected, the BOR activates the Oscillator Start-up
Timer (OST). The system clock is held until OST
expires. If the PLL is used, then the clock is held until
the LOCK bit (OSCCON) is ‘1’.
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
Concurrently, the POR time-out (TPOR) and the PWRT
time-out (TPWRT) are applied before the internal Reset
is released. If TPWRT = 0 and a crystal oscillator is
being used, then a nominal delay of TFSCM = 100 μs is
applied. The total delay in this case is (TPOR + TFSCM).
If the FSCM is enabled and one of the above conditions
is true, then a clock failure trap occurs. The device
automatically switches to the FRC oscillator and the
user can switch to the desired crystal oscillator in the
trap ISR.
The BOR status bit (RCON) is set to indicate that a
BOR has occurred. The BOR circuit, if enabled, continues to operate while in Sleep or Idle modes and resets
the device if VDD falls below the BOR threshold voltage.
21.3.1.2
Operating without FSCM and PWRT
FIGURE 21-6:
If the FSCM is disabled and the Power-up Timer
(PWRT) is also disabled, then the device exits rapidly
from Reset on power-up. If the clock source is FRC,
LPRC, ERC or EC, it will be active immediately.
VDD
D
If the FSCM is disabled and the system clock has not
started, the device will be in a frozen state at the Reset
vector until the system clock starts. From the user’s
perspective, the device will appear to be in Reset until
a system clock is available.
21.3.2
BOR: PROGRAMMABLE
BROWN-OUT RESET
• 2.6V-2.71V
• 4.1V-4.4V
• 4.58V-4.73V
Note:
R
R1
MCLR
C
dsPIC30F
Note 1:
External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2:
R should be suitably chosen so as to make
sure that the voltage drop across R does not
violate the device’s electrical specification.
3:
R1 should be suitably chosen so as to limit
any current flowing into MCLR from external
capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD)
or Electrical Overstress (EOS).
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned
on).
The BOR module allows selection of one of the
following voltage trip points (see Table 24-10):
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note:
Dedicated supervisory devices, such as
the MCP1XX and MCP8XX, may also be
used as an external Power-on Reset
circuit.
The BOR voltage trip points indicated here
are nominal values provided for design
guidance only.
© 2010 Microchip Technology Inc.
DS70135G-page 159
dsPIC30F4011/4012
Table 21-5 lists the Reset conditions for the RCON
Register. Since the control bits within the RCON register are R/W, the information in the table implies that all
the bits are negated prior to the action specified in the
condition column.
TABLE 21-5:
INITIALIZATION CONDITION FOR RCON REGISTER, CASE 1
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
0x000000
Brown-out Reset
0x000000
0
0
0
0
0
0
0
0
1
MCLR Reset during normal
operation
0x000000
0
0
1
0
0
0
0
0
0
Software Reset during
normal operation
0x000000
0
0
0
1
0
0
0
0
0
MCLR Reset during Sleep
0x000000
0
0
1
0
0
0
1
0
0
MCLR Reset during Idle
0x000000
0
0
1
0
0
1
0
0
0
WDT Time-out Reset
0x000000
0
0
0
0
1
0
0
0
0
WDT Wake-up
0
0
0
0
0
0
0
1
1
PC + 2
0
0
0
0
1
0
1
0
0
Interrupt Wake-up from
Sleep
PC + 2(1)
0
0
0
0
0
0
1
0
0
Clock Failure Trap
0x000004
0
0
0
0
0
0
0
0
0
Trap Reset
0x000000
1
0
0
0
0
0
0
0
0
Illegal Operation Trap
0x000000
0
1
0
0
0
0
0
0
0
Note 1:
When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
Table 21-6 lists a second example of the bit
conditions for the RCON register. In this case, it is not
assumed that the user has set/cleared specific bits
prior to action specified in the condition column.
TABLE 21-6:
INITIALIZATION CONDITION FOR RCON REGISTER, CASE 2
Condition
Program
Counter
TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR
Power-on Reset
0x000000
Brown-out Reset
0x000000
u
u
u
u
u
u
u
0
1
MCLR Reset during normal
operation
0x000000
u
u
1
0
0
0
0
u
u
Software Reset during
normal operation
0x000000
u
u
0
1
0
0
0
u
u
MCLR Reset during Sleep
0x000000
u
u
1
u
0
0
1
u
u
MCLR Reset during Idle
0x000000
u
u
1
u
0
1
0
u
u
WDT Time-out Reset
0x000000
u
u
0
0
1
0
0
u
u
WDT Wake-up
0
0
0
0
0
0
0
1
1
PC + 2
u
u
u
u
1
u
1
u
u
Interrupt Wake-up from
Sleep
PC + 2(1)
u
u
u
u
u
u
1
u
u
Clock Failure Trap
0x000004
u
u
u
u
u
u
u
u
u
Trap Reset
0x000000
1
u
u
u
u
u
u
u
u
Illegal Operation Reset
0x000000
u
1
u
u
u
u
u
u
u
Legend: u = unchanged
Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector.
DS70135G-page 160
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
21.4
21.4.1
Watchdog Timer (WDT)
WATCHDOG TIMER OPERATION
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer that runs
off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer continues to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
21.4.2
ENABLING AND DISABLING
THE WDT
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register, FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer.
The enabling is done when programming the device.
By default, after chip erase, FWDTEN bit = 1. Any
device programmer capable of programming
dsPIC30F devices allows programming of this and
other Configuration bits.
If enabled, the WDT increments until it overflows or
“times out”. A WDT time-out forces a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device wakes-up.
The WDTO bit in the RCON register is cleared to
indicate a wake-up resulting from a WDT time-out.
Setting FWDTEN = 0 allows user software to enable/
disable the Watchdog Timer via the SWDTEN
(RCON) control bit.
21.5
Power-Saving Modes
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV.
These are: Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV
where,
‘parameter’ defines Idle or Sleep mode.
© 2010 Microchip Technology Inc.
21.5.1
SLEEP MODE
In Sleep mode, the clock to the CPU and peripherals is
shut down. If an on-chip oscillator is being used, it is
shut down.
The Fail-Safe Clock Monitor is not functional during
Sleep, since there is no clock to monitor. However, the
LPRC clock remains active if WDT is operational during
Sleep.
The Brown-out Reset protection circuit and the LowVoltage Detect (LVD) circuit, if enabled, remain
functional during Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• Any interrupt that is individually enabled and
meets the required priority level
• Any Reset (POR, BOR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor restarts
the same clock that was active prior to entry into Sleep
mode. When clock switching is enabled, bits
COSC determine the oscillator source to be
used on wake-up. If clock switch is disabled, then
there is only one system clock.
Note:
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS
and FPR Configuration bits.
If the clock source is an oscillator, the clock to the
device is held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stable). In either case, TPOR, TLOCK and TPWRT delays
are applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of TPOR (~10 μs) is applied. This is the smallest
delay possible on wake-up from Sleep.
Moreover, if the LP oscillator was active during Sleep,
and LP is the oscillator used on wake-up, then the startup delay is equal to TPOR. PWRT and OST delays are
not applied. In order to have the smallest possible startup delay when waking up from Sleep, one of these
faster wake-up options should be selected before
entering Sleep.
DS70135G-page 161
dsPIC30F4011/4012
Any interrupt that is individually enabled (using the
corresponding IE bit) and meets the prevailing priority
level can wake-up the processor. The processor
processes the interrupt and branches to the ISR. The
SLEEP status bit in the RCON register is set upon
wake-up.
Note:
In spite of various delays applied (TPOR,
TLOCK and TPWRT), the crystal oscillator
(and PLL) may not be active at the end of
the time-out (e.g., for low-frequency crystals). In such cases, if FSCM is enabled,
the device detects this condition as a
clock failure and processes the clock failure trap. The FRC oscillator is enabled,
and the user must re-enable the crystal
oscillator. If FSCM is not enabled, then the
device simply suspends execution of code
until the clock is stable and remains in
Sleep until the oscillator clock has started.
All Resets wake-up the processor from Sleep mode.
Any Reset, other than POR, sets the SLEEP status bit.
In a POR, the SLEEP bit is cleared.
If Watchdog Timer is enabled, the processor wakes-up
from Sleep mode upon WDT time-out. The SLEEP and
WDTO status bits are both set.
Any interrupt that is individually enabled (using IE bit)
and meets the prevailing priority level can wake-up the
processor. The processor processes the interrupt and
branches to the ISR. The IDLE status bit in RCON
register is set upon wake-up.
Any Reset, other than POR, sets the IDLE status bit.
On a POR, the IDLE bit is cleared.
If Watchdog Timer is enabled, then the processor
wakes-up from Idle mode upon WDT time-out. The
IDLE and WDTO status bits are both set.
Unlike wake-up from Sleep, there are no time delays
involved in wake-up from Idle.
21.6
The Configuration bits in each device Configuration
register specify some of the device modes and are
programmed by a device programmer, or by using the
In-Circuit Serial Programming™ (ICSP™) feature of the
device. Each device Configuration register is a 24-bit
register, but only the lower 16 bits of each register are
used to hold configuration data. There are five device
Configuration registers available to the user:
1.
2.
21.5.2
IDLE MODE
In Idle mode, the clock to the CPU is shut down while
peripherals keep running. Unlike Sleep mode, the clock
source remains active.
Several peripherals have a control bit in each module,
that allows them to operate during Idle.
LPRC Fail-Safe Clock Monitor remains active if clock
failure detect is enabled.
The processor wakes up from Idle if at least one of the
following conditions is true:
• Any interrupt that is individually enabled (IE bit is
‘1’) and meets the required priority level
• Any Reset (POR, BOR, MCLR)
• WDT time-out
Upon wake-up from Idle mode, the clock is re-applied
to the CPU and instruction execution begins
immediately, starting with the instruction following the
PWRSAV instruction.
DS70135G-page 162
Device Configuration Registers
3.
4.
5.
FOSC (0xF80000): Oscillator Configuration
Register
FWDT (0xF80002): Watchdog Timer
Configuration Register
FBORPOR (0xF80004): BOR and POR
Configuration Register
FGS (0xF8000A): General Code Segment
Configuration Register
FICD (0xF8000C): Debug Configuration
Register
The placement of the Configuration bits is automatically
handled when you select the device in your device
programmer. The desired state of the Configuration bits
may be specified in the source code (dependent on the
language tool used), or through the programming
interface. After the device has been programmed, the
application software may read the Configuration bit
values through the table read instructions. For additional
information, please refer to the programming
specifications of the device.
Note:
If the code protection Configuration fuse
bits (FGS and FGS)
have been programmed, an erase of the
entire code-protected device is only
possible at voltages VDD ≥ 4.5V.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
21.7
In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the
in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with
MPLAB IDE. When the device has this feature enabled,
some of the resources are not available for general
use. These resources include the first 80 bytes of data
RAM and two I/O pins.
one of four pairs of debug I/O pins may be selected by
the user using configuration options in MPLAB IDE.
These pin pairs are named EMUD/EMUC, EMUD1/
EMUC1, EMUD2/EMUC2 and EMUD3/EMUC3.
In each case, the selected EMUD pin is the emulation/
debug data line and the EMUC pin is the emulation/
debug clock line. These pins interface to the MPLAB
ICD 2 module available from Microchip. The selected
pair of debug I/O pins is used by MPLAB ICD 2 to send
commands and receive responses, as well as to send
and receive data. To use the in-circuit debugger function of the device, the design must implement ICSP
connections to MCLR, VDD, VSS, PGC, PGD and the
selected EMUDx/EMUCx pin pair.
This gives rise to two possibilities:
1.
2.
© 2010 Microchip Technology Inc.
If EMUD/EMUC is selected as the debug I/O pin
pair, then only a 5-pin interface is required as the
EMUD and EMUC pin functions are multiplexed
with the PGD and PGC pin functions in all
dsPIC30F devices.
If EMUD1/EMUC1, EMUD2/EMUC2 or EMUD3/
EMUC3 is selected as the debug I/O pin pair,
then a 7-pin interface is required as the EMUDx/
EMUCx pin functions (x = 1, 2 or 3) are not
multiplexed with the PGD and PGC pin
functions.
DS70135G-page 163
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
RCON
0740 TRAPR IOPUWR BGST
OSCCON
0742
Legend:
Note 1:
TUN3
Bit 11
Bit 10
Bit 9
Bit 8
TUN1
TUN0
NOSC
—
COSC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
LOCK
—
CF
—
POST
Bit 1
Bit 0
BOR
POR
Reset State
Depends on type of Reset.
LPOSCEN OSWEN Depends on Configuration bits.
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
TABLE 21-8:
Name
TUN2
Bit 12
Address
DEVICE CONFIGURATION REGISTER MAP(1)
Bit 15
FOSC
F80000
FWDT
F80002
FWDTEN
FBORPOR F80004
MCLREN
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PWMPIN
HPOL
—
Reserved(2)
FCKSM
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
—
—
—
—
—
FWPSA
LPOL
BOREN
—
BORV
—
—
—
—
Reserved(2)
—
—
—
—
Reserved(2)
FOS
Bit 3
Bit 2
—
F80006
—
—
Reserved(2)
—
—
FSS
F80008
—
—
Reserved(2)
—
—
FGS
F8000A
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved(2)
FICD
F8000C
BKBUG
COE
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
Note 1:
2:
— = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Reserved bits read as ‘1’ and must be programmed as ‘1’.
Bit 0
FWPSB
—
FBS
Reserved(2)
Bit 1
FPR
FPWRT
GCP
GWRP
ICS
dsPIC30F4011/4012
DS70135G-page 164
SYSTEM INTEGRATION REGISTER MAP(1)
TABLE 21-7:
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
22.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
dsPIC30F Family Reference Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
The dsPIC30F instruction set adds many
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from PIC
MCU instruction sets.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’
or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register ‘Wb’)
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type, and one or more operands which further specify
the operation of the instruction.
• The first source operand which is a register ‘Wb’
without any address modifier
• The second source operand which is a literal
value
• The destination of the result (only if not the same
as the first source operand) which is typically a
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
The MAC class of DSP instructions may use some of the
following operands:
•
•
•
•
•
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 22-1 shows the general symbols used in
describing the instructions.
The dsPIC30F instruction set summary in Table 22-2
lists all the instructions along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could either be the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
© 2010 Microchip Technology Inc.
The other DSP instructions do not involve any
multiplication and may include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift, specified by a W register ‘Wn’
or a literal value
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made doubleword instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
DS70135G-page 165
dsPIC30F4011/4012
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over
the subsequent instruction, require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or twoword instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
TABLE 22-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
.b
.d
.S
.w
Acc
Means literal defined by “text“
Means “content of text“
Means “the location addressed by text”
Optional field or operation
Register bit field
Byte mode selection
Double-Word mode selection
Shadow register select
Word mode selection (default)
One of two accumulators {A, B}
AWB
bit4
C, DC, N, OV, Z
Expr
f
lit1
lit4
lit5
lit8
lit10
lit14
lit16
Accumulator Write-Back Destination Address register ∈ {W13, [W13]+=2}
4-bit bit selection field (used in word addressed instructions) ∈ {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Zero
Absolute address, label or expression (resolved by the linker)
File register address ∈ {0x0000...0x1FFF}
1-bit unsigned literal ∈ {0,1}
4-bit unsigned literal ∈ {0...15}
5-bit unsigned literal ∈ {0...31}
8-bit unsigned literal ∈ {0...255}
10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal ∈ {0...16384}
16-bit unsigned literal ∈ {0...65535}
lit23
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
23-bit unsigned literal ∈ {0...8388608}; LSB must be 0
Field does not require an entry, may be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
10-bit signed literal ∈ {-512...511}
16-bit signed literal ∈ {-32768...32767}
6-bit signed literal ∈ {-16...16}
DS70135G-page 166
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 22-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Wb
Wd
Wdo
Wm,Wn
Wm*Wm
Wm*Wn
Wn
Wnd
Wns
WREG
Ws
Wso
Wx
Wxd
Wy
Wyd
© 2010 Microchip Technology Inc.
Description
Base W register ∈ {W0..W15}
Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Destination W register ∈
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Dividend, Divisor working register pair (Direct Addressing)
Multiplicand and Multiplier working register pair for Square instructions ∈
{W4*W4, W5*W5, W6*W6, W7*W7}
Multiplicand and Multiplier working register pair for DSP instructions ∈
{W4*W5, W4*W6, W4*W7, W5*W6, W5*W7, W6*W7}
One of 16 working registers ∈ {W0..W15}
One of 16 destination working registers ∈ {W0..W15}
One of 16 source working registers ∈ {W0..W15}
W0 (working register used in file register instructions)
Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Source W register ∈
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
X Data Space Prefetch Address register for DSP instructions
∈ {[W8]+=6, [W8]+=4, [W8]+=2, [W8], [W8]-=6, [W8]-=4, [W8]-=2,
[W9]+=6, [W9]+=4, [W9]+=2, [W9], [W9]-=6, [W9]-=4, [W9]-=2,
[W9+W12],none}
X Data Space Prefetch Destination register for DSP instructions ∈ {W4..W7}
Y Data Space Prefetch Address register for DSP instructions
∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2,
[W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2,
[W11+W12], none}
Y Data Space Prefetch Destination register for DSP instructions ∈ {W4..W7}
DS70135G-page 167
dsPIC30F4011/4012
TABLE 22-2:
INSTRUCTION SET OVERVIEW
Base
Assembly
Instr
Mnemonic
#
1
2
3
4
5
6
7
8
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
Assembly Syntax
Description
# of
words
# of
cycles
Status Flags
Affected
ADD
Acc
Add Accumulators
1
1
OA, OB, SA, SB
ADD
f
f = f + WREG
1
1
C, DC, N, OV, Z
ADD
f,WREG
WREG = f + WREG
1
1
C, DC, N, OV, Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C, DC, N, OV, Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C, DC, N, OV, Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C, DC, N, OV, Z
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
OA, OB, SA, SB
ADDC
f
f = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C, DC, N, OV, Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C, DC, N, OV, Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C, DC, N, OV, Z
AND
f
f = f .AND. WREG
1
1
N, Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N, Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N, Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N, Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N, Z
ASR
f
f = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C, N, OV, Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C, N, OV, Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N, Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N, Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if greater than or equal
1
1 (2)
None
BRA
GEU,Expr
Branch if unsigned greater than or equal
1
1 (2)
None
BRA
GT,Expr
Branch if greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if unsigned greater than
1
1 (2)
None
BRA
LE,Expr
Branch if less than or equal
1
1 (2)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1
1 (2)
None
BRA
LT,Expr
Branch if less than
1
1 (2)
None
BRA
LTU,Expr
Branch if unsigned less than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1
1 (2)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
SA,Expr
Branch if Accumulator A saturated
1
1 (2)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
DS70135G-page 168
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 22-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly
Instr
Mnemonic
#
9
10
11
12
13
14
15
BTG
BTSC
BTSS
BTST
BTSTS
CALL
CLR
Assembly Syntax
Description
# of
words
# of
cycles
Status Flags
Affected
BTG
f,#bit4
Bit Toggle f
1
1
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
Z
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
CALL
lit23
Call subroutine
2
2
None
CALL
Wn
Call indirect subroutine
1
2
None
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA, OB, SA, SB
Clear Watchdog Timer
1
1
WDTO, Sleep
16
CLRWDT
CLRWDT
17
COM
COM
f
f=f
1
1
N, Z
COM
f,WREG
WREG = f
1
1
N, Z
COM
Ws,Wd
Wd = Ws
1
1
N, Z
CP
f
Compare f with WREG
1
1
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C, DC, N, OV, Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C, DC, N, OV, Z
CP0
f
Compare f with 0x0000
1
1
C, DC, N, OV, Z
CP0
Ws
Compare Ws with 0x0000
1
1
C, DC, N, OV, Z
CPB
f
Compare f with WREG, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C, DC, N, OV, Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C, DC, N, OV, Z
18
19
20
CP
CP0
CPB
21
CPSEQ
CPSEQ
Wb, Wn
Compare Wb with Wn, skip if =
1
1
(2 or 3)
None
22
CPSGT
CPSGT
Wb, Wn
Compare Wb with Wn, skip if >
1
1
(2 or 3)
None
23
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, skip if <
1
1
(2 or 3)
None
24
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, skip if ≠
1
1
(2 or 3)
None
25
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
26
DEC
DEC
f
f = f –1
1
1
C, DC, N, OV, Z
DEC
f,WREG
WREG = f –1
1
1
C, DC, N, OV, Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C, DC, N, OV, Z
DEC2
f
f=f–2
1
1
C, DC, N, OV, Z
DEC2
f,WREG
WREG = f – 2
1
1
C, DC, N, OV, Z
27
28
DEC2
DISI
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C, DC, N, OV, Z
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
© 2010 Microchip Technology Inc.
DS70135G-page 169
dsPIC30F4011/4012
TABLE 22-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly
Instr
Mnemonic
#
29
DIV
Assembly Syntax
Description
# of
words
# of
cycles
Status Flags
Affected
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N, Z, C, OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N, Z, C, OV
30
DIVF
DIVF
Wm,Wn
Signed 16/16-bit Fractional Divide
1
18
N, Z, C, OV
31
DO
DO
#lit14,Expr
Do code to PC + Expr, lit14 + 1 time
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) +1 time
2
2
None
32
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance ( no accumulate)
1
1
OA, OB, OAB,
SA, SB, SAB
33
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA, OB, OAB,
SA, SB, SAB
34
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
35
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
36
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
37
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
38
GOTO
GOTO
Expr
Go to address
2
2
None
GOTO
Wn
Go to indirect
1
2
None
INC
f
f=f+1
1
1
C, DC, N, OV, Z
INC
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
39
40
41
42
INC
INC2
IOR
LAC
INC
Ws,Wd
Wd = Ws + 1
1
1
INC2
f
f=f+2
1
1
C, DC, N, OV, Z
INC2
f,WREG
WREG = f + 2
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N, Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N, Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N, Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N, Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N, Z
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
OA, OB, OAB,
SA, SB, SAB
None
43
LNK
LNK
#lit14
Link Frame Pointer
1
1
44
LSR
LSR
f
f = Logical Right Shift f
1
1
C, N, OV, Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C, N, OV, Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C, N, OV, Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N, Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N, Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate
AWB
1
1
OA, OB, OAB,
SA, SB, SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA, OB, OAB,
SA, SB, SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
None
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
45
46
47
MAC
MOV
MOVSAC
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
Prefetch and store accumulator
1
1
None
MOVSAC
DS70135G-page 170
Acc,Wx,Wxd,Wy,Wyd,AWB
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 22-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly
Instr
Mnemonic
#
48
MPY
Assembly Syntax
Description
# of
words
# of
cycles
Status Flags
Affected
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA, OB, OAB,
SA, SB, SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA, OB, OAB,
SA, SB, SAB
-(Multiply Wm by Wn) to Accumulator
1
1
None
1
1
OA, OB, OAB,
SA, SB, SAB
49
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
50
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd, Multiply and Subtract from Accumulator
AWB
51
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd+1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd+1, Wnd} = signed(Wb) * unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd+1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd+1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd+1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
52
NEG
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
Acc
Negate Accumulator
1
1
OA, OB, OAB,
SA, SB, SAB
NEG
f
f=f+1
1
1
C, DC, N, OV, Z
NEG
f,WREG
WREG = f + 1
1
1
C, DC, N, OV, Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C, DC, N, OV, Z
No Operation
1
1
None
None
53
NOP
NOP
No Operation
1
1
54
POP
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to W(nd):W(nd
+1)
1
2
None
Pop Shadow Registers
1
1
All
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
1
2
None
None
NOPR
POP.S
55
PUSH
Push Shadow Registers
1
1
56
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO, Sleep
57
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
58
REPEAT
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 time
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 time
1
1
None
PUSH.S
59
RESET
RESET
Software device Reset
1
1
None
60
RETFIE
RETFIE
Return from interrupt
1
3 (2)
None
61
RETLW
RETLW
62
RETURN
RETURN
63
RLC
RLC
RLC
64
65
RLNC
RRC
Return with literal in Wn
1
3 (2)
None
Return from Subroutine
1
3 (2)
None
f
f = Rotate Left through Carry f
1
1
C, N, Z
f,WREG
WREG = Rotate Left through Carry f
1
1
C, N, Z
C, N, Z
#lit10,Wn
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
RLNC
f
f = Rotate Left (No Carry) f
1
1
N, Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N, Z
N, Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
RRC
f
f = Rotate Right through Carry f
1
1
C, N, Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C, N, Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C, N, Z
© 2010 Microchip Technology Inc.
DS70135G-page 171
dsPIC30F4011/4012
TABLE 22-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Assembly
Instr
Mnemonic
#
66
RRNC
Assembly Syntax
Description
# of
words
# of
cycles
Status Flags
Affected
RRNC
f
f = Rotate Right (No Carry) f
1
1
N, Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N, Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N, Z
67
SAC
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
68
SE
SE
Ws,Wnd
Wnd = sign-extended Ws
1
1
C, N, Z
69
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
70
71
72
73
74
75
76
77
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
SWAP
TBLRDH
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA, OB, OAB,
SA, SB, SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA, OB, OAB,
SA, SB, SAB
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N, Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N, Z
SUB
Acc
Subtract Accumulators
1
1
OA, OB, OAB,
SA, SB, SAB
SUB
f
f = f – WREG
1
1
C, DC, N, OV, Z
SUB
f,WREG
WREG = f – WREG
1
1
C, DC, N, OV, Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C, DC, N, OV, Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C, DC, N, OV, Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C, DC, N, OV, Z
SUBB
f
f = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C, DC, N, OV, Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C, DC, N, OV, Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C, DC, N, OV, Z
SUBR
f
f = WREG – f
1
1
C, DC, N, OV, Z
SUBR
f,WREG
WREG = WREG – f
1
1
C, DC, N, OV, Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C, DC, N, OV, Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C, DC, N, OV, Z
SUBBR
f
f = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C, DC, N, OV, Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C, DC, N, OV, Z
SWAP.b
Wn
Wn = nibble swap Wn
1
1
None
SWAP
Wn
Wn = byte swap Wn
1
1
None
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
None
78
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
79
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
Ws,Wd
None
80
TBLWTL
TBLWTL
81
ULNK
ULNK
82
XOR
XOR
83
ZE
Write Ws to Prog
1
2
Unlink Frame Pointer
1
1
None
f
f = f .XOR. WREG
1
1
N, Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N, Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N, Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N, Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N, Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C, N, Z
DS70135G-page 172
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
23.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
23.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2010 Microchip Technology Inc.
DS70135G-page 173
dsPIC30F4011/4012
23.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
23.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker,
preprocessor, and one-step driver, and can run on
multiple platforms.
23.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
23.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
23.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS70135G-page 174
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
23.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The
software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory
environment, making it an excellent, economical
software development tool.
23.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2010 Microchip Technology Inc.
23.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
23.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and
and
dsPIC®
Flash
programming
of
PIC®
microcontrollers at a most affordable price point using
the powerful graphical user interface of the MPLAB
Integrated Development Environment (IDE). The
MPLAB PICkit 3 is connected to the design engineer's
PC using a full speed USB interface and can be
connected to the target via an Microchip debug (RJ-11)
connector (compatible with MPLAB ICD 3 and MPLAB
REAL ICE). The connector uses two device I/O pins
and the reset line to implement in-circuit debugging and
In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS70135G-page 175
dsPIC30F4011/4012
23.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
23.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
23.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS70135G-page 176
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
24.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC30F electrical characteristics. Additional information will be provided in future
revisions of this document as it becomes available.
For detailed information about the dsPIC30F architecture and core, refer to the “dsPIC30F Family Reference Manual”
(DS70046).
Absolute maximum ratings for the dsPIC30F family are listed below. Exposure to these maximum rating conditions for
extended periods may affect device reliability. Functional operation of the device at these or any other conditions above
the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) (Note 1) ..................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS ....................................................................................................... 0V to +13.25V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin (Note 2)................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................... ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/ pin, rather than
pulling this pin directly to VSS.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 24-2).
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2010 Microchip Technology Inc.
DS70135G-page 177
dsPIC30F4011/4012
24.1
DC Characteristics
TABLE 24-1:
OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
Temp Range
dsPIC30F401X-30I
dsPIC30F401X-20E
30
—
20
4.5-5.5V
-40°C to +85°C
4.5-5.5V
-40°C to +125°C
—
3.0-3.6V
-40°C to +85°C
20
—
3.0-3.6V
-40°C to +125°C
—
15
2.5-3.0V
-40°C to +85°C
10
—
TABLE 24-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+150
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
dsPIC30F401X-30I
dsPIC30F401X-20E
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD X (IDD – ∑IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/θJA
W
I/O Pin power dissipation:
PI/O = ∑({VDD – VOH} X IOH) + ∑(VOL X IOL)
Maximum Allowed Power Dissipation
TABLE 24-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 28-pin SPDIP (SP)
θJA
41
—
°C/W
1
Package Thermal Resistance, 28-pin SOIC (SO)
θJA
45
—
°C/W
1
Package Thermal Resistance, 40-pin PDIP (P)
θJA
37
—
°C/W
1
Package Thermal Resistance, 44-pin TQFP, 10x10x1 mm (PT)
θJA
40
—
°C/W
1
Package Thermal Resistance, 44-pin QFN (ML)
θJA
28
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-ja (θJA) numbers are achieved by package simulations.
DS70135G-page 178
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ(1)
Max
Units
Conditions
Operating Voltage(2)
DC10
VDD
Supply Voltage
2.5
—
5.5
V
Industrial temperature
DC11
VDD
Supply Voltage
3.0
—
5.5
V
Extended temperature
DC12
VDR
RAM Data Retention
Voltage(3)
1.75
—
—
V
DC16
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
VSS
—
V
DC17
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
V/ms
Note 1:
2:
3:
0-5V in 0.1 sec,
0-3V in 60 ms
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
This is the limit to which VDD can be lowered without losing RAM data.
© 2010 Microchip Technology Inc.
DS70135G-page 179
dsPIC30F4011/4012
TABLE 24-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC31a
2
4
mA
+25°C
DC31b
2
4
mA
+85°C
DC31c
2
4
mA
+125°C
DC31e
3
5
mA
+25°C
DC31f
3
5
mA
+85°C
+125°C
DC31g
3
5
mA
DC30a
4
6
mA
+25°C
DC30b
4
6
mA
+85°C
DC30c
4
6
mA
+125°C
DC30e
7
10
mA
+25°C
DC30f
7
10
mA
+85°C
+125°C
DC30g
7
10
mA
DC23a
12
19
mA
+25°C
DC23b
12
19
mA
+85°C
DC23c
13
19
mA
+125°C
DC23e
19
31
mA
+25°C
DC23f
20
31
mA
+85°C
DC23g
20
31
mA
+125°C
DC24a
28
39
mA
+25°C
DC24b
28
39
mA
+85°C
DC24c
29
39
mA
+125°C
DC24e
46
64
mA
+25°C
DC24f
46
64
mA
+85°C
DC24g
47
64
mA
+125°C
DC27a
53
72
mA
+25°C
DC27b
53
72
mA
+85°C
DC27d
87
120
mA
+25°C
DC27e
87
120
mA
+85°C
DC27f
87
120
mA
+125°C
DC29a
124
170
mA
+25°C
DC29b
125
170
mA
+85°C
Note 1:
2:
3.3V
0.128 MIPS
LPRC (512 kHz)
5V
3.3V
(1.8 MIPS)
FRC (7.37 MHz)
5V
3.3V
4 MIPS
5V
3.3V
10 MIPS
5V
3.3V
20 MIPS
5V
5V
30 MIPS
Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, program memory and data memory
are operational. No peripheral modules are operating.
DS70135G-page 180
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1,2)
Max
Units
Conditions
Operating Current (IDD)(3)
DC51a
1.3
3
mA
+25°C
DC51b
1.3
3
mA
+85°C
DC51c
1.3
3
mA
+125°C
DC51e
2.7
5
mA
+25°C
DC51f
2.7
5
mA
+85°C
DC51g
2.7
5
mA
+125°C
DC50a
4
6
mA
+25°C
DC50b
4
6
mA
+85°C
DC50c
4
6
mA
+125°C
DC50e
7
11
mA
+25°C
DC50f
7
11
mA
+85°C
DC50g
7
11
mA
+125°C
DC43a
7
11
mA
+25°C
DC43b
7
11
mA
+85°C
DC43c
7
11
mA
+125°C
DC43e
12
17
mA
+25°C
DC43f
12
17
mA
+85°C
DC43g
12
17
mA
+125°C
DC44a
15
22
mA
+25°C
DC44b
15
22
mA
+85°C
DC44c
16
22
mA
+125°C
DC44e
26
36
mA
+25°C
DC44f
27
36
mA
+85°C
DC44g
27
36
mA
+125°C
DC47a
30
40
mA
+25°C
DC47b
30
40
mA
+85°C
DC47d
50
65
mA
+25°C
DC47e
50
65
mA
+85°C
DC47f
51
65
mA
+125°C
DC49a
72
95
mA
+25°C
DC49b
73
95
mA
+85°C
Note 1:
2:
3.3V
0.128 MIPS
LPRC (512 kHz)
5V
3.3V
(1.8 MIPS)
FRC (7.37 MHz)
5V
3.3V
4 MIPS
5V
3.3V
10 MIPS
5V
3.3V
20 MIPS
5V
5V
30 MIPS
Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IIDLE current is measured with core off, clock on and all modules turned off.
© 2010 Microchip Technology Inc.
DS70135G-page 181
dsPIC30F4011/4012
TABLE 24-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD)(2)
DC60a
0.3
—
μA
25°C
DC60b
1
30
μA
85°C
DC60c
12
60
μA
125°C
DC60e
0.5
—
μA
25°C
DC60f
2
45
μA
85°C
DC60g
17
90
μA
125°C
DC61a
5
8
μA
25°C
DC61b
5
8
μA
85°C
DC61c
6
9
μA
125°C
DC61e
10
15
μA
25°C
DC61f
10
15
μA
85°C
DC61g
11
17
μA
125°C
DC62a
4
10
μA
25°C
DC62b
5
10
μA
85°C
DC62c
4
10
μA
125°C
DC62e
4
15
μA
25°C
DC62f
6
15
μA
85°C
DC62g
5
15
μA
125°C
DC63a
32
48
μA
25°C
DC63b
35
53
μA
85°C
DC63c
37
56
μA
125°C
DC63e
37
56
μA
25°C
DC63f
41
62
μA
85°C
57
86
μA
125°C
DC63g
Note 1:
2:
3.3V
Base power-down current(3)
5V
3.3V
Watchdog Timer current: ΔIWDT(3)
5V
3.3V
Timer1 w/32 kHz crystal: ΔITI32(3)
5V
3.3V
BOR on: ΔIBOR(3)
5V
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
DS70135G-page 182
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(2)
DI10
I/O pins:
with Schmitt Trigger buffer
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSC1 (in XT, HS and LP modes)
VSS
—
0.2 VDD
V
DI17
OSC1 (in RC mode)(3)
VSS
—
0.3 VDD
V
DI18
SDA, SCL
VSS
—
0.3 VDD
V
SMBus disabled
DI19
SDA, SCL
VSS
—
0.8
V
SMBus enabled
I/O pins:
with Schmitt Trigger buffer
0.8 VDD
—
VDD
V
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSC1 (in XT, HS and LP modes) 0.7 VDD
—
VDD
V
VIH
DI20
Input High Voltage(2)
mode)(3)
DI27
OSC1 (in RC
0.9 VDD
—
VDD
V
DI28
SDA, SCL
0.7 VDD
—
VDD
V
SMBus disabled
SDA, SCL
2.1
—
VDD
V
SMBus enabled
CNXX Pull-up Current(2)
50
250
400
μA
VDD = 5V, VPIN = VSS
DI29
DI30
ICNPU
IIL
Input Leakage
Current(2,4,5)
DI50
I/O ports
—
0.01
±1
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI51
Analog input pins
—
0.50
—
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI55
MCLR
—
0.05
±5
μA
VSS ≤VPIN ≤VDD
DI56
OSC1
—
0.05
±5
μA
VSS ≤VPIN ≤VDD,
XT, HS and LP Osc mode
Note 1:
2:
3:
4:
5:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that the
dsPIC30F device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
Negative current is defined as current sourced by the pin.
© 2010 Microchip Technology Inc.
DS70135G-page 183
dsPIC30F4011/4012
TABLE 24-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VOL
DO10
Characteristic
VOH
Typ(1)
Max
Units
Conditions
Output Low Voltage(2)
I/O ports
DO16
Min
—
—
0.6
V
IOL = 8.5 mA, VDD = 5V
—
—
0.15
V
IOL = 2.0 mA, VDD = 3V
OSC2/CLKO
—
—
0.6
V
IOL = 1.6 mA, VDD = 5V
(RC or EC Osc mode)
—
—
0.72
V
IOL = 2.0 mA, VDD = 3V
Output High Voltage
(2)
DO20
I/O ports
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 5V
VDD – 0.2
—
—
V
IOH = -2.0 mA, VDD = 3V
DO26
OSC2/CLKO
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 5V
(RC or EC Osc mode)
VDD – 0.1
—
—
V
IOH = -2.0 mA, VDD = 3V
15
pF
In XTL, XT, HS and LP modes
when external clock is used to
drive OSC1
Capacitive Loading Specs
on Output Pins(2)
DO50
COSC2
OSC2/SOSC2 pin
—
—
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
RC or EC Osc mode
DO58
CB
SCL, SDA
—
—
400
pF
In I2C™ mode
Note 1:
2:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
FIGURE 24-1:
BROWN-OUT RESET CHARACTERISTICS
VDD
BO10
(Device in Brown-out Reset)
BO15
(Device not in Brown-out Reset)
Reset (due to BOR)
Power-up Time-out
DS70135G-page 184
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-10: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
BO10
VBOR
BO15
Characteristic
BOR Voltage on
VDD Transition
High-to-Low(2)
Min
2:
3:
Max
Units
Conditions
Not in operating range
BORV = 11(3)
—
—
—
V
BORV = 10
2.6
—
2.71
V
BORV = 01
4.1
—
4.4
V
BORV = 00
4.58
—
4.73
V
—
5
—
mV
VBHYS
Note 1:
Typ(1)
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
‘11’ values not in usable operating range.
TABLE 24-11: DC CHARACTERISTICS: PROGRAM AND EEPROM
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ(1)
Max
Units
Conditions
Data EEPROM Memory(2)
E/W -40° C ≤TA ≤+85°C
D120
ED
Byte Endurance
100K
1M
—
D121
VDRW
VDD for Read/Write
VMIN
—
5.5
V
D122
TDEW
Erase/Write Cycle Time
0.8
2
2.6
ms
D123
TRETD
Characteristic Retention
40
100
—
Year Provided no other specifications are
violated
D124
IDEW
IDD During Programming
—
10
30
mA
E/W -40° C ≤TA ≤+85°C
Using EECON to read/write,
VMIN = Minimum operating voltage
RTSP
Row Erase
Program Flash Memory(2)
D130
EP
Cell Endurance
10K
100K
—
D131
VPR
VDD for Read
VMIN
—
5.5
V
D132
VEB
VDD for Bulk Erase
4.5
—
5.5
V
D133
VPEW
VDD for Erase/Write
3.0
—
5.5
V
ms
VMIN = Minimum operating voltage
D134
TPEW
Erase/Write Cycle Time
0.8
2
2.6
D135
TRETD
Characteristic Retention
40
100
—
Year Provided no other specifications are
violated
D137
IPEW
IDD During Programming
—
10
30
mA
Row Erase
D138
IEB
IDD During Programming
—
10
30
mA
Bulk Erase
Note 1:
2:
RTSP
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
These parameters are characterized but not tested in manufacturing.
© 2010 Microchip Technology Inc.
DS70135G-page 185
dsPIC30F4011/4012
24.2
AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 24-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Operating voltage VDD range as described in Section 24.1 “DC
Characteristics”.
AC CHARACTERISTICS
FIGURE 24-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2
5 pF for OSC2 output
VSS
FIGURE 24-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKO
OS40
DS70135G-page 186
OS41
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-13: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
OS10
FOSC
Characteristic
Min
Typ(1)
Max
Units
External CLKI Frequency
(external clocks allowed only
in EC mode)(2)
DC
4
4
4
—
—
—
—
40
10
10
7.5
MHz
MHz
MHz
MHz
EC
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
Oscillator Frequency(2)
DC
0.4
4
4
4
4
10
31
—
—
—
—
—
—
—
—
—
—
7.37
512
4
4
10
10
10
7.5
25
33
—
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
MHz
kHz
RC
XTL
XT
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
HS
LP
FRC internal
LPRC internal
Conditions
OS20
TOSC
TOSC = 1/FOSC
—
—
—
—
See parameter OS10
for FOSC value
OS25
TCY
Instruction Cycle Time(2,3)
33
—
DC
ns
See Table 24-16
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time(2)
.45 x TOSC
—
—
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time(2)
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(2,4)
—
—
—
ns
See parameter DO31
OS41
TckF
CLKO Fall Time(2,4)
—
—
—
ns
See parameter DO32
Note 1:
2:
3:
4:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC or ERC modes. The CLKO signal is measured on the OSC2 pin. CLKO is
low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
© 2010 Microchip Technology Inc.
DS70135G-page 187
dsPIC30F4011/4012
TABLE 24-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5V)
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
—
—
—
—
—
—
10
10
7.5(3)
10
10
7.5(3)
MHz
MHz
MHz
MHz
MHz
MHz
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
EC, XT with PLL
OS50
FPLLI
PLL Input Frequency Range(2)
4
4
4
4
4
4
OS51
FSYS
On-Chip PLL Output(2)
16
—
120
MHz
OS52
TLOC
PLL Start-up Time (Lock Time)
—
20
50
μs
Note 1:
2:
3:
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
Limited by device operating frequency range.
TABLE 24-15: PLL JITTER
AC CHARACTERISTICS
Param
No.
OS61
Characteristic
x4 PLL
x8 PLL
x16 PLL
Note 1:
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ(1)
Max
Units
Conditions
—
0.251
0.413
%
-40°C ≤TA ≤+85°C
VDD = 3.0 to 3.6V
—
0.251
0.413
%
-40°C ≤TA ≤+125°C
VDD = 3.0 to 3.6V
—
0.256
0.47
%
-40°C ≤TA ≤+85°C
VDD = 4.5 to 5.5V
—
0.256
0.47
%
-40°C ≤TA ≤+125°C
VDD = 4.5 to 5.5V
—
0.355
0.584
%
-40°C ≤TA ≤+85°C
VDD = 3.0 to 3.6V
—
0.355
0.584
%
-40°C ≤TA ≤+125°C
VDD = 3.0 to 3.6V
—
0.362
0.664
%
-40°C ≤TA ≤+85°C
VDD = 4.5 to 5.5V
—
0.362
0.664
%
-40°C ≤TA ≤+125°C
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
—
0.67
0.92
%
-40°C ≤TA ≤+85°C
—
0.632
0.956
%
-40°C ≤TA ≤+85°C
VDD = 4.5 to 5.5V
—
0.632
0.956
%
-40°C ≤TA ≤+125°C
VDD = 4.5 to 5.5V
These parameters are characterized but not tested in manufacturing.
DS70135G-page 188
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-16: INTERNAL CLOCK TIMING EXAMPLES
Clock
Oscillator
Mode
FOSC
(MHz)(1)
TCY (μsec)(2)
MIPS
w/o PLL(3)
MIPS
w/PLL x4(3)
MIPS
w/PLL x8(3)
MIPS
w/PLL x16(3)
EC
0.200
20.0
0.05
—
—
—
XT
Note 1:
2:
3:
4
1.0
1.0
4.0
8.0
16.0
10
0.4
2.5
10.0
20.0
—
25
0.16
6.25
—
—
—
4
1.0
1.0
4.0
8.0
16.0
10
0.4
2.5
10.0
20.0
—
Assumption: Oscillator postscaler is divide by 1.
Instruction Execution Cycle Time: TCY = 1/MIPS.
Instruction Execution Frequency: MIPS = (FOSC * PLLx)/4, since there are 4 Q clocks per instruction cycle.
© 2010 Microchip Technology Inc.
DS70135G-page 189
dsPIC30F4011/4012
TABLE 24-17: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)
OS63
Note 1:
FRC
—
—
±2.00
%
-40°C ≤TA ≤+85°C
VDD = 3.0-5.5V
—
—
±5.00
%
-40°C ≤TA ≤+125°C
VDD = 3.0-5.5V
Frequency calibrated at 7.372 MHz ±2%, 25°C and 5V. TUN bits can be used to compensate for
temperature drift.
TABLE 24-18: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ
Max
Units
Conditions
OS65A
-50
—
+50
%
VDD = 5.0V, ±10%
OS65B
-60
—
+60
%
VDD = 3.3V, ±10%
-70
—
+70
%
VDD = 2.5V
LPRC @ Freq. = 512 kHz(1)
OS65C
Note 1:
Change of LPRC frequency as VDD changes.
DS70135G-page 190
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-4:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to the Figure 24-2 for load.
TABLE 24-19: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1,2,3)
Typ(4)
Max
Units
—
7
20
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
7
20
ns
DI35
TINP
INTx Pin High or Low Time (output)
20
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2 TCY
—
—
ns
Note 1:
2:
3:
4:
Port Output Rise Time
Min
Conditions
These parameters are asynchronous events not related to any internal clock edges
Measurements are taken in RC mode and EC mode where CLKO output is 4 x TOSC.
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
© 2010 Microchip Technology Inc.
DS70135G-page 191
dsPIC30F4011/4012
FIGURE 24-5:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
Oscillator
Time-out
SY30
Internal
Reset
Watchdog
Timer
Reset
SY13
SY20
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to the Figure 24-2 for load conditions.
DS70135G-page 192
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SY10
TmcL
MCLR Pulse Width (low)
2
—
—
μs
-40°C to +85°C
SY11
TPWRT
Power-up Timer Period
2
8
32
4
16
64
6
24
96
ms
-40°C to +85°C, VDD = 5V
User programmable
SY12
TPOR
Power-on Reset Delay
3
10
30
μs
-40°C to +85°C
SY13
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
0.8
1.0
μs
SY20
TWDT1
TWDT2
TWDT3
Watchdog Timer Time-out
Period
(No Prescaler)
0.6
0.8
1.0
2.0
2.0
2.0
3.4
3.2
3.0
ms
ms
ms
VDD = 2.5V
VDD = 3.3V, ±10%
VDD = 5V, ±10%
SY25
TBOR
Brown-out Reset Pulse Width(3)
100
—
—
μs
VDD ≤VBOR (D034)
SY30
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
SY35
TFSCM
Fail-Safe Clock Monitor Delay
—
500
900
μs
-40°C to +85°C
Note 1:
2:
3:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
Refer to Figure 24-1 and Table 24-10 for BOR.
FIGURE 24-6:
BAND GAP START-UP TIME CHARACTERISTICS
VBGAP
0V
Enable
Band Gap(1)
Band Gap
Stable
SY40
Note 1:
Band gap is enabled when FBORPOR is set.
TABLE 24-21: BAND GAP START-UP TIME REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Param
No.
Symbol
Min
Typ(2)
Max
Units
SY40
TBGAP
—
40
65
μs
Note 1:
2:
Characteristic(1)
Band Gap
Start-up Time
Conditions
Defined as the time between the instant
that the band gap is enabled and the
moment that the band gap reference
voltage is stable (RCON status bit)
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
© 2010 Microchip Technology Inc.
DS70135G-page 193
dsPIC30F4011/4012
FIGURE 24-7:
TIMERx EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 24-2 for load conditions.
TABLE 24-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristic
Min
Typ
Max
Units
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
ns
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
ns
Synchronous,
no prescaler
TCY + 10
—
—
ns
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
—
—
—
Asynchronous
20
—
—
ns
SOSCO/T1CK Oscillator
Input frequency Range
(oscillator enabled by setting
bit, TCS (T1CON)
DC
—
50
kHz
0.5 TCY
—
1.5 TCY
—
T1CK High
Time
T1CK Low
Time
T1CK Input
Period
OS60
Ft1
TA20
TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
DS70135G-page 194
Conditions
Must also meet
parameter TA15
Must also meet
parameter TA15
N = prescale value
(1, 8, 64, 256)
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
TB10
TB11
TB15
TB20
Symbol
TTXH
TTXL
TTXP
Characteristic
TxCK High Time
TxCK Low Time
TxCK Input
Period
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
ns
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
Synchronous,
no prescaler
TCY + 10
—
—
ns
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
—
1.5 TCY
—
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
Must also meet
parameter TB15
N = prescale
value
(1, 8, 64, 256)
TABLE 24-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High Time
Synchronous
0.5 TCY + 20
—
—
ns
Must also meet
parameter TC15
TC11
TtxL
TxCK Low Time
Synchronous
0.5 TCY + 20
—
—
ns
Must also meet
parameter TC15
TC15
TtxP
TxCK Input Period Synchronous,
no prescaler
TCY + 10
—
—
ns
N = prescale
value
(1, 8, 64, 256)
—
1.5 TCY
—
Synchronous,
with prescaler
TC20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
© 2010 Microchip Technology Inc.
Greater of:
20 ns or
(TCY + 40)/N
0.5 TCY
DS70135G-page 195
dsPIC30F4011/4012
FIGURE 24-8:
QEI MODULE EXTERNAL CLOCK TIMING CHARACTERISTICS
QEB
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 24-25: QEI MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TQ10
TtQH
TxCK High Time
Synchronous,
with prescaler
TCY + 20
—
—
ns
Must also meet
parameter TQ15
TQ11
TtQL
TxCK Low Time
Synchronous,
with prescaler
TCY + 20
—
—
ns
Must also meet
parameter TQ15
TQ15
TtQP
TxCK Input Period Synchronous, 2 * TCY + 40
with prescaler
—
—
ns
TQ20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
—
1.5 TCY
ns
Note 1:
0.5 TCY
These parameters are characterized but not tested in manufacturing.
DS70135G-page 196
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-9:
INPUT CAPTURE TIMING CHARACTERISTICS
ICX
IC10
IC11
IC15
Note: Refer to Figure 24-2 for load conditions.
TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
IC10
TccL
ICx Input Low Time
No prescaler
IC11
TccH
ICx Input High Time
No prescaler
IC15
TccP
ICx Input Period
Characteristic(1)
With prescaler
With prescaler
Note 1:
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(2 TCY + 40)/N
—
ns
Conditions
N = prescale
value (1, 4, 16)
These parameters are characterized but not tested in manufacturing.
© 2010 Microchip Technology Inc.
DS70135G-page 197
dsPIC30F4011/4012
FIGURE 24-10:
OUTPUT COMPARE MODULE TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 24-2 for load conditions.
TABLE 24-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ(2)
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70135G-page 198
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-11:
OUTPUT COMPARE/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 24-28: SIMPLE OUTPUT COMPARE/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
OC15
TFD
Fault Input to PWM I/O
Change
—
—
50
ns
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
Note 1:
2:
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
© 2010 Microchip Technology Inc.
DS70135G-page 199
dsPIC30F4011/4012
FIGURE 24-12:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA
MP20
PWMx
FIGURE 24-13:
MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 24-2 for load conditions.
TABLE 24-29: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
MP10
TFPWM
PWM Output Fall Time
—
—
—
ns
See parameter DO32
MP11
TRPWM
PWM Output Rise
Time
—
—
—
ns
See parameter DO31
MP20
TFD
Fault Input ↓ to PWM
I/O Change
—
—
50
ns
MP30
TFH
Minimum Pulse Width
50
—
—
ns
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70135G-page 200
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-14:
QEA/QEB INPUT CHARACTERISTICS
TQ36
QEA
(input)
TQ30
TQ31
TQ35
QEB
(input)
TQ41
TQ40
TQ30
TQ31
TQ35
QEB
Internal
TABLE 24-30: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Max
Units
6 TCY
—
ns
Conditions
TQ30
TQUL
TQ31
TQUH
Quadrature Input High Time
6 TCY
—
ns
TQ35
TQUIN
Quadrature Input Period
12 TCY
—
ns
TQ36
TQUP
Quadrature Phase Period
3 TCY
—
ns
TQ40
TQUFL
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64, 128
and 256 (Note 2)
TQ41
TQUFH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64, 128
and 256 (Note 2)
Note 1:
2:
Quadrature Input Low Time
Typ(2)
These parameters are characterized but not tested in manufacturing.
N = Index Channel Digital Filter Clock Divide Select bits. Refer to Section 16. “Quadrature Encoder
Interface (QEI)” in the “dsPIC30F Family Reference Manual” (DS70046).
© 2010 Microchip Technology Inc.
DS70135G-page 201
dsPIC30F4011/4012
FIGURE 24-15:
QEI MODULE INDEX PULSE TIMING CHARACTERISTICS
QEA
(input)
QEB
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position Counter
Reset
TABLE 24-31: QEI INDEX PULSE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
TQ50
TqIL
Filter Time to Recognize Low,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ51
TqiH
Filter Time to Recognize High,
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ55
Tqidxr
Index Pulse Recognized to Position
Counter Reset (ungated index)
3 TCY
—
ns
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for
forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but
index pulse recognition occurs on falling edge.
DS70135G-page 202
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-16:
SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
SP31
SDI1
LSb
Bit 14 - - - - - -1
MSb
SDO1
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 24-2 for load conditions.
TABLE 24-32: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
TscL
SCK1 Output Low Time(3)
TCY/2
—
—
ns
SP11
TscH
SCK1 Output High
Time(3)
TCY/2
—
—
ns
SP20
TscF
SCK1 Output Fall Time(4
—
—
—
ns
See parameter DO32
SP10
Time(4)
SP21
TscR
SCK1 Output Rise
—
—
—
ns
See parameter DO31
SP30
TdoF
SDO1 Data Output Fall Time(4)
—
—
—
ns
See parameter DO32
SP31
TdoR
SDO1 Data Output Rise
Time(4)
—
—
—
ns
See parameter DO31
SP35
TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
—
—
30
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK1 is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
© 2010 Microchip Technology Inc.
DS70135G-page 203
dsPIC30F4011/4012
FIGURE 24-17:
SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
SP40
SDI1
LSb
Bit 14 - - - - - -1
MSb
SDO1
SP30,SP31
Bit 14 - - - -1
MSb In
LSb In
SP41
Note: Refer to Figure 24-2 for load conditions.
TABLE 24-33: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
SP10
TscL
SCK1 Output Low Time(3)
TCY/2
—
—
ns
SP11
TscH
SCK1 Output High Time(3)
TCY/2
—
—
ns
Time(4)
Conditions
SP20
TscF
SCK1 Output Fall
—
—
—
ns
See parameter DO32
SP21
TscR
SCK1 Output Rise Time(4)
—
—
—
ns
See parameter DO31
SP30
TdoF
SDO1 Data Output Fall
Time(4)
—
—
—
ns
See parameter DO32
SP31
TdoR
SDO1 Data Output Rise
Time(4)
—
—
—
ns
See parameter DO31
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
—
30
ns
SP36
TdoV2sc, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
30
—
—
ns
SP40
TdiV2scH, Setup Time of SDI1 Data
TdiV2scL Input to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
20
—
—
ns
Note 1:
2:
3:
4:
Hold Time of SDI1 Data Input
to SCK1 Edge
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK1 is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
DS70135G-page 204
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-18:
SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SS1
SP52
SP50
SCK1
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDI1
SDI
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 24-2 for load conditions.
© 2010 Microchip Technology Inc.
DS70135G-page 205
dsPIC30F4011/4012
TABLE 24-34: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
—
—
ns
SP70
TscL
SCK1 Input Low Time
30
SP71
TscH
SCK1 Input High Time
30
—
—
ns
SP72
TscF
SCK1 Input Fall Time(3)
—
10
25
ns
Time(3)
Conditions
SP73
TscR
SCK1 Input Rise
—
10
25
ns
SP30
TdoF
SDO1 Data Output Fall Time(3)
—
—
—
ns
See parameter
DO32
SP31
TdoR
SDO1 Data Output Rise Time(3)
—
—
—
ns
See parameter
DO31
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDI1 Data Input
TdiV2scL to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
20
—
—
ns
SP50
TssL2scH, SS1↓ to SCK1↑ or SCK1↓ Input
TssL2scL
120
—
—
ns
SP51
TssH2doZ SS1↑ to SDO1 Output
High-Impedance(3)
10
—
50
ns
SP52
TscH2ssH SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
Note 1:
2:
3:
Hold Time of SDI1 Data Input
to SCK1 Edge
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
Assumes 50 pF load on all SPI pins.
DS70135G-page 206
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-19:
SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SS1
SP52
SP50
SCK1
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35
SP52
MSb
SDO1
Bit 14 - - - - - -1
LSb
SP30,SP31
SDI
SDI1
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 24-2 for load conditions.
© 2010 Microchip Technology Inc.
DS70135G-page 207
dsPIC30F4011/4012
TABLE 24-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
—
—
ns
Conditions
SP70
TscL
SCK1 Input Low Time
30
SP71
TscH
SCK1 Input High Time
30
—
—
ns
SP72
TscF
SCK1 Input Fall Time(3)
—
10
25
ns
SP73
TscR
SCK1 Input Rise Time(3)
—
10
25
ns
SP30
TdoF
SDO1 Data Output Fall Time(3)
—
—
—
ns
See parameter DO32
See parameter DO31
SP31
TdoR
—
—
—
ns
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDI1 Data Input
TdiV2scL to SCK1 Edge
20
—
—
ns
SP41
TscH2diL, Hold Time of SDI1 Data Input
TscL2diL to SCK1 Edge
20
—
—
ns
SP50
TssL2scH, SS1↓ to SCK1↓ or SCK1↑ Input
TssL2scL
120
—
—
ns
SP51
TssH2doZ SS1↑ to SDO1 Output
High-Impedance(4)
10
—
50
ns
SP52
TscH2ssH SS1↑ after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
SP60
TssL2doV SDO1 Data Output Valid after
SS1 Edge
—
—
50
ns
Note 1:
2:
3:
4:
SDO1 Data Output Rise Time
(3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK1 is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
DS70135G-page 208
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-20:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL
IM31
IM34
IM30
IM33
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 24-2 for load conditions.
FIGURE 24-21:
I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM25
IM33
SDA
In
IM40
IM40
IM45
SDA
Out
Note: Refer to Figure 24-2 for load conditions.
© 2010 Microchip Technology Inc.
DS70135G-page 209
dsPIC30F4011/4012
TABLE 24-36: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
I
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
Min(1)
Max
Units
TLO:SCL Clock Low Time 100 kHz mode
TCY/2 (BRG + 1)
—
μs
400 kHz mode
TCY/2 (BRG + 1)
—
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
μs
Clock High Time 100 kHz mode
TCY/2 (BRG + 1)
—
μs
400 kHz mode
TCY/2 (BRG + 1)
—
μs
mode(2)
THI:SCL
Characteristic
TCY/2 (BRG + 1)
—
μs
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(2)
—
—
ns
1 MHz
IM20
TF:SCL
IM21
TR:SCL
IM25
SDA and SCL
Fall Time
SDA and SCL
Rise Time
TSU:DAT Data Input
Setup Time
IM26
THD:DAT Data Input
Hold Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
1 MHz
IM30
TSU:STA
IM31
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
IM33
TSU:STO Stop Condition
Setup Time
IM34
THD:STO Stop Condition
Hold Time
mode(2)
—
—
ns
100 kHz mode
TCY/2 (BRG + 1)
—
μs
400 kHz mode
TCY/2 (BRG + 1)
—
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
μs
100 kHz mode
TCY/2 (BRG + 1)
—
μs
400 kHz mode
TCY/2 (BRG + 1)
—
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
μs
100 kHz mode
TCY/2 (BRG + 1)
—
μs
400 kHz mode
TCY/2 (BRG + 1)
—
μs
1 MHz mode(2)
TCY/2 (BRG + 1)
—
μs
100 kHz mode
TCY/2 (BRG + 1)
—
ns
400 kHz mode
TCY/2 (BRG + 1)
—
ns
(2)
TCY/2 (BRG + 1)
—
ns
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
—
ns
1 MHz mode
IM40
TAA:SCL
IM45
Output Valid
From Clock
TBF:SDA Bus Free Time
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode(2)
IM50
CB
Note 1:
2:
Bus Capacitive Loading
—
—
μs
—
400
pF
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit (I2C™)”
in the “dsPIC30F Family Reference Manual” (DS70046).
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS70135G-page 210
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-22:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL
IS34
IS31
IS30
IS33
SDA
Stop
Condition
Start
Condition
FIGURE 24-23:
I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS25
IS33
SDA
In
IS40
IS40
IS45
SDA
Out
© 2010 Microchip Technology Inc.
DS70135G-page 211
dsPIC30F4011/4012
TABLE 24-37: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
IS10
IS11
IS20
IS21
IS25
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
Characteristic
Clock Low Time
Clock High Time
SDA and SCL
Fall Time
SDA and SCL
Rise Time
Data Input
Setup Time
Min
Max
Units
100 kHz mode
4.7
—
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
Device must operate at a
minimum of 10 MHz.
1 MHz mode(1)
0.5
—
μs
100 kHz mode
4.0
—
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
μs
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
mode(1)
1 MHz
IS26
THD:DAT
Data Input
Hold Time
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
mode(1)
0
0.3
μs
100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
1 MHz mode(1)
0.25
—
μs
100 kHz mode
4.0
—
μs
400 kHz mode
0.6
—
μs
1 MHz mode(1)
0.25
—
μs
100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
1 MHz
IS30
IS31
IS33
TSU:STA
THD:STA
TSU:STO
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
0.6
—
μs
Stop Condition
100 kHz mode
4000
—
ns
Hold Time
400 kHz mode
600
—
ns
mode(1)
250
1 MHz
IS34
THD:STO
1 MHz
IS40
TAA:SCL
Output Valid
From Clock
0
3500
ns
400 kHz mode
0
1000
ns
IS50
Note 1:
TBF:SDA
CB
Bus Free Time
mode(1)
0
350
ns
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode(1)
0.5
—
μs
—
400
pF
Bus Capacitive Loading
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
ns
100 kHz mode
1 MHz
IS45
mode(1)
Conditions
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
DS70135G-page 212
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-24:
C1TX Pin
(output)
CAN MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
C1RX Pin
(input)
CA20
TABLE 24-38: CAN MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
TioF
Port Output Fall Time
—
—
—
ns
See parameter DO32
CA11
TioR
Port Output Rise Time
—
—
—
ns
See parameter DO31
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
500
—
—
ns
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
© 2010 Microchip Technology Inc.
DS70135G-page 213
dsPIC30F4011/4012
TABLE 24-39: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 2.7
—
Lesser of
VDD + 0.3
or 5.5
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
AVDD
V
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 2.7
—
AD06
VREFL
Reference Voltage Low
AVSS
—
AVDD – 2.7
V
AD07
VREF
Absolute Reference Voltage AVSS – 0.3
—
AVDD + 0.3
V
AD08
IREF
Current Drain
—
200
.001
300
3
μA
μA
VREFL
—
VREFH
V
A/D operating
A/D off
Analog Input
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
AVSS – 0.3
—
AVDD + 0.3
V
AD12
—
Leakage Current
—
±0.001
±0.244
μA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V,
Source Impedance = 5 kΩ
AD13
—
Leakage Current
—
±0.001
±0.244
μA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 5 kΩ
Recommended Impedance
of Analog Voltage Source
—
—
5K
Ω
AD17
Absolute Input Voltage
RIN
DC Accuracy
AD20
Nr
Resolution
10 data bits
bits
(3)
—
±1
±1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD21A INL
Integral Nonlinearity(3)
—
±1
±1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD22
DNL
Differential Nonlinearity(3)
—
±1
±1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD22A DNL
Differential Nonlinearity(3)
—
±1
±1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD23
GERR
Gain Error(3)
±1
±5
±6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD23A GERR
Gain Error(3)
±1
±5
±6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD24
EOFF
Offset Error
±1
±2
±3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5V
AD24A EOFF
Offset Error
±1
±2
±3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V
AD25
Monotonicity(2)
—
—
—
AD21
INL
Integral Nonlinearity
—
Note 1:
2:
3:
—
Guaranteed
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
Measurements taken with external VREF+ and VREF- used as the ADC voltage references.
DS70135G-page 214
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
TABLE 24-39: 10-BIT HIGH-SPEED A/D MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min.
Typ
Max.
Units
Conditions
Dynamic Performance
AD30
THD
Total Harmonic Distortion
—
-64
-67
dB
AD31
SINAD
Signal to Noise and
Distortion
—
57
58
dB
AD32
SFDR
Spurious Free Dynamic
Range
—
67
71
dB
AD33
FNYQ
Input Signal Bandwidth
—
—
500
kHz
AD34
ENOB
Effective Number of Bits
9.29
9.41
—
bits
Note 1:
2:
3:
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
Measurements taken with external VREF+ and VREF- used as the ADC voltage references.
© 2010 Microchip Technology Inc.
DS70135G-page 215
dsPIC30F4011/4012
FIGURE 24-25:
10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS
(CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000)
AD50
ADCLK
Instruction
Execution Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
AD55
TSAMP
AD55
DONE
ADIF
ADRES(0)
ADRES(1)
1
2
3
4
5
6
8
9
5
6
8
9
1 - Software sets ADCONx. SAMP to start sampling.
2 - Sampling starts after discharge period.
TSAMP is described in Section 17. 10-Bit A/D Converter” in the “dsPIC30F Family Reference Manual” (DS70046).
3 - Software clears ADCONx. SAMP to start conversion.
4 - Sampling ends, conversion sequence starts.
5 - Convert bit 9.
6 - Convert bit 8.
8 - Convert bit 0.
9 - One TAD for end of conversion.
DS70135G-page 216
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
FIGURE 24-26:
10-BIT HIGH-SPEED A/D CONVERSION TIMING CHARACTERISTICS
(CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)
AD50
ADCLK
Instruction
Execution Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP
TSAMP
AD55
TCONV
AD55
DONE
ADIF
ADRES(0)
ADRES(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
1 - Software sets ADCONx. ADON to start AD operation.
5 - Convert bit 0.
2 - Sampling starts after discharge period.
TSAMP is described in Section 17. 10-Bit A/D Converter”
in the “dsPIC30F Family Reference Manual” (DS70046).
6 - One TAD for end of conversion.
3 - Convert bit 9.
8 - Sample for time specified by SAMC.
7 - Begin conversion of next channel
4 - Convert bit 8.
© 2010 Microchip Technology Inc.
DS70135G-page 217
dsPIC30F4011/4012
TABLE 24-40: 10-BIT HIGH-SPEED A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
—
84
—
ns
700
900
1100
ns
Conditions
Clock Parameters
AD50
TAD
A/D Clock Period
AD51
tRC
A/D Internal RC Oscillator Period
See Table 20-2(1)
Conversion Rate
AD55
tCONV
Conversion Time
—
12 TAD
—
—
AD56
FCNV
Throughput Rate
—
1.0
—
Msps
See Table 20-2(1)
AD57
TSAMP
Sample Time
—
1 TAD
—
—
See Table 20-2(1)
—
1.0 TAD
—
—
Timing Parameters
AD60
tPCS
Conversion Start from Sample
Trigger
AD61
tPSS
Sample Start from Setting
Sample (SAMP) Bit
0.5 TAD
—
1.5 TAD
—
AD62
tCSS
Conversion Completion to
Sample Start (ASAM = 1)
—
0.5 TAD
—
—
AD63
tDPU(2)
Time to Stabilize Analog Stage
from A/D Off to A/D On
—
—
20
μs
Note 1:
2:
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
tDPU is the time required for the ADC module to stabilize when it is turned on (ADCON1 = 1). During this time the ADC result is indeterminate.
DS70135G-page 218
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
25.0
PACKAGING INFORMATION
25.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
dsPIC30F401230I/SP e3
0710017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
0710017
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
dsPIC30F401230I/SO e3
dsPIC30F401130I/P e3
0710017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2010 Microchip Technology Inc.
DS70135G-page 219
dsPIC30F4011/4012
Package Marking Information (Continued)
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS70135G-page 220
Example
dsPIC30F
4012-30I/
ML e3
0710017
Example
dsPIC30F
4011-30I/
PT e3
0710017
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
25.2
Package Details
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
28
Pitch
e
Top to Seating Plane
A
–
–
.200
Molded Package Thickness
A2
.120
.135
.150
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.335
Molded Package Width
E1
.240
.285
.295
Overall Length
D
1.345
1.365
1.400
Tip to Seating Plane
L
.110
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.050
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
© 2010 Microchip Technology Inc.
DS70135G-page 221
dsPIC30F4011/4012
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1 2 3
e
b
h
α
A2
A
h
c
φ
L
A1
Units
Dimension Limits
Number of Pins
β
L1
MILLMETERS
MIN
N
NOM
MAX
28
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
2.05
–
–
Standoff §
A1
0.10
–
0.30
Overall Width
E
Molded Package Width
E1
7.50 BSC
Overall Length
D
17.90 BSC
2.65
10.30 BSC
Chamfer (optional)
h
0.25
–
0.75
Foot Length
L
0.40
–
1.27
Footprint
L1
1.40 REF
Foot Angle Top
φ
0°
–
8°
Lead Thickness
c
0.18
–
0.33
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
DS70135G-page 222
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
40
Pitch
e
Top to Seating Plane
A
–
–
.250
Molded Package Thickness
A2
.125
–
.195
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.590
–
.625
Molded Package Width
E1
.485
–
.580
Overall Length
D
1.980
–
2.095
Tip to Seating Plane
L
.115
–
.200
Lead Thickness
c
.008
–
.015
b1
.030
–
.070
b
.014
–
.023
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.700
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-016B
© 2010 Microchip Technology Inc.
DS70135G-page 223
dsPIC30F4011/4012
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
E2
b
2
2
1
N
1
N
NOTE 1
TOP VIEW
K
L
BOTTOM VIEW
A
A3
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
44
Pitch
e
Overall Height
A
0.80
0.65 BSC
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
0.20 REF
Overall Width
E
Exposed Pad Width
E2
Overall Length
D
Exposed Pad Length
D2
6.30
6.45
6.80
b
0.25
0.30
0.38
Contact Length
L
0.30
0.40
0.50
Contact-to-Exposed Pad
K
0.20
–
–
Contact Width
8.00 BSC
6.30
6.45
6.80
8.00 BSC
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
DS70135G-page 224
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
φ
c
β
A2
A1
L
L1
Units
Dimension Limits
Number of Leads
MILLIMETERS
MIN
N
NOM
MAX
44
Lead Pitch
e
Overall Height
A
–
0.80 BSC
–
Molded Package Thickness
A2
0.95
1.00
1.05
Standoff
A1
0.05
–
0.15
Foot Length
L
0.45
0.60
0.75
Footprint
L1
1.20
1.00 REF
Foot Angle
φ
Overall Width
E
12.00 BSC
Overall Length
D
12.00 BSC
Molded Package Width
E1
10.00 BSC
Molded Package Length
D1
10.00 BSC
0°
3.5°
7°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.30
0.37
0.45
Mold Draft Angle Top
α
11°
12°
13°
Mold Draft Angle Bottom
β
11°
12°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076B
© 2010 Microchip Technology Inc.
DS70135G-page 225
dsPIC30F4011/4012
NOTES:
DS70135G-page 226
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
APPENDIX A:
REVISION HISTORY
Revision D (August 2006)
Previous versions of this data sheet contained
Advance or Preliminary Information. They were
distributed with incomplete characterization data.
This revision reflects these changes:
• Revised I2C Slave Addresses
(see Table 17-1)
• Updated Section 20.0 “10-bit, High-Speed
Analog-to-Digital Converter (ADC) Module” to
more fully describe configuration guidelines
• Base Instruction CP1 removed from instruction
set (see Table 22-2)
• Revised Electrical Characteristics:
- Operating Current (IDD) Specifications
(seeTable 24-5)
- Idle Current (IIDLE) Specifications
(see Table 24-6)
- Power-Down Current (IPD) Specifications
(see Table 24-7)
- I/O Pin Input Specifications
(see Table 24-8)
- BOR Voltage Limits
(see Table 24-11)
- Watchdog Timer Time-out Limits
(see Table 24-21)
Revision E (January 2007)
- This revision includes updates to the
packaging diagrams.
© 2010 Microchip Technology Inc.
Revision F (March 2008)
This revision reflects these updates:
• Added Note 1 to 32-bit Timer4/5 Block Diagram
(see Figure 11-1) and 16-bit Timer4/5 Block
Diagram (see Figure 11-2)
• Changed the location of the input reference in the
10-bit High-Speed ADC Functional Block Diagram
(see Figure 20-1)
• Added FUSE Configuration Register (FICD)
details (see Section 21.6 “Device Configuration
Registers” and Table 21-8)
• Removed erroneous statement regarding generation of CAN receive errors (see Section 19.4.5
“Receive Errors”)
• Electrical Specifications:
- Resolved TBD values for parameters DO10,
DO16, DO20, and DO26 (see Table 24-9)
- 10-bit High-Speed ADC tPDU timing parameter (time to stabilize) has been updated from
20 µs typical to 20 µs maximum (see
Table 24-40)
- Parameter OS65 (Internal RC Accuracy) has
been expanded to reflect multiple Min and
Max values for different temperatures (see
Table 24-18)
- Parameter DC12 (RAM Data Retention Voltage) has been updated to include a Min value
(see Table 24-4)
- Parameter D134 (Erase/Write Cycle Time)
has been updated to include Min and Max
values and the Typ value has been removed
(see Table 24-11)
- Removed parameters OS62 (Internal FRC
Jitter) and OS64 (Internal FRC Drift) and
Note 2 from AC Characteristics (see
Table 24-17)
- Parameter OS63 (Internal FRC Accuracy)
has been expanded to reflect multiple Min
and Max values for different temperatures
(see Table 24-17)
- Updated Min and Max values and Conditions
for parameter SY11 and updated Min, Typ,
and Max values and Conditions for parameter SY20 (see Table 24-20)
• Corrected erroneous device number (see
“Product Identification System”)
• Additional minor corrections throughout the
document
DS70135G-page 227
dsPIC30F4011/4012
Revision G (December 2010)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in Table A-1.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit
Digital Signal Controllers”
Added Note 1 to all QFN pin diagrams (see “Pin Diagrams”).
Section 15.0 “Motor Control
PWM Module”
Added the IUE bit (PWMCON2) to the PWM Register Map (see Table 15-1).
Updated the PWM Period equations (see Equation 15-1 and Equation 15-2).
Section 21.0 “System
Integration”
Added a shaded note on OSCTUN functionality in Section 21.2.5 “Fast RC
Oscillator (FRC)”.
Section 24.0 “Electrical
Characteristics”
Updated the maximum value for parameter DI19 and the minimum value for
parameter DI29 in the I/O Pin Input Specifications (see Table 24-8).
Removed parameter D136 and updated the minimum, typical, maximum, and
conditions for parameters D122 and D134 in the Program and EEPROM
specifications (see Table 24-11).
“Product Identification System”
DS70135G-page 228
Added the “ML” package definition.
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
INDEX
Numerics
10-Bit, High-Speed Analog-to-Digital Converter (ADC) Module ............................................................................. 137
16-bit Up/Down Position Counter Mode.............................. 90
Count Direction Status ................................................ 90
Counter Reset............................................................. 90
Error Checking ............................................................ 90
A
AC Characteristics ............................................................ 184
Load Conditions ........................................................ 184
Temperature and Voltage Specifications .................. 184
ADC
1 Msps Configuration Guideline................................ 142
600 ksps Configuration Guideline ............................. 143
750 ksps Configuration Guideline ............................. 143
Aborting a Conversion .............................................. 140
Acquisition Requirements ......................................... 144
ADCHS ..................................................................... 137
ADCON1 ................................................................... 137
ADCON2 ................................................................... 137
ADCON3 ................................................................... 137
ADCSSL.................................................................... 137
ADPCFG ................................................................... 137
Configuring Analog Port Pins.................................... 146
Connection Considerations....................................... 146
Conversion Operation ............................................... 139
Conversion Rate Parameters.................................... 141
Conversion Speeds................................................... 141
Effects of a Reset...................................................... 145
Operation During CPU Idle Mode ............................. 145
Operation During CPU Sleep Mode.......................... 145
Output Formats ......................................................... 145
Power-Down Modes.................................................. 145
Programming the Start of Conversion Trigger .......... 140
Register Map............................................................. 147
Result Buffer ............................................................. 139
Selecting the Conversion Clock ................................ 140
Selecting the Conversion Sequence......................... 139
Voltage Reference Schematic .................................. 142
Address Generator Units .................................................... 37
Alternate 16-bit Timer/Counter............................................ 91
Alternate Interrupt Vector Table .......................................... 47
Assembler
MPASM Assembler................................................... 172
B
Barrel Shifter ....................................................................... 24
Bit-Reversed Addressing .................................................... 40
Example ...................................................................... 40
Implementation ........................................................... 40
Modifier Values (table) ................................................ 41
Sequence Table (16-Entry)......................................... 41
Block Diagrams
10-Bit, High-Speed ADC ........................................... 138
16-bit Timer1 Module .................................................. 66
16-bit Timer4............................................................... 76
16-bit Timer5............................................................... 76
32-bit Timer4/5............................................................ 75
ADC Analog Input Model .......................................... 144
CAN Buffers and Protocol Engine............................. 128
Dedicated Port Structure............................................. 59
DSP Engine ................................................................ 21
© 2010 Microchip Technology Inc.
dsPIC30F4011............................................................ 10
dsPIC30F4012............................................................ 11
External Power-on Reset Circuit .............................. 157
I2C ............................................................................ 112
Input Capture Mode.................................................... 79
Oscillator System...................................................... 151
Output Compare Mode ............................................... 83
PWM Module .............................................................. 96
Quadrature Encoder Interface .................................... 89
Reset System ........................................................... 155
Shared Port Structure................................................. 60
SPI............................................................................ 108
SPI Master/Slave Connection................................... 108
UART Receiver......................................................... 120
UART Transmitter..................................................... 119
BOR. See Brown-out Reset.
Brown-out Reset
Characteristics.......................................................... 182
C
C Compilers
MPLAB C18.............................................................. 172
CAN Module ..................................................................... 127
Baud Rate Setting .................................................... 132
CAN1 Register Map.................................................. 134
Frame Types ............................................................ 127
Message Reception.................................................. 130
Message Transmission............................................. 131
Modes of Operation .................................................. 129
Overview................................................................... 127
Center-Aligned PWM .......................................................... 99
Code Examples
Data EEPROM Block Erase ....................................... 56
Data EEPROM Block Write ........................................ 58
Data EEPROM Read.................................................. 55
Data EEPROM Word Erase ....................................... 56
Data EEPROM Word Write ........................................ 57
Erasing a Row of Program Memory ........................... 51
Initiating a Programming Sequence ........................... 52
Loading Write Latches................................................ 52
Port Write/Read .......................................................... 60
Code Protection ................................................................ 149
Complementary PWM Operation...................................... 100
Configuring Analog Port Pins.............................................. 60
Core Overview .................................................................... 17
Core Register Map.............................................................. 34
Customer Change Notification Service............................. 235
Customer Notification Service .......................................... 235
Customer Support............................................................. 235
D
Data Access from Program Memory
Using Program Space Visibility .................................. 28
Data Accumulators and Adder/Subtracter .......................... 22
Data Space Write Saturation ...................................... 24
Overflow and Saturation ............................................. 22
Round Logic ............................................................... 23
Write-Back .................................................................. 23
Data Address Space........................................................... 29
Alignment.................................................................... 32
Alignment (Figure) ...................................................... 32
Data Spaces ............................................................... 32
Effect of Invalid Memory Accesses............................. 32
MCU and DSP (MAC Class) Instructions Example .... 31
DS70135G-page 229
dsPIC30F4011/4012
Memory Map ............................................................... 30
Near Data Space ........................................................ 33
Software Stack ............................................................ 33
Width ........................................................................... 32
Data EEPROM Memory ...................................................... 55
Erasing ........................................................................ 56
Erasing, Block ............................................................. 56
Erasing, Word ............................................................. 56
Protection Against Spurious Write .............................. 58
Reading....................................................................... 55
Write Verify ................................................................. 58
Writing ......................................................................... 57
Writing, Block .............................................................. 58
Writing, Word .............................................................. 57
DC Characteristics ............................................................ 176
BOR .......................................................................... 183
I/O Pin Input Specifications ....................................... 181
I/O Pin Output Specifications .................................... 182
Idle Current (IIDLE) .................................................... 179
Operating Current (IDD)............................................. 178
Power-Down Current (IPD) ........................................ 180
Program and EEPROM............................................. 183
DC Temperature and Voltage Specifications .................... 177
Dead-Time Generators ..................................................... 100
Ranges...................................................................... 101
Development Support ....................................................... 171
Device Configuration
Register Map............................................................. 162
Device Configuration Registers......................................... 160
FBORPOR ................................................................ 160
FGS........................................................................... 160
FOSC ........................................................................ 160
FWDT........................................................................ 160
Divide Support..................................................................... 20
DSP Engine......................................................................... 20
Multiplier...................................................................... 22
dsPIC30F4011 Port Register Map ...................................... 61
dsPIC30F4012 Port Register Map ...................................... 62
Dual Output Compare Match Mode .................................... 84
Continuous Output Pulse Mode .................................. 84
Single Output Pulse Mode .......................................... 84
E
Edge-Aligned PWM............................................................. 99
Electrical Characteristics................................................... 175
Equations
A/D Conversion Clock ............................................... 140
Baud Rate ................................................................. 123
I2CBRG Value .......................................................... 116
PWM Period ................................................................ 98
PWM Period (Center-Aligned Mode) .......................... 98
PWM Resolution ......................................................... 98
Time Quantum for Clock Generation ........................ 133
Errata .................................................................................... 8
External Interrupt Requests ................................................ 47
F
Fast Context Saving............................................................ 47
Flash Program Memory....................................................... 49
In-Circuit Serial Programming (ICSP) ......................... 49
Run-Time Self-Programming (RTSP) ......................... 49
Table Instruction Operation Summary ........................ 49
DS70135G-page 230
I
I/O Ports
Parallel I/O (PIO) ........................................................ 59
I2C Module
10-bit Slave Mode Operation .................................... 113
Reception ......................................................... 114
Transmission .................................................... 114
7-bit Slave Mode Operation ...................................... 113
Reception ......................................................... 113
Transmission .................................................... 113
Addresses................................................................. 113
Automatic Clock Stretch ........................................... 114
During 10-bit Addressing (STREN = 1) ............ 114
During 7-bit Addressing (STREN = 1) .............. 114
Reception ......................................................... 114
Transmission .................................................... 114
General Call Address Support .................................. 115
Interrupts .................................................................. 115
IPMI Support............................................................. 115
Master Operation ...................................................... 115
Baud Rate Generator (BRG) ............................ 116
Clock Operation................................................ 116
Multi-Master Communication,
Bus Collision and Arbitration .................... 116
Reception ......................................................... 116
Transmission .................................................... 115
Master Support ......................................................... 115
Operating Function Description ................................ 111
Operation During CPU Sleep and Idle Modes .......... 116
Pin Configuration ...................................................... 111
Programmer’s Model ................................................ 111
Register Map ............................................................ 117
Registers .................................................................. 111
Slope Control ............................................................ 115
Software Controlled Clock Stretching (STREN = 1) . 114
Various Modes.......................................................... 111
In-Circuit Serial Programming (ICSP)............................... 149
Independent PWM Output ................................................ 102
Initialization Condition for RCON Register, Case 1 .......... 158
Initialization Condition for RCON Register, Case 2 .......... 158
Input Capture Module ......................................................... 79
In CPU Idle Mode ....................................................... 80
In CPU Sleep Mode .................................................... 80
Interrupts .................................................................... 81
Register Map .............................................................. 82
Simple Capture Event Mode....................................... 80
Input Change Notification Module....................................... 63
Register Map (bits 7-0) ............................................... 63
Input Diagrams
QEA/QEB Input ........................................................ 199
Instruction Addressing Modes ............................................ 37
File Register Instructions ............................................ 37
Fundamental Modes Supported ................................. 37
MAC Instructions ........................................................ 38
MCU Instructions ........................................................ 37
Move and Accumulator Instructions............................ 38
Other Instructions ....................................................... 38
Instruction Set Summary .................................................. 163
Internal Clock Timing Examples ....................................... 187
Internet Address ............................................................... 235
Interrupt Controller
Register Map .............................................................. 48
Interrupt Priority .................................................................. 44
Interrupt Sequence ............................................................. 47
Interrupt Stack Frame ................................................. 47
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
M
Operating MIPS vs. Voltage.............................................. 176
Oscillator
Configurations........................................................... 152
Fail-Safe Clock Monitor .................................... 154
Fast RC (FRC) .................................................. 153
Initial Clock Source Selection ........................... 152
Low-Power RC (LPRC)..................................... 153
LP ..................................................................... 153
Phase Locked Loop (PLL) ................................ 153
Start-up Timer (OST) ........................................ 152
Operating Modes (Table) .......................................... 150
Oscillator Selection ........................................................... 149
Output Compare Module..................................................... 83
During CPU Idle Mode ................................................ 86
During CPU Sleep Mode............................................. 86
Interrupts..................................................................... 86
Register Map............................................................... 87
Diagram ...................................................................... 19
Programming Operations.................................................... 51
Algorithm for Program Flash....................................... 51
Erasing a Row of Program Memory ........................... 51
Initiating the Programming Sequence ........................ 52
Loading Write Latches................................................ 52
Protection Against Accidental Writes to OSCCON ........... 154
PWM Duty Cycle Comparison Units ................................. 100
Duty Cycle Register Buffers ..................................... 100
PWM Fault Pin.................................................................. 103
Enable Bits ............................................................... 103
Fault States .............................................................. 103
Input Modes.............................................................. 103
Cycle-by-Cycle ................................................. 103
Latched............................................................. 103
PWM Operation During CPU Idle Mode ........................... 104
PWM Operation During CPU Sleep Mode........................ 104
PWM Output and Polarity Control..................................... 103
Output Pin Control .................................................... 103
PWM Output Override ...................................................... 102
Complementary Output Mode .................................. 102
Synchronization ........................................................ 102
PWM Period........................................................................ 98
PWM Special Event Trigger.............................................. 104
Postscaler................................................................. 104
PWM Time Base................................................................. 97
Continuous Up/Down Count Modes ........................... 97
Double Update Mode.................................................. 98
Free-Running Mode.................................................... 97
Postscaler................................................................... 98
Prescaler .................................................................... 98
Single-Shot Mode ....................................................... 97
PWM Update Lockout....................................................... 104
P
Q
Packaging ......................................................................... 219
Details ....................................................................... 221
Marking ..................................................................... 219
Pinout Descriptions
dsPIC30F4011 ............................................................ 12
dsPIC30F4012 ............................................................ 14
POR. See Power-on Reset.
Position Measurement Mode .............................................. 91
Power-Saving Modes ........................................................ 159
Idle ............................................................................ 160
Sleep......................................................................... 159
Power-Saving Modes (Sleep and Idle) ............................. 149
Program Address Space ..................................................... 25
Construction................................................................ 26
Data Access From Program Memory Using Table Instructions ............................................................ 27
Data Access From, Address Generation .................... 26
Memory Map ............................................................... 25
Table Instructions
TBLRDH ............................................................. 27
TBLRDL .............................................................. 27
TBLWTH ............................................................. 27
TBLWTL.............................................................. 27
Program Counter ................................................................ 18
Program Data Table Access (lsw) ...................................... 27
Program Data Table Access (MSB) .................................... 28
Program Space Visibility
Window into Program Space Operation...................... 29
Programmable Digital Noise Filters .................................... 91
Programmer’s Model........................................................... 18
QEI Module
Operation During CPU Sleep Mode ........................... 91
Timer Operation During CPU Sleep Mode ................. 91
Quadrature Encoder Interface (QEI)................................... 89
Interrupts .................................................................... 92
Logic ........................................................................... 90
Operation During CPU Idle Mode............................... 92
Register Map .............................................................. 93
Timer Operation During CPU Idle Mode..................... 92
Microchip Internet Web Site .............................................. 235
Modulo Addressing ............................................................. 38
Applicability ................................................................. 40
Operation Example ..................................................... 39
Start and End Address................................................ 39
W Address Register Selection .................................... 39
Motor Control PWM Module................................................ 95
Register Map............................................................. 105
MPLAB ASM30 Assembler, Linker, Librarian ................... 172
MPLAB Integrated Development Environment Software .. 171
MPLAB PM3 Device Programmer .................................... 174
MPLAB REAL ICE In-Circuit Emulator System................. 173
MPLINK Object Linker/MPLIB Object Librarian ................ 172
O
© 2010 Microchip Technology Inc.
R
Reader Response............................................................. 236
Reset ........................................................................ 149, 155
BOR, Programmable ................................................ 157
Oscillator Start-up Timer (OST)................................ 149
POR.......................................................................... 155
Long Crystal Start-up Time............................... 157
Operating Without FSCM and PWRT............... 157
Power-on Reset (POR)............................................. 149
Power-up Timer (PWRT) .......................................... 149
Programmable Brown-out Reset (BOR) ................... 149
Reset Sequence ................................................................. 45
Reset Sources ............................................................ 45
Revision History................................................................ 227
RTSP
Control Registers........................................................ 50
NVMADR ............................................................ 50
NVMADRU ......................................................... 50
NVMCON............................................................ 50
NVMKEY ............................................................ 50
Operation.................................................................... 50
DS70135G-page 231
dsPIC30F4011/4012
S
Simple Capture Event Mode
Capture Buffer Operation............................................ 80
Capture Prescaler ....................................................... 80
Hall Sensor Mode ....................................................... 80
Timer2 and Timer3 Selection Mode ............................ 80
Simple Output Compare Match Mode................................. 84
Simple PWM Mode ............................................................. 84
Input Pin Fault Protection............................................ 84
Period.......................................................................... 85
Single Pulse PWM Operation............................................ 102
Software Simulator (MPLAB SIM)..................................... 173
Software Stack Pointer, Frame Pointer............................... 18
CALL Stack Frame...................................................... 33
SPI Module........................................................................ 107
Framed SPI Support ................................................. 108
Operating Function Description ................................ 107
Operation During CPU Idle Mode ............................. 109
Operation During CPU Sleep Mode .......................... 109
Register Map............................................................. 110
SDO1 Disable ........................................................... 107
Slave Select Synchronization ................................... 109
Word and Byte Communication ................................ 107
STATUS Register................................................................ 18
System Integration
Overview ................................................................... 149
Register Map............................................................. 162
T
Thermal Operating Conditions .......................................... 176
Thermal Packaging Characteristics .................................. 176
Timer1 Module
16-bit Asynchronous Counter Mode ........................... 65
16-bit Synchronous Counter Mode ............................. 65
16-bit Timer Mode ....................................................... 65
Gate Operation ........................................................... 66
Interrupt....................................................................... 67
Operation During Sleep Mode .................................... 66
Prescaler ..................................................................... 66
Real-Time Clock ......................................................... 67
RTC Interrupts .................................................... 67
RTC Oscillator Operation.................................... 67
Register Map............................................................... 68
Timer2 and Timer3 Selection Mode .................................... 84
Timer2/3 Module
16-bit Timer Mode ....................................................... 69
32-bit Synchronous Counter Mode ............................. 69
32-bit Timer Mode ....................................................... 69
ADC Event Trigger ...................................................... 72
Gate Operation ........................................................... 72
Interrupt....................................................................... 72
Operation During Sleep Mode .................................... 72
Register Map............................................................... 73
Timer Prescaler........................................................... 72
Timer4/5 Module ................................................................. 75
Register Map............................................................... 77
Timing Diagram
A/D Conversion
10-Bit High-Speed (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111,
SAMC = 00001) ............................... 216
I2C Bus Data (Slave Mode)....................................... 209
Timing Diagrams
A/D Conversion
10-Bit High-Speed (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) ................. 215
DS70135G-page 232
Band Gap Start-up Time........................................... 191
CAN Bit ..................................................................... 132
CAN Module I/O........................................................ 211
Center-Aligned PWM .................................................. 99
CLKO and I/O ........................................................... 189
Dead-Time Timing .................................................... 101
Edge-Aligned PWM .................................................... 99
External Clock........................................................... 184
I2C Bus Data (Master Mode) .................................... 207
I2C Bus Start/Stop Bits (Master Mode) ..................... 207
I2C Bus Start/Stop Bits (Slave Mode) ....................... 209
Input Capture ............................................................ 195
Motor Control PWM .................................................. 198
Motor Control PWM Module Fault ............................ 198
Output Compare ....................................................... 196
Output Compare/PWM ............................................. 197
PWM Output ............................................................... 85
QEI Module External Clock....................................... 194
QEI Module Index Pulse ........................................... 200
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 190
SPI Master Mode (CKE = 0) ..................................... 201
SPI Master Mode (CKE = 1) ..................................... 202
SPI Slave Mode (CKE = 0) ....................................... 203
SPI Slave Mode (CKE = 1) ....................................... 205
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ..................... 156
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ..................... 156
Time-out Sequence on Power-up
(MCLR Tied to VDD) ......................................... 156
Timerx External Clock............................................... 192
Timing Requirements
A/D Conversion
10-Bit High-Speed ............................................ 217
Band Gap Start-up Time........................................... 191
CAN Module I/O........................................................ 211
CLKO and I/O ........................................................... 189
External Clock........................................................... 185
I2C Bus Data (Master Mode) .................................... 208
I2C Bus Data (Slave Mode) ...................................... 210
Input Capture ............................................................ 195
Motor Control PWM .................................................. 198
Output Compare ....................................................... 196
QEI Module External Clock....................................... 194
QEI Module Index Pulse ........................................... 200
Quadrature Decoder ................................................. 199
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 191
Simple Output Compare/PWM Mode ....................... 197
SPI Master Mode (CKE = 0) ..................................... 201
SPI Master Mode (CKE = 1) ..................................... 202
SPI Slave Mode (CKE = 0) ....................................... 204
SPI Slave Mode (CKE = 1) ....................................... 206
Timer1 External Clock .............................................. 192
Timer2 and Timer4 External Clock ........................... 193
Timer3 and Timer5 External Clock ........................... 193
Timing Specifications
PLL Clock ................................................................. 186
PLL Jitter .................................................................. 186
Trap Vectors ....................................................................... 46
Traps................................................................................... 45
Hard and Soft ............................................................. 46
Trap Sources .............................................................. 45
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
U
UART
Address Detect Mode ............................................... 123
Alternate I/O.............................................................. 121
Auto-Baud Support ................................................... 124
Baud Rate Generator................................................ 123
Disabling ................................................................... 121
Enabling and Setting Up ........................................... 121
Loopback Mode ........................................................ 123
Module Overview ...................................................... 119
Operation During CPU Sleep and Idle Modes .......... 124
Receiving Data.......................................................... 122
In 8-bit or 9-bit Data Mode ................................ 122
Interrupt ............................................................ 122
Receive Buffer (UxRCB) ................................... 122
Reception Error Handling.......................................... 122
Framing Error (FERR) ...................................... 123
Idle Status ......................................................... 123
Parity Error (PERR) .......................................... 123
Receive Break .................................................. 123
Receive Buffer Overrun Error (OERR Bit) ........ 122
Setting Up Data, Parity and Stop Bit Selections ....... 121
Transmitting Data...................................................... 121
Break ................................................................ 122
In 8-bit Data Mode ............................................ 121
In 9-bit Data Mode ............................................ 121
Interrupt ............................................................ 122
Transmit Buffer (UxTXB) .................................. 121
UART1 Register Map................................................ 125
UART2 Register Map................................................ 125
Unit ID Locations............................................................... 149
Universal Asynchronous Receiver
Transmitter Module (UART)...................................... 119
W
Wake-up from Sleep ......................................................... 149
Wake-up from Sleep and Idle ............................................. 47
Watchdog Timer (WDT) ............................................ 149, 159
Enabling and Disabling ............................................. 159
Operation .................................................................. 159
WWW Address.................................................................. 235
WWW, On-Line Support ....................................................... 8
© 2010 Microchip Technology Inc.
DS70135G-page 233
dsPIC30F4011/4012
NOTES:
DS70135G-page 234
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
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Questions (FAQ), technical support requests,
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program member listing
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ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
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support. Local sales offices are also available to help
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Technical support is available through the web site
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CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
© 2010 Microchip Technology Inc.
DS70135G-page 235
dsPIC30F4011/4012
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
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Device: dsPIC30F4011/4012
Literature Number: DS70135G
Questions:
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DS70135G-page 236
© 2010 Microchip Technology Inc.
dsPIC30F4011/4012
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
d s P I C 3 0 F 4 0 11 AT- 3 0 I / P F - 0 0 0
Custom ID (3 digits) or
Engineering Sample (ES)
Trademark
Architecture
SP
SO
P
ML
PT
S
W
Flash
Memory Size in Bytes
0 = ROMless
1 = 1K to 6K
2 = 7K to 12K
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
Package
= 28L PDIP (Skinny DIP)
= 28L SOIC
= 40L PDIP
= 44L QFN 8x8
= 44L TQFP 10x10
= Die (Waffle Pack)
= Die (Wafers)
Temperature
I = Industrial -40°C to +85°C
E = Extended High Temp -40°C to +125°C
Speed
20 = 20 MIPS
30 = 30 MIPS
Device ID
T = Tape and Reel
A,B,C… = Revision Level
Example:
dsPIC30F4011AT-30I/PF = 30 MIPS, Industrial temp., TQFP package, Rev. A
© 2010 Microchip Technology Inc.
DS70135G-page 237
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
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08/04/10
DS70135G-page 238
© 2010 Microchip Technology Inc.
