dsPIC30F5011/5013
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2011 Microchip Technology Inc.
DS70116J
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-843-6
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70116J-page 2
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
High-Performance, Digital Signal Controllers
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
High-Performance Modified RISC CPU:
•
•
•
•
•
•
•
•
•
•
Modified Harvard architecture
C compiler optimized instruction set architecture
Flexible addressing modes
83 base instructions
24-bit wide instructions, 16-bit wide data path
66 Kbytes on-chip Flash program space
4 Kbytes of on-chip data RAM
1 Kbyte of nonvolatile data EEPROM
16 x 16-bit working register array
Up to 30 MIPS operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
• Up to 41 interrupt sources:
- Eight user selectable priority levels
- Five external interrupt sources
- Four processor traps
DSP Features:
• Dual data fetch
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single cycle hardware fractional/
integer multiplier
• All DSP instructions are single cycle
- Multiply-Accumulate (MAC) operation
• Single cycle ±16 shift
© 2011 Microchip Technology Inc.
Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Five 16-bit timers/counters; optionally pair up
16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• Data Converter Interface (DCI) supports common
audio codec protocols, including I2S and AC’97
• 3-wire SPI modules (supports four Frame modes)
• I2C™ module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Two addressable UART modules with FIFO
buffers
• Two CAN bus modules compliant with CAN 2.0B
standard
Analog Features:
• 12-bit Analog-to-Digital Converter (ADC) with:
- 200 ksps conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
• Programmable Low-Voltage Detection (PLVD)
• Programmable Brown-out Detection and Reset
generation
Special Microcontroller Features:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip
low- power RC oscillator for reliable operation
• Fail-Safe Clock Monitor operation:
- Detects clock failure and switches to on-chip
low-power RC oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Selectable Power Management modes:
- Sleep, Idle and Alternate Clock modes
DS70116J-page 3
dsPIC30F5011/5013
CMOS Technology:
•
•
•
•
Low-power, high-speed Flash technology
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low power consumption
TABLE 1:
dsPIC30F5011/5013 CONTROLLER FAMILY
SPI
I2C™
CAN
Output
Codec A/D 12-bit
SRAM EEPROM Timer Input
Comp/Std
Interface 200 ksps
Bytes
16-bit Cap
Bytes Instructions Bytes
PWM
Pins
UART
Program Memory
Device
dsPIC30F5011
64
66K
22K
4096
1024
5
8
8
AC’97, I2S
16 ch
2
2
1
2
dsPIC30F5013
80
66K
22K
4096
1024
5
8
8
AC’97, I2S
16 ch
2
2
1
2
DS70116J-page 4
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CSDO/RG13
CSDI/RG12
CSCK/RG14
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VSS
OC8/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC30F5011
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC2/OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/INT2/RD9
IC1/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKI
VDD
SCL/RG2
SDA/RG3
EMUC3/SCK1/INT0/RF6
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/CN17/RF4
U2TX/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
COFS/RG15
T2CK/RC1
T3CK/RC2
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/IC8/CN7/RB5
AN4/IC7/CN6/RB4
AN3/CN5/RB3
AN2/SS1/LVDIN/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
© 2011 Microchip Technology Inc.
DS70116J-page 5
dsPIC30F5011/5013
Pin Diagrams (Continued)
IC5/RD12
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
OC7/CN15/RD6
CSCK/RG14
CN23/RA7
CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VSS
OC8/CN16/RD7
CSDI/RG12
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
CSDO/RG13
80-Pin TQFP
COFS/RG15
1
T2CK/RC1
2
T3CK/RC2
3
T4CK/RC3
T5CK/RC4
SCK2/CN8/RG6
4
5
6
60
EMUC1/SOSCO/T1CK/CN0/RC14
59
EMUD1/SOSCI/CN1/RC13
58
EMUC2/OC1/RD0
57
56
IC4/RD11
IC3/RD10
55
IC2/RD9
IC1/RD8
SDI2/CN9/RG7
7
54
SDO2/CN10/RG8
MCLR
8
53
INT4/RA15
9
52
SS2/CN11/RG9
VSS
10
51
INT3/RA14
VSS
VDD
12
49
OSC2/CLKO/RC15
OSC1/CLKI
INT1/RA12
13
48
VDD
SCL/RG2
dsPIC30F5013
11
50
14
47
AN5/CN7/RB5
15
46
SDA/RG3
AN4/CN6/RB4
AN3/CN5/RB3
16
45
17
44
EMUC3/SCK1/INT0/RF6
SDI1/RF7
INT2/RA13
DS70116J-page 6
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
IC7/CN20/RD14
IC8/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
AVDD
AVSS
25
AN8/RB8
24
U1TX/RF3
VREF+/RA10
41
22
20
23
U1RX/RF2
PGD/EMUD/AN0/CN2/RB0
VREF-/RA9
EMUD3/SDO1/RF8
42
21
43
19
AN7/RB7
18
AN6/OCFA/RB6
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 15
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Interrupts .................................................................................................................................................................................... 35
5.0 Address Generator Units............................................................................................................................................................ 41
6.0 Flash Program Memory.............................................................................................................................................................. 47
7.0 Data EEPROM Memory ............................................................................................................................................................. 53
8.0 I/O Ports ..................................................................................................................................................................................... 57
9.0 Timer1 Module ........................................................................................................................................................................... 63
10.0 Timer2/3 Module ........................................................................................................................................................................ 67
11.0 Timer4/5 Module ....................................................................................................................................................................... 73
12.0 Input Capture Module................................................................................................................................................................. 77
13.0 Output Compare Module ............................................................................................................................................................ 81
14.0 SPI™ Module ............................................................................................................................................................................. 87
15.0 I2C™ Module ............................................................................................................................................................................. 91
16.0 Universal Asynchronous Receiver Transmitter (UART) Module ................................................................................................ 99
17.0 CAN Module ............................................................................................................................................................................. 107
18.0 Data Converter Interface (DCI) Module.................................................................................................................................... 117
19.0 12-bit Analog-to-Digital Converter (ADC) Module .................................................................................................................... 127
20.0 System Integration ................................................................................................................................................................... 137
21.0 Instruction Set Summary .......................................................................................................................................................... 151
22.0 Development Support............................................................................................................................................................... 159
23.0 Electrical Characteristics .......................................................................................................................................................... 163
24.0 Packaging Information.............................................................................................................................................................. 203
Index .................................................................................................................................................................................................. 209
The Microchip Web Site ..................................................................................................................................................................... 215
Customer Change Notification Service .............................................................................................................................................. 215
Customer Support .............................................................................................................................................................................. 215
Reader Response .............................................................................................................................................................................. 216
Product Identification System ............................................................................................................................................................ 217
TO OUR VALUED CUSTOMERS
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2011 Microchip Technology Inc.
DS70116J-page 7
dsPIC30F5011/5013
NOTES:
DS70116J-page 8
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
This document contains specific information for the
dsPIC30F5011/5013 Digital Signal Controller (DSC)
devices. The dsPIC30F5011/5013 devices contain
extensive Digital Signal Processor (DSP) functionality
within a high-performance 16-bit microcontroller (MCU)
architecture. Figure 1-1 and Figure 1-2 show device
block diagrams for dsPIC30F5011 and dsPIC30F5013,
respectively.
© 2011 Microchip Technology Inc.
DS70116J-page 9
dsPIC30F5011/5013
FIGURE 1-1:
dsPIC30F5011 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/IC7/CN6/RB4
AN5/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
16
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Address Latch
Program
Memory
(66 Kbytes)
Data EEPROM
(1 Kbyte)
16
Data Latch Data Latch
X Data
Y Data
RAM
RAM
(2 Kbytes)
(2 Kbytes)
Address
Address
Latch
Latch
16 16
16
16
24
24
16
16
Effective Address
16
Data Latch
ROM Latch
PORTB
16
24
IR
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
Power-up
Timer
Timing
Generation
DSP
Engine
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/IC5/CN13/RD4
OC6/IC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/INT1/RD8
IC2/INT2/RD9
IC3/INT3/RD10
IC4/INT4/RD11
Divide
Unit
Oscillator
Start-up Timer
ALU
POR/BOR
MCLR
VDD, VSS
AVDD, AVSS
CAN1,
CAN2
PORTC
16 16
Control Signals
to Various Blocks
OSC1/CLKI
T2CK/RC1
T3CK/RC2
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
16
Watchdog
Timer
Low-Voltage
Detect
12-bit ADC
Timers
Input
Capture
Module
DCI
16
16
PORTD
Output
Compare
Module
I2C™
SPI1,
SPI2
UART1,
UART2
C1RX/RF0
C1TX/RF1
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
PORTF
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15
PORTG
DS70116J-page 10
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 1-2:
dsPIC30F5013 BLOCK DIAGRAM
Y Data Bus
PSV & Table
Data Access
24 Control Block
8
Address Latch
Data EEPROM
(1 Kbyte)
16
PORTA
X RAGU
X WAGU
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Program Memory
(66 Kbytes)
16
Data Latch
Data Latch
X Data
Y Data
RAM
RAM
(2 Kbytes)
(2 Kbytes)
Address
Address
Latch
Latch
16 16
16
16
24
24
16
16
16
Interrupt
Controller
CN22/RA6
CN23/RA7
VREF-/RA9
VREF+/RA10
INT1/RA12
INT2/RA13
INT3/RA14
INT4/RA15
X Data Bus
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
IR
16
16
16 x 16
W Reg Array
Decode
Instruction
Decode &
Control
Control Signals
to Various Blocks
OSC1/CLKI
Power-up
Timer
Timing
Generation
DSP
Engine
Divide
Unit
Oscillator
Start-up Timer
ALU
POR/BOR
MCLR
VDD, VSS
AVDD, AVSS
CAN1,
CAN2
PORTC
16 16
Watchdog
Timer
Low-Voltage
Detect
12-bit ADC
Timers
16
16
PORTD
Input
Capture
Module
DCI
Output
Compare
Module
I2C™
SPI1,
SPI2
UART1,
UART2
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
AN4/CN6/RB4
AN5/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/RC4
EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
PORTF
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15
PORTG
© 2011 Microchip Technology Inc.
DS70116J-page 11
dsPIC30F5011/5013
Table 1-1 provides a brief description of device I/O pinouts and the functions that may be multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN15
I
Analog
Analog input channels.
AN0 and AN1 are also used for device programming data and clock inputs,
respectively.
AVDD
P
P
Positive supply for analog module. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog module. This pin must be connected at all times.
CLKI
CLKO
I
O
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
—
Data Converter Interface Frame Synchronization pin.
Data Converter Interface Serial Clock input/output pin.
Data Converter Interface Serial data input pin.
Data Converter Interface Serial data output pin.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
CAN1 Bus Receive pin.
CAN1 Bus Transmit pin.
CAN2 Bus Receive pin.
CAN2 Bus Transmit pin
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1-IC8
I
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
LVDIN
I
Analog
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an active
low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
Pin Name
Description
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
Low-Voltage Detect Reference Voltage input pin.
Legend: CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
I
= Input
DS70116J-page 12
Analog = Analog input
O
= Output
P
= Power
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
Description
OSC1
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
OSC2
I/O
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
RA6-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1-RC4
RC13-RC15
I/O
I/O
ST
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RF0-RF8
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
I/O
I
O
I
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
—
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
UART2 Transmit.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
Ground reference for logic and I/O pins.
VREF+
I
Analog
Analog Voltage Reference (High) input.
VREF-
I
Analog
Analog Voltage Reference (Low) input.
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when
configured in RC mode; CMOS otherwise.
Legend: CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
I
= Input
© 2011 Microchip Technology Inc.
Analog = Analog input
O
= Output
P
= Power
DS70116J-page 13
dsPIC30F5011/5013
NOTES:
DS70116J-page 14
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
2.0
Note:
2.1
CPU ARCHITECTURE
OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
Core Overview
This section contains a brief overview of the CPU
architecture of the dsPIC30F. For additional hardware and programming information, please refer to
the “dsPIC30F Family Reference Manual” (DS70046)
and the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157), respectively.
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (refer to Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are supported using the DO and REPEAT instructions, both of
which are interruptible at any point.
The working register array consists of 16 x 16-bit registers, each of which can act as data, address or offset
registers. One working register (W15) operates as a
software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Generation Unit (AGU). Most instructions operate solely
through the X memory, AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
© 2011 Microchip Technology Inc.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can
be mapped into the lower half (user space) of program space at any 16K program word boundary,
defined by the 8-bit Program Space Visibility
Page (PSVPAG) register. This lets any instruction
access program space as if it were data space,
with a limitation that the access requires an additional cycle. Moreover, only the lower 16 bits of
each instruction word can be accessed using this
method.
• Linear indirect access of 32K word pages within
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports bit-reversed addressing on
destination effective addresses to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 5.0 “Address Generator Units” for
details on modulo and bit-reversed addressing.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect, Register Offset and Literal Offset Addressing
modes. Instructions are associated with predefined
Addressing modes, depending upon their functional
requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 15 bits
right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by dedicating certain working registers to each address space
for the MAC class of instructions.
DS70116J-page 15
dsPIC30F5011/5013
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest), in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities ranging from 8 to 15.
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start, and popped on loop end.
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC® DSC devices contain a software stack.
W15 is the dedicated software Stack Pointer (SP), and
will be automatically modified by exception processing
and subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
Note:
In order to protect against misaligned
stack accesses, W15 is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS register
(SR), the LSB of which is referred to as the SR Low
byte (SRL) and the MSB as the SR High byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Priority Level status bits, IPL and the Repeat Active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a complete word value which is then stacked.
The upper byte of the STATUS register contains the
DSP Adder/Subtracter status bits, the DO Loop Active
bit (DA) and the Digit Carry (DC) Status bit.
2.2.3
PROGRAM COUNTER
The program counter is 23 bits wide; bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
When a byte operation is performed on a working register, only the Least Significant Byte (LSB) of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes (MSBs) can be manipulated
through byte wide data memory space accesses.
DS70116J-page 16
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 2-1:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
AccA
DSP
Accumulators
AccB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
Data Table Page Address
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
© 2011 Microchip Technology Inc.
DC IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70116J-page 17
dsPIC30F5011/5013
2.3
Divide Support
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and 16/
16-bit signed and unsigned integer divide operations, in
the form of single instruction iterative divides. The
following instructions and data sizes are supported:
•
•
•
•
•
DIVF - 16/16 signed fractional divide
DIV.sd - 32/16 signed divide
DIV.ud - 32/16 unsigned divide
DIV.sw - 16/16 signed divide
DIV.uw - 16/16 unsigned divide
The 16/16 divides are similar to the 32/16 (same number
of iterations), but the dividend is either zero-extended or
sign-extended during the first iteration.
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value and it must, therefore, be
explicitly and correctly specified in the REPEAT instruction as shown in Table 2-2 (REPEAT will execute the target instruction {operand value+1} times). The REPEAT
loop count must be setup for 18 iterations of the DIV/
DIVF instruction. Thus, a complete divide operation
requires 19 cycles.
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
2.4
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform
inherent
accumulator-to-accumulator
operations,
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction (e.g.,
ED, EDAC).
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
•
•
•
•
•
•
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for AccA (SATA)
Automatic saturation on/off for AccB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
Note:
For CORCON layout, see Table 3-3.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-1:
Instruction
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY.N
MSC
TABLE 2-2:
Algebraic
Operation
ACC WB?
A=0
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
No change in A
A=x*y
A=–x*y
A=A–x*y
Yes
No
No
Yes
No
Yes
No
No
Yes
DIVIDE INSTRUCTIONS
Instruction
DIVF
DIV.sd
DIV.sw or DIV.s
DIV.ud
DIV.uw or DIV.u
DS70116J-page 18
DSP INSTRUCTION
SUMMARY
Function
Signed fractional divide: Wm/Wn →W0; Rem →W1
Signed divide: (Wm+1:Wm)/Wn →W0; Rem →W1
Signed divide: Wm/Wn →W0; Rem →W1
Unsigned divide: (Wm+1:Wm)/Wn →W0; Rem →W1
Unsigned divide: Wm/Wn →W0; Rem →W1
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
40
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
40
Saturate
S
a
Round t 16
u
Logic r
a
t
e
Adder
Negate
40
40
40
Barrel
Shifter
16
X Data Bus
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
© 2011 Microchip Technology Inc.
DS70116J-page 19
dsPIC30F5011/5013
2.4.1
MULTIPLIER
The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17 x 17-bit multiplier/scaler is a 33-bit value which is sign-extended to
40 bits. Integer data is inherently represented as a
signed two’s complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF) including ‘0’. For a 32-bit integer,
the data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction
with this implied radix point is -1.0 to (1 – 21-N). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518x10-5. In Fractional mode, the 16x16
multiply operation generates a 1.31 product which has
a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
DS70116J-page 20
2.4.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true, or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS
register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
• OA: AccA overflowed into guard bits
• OB: AccB overflowed into guard bits
• SA: AccA saturated (bit 31 overflow and
saturation)
or
AccA overflowed into guard bits and saturated (bit
39 overflow and saturation)
• SB: AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated (bit
39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to Section 4.0 “Interrupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
The SA and SB bits are modified each time data
passes through the adder/subtracter but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation, or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has
occurred. If the COVTE bit in the INTCON1 register is
set, SA and SB bits will generate an arithmetic warning
trap when saturation is disabled.
The overflow and saturation status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF), or maximally negative 9.31
value (0x8000000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erroneous data, or unexpected algorithm problems (e.g.,
gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF), or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user. When this Saturation
mode is in effect, the guard bits are not used (so
the OA, OB or OAB bits are never set).
• Bit 39 Catastrophic Overflow:
The bit 39 overflow Status bit from the adder is
used to set the SA or SB bit which remain set until
cleared by the user. No saturation operation is
performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic overflow can initiate a trap exception.
© 2011 Microchip Technology Inc.
2.4.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following Addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
• [W13]+=2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block which performs a conventional (biased) or convergent (unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a 16bit, 1.15 data value which is passed to the data space
write saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word (lsw) is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word
(bits 0 through 15 of the accumulator) is between
0x8000 and 0xFFFF (0x8000 included), ACCxH is
incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb
(bit 16 of the accumulator) of ACCxH is examined. If it
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
DS70116J-page 21
dsPIC30F5011/5013
2.4.2.4
Data Space Write Saturation
2.4.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space may also be saturated but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators, or the X bus (to support multi-bit
shifts of register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly, For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MSb of the
source (bit 39) is used to determine the sign of the
operand being tested.
The barrel shifter is 40-bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 16 for left shifts.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
DS70116J-page 22
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
Note:
3.1
MEMORY ORGANIZATION
FIGURE 3-1:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
Program Address Space
The program address space is 4M instruction words. It
is addressable by a 24-bit value from either the 23-bit
PC, table instruction Effective Address (EA), or data
space EA, when program space is mapped into data
space as defined by Table 3-1. Note that the program
space address is incremented by two between successive program words in order to provide compatibility
with data space addressing.
PROGRAM SPACE
MEMORY MAP
Reset - GOTO Instruction
Reset - Target Address
000000
000002
000004
Vector Tables
Interrupt Vector Table
User Memory
Space
3.0
Reserved
Alternate Vector Table
User Flash
Program Memory
(22K instructions)
Reserved
(Read ‘0’s)
Data EEPROM
(1 Kbyte)
00007E
000080
000084
0000FE
000100
00AFFE
00B000
7FFBFE
7FFC00
7FFFFE
800000
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE) for all accesses other than TBLRD/TBLWT,
which use TBLPAG to determine user or configuration space access. In Table 3-1, Program Space
Address Construction, bit 23 allows access to the
Device ID, the User ID and the Configuration bits.
Otherwise, bit 23 is always clear.
Configuration Memory
Space
Reserved
UNITID (32 instr.)
8005BE
8005C0
8005FE
800600
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
© 2011 Microchip Technology Inc.
FEFFFE
FF0000
FFFFFE
DS70116J-page 23
dsPIC30F5011/5013
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
Instruction Access
User
TBLRD/TBLWT
User
(TBLPAG = 0)
TBLPAG
Data EA
TBLRD/TBLWT
Configuration
(TBLPAG = 1)
TBLPAG
Data EA
Program Space Visibility
User
FIGURE 3-2:
PC
0
0
PSVPAG
0
Data EA
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
Select
Using
Program
Space
Visibility
0
1
0
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0
User/
Configuration
Space
Select
Note:
DS70116J-page 24
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
Program space visibility cannot be used to access bits of a word in program memory.
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
A set of table instructions are provided to move byte or
word sized data to and from program space.
1.
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned.
However, as the architecture is modified Harvard, data
can also be present in program space.
There are two methods by which program space can
be accessed: via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the least
significant word of any address within program space,
without going through data space. The TBLRDH and
TBLWTH instructions are the only method whereby the
upper 8 bits of a program space word can be accessed
as data.
2.
3.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the Most Significant data Byte.
4.
TBLRDL: Table Read Low
Word: Read the lsw of the program address;
P maps to D.
Byte: Read one of the LSBs of the program
address;
P maps to the destination byte when byte
select = 0;
P maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming)
TBLRDH: Table Read High
Word: Read the most significant word of the program address; P maps to D;
D will always be = 0.
Byte: Read one of the MSBs of the program
address;
P maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming)
Figure 3-2 shows how the EA is created for table operations and data space accesses (PSV = 1). Here,
P refers to a program space word, whereas
D refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
© 2011 Microchip Technology Inc.
TBLRDL.W
TBLRDL.B (Wn = 0)
TBLRDL.B (Wn = 1)
DS70116J-page 25
dsPIC30F5011/5013
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
TBLRDH.W
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDH.B (Wn = 0)
Program Memory
‘Phantom’ Byte
(read as ‘0’)
3.1.2
TBLRDH.B (Wn = 1)
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM
SPACE VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer to
the “16-bit MCU and DSC Programmer’s Reference
Manual” (DS70157) for details on instruction encoding.
DS70116J-page 26
Note that by incrementing the PC by 2 for each
program memory word, the Least Significant 15 bits of
data space addresses directly map to the Least Significant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the Program Space Visibility Page register, PSVPAG, as
shown in Figure 3-5.
Note:
PSV access is temporarily disabled during
table reads/writes.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions will require one
instruction cycle in addition to the specified
execution time:
- MAC class of instructions with data operand
prefetch
- MOV instructions
- MOV.D instructions
• All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction accessing data, using PSV, to
execute in a single cycle.
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Data Space
Program Space
0x000100
0x0000
EA = 0
PSVPAG(1)
0x01
8
15
Data 16
Space
15
EA
EA = 1
0x8000
15
Address
Concatenation 23
23
15
0
0x008000
Upper Half of Data
Space is Mapped
into Program Space
0x017FFF
0xFFFF
BSET
MOV
MOV
MOV
Note:
CORCON,#2
#0x01, W0
W0, PSVPAG
0x8000, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
PSVPAG is an 8-bit register, containing bits of the program space address (i.e., it defines
the page in program space to which the upper half of data space is being mapped).
© 2011 Microchip Technology Inc.
DS70116J-page 27
dsPIC30F5011/5013
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
FIGURE 3-6:
The data space memory map is shown in Figure 3-6.
The X data space is used by all instructions and supports
all addressing modes, as shown in Figure 3-7.
DATA SPACE MEMORY MAP
MSB
Address
2 Kbyte
SFR Space
4 Kbyte
SRAM Space
16 bits
MSB
LSB
LSB
Address
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
0x0FFF
0x1001
X Data RAM (X)
0x0FFE
0x1000
8 Kbyte
Near
Data
Space
Y Data RAM (Y)
0x17FF
0x1801
0x17FE
0x1800
0x1FFF
0x1FFE
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70116J-page 28
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the 64Kbyte data address space (including all Y addresses).
When executing one of the MAC class of instructions,
the X block consists of the 64 Kbyte data address
space excluding the Y address block (for data reads
only). In other words, all other instructions regard the
entire data memory as one composite address space.
The MAC class instructions extract the Y address space
from data space and address it using EAs sourced from
W10 and W11. The remaining X data space is
addressed using W8 and W9. Both address spaces are
concurrently accessed only with the MAC class
instructions.
0xFFFE
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-7:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write)
MAC Class Ops (Write)
Indirect EA using any W
© 2011 Microchip Technology Inc.
MAC Class Ops (Read)
Indirect EA using W8, W9
Indirect EA using W10, W11
DS70116J-page 29
dsPIC30F5011/5013
3.2.2
DATA SPACES
3.2.3
X data space is used by all instructions and supports all
Addressing modes. There are separate read and write
data buses. The X read data bus is the return data path
for all instructions that view data space as combined X
and Y address space. It is also the X address space
data path for the dual operand read instructions (MAC
class). The X write data bus is the only write path to
data space for all instructions.
The X data space also supports modulo addressing for
all instructions, subject to Addressing mode restrictions. Bit-reversed addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always
address Y data space, independent of X data space,
whereas W8 and W9 always address X data space.
Note that during accumulator write back, the data
address space is considered a combination of X and Y
data spaces, so the write occurs across the X bus.
Consequently, the write can be to any address in the
entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports modulo addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user programmable. Should an EA point to data outside its own
assigned address space, or to a location outside physical memory, an all zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any Addressing mode, an
attempt by a MAC instruction to fetch data from that
space using W8 or W9 (X space pointers) will return
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data
space in a MAC instruction
0x0000
W10 or W11 used to access X
data space in a MAC instruction
0x0000
DATA SPACE WIDTH
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
MCU devices and improve data space memory usage
efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws+1 for byte operations
and Ws+2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a misaligned read or write be attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be executed but
the write will not occur. In either case, a trap will then
be executed, allowing the system and/or user to examine the machine state prior to execution of the address
fault.
FIGURE 3-8:
15
DATA ALIGNMENT
MSB
87
LSB
0
0001
Byte1
Byte 0
0000
0003
Byte3
Byte 2
0002
0005
Byte5
Byte 4
0004
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70116J-page 30
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6
SOFTWARE STACK
There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM
is forced to ‘0’ because all stack operations must be
word aligned. Whenever an effective address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a Stack Error Trap will not
occur. The Stack Error Trap will occur on a subsequent
push operation. Thus, for example, if it is desirable to
cause a Stack Error Trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
0x0000
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
and post-increments for stack pushes as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
Stack Grows Towards
Higher Address
The dsPIC DSC devices contain a software stack. W15
is used as the Stack Pointer.
CALL STACK FRAME
15
0
PC
W15 (before CALL)
000000000 PC
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
3.2.7
DATA RAM PROTECTION FEATURE
The dsPIC30F5011/5013 devices support data RAM
protection features which enable segments of RAM to
be protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM
segment for RAM) is accessible only from the Secure
Segment Flash code when enabled. See Table 3-3 for
the BSRAM and SSRAM SFRs.
© 2011 Microchip Technology Inc.
DS70116J-page 31
DS70116J-page 32
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
W7
W8
W9
W10
W11
W12
W13
W14
W15
SPLIM
ACCAL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 7
—
—
—
PCL
ACCBH
ACCBL
ACCAH
ACCAL
SPLIM
W15
W14
W13
W12
W11
W10
W9
W8
W7
W6
W5
W4
W3
W2
W1
—
W0 / WREG
Bit 8
003E
0040
0042
DOENDL
DOENDH
SR
OA
—
—
OB
—
—
SA
—
—
SB
—
—
OAB
—
—
SAB
—
—
DA
—
—
DC
—
DOENDL
—
DOSTARTL
IPL2
—
—
u = uninitialized bit; — = unimplemented, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
003C
DOSTARTH
Legend:
Note 1:
0038
003A
DCOUNT
DOSTARTL
DCOUNT
—
—
—
Sign-Extension (ACCB)
Bit 9
RCOUNT
TBLPAG
Bit 10
0036
0032
PCH
Bit 11
0034
0030
PCL
Bit 12
Sign-Extension (ACCA)
Bit 13
RCOUNT
002E
ACCBU
Bit 14
PSVPAG
002A
002C
ACCBH
0028
000C
W6
ACCBL
000A
W5
0024
0008
W4
0026
0006
W3
ACCAU
0004
W2
ACCAH
0000
0002
W0
Bit 15
CORE REGISTER MAP(1)
Address
(Home)
W1
SFR Name
TABLE 3-3:
IPL1
Bit 6
IPL0
Bit 5
Bit 3
RA
N
DOENDH
DOSTARTH
PSVPAG
TBLPAG
PCH
ACCBU
ACCAU
Bit 4
OV
Bit 2
Z
Bit 1
C
0
0
Bit 0
0000 0000 0000 0000
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
0000 0000 0uuu uuuu
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 1000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Reset State
dsPIC30F5011/5013
© 2011 Microchip Technology Inc.
—
© 2011 Microchip Technology Inc.
Legend:
Note 1:
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 4
—
—
—
—
SATDW ACCSAT
Bit 5
YWM
SATB
Bit 6
DISICNT
XB
SATA
Bit 7
u = uninitialized bit; — = unimplemented, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
—
—
0752
—
SSRAM
—
—
0750
BSRAM
—
0052
DISICNT
—
0050
XBREV
—
YS
004E
YE
004C
YMODSRT
XS
DL0
Bit 8
YMODEND
—
DL1
Bit 9
BWM
DL2
Bit 10
XE
BREN
EDT
Bit 11
0048
—
US
Bit 12
004A
—
—
Bit 13
XMODSRT
YMODEN
—
Bit 14
XMODEND
XMODEN
0044
0046
CORCON
MODCON
SFR Name
Bit 15
CORE REGISTER MAP(1) (CONTINUED)
Address
(Home)
TABLE 3-3:
—
—
IPL3
Bit 3
RND
Bit 1
1
0
1
0
IF
Bit 0
0000 0000 0000 0000
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuu0
uuuu uuuu uuuu uuu1
uuuu uuuu uuuu uuu0
0000 0000 0000 0000
0000 0000 0010 0000
Reset State
IW_SSR IR_SSR RL_SSR 0000 0000 0000 0000
IW_BSR IR_BSR RL_BSR 0000 0000 0000 0000
XWM
PSV
Bit 2
dsPIC30F5011/5013
DS70116J-page 33
dsPIC30F5011/5013
NOTES:
DS70116J-page 34
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
4.0
Note:
INTERRUPTS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
The dsPIC30F Sensor and General Purpose Family
has up to 41 interrupt sources and 4 processor exceptions (traps) which must be arbitrated based on a
priority scheme.
The CPU is responsible for reading the Interrupt Vector
Table (IVT) and transferring the address contained in
the interrupt vector to the program counter. The interrupt vector is transferred from the program data bus
into the program counter via a 24-bit wide multiplexer
on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004). The IVT and AIVT are
shown in Figure 4-1.
The interrupt controller is responsible for preprocessing the interrupts and processor exceptions
prior to them being presented to the processor core.
The peripheral interrupts and traps are enabled, prioritized and controlled using centralized Special Function
Registers:
• IFS0, IFS1, IFS2
All interrupt request flags are maintained in these
three registers. The flags are set by their respective peripherals or external signals, and they are
cleared via software.
• IEC0, IEC1, IEC2
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
• IPC0... IPC10
The user assignable priority level associated with
each of these 41 interrupts is held centrally in
these twelve registers.
• IPL
The current CPU priority level is explicitly stored
in the IPL bits. IPL is present in the CORCON
register, whereas IPL are present in the
STATUS register (SR) in the processor core.
• INTCON1, INTCON2
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control and status flags for the processor exceptions.
The INTCON2 register controls the external
interrupt request signal behavior and the use of
the alternate vector table.
© 2011 Microchip Technology Inc.
• INTTREG
The associated interrupt vector number and the
new CPU interrupt priority level are latched into
vector number (VECNUM) and interrupt
level (ILR) bit fields in the INTTREG register. The new interrupt priority level is the priority of
the pending interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
All interrupt sources can be user assigned to one of 7
priority levels, 1 through 7, via the IPCx registers. Each
interrupt source is associated with an interrupt vector,
as shown in Table 4-1. Levels 7 and 1 represent the
highest and lowest maskable priorities, respectively.
Note:
Assigning a priority level of ‘0’ to an interrupt source is equivalent to disabling that
interrupt.
If the NSTDIS bit (INTCON1) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is prevented even if the new interrupt is of higher priority than
the one currently being serviced.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupton-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program memory that corresponds to the interrupt. There are 63 different vectors within the IVT (refer to Table 4-1). These
vectors are contained in locations 0x000004 through
0x0000FE of program memory (refer to Table 4-1).
These locations contain 24-bit addresses and in order
to preserve robustness, an address error trap will take
place should the PC attempt to fetch any of these
words during normal execution. This prevents execution of random data as a result of accidentally decrementing a PC into vector space, accidentally mapping
a data space address into vector space or the PC rolling over to 0x000000 after reaching the end of implemented program memory space. Execution of a GOTO
instruction to this vector space will also generate an
address error trap.
DS70116J-page 35
dsPIC30F5011/5013
4.1
Interrupt Priority
The user-assignable interrupt priority (IP) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble within the IPCx register(s). Bit 3 of each nibble is not used and is read as a
‘0’. These bits define the priority level assigned to a
particular interrupt by the user.
Note:
The user-assignable priority levels start at
0 as the lowest priority and level 7 as the
highest priority.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural order priority is determined by the position of an
interrupt in the vector table, and only affects interrupt
operation when multiple interrupts with the same userassigned priority become pending at the same time.
Table 4-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC device and their associated
vector numbers.
Note 1: The natural order priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The natural order priority number is the
same as the INT number.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example, the PLVD (LowVoltage Detect) can be given a priority of 7. The INT0
(External Interrupt 0) may be assigned to priority level
1, thus giving it a very low effective priority.
DS70116J-page 36
TABLE 4-1:
INT
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39-40
41
42
43-53
INTERRUPT VECTOR TABLE
Vector
Number
Interrupt Source
Highest Natural Order Priority
8
INT0 – External Interrupt 0
9
IC1 – Input Capture 1
10
OC1 – Output Compare 1
11
T1 – Timer1
12
IC2 – Input Capture 2
13
OC2 – Output Compare 2
14
T2 – Timer2
15
T3 – Timer3
16
SPI1
17
U1RX – UART1 Receiver
18
U1TX – UART1 Transmitter
19
ADC – ADC Convert Done
20
NVM – NVM Write Complete
21
SI2C – I2C™ Slave Interrupt
22
MI2C – I2C Master Interrupt
23
Input Change Interrupt
24
INT1 – External Interrupt 1
25
IC7 – Input Capture 7
26
IC8 – Input Capture 8
27
OC3 – Output Compare 3
28
OC4 – Output Compare 4
29
T4 – Timer4
30
T5 – Timer5
31
INT2 – External Interrupt 2
32
U2RX – UART2 Receiver
33
U2TX – UART2 Transmitter
34
SPI2
35
C1 – Combined IRQ for CAN1
36
IC3 – Input Capture 3
37
IC4 – Input Capture 4
38
IC5 – Input Capture 5
39
IC6 – Input Capture 6
40
OC5 – Output Compare 5
41
OC6 – Output Compare 6
42
OC7 – Output Compare 7
43
OC8 – Output Compare 8
44
INT3 – External Interrupt 3
45
INT4 – External Interrupt 4
46
C2 – Combined IRQ for CAN2
47-48 Reserved
49
DCI – Codec Transfer Done
50
LVD – Low-Voltage Detect
51-61 Reserved
Lowest Natural Order Priority
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
4.2
Reset Sequence
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory location immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
4.2.1
4.3
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority as shown in Figure 4-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
RESET SOURCES
In addition to external Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
Traps
If the user does not intend to take corrective action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which implies that the IPL3 is always
set during processing of a trap.
If the user is not currently executing a trap, and sets the
IPL bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
4.3.1
TRAP SOURCES
The following traps are provided with increasing priority. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The Math Error trap executes under the following four
circumstances:
• If an attempt is made to divide by zero, the divide
operation will be aborted on a cycle boundary and
the trap taken
• If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A or
B causes an overflow from bit 31 and the accumulator guard bits are not utilized
• If enabled, a Math Error trap will be taken when
an arithmetic operation on either accumulator A or
B causes a catastrophic overflow from bit 39 and
all saturation is disabled
• If the shift amount specified in a shift instruction is
greater than the maximum allowed shift amount, a
trap will occur
© 2011 Microchip Technology Inc.
DS70116J-page 37
dsPIC30F5011/5013
Address Error Trap:
4.3.2
This trap is initiated when any of the following
circumstances occurs:
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 4-2 is implemented,
which may require the user to check if other traps are
pending, in order to completely correct the fault.
• A misaligned data word access is attempted
• A data fetch from an unimplemented data memory
location is attempted
• A data access of an unimplemented program
memory location is attempted
• An instruction fetch from vector space is
attempted
Note:
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
• Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal is
an unimplemented program memory address
• Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading a
value into the stack and executing a RETURN
instruction.
Stack Error Trap:
HARD AND SOFT TRAPS
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically Reset in a hard trap conflict
condition. The TRAPR Status bit (RCON) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 4-1:
This trap is initiated under the following conditions:
Oscillator Fail Trap:
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
Reset - GOTO Instruction
Reset - GOTO Address
Decreasing
Priority
• The Stack Pointer is loaded with a value that is
greater than the (user programmable) limit value
written into the SPLIM register (stack overflow)
• The Stack Pointer is loaded with a value that is
less than 0x0800 (simple stack underflow)
TRAP VECTORS
IVT
AIVT
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
0x000000
0x000002
0x000004
0x000014
0x00007E
0x000080
0x000082
0x000084
0x000094
Interrupt 1 Vector
—
—
—
Interrupt 52 Vector
Interrupt 53 Vector
DS70116J-page 38
0x0000FE
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
4.4
Interrupt Sequence
4.5
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
interrupt request (IRQ) is indicated by the flag bit being
equal to a ‘1’ in an IFSx register. The IRQ will cause an
interrupt to occur if the corresponding bit in the Interrupt
Enable (IECx) register is set. For the remainder of the
instruction cycle, the priorities of all pending interrupt
requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 4-2. The low byte of the
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this interrupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.
FIGURE 4-2:
Stack Grows Towards
Higher Address
0x0000 15
INTERRUPT STACK
FRAME
0
Alternate Vector Table
In program memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 4-1. Access to the alternate vector
table is provided by the ALTIVT bit in the INTCON2 register. If the ALTIVT bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a
means to switch between an application and a support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time.
If the AIVT is not required, the program memory allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
4.6
Fast Context Saving
A context saving option is available using shadow registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
PC
SRL IPL3 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instructions. Users must save the key registers in software
during a lower priority interrupt if the higher priority ISR
uses fast context saving.
4.7
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority, in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON) is always
clear when interrupts are being processed. It is set only during execution of
traps.
The RETFIE (return from interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.
© 2011 Microchip Technology Inc.
External Interrupt Requests
The interrupt controller supports up to five external
interrupt request signals, INT0-INT4. These inputs are
edge sensitive; they require a low-to-high or a high-tolow transition to generate an interrupt request. The
INTCON2 register has five bits, INT0EP-INT4EP, that
select the polarity of the edge detection circuitry.
4.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine (ISR) needed to process the interrupt request.
DS70116J-page 39
Bit 15
0086
0088
008C
008E
0090
0094
0096
0098
009A
009C
009E
00A0
00A2
00A4
00A6
IFS1
DS70116J-page 40
IFS2
IEC0
IEC1
IEC2
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC10
—
Legend:
Note 1:
—
—
00A8
INTTREG 00B0
C1IP
OC8IP
—
—
—
—
IC3IF
—
—
—
—
IC3IE
NVMIE
INT2IP
IC6IP
—
NVMIF
OC3IP
CNIP
ADIP
T31P
T1IP
—
IC4IE
SI2CIE
—
IC4IF
SI2CIF
—
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
C1IE
ADIE
—
C1IF
ADIF
—
—
Bit 11
—
OVBTE
Bit 9
DCIIF
U2TXIF
LVDIP
C2IP
OC7IP
IC5IP
SPI2IP
T5IP
—
U2RXIE
SPI1IE
—
U2RXIF
MI2CIP
IC8IP
—
SPI1IF
U1TXIP
T2IP
Bit 8
COVTE
OC1IP
DCIIE
U2TXIE
ILR
LVDIE
SPI2IE
U1TXIE U1RXIE
LVDIF
SPI2IF
U1TXIF U1RXIF
—
OVATE
Bit 10
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2IE
T3IE
—
INT2IF
T3IF
—
—
Bit 7
—
C2IE
T5IE
T2IE
C2IF
T5IF
T2IF
—
—
Bit 6
— = unimplemented, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
—
—
—
IC5IE
MI2CIE
—
IC5IF
MI2CIF
—
—
—
DISI
Bit 13
Bit 14
—
—
—
—
—
—
—
—
—
—
—
IC6IE
CNIE
—
IC6IF
CNIF
0082 ALTIVT
0084
INTCON2
IFS0
0080 NSTDIS
ADR
INTERRUPT CONTROLLER REGISTER MAP(1)
INTCON1
SFR
Name
TABLE 4-2:
Bit 4
INT3IE
OC4IE
IC2IE
INT3IF
OC4IF
IC2IF
INT4EP
MATHERR
DCIIP
INT41IP
OC6IP
IC4IP
U2TXIP
T4IP
IC7IP
SI2CIP
U1RXIP
OC2IP
IC1IP
INT4IE
T4IE
OC2IE
INT4IF
T4IF
OC2IF
—
—
Bit 5
Bit 1
—
OC7IE
IC8IE
OC1IE
OC7IF
IC8IF
OC1IF
INT2EP
—
INT3IP
OC5IP
IC3IP
U2RXIP
OC4IP
INT1IP
NVMIP
SPI1IP
IC2IP
INT0IP
OC6IE
IC7IE
IC1IE
OC6IF
IC7IF
IC1IF
INT1EP
STKERR OSCFAIL
Bit 2
VECNUM
—
—
—
—
—
—
—
—
—
—
—
OC8IE
OC3IE
T1IE
OC8IF
OC3IF
T1IF
INT3EP
ADDRERR
Bit 3
0000 0000 0000 0000
Reset State
—
OC5IE
INT1IE
INT0IE
OC5IF
INT1IF
INT0IF
0000 0000 0000 0000
0000 0100 0100 0000
0000 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0100 0100 0100 0100
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
INT0EP 0000 0000 0000 0000
—
Bit 0
dsPIC30F5011/5013
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
5.0
Note:
ADDRESS GENERATOR UNITS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
The dsPIC DSC core contains two independent
address generator units: the X AGU and Y AGU. The Y
AGU supports word sized data reads for the DSP MAC
class of instructions only. The dsPIC DSC AGUs
support three types of data addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
5.1.2
MCU INSTRUCTIONS
The three operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where:
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-reversed
addressing is only applicable to data space addresses.
5.1
5.1.1
Instruction Addressing Modes
The addressing modes in Table 5-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
Operand 1 is always a working register (i.e., the
addressing mode can only be register direct), which is
referred to as Wb.
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal. The result location can be
either a W register or an address location. The
following addressing modes are supported by MCU
instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
5-bit or 10-bit Literal
Note:
TABLE 5-1:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the File register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
© 2011 Microchip Technology Inc.
The sum of Wn and a literal forms the EA.
DS70116J-page 41
dsPIC30F5011/5013
5.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instructions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
5.1.4
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The 2 source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
Note:
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
5.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
5.2
Modulo Addressing
Modulo addressing is a method of providing an automated means to support circular data buffers using
hardware. The objective is to remove the need for software to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo addressing can operate in either data or program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for modulo addressing since these two registers are used as
the Stack Frame Pointer and Stack Pointer,
respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buffers that have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks are performed on both the lower and upper
address boundaries).
Register indirect with register offset
addressing is only available for W9 (in X
space) and W11 (in Y space).
DS70116J-page 42
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
5.2.1
START AND END ADDRESS
5.2.2
The modulo addressing scheme requires that a starting
and an ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
Note:
Y space modulo addressing EA calculations assume word sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words
(64 Kbytes).
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control register MODCON contains enable flags as well as
a W register field to specify the W address registers.
The XWM and YWM fields select which registers will
operate with modulo addressing. If XWM = 15, X
RAGU and X WAGU modulo addressing is disabled.
Similarly, if YWM = 15, Y AGU modulo addressing is
disabled.
The X Address Space Pointer W register (XWM), to
which modulo addressing is to be applied, is stored in
MODCON (see Table 3-3). Modulo addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM), to
which modulo addressing is to be applied, is stored in
MODCON. Modulo addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON.
FIGURE 5-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100,W0
W0,XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
MOV
#0x0000,W0
;W0 holds buffer fill value
MOV
#0x1110,W1
;point W1 to buffer
DO
AGAIN,#0x31
MOV
W0,[W1++]
AGAIN: INC W0,W0
0x1163
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations
;fill the next location
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
© 2011 Microchip Technology Inc.
DS70116J-page 43
dsPIC30F5011/5013
5.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo addressing can be applied to the Effective
Address (EA) calculation associated with any W register. It is important to realize that the address boundaries check for addresses less than, or greater than, the
upper (for incrementing buffers), and lower (for decrementing buffers) boundary addresses (not just equal
to). Address changes may, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
5.3
The modulo corrected effective address is
written back to the register only when PreModify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (e.g., [W7 + W2])
is used, modulo address correction is performed but the contents of the register
remain unchanged.
Bit-Reversed Addressing
Bit-reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by
the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
5.3.1
2.
3.
XB is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
BWM (W register selection) in the MODCON
register is any value other than ‘15’ (the stack
cannot be accessed using bit-reversed
addressing) and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 5-2:
All bit-reversed EA calculations assume
word sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, bit-reversed addressing will only be
executed for register indirect with pre-increment or
post-increment addressing and word sized data writes.
It will not function for any other addressing mode or for
byte sized data, and normal addresses will be generated instead. When bit-reversed addressing is active,
the W address pointer will always be added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode will be ignored.
In addition, as word sized data is a requirement, the
LSb of the EA is ignored (and always clear).
Note:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-reversed addressing is enabled when:
1.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
Modulo addressing and bit-reversed
addressing should not be enabled
together. In the event that the user
attempts to do this, bit-reversed addressing will assume priority when active for the
X WAGU, and X WAGU modulo addressing will be disabled. However, modulo
addressing will continue to function in the X
RAGU.
If bit-reversed addressing has already been enabled by
setting the BREN (XBREV) bit, then a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9
b8
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b1
b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
DS70116J-page 44
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 5-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
TABLE 5-3:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Buffer Size (Words)
XB Bit-Reversed Address Modifier Value
2048
0x0400
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
8
0x0004
4
0x0002
2
0x0001
© 2011 Microchip Technology Inc.
DS70116J-page 45
dsPIC30F5011/5013
NOTES:
DS70116J-page 46
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
6.0
Note:
FLASH PROGRAM MEMORY
6.2
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.
With RTSP, the user may erase program memory, 32
instructions (96 bytes) at a time and can write program
memory data, 32 instructions (96 bytes) at a time.
6.3
The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are
two methods by which the user can program this
memory:
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
In-Circuit Serial Programming
(ICSP)
A 24-bit program memory address is formed using
bits of the TBLPAG register and the effective
address (EA) from a W register specified in the table
instruction, as shown in Figure 6-1.
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices, and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 6-1:
Table Instruction Operation
Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
• Run-Time Self-Programming (RTSP)
• In-Circuit Serial Programming (ICSP)
6.1
Run-Time Self-Programming
(RTSP)
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
© 2011 Microchip Technology Inc.
1/0
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
DS70116J-page 47
dsPIC30F5011/5013
6.4
RTSP Operation
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program four
instructions at one time. RTSP may be used to program
multiple program memory panels, but the table pointer
must be changed at each panel boundary.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches: instruction 0, instruction 1,
etc. The instruction words loaded must always be from
a group of 32 boundary.
The basic sequence for RTSP programming is to set up
a table pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and four TBLWTH instructions are required to
load the 32 instructions. If multiple panel programming
is required, the table pointer needs to be changed and
the next set of multiple write latches written.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written. A programming cycle is required for
programming each row.
The Flash Program Memory is readable, writable and
erasable during normal operation over the entire VDD
range.
6.5
The four SFRs used to read and write the program
Flash memory are:
•
•
•
•
NVMCON
NVMADR
NVMADRU
NVMKEY
6.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
the start of the programming cycle.
6.5.2
NVMADR REGISTER
The NVMADR register is used to hold the lower two
bytes of the effective address. The NVMADR register
captures the EA of the last table instruction that
has been executed and selects the row to write.
6.5.3
NVMADRU REGISTER
The NVMADRU register is used to hold the upper byte
of the effective address. The NVMADRU register captures the EA of the last table instruction that
has been executed.
6.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
“Programming Operations” for further details.
Note:
DS70116J-page 48
Control Registers
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
6.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
6.6.1
4.
5.
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase or program one row of program
Flash memory at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a) Set up NVMCON register for multi-word,
program Flash, erase and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 6-1:
6.
Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a) Set up NVMCON register for multi-word,
program Flash, program, and set WREN
bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. This will begin program
cycle.
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
6.6.2
ERASING A ROW OF PROGRAM
MEMORY
Example 6-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word
; program memory selected, and writes enabled
MOV
#0x4041,W0
;
MOV
W0,NVMCON
;
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR),W0
;
MOV
W0,NVMADRU
;
MOV
#tbloffset(PROG_ADDR),W0
;
MOV
W0, NVMADR
;
DISI
#5
;
;
MOV
#0x55,W0
MOV
W0,NVMKEY
;
MOV
#0xAA,W1
;
MOV
W1,NVMKEY
;
BSET
NVMCON,#WR
;
NOP
;
NOP
;
© 2011 Microchip Technology Inc.
write
Init NVMCON SFR
Initialize PM Page Boundary SFR
Intialize in-page EA[15:0] pointer
Initialize NVMADR SFR
Block all interrupts with priority VDD) .......................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................................................................... ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (2) ..............................................................................................................200 mA
Note 1:
2:
Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
Maximum allowable current is a function of device maximum power dissipation. See Table 23-2 for PDMAX.
†NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
All peripheral electrical characteristics are specified. For exact peripherals available on specific devices,
please refer to the dsPIC30F5011/5013 Controller Family table. See Table 1
© 2011 Microchip Technology Inc.
DS70116J-page 163
dsPIC30F5011/5013
23.1
DC Characteristics
TABLE 23-1:
OPERATING MIPS VS. VOLTAGE
VDD Range
Temp Range
4.75-5.5V
-40°C to 85°C
4.75-5.5V
-40°C to 125°C
3.0-3.6V
-40°C to 85°C
3.0-3.6V
-40°C to 125°C
2.5-3.0V
-40°C to 85°C
TABLE 23-2:
Max MIPS
dsPIC30F501X-30I
dsPIC30F501X-20I
dsPIC30F501X-20E
30
20
—
—
—
20
15
10
—
—
—
10
7.5
7.5
—
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+150
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+150
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
dsPIC30F501x-30I
dsPIC30F501x-20I
dsPIC30F501x-20E
Power Dissipation:
Internal chip power dissipation:
P INT = V DD × ⎛I D D –∑I OH⎞
⎝
⎠
I/O Pin power dissipation:
P I/O = ∑( {V DD – V O H }× I OH ) + ∑( V OL × I O L )
Maximum Allowed Power Dissipation
TABLE 23-3:
PINT + PI/O
W
PDMAX
(TJ - TA) / θ JA
W
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Package Thermal Resistance, 64-pin TQFP (10x10x1mm)
Package Thermal Resistance, 80-pin TQFP (12x12x1mm)
Note 1:
PD
Symbol
Typ
Max
Unit
Notes
θJA
θJA
39
—
°C/W
1
39
—
°C/W
1
Junction to ambient thermal resistance, Theta-ja (θ JA) numbers are achieved by package simulations.
DS70116J-page 164
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
2.5
—
5.5
V
Industrial temperature
3.0
—
5.5
V
Extended temperature
Conditions
Operating Voltage(2)
DC10
VDD
Supply Voltage
DC11
VDD
Supply Voltage
(3)
DC12
VDR
RAM Data Retention Voltage
1.75
—
—
V
DC16
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
VSS
—
V
DC17
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
Note 1:
2:
3:
V/ms 0-5V in 0.1 sec
0-3V in 60 ms
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
This is the limit to which VDD can be lowered without losing RAM data.
TABLE 23-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC30a
7.3
11
mA
25°C
DC30b
7.5
11.2
mA
85°C
DC30c
7.6
11.4
mA
125°C
DC30e
12.9
19.2
mA
25°C
DC30f
12.8
19.1
mA
85°C
DC30g
12.8
19.1
mA
125°C
DC31a
1.9
2.8
mA
25°C
DC31b
2.0
3
mA
85°C
DC31c
2.0
3
mA
125°C
DC31e
4.1
6.1
mA
25°C
DC31f
4.0
6
mA
85°C
DC31g
3.8
5.7
mA
125°C
Note 1:
2:
3.3V
FRC (~2 MIPS)
5V
3.3V
LPRC (~512 kHz)
5V
Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory
are operational. No peripheral modules are operating.
© 2011 Microchip Technology Inc.
DS70116J-page 165
dsPIC30F5011/5013
TABLE 23-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC23a
13.5
20
mA
25°C
DC23b
14
21
mA
85°C
DC23c
15
22.5
mA
125°C
DC23e
23
34.5
mA
25°C
DC23f
23.5
35
mA
85°C
DC23g
24
36
mA
125°C
DC24a
32
48
mA
25°C
DC24b
32.5
49
mA
85°C
DC24c
33
49.5
mA
125°C
DC24e
53.5
80
mA
25°C
DC24f
54
81
mA
85°C
DC24g
54
81
mA
125°C
DC27d
101
152
mA
25°C
DC27e
100
150
mA
85°C
DC27f
100
150
mA
125°C
DC29a
145
217
mA
25°C
DC29b
144
216
mA
85°C
Note 1:
2:
3.3V
4 MIPS
5V
3.3V
10 MIPS
5V
5V
20 MIPS
5V
30 MIPS
Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as Inputs and pulled to VDD.
MCLR = VDD, WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory
are operational. No peripheral modules are operating.
DS70116J-page 166
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1,2)
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC50a
4.8
7.2
mA
25°C
DC50b
4.9
7.3
mA
85°C
DC50c
5.0
7.5
mA
125°C
DC50e
8.9
13.3
mA
25°C
DC50f
8.8
13.2
mA
85°C
DC50g
8.8
13.2
mA
125°C
DC51a
1.6
2.4
mA
25°C
DC51b
1.62
2.43
mA
85°C
DC51c
1.62
2.43
mA
125°C
DC51e
3.65
5.47
mA
25°C
DC51f
3.4
5.1
mA
85°C
DC51g
3.3
4.95
mA
125°C
DC43a
8.5
12.75
mA
25°C
DC43b
8.7
13
mA
85°C
DC43c
9.6
14.4
mA
125°C
DC43e
15.2
22.8
mA
25°C
DC43f
15.2
22.8
mA
85°C
DC43g
15.2
22.8
mA
125°C
DC44a
19.9
29.8
mA
25°C
DC44b
20.2
30.3
mA
85°C
DC44c
20.5
30.7
mA
125°C
DC44e
33.4
50
mA
25°C
DC44f
33.7
50.5
mA
85°C
DC44g
34
51
mA
125°C
DC47a
37.4
56
mA
25°C
DC47b
38
57
mA
85°C
DC47d
62.3
93.4
mA
25°C
DC47e
62.9
94.3
mA
85°C
DC47f
63.5
95.2
mA
125°C
DC49a
90.8
136
mA
25°C
DC49b
91
137
mA
85°C
Note 1:
2:
3.3V
FRC (~2MIPS)
5V
3.3V
LPRC (~512 kHz)
5V
3.3V
4 MIPS EC mode, 4X PLL
5V
3.3V
10 MIPS EC mode, 4X PLL
5V
3.3V
20 MIPS EC mode, 8X PLL
5V
5V
30 MIPS EC mode,16X PLL
Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Base IIDLE current is measured with core off, clock on and all modules turned off.
© 2011 Microchip Technology Inc.
DS70116J-page 167
dsPIC30F5011/5013
TABLE 23-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
25
μA
Conditions
Power Down Current (IPD)(2)
DC60a
5
25°C
DC60b
8
40
μA
85°C
DC60c
14
70
μA
125°C
DC60e
8
40
μA
25°C
DC60f
12
55
μA
85°C
DC60g
20
100
μA
125°C
DC61a
7.8
12
μA
25°C
DC61b
7.9
12
μA
85°C
DC61c
8.4
13
μA
125°C
DC61e
15.4
23.1
μA
25°C
DC61f
14.7
22
μA
85°C
DC61g
14.1
21.1
μA
125°C
DC62a
3.8
6
μA
25°C
DC62b
—
—
μA
85°C
DC62c
—
—
μA
125°C
DC62e
5.5
10
μA
25°C
DC62f
—
—
μA
85°C
DC62g
—
—
μA
125°C
DC63a
31.5
47.2
μA
25°C
DC63b
34.4
51.5
μA
85°C
DC63c
36.5
55
μA
125°C
DC63e
36.5
54.7
μA
25°C
DC63f
39.1
58.7
μA
85°C
DC63g
40.5
61
μA
125°C
DC66a
19.6
29.4
μA
25°C
DC66b
21.5
32.3
μA
85°C
DC66c
23
34.5
μA
125°C
DC66e
24
36
μA
25°C
DC66f
25.5
38.3
μA
85°C
26.2
39
μA
125°C
DC66g
Note 1:
2:
3:
3.3V
Base Power Down Current(3)
5V
3.3V
Watchdog Timer Current: ΔIWDT(3)
5V
3.3V
Timer 1 w/32 kHz Crystal: ΔITI32(3)
5V
3.3V
BOR On: ΔIBOR(3)
5V
3.3V
Low-Voltage Detect: ΔILVD(3)
5V
Data in the Typical column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled high. LVD, BOR, WDT, etc. are all switched off.
The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
DS70116J-page 168
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage(2)
DI10
I/O pins:
with Schmitt Trigger buffer
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
OSC1 (in XT, HS and LP modes)
VSS
—
0.2 VDD
V
DI17
OSC1 (in RC mode)(3)
VSS
—
0.3 VDD
V
DI18
SDA, SCL
VSS
—
0.3 VDD
V
SM bus disabled
DI19
SDA, SCL
VSS
—
0.8
V
SM bus enabled
VIH
Input High Voltage(2)
DI20
I/O pins:
with Schmitt Trigger buffer
0.8 VDD
—
VDD
V
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSC1 (in XT, HS and LP modes) 0.7 VDD
—
VDD
V
DI27
OSC1 (in RC mode)(3)
0.9 VDD
—
VDD
V
DI28
SDA, SCL
0.7 VDD
—
VDD
V
SM bus disabled
SDA, SCL
2.1
—
VDD
V
SM bus enabled
50
250
400
μA
VDD = 5V, VPIN = VSS
DI29
ICNPU
CNXX Pull-up Current(2)
DI30
IIL
Input Leakage
Current(2)(4)(5)
DI50
I/O ports
—
0.01
±1
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI51
Analog input pins
—
0.50
—
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI55
MCLR
—
0.05
±5
μA
VSS ≤VPIN ≤VDD
DI56
OSC1
—
0.05
±5
μA
VSS ≤VPIN ≤VDD, XT, HS
and LP Osc mode
Note 1:
2:
3:
4:
5:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
In RC oscillator configuration, the OSC1/CLKl pin is a Schmitt Trigger input. It is not recommended that
the dsPIC30F device be driven with an external clock while in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
© 2011 Microchip Technology Inc.
DS70116J-page 169
dsPIC30F5011/5013
TABLE 23-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
—
0.6
V
Conditions
Output Low Voltage(2)
VOL
DO10
I/O ports
—
IOL = 8.5 mA, VDD = 5V
—
—
0.15
V
IOL = 2.0 mA, VDD = 3V
DO16
OSC2/CLKOUT
—
—
0.6
V
IOL = 1.6 mA, VDD = 5V
(RC or EC Osc mode)
—
—
0.72
V
IOL = 2.0 mA, VDD = 3V
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 5V
VDD – 0.2
—
—
V
IOH = -2.0 mA, VDD = 3V
OSC2/CLKOUT
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 5V
(RC or EC Osc mode)
VDD – 0.1
—
—
V
IOH = -2.0 mA, VDD = 3V
Output High Voltage(2)
VOH
DO20
I/O ports
DO26
Capacitive Loading Specs
on Output Pins(2)
DO50
COSC2
OSC2/SOSC2 pin
—
—
15
pF
In XTL, XT, HS and LP modes
when external clock is used to
drive OSC1.
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
RC or EC Osc mode
DO58
CB
SCL, SDA
—
—
400
pF
In I2C mode
Note 1:
2:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
FIGURE 23-1:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
LV10
LVDIF
(LVDIF set by hardware)
DS70116J-page 170
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-10: ELECTRICAL CHARACTERISTICS: LVDL
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
No.
LV10
Characteristic(1)
Min
Typ
Max
Units
LVDL Voltage on VDD transition LVDL = 0000(2)
high to low
—
—
—
V
LVDL = 0001(2)
—
—
—
V
LVDL = 0010(2)
—
—
—
V
Symbol
VPLVD
LVDL = 0011
LV15
Note 1:
2:
VLVDIN
External LVD input pin
threshold voltage
(2)
—
—
—
V
LVDL = 0100
2.50
—
2.65
V
LVDL = 0101
2.70
—
2.86
V
LVDL = 0110
2.80
—
2.97
V
LVDL = 0111
3.00
—
3.18
V
LVDL = 1000
3.30
—
3.50
V
LVDL = 1001
3.50
—
3.71
V
LVDL = 1010
3.60
—
3.82
V
LVDL = 1011
3.80
—
4.03
V
LVDL = 1100
4.00
—
4.24
V
LVDL = 1101
4.20
—
4.45
V
LVDL = 1110
4.50
—
4.77
V
LVDL = 1111
—
—
—
V
Conditions
These parameters are characterized but not tested in manufacturing.
These values not in usable operating range.
FIGURE 23-2:
BROWN-OUT RESET CHARACTERISTICS
VDD
BO10
(Device in Brown-out Reset)
BO15
(Device not in Brown-out Reset)
RESET (due to BOR)
Power-Up Time-out
© 2011 Microchip Technology Inc.
DS70116J-page 171
dsPIC30F5011/5013
TABLE 23-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
No.
BO10
Symbol
VBOR
Characteristic
BOR Voltage(2) on
VDD transition high to
low
BORV = 11(3)
Min
Typ(1)
Max
Units
—
—
—
V
BORV = 10
2.60
—
2.71
V
BORV = 01
4.10
—
4.40
V
BORV = 00
4.58
—
4.73
V
—
5
—
mV
Conditions
Not in operating
range
BO15
VBHYS
Note 1:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
11 values not in usable operating range.
2:
3:
TABLE 23-12: DC CHARACTERISTICS: PROGRAM AND EEPROM
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Data EEPROM Memory(2)
-40° C ≤TA ≤+85°C
D120
ED
Byte Endurance
100K
1M
—
E/W
D121
VDRW
VDD for Read/Write
VMIN
—
5.5
V
D122
TDEW
Erase/Write Cycle Time
0.8
2
2.6
ms
D123
TRETD
Characteristic Retention
40
100
—
Year
Provided no other specifications
are violated
D124
IDEW
IDD During Programming
—
10
30
mA
Row Erase
-40° C ≤TA ≤+85°C
Using EECON to read/write
VMIN = Minimum operating
voltage
RTSP
Program FLASH Memory(2)
D130
EP
Cell Endurance
10K
100K
—
E/W
D131
VPR
VDD for Read
VMIN
—
5.5
V
D132
VEB
VDD for Bulk Erase
4.5
—
5.5
V
D133
VPEW
VDD for Erase/Write
3.0
—
5.5
V
D134
TPEW
Erase/Write Cycle Time
0.8
2
2.6
ms
D135
TRETD
Characteristic Retention
40
100
—
Year
Provided no other specifications
are violated
D137
IPEW
IDD During Programming
—
10
30
mA
Row Erase
D138
IEB
IDD During Programming
—
10
30
mA
Bulk Erase
Note 1:
2:
VMIN = Minimum operating
voltage
RTSP
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
These parameters are characterized but not tested in manufacturing.
DS70116J-page 172
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
23.2
AC Characteristics and Timing Parameters
The information contained in this section defines dsPIC30F AC characteristics and timing parameters.
TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Operating voltage VDD range as described in Table 23-1.
AC CHARACTERISTICS
FIGURE 23-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464 Ω
CL = 50 pF for all pins except OSC2
VSS
FIGURE 23-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKOUT
OS40
© 2011 Microchip Technology Inc.
OS41
DS70116J-page 173
dsPIC30F5011/5013
TABLE 23-14: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
OS10
FOSC
Characteristic
Min
Typ(1)
Max
Units
External CLKIN Frequency(2)
(External clocks allowed only
in EC mode)
DC
4
4
4
—
—
—
—
40
10
10
7.5
MHz
MHz
MHz
MHz
EC
EC with 4x PLL
EC with 8x PLL
EC with 16x PLL
Oscillator Frequency(2)
DC
0.4
4
4
4
4
10
—
—
—
—
—
—
—
—
32.768
4
4
10
10
10
7.5
25
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
RC
XTL
XT
XT with 4x PLL
XT with 8x PLL
XT with 16x PLL
HS
LP
Conditions
OS20
TOSC
TOSC = 1/FOSC
—
—
—
—
See parameter OS10
for FOSC value
OS25
TCY
Instruction Cycle Time(2,3)
33
—
DC
ns
See Table 23-17
(2)
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
.45 x
TOSC
—
—
ns
EC
OS31
TosR,
TosF
External Clock(2) in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKOUT Rise Time(2,4)
—
—
—
ns
See parameter DO31
—
—
—
ns
See parameter DO32
OS41
TckF
Note 1:
2:
3:
4:
CLKOUT Fall Time
(2,4)
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
These parameters are characterized but not tested in manufacturing.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC or ERC modes. The CLKOUT signal is measured on the OSC2 pin.
CLKOUT is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
DS70116J-page 174
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.5 TO 5.5 V)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
OS50
Characteristic(1)
Symbol
FPLLI
PLL Input Frequency Range(2)
(2)
OS51
FSYS
On-Chip PLL Output
OS52
TLOC
PLL Start-up Time (Lock Time)
Note 1:
2:
Min
Typ(2)
Max
4
—
10
MHz EC, XT, FRC modes with PLL
16
—
120
MHz EC, XT, FRC modes with PLL
—
20
50
Units
Conditions
μs
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
TABLE 23-16: PLL JITTER
AC CHARACTERISTICS
Param
No.
OS61
Characteristic
x4 PLL
x8 PLL
x16 PLL
Note 1:
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ(1)
Max
Units
Conditions
—
0.251
0.413
%
-40°C ≤TA ≤+85°C
VDD = 3.0 to 3.6V
—
0.251
0.413
%
-40°C ≤TA ≤+125°C
VDD = 3.0 to 3.6V
—
0.256
0.47
%
-40°C ≤TA ≤+85°C
VDD = 4.5 to 5.5V
—
0.256
0.47
%
-40°C ≤TA ≤+125°C
VDD = 4.5 to 5.5V
—
0.355
0.584
%
-40°C ≤TA ≤+85°C
VDD = 3.0 to 3.6V
—
0.355
0.584
%
-40°C ≤TA ≤+125°C
VDD = 3.0 to 3.6V
—
0.362
0.664
%
-40°C ≤TA ≤+85°C
VDD = 4.5 to 5.5V
—
0.362
0.664
%
-40°C ≤TA ≤+125°C
VDD = 4.5 to 5.5V
VDD = 3.0 to 3.6V
—
0.67
0.92
%
-40°C ≤TA ≤+85°C
—
0.632
0.956
%
-40°C ≤TA ≤+85°C
VDD = 4.5 to 5.5V
—
0.632
0.956
%
-40°C ≤TA ≤+125°C
VDD = 4.5 to 5.5V
These parameters are characterized but not tested in manufacturing.
© 2011 Microchip Technology Inc.
DS70116J-page 175
dsPIC30F5011/5013
TABLE 23-17: INTERNAL CLOCK TIMING EXAMPLES
Clock
Oscillator Mode
FOSC
(MHz)(1)
TCY
(μsec)(2)
MIPS(3)
w/o PLL
EC
0.200
20.0
0.05
—
—
—
4
1.0
1.0
4.0
8.0
16.0
XT
Note 1:
2:
3:
MIPS(3)
w PLL x4
MIPS(3)
w PLL x8
MIPS(3)
w PLL x16
10
0.4
2.5
10.0
20.0
—
25
0.16
6.25
—
—
—
4
1.0
1.0
4.0
8.0
16.0
10
0.4
2.5
10.0
20.0
—
Assumption: Oscillator Postscaler is divide by 1.
Instruction Execution Cycle Time: TCY = 1 / MIPS.
Instruction Execution Frequency: MIPS = (FOSC * PLLx) / 4 [since there are 4 Q clocks per instruction cycle].
TABLE 23-18: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Freq. = 7.37 MHz(1)
OS63
Note 1:
FRC
—
—
±2.00
%
-40°C ≤TA ≤+85°C
VDD = 3.0-5.5V
—
—
±5.00
%
-40°C ≤TA ≤+125°C
VDD = 3.0-5.5V
Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift
percentages.
TABLE 23-19:
AC CHARACTERISTICS: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ
Max
Units
Conditions
OS65A
-50
—
+50
%
VDD = 5.0V, ±10%
OS65B
-60
—
+60
%
VDD = 3.3V, ±10%
-70
—
+70
%
VDD = 2.5V
LPRC @ Freq. = 512 kHz(1)
OS65C
Note 1:
Change of LPRC frequency as VDD changes.
DS70116J-page 176
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 23-5:
CLKOUT AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-20: CLKOUT AND I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)(2)(3)
Symbol
Typ(4)
Max
Units
—
7
20
ns
DO31
TIOR
DO32
TIOF
Port output fall time
—
7
20
ns
DI35
TINP
INTx pin high or low time (output)
20
—
—
ns
TRBP
CNx high or low time (input)
2 TCY
—
—
ns
DI40
Note 1:
2:
3:
4:
Port output rise time
Min
Conditions
These parameters are asynchronous events not related to any internal clock edges.
Measurements are taken in RC mode and EC mode where CLKOUT output is 4 x TOSC.
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
© 2011 Microchip Technology Inc.
DS70116J-page 177
dsPIC30F5011/5013
FIGURE 23-6:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
PWRT
Time-out
OSC
Time-out
SY11
SY30
Internal
RESET
Watchdog
Timer
RESET
SY13
SY20
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 23-3 for load conditions.
DS70116J-page 178
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SY10
TmcL
MCLR Pulse Width (low)
2
—
—
μs
-40°C to +85°C
SY11
TPWRT
Power-up Timer Period
2
8
32
4
16
64
6
24
96
ms
-40°C to +85°C, VDD =
5V
User programmable
SY12
TPOR
Power-on Reset Delay
3
10
30
μs
-40°C to +85°C
SY13
TIOZ
I/O High-impedance from MCLR
Low or Watchdog Timer Reset
—
0.8
1.0
μs
SY20
TWDT1
TWDT2
TWDT3
Watchdog Timer Time-out Period
(No Prescaler)
0.6
0.8
1.0
2.0
2.0
2.0
3.4
3.2
3.0
ms
ms
ms
VDD = 2.5V
VDD = 3.3V, ±10%
VDD = 5V, ±10%
SY25
TBOR
Brown-out Reset Pulse Width(3)
100
—
—
μs
VDD ≤VBOR (D034)
SY30
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
SY35
TFSCM
Fail-Safe Clock Monitor Delay
—
500
900
μs
-40°C to +85°C
Note 1:
2:
3:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
Refer to Figure 23-2 and Table 23-11 for BOR.
© 2011 Microchip Technology Inc.
DS70116J-page 179
dsPIC30F5011/5013
FIGURE 23-7:
BAND GAP START-UP TIME CHARACTERISTICS
VBGAP
0V
Enable Band Gap
(see Note)
Band Gap
Stable
SY40
Note: Set LVDEN bit (RCON) or FBORPORset.
TABLE 23-22: BAND GAP START-UP TIME REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SY40
Note 1:
2:
Symbol
TBGAP
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Characteristic(1)
Min
Typ(2)
Max
Units
Band Gap Start-up Time
—
40
65
µs
Conditions
Defined as the time between the
instant that the band gap is enabled
and the moment that the band gap
reference voltage is stable.
RCON Status bit
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated.
DS70116J-page 180
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 23-8:
TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRX
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-23:
TYPE A TIMER (TIMER1) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristic
TxCK High Time
TxCK Low Time
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
ns
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
ns
TCY + 10
—
—
ns
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
—
—
—
Asynchronous
20
—
—
ns
DC
—
50
kHz
0.5 TCY
—
1.5
TCY
—
TxCK Input Period Synchronous,
no prescaler
OS60
Ft1
TA20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
Note:
SOSC1/T1CK oscillator input
frequency range (oscillator enabled
by setting bit TCS (T1CON, bit 1))
Must also meet
parameter TA15
N = prescale
value
(1, 8, 64, 256)
Timer1 is a Type A.
© 2011 Microchip Technology Inc.
DS70116J-page 181
dsPIC30F5011/5013
TABLE 23-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
TB10
TB11
TB15
Symbol
TtxH
TtxL
TtxP
Characteristic
TxCK High Time
TxCK Low Time
Min
Typ
Max
Units
Conditions
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
ns
Synchronous,
no prescaler
0.5 TCY + 20
—
—
ns
Synchronous,
with prescaler
10
—
—
ns
TCY + 10
—
—
ns
—
1.5 TCY
—
TxCK Input Period Synchronous,
no prescaler
Synchronous,
with prescaler
TB20
TCKEXTMRL
Note:
Delay from External TxCK Clock
Edge to Timer Increment
Greater of:
20 ns or
(TCY + 40)/N
0.5 TCY
Must also meet
parameter TB15
N = prescale
value
(1, 8, 64, 256)
Timer2 and Timer4 are Type B.
TABLE 23-25: TYPE C TIMER (TIMER3 AND TIMER5) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High Time
Synchronous
0.5 TCY + 20
—
—
ns
Must also meet
parameter TC15
TC11
TtxL
TxCK Low Time
Synchronous
0.5 TCY + 20
—
—
ns
Must also meet
parameter TC15
TC15
TtxP
TxCK Input Period Synchronous,
no prescaler
TCY + 10
—
—
ns
N = prescale
value
(1, 8, 64, 256)
—
1.5
TCY
—
Synchronous,
with prescaler
TC20
TCKEXTMRL
Note:
Delay from External TxCK Clock
Edge to Timer Increment
Greater of:
20 ns or
(TCY + 40)/N
0.5 TCY
Timer3 and Timer5 are Type C.
DS70116J-page 182
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 23-9:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICX
IC10
IC11
IC15
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-26: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
IC10
TccL
ICx Input Low Time
No Prescaler
IC11
TccH
ICx Input High Time
No Prescaler
IC15
TccP
ICx Input Period
Characteristic(1)
With Prescaler
With Prescaler
Note 1:
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(2 TCY + 40)/N
—
ns
Conditions
N = prescale
value (1, 4, 16)
These parameters are characterized but not tested in manufacturing.
© 2011 Microchip Technology Inc.
DS70116J-page 183
dsPIC30F5011/5013
FIGURE 23-10:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Min
Typ(2)
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70116J-page 184
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 23-11:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
TABLE 23-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
OC15
TFD
Fault Input to PWM I/O
Change
—
—
50
ns
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
Note 1:
2:
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
© 2011 Microchip Technology Inc.
DS70116J-page 185
dsPIC30F5011/5013
FIGURE 23-12:
DCI MODULE (MULTICHANNEL, I2S MODES) TIMING CHARACTERISTICS
CSCK
(SCKE = 0)
CS11
CS10
CS21
CS20
CS20
CS21
CSCK
(SCKE = 1)
COFS
CS55 CS56
CS35
CS51
CSDO
HIGH-Z
70
CS50
LSb
MSb
CS30
CSDI
MSb IN
HIGH-Z
CS31
LSb IN
CS40 CS41
Note: Refer to Figure 23-3 for load conditions.
DS70116J-page 186
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-29: DCI MODULE (MULTICHANNEL, I2S MODES) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
CS10
Symbol
TcSCKL
Characteristic(1)
Min
Typ(2)
Max
Units
TCY / 2 +
20
—
—
ns
30
—
—
ns
TCY / 2 +
20
—
—
ns
CSCK Output High Time(3)
(CSCK pin is an output)
30
—
—
ns
CSCK Input Low Time
(CSCK pin is an input)
CSCK Output Low Time(3)
(CSCK pin is an output)
CS11
TcSCKH
CSCK Input High Time
(CSCK pin is an input)
CS20
TcSCKF
CSCK Output Fall Time(4)
(CSCK pin is an output)
—
10
25
ns
CS21
TcSCKR
CSCK Output Rise Time(4)
(CSCK pin is an output)
—
10
25
ns
CS30
TcSDOF
CSDO Data Output Fall Time(4)
—
10
25
ns
Time(4)
Conditions
CS31
TcSDOR
CSDO Data Output Rise
—
10
25
ns
CS35
TDV
Clock edge to CSDO data valid
—
—
10
ns
CS36
TDIV
Clock edge to CSDO tri-stated
10
—
20
ns
CS40
TCSDI
Setup time of CSDI data input to
CSCK edge (CSCK pin is input
or output)
20
—
—
ns
CS41
THCSDI
Hold time of CSDI data input to
CSCK edge (CSCK pin is input
or output)
20
—
—
ns
CS50
TcoFSF
COFS Fall Time
(COFS pin is output)
—
10
25
ns
Note 1
CS51
TcoFSR
COFS Rise Time
(COFS pin is output)
—
10
25
ns
Note 1
CS55
TscoFS
Setup time of COFS data input to
CSCK edge (COFS pin is input)
20
—
—
ns
CS56
THCOFS
Hold time of COFS data input to
CSCK edge (COFS pin is input)
20
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all DCI pins.
© 2011 Microchip Technology Inc.
DS70116J-page 187
dsPIC30F5011/5013
FIGURE 23-13:
DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS
BIT_CLK
(CSCK)
CS61
CS60
CS62
CS21
CS20
CS71
CS70
CS72
SYNC
(COFS)
CS75
CS76
CS80
SDO
(CSDO)
MSb
LSb
LSb
CS76
CS75
MSb IN
SDI
(CSDI)
CS65 CS66
TABLE 23-30: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)(2)
Min
Typ(3)
Max
Units
Conditions
CS60
TBCLKL
BIT_CLK Low Time
36
40.7
45
ns
CS61
TBCLKH
BIT_CLK High Time
36
40.7
45
ns
CS62
TBCLK
BIT_CLK Period
—
81.4
—
ns
CS65
TSACL
Input Setup Time to
Falling Edge of BIT_CLK
—
—
10
ns
CS66
THACL
Input Hold Time from
Falling Edge of BIT_CLK
—
—
10
ns
CS70
TSYNCLO
SYNC Data Output Low Time
—
19.5
—
μs
Note 1
CS71
TSYNCHI
SYNC Data Output High Time
—
1.3
—
μs
Note 1
CS72
TSYNC
SYNC Data Output Period
—
20.8
—
μs
Note 1
Bit clock is input
CS75
TRACL
Rise Time, SYNC, SDATA_OUT
—
10
25
ns
CLOAD = 50 pF, VDD = 5V
CS76
TFACL
Fall Time, SYNC, SDATA_OUT
—
10
25
ns
CLOAD = 50 pF, VDD = 5V
CS77
TRACL
Rise Time, SYNC, SDATA_OUT
—
10
25
ns
CLOAD = 50 pF, VDD = 3V
CS78
TFACL
Fall Time, SYNC, SDATA_OUT
—
10
25
ns
CLOAD = 50 pF, VDD = 3V
CS80
TOVDACL
Output valid delay from rising
edge of BIT_CLK
—
—
15
ns
Note 1:
2:
3:
These parameters are characterized but not tested in manufacturing.
These values assume BIT_CLK frequency is 12.288 MHz.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70116J-page 188
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 23-14:
SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
BIT14 - - - - - -1
SP31
SDIx
MSb IN
LSb
SP30
LSb IN
BIT14 - - - -1
SP40 SP41
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-31: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscL
SCKX Output Low Time(3)
TCY / 2
—
—
ns
SP11
TscH
SCKX Output High Time(3)
TCY/2
—
—
ns
SP20
TscF
SCKX Output Fall Time(4
—
—
—
ns
See parameter
DO32
SP21
TscR
SCKX Output Rise Time(4)
—
—
—
ns
See parameter
DO31
SP30
TdoF
SDOX Data Output Fall Time(4)
—
—
—
ns
See parameter
DO32
SP31
TdoR
SDOX Data Output Rise
Time(4)
—
—
—
ns
See parameter
DO31
SP35
TscH2doV,
TscL2doV
SDOX Data Output Valid after
SCKX Edge
—
—
30
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIX Data Input
to SCKX Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIX Data Input
to SCKX Edge
20
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
© 2011 Microchip Technology Inc.
DS70116J-page 189
dsPIC30F5011/5013
FIGURE 23-15:
SPI MODULE MASTER MODE (CKE =1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
BIT14 - - - - - -1
MSb
SDOX
SP40
SDIX
LSb
SP30,SP31
MSb IN
BIT14 - - - -1
LSb IN
SP41
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-32: SPI MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscL
SCKX output low time(3)
TCY / 2
—
—
ns
SP11
TscH
SCKX output high time(3)
TCY / 2
—
—
ns
—
—
—
ns
See Parameter
DO32
time(4)
SP20
TscF
SCKX output fall
SP21
TscR
SCKX output rise time(4)
—
—
—
ns
See Parameter
DO31
SP30
TdoF
SDOX data output fall time(4)
—
—
—
ns
See Parameter
DO32
SP31
TdoR
SDOX data output rise time(4)
—
—
—
ns
See Parameter
DO31
SP35
TscH2doV SDOX data output valid after
,
SCKX edge
TscL2doV
—
—
30
ns
SP36
TdoV2sc, SDOX data output setup to
TdoV2scL first SCKX edge
30
—
—
ns
SP40
TdiV2scH, Setup time of SDIX data input
TdiV2scL to SCKX edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
20
—
—
ns
Note 1:
2:
3:
4:
Hold time of SDIX data input
to SCKX edge
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
DS70116J-page 190
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
FIGURE 23-16:
SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
BIT14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb IN
BIT14 - - - -1
LSb IN
SP41
SP40
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-33: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
—
—
ns
Conditions
SP70
TscL
SCKX Input Low Time
30
SP71
TscH
SCKX Input High Time
30
—
—
ns
SP72
TscF
SCKX Input Fall Time(3)
—
10
25
ns
SP73
TscR
SCKX Input Rise Time(3)
—
10
25
ns
SP30
TdoF
SDOX Data Output Fall Time(3)
—
—
—
ns
See Parameter DO32
See Parameter DO31
SP31
TdoR
—
—
—
ns
SP35
TscH2doV, SDOX Data Output Valid after
TscL2doV SCKX Edge
—
—
30
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIX Data Input to
SCKX Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIX Data Input
to SCKX Edge
20
—
—
ns
SP50
TssL2scH,
TssL2scL
SSX↓ to SCKX↑ or SCKX↓ Input
120
—
—
ns
SP51
TssH2doZ
SSX↑ to SDOX Output
High-Impedance(3)
10
—
50
ns
SP52
TscH2ssH SSX after SCK Edge
TscL2ssH
1.5 TCY
+40
—
—
ns
Note 1:
2:
3:
SDOX Data Output Rise Time
(3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
Assumes 50 pF load on all SPI pins.
© 2011 Microchip Technology Inc.
DS70116J-page 191
dsPIC30F5011/5013
FIGURE 23-17:
SPI MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SP52
MSb
SDOX
BIT14 - - - - - -1
LSb
SP30,SP31
SDIX
MSb IN
BIT14 - - - -1
SP51
LSb IN
SP41
SP40
Note: Refer to Figure 23-3 for load conditions.
DS70116J-page 192
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
—
—
ns
SP70
TscL
SCKX Input Low Time
30
SP71
TscH
SCKX Input High Time
30
—
—
ns
SP72
TscF
SCKX Input Fall Time(3)
—
10
25
ns
SP73
TscR
SCKX Input Rise Time(3)
—
10
25
ns
(3)
Conditions
SP30
TdoF
SDOX Data Output Fall Time
—
—
—
ns
See parameter
DO32
SP31
TdoR
SDOX Data Output Rise Time(3)
—
—
—
ns
See parameter
DO31
SP35
TscH2doV SDOX Data Output Valid after
,
SCKX Edge
TscL2doV
—
—
30
ns
SP40
TdiV2scH, Setup Time of SDIX Data Input
TdiV2scL to SCKX Edge
20
—
—
ns
SP41
TscH2diL, Hold Time of SDIX Data Input
TscL2diL to SCKX Edge
20
—
—
ns
SP50
TssL2scH, SSX↓ to SCKX↓ or SCKX↑ input
TssL2scL
120
—
—
ns
SP51
TssH2doZ SS↑ to SDOX Output
High-Impedance(4)
10
—
50
ns
SP52
TscH2ssH SSX↑ after SCKX Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
SP60
TssL2doV SDOX Data Output Valid after
SSX Edge
—
—
50
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
© 2011 Microchip Technology Inc.
DS70116J-page 193
dsPIC30F5011/5013
FIGURE 23-18:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL
IM31
IM34
IM30
IM33
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 23-3 for load conditions.
FIGURE 23-19:
I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL
IM11
IM26
IM10
IM25
IM33
SDA
In
IM40
IM40
IM45
SDA
Out
Note: Refer to Figure 23-3 for load conditions.
DS70116J-page 194
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-35: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
Min(1)
Max
Units
TLO:SCL Clock Low Time 100 kHz mode
TCY / 2 (BRG + 1)
—
µs
400 kHz mode
TCY / 2 (BRG + 1)
—
µs
mode(2)
TCY / 2 (BRG + 1)
—
µs
Clock High Time 100 kHz mode
TCY / 2 (BRG + 1)
—
µs
400 kHz mode
TCY / 2 (BRG + 1)
—
µs
1 MHz mode(2) TCY / 2 (BRG + 1)
—
µs
Characteristic
1 MHz
IM11
THI:SCL
IM20
TF:SCL
IM21
TR:SCL
IM25
SDA and SCL
Fall Time
SDA and SCL
Rise Time
TSU:DAT Data Input
Setup Time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
mode(2)
—
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
1 MHz mode(2)
—
—
ns
100 kHz mode
TCY / 2 (BRG + 1)
—
µs
400 kHz mode
TCY / 2 (BRG + 1)
—
µs
1 MHz
IM26
THD:DAT Data Input
Hold Time
IM30
TSU:STA
IM31
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
IM33
TSU:STO Stop Condition
Setup Time
1 MHz mode(2) TCY / 2 (BRG + 1)
—
µs
100 kHz mode
TCY / 2 (BRG + 1)
—
µs
400 kHz mode
TCY / 2 (BRG + 1)
—
µs
1 MHz mode(2) TCY / 2 (BRG + 1)
—
µs
100 kHz mode
TCY / 2 (BRG + 1)
—
µs
400 kHz mode
TCY / 2 (BRG + 1)
—
µs
mode(2)
TCY / 2 (BRG + 1)
—
µs
100 kHz mode
TCY / 2 (BRG + 1)
—
ns
400 kHz mode
TCY / 2 (BRG + 1)
—
ns
1 MHz mode(2) TCY / 2 (BRG + 1)
—
ns
1 MHz
IM34
THD:STO Stop Condition
Hold Time
IM40
TAA:SCL
Output Valid
From Clock
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
mode(2)
—
—
ns
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
1 MHz mode(2)
—
—
µs
—
400
pF
1 MHz
IM45
TBF:SDA Bus Free Time
IM50
CB
Note 1:
2:
Bus Capacitive Loading
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
repeated Start
condition
After this period the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
BRG is the value of the I2C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit™ (I2C)”
in the “dsPIC30F Family Reference Manual” (DS70046).
Maximum pin capacitance = 10 pF for all I2C pins (for 1 MHz mode only).
© 2011 Microchip Technology Inc.
DS70116J-page 195
dsPIC30F5011/5013
FIGURE 23-20:
I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL
IS34
IS31
IS30
IS33
SDA
Stop
Condition
Start
Condition
FIGURE 23-21:
I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL
IS30
IS26
IS31
IS25
IS33
SDA
In
IS40
IS40
IS45
SDA
Out
DS70116J-page 196
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-36: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
IS10
IS11
Symbol
TLO:SCL
THI:SCL
Characteristic
Clock Low Time
Clock High Time
IS20
TF:SCL
SDA and SCL
Fall Time
IS21
TR:SCL
SDA and SCL
Rise Time
IS25
TSU:DAT
Data Input
Setup Time
IS26
THD:DAT
Data Input
Hold Time
IS30
TSU:STA
Start Condition
Setup Time
IS31
THD:STA
Start Condition
Hold Time
IS33
TSU:STO
Stop Condition
Setup Time
IS34
THD:STO
Stop Condition
Hold Time
IS40
TAA:SCL
Output Valid
From Clock
Min
Max
Units
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode(1)
100 kHz mode
0.5
4.0
—
—
μs
μs
400 kHz mode
0.6
—
μs
1 MHz mode(1)
0.5
—
20 + 0.1 CB
—
—
20 + 0.1 CB
—
250
100
100
0
0
0
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
0
—
300
300
100
1000
300
300
—
—
—
—
0.9
0.3
—
—
—
—
—
—
—
—
—
—
—
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
3500
1000
0
350
ns
1 MHz mode(1)
IS45
TBF:SDA Bus Free Time
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode(1)
0.5
—
μs
IS50
CB
Bus Capacitive Loading
—
400
pF
2
Note 1: Maximum pin capacitance = 10 pF for all I C™ pins (for 1 MHz mode only).
© 2011 Microchip Technology Inc.
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz.
—
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for repeated
Start condition
After this period the first
clock pulse is generated
Time the bus must be free
before a new transmission
can start
DS70116J-page 197
dsPIC30F5011/5013
FIGURE 23-22:
CXTX Pin
(output)
CAN MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CXRX Pin
(input)
CA20
TABLE 23-37: CAN MODULE I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
TioF
Port Output Fall Time
—
—
—
ns
See parameter
DO32
CA11
TioR
Port Output Rise Time
—
—
—
ns
See parameter
DO31
CA20
Tcwf
Pulse Width to Trigger
CAN Wakeup Filter
500
—
—
ns
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
DS70116J-page 198
© 2011 Microchip Technology Inc.
dsPIC30F5011/5013
TABLE 23-38: 12-BIT A/D MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
AD02
AVSS
Module VSS Supply
Greater of
VDD - 0.3
or 2.7
—
Lesser of
VDD + 0.3
or 5.5
V
VSS - 0.3
—
VSS + 0.3
V
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 2.7
—
AVDD
V
AVSS
—
AVDD - 2.7
V
AVSS - 0.3
—
AVDD + 0.3
V
—
150
.001
200
1
μA
μA
A/D operating
A/D off
VREFL
VREFH
V
See Note
AVSS - 0.3
AVDD + 0.3
V
AD06
VREFL
Reference Voltage Low
AD07
VREF
Absolute Reference
Voltage
AD08
IREF
Current Drain
Analog Input
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AD12
—
Leakage Current
—
±0.001
±0.610
μA
VINL = AVSS = VREFL =
0V, AVDD = VREFH = 5V
Source Impedance =
2.5 kΩ
AD13
—
Leakage Current
—
±0.001
±0.610
μA
VINL = AVSS = VREFL =
0V, AVDD = VREFH = 3V
Source Impedance =
2.5 kΩ
AD17
RIN
Recommended Impedance
of Analog Voltage Source
—
—
2.5K
Ω
AD20
Nr
Resolution
AD21
INL
Integral Nonlinearity
—
—
