dsPIC30F6010A/6015
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2011 Microchip Technology Inc.
DS70150E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-953-2
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70150E-page 2
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
High-Performance, 16-bit Digital Signal Controllers
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
with flexible Addressing modes
• 83 base instructions
• 24-bit wide instructions, 16-bit wide data path
• 144 Kbytes on-chip Flash program space
(Instruction words)
• 8 Kbytes of on-chip data RAM
• 4 Kbytes of nonvolatile data EEPROM
• Up to 30 MIPS operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with
PLL active (4x, 8x, 16x)
- 7.37 MHz internal RC with PLL active
(4x, 8x, 16x)
• 44 interrupt sources:
- Five external interrupt sources
- Eight user selectable priority levels for each
interrupt source
- Four processor trap sources
• 16 x 16-bit working register array
DSP Engine Features:
•
•
•
•
Dual data fetch
Accumulator write-back for DSP operations
Modulo and Bit-Reversed Addressing modes
Two, 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• All DSP instructions single cycle
• ±16-bit single-cycle shift
© 2011 Microchip Technology Inc.
Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Timer module with programmable prescaler:
- Five 16-bit timers/counters; optionally pair
16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• 3-wire SPI modules (supports 4 Frame modes)
• I2CTM module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Two UART modules with FIFO Buffers
• Two CAN modules, 2.0B compliant (dsPIC306010A)
• One CAN module, 2.0B compliant (dsPIC306015)
Motor Control PWM Module Features:
• Eight PWM output channels:
- Complementary or Independent Output
modes
- Edge and Center-Aligned modes
• Four duty cycle generators
• Dedicated time base
• Programmable output polarity
• Dead-Time control for Complementary mode
• Manual output control
• Trigger for A/D conversions
Quadrature Encoder Interface Module
Features:
•
•
•
•
•
•
•
Phase A, Phase B and Index Pulse input
16-bit up/down position counter
Count direction status
Position Measurement (x2 and x4) mode
Programmable digital noise filters on inputs
Alternate 16-bit Timer/Counter mode
Interrupt on position counter rollover/underflow
Analog Features:
• 10-bit Analog-to-Digital Converter (ADC) with
four S/H Inputs:
- 1 Msps conversion rate
- 16 input channels
- Conversion available during Sleep and Idle
• Programmable Brown-out Reset
DS70150E-page 3
dsPIC30F6010A/6015
Special Microcontroller Features:
CMOS Technology:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for
industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for
industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip,
low-power RC oscillator for reliable operation
• Fail-Safe Clock Monitor operation detects clock
failure and switches to on-chip, low-power RC
oscillator
• Programmable code protection
• In-Circuit Serial Programming™ (ICSP™)
• Selectable Power Management modes
- Sleep, Idle and Alternate Clock modes
•
•
•
•
Low-power, high-speed Flash technology
Wide operating voltage range (2.5V to 5.5V)
Industrial and Extended temperature ranges
Low-power consumption
dsPIC30F Motor Control and Power Conversion Family
UART
SPI
I2C™
CAN
Motor
Output
Program
A/D 10-bit Quad
SRAM EEPROM Timer Input
Comp/Std Control
Pins Mem. Bytes/
1 Msps
Enc
Bytes
Bytes
16-bit Cap
PWM
PWM
Instructions
dsPIC30F6010A
80
144K/48K
8192
4096
5
8
8
8 ch
16 ch
Yes
2
2
1
2
dsPIC30F6015
64
144K/48K
8192
4096
5
8
8
8 ch
16 ch
Yes
2
2
1
1
Device
DS70150E-page 4
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
Pin Diagram
PWM3H/RE5
PWM4L/RE6
IC5/RD12
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
OC7/CN15/RD6
67
66
65
64
63
62
61
70
69
68
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VSS
OC8/UPDN/CN16/RD7
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
PWM2H/RE3
80
79
78
77
76
75
74
73
72
71
PWM3L/RE4
80-Pin TQFP
1
2
PWM4H/RE7
3
T2CK/RC1
T4CK/RC3
SCK2/CN8/RG6
4
60
EMUC1/SOSCO/T1CK/CN0/RC14
59
EMUD1/SOSCI/CN1/RC13
58
EMUC2/OC1/RD0
57
5
56
IC4/RD11
IC3/RD10
6
55
IC2/RD9
SDI2/CN9/RG7
7
54
IC1/RD8
SDO2/CN10/RG8
MCLR
8
53
INT4/RA15
9
52
SS2/CN11/RG9
VSS
10
51
INT3/RA14
VSS
11
50
VDD
12
49
OSC2/CLKO/RC15
OSC1/CLKI
13
48
VDD
SCL/RG2
FLTA/INT1/RE8
dsPIC30F6010A
FLTB/INT2/RE9
14
47
AN5/QEB/CN7/RB5
15
46
SDA/RG3
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
16
45
EMUC3/SCK1/INT0/RF6
SDI1/RF7
© 2011 Microchip Technology Inc.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
IC7/CN20/RD14
IC8/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
U1TX/RF3
AVDD
41
24
20
VREF+/RA10
U1RX/RF2
PGD/EMUD/AN0/CN2/RB0
22
42
23
19
VREF-/RA9
EMUD3/SDO1/RF8
PGC/EMUC/AN1/CN3/RB1
21
18
43
AN7/RB7
AN2/SS1/CN4/RB2
AN6/OCFA/RB6
17
44
DS70150E-page 5
dsPIC30F6010A/6015
Pin Diagram
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C1TX/RF1
C1RX/RF0
VDD
VSS
OC8/UPDN/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
EMUD2/OC2/RD1
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC30F6015
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC2/OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKI
VDD
SCL/RG2
SDA/RG3
EMUC3/SCK1/INT0/RF6
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/CN17/RF4
U2TX/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
AN1/VREF-/CN3/RB1
AN0/VREF+/CN2/RB0
DS70150E-page 6
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 CPU Architecture Overview........................................................................................................................................................ 15
3.0 Memory Organization ................................................................................................................................................................. 23
4.0 Address Generator Units............................................................................................................................................................ 35
5.0 Interrupts .................................................................................................................................................................................... 41
6.0 Flash Program Memory.............................................................................................................................................................. 49
7.0 Data EEPROM Memory ............................................................................................................................................................. 55
8.0 I/O Ports ..................................................................................................................................................................................... 59
9.0 Timer1 Module ........................................................................................................................................................................... 65
10.0 Timer2/3 Module ........................................................................................................................................................................ 69
11.0 Timer4/5 Module ....................................................................................................................................................................... 77
12.0 Input Capture Module ................................................................................................................................................................ 81
13.0 Output Compare Module ............................................................................................................................................................ 85
14.0 Quadrature Encoder Interface (QEI) Module ............................................................................................................................. 91
15.0 Motor Control PWM Module ....................................................................................................................................................... 97
16.0 SPI Module............................................................................................................................................................................... 107
17.0 I2C™ Module ........................................................................................................................................................................... 111
18.0 Universal Asynchronous Receiver Transmitter (UART) Module .............................................................................................. 119
19.0 CAN Module ............................................................................................................................................................................. 127
20.0 10-bit High-Speed Analog-to-Digital Converter (ADC) Module ................................................................................................ 139
21.0 System Integration ................................................................................................................................................................... 151
22.0 Instruction Set Summary .......................................................................................................................................................... 165
23.0 Development Support............................................................................................................................................................... 173
24.0 Electrical Characteristics .......................................................................................................................................................... 177
25.0 Packaging Information.............................................................................................................................................................. 217
Appendix A: Revision History............................................................................................................................................................. 225
Index ................................................................................................................................................................................................. 227
The Microchip Web Site ..................................................................................................................................................................... 233
Customer Change Notification Service .............................................................................................................................................. 233
Customer Support .............................................................................................................................................................................. 233
Reader Response .............................................................................................................................................................................. 234
Product Identification System ............................................................................................................................................................ 235
TO OUR VALUED CUSTOMERS
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2011 Microchip Technology Inc.
DS70150E-page 7
dsPIC30F6010A/6015
NOTES:
DS70150E-page 8
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
This document contains device-specific information for
the dsPIC30F6010A and dsPIC30F6015 devices. The
dsPIC30F devices contain extensive Digital Signal
Processor (DSP) functionality within a high-performance 16-bit microcontroller (MCU) architecture.
Figure 1-1 shows a device block diagram for the
dsPIC30F6010A device. Figure 1-2 shows a device
block diagram for the dsPIC30F6015 device.
© 2011 Microchip Technology Inc.
DS70150E-page 9
dsPIC30F6010A/6015
FIGURE 1-1:
dsPIC30F6010A BLOCK DIAGRAM
Y Data Bus
X Data Bus
16
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
16
Data Latch
Y Data
RAM
(4 Kbytes)
Address
Latch
16
24
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Address Latch
Program Memory
(144 Kbytes)
Data EEPROM
(4 Kbytes)
Data Latch
X Data
RAM
(4 Kbytes)
Address
Latch
16
VREF-/RA9
VREF+/RA10
INT3/RA14
INT4/RA15
PORTA
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/CN6/RB4
AN5/QEB/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
16
16
X RAGU
X WAGU
16
24
16
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
T2CK/RC1
T4CK/RC3
EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
IR
16
16
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode and
Control
16 16
Control Signals
to Various Blocks
OSC1/CLKI
DSP
Engine
Power-up
Timer
ALU
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
SPI1,
SPI2
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
CAN1,
CAN2
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/UPDN/CN16/RD7
IC1/RD8
IC2/RD9
IC3/RD10
IC4/RD11
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
Watchdog
Timer
Low-Voltage
Detect
16
16
PORTD
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
Timers
QEI
Motor Control
PWM
UART1,
UART2
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
FLTA/INT1/RE8
FLTB/INT2/RE9
PORTE
C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
PORTG
DS70150E-page 10
PORTF
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
FIGURE 1-2:
dsPIC30F6015 BLOCK DIAGRAM
Y Data Bus
X Data Bus
Interrupt
Controller
PSV & Table
Data Access
24 Control Block
8
16
16
16
Data Latch
Y Data
RAM
(4 Kbytes)
Address
Latch
16
24
Y AGU
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Address Latch
Program Memory
(144 Kbytes)
Data EEPROM
(4 Kbytes)
16
Data Latch
X Data
RAM
(4 Kbytes)
Address
Latch
AN0/VREF+/CN2/RB0
AN1/VREF-/CN3/RB1
AN2/SS1/CN4/RB2
AN3/INDX/CN5/RB3
AN4/QEA/IC7/CN6/RB4
AN5/QEB/IC8/CN7/RB5
PGC/EMUC/AN6/OCFA/RB6
PGD/EMUD/AN7/RB7
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
16
16
X RAGU
X WAGU
16
24
16
Effective Address
16
Data Latch
ROM Latch
16
24
PORTB
IR
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode and
Control
16 16
Control Signals
to Various Blocks
OSC1/CLKI
EMUD1/SOSCI/T4CK/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
16
16
DSP
Engine
Power-up
Timer
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
OC4/RD3
OC5/IC5/CN13/RD4
OC6/IC6/CN14/RD5
OC7/CN15/RD6
OC8/UPDN/CN16/RD7
IC1/FLTA/INT1/RD8
IC2/FLTB/INT2/RD9
IC3/INT3/RD10
IC4/INT4/RD11
Divide
Unit
Oscillator
Start-up Timer
Timing
Generation
ALU
POR/BOR
Reset
MCLR
VDD, VSS
AVDD, AVSS
Watchdog
Timer
Low-Voltage
Detect
16
16
PORTD
CAN1
10-bit ADC
Input
Capture
Module
Output
Compare
Module
I2C™
SPI1,
SPI2
Timers
QEI
Motor Control
PWM
UART1,
UART2
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
PORTE
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
C1RX/RF0
C1TX/RF1
U1RX/SDI1/RF2
EMUD3/U1TX/SDO1/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
PORTG
© 2011 Microchip Technology Inc.
PORTF
DS70150E-page 11
dsPIC30F6010A/6015
Table 1-1 provides a brief description of the device I/O
pinout and the functions that are multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 1-1:
dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN15
I
Analog
Analog input channels. AN0 and AN1 are also used for device programming
data and clock inputs, respectively.
Pin Name
Description
AVDD
P
P
Positive supply for analog module. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog module. This pin must be connected at all times.
CLKI
CLKO
I
O
CN0-CN23
I
ST
Input change notification inputs. Can be software programmed for internal weak
pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN2 bus transmit pin.
EMUD
EMUC
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ICD Primary Communication Channel data input/output pin.
ICD Primary Communication Channel clock input/output pin.
ICD Secondary Communication Channel data input/output pin.
ICD Secondary Communication Channel clock input/output pin.
ICD Tertiary Communication Channel data input/output pin.
ICD Tertiary Communication Channel clock input/output pin.
ICD Quaternary Communication Channel data input/output pin.
ICD Quaternary Communication Channel clock input/output pin.
IC1-IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
I
I
ST
ST
QEB
I
ST
UPDN
O
—
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase B input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
Legend: CMOS =
ST
=
I
=
DS70150E-page 12
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog =
O
=
P
=
Analog input
Output
Power
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
TABLE 1-1:
dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
FLTA
FLTB
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM1 Low output.
PWM1 High output.
PWM2 Low output.
PWM2 High output.
PWM3 Low output.
PWM3 High output.
PWM4 Low output.
PWM4 High output.
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an
active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
OSC2
I/O
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming™ data input/output pin.
In-Circuit Serial Programming clock input pin.
RA9-RA10
RA14-RA15
I/O
I/O
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1
RC3
RC13-RC15
I/O
I/O
I/O
ST
ST
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
Pin Name
Description
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
RE0-RE9
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF8
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
I/O
I/O
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
I/O
I
O
I
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
SPI1 Data Out.
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SPI2 Data Out.
SPI2 Slave Synchronization.
SCL
SDA
I/O
I/O
ST
ST
Synchronous serial clock input/output for I2C™.
Synchronous serial data input/output for I2C.
SOSCO
SOSCI
O
I
T1CK
T2CK
T4CK
I
I
I
Legend: CMOS =
ST
=
I
=
—
32 kHz low-power oscillator crystal output.
ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC
mode; CMOS otherwise.
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer4 external clock input.
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
© 2011 Microchip Technology Inc.
Analog =
O
=
P
=
Analog input
Output
Power
DS70150E-page 13
dsPIC30F6010A/6015
TABLE 1-1:
dsPIC30F6010A/6015 I/O PIN DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
U1RX
U1TX
U1ARX
U1ATX
U2RX
U2TX
I
O
I
O
I
O
ST
—
ST
—
ST
—
UART1 Receive.
UART1 Transmit.
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
UART2 Transmit.
VDD
P
—
Positive supply for logic and I/O pins.
VSS
P
—
Ground reference for logic and I/O pins.
VREF+
I
Analog
Analog Voltage Reference (High) input.
VREF-
I
Analog
Analog Voltage Reference (Low) input.
Pin Name
Legend: CMOS =
ST
=
I
=
DS70150E-page 14
Description
CMOS compatible input or output
Schmitt Trigger input with CMOS levels
Input
Analog =
O
=
P
=
Analog input
Output
Power
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
2.0
Note:
CPU ARCHITECTURE
OVERVIEW
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
This chapter summarizes the CPU and peripheral
functions of the dsPIC30F6010A/6015.
2.1
Core Overview
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are supported using the DO and REPEAT instructions, both of
which are interruptible at any point.
The working register array consists of 16x16-bit registers, each of which can act as data, address or offset
registers. One working register (W15) operates as a
Software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split into
two blocks, referred to as X and Y data memory. Each
block has its own independent Address Generation Unit
(AGU). Most instructions operate solely through the X
memory AGU, which provides the appearance of a single unified data space. The Multiply-Accumulate (MAC)
class of dual source DSP instructions operate through
both the X and Y AGUs, splitting the data address space
into two parts (see Section 3.2 “Data Address
Space”). The X and Y data space boundary is devicespecific and cannot be altered by the user. Each data
word consists of 2 bytes, and most instructions can
address data either as words or bytes.
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can be
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined by
the 8-bit Program Space Visibility Page (PSVPAG)
register. This lets any instruction access program
space as if it were data space, with a limitation that
the access requires an additional cycle. Moreover,
only the lower 16 bits of each instruction word can be
accessed using this method.
© 2011 Microchip Technology Inc.
• Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions. Table
read and write instructions can be used to access all
24 bits of an instruction word.
Overhead-free circular buffers (Modulo Addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing on
destination Effective Addresses, to greatly simplify
input or output data reordering for radix-2 FFT algorithms. Refer to Section 4.0 “Address Generator
Units” for details on Modulo and Bit-Reversed
Addressing.
The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working register (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 16 bits
right or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by dedicating certain working registers to each address space
for the MAC class of instructions.
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction prefetch
mechanism is used, which accesses and partially
decodes instructions a cycle ahead of execution, in
order to maximize available execution time. Most
instructions execute in a single cycle, with certain
exceptions.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps (of
which 4 are reserved) and 54 interrupts. Each interrupt
is prioritized based on a user-assigned priority between
1 and 7 (1 being the lowest priority and 7 being the
highest) in conjunction with a predetermined ‘natural
order’. Traps have fixed priorities, ranging from 8 to 15.
DS70150E-page 15
dsPIC30F6010A/6015
2.2
Programmer’s Model
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (AccA and AccB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register associated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
• DO instruction
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start and popped on loop end.
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte-wide data memory space accesses.
2.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
The dsPIC DSC devices contain a software stack. W15
is the dedicated Software Stack Pointer (SP), and will
be automatically modified by exception processing and
subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the Stack Pointer (e.g., creating
stack frames).
Note:
In order to protect against misaligned
stack accesses, W15 is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
STATUS REGISTER
The dsPIC DSC core has a 16-bit STATUS register
(SR), the LSB of which is referred to as the SR Low
Byte (SRL) and the MSB as the SR High Byte (SRH).
See Figure 2-1 for SR layout.
SRL contains all the MCU ALU operation status flags
(including the Z bit), as well as the CPU Interrupt Priority Level Status bits, IPL, and the Repeat Active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the SR register contains the DSP
adder/subtractor Status bits, the DO Loop Active bit
(DA) and the Digit Carry (DC) Status bit.
2.2.3
PROGRAM COUNTER
The Program Counter is 23 bits wide. Bit 0 is always
clear. Therefore, the PC can address up to 4M
instruction words.
DS70150E-page 16
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
FIGURE 2-1:
dsPIC30F6010A/6015 PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
AccA
DSP
Accumulators
AccB
PC22
PC0
Program Counter
0
0
7
TABPAG
TBLPAG
7
Data Table Page Address
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
© 2011 Microchip Technology Inc.
DC IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70150E-page 17
dsPIC30F6010A/6015
2.3
Divide Support
2.4
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit signed and unsigned integer divide operations, in the form of single instruction iterative divides.
The following instructions and data sizes are
supported:
•
•
•
•
•
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.s – 16/16 signed divide
DIV.u – 16/16 unsigned divide
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g., a
series of discrete divide instructions) will not function
correctly because the instruction flow depends on
RCOUNT. The divide instruction does not automatically
set up the RCOUNT value, and it must, therefore, be
explicitly and correctly specified in the REPEAT instruction, as shown in Table 2-2 (REPEAT will execute the
target instruction {operand value + 1} times). The
REPEAT loop count must be set up for 18 iterations of
the DIV/DIVF instruction. Thus, a complete divide
operation requires 19 cycles.
Note:
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter, and a 40-bit adder/subtractor (with two target accumulators, round and
saturation logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
Fractional or Integer DSP Multiply (IF).
Signed or Unsigned DSP Multiply (US).
Conventional or Convergent Rounding (RND).
Automatic Saturation On/Off for AccA (SATA).
Automatic Saturation On/Off for AccB (SATB).
Automatic Saturation On/Off for Writes to Data
Memory (SATDW).
Accumulator Saturation mode Selection
(ACCSAT).
Note:
For CORCON layout, see Table 3-3.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-1:
DSP INSTRUCTION
SUMMARY
Instruction
Algebraic Operation
CLR
A=0
ED
A = (x – y)2
EDAC
A = A + (x – y)2
MAC
A = A + (x * y)
No change in A
MOVSAC
A=x*y
MPY
A=–x*y
MPY.N
A=A–x*y
MSC
TABLE 2-2:
DIVIDE INSTRUCTIONS
Instruction
DIVF
Function
Signed fractional divide: Wm/Wn →W0; Rem →W1
DIV.sd
Signed divide: (Wm+1:Wm)/Wn →W0; Rem →W1
DIV.s
Signed divide: Wm/Wn →W0; Rem →W1
DIV.ud
Unsigned divide: (Wm+1:Wm)/Wn →W0; Rem →W1
DIV.u
Unsigned divide: Wm/Wn →W0; Rem →W1
DS70150E-page 18
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
FIGURE 2-2:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
Barrel
Shifter
16
X Data Bus
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
© 2011 Microchip Technology Inc.
DS70150E-page 19
dsPIC30F6010A/6015
2.4.1
MULTIPLIER
The 17x17-bit multiplier is capable of signed or
unsigned operations and can multiplex its output using
a scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17x17-bit multiplier/
scaler is a 33-bit value, which is sign-extended to
40 bits. Integer data is inherently represented as a
signed two’s complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF), including 0. For a 32-bit integer, the
data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit
(QX format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1-21-N).
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF), including 0 and
has a precision of 3.01518x10-5. In Fractional mode, a
16x16 multiply operation generates a 1.31 product,
which has a precision of 4.65661x10-10.
The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
2.4.2.1
The adder/subtractor is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active-high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active-low and the
other input is complemented. The adder/subtractor
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS register.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above, and the SATA/B (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow. They are:
1.
2.
3.
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTOR
The data accumulator consists of a 40-bit adder/subtractor with automatic sign extension logic. It can select
one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
DS70150E-page 20
Adder/Subtractor, Overflow and
Saturation
4.
5.
6.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data passes
through the adder/subtractor. When set, they indicate
that the most recent operation has overflowed into the
accumulator guard bits (bits 32 through 39). The OA and
OB bits can also optionally generate an arithmetic warning trap when set and the corresponding overflow trap
flag enable bit (OVATE, OVBTE) in the INTCON1 register (refer to Section 5.0 “Interrupts”) is set. This allows
the user to take immediate action, for example, to correct
system gain.
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
The SA and SB bits are modified each time data passes
through the adder/subtractor, but can only be cleared by
the user. When set, they indicate that the accumulator
has overflowed its maximum range (bit 31 for 32-bit
saturation, or bit 39 for 40-bit saturation) and will be
saturated if saturation is enabled. When saturation is not
enabled, SA and SB default to bit 39 overflow and thus
indicate that a catastrophic overflow has occurred. If the
COVTE bit in the INTCON1 register is set, SA and SB
bits will generate an arithmetic warning trap when
saturation is disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). This allows programmers to check
one bit in the STATUS register to determine if either
accumulator has overflowed, or one bit to determine if
either accumulator has saturated. This would be useful
for complex number arithmetic which typically uses
both the accumulators.
The device supports three Saturation and Overflow
modes.
1.
2.
3.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against erroneous data or unexpected algorithm problems
(e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are not
used so the OA, OB or OAB bits are never set.
Bit 39 Catastrophic Overflow
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remain set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
© 2011 Microchip Technology Inc.
2.4.2.2
Accumulator ‘Write-Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
2.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a 1.15
fraction.
[W13]+ = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
2.4.2.3
Round Logic
The round logic is a combinational block, which performs a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15 data
value which is passed to the data space write saturation
logic. If rounding is not indicated by the instruction, a
truncated 1.15 data value is stored and the least
significant word is simply discarded.
Conventional rounding takes bit 15 of the accumulator,
zero-extends it and adds it to the ACCxH word (bits 16
through 31 of the accumulator). If the ACCxL word (bits
0 through 15 of the accumulator) is between 0x8000
and 0xFFFF (0x8000 included), ACCxH is incremented. If ACCxL is between 0x0000 and 0x7FFF,
ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding
operations, the value will tend to be biased slightly
positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. If this is the case, the LSb
(bit 16 of the accumulator) of ACCxH is examined. If it
is ‘1’, ACCxH is incremented. If it is ‘0’, ACCxH is not
modified. Assuming that bit 16 is effectively random in
nature, this scheme will remove any rounding bias that
may accumulate.
The SAC and SAC.R instructions store either a truncated (SAC) or rounded (SAC.R) version of the contents
of the target accumulator to data memory, via the X bus
(subject to data saturation, see Section 2.4.2.4 “Data
Space Write Saturation”). Note that for the MAC class
of instructions, the accumulator write-back operation
will function in the same manner, addressing combined
MCU (X and Y) data space though the X bus. For this
class of instructions, the data is always subject to
rounding.
DS70150E-page 21
dsPIC30F6010A/6015
2.4.2.4
Data Space Write Saturation
2.4.3
BARREL SHIFTER
In addition to adder/subtractor saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These are
combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The MSb of the
source (bit 39) is used to determine the sign of the
operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 to
31 for right shifts, and bit positions 0 to 15 for left shifts.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value will shift the operand
right. A negative value will shift the operand left. A
value of ‘0’ will not modify the operand.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
DS70150E-page 22
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
Note:
3.1
MEMORY ORGANIZATION
FIGURE 3-1:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
Program Address Space
The program address space is 4M instruction words. It
is addressable by the 23-bit PC, table instruction
Effective Address (EA), or data space EA, when
program space is mapped into data space, as defined
by Table 3-1. Note that the program space address is
incremented by two between successive program
words, in order to provide compatibility with data space
addressing.
PROGRAM SPACE
MEMORY MAP FOR
dsPIC30F6010A/6015
Reset – GOTO Instruction
Reset – Target Address
000000
000002
000004
Vector Tables
Interrupt Vector Table
User Memory
Space
3.0
Reserved
Alternate Vector Table
User Flash
Program Memory
(48K instructions)
Reserved
(Read ‘0’s)
00007E
000080
000084
0000FE
000100
017FFE
018000
7FEFFE
7FF000
Data EEPROM
(4 Kbytes)
User program space access is restricted to the lower
4M instruction word address range (0x000000 to
0x7FFFFE), for all accesses other than TBLRD/TBLWT,
which use TBLPAG to determine user or configuration space access. In Table 3-1, read/write instructions,
bit 23 allows access to the device ID, the user ID and
the Configuration bits. Otherwise, bit 23 is always clear.
7FFFFE
800000
Configuration Memory
Space
Reserved
UNITID (32 instr.)
8005BE
8005C0
8005FE
800600
Reserved
Device Configuration
Registers
F7FFFE
F80000
F8000E
F80010
Reserved
DEVID (2)
© 2011 Microchip Technology Inc.
FEFFFE
FF0000
FFFFFE
DS70150E-page 23
dsPIC30F6010A/6015
TABLE 3-1:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Instruction Access
TBLRD/TBLWT
TBLRD/TBLWT
Program Space Visibility
FIGURE 3-2:
User
User
(TBLPAG = 0)
Configuration
(TBLPAG = 1)
User
Program Space Address
0
PC
TBLPAG
Data EA
TBLPAG
0
0
Data EA
PSVPAG
Data EA
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
23 bits
Using
Program
Counter
Program Counter
0
Select
Using
Program
Space
Visibility
0
1
0
EA
PSVPAG Reg
8 bits
15 bits
EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 bits
User/
Configuration
Space
Select
16 bits
24-bit EA
Byte
Select
Note: Program Space Visibility cannot be used to access bits of a word in program memory.
DS70150E-page 24
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
3.1.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
A set of table instructions are provided to move byte or
word-sized data to and from program space.
1.
This architecture fetches 24-bit wide program memory.
Consequently, instructions are always aligned. However, as the architecture is modified Harvard, data can
also be present in program space.
There are two methods by which program space can
be accessed; via special table instructions, or through
the remapping of a 16K word program space page into
the upper half of data space (see Section 3.1.2 “Data
Access from Program Memory Using Program
Space Visibility”). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the least
significant word of any address within program space,
without going through data space. The TBLRDH and
TBLWTH instructions are the only method whereby the
upper 8 bits of a program space word can be accessed
as data.
2.
3.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the lsw, and TBLRDH
and TBLWTH access the space which contains the
MSB.
4.
TBLRDL: Table Read Low
Word: Read the least significant word of the
program address;
P maps to D.
Byte: Read one of the Least Significant Bytes of
the program address;
P maps to the destination byte when byte
select = 0;
P maps to the destination byte when byte
select = 1.
TBLWTL: Table Write Low (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
TBLRDH: Table Read High
Word: Read the most significant word of the
program address;
P maps to D; D always
be = 0.
Byte: Read one of the Most Significant Bytes of
the program address;
P maps to the destination byte when
byte select = 0;
The destination byte will always be = 0 when
byte select = 1.
TBLWTH: Table Write High (refer to Section 6.0
“Flash Program Memory” for details on Flash
Programming).
Figure 3-2 shows how the EA is created for table operations and data space accesses (PSV = 1). Here,
P refers to a program space word, whereas
D refers to a data space word.
FIGURE 3-3:
PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)
PC Address
0x000000
0x000002
0x000004
0x000006
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
© 2011 Microchip Technology Inc.
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDL.W
TBLRDL.B (Wn = 0)
TBLRDL.B (Wn = 1)
DS70150E-page 25
dsPIC30F6010A/6015
FIGURE 3-4:
PROGRAM DATA TABLE ACCESS (MOST SIGNIFICANT BYTE)
TBLRDH.W
PC Address
0x000000
0x000002
0x000004
0x000006
23
16
8
0
00000000
00000000
00000000
00000000
TBLRDH.B (Wn = 0)
Program Memory
‘Phantom’ Byte
(Read as ‘0’)
3.1.2
TBLRDH.B (Wn = 1)
DATA ACCESS FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word program space page. This
provides transparent access of stored constant data
from X data space, without the need to use special
instructions (i.e., TBLRDL/H, TBLWTL/H instructions).
Program space access through the data space occurs
if the MSb of the data space EA is set and program
space visibility is enabled, by setting the PSV bit in the
Core Control register (CORCON). The functions of
CORCON are discussed in Section 2.4 “DSP
Engine”.
Data accesses to this area add an additional cycle to
the instruction being executed, since two program
memory fetches are required.
Note that the upper half of addressable data space is
always part of the X data space. Therefore, when a
DSP operation uses program space mapping to access
this memory region, Y data space should typically contain state (variable) data for DSP operations, whereas
X data space should typically contain coefficient
(constant) data.
Although each data space address, 0x8000 and higher,
maps directly into a corresponding program memory
address (see Figure 3-5), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits should be programmed to force an illegal
instruction to maintain machine robustness. Refer
to the “16-bit MCU and DSC Programmer’s Reference
Manual” (DS70157) for details on instruction encoding.
DS70150E-page 26
Note that by incrementing the PC by 2 for each
program memory word, the Least Significant 15 bits of
data space addresses directly map to the Least Significant 15 bits in the corresponding program space
addresses. The remaining bits are provided by the
Program Space Visibility Page register, PSVPAG,
as shown in Figure 3-5.
Note:
PSV access is temporarily disabled during
table reads/writes.
For instructions that use PSV which are executed
outside a REPEAT loop:
• The following instructions will require one instruction cycle in addition to the specified execution
time:
- MAC class of instructions with data operand
prefetch
- MOV instructions
- MOV.D instructions
• All other instructions will require two instruction
cycles in addition to the specified execution time
of the instruction.
For instructions that use PSV which are executed
inside a REPEAT loop:
• The following instances will require two instruction
cycles in addition to the specified execution time
of the instruction:
- Execution in the first iteration
- Execution in the last iteration
- Execution prior to exiting the loop due to an
interrupt
- Execution upon re-entering the loop after an
interrupt is serviced
• Any other iteration of the REPEAT loop will allow
the instruction, accessing data using PSV, to
execute in a single cycle.
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
FIGURE 3-5:
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
Data Space
Program Space
0x000100
0x0000
PSVPAG(1)
0x00
8
15
EA = 0
Data
Space
EA
16
15
EA = 1
0x8000
Address
15 Concatenation 23
23
15
0
0x001200
Upper half of Data
Space is mapped
into Program Space
0x017FFE
0xFFFF
BSET
MOV
MOV
MOV
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Read
Note: PSVPAG is an 8-bit register, containing bits of the program space address
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
3.2
Data Address Space
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instructions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
DATA SPACE MEMORY MAP
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent Linear
Addressing space, X and Y spaces have contiguous
addresses.
© 2011 Microchip Technology Inc.
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
64 Kbyte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 64 Kbyte data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in Figure 3-6.
Figure 3-7 shows a graphical summary of how X and Y
data spaces are accessed for MCU and DSP
instructions.
DS70150E-page 27
dsPIC30F6010A/6015
FIGURE 3-6:
dsPIC30F6010A/6015 DATA SPACE MEMORY MAP
Most Significant Byte
Address
MSB
2 Kbyte
SFR Space
0x0001
Least Significant Byte
Address
16 bits
LSB
0x0000
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8 Kbyte
Near
Data
Space
X Data RAM (X)
8 Kbyte
SRAM Space
0x17FF
0x1801
0x17FE
0x1800
0x1FFF
0x1FFE
Y Data RAM (Y)
0x27FF
0x27FE
0x2801
0x2800
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70150E-page 28
0xFFFE
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE
SFR SPACE
SFR SPACE
X SPACE
FIGURE 3-7:
Y SPACE
UNUSED
X SPACE
(Y SPACE)
X SPACE
UNUSED
UNUSED
Non-MAC Class Ops (Read/Write)
MAC Class Ops (Write)
MAC Class Ops Read-Only
Indirect EA using any W
Indirect EA using W10, W11 Indirect EA using W8, W9
© 2011 Microchip Technology Inc.
DS70150E-page 29
dsPIC30F6010A/6015
3.2.2
DATA SPACES
3.2.3
The X data space is used by all instructions and supports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
The X data space also supports Modulo Addressing for
all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing is only supported for
writes to X data space.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED, EDAC,
MAC, MOVSAC, MPY, MPY.N and MSC) to provide two
concurrent data read paths. No writes occur across the
Y bus. This class of instructions dedicates two W register pointers, W10 and W11, to always address Y data
space, independent of X data space, whereas W8 and
W9 always address X data space. Note that during
accumulator write-back, the data address space is considered a combination of X and Y data spaces, so the
write occurs across the X bus. Consequently, the write
can be to any address in the entire data space.
The Y data space can only be used for the data
prefetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other instructions can access the Y data address space through the
X data path, as part of the composite linear space.
The boundary between the X and Y data spaces is
defined as shown in Figure 3-6 and is not user programmable. Should an EA point to data outside its own
assigned address space, or to a location outside physical memory, an all-zero word/byte will be returned. For
example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
TABLE 3-2:
EFFECT OF INVALID
MEMORY ACCESSES
Attempted Operation
The core data width is 16 bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
3.2.4
0x0000
W8 or W9 used to access Y data
space in a MAC instruction
0x0000
W10 or W11 used to access X
data space in a MAC instruction
0x0000
DATA ALIGNMENT
To help maintain backward compatibility with PIC®
devices and improve data space memory usage efficiency, the dsPIC30F instruction set supports both
word and byte operations. Data is aligned in data memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word, which contains the byte, using the LSb of any EA
to determine which byte to select. The selected byte is
placed onto the LSB of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
As a consequence of this byte accessibility, all Effective
Address calculations (including those generated by the
DSP operations, which are restricted to word-sized
data) are internally scaled to step through word-aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. Should a
misaligned read or write be attempted, an address
error trap will be generated. If the error occurred on a
read, the instruction underway is completed, whereas if
it occurred on a write, the instruction will be executed
but the write will not occur. In either case, a trap will
then be executed, allowing the system and/or user to
examine the machine state prior to execution of the
address Fault.
FIGURE 3-8:
Data Returned
EA = an unimplemented address
DATA SPACE WIDTH
15
DATA ALIGNMENT
MSB
87
LSB
0
0001
Byte 1
Byte 0
0000
0003
Byte 3
Byte 2
0002
0005
Byte 5
Byte 4
0004
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
DS70150E-page 30
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
NEAR DATA SPACE
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6
SOFTWARE STACK
The dsPIC DSC device contains a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
Figure 3-9. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
CALL STACK FRAME
0x0000 15
Stack Grows Towards
Higher Address
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP: [--W15]
PUSH: [W15++]
3.2.7
DATA RAM PROTECTION FEATURE
The dsPIC30F6010A/6015 devices support Data RAM
protection features which enable segments of RAM to
be protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM
segment for RAM) is accessible only from the Secure
Segment Flash code when enabled.
See Table 3-3 for an overview of the BSRAM and
SSRAM SFRs.
There is a Stack Pointer Limit register (SPLIM) associated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM
is forced to ‘0’, because all stack operations must be
word-aligned. Whenever an Effective Address (EA) is
generated using W15 as a source or destination
pointer, the address thus generated is compared with
the value in SPLIM. If the contents of the Stack Pointer
(W15) and the SPLIM register are equal and a push
operation is performed, a stack error trap will not occur.
The stack error trap will occur on a subsequent push
operation. Thus, for example, if it is desirable to cause
a stack error trap when the stack grows beyond
address 0x2000 in RAM, initialize the SPLIM with the
value, 0x1FFE.
© 2011 Microchip Technology Inc.
DS70150E-page 31
SFR Name
CORE REGISTER MAP(1)
Address
(Home)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
© 2011 Microchip Technology Inc.
W0
0000
W0 / WREG
0000 0000 0000 0000
W1
0002
W1
0000 0000 0000 0000
W2
0004
W2
0000 0000 0000 0000
W3
0006
W3
0000 0000 0000 0000
W4
0008
W4
0000 0000 0000 0000
W5
000A
W5
0000 0000 0000 0000
W6
000C
W6
0000 0000 0000 0000
W7
000E
W7
0000 0000 0000 0000
W8
0010
W8
0000 0000 0000 0000
W9
0012
W9
0000 0000 0000 0000
W10
0014
W10
0000 0000 0000 0000
W11
0016
W11
0000 0000 0000 0000
W12
0018
W12
0000 0000 0000 0000
W13
001A
W13
0000 0000 0000 0000
W14
001C
W14
0000 0000 0000 0000
W15
001E
W15
0000 1000 0000 0000
SPLIM
0020
SPLIM
0000 0000 0000 0000
ACCAL
0022
ACCAL
0000 0000 0000 0000
ACCAH
0024
ACCAH
ACCAU
0026
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
PCL
002E
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
—
TBLPAG
0000 0000 0000 0000
PSVPAG
0034
—
—
—
—
—
—
—
—
PSVPAG
0000 0000 0000 0000
RCOUNT
0036
RCOUNT
DCOUNT
0038
DCOUNT
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
0040
Legend:
Note 1:
0000 0000 0000 0000
Sign Extension (ACCA)
ACCAU
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Sign Extension (ACCB)
ACCBU
0000 0000 0000 0000
PCL
0000 0000 0000 0000
—
PCH
uuuu uuuu uuuu uuuu
uuuu uuuu uuuu uuuu
DOSTARTL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
0
uuuu uuuu uuuu uuu0
0
uuuu uuuu uuuu uuu0
DOSTARTH
DOENDL
—
0000 0000 0000 0000
DOENDH
0000 0000 0uuu uuuu
0000 0000 0uuu uuuu
dsPIC30F6010A/6015
DS70150E-page 32
TABLE 3-3:
© 2011 Microchip Technology Inc.
TABLE 3-3:
SFR Name
SR
CORE REGISTER MAP(1) (CONTINUED)
Address
(Home)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
0000 0000 0000 0000
—
—
—
US
EDT
DL2
DL1
DL0
SATA
SATB
IPL3
PSV
RND
IF
—
—
CORCON
0044
MODCON
0046
XMODEN YMODEN
BWM
SATDW ACCSAT
YWM
XWM
0000 0000 0010 0000
0000 0000 0000 0000
XMODSRT
0048
XS
0
uuuu uuuu uuuu uuu0
XMODEND
004A
XE
1
uuuu uuuu uuuu uuu1
YMODSRT
004C
YS
0
uuuu uuuu uuuu uuu0
YMODEND
004E
YE
1
uuuu uuuu uuuu uuu1
XBREV
0050
BREN
DISICNT
0052
—
—
BSRAM
0750
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR IR_BSR RL_BSR 0000 0000 0000 0000
0752
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_SSR IR_SSR RL_SSR 0000 0000 0000 0000
SSRAM
Legend:
Note 1:
XB
uuuu uuuu uuuu uuuu
DISICNT
0000 0000 0000 0000
u = uninitialized bit; — = unimplemented bit, read as ‘0’
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
dsPIC30F6010A/6015
DS70150E-page 33
dsPIC30F6010A/6015
NOTES:
DS70150E-page 34
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
4.0
Note:
ADDRESS GENERATOR UNITS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
The dsPIC DSC core contains two independent
Address Generator Units (AGU): the X AGU and Y
AGU. The Y AGU supports word-sized data reads for
the DSP MAC class of instructions only. The dsPIC DSC
AGUs support three types of data addressing:
• Linear Addressing
• Modulo (Circular) Addressing
• Bit-Reversed Addressing
Linear and Modulo Data Addressing modes can be
applied to data space or program space. Bit-Reversed
Addressing mode is only applicable to data space
addresses.
4.1
Instruction Addressing Modes
The addressing modes in Table 4-1 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
TABLE 4-1:
4.1.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (near data space). Most file
register instructions employ a working register W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register, or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space during file register
operation.
4.1.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct), which is
referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or an address
location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
© 2011 Microchip Technology Inc.
The sum of Wn and a literal forms the EA.
DS70150E-page 35
dsPIC30F6010A/6015
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP Accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instructions, Move and Accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. However, the 4-bit Wb (Register Offset) field is
shared between both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by Move and Accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
4.1.4
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also
referred to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the data pointers through Register Indirect
tables.
The two source operand prefetch registers must be a
member of the set {W8, W9, W10, W11}. For data reads,
W8 and W9 will always be directed to the X RAGU and
W10 and W11 will always be directed to the Y AGU. The
Effective Addresses generated (before and after modification) must, therefore, be valid addresses within X data
space for W8 and W9 and Y data space for W10 and
W11.
Note:
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.1.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ADD Acc, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as NOP, do not have any
operands.
4.2
Modulo Addressing
Modulo Addressing is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or
program space (since the data pointer mechanism is
essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Modulo
Addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for
Modulo Addressing, since these two registers are used
as the Stack Frame Pointer and Stack Pointer,
respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer start address (for
incrementing buffers) or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers which have a power-of-2 length. As these
buffers satisfy the start and end address criteria, they
may operate in a Bidirectional mode, (i.e., address
boundary checks will be performed on both the lower
and upper address boundaries).
Register Indirect with Register Offset
Addressing is only available for W9 (in X
space) and W11 (in Y space).
DS70150E-page 36
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
4.2.1
START AND END ADDRESS
4.2.2
The Modulo Addressing scheme requires that a
starting and an ending address be specified and
loaded into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 3-3).
Note:
Y space Modulo Addressing EA calculations assume word-sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON, contains enable flags, as
well as a W register field to specify the W Address
registers. The XWM and YWM fields select which
registers will operate with Modulo Addressing. If
XWM = 15, X RAGU and X WAGU Modulo Addressing
are disabled. Similarly, if YWM = 15, Y AGU Modulo
Addressing is disabled.
The X Address Space Pointer W register (XWM) to
which Modulo Addressing is to be applied, is stored in
MODCON (see Table 3-3). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied, is stored in
MODCON. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON.
FIGURE 4-1:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
DO
MOV
AGAIN:
0x1100
#0x1100,W0
W0, XMODSRT
#0x1163,W0
W0,MODEND
#0x8001,W0
W0,MODCON
#0x0000,W0
#0x1110,W1
AGAIN,#0x31
W0, [W1++]
INC
W0,W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
;fill the 50 buffer locations
;fill the next location
;increment the fill value
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
© 2011 Microchip Technology Inc.
DS70150E-page 37
dsPIC30F6010A/6015
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the upper (for incrementing buffers) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
Note:
4.3
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (e.g.,
[W7+W2]) is used, Modulo Address correction is performed, but the contents of
the register remains unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.3.1
2.
3.
XB is the Bit-Reversed Address modifier or
‘pivot point’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
BWM (W register selection) in the MODCON register is any value other than 15 (the stack cannot
be accessed using Bit-Reversed Addressing)
and
the BREN bit is set in the XBREV register and
the addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
FIGURE 4-2:
All Bit-Reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing will only be
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data writes.
It will not function for any other addressing mode or for
byte-sized data, and normal addresses will be generated
instead. When Bit-Reversed Addressing is active, the W
Address Pointer will always be added to the address
modifier (XB) and the offset associated with the Register
Indirect Addressing mode will be ignored. In addition, as
word-sized data is a requirement, the LSb of the EA is
ignored (and always clear).
Note:
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
1.
If the length of a Bit-Reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer start address
must be zeros.
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do this, Bit-Reversed
Addressing will assume priority when
active for the X WAGU, and X WAGU
Modulo Addressing will be disabled. However, Modulo Addressing will continue to
function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV) bit, then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b1
b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-word Bit-Reversed Buffer
DS70150E-page 38
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
TABLE 4-2:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
TABLE 4-3:
BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER
Buffer Size (Words)
XB Bit-Reversed Address Modifier Value
4096
0x0800
2048
0x0400
1024
0x0200
512
0x0100
256
0x0080
128
0x0040
64
0x0020
32
0x0010
16
0x0008
8
0x0004
4
0x0002
2
0x0001
© 2011 Microchip Technology Inc.
DS70150E-page 39
dsPIC30F6010A/6015
NOTES:
DS70150E-page 40
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
5.0
Note:
INTERRUPTS
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
The dsPIC30F6010A/6015 has 44 interrupt sources
and four processor exceptions (traps), which must be
arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt
Vector Table (IVT) and transferring the address contained in the interrupt vector to the program counter.
The interrupt vector is transferred from the program
data bus into the program counter, via a 24-bit wide
multiplexer on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt Vector Table (AIVT) are placed near the beginning
of program memory (0x000004). The IVT and AIVT
are shown in Figure 5-1.
The interrupt controller is responsible for preprocessing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers:
• IFS0, IFS1, IFS2
All Interrupt Request Flags are maintained in these
three registers. The flags are set by their respective
peripherals or external signals, and they are cleared
via software.
• IEC0, IEC1, IEC2
All Interrupt Enable Control bits are maintained in
these three registers. These control bits are used to
individually enable interrupts from the peripherals or
external signals.
• IPC0... IPC11
The user assignable priority level associated with
each of these 44 interrupts is held centrally in these
twelve registers.
• IPL
The current CPU priority level is explicitly stored in
the IPL bits. IPL is present in the CORCON register, whereas IPL are present in the STATUS
register (SR) in the processor core.
• INTCON1, INTCON2
Global interrupt control functions are derived from
these two registers. INTCON1 contains the control
and status flags for the processor exceptions. The
INTCON2 register controls the external interrupt
request signal behavior and the use of the alternate
vector table.
© 2011 Microchip Technology Inc.
• INTTREG
The associated interrupt vector number and the
new CPU interrupt priority level are latched into
Vector number (VECNUM) and Interrupt
level ILR bit fields in the INTTREG register.
The new interrupt priority level is the priority of the
pending interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
All interrupt sources can be user assigned to one of
seven priority levels, 1 through 7, via the IPCx
registers. Each interrupt source is associated with an
interrupt vector, as shown in Table 5-1. Levels 7 and 1
represent the highest and lowest maskable priorities,
respectively.
Note:
Assigning a priority level of 0 to an interrupt source is equivalent to disabling that
interrupt.
If the NSTDIS bit (INTCON1) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, interrupt-on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to Figure 5-2).
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Figure 5-2). These locations contain 24-bit addresses,
and in order to preserve robustness, an address error
trap will take place should the PC attempt to fetch any
of these words during normal execution. This prevents
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space, or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO instruction to this vector space will also generate
an address error trap.
DS70150E-page 41
dsPIC30F6010A/6015
5.1
Interrupt Priority
The user-assignable Interrupt Priority bits (IP)
for each individual interrupt source are located in the
Least Significant 3 bits of each nibble within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned
to a particular interrupt by the user.
Note:
The user-assignable priority levels start at
0, as the lowest priority and level 7, as the
highest priority.
Since more than one interrupt request source may be
assigned to a specific user-assigned priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority”.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their associated
vector numbers.
Note 1: The Natural Order Priority scheme has 0
as the highest priority and 53 as the
lowest priority.
2: The Natural Order Priority number is the
same as the INT number.
The ability for the user to assign every interrupt to one
of seven priority levels means that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority.
DS70150E-page 42
TABLE 5-1:
INTERRUPT VECTOR TABLE
INT
Vector
Number Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45-53
Interrupt Source
Highest Natural Order Priority
8
INT0 – External Interrupt 0
9
IC1 – Input Capture 1
10
OC1 – Output Compare 1
11
T1 – Timer1
12
IC2 – Input Capture 2
13
OC2 – Output Compare 2
14
T2 – Timer2
15
T3 – Timer3
16
SPI1
17
U1RX – UART1 Receiver
18
U1TX – UART1 Transmitter
19
ADC – ADC Convert Done
20
NVM - NVM Write Complete
21
SI2C – I2C™ Slave Interrupt
22
MI2C – I2C Master Interrupt
23
Input Change Interrupt
24
INT1 – External Interrupt 1
25
IC7 – Input Capture 7
26
IC8 – Input Capture 8
27
OC3 – Output Compare 3
28
OC4 – Output Compare 4
29
T4 – Timer4
30
T5 – Timer5
31
INT2 – External Interrupt 2
32
U2RX – UART2 Receiver
33
U2TX – UART2 Transmitter
34
SPI2
35
C1 – Combined IRQ for CAN1
36
IC3 – Input Capture 3
37
IC4 – Input Capture 4
38
IC5 – Input Capture 5
39
IC6 – Input Capture 6
40
OC5 – Output Compare 5
41
OC6 – Output Compare 6
42
OC7 – Output Compare 7
43
OC8 – Output Compare 8
44
INT3 – External Interrupt 3
45
INT4 - External Interrupt 4
46
C2 – Combined IRQ for CAN2
47
PWM – PWM Period Match
48
QEI – QEI Interrupt
49
Reserved
50
Reserved
51
FLTA – PWM Fault A
52
FLTB – PWM Fault B
53-61 Reserved
Lowest Natural Order Priority
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
5.2
Reset Sequence
A Reset is not a true exception because the interrupt
controller is not involved in the Reset process. The processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory location, immediately followed by the address target for the
GOTO instruction. The processor executes the GOTO to
the specified address and then begins operation at the
specified target (start) address.
5.2.1
5.3
Traps
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority, as shown in Figure 5-1. They
are intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
Note:
RESET SOURCES
There are 6 sources of error which will cause a device
Reset.
• Watchdog Time-out:
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
• Uninitialized W Register Trap:
An attempt to use an uninitialized W register as
an Address Pointer will cause a Reset.
• Illegal Instruction Trap:
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
• Brown-out Reset (BOR):
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
• Trap Lockout:
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
If the user does not intend to take corrective action in the event of a trap error
condition, these vectors must be loaded
with the address of a default handler that
simply contains the RESET instruction. If,
on the other hand, one of the vectors
containing an invalid address is called, an
address error trap is generated.
Note that many of these trap conditions can only be
detected when they occur. Consequently, the questionable instruction is allowed to complete prior to trap
exception processing. If the user chooses to recover
from the error, the result of the erroneous action that
caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: Level 8
through Level 15, which means that IPL3 is always set
during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL bits to a value of ‘0111’ (Level 7), then all
interrupts are disabled, but traps can still be processed.
5.3.1
TRAP SOURCES
The following traps are provided with increasing priority. However, since all traps can be nested, priority has
little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
1.
2.
3.
4.
© 2011 Microchip Technology Inc.
Should an attempt be made to divide by zero,
the divide operation will be aborted on a cycle
boundary and the trap taken.
If enabled, a math error trap will be taken when
an arithmetic operation on either Accumulator A
or B causes an overflow from bit 31 and the
Accumulator Guard bits are not utilized.
If enabled, a math error trap will be taken when
an arithmetic operation on either Accumulator A
or B causes a catastrophic overflow from bit 39
and all saturation is disabled.
If the shift amount specified in a shift instruction
is greater than the maximum allowed shift
amount, a trap will occur.
DS70150E-page 43
dsPIC30F6010A/6015
Address Error Trap:
5.3.2
This trap is initiated when any of the following
circumstances occurs:
It is possible that multiple traps can become active
within the same cycle (e.g., a misaligned word stack
write to an overflowed address). In such a case, the
fixed priority shown in Figure 5-2 is implemented,
which may require the user to check if other traps are
pending in order to completely correct the Fault.
1.
2.
3.
4.
A misaligned data word access is attempted.
A data fetch from our unimplemented data
memory location is attempted.
A data access of an unimplemented program
memory location is attempted.
An instruction fetch from vector space is
attempted.
Note:
5.
6.
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
Execution of a “BRA #literal” instruction or a
“GOTO #literal” instruction, where literal
is an unimplemented program memory address.
Executing instructions after modifying the PC to
point to unimplemented program memory
addresses. The PC may be modified by loading
a value into the stack and executing a RETURN
instruction.
Stack Error Trap:
HARD AND SOFT TRAPS
‘Soft’ traps include exceptions of priority level 8 through
level 11, inclusive. The arithmetic error trap (level 11)
falls into this category of traps.
‘Hard’ traps include exceptions of priority level 12
through level 15, inclusive. The address error (level
12), stack error (level 13) and oscillator error (level 14)
traps fall into this category.
Each hard trap that occurs must be Acknowledged
before code execution of any type may continue. If a
lower priority hard trap occurs while a higher priority
trap is pending, Acknowledged, or is being processed,
a hard trap conflict will occur.
The device is automatically reset in a hard trap conflict
condition. The TRAPR Status bit (RCON) is set
when the Reset occurs, so that the condition may be
detected in software.
FIGURE 5-1:
This trap is initiated under the following conditions:
2.
The Stack Pointer is loaded with a value which
is greater than the (user programmable) limit
value written into the SPLIM register (stack
overflow).
The Stack Pointer is loaded with a value which
is less than 0x0800 (simple stack underflow).
Oscillator Fail Trap:
Reset – GOTO Instruction
Reset – GOTO Address
Decreasing
Priority
1.
TRAP VECTORS
IVT
This trap is initiated if the external oscillator fails and
operation becomes reliant on an internal RC backup.
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
Interrupt 1 Vector
0x000000
0x000002
0x000004
0x000014
Interrupt 52 Vector
Interrupt 53 Vector
AIVT
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Stack Error Trap Vector
Address Error Trap Vector
Math Error Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
Interrupt 0 Vector
0x00007E
0x000080
0x000082
0x000084
0x000094
Interrupt 1 Vector
Interrupt 52 Vector
Interrupt 53 Vector
DS70150E-page 44
0x0000FE
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
5.4
Interrupt Sequence
5.5
All interrupt event flags are sampled in the beginning of
each instruction cycle by the IFSx registers. A pending
Interrupt Request (IRQ) is indicated by the flag bit
being equal to a ‘1’ in an IFSx register. The IRQ will
cause an interrupt to occur if the corresponding bit in
the Interrupt Enable register (IECx) is set. For the
remainder of the instruction cycle, the priorities of all
pending interrupt requests are evaluated.
If there is a pending IRQ with a priority level greater
than the current processor priority level in the IPL bits,
the processor will be interrupted.
The processor then stacks the current program counter
and the low byte of the processor STATUS register
(SRL), as shown in Figure 5-2. The low byte of the
STATUS register contains the processor priority level at
the time prior to the beginning of the interrupt cycle.
The processor then loads the priority level for this interrupt into the STATUS register. This action will disable
all lower priority interrupts until the completion of the
Interrupt Service Routine.
FIGURE 5-2:
INTERRUPT STACK
FRAME
Stack Grows Towards
Higher Address
0x0000 15
0
PC
SRL IPL3 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
Note 1: The user can always lower the priority
level by writing a new value into SR. The
Interrupt Service Routine must clear the
interrupt flag bits in the IFSx register
before lowering the processor interrupt
priority in order to avoid recursive
interrupts.
2: The IPL3 bit (CORCON) is always
clear when interrupts are being processed. It is set only during execution of
traps.
The RETFIE (Return from Interrupt) instruction will
unstack the program counter and STATUS registers to
return the processor to its state prior to the interrupt
sequence.
© 2011 Microchip Technology Inc.
Alternate Vector Table
In program memory, the Interrupt Vector Table (IVT) is
followed by the Alternate Interrupt Vector Table (AIVT),
as shown in Figure 5-1. Access to the Alternate Vector
Table is provided by the ALTIVT bit in the INTCON2
register. If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of
the default vectors. The alternate vectors are organized
in the same manner as the default vectors. The AIVT
supports emulation and debugging efforts by providing
a means to switch between an application and a
support environment, without requiring the interrupt
vectors to be reprogrammed. This feature also enables
switching between applications for evaluation of
different software algorithms at run time.
If the AIVT is not required, the program memory allocated to the AIVT may be used for other purposes.
AIVT is not a protected section and may be freely
programmed by the user.
5.6
Fast Context Saving
A context saving option is available using shadow registers. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instructions. Users must save the key registers in software
during a lower priority interrupt, if the higher priority ISR
uses fast context saving.
5.7
External Interrupt Requests
The interrupt controller supports five external interrupt
request signals, INT0-INT4. These inputs are edge
sensitive; they require a low-to-high or a high-to-low
transition to generate an interrupt request. The
INTCON2 register has five bits, INT0EP-INT4EP, that
select the polarity of the edge detection circuitry.
5.8
Wake-up from Sleep and Idle
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor will wake-up from Sleep or
Idle and begin execution of the Interrupt Service
Routine (ISR) needed to process the interrupt request.
DS70150E-page 45
SFR
Name
ADR
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6010A(1)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
INTCON1 0080
NSTDIS
—
—
—
—
OVATE
OVBTE
COVTE
—
—
—
MATHERR
INTCON2 0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
Bit 3
Bit 2
Bit 1
ADDRERR STKERR OSCFAIL
INT3EP
INT2EP
INT1EP
Bit 0
Reset State
—
0000 0000 0000 0000
INT0EP 0000 0000 0000 0000
IFS0
0084
CNIF
MI2CIF
SI2CIF
NVMIF
ADIF
U1TXIF U1RXIF
SPI1IF
T3IF
T2IF
OC2IF
IC2IF
T1IF
OC1IF
IC1IF
INT0IF
0000 0000 0000 0000
IFS1
0086
IC6IF
IC5IF
IC4IF
IC3IF
C1IF
SPI2IF
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
IC8IF
IC7IF
INT1IF
0000 0000 0000 0000
IFS2
0088
—
—
—
FLTBIF
FLTAIF
—
—
QEIIF
PWMIF
C2IF
INT4IF
INT3IF
OC8IF
OC7IF
OC6IF
OC5IF
0000 0000 0000 0000
IEC0
008C
CNIE
MI2CIE
SI2CIE
NVMIE
ADIE
U1TXIE U1RXIE
SPI1IE
T3IE
T2IE
OC2IE
IC2IE
T1IE
OC1IE
IC1IE
INT0IE
0000 0000 0000 0000
IEC1
008E
IC6IE
IC5IE
IC4IE
IC3IE
C1IE
SPI2IE
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
IC8IE
IC7IE
INT1IE
0000 0000 0000 0000
IEC2
0090
—
—
—
—
—
QEIIE
PWMIE
C2IE
INT4IE
INT3IE
OC8IE
OC7IE
OC6IE
OC5IE
0000 0000 0000 0000
FLTBIE FLTAIE
IPC0
0094
—
T1IP
—
OC1IP
—
IC1IP
—
INT0IP
0100 0100 0100 0100
IPC1
0096
—
T31P
—
T2IP
—
OC2IP
—
IC2IP
0100 0100 0100 0100
IPC2
0098
—
ADIP
—
U1TXIP
—
U1RXIP
—
SPI1IP
0100 0100 0100 0100
IPC3
009A
—
CNIP
—
MI2CIP
—
SI2CIP
—
NVMIP
0100 0100 0100 0100
IPC4
009C
—
OC3IP
—
IC8IP
—
IC7IP
—
INT1IP
0100 0100 0100 0100
IPC5
009E
—
INT2IP
—
T5IP
—
T4IP
—
OC4IP
0100 0100 0100 0100
IPC6
00A0
—
C1IP
—
SPI2IP
—
U2TXIP
—
U2RXIP
0100 0100 0100 0100
IPC7
00A2
—
IC6IP
—
IC5IP
—
IC4IP
—
IC3IP
0100 0100 0100 0100
IPC8
00A4
—
OC8IP
—
OC7IP
—
OC6IP
—
OC5IP
0100 0100 0100 0100
IPC9
00A6
—
PWMIP
—
C2IP
—
INT41IP
—
INT3IP
0100 0100 0100 0100
IPC10
00A8
—
FLTAIP
—
—
—
—
—
—
—
—
—
QEIIP
0100 0000 0000 0000
IPC11
00AA
—
—
—
—
—
—
—
—
—
—
FLTBIP
0000 0000 0000 0100
—
—
—
INTTREG 00B0
—
—
—
—
ILR
—
—
Legend:
— = unimplemented bit, read as ‘0’
Note 1:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
VECNUM
0000 0000 0000 0000
dsPIC30F6010A/6015
DS70150E-page 46
TABLE 5-2:
© 2011 Microchip Technology Inc.
© 2011 Microchip Technology Inc.
TABLE 5-3:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC30F6015(1)
ADR
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
INTCON1
0080
NSTDIS
—
—
—
—
OVATE
OVBTE
COVTE
—
—
—
MATHERR
INTCON2
0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP 0000 0000 0000 0000
IFS0
0084
CNIF
MI2CIF
SI2CIF
NVMIF
ADIF
U1TXIF U1RXIF
SPI1IF
T3IF
T2IF
OC2IF
IC2IF
T1IF
OC1IF
IC1IF
INT0IF 0000 0000 0000 0000
IFS1
0086
IC6IF
IC5IF
IC4IF
IC3IF
C1IF
SPI2IF
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
IC8IF
IC7IF
INT1IF 0000 0000 0000 0000
IFS2
0088
—
—
—
FLTBIF
FLTAIF
—
—
QEIIF
PWMIF
—
INT4IF
INT3IF
OC8IF
OC7IF
OC6IF
OC5IF 0000 0000 0000 0000
IEC0
008C
CNIE
MI2CIE
SI2CIE
NVMIE
ADIE
U1TXIE U1RXIE
SPI1IE
T3IE
T2IE
OC2IE
IC2IE
T1IE
OC1IE
IC1IE
INT0IE 0000 0000 0000 0000
IEC1
008E
IC6IE
IC5IE
IC4IE
IC3IE
C1IE
SPI2IE
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
IC8IE
IC7IE
INT1IE 0000 0000 0000 0000
IEC2
0090
—
—
—
—
—
QEIIE
PWMIE
—
INT4IE
INT3IE
OC8IE
OC7IE
OC6IE
OC5IE 0000 0000 0000 0000
IPC0
0094
—
T1IP
—
OC1IP
—
IC1IP
—
INT0IP
0100 0100 0100 0100
IPC1
0096
—
T31P
—
T2IP
—
OC2IP
—
IC2IP
0100 0100 0100 0100
IPC2
0098
—
ADIP
—
U1TXIP
—
U1RXIP
—
SPI1IP
0100 0100 0100 0100
IPC3
009A
—
CNIP
—
MI2CIP
—
SI2CIP
—
NVMIP
0100 0100 0100 0100
IPC4
009C
—
OC3IP
—
IC8IP
—
IC7IP
—
INT1IP
0100 0100 0100 0100
IPC5
009E
—
INT2IP
—
T5IP
—
T4IP
—
OC4IP
0100 0100 0100 0100
IPC6
00A0
—
C1IP
—
SPI2IP
—
U2TXIP
—
U2RXIP
0100 0100 0100 0100
IPC7
00A2
—
IC6IP
—
IC5IP
—
IC4IP
—
IC3IP
0100 0100 0100 0100
IPC8
00A4
—
OC8IP
—
OC7IP
—
OC6IP
—
OC5IP
0100 0100 0100 0100
IPC9
00A6
—
PWMIP
—
—
—
—
—
INT41IP
—
INT3IP
0100 0000 0100 0100
IPC10
00A8
—
FLTAIP
—
—
—
—
—
—
—
—
—
QEIIP
0100 0000 0000 0000
IPC11
00AA
—
—
—
—
—
—
—
—
—
—
FLTBIP
0000 0000 0000 0100
—
—
FLTBIE FLTAIE
—
INTTREG 00B0
—
—
—
—
ILR
—
—
Legend:
— = unimplemented bit, read as ‘0’
Note 1:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Bit 3
Bit 2
Bit 1
ADDRERR STKERR OSCFAIL
VECNUM
Bit 0
Reset State
—
0000 0000 0000 0000
0000 0000 0000 0000
DS70150E-page 47
dsPIC30F6010A/6015
SFR
Name
dsPIC30F6010A/6015
NOTES:
DS70150E-page 48
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
6.0
FLASH PROGRAM MEMORY
Note:
6.2
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals, register descriptions and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC Programmer’s
Reference
Manual”
(DS70157).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions.
With RTSP, the user may erase program memory,
32 instructions (96 bytes) at a time and can write
program memory data, 32 instructions (96 bytes) at a
time.
6.3
6.1
Table Instruction Operation Summary
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
Word or Byte mode.
The dsPIC30F family of devices contains internal
program Flash memory for executing user code. There
are two methods by which the user can program this
memory:
1.
2.
Run-Time Self-Programming
(RTSP)
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can access program memory in Word or
Byte mode.
In-Circuit Serial Programming™ (ICSP™)
Run-Time Self-Programming (RTSP)
A 24-bit program memory address is formed using
bits of the TBLPAG register and the Effective
Address (EA) from a W register specified in the table
instruction, as shown in Figure 6-1.
In-Circuit Serial Programming
(ICSP)
dsPIC30F devices can be serially programmed while in
the end application circuit. This is simply done with two
lines for Programming Clock and Programming Data
(which are named PGC and PGD, respectively), and
three other lines for Power (VDD), Ground (VSS) and
Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 6-1:
ADDRESSING FOR TABLE AND NVM REGISTERS
24 bits
Using
Program
Counter
Program Counter
0
0
NVMADR Reg EA
Using
NVMADR
Addressing
1/0
NVMADRU Reg
8 bits
16 bits
Working Reg EA
Using
Table
Instruction
User/Configuration
Space Select
© 2011 Microchip Technology Inc.
1/0
TBLPAG Reg
8 bits
16 bits
24-bit EA
Byte
Select
DS70150E-page 49
dsPIC30F6010A/6015
6.4
RTSP Operation
The dsPIC30F Flash program memory is organized
into rows and panels. Each row consists of 32 instructions, or 96 bytes. Each panel consists of 128 rows, or
4K x 24 instructions. RTSP allows the user to erase one
row (32 instructions) at a time and to program
32 instructions at one time.
Each panel of program memory contains write latches
that hold 32 instructions of programming data. Prior to
the actual programming operation, the write data must
be loaded into the panel write latches. The data to be
programmed into the panel is loaded in sequential
order into the write latches; instruction 0, instruction 1,
etc. The addresses loaded must always be from a 32
address boundary.
6.5
RTSP Control Registers
The four SFRs used to read and write the program
Flash memory are:
•
•
•
•
NVMCON
NVMADR
NVMADRU
NVMKEY
6.5.1
NVMCON REGISTER
The NVMCON register controls which blocks are to be
erased, which memory type is to be programmed and
start of the programming cycle.
6.5.2
NVMADR REGISTER
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the write latches. Programming is performed by
setting the special bits in the NVMCON register. 32
TBLWTL and 32 TBLWTH instructions are required to
load the 32 instructions.
The NVMADR register is used to hold the lower two
bytes of the Effective Address. The NVMADR register
captures the EA of the last table instruction that
has been executed and selects the row to write.
All of the table write operations are single-word writes
(2 instruction cycles), because only the table latches
are written.
The NVMADRU register is used to hold the upper byte
of the Effective Address. The NVMADRU register captures the EA of the last table instruction that
has been executed.
After the latches are written, a programming operation
needs to be initiated to program the data.
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
6.5.3
6.5.4
NVMKEY REGISTER
NVMKEY is a write-only register that is used for write
protection. To start a programming or an erase
sequence, the user must consecutively write 0x55 and
0xAA to the NVMKEY register. Refer to Section 6.6
“Programming Operations” for further details.
Note:
DS70150E-page 50
NVMADRU REGISTER
The user can also directly write to the
NVMADR and NVMADRU registers to
specify a program memory address for
erasing or programming.
© 2011 Microchip Technology Inc.
dsPIC30F6010A/6015
6.6
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. A programming operation is nominally 2 msec in
duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON)
starts the operation, and the WR bit is automatically
cleared when the operation is finished.
6.6.1
4.
5.
PROGRAMMING ALGORITHM FOR
PROGRAM FLASH
The user can erase or program one row of program
Flash memory at a time. The general process is:
1.
2.
3.
Read one row of program Flash (32 instruction
words) and store into data RAM as a data
“image”.
Update the data image with the desired new
data.
Erase program Flash row.
a) Set up NVMCON register for multi-word,
program Flash, erase, and set WREN bit.
b) Write address of row to be erased into
NVMADRU/NVMDR.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit. This will begin erase cycle.
f) CPU will stall for the duration of the erase
cycle.
g) The WR bit is cleared when erase cycle
ends.
EXAMPLE 6-1:
6.
Write 32 instruction words of data from data
RAM “image” into the program Flash write
latches.
Program 32 instruction words into program
Flash.
a) Set up NVMCON register for multi-word,
program Flash, program, and set WREN
bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. This will begin program
cycle.
e) CPU will stall for duration of the program
cycle.
f) The WR bit is cleared by the hardware
when program cycle ends.
Repeat steps 1 through 5 as needed to program
desired amount of program Flash memory.
6.6.2
ERASING A ROW OF PROGRAM
MEMORY
Example 6-1 shows a code sequence that can be used
to erase a row (32 instructions) of program memory.
ERASING A ROW OF PROGRAM MEMORY
; Setup NVMCON for erase operation, multi word
; program memory selected, and writes enabled
MOV
#0x4041,W0
;
MOV
W0,NVMCON
;
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR),W0
;
MOV
W0,NVMADRU
;
MOV
#tbloffset(PROG_ADDR),W0
;
MOV
W0, NVMADR
;
DISI
#5
;
;
MOV
#0x55,W0
MOV
W0,NVMKEY
;
MOV
#0xAA,W1
;
MOV
W1,NVMKEY
;
BSET
NVMCON,#WR
;
NOP
;
NOP
;
© 2011 Microchip Technology Inc.
write
Init NVMCON SFR
Initialize PM Page Boundary SFR
Intialize in-page EA[15:0] pointer
Intialize NVMADR SFR
Block all interrupts with priority
