dsPIC33EPXXXGM3XX/6XX/7XX
16-Bit Digital Signal Controllers with High-Speed PWM,
Op Amps and Advanced Analog Features
Operating Conditions
Timers/Output Compare/Input Capture
• 3.0V to 3.6V, -40°C to +85°C, up to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, up to 60 MIPS
• 21 General Purpose Timers:
- Nine 16-bit and up to four 32-bit timers/counters
- Eight output capture modules configurable as
timers/counters
- PTG module with two configurable timers/counters
- Two 32-bit Quadrature Encoder Interface (QEI)
modules configurable as a timer/counter
• Eight Input Capture modules
• Peripheral Pin Select (PPS) to allow Function Remap
• Peripheral Trigger Generator (PTG) for Scheduling
Complex Sequences
Core: 16-Bit dsPIC33E CPU
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Clock Management
•
•
•
•
•
Internal Fast FRC Oscillator with 1% Accuracy
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
•
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Executing Optimized NOP String with Flash Fetch
Integrated Power-on Reset and Brown-out Reset
0.6 mA/MHz Dynamic Current (typical)
30 µA IPD Current (typical)
Communication Interfaces
• Four Enhanced Addressable UART modules
(17.5 Mbps):
- With support for LIN/J2602 protocols and IrDA®
• Three 3-Wire/4-Wire SPI modules (15 Mbps)
• 25 Mbps Data Rate for Dedicated SPI module
(with no PPS)
• Two I2C™ modules (up to 1 Mbps) with SMBus Support
• Two CAN modules (1 Mbps) with CAN 2.0B Support
• Programmable Cyclic Redundancy Check (CRC)
• Codec Interface module (DCI) with I2S Support
High-Speed PWM
Direct Memory Access (DMA)
• Up to 12 PWM Outputs (six generators)
• Primary Master Time Base Inputs allow Time Base
Synchronization from Internal/External Sources
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
• Supports PWM Lock, PWM Output Chopping and
Dynamic Phase Shifting
• 4-Channel DMA with User-Selectable Priority Arbitration
• Peripherals Supported by the DMA Controller include:
- UART, SPI, ADC, CAN and input capture
- Output compare and timers
Advanced Analog Features
• Two Independent ADC modules:
- Configurable as 10-bit, 1.1 Msps with
four S&H or 12-bit, 500 ksps with one S&H
- 11, 13, 18, 30 or 49 analog inputs
• Flexible and Independent ADC Trigger Sources
• Up to Four Op Amp/Comparators with Direct
Connection to the ADC module:
- Additional dedicated comparator
- Programmable references with 32 voltage points
- Programmable blanking and filtering
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
2013-2014 Microchip Technology Inc.
Input/Output
• Sink/Source 15 mA or 10 mA, Pin-Specific for
Standard VOH/VOL
• 5V Tolerant Pins
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Up to 5 mA Overvoltage Clamp Current
• Change Notice Interrupts on All I/O Pins
• PPS to allow Function Remap
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40°C to +125°C) Planned
• AEC-Q100 REVG (Grade 0, -40°C to +150°C) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Three Complex and Five Simple Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
DS70000689D-page 1
dsPIC33EPXXXGM3XX/6XX/7XX
dsPIC33EPXXXGM3XX/6XX/7XX
PRODUCT FAMILY
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1. Their pinout diagrams appear on the following
pages.
dsPIC33EPXXXGM3XX/6XX/7XX FAMILY DEVICES
dsPIC33EP128GM310
dsPIC33EP128GM710
128
16
dsPIC33EP256GM310
dsPIC33EP256GM710
256
32
dsPIC33EP512GM310
dsPIC33EP512GM710
512
48
Note
1:
2:
Packages
48
Pins
512
I/O Pins
dsPIC33EP512GM706
RTCC
dsPIC33EP512GM306
PMP
32
PTG
256
CTMU
dsPIC33EP256GM706
Op Amps/Comparators
dsPIC33EP256GM306
ADC
16
10-Bit/12-Bit ADC (Channels)
128
CRC Generator
dsPIC33EP128GM306
dsPIC33EP128GM706
I2C™
48
External Interrupts(2)
512
DCI
dsPIC33EP512GM604
SPI(1)
dsPIC33EP512GM304
UART
32
QEI
256
Output Compare
dsPIC33EP256GM604
Motor Control PWM (Channels)
dsPIC33EP256GM304
Input Capture
16
16-Bit/32-Bit Timers
dsPIC33EP128GM304
CAN
RAM (Kbytes)
128
Device
dsPIC33EP128GM604
Remappable Peripherals
Program Flash Memory (Kbytes)
TABLE 1:
9/4
8
8
12
2
4
3
1
5
2
1
2
18
4/5
1
Yes
No
No
35
44
TQFP,
QFN
9/4
8
8
12
2
4
3
1
5
2
1
2
30
4/5
1
Yes Yes Yes
53
64
TQFP,
QFN
9/4
8
8
12
2
4
3
1
5
2
1
2
49
4/5
1
Yes Yes Yes
85
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
100/ TQFP,
121 TFBGA
0
2
Only SPI2 and SPI3 are remappable.
INT0 is not remappable.
DS70000689D-page 2
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
Pin Diagrams
= Pins are up to 5V tolerant
TCK/AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
VSS
AN31/CVREF2O/SCL1/RPI53/RC5
AN30/SDA1/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/ASDA1/SDI1/RPI25/RA9
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP(1,2)
TMS/OA5IN-/AN27/C5IN1-/RP41/RB9
1
33
FLT32/SCL2/RP36/RB4
RP54/PWM6H/RC6
2
32
SDA2/RPI24/RA8
RP55/PWM6L/RC7
3
31
OSC2/CLKO/RPI19/RA3
RP56/PWM5H/RC8
4
30
AN32/OSC1/CLKI/RPI18/RA2
RP57/PWM5L/RC9
5
29
VSS
VSS
6
28
VDD
dsPIC33EPXXXGM304/604
Note 1:
2:
18
19
20
21
22
OA2OUT/AN0/C2IN4-/C5IN2-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/VREF-/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
MCLR
23
17
11
AVDD
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM2L/CTPLS/RB13
16
24
AVSS
10
15
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/OCFB/RC0
RPI44/PWM2H/RB12
RPI47/PWM1L/T5CK/T6CK/RB15
25
14
9
RPI46/PWM1H/T3CK/T7CK/RB14
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
RP43/PWM3L/RB11
13
OA4IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
26
12
27
8
TDI/PWM4L/RA7
7
TDO/PWM4H/RA10
VCAP
RP42/PWM3H/RB10
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral
Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
2013-2014 Microchip Technology Inc.
DS70000689D-page 3
dsPIC33EPXXXGM3XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
AN28/ASDA1/SDI1/RPI25/RA9
AN29/SCK1/RPI51/RC3
AN30/SDA1/RPI52/RC4
AN31/CVREF2O/SCL1/RPI53/RC5
VSS
VDD
PGED2/ASDA2/RP37/RB5
PGEC2/ASCL2/RP38/RB6
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
TCK/AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
44-Pin QFN(1,2,3)
44 43 42 41 40 39 38 37 36 35 34
TMS/OA5IN-/AN27/C5IN1-/RP41/RB9
1
33
FLT32/SCL2/RP36/RB4
RP54/PWM6H/RC6
2
32
SDA2/RPI24/RA8
RP55/PWM6L/RC7
3
31
OSC2/CLKO/RPI19/RA3
RP56/PWM5H/RC8
4
30
AN32/OSC1/CLKI/RPI18/RA2
RP57/PWM5L/RC9
5
29
VSS
VSS
6
28
VDD
VCAP
7
27
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
RP42/PWM3H/RB10
8
26
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
RP43/PWM3L/RB11
9
25
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/OCFB/RC0
RPI44/PWM2H/RB12
10
24
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM2L/CTPLS/RB13
11
23
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
dsPIC33EPXXXGM304/604
Note 1:
2:
3:
PGEC3/VREF+/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
PGED3/VREF-/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
OA2IN+/AN1/C2IN1+/RPI17/RA1
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
MCLR
AVDD
AVSS
RPI47/PWM1L/T5CK/T6CK/RB15
RPI46/PWM1H/T3CK/T7CK/RB14
TDI/PWM4L/RA7
TDO/PWM4H/RA10
12 13 14 15 16 17 18 19 20 21 22
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral
Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS70000689D-page 4
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
50
49
51
52
53
54
56
55
57
58
59
60
62
61
1
48
47
2
3
4
46
45
44
5
6
7
8
43
42
41
dsPIC33EP128GM306/706
dsPIC33EP256GM306/706
dsPIC33EP512GM306/706
9
10
11
12
13
14
15
16
40
39
38
37
36
35
32
31
30
29
28
27
26
25
24
23
22
21
20
19
TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8
SOSCI/RPI61/RC13
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN48/CVREF2O/RPI58/PMCS1/RC10
PGEC2/ASCL2/RP38/PMCS2/RB6
PGED2/ASDA2/RP37/RB5
RPI72/RD8
VSS
OSC2/CLKO/RPI63/RC15
AN49/OSC1/CLKI/RPI60/RC12
VDD
AN31/SCL1/RPI53/RC5
AN30/SDA1/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RTCC/RB3
AVDD
AVSS
OA3OUT/AN6/C3IN4-/C4IN1+/RP48/OCFB/RC0
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-/U1CTS/FLT4/PMA12/RC11
VSS
VDD
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/PMA11/RE12
AN13/C3IN2-/U2CTS/FLT6/PMA10/RE13
AN14/RPI94/FLT7/PMA1/RE14
AN15/RPI95/FLT8/PMA0/RE15
SDA2/RPI24/PMA9/RA8
FLT32/SCL2/RP36/PMA8/RB4
18
34
33
17
TDI/PWM4L/PMD5/RA7
RPI46/PWM1H/T3CK/T7CK/PMD6/RB14
RPI47/PWM1L/T5CK/T6CK/PMD7/RB15
AN19/RP118/PMA5/RG6
AN18/ASCL1/RPI119/PMA4/RG7
AN17/ASDA1/RP120/PMA3/RG8
MCLR
AN16/RPI121/PMA2/RG9
VSS
VDD
AN10/RPI28/RA12
AN9/RPI27/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/VREF-/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
63
64
TDO/PWM4H/PMD4/RA10
RPI45/PWM2L/CTPLS/PMD3/RB13
RPI44/PWM2H/PMD2/RB12
RP43/PWM3L/PMD1/RB11
RP42/PWM3H/PMD0/RB10
RP97/RF1
RPI96/RF0
VDD
VCAP
RP57/PWM5L/RC9
RP70/RD6
RP69/PMRD/RD5
RP56/PWM5H/PMWR/RC8
RP55/PWM6L/PMBE/RC7
RP54/PWM6H/RC6
TMS/OA5IN-/AN27/C5IN4-/RP41/RB9
64-Pin TQFP(1,2,3)
Note 1:
2:
3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral
Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
This pin is not available as an input when OPMODE (CMxCON) = 1.
2013-2014 Microchip Technology Inc.
DS70000689D-page 5
dsPIC33EPXXXGM3XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
2:
3:
4:
49
50
RP56/PWM5H/PMWR/RC8
RP55/PWM6L/PMBE/RC7
RP54/PWM6H/RC6
TMS/OA5IN-/AN27/C5IN1-/RP41/RB9
52
51
53
54
55
VDD
VCAP
RP57/PWM5L/RC9
RP70/RD6
RP69/PMRD/RD5
57
56
RP97/RF1
RPI96/RF0
59
58
RP42/PWM3H/PMD0/RB10
60
48
47
2
3
46
4
5
6
7
45
44
43
42
41
40
39
38
37
dsPIC33EP128GM306/706
dsPIC33EP256GM306/706
dsPIC33EP512GM306/706
8
9
10
11
12
13
14
15
16
36
35
32
31
TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8
SOSCI/RPI61/RC13
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN48/CVREF2O/RPI58/PMCS1/RC10
PGEC2/ASCL2/RP38/PMCS2/RB6
PGED2/ASDA2/RP37/RB5
RPI72/RD8
VSS
OSC2/CLKO/RPI63/RC15
AN49/OSC1/CLKI/RPI60/RC12
VDD
AN31/SCL1/RPI53/RC5
AN30/SDA1/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
SDA2/RPI24/PMA9/RA8
FLT32/SCL2/RP36/PMA8/RB4
30
29
28
AN13/C3IN2-/U2CTS/FLT6/PMA10/RE13
AN14/RPI94/FLT7/PMA1/RE14
AN15/RPI95/FLT8/PMA0/RE15
27
26
25
24
AN11/C1IN2-/U1CTS/FLT4/PMA12/RC11
VSS
VDD
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/PMA11/RE12
23
22
21
20
AVSS
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/OCFB/RC0
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
18
19
34
33
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RTCC/RB3
AVDD
Note 1:
61
TDO/PWM4H/PMD4/RA10
RPI45/PWM2L/CTPLS/PMD3/RB13
RPI44/PWM2H/PMD2/RB12
RP43/PWM3L/PMD1/RB11
62
1
17
TDI/PWM4L/PMD5/RA7
RPI46/PWM1H/T3CK/T7CK/PMD6/RB14
RPI47/PWM1L/T5CK/T6CK/PMD7/RB15
AN19/RP118/PMA5/RG6
AN18/ASCL1/RPI119/PMA4/RG7
AN17/ASDA1/RP120/PMA3/RG8
MCLR
AN16/RPI121/PMA2/RG9
VSS
VDD
AN10/RPI28/RA12
AN9/RPI27/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/VREF-/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
64
63
64-Pin QFN(1,2,3,4)
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral
Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
This pin is not available as an input when OPMODE (CMxCON) = 1.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS70000689D-page 6
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TDO/PWM4H/PMD4/RA10
RPI45/PWM2L/CTPLS/PMD3/RB13
RPI44/PWM2H/PMD2/RB12
RP125/RG13
RPI124/RG12
RP126/RG14
RP43/PWM3L/PMD1/RB11
RP42/PWM3H/PMD0/RB10
RF7
RF6
RPI112/RG0
RP113/RG1
RP97/RF1
RPI96/RF0
VDD
VCAP
RP57/RC9
RP70/RD6
RP69/PMRD/RD5
RP56/PMWR/RC8
RPI77/RD13
RPI76/RD12
RP55/PMBE/RC7
RP54/RC6
TMS/OA5IN-/AN27/C5IN1-/RP41/RB9
100-Pin TQFP(1,2,3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33EP128GM310/710
dsPIC33EP256GM310/710
dsPIC33EP512GM310/710
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8
SOSCI/RPI61/RC13
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN48/CVREF2O/RPI58/PMCS1/RC10
PGEC2/ASCL2/RP38/PMCS2/RB6
PGED2/ASDA2/RP37/RB5
RPI72/RD8
AN47/INT4/RA15
AN46/INT3/RA14
VSS
OSC2/CLKO/RPI63/RC15
AN49/OSC1/CLKI/RPI60/RC12
VDD
AN45/RF5
AN44/RF4
AN43/RG3
AN42/RG2
AN31/SCL1/RPI53/RC5
AN30/SDA1/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
AN41/RP81/RE1
AN40/RPI80/RE0
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RTCC/RB3
VREF-/AN33/PMA6/RF9
VREF+/AN34/PMA7/RF10
AVDD
AVSS
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/OCFB/RC0
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-/U1CTS/FLT4/PMA12/RC11
VSS
VDD
AN35/RG11
AN36/RF13
AN37/RF12
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/PMA11/RE12
AN13/C3IN2-/U2CTS/FLT6/PMA10/RE13
AN14/RPI94/FLT7/PMA1/RE14
AN15/RPI95/FLT8/PMA0/RE15
VSS
VDD
AN38/RD14
AN39/RD15
SDA2/RPI24/PMA9/RA8
FLT32/SCL2/RP36/PMA8/RB4
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN23/RP127/RG15
VDD
TDI/PWM4L/PMD5/RA7
RPI46/PWM1H/T3CK/T7CK/PMD6/RB14
RPI47/PWM1L/T5CK/T6CK/PMD7/RB15
PWM5L/RD1
PWM5H/RD2
PWM6L/T9CK/RD3
PWM6H/T8CK/RD4
AN19/RP118/PMA5/RG6
AN18/ASCL1/RPI119/PMA4/RG7
AN17/ASDA1/RP120/PMA3/RG8
MCLR
AN16/RPI121/PMA2/RG9
VSS
VDD
AN22/RG10
AN21/RE8
AN20/RE9
AN10/RPI28/RA12
AN9/RPI27/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
Note 1:
2:
3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral
Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
This pin is not available as an input when OPMODE (CMxCON) = 1.
2013-2014 Microchip Technology Inc.
DS70000689D-page 7
dsPIC33EPXXXGM3XX/6XX/7XX
Pin Diagrams (Continued)
121-Pin TFBGA(1)
= Pins are up to 5V tolerant
dsPIC33EP128GM310/710
dsPIC33EP256GM310/710
dsPIC33EP512GM310/710
A
B
C
D
E
F
G
H
J
K
L
Note 1:
1
2
3
4
5
6
7
8
9
10
11
RA10
RB13
RG13
RB10
RG0
RF1
VDD
NC
RD12
RC6
RB9
NC
RG15
RB12
RB11
RF7
RF0
VCAP
RD5
RC7
VSS
RB8
RB14
VDD
RG12
RG14
RF6
NC
RC9
RC8
NC
RC13
RC10
RD1
RB15
RA7
NC
NC
NC
RD6
RD13
RB7
NC
RB6
RD4
RD3
RG6
RD2
NC
RG1
NC
RA15
RD8
RB5
RA14
MCLR
RG8
RG9
RG7
VSS
NC
NC
VDD
RC12
VSS
RC15
RE8
RE9
RG10
NC
VDD
VSS
VSS
NC
RF5
RG3
RF4
RA12
RA11
NC
NC
NC
VDD
NC
RA9
RC3
RC5
RG2
RA0
RA1
RB3
AVDD
RC11
RG11
RE12
NC
NC
RE1
RC4
RB0
RB1
RF10
RC0
NC
RF12
RE14
VDD
RD15
RA4
RE0
RB2
RF9
AVSS
RC1
RC2
RF13
RE13
RE15
RD14
RA8
RB4
Refer to Table 2 for full pin names.
DS70000689D-page 8
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 2:
PIN NAMES: dsPIC33EP128/256/512GM310/710 DEVICES(1,2,3)
Pin #
A1
Full Pin Name
TDO/PWM4H/PMD4/RA10
Pin #
Full Pin Name
E8
AN47/INT4/RA15
A2
RPI45/PWM2L/CTPLS/PMD3/RB13
E9
RPI72/RD8
A3
RP125/RG13
E10
PGED2/ASDA2/RP37/RB5
A4
RP42/PWM3H/PMD0/RB10
E11
AN46/INT3/RA14
A5
RPI112/RG0
F1
MCLR
A6
RP97/RF1
F2
AN17/ASDA1/RP120/PMA3/RG8
A7
VDD
F3
AN16/RPI121/PMA2/RG9
A8
No Connect
F4
AN18/ASCL1/RPI119/PMA4/RG7
A9
RPI76/RD12
F5
VSS
A10
RP54/RC6
F6
No Connect
A11
TMS/OA5IN-/AN27/C5IN1-/RP41/RB9
F7
No Connect
B1
No Connect
F8
VDD
B2
AN23/RP127/RG15
F9
AN49/OSC1/CLKI/RPI60/RC12
B3
RPI44/PWM2H/PMD2/RB12
F10
VSS
B4
RP43/PWM3L/PMD1/RB11
F11
OSC2/CLKO/RPI63/RC15
B5
RF7
G1
AN21/RE8
B6
RPI96/RF0
G2
AN20/RE9
AN22/RG10
B7
VCAP
G3
B8
RP69/PMRD/RD5
G4
No Connect
B9
RP55/PMBE/RC7
G5
VDD
B10
VSS
G6
VSS
B11
TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8
G7
VSS
C1
RPI46/PWM1H/T3CK/T7CK/PMD6/RB14
G8
No Connect
C2
VDD
G9
AN45/RF5
C3
RPI124/RG12
G10
AN43/RG3
C4
RP126/RG14
G11
AN44/RF4
C5
RF6
H1
AN10/RPI28/RA12
C6
No Connect
H2
AN9/RPI27/RA11
C7
RP57/RC9
H3
No Connect
C8
RP56/PMWR/RC8
H4
No Connect
C9
No Connect
H5
No Connect
C10
SOSCI/RPI61/RC13
H6
VDD
C11
AN48/CVREF2O/RPI58/PMCS1/RC10
H7
No Connect
D1
PWM5L/RD1
H8
AN28/SDI1/RPI25/RA9
D2
RPI47/PWM1L/T5CK/T6CK/PMD7/RB15
H9
AN29/SCK1/RPI51/RC3
D3
TDI/PWM4L/PMD5/RA7
H10
AN31/SCL1/RPI53/RC5
D4
No Connect
H11
AN42/RG2
D5
No Connect
J1
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
D6
No Connect
J2
OA2IN+/AN1/C2IN3-/C2IN1+/RPI17/RA1
D7
RP70/RD6
J3
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RTCC/RB3
D8
RPI77/RD13
J4
AVDD
D9
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
J5
AN11/C1IN2-/U1CTS/FLT4/PMA12/RC11
D10
No Connect
J6
AN35/RG11
PGEC2/ASCL2/RP38/PMCS2/RB6
J7
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/PMA11/RE12
D11
Note 1:
2:
3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select (PPS)” for
available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.
The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits,
ALTI2C1 and ALTI2C2 (FPOR). See Section 30.0 “Special Features” for more information.
2013-2014 Microchip Technology Inc.
DS70000689D-page 9
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 2:
PIN NAMES: dsPIC33EP128/256/512GM310/710 DEVICES(1,2,3) (CONTINUED)
Pin #
Full Pin Name
Pin #
Full Pin Name
E1
PWM6H/T8CK/RD4
J8
No Connect
E2
PWM6L/T9CK/RD3
J9
No Connect
E3
AN19/RP118/PMA5/RG6
J10
AN41/RP81/RE1
E4
PWM5H/RD2
J11
AN30/SDA1/RPI52/RC4
E5
No Connect
K1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
E6
RP113/RG1
K2
PGEC3/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/
CTED1/RB1
VREF+/AN34/PMA7/RF10
E7
No Connect
K3
K4
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/OCFB/RC0
L3
AVSS
K5
No Connect
L4
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
K6
AN37/RF12
L5
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/
PMA13/RC2
K7
AN14/RPI94/FLT7/PMA1/RE14
L6
AN36/RF13
K8
VDD
L7
AN13/C3IN2-/U2CTS/FLT6/PMA10/RE13
K9
AN39/RD15
L8
AN15/RPI95/FLT8/PMA0/RE15
AN38/RD14
K10
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
L9
K11
AN40/RPI80/RE0
L10
SDA2/RPI24/PMA9/RA8
L1
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
L11
FLT32/SCL2/RP36/PMA8/RB4
L2
Note 1:
2:
3:
VREF-/AN33/PMA6/RF9
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select (PPS)” for
available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.
The availability of I2C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits,
ALTI2C1 and ALTI2C2 (FPOR). See Section 30.0 “Special Features” for more information.
DS70000689D-page 10
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
Table of Contents
dsPIC33EPXXXGM3XX/6XX/7XX Product Family ................................................................................................................................ 2
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 21
3.0 CPU............................................................................................................................................................................................ 27
4.0 Memory Organization ................................................................................................................................................................. 37
5.0 Flash Program Memory............................................................................................................................................................ 103
6.0 Resets ..................................................................................................................................................................................... 111
7.0 Interrupt Controller ................................................................................................................................................................... 115
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 129
9.0 Oscillator Configuration ............................................................................................................................................................ 143
10.0 Power-Saving Features............................................................................................................................................................ 153
11.0 I/O Ports ................................................................................................................................................................................... 163
12.0 Timer1 ...................................................................................................................................................................................... 211
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 213
14.0 Input Capture............................................................................................................................................................................ 219
15.0 Output Compare....................................................................................................................................................................... 223
16.0 High-Speed PWM Module........................................................................................................................................................ 229
17.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 257
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 273
19.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 281
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 289
21.0 Controller Area Network (CAN) Module (dsPIC33EPXXXGM6XX/7XX Devices Only) ........................................................... 295
22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 321
23.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 327
24.0 Data Converter Interface (DCI) Module.................................................................................................................................... 343
25.0 Peripheral Trigger Generator (PTG) Module............................................................................................................................ 349
26.0 Op Amp/Comparator Module ................................................................................................................................................... 365
27.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 383
28.0 Parallel Master Port (PMP)....................................................................................................................................................... 395
29.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 405
30.0 Special Features ...................................................................................................................................................................... 411
31.0 Instruction Set Summary .......................................................................................................................................................... 419
32.0 Development Support............................................................................................................................................................... 429
33.0 Electrical Characteristics .......................................................................................................................................................... 433
34.0 High-Temperature Electrical Characteristics............................................................................................................................ 499
35.0 Packaging Information.............................................................................................................................................................. 507
Appendix A: Revision History............................................................................................................................................................. 527
Index ................................................................................................................................................................................................. 529
The Microchip Web Site ..................................................................................................................................................................... 537
Customer Change Notification Service .............................................................................................................................................. 537
Customer Support .............................................................................................................................................................................. 537
Product Identification System ............................................................................................................................................................ 539
2013-2014 Microchip Technology Inc.
DS70000689D-page 11
dsPIC33EPXXXGM3XX/6XX/7XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS70000689D-page 12
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family Reference Manual”, which are available from the Microchip
web site (www.microchip.com). These documents
should be considered as the general reference for the
operation of a particular module or device feature.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“Introduction” (DS70573)
“CPU” (DS70359)
“Data Memory” (DS70595)
“Program Memory” (DS70613)
“Flash Programming” (DS70609)
“Interrupts” (DS70000600)
“Oscillator” (DS70580)
“Reset” (DS70602)
“Watchdog Timer and Power-Saving Modes” (DS70615)
“I/O Ports” (DS70000598)
“Timers” (DS70362)
“Input Capture” (DS70000352)
“Output Compare” (DS70005157)
“High-Speed PWM” (DS70645)
“Quadrature Encoder Interface (QEI)” (DS70601)
“Analog-to-Digital Converter (ADC)” (DS70621)
“Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)
“Serial Peripheral Interface (SPI)” (DS70005185)
“Inter-Integrated Circuit™ (I2C™)” (DS70000195)
“Data Converter Interface (DCI) Module” (DS70356)
“Enhanced Controller Area Network (ECAN™)” (DS70353)
“Direct Memory Access (DMA)” (DS70348)
“Programming and Diagnostics” (DS70608)
“Op Amp/Comparator” (DS70000357)
“32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS70346)
“Parallel Master Port (PMP)” (DS70576)
“Device Configuration” (DS70000618)
“Peripheral Trigger Generator (PTG)” (DS70669)
“Charge Time Measurement Unit (CTMU)” (DS70661)
2013-2014 Microchip Technology Inc.
DS70000689D-page 13
dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 14
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
1.0
This document contains device-specific information for
the dsPIC33EPXXXGM3XX/6XX/7XX Digital Signal
Controller (DSC) devices.
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive resource. To complement the information in this data sheet,
refer to the related section of the
“dsPIC33/PIC24
Family
Reference
Manual”, which is available from the
Microchip web site (www.microchip.com)
dsPIC33EPXXXGM3XX/6XX/7XX devices contain
extensive Digital Signal Processor (DSP) functionality
with a high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 1-1:
dsPIC33EPXXXGM3XX/6XX/7XX BLOCK DIAGRAM
PORTA
CPU
16
Refer to Figure 3-1 for CPU diagram details.
PORTB
PORTC
Power-up
Timer
OSC1/CLKI
Timing
Generation
Oscillator
Start-up
Timer
PORTD
POR/BOR
PORTE
MCLR
VDD, VSS
AVDD, AVSS
PTG
Op Amp/
Comparator
CAN1/2(1)
ADC
Input
Capture
16
Watchdog
Timer
PORTF
Output
Compare
PORTG
I2C1/2
Remappable
Pins
CTMU
QEI1/2
PWM
Timers
CRC
SPI1/2/3
UART1/2/3/4
PORTS
Peripheral Modules
Note 1:
This feature or peripheral is only available on dsPIC33EPXXXGM6XX/7XX devices.
2013-2014 Microchip Technology Inc.
DS70000689D-page 15
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin Buffer
PPS
Type Type
Description
AN0-AN49
I
Analog
No
Analog Input Channels 0-49.
CLKI
I
No
External clock source input. Always associated with OSC1 pin function.
CLKO
O
ST/
CMOS
—
No
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
No
OSC2
I/O
ST/
CMOS
—
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
I
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
O
ST/
CMOS
—
No
32.768 kHz low-power oscillator crystal output.
IC1-IC8
I
ST
Yes Input Capture Inputs 1 through 8.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Yes Output Compare Fault A input (for compare channels).
No Output Compare Fault B input (for compare channels).
Yes Output Compare 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
No
Yes
Yes
No
No
RA0-RA4, RA7-RA12,
RA14-RA15
I/O
ST
Yes PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
Yes PORTB is a bidirectional I/O port.
RC0-RC13, RC15
I/O
ST
Yes PORTC is a bidirectional I/O port.
RD1-RD6, RD8,
RD12-RD15
I/O
ST
Yes PORTD is a bidirectional I/O port.
RE0-RE1, RE8-RE9,
RE12-RE15
I/O
ST
Yes PORTE is a bidirectional I/O port.
RF0-RF1, RF4-RF7,
RF9-RF10,
RF12-RF13
I/O
ST
No
RG0-RG3,
RG6-RG15
I/O
ST
Yes PORTG is a bidirectional I/O port.
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
No
Yes
No
No
No
No
No
No
No
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
No
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
External Interrupt 3.
External Interrupt 4.
PORTF is a bidirectional I/O port.
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
Note 1: This pin is not available on all devices. For more information, see the “Pin Diagrams” section for pin
availability.
2: AVDD must be connected at all times.
DS70000689D-page 16
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
PPS
Type Type
Description
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
UART1 transmit.
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART2 Clear-to-Send.
UART2 Ready-to-Send.
UART2 receive.
UART2 transmit.
U3CTS
U3RTS
U3RX
U3TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART3 Clear-to-Send.
UART3 Ready-to-Send.
UART3 receive.
UART3 transmit.
U4CTS
U4RTS
U4RX
U4TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART4 Clear-to-Send.
UART4 Ready-to-Send.
UART4 receive.
UART4 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
No
No
No
No
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCK3
SDI3
SDO3
SS3
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI3.
SPI3 data in.
SPI3 data out.
SPI3 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
SCL2
SDA2
ASCL2
ASDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
Alternate synchronous serial clock input/output for I2C2.
Alternate synchronous serial data input/output for I2C2.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
Note 1: This pin is not available on all devices. For more information, see the “Pin Diagrams” section for pin
availability.
2: AVDD must be connected at all times.
2013-2014 Microchip Technology Inc.
DS70000689D-page 17
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Buffer
PPS
Type Type
INDX1(1)
HOME1(1)
QEA1(1)
I
I
I
ST
ST
ST
QEB1(1)
I
ST
CNTCMP1(1)
O
—
INDX2(1)
HOME2(1)
QEA2(1)
I
I
I
ST
ST
ST
QEB2(1)
I
ST
Description
Yes Quadrature Encoder Index1 pulse input.
Yes Quadrature Encoder Home1 pulse input.
Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer
external clock input in Timer mode.
Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer
external gate input in Timer mode.
Yes Quadrature Encoder Compare Output 1.
CNTCMP2(1)
O
—
Yes Quadrature Encoder Index2 Pulse input.
Yes Quadrature Encoder Home2 Pulse input.
Yes Quadrature Encoder Phase A input in QEI2 mode. Auxiliary timer
external clock input in Timer mode.
Yes Quadrature Encoder Phase B input in QEI2 mode. Auxiliary timer
external gate input in Timer mode.
Yes Quadrature Encoder Compare Output 2.
COFS
CSCK
CSDI
CSDO
I/O
I/O
I
O
ST
ST
ST
—
Yes
Yes
Yes
Yes
C1RX
C1TX
I
O
ST
—
Yes CAN1 bus receive pin.
Yes CAN1 bus transmit pin
C2RX
C2TX
I
O
ST
—
Yes CAN2 bus receive pin.
Yes CAN2 bus transmit pin
RTCC
O
—
No
Real-Time Clock and Calendar alarm output.
CVREF
O
Analog
No
Comparator Voltage Reference output.
C1IN1+, C1IN2-,
C1IN1-, C1IN3C1OUT
I
Analog
No
Comparator 1 inputs.
O
—
I
Analog
O
—
I
Analog
O
—
I
Analog
O
—
I
Analog
O
—
C2IN1+, C2IN2-,
C2IN1-, C2IN3C2OUT
C3IN1+, C3IN2-,
C2IN1-, C3IN3C3OUT
C4IN1+, C4IN2-,
C4IN1-, C4IN3C4OUT
C5IN1-, C5IN2-,
C5IN3-, C5IN4-,
C5IN1+
C5OUT
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
Yes Comparator 1 output.
No
Comparator 2 inputs.
Yes Comparator 2 output.
No
Comparator 3 inputs.
Yes Comparator 3 output.
No
Comparator 4 inputs.
Yes Comparator 4 output.
No
Comparator 5 inputs.
Yes Comparator 5 output.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
Note 1: This pin is not available on all devices. For more information, see the “Pin Diagrams” section for pin
availability.
2: AVDD must be connected at all times.
DS70000689D-page 18
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Buffer
PPS
Type Type
Description
PMA0
I/O
TTL/ST
No
PMA1
I/O
TTL/ST
No
PMA2-PMA13
PMBE
PMCS1, PMCS2
PMD0-PMD7
O
O
O
I/O
—
—
—
TTL/ST
No
No
No
No
PMRD
PMWR
O
O
—
—
No
No
Parallel Master Port Address Bit 0 input (Buffered Slave modes) and
output (Master modes).
Parallel Master Port Address Bit 1 input (Buffered Slave modes) and
output (Master modes).
Parallel Master Port Address Bits 2-13 (Demultiplexed Master modes).
Parallel Master Port Byte Enable strobe.
Parallel Master Port Chip Select 1 and 2 strobe.
Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).
Parallel Master Port Read strobe.
Parallel Master Port Write strobe.
FLT1-FLT2(1)
FLT3-FLT8(1)
FLT32
DTCMP1-DTCMP6(1)
PWM1L-PWM6L(1)
PWM1H-PWM6H(1)
SYNCI1(1), SYNCI2(1)
SYNCO1, SYNCO2(1)
I
I
I
I
O
O
I
O
ST
ST
ST
ST
—
—
ST
—
Yes
No
No
Yes
No
No
Yes
Yes
PWMx Fault Inputs 1 through 2.
PWMx Fault Inputs 3 through 8
PWMx Fault Input 32
PWMx Dead-Time Compensation Inputs 1 through 6.
PWMx Low Outputs 1 through 7.
PWMx High Outputs 1 through 7.
PWMx Synchronization Input 1.
PWMx Synchronization Outputs 1 and 2.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD(2)
P
P
No
Positive supply for analog modules. This pin must be connected at all
times.
AVSS
P
P
No
Ground reference for analog modules.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
VREF+
I
Analog
No
Analog voltage reference (high) input.
VREF-
I
Analog
No
Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
Note 1: This pin is not available on all devices. For more information, see the “Pin Diagrams” section for pin
availability.
2: AVDD must be connected at all times.
2013-2014 Microchip Technology Inc.
DS70000689D-page 19
dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 20
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24
Family
Reference
Manual”, which is available from the
Microchip web site (www.microchip.com)
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33EPXXXGM3XX/6XX/7XX
family requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, above tens of
MHz, add a second ceramic-type capacitor in
parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
Additionally, the following pins may be required:
• VREF+/VREF- pins are used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2013-2014 Microchip Technology Inc.
DS70000689D-page 21
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
VDD
The placement of this capacitor should be close to the
VCAP pin. It is recommended that the trace length not
exceeds one-quarter inch (6 mm). See Section 30.3
“On-Chip Voltage Regulator” for details.
VSS
R1
VDD
VCAP
2.4
R
The MCLR
functions:
MCLR
dsPIC33EP
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note 1:
pin
provides
two
specific
device
• Device Reset
• Device Programming and Debugging.
C
0.1 µF
Ceramic
Master Clear (MCLR) Pin
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------(i.e., ADC Conversion Rate/2)
2
1
f = ---------------------- 2 LC
2
1
L = ----------------------
2f C
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor, C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components as shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R(1)
R1(2)
2.2.1
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
MCLR
TANK CAPACITORS
CPU Logic Filter Capacitor
Connection (VCAP)
JP
dsPIC33EP
C
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR (< 1 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor greater
than 4.7 µF (10 µF is recommended), 16V connected
to ground. The type can be ceramic or tantalum. See
Section 33.0 “Electrical Characteristics” for
additional information.
DS70000689D-page 22
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
2.5
ICSP Pins
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB REAL
ICE™.
For more information on MPLAB ICD 2, ICD 3 and
REAL ICE connection requirements, refer to the
following documents that are available on the
Microchip web site:
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™ In-Circuit Emulator”
(poster) DS51749
2013-2014 Microchip Technology Inc.
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. For details, see Section 9.0
“Oscillator Configuration” for details.
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
Guard Ring
Guard Trace
Oscillator Pins
DS70000689D-page 23
dsPIC33EPXXXGM3XX/6XX/7XX
2.7
Oscillator Value Conditions on
Device Start-up
2.9
•
•
•
•
•
•
•
•
•
•
•
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 5 MHz < FIN < 13.6 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
•
•
•
•
•
•
•
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins, and drive the output to logic low.
FIGURE 2-4:
Application Examples
Induction heating
Uninterruptable Power Supplies (UPS)
DC/AC inverters
Compressor motor control
Washing machine 3-phase motor control
BLDC motor control
Automotive HVAC, cooling fans, fuel pumps
Stepper motor control
Audio and fluid sensor monitoring
Camera lens focus and stability control
Speech (playback, hands-free kits, answering
machines, VoIP)
Consumer audio
Industrial and building control (security systems
and access control)
Barcode reading
Networking: LAN switches, gateways
Data storage device management
Smart cards and smart card readers
Dual motor control
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-8.
BOOST CONVERTER IMPLEMENTATION
IPFC
VINPUT
VOUTPUT
k1
k3
ADC Channel
k2
FET
Driver
Op Amp/
Comparator
PWM
Output
ADC Channel
dsPIC33EP
DS70000689D-page 24
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 2-5:
SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
12V Input
5V Output
I5V
PWM
ADC
Channel
PWM
FET
Driver
k7
k1
k2
Op Amp/
Comparator
ADC
Channel
dsPIC33EP
FIGURE 2-6:
MULTIPHASE SYNCHRONOUS BUCK CONVERTER
3.3V Output
FET
Driver
FET
Driver
ADC
Channel
PWM
PWM
k7
PWM
PWM
12V Input
k6
PWM
PWM
FET
Driver
Op Amp/Comparator
k3
Op Amp/Comparator
k4
Op Amp/Comparator
k5
dsPIC33EP
ADC Channel
2013-2014 Microchip Technology Inc.
DS70000689D-page 25
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 2-7:
INTERLEAVED PFC
VOUT+
|VAC|
k4
VAC
k3
k1
k2
VOUT-
Op Amp/Comparator
FET
Driver
FET
Driver
PWM
Op Amp/ PWM
Comparator
Op Amp/
Comparator
ADC
Channel
dsPIC33EP
ADC Channel
FIGURE 2-8:
BEMF VOLTAGE MEASURED USING THE ADC MODULE
dsPIC33EP
BLDC
PWM3H
PWM3L
PWM2H
PWM2L
PWM1H
PWM1L
FLTx
3-Phase
Inverter
Fault
R49
R41
R34 R36
R44
AN2
R52
Demand
AN3
AN4
AN5
DS70000689D-page 26
Phase Terminal Voltage Feedback
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
3.0
CPU
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family Reference Manual”, “CPU” (DS70359), which
is available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including
significant support for digital signal processing. The
CPU has a 24-bit instruction word, with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle, effective execution rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
3.1
Registers
The dsPIC33EPXXXGM3XX/6XX/7XX devices have
sixteen 16-bit Working registers in the programmer’s
model. Each of the Working registers can act as a data,
address or address offset register. The 16th Working
register (W15) operates as a Software Stack Pointer for
interrupts and calls.
3.2
Instruction Set
The device instruction set has two classes of instructions: the MCU class of instructions and the DSP class
of instructions. These two instruction classes are
seamlessly integrated into the architecture and execute from a single execution unit. The instruction set
includes many addressing modes and was designed
for optimum C compiler efficiency.
2013-2014 Microchip Technology Inc.
3.3
Data Space Addressing
The Base Data Space can be addressed as 4K words
or 8 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operate solely through the X
memory AGU, which accesses the entire memory map
as one linear Data Space. On dsPIC33EP devices,
certain DSP instructions operate through the X and Y
AGUs to support dual operand reads, which splits the
data address space into two parts. The X and Y Data
Space boundary is device-specific.
The upper 32 Kbytes of the Data Space memory map
can optionally be mapped into Program Space at any
16K program word boundary. The program-to-Data
Space mapping feature, known as Program Space
Visibility (PSV), lets any instruction access Program
Space as if it were Data Space. Moreover, the Base
Data Space address is used in conjunction with a Data
Space Read or Write Page register (DSRPAG or
DSWPAG) to form an Extended Data Space (EDS)
address. The EDS can be addressed as 8M words or
16 Mbytes. Refer to “Data Memory” (DS70595) and
“Program Memory” (DS70613) in the “dsPIC33/
PIC24 Family Reference Manual” for more details on
EDS, PSV and table accesses.
On dsPIC33EP devices, overhead-free circular buffers
(Modulo Addressing) are supported in both X and Y
address spaces. The Modulo Addressing removes the
software boundary checking overhead for DSP
algorithms. The X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
3.4
Addressing Modes
The CPU supports these addressing modes:
•
•
•
•
•
•
Inherent (no operand)
Relative
Literal
Memory Direct
Register Direct
Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
DS70000689D-page 27
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 3-1:
dsPIC33EPXXXGM3XX/6XX/7XX CPU BLOCK DIAGRAM
X Address Bus
Y Data Bus
X Data Bus
Interrupt
Controller
PSV and Table
Data Access
24 Control Block
8
Data Latch
Y Data
RAM
X Data
RAM
Address
Latch
Address
Latch
16
Y Address Bus
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
Address Latch
16
Data Latch
24
24
16
16
16
16
16
24
16
X RAGU
X WAGU
16
Y AGU
Program Memory
EA MUX
16
Data Latch
24
16
Literal Data
IR
24
ROM Latch
16
16
16 x 16
W Register Array
16
16
16
Divide
Support
DSP
Engine
16-Bit ALU
Control Signals
to Various Blocks
Instruction
Decode and
Control
Power, Reset
and Oscillator
Modules
16
16
Ports
Peripheral
Modules
DS70000689D-page 28
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
3.5
Programmer’s Model
The programmer’s model for the dsPIC33EPXXXGM3XX/
6XX/7XX devices is shown in Figure 3-2. All registers in
the programmer’s model are memory-mapped and can be
manipulated directly by instructions. Table 3-1 lists a
description of each register.
Addressing and Bit-Reversed Addressing, and
interrupts. These registers are described in subsequent
sections of this document.
All registers associated with the programmer’s model
are memory-mapped, as shown in Table 4-1.
In addition to the registers contained in the
programmer’s model, the dsPIC33EPXXXGM3XX/
6XX/7XX devices contain control registers for Modulo
TABLE 3-1:
PROGRAMMER’S MODEL REGISTER DESCRIPTIONS
Register(s) Name
Description
W0 through W15
Working Register Array
ACCA, ACCB
40-Bit DSP Accumulators
PC
23-Bit Program Counter
SR
ALU and DSP Engine Status register
SPLIM
Stack Pointer Limit Value register
TBLPAG
Table Memory Page Address register
DSRPAG
Extended Data Space (EDS) Read Page register
DSWPAG
Extended Data Space (EDS) Write Page register
RCOUNT
REPEAT Loop Count register
DCOUNT
DO Loop Count register
(1),
DOSTARTH
DOSTARTL(1)
DO Loop Start Address register (High and Low)
DOENDH, DOENDL
DO Loop End Address register (High and Low)
CORCON
Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1:
The DOSTARTH and DOSTARTL registers are read-only.
2013-2014 Microchip Technology Inc.
DS70000689D-page 29
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 3-2:
PROGRAMMER’S MODEL
D15
D0
W0 (WREG)
W1
W2
W3
W4
W5
DSP Operand
Registers
W6
W7
Working/Address
Registers
W8
DSP Address
Registers
W9
W10
W11
W12
W13
Frame Pointer/W14
Stack Pointer/W15 0
PUSH.s and POP.s shadows
Nested DO Stack
0
SPLIM
AD15
AD31
AD39
DSP
Accumulators(1)
Stack Pointer Limit
AD0
ACCA
ACCB
PC23
PC0
0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
9
0
DSRPAG
X Data Space Read Page Address
8
0
X Data Space Write Page Address
DSWPAG
15
0
REPEAT Loop Counter
RCOUNT
15
0
DCOUNT
DO Loop Counter and Stack
23
0
0
DOSTART
0
DO Loop Start Address and Stack
23
0
DOEND
0
0
DO Loop End Address and Stack
15
0
CORCON
CPU Core Control Register
SRL
OA(1) OB(1) SA(1) SB(1) OAB(1) SAB(1) DA(1) DC IPL2 IPL1 IPL0 RA
DS70000689D-page 30
N
OV
Z
C
STATUS Register
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
3.6
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R/W-0
R/W-0
OA
OB
R/W-0
(3)
SA
R/W-0
(3)
SB
R/C-0
R/C-0
R-0
R/W-0
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(2)
R/W-0(2)
(1)
IPL1
IPL2
(1)
R/W-0(2)
IPL0
(1)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(3)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(3)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Neither Accumulator A or B has overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulator A or B is saturated or has been saturated at some time
0 = Neither Accumulator A or B is saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when the NSTDIS bit (INTCON1) = 1.
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
2013-2014 Microchip Technology Inc.
DS70000689D-page 31
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when the NSTDIS bit (INTCON1) = 1.
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
DS70000689D-page 32
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER(3)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
VAR
—
US1
US0
EDT(1)
DL2
DL1
DL0
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-0
R/C-0
R-0
R/W-0
R/W-0
SATA
SATB
SATDW
ACCSAT
IPL3(2)
SFA
RND
IF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing latency is enabled
0 = Fixed exception processing latency is enabled
bit 14
Unimplemented: Read as ‘0’
bit 13-12
US: DSP Multiply Unsigned/Signed Control bits
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
bit 11
EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at end of current loop iteration
0 = No effect
bit 10-8
DL: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
bit 7
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data Space write saturation is enabled
0 = Data Space write saturation is disabled
bit 4
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
Note 1:
2:
3:
x = Bit is unknown
This bit is always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level.
Refer to the “dsPIC33/PIC24 Family Reference Manual”, “CPU” (DS70359) for more detailed information.
2013-2014 Microchip Technology Inc.
DS70000689D-page 33
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER(3) (CONTINUED)
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
bit 2
SFA: Stack Frame Active Status bit
1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and
DSWPAG values
0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space
bit 1
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply
0 = Fractional mode is enabled for DSP multiply
Note 1:
2:
3:
This bit is always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level.
Refer to the “dsPIC33/PIC24 Family Reference Manual”, “CPU” (DS70359) for more detailed information.
DS70000689D-page 34
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dsPIC33EPXXXGM3XX/6XX/7XX
3.7
Arithmetic Logic Unit (ALU)
The dsPIC33EPXXXGM3XX/6XX/7XX family ALU is
16 bits wide and is capable of addition, subtraction, bit
shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in
nature. Depending on the operation, the ALU can affect
the values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow and
Digit Borrow bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The core CPU incorporates hardware support for both
multiplication and division. This includes a dedicated
hardware multiplier and support hardware for 16-bit
divisor division.
3.7.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed, or mixed-sign operation in
several MCU multiplication modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit signed x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.7.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
•
•
•
•
3.8
DSP Engine
The DSP engine consists of a high-speed, 17-bit x 17-bit
multiplier, a 40-bit barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine can also perform inherent accumulatorto-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
•
•
•
•
•
•
Fractional or integer DSP multiply (IF)
Signed, unsigned or mixed-sign DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for ACCA (SATA)
Automatic saturation on/off for ACCB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
TABLE 3-2:
Instruction
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
CLR
A=0
ED
A = (x – y)2
ACC Write
Back
Yes
No
y)2
No
EDAC
A = A + (x –
MAC
A = A + (x • y)
MAC
A = A + x2
No
MOVSAC
No change in A
Yes
MPY
A=x•y
No
MPY
A = x2
No
MPY.N
A=–x•y
No
MSC
A=A–x•y
Yes
Yes
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
2013-2014 Microchip Technology Inc.
DS70000689D-page 35
dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 36
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
4.0
MEMORY ORGANIZATION
Note:
4.1
The program address memory space of the
dsPIC33EPXXXGM3XX/6XX/7XX devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program
execution, or from table operation or Data Space
remapping, as described in Section 4.7 “Interfacing
Program and Data Memory Spaces”.
This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/
7XX family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Program Memory”
(DS70613), which is available from the
Microchip web site (www.microchip.com).
The dsPIC33EPXXXGM3XX/6XX/7XX family architecture features separate program and data memory
spaces and buses. This architecture also allows the
direct access of program memory from the Data Space
(DS) during code execution.
FIGURE 4-1:
Program Address Space
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD operations, which use TBLPAG to read
Device ID sections of the configuration memory space.
The program memory maps, which are presented by
device family and memory size, are shown in
Figure 4-1 through Figure 4-3.
PROGRAM MEMORY MAP FOR dsPIC33EP128GM3XX/6XX/7XX DEVICES(1)
GOTO Instruction
0x000000
Reset Address
0x000002
0x000004
0x0001FE
0x000200
User Memory Space
Interrupt Vector Table
User Program
Flash Memory
(44K instructions)
Flash Configuration
Bytes(2)
0x0155EA
0x0155EC
0x0155FE
0x015600
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
Configuration Memory Space
USERID
0x800FFE
0x801000
Reserved
Write Latches
Reserved
DEVID
Reserved
0xF9FFFE
0xFA0000
0xFA0002
0xFA0004
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
0xFFFFFE
Note 1:
2:
Memory areas are not shown to scale.
On Reset, these bits are automatically copied into the device Configuration Shadow registers.
2013-2014 Microchip Technology Inc.
DS70000689D-page 37
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 4-2:
PROGRAM MEMORY MAP FOR dsPIC33EP256GM3XX/6XX/7XX DEVICES(1)
GOTO Instruction
0x000000
Reset Address
0x000002
0x000004
0x0001FE
0x000200
User Memory Space
Interrupt Vector Table
User Program
Flash Memory
(88K instructions)
Flash Configuration
Bytes(2)
0x02ABEA
0x02ABEC
0x02ABFE
0x02AC00
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
Configuration Memory Space
USERID
0x800FFE
0x801000
Reserved
Write Latches
Reserved
DEVID
Reserved
0xF9FFFE
0xFA0000
0xFA0002
0xFA0004
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
0xFFFFFE
Note 1:
2:
Memory areas are not shown to scale.
On Reset, these bits are automatically copied into the device Configuration Shadow registers.
DS70000689D-page 38
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 4-3:
PROGRAM MEMORY MAP FOR dsPIC33EP512GM3XX/6XX/7XX DEVICES(1)
GOTO Instruction
0x000000
Reset Address
0x000002
0x000004
0x0001FE
0x000200
User Memory Space
Interrupt Vector Table
User Program
Flash Memory
(175K instructions)
Flash Configuration
Bytes(2)
0x0557EA
0x0557EC
0x0557FE
0x055800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800FF6
0x800FF8
Configuration Memory Space
USERID
Reserved
Write Latches
0xF9FFFE
0xFA0000
0xFA0002
0xFA0004
Reserved
DEVID
Reserved
Note 1:
2:
0x800FFE
0x801000
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
0xFFFFFE
Memory areas are not shown to scale.
On Reset, these bits are automatically copied into the device Configuration Shadow registers.
2013-2014 Microchip Technology Inc.
DS70000689D-page 39
dsPIC33EPXXXGM3XX/6XX/7XX
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All dsPIC33EPXXXGM3XX/6XX/7XX devices reserve
the addresses between 0x000000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user application at address, 0x000000 of Flash
memory, with the actual address for the start of code at
address, 0x000002 of Flash memory.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-4).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-4:
msw
Address
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS70000689D-page 40
A more detailed discussion of the interrupt vector
tables is provided in Section 7.1 “Interrupt Vector
Table”.
PROGRAM MEMORY ORGANIZATION
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
4.2
Data Address Space
The dsPIC33EPXXXGM3XX/6XX/7XX CPU has a
separate 16-bit wide data memory space. The Data
Space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps, which are presented by device family
and memory size, are shown in Figure 4-5 through
Figure 4-7.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the Data
Space. This arrangement gives a Base Data Space
address range of 64 Kbytes or 32K words.
The Base Data Space address is used in conjunction
with a Data Space Read or Write Page register
(DSRPAG or DSWPAG) to form an Extended Data
Space, which has a total address range of 16 Mbytes.
dsPIC33EPXXXGM3XX/6XX/7XX devices implement
up to 52 Kbytes of data memory (4 Kbytes of data
memory for Special Function Registers and up to
48 Kbytes of data memory for RAM). If an EA points to
a location outside of this area, an all zero word or byte
is returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byteaddressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
LSB; the MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3
The first 4 Kbytes of the Near Data Space, from
0x0000 to 0x0FFF, is primarily occupied by Special
Function Registers (SFRs). These are used by the
dsPIC33EPXXXGM3XX/6XX/7XX core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note:
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve Data Space memory usage
efficiency,
the
dsPIC33EPXXXGM3XX/6XX/7XX
instruction set supports both word and byte operations.
As a consequence of byte accessibility, all Effective
Address calculations are internally scaled to step
through word-aligned memory. For example, the core
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1 for
byte operations and Ws + 2 for word operations.
A data byte read, reads the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and
registers are organized as two parallel, byte-wide
entities with shared (word) address decode but
separate write lines. Data byte writes only write to the
corresponding side of the array or register that matches
the byte address.
2013-2014 Microchip Technology Inc.
SFR SPACE
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Refer to the
corresponding device tables and pinout
diagrams for device-specific information.
NEAR DATA SPACE
The 8-Kbyte area, between 0x0000 and 0x1FFF, is
referred to as the Near Data Space. Locations in this
space are directly addressable through a 13-bit absolute address field within all memory direct instructions.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a Working
register as an Address Pointer.
DS70000689D-page 41
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 4-5:
DATA MEMORY MAP FOR 128-KBYTE DEVICES
MSB
Address
MSB
4-Kbyte
SFR Space
LSB
0x0000
0x0001
SFR Space
0x0FFE
0x1000
0x0FFF
0x1001
0x1FFF
0x2001
16-Kbyte
SRAM Space
LSB
Address
16 Bits
X Data RAM (X)
0x2FFF
0x3001
8-Kbyte
Near Data
Space
0x1FFE
0x2000
0x2FFE
0x3000
Y Data RAM (Y)
0x4FFF
0x5001
0x4FFE
0x5000
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory Space
(via PSV)
0xFFFF
Note:
0xFFFE
Memory areas are not shown to scale.
DS70000689D-page 42
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 4-6:
DATA MEMORY MAP FOR 256-KBYTE DEVICES
MSB
Address
MSB
4-Kbyte
SFR Space
LSB
0x0000
0x0001
SFR Space
0x0FFE
0x1000
0x0FFF
0x1001
0x1FFF
0x2001
32-Kbyte
SRAM Space
LSB
Address
16 Bits
X Data RAM (X)
0x4FFF
0x5001
0x7FFF
0x8001
0x1FFE
0x2000
0x4FFE
0x5000
Y Data RAM (Y)
0x8FFF
0x9001
0x7FFE
0x8000
0x8FFE
0x9000
Optionally
Mapped
into Program
Memory Space
(via PSV)
X Data
Unimplemented (X)
0xFFFF
Note:
8-Kbyte
Near Data
Space
0xFFFE
Memory areas are not shown to scale.
2013-2014 Microchip Technology Inc.
DS70000689D-page 43
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 4-7:
DATA MEMORY MAP FOR 512-KBYTE DEVICES
MSB
Address
MSB
4-Kbyte
SFR Space
LSB
Address
16 Bits
LSB
0x0000
0x0001
SFR Space
0x0FFF
0x1001
0x0FFE
0x1000
0x1FFF
0x2001
0x1FFE
0x2000
8-Kbyte
Near Data
Space
X Data RAM (X)
48-Kbyte
SRAM Space
0x7FFF
0x8001
0x7FFE
0x8000
0x8FFF
0x9001
0x8FFE
0x9000
Y Data RAM (Y)
0xEFFF
0xD001
0xEFFE
0xD000
Optionally
Mapped
into Program
Memory Space
(via PSV)
X Data
Unimplemented (X)
0xFFFF
Note:
0xFFFE
Memory areas are not shown to scale.
DS70000689D-page 44
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
4.2.5
X AND Y DATA SPACES
The dsPIC33EP core has two Data Spaces: X and Y.
These Data Spaces can be considered either separate
(for some DSP instructions) or as one unified linear
address range (for MCU instructions). The Data
Spaces are accessed using two Address Generation
Units (AGUs) and separate data paths. This feature
allows certain instructions to concurrently fetch two
words from RAM, thereby enabling efficient execution
of DSP algorithms, such as Finite Impulse Response
(FIR) filtering and Fast Fourier Transform (FFT).
The X Data Space is used by all instructions and
supports all addressing modes. The X Data Space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
Data Space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
2013-2014 Microchip Technology Inc.
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y Data Spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X Data Space.
All data memory writes, including in DSP instructions,
view Data Space as combined X and Y address space.
The boundary between the X and Y Data Spaces is
device-dependent and is not user-programmable.
DS70000689D-page 45
Special Function Register Maps
TABLE 4-1:
SFR
Name
Addr.
CPU CORE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
W0
0000
W0 (WREG)
xxxx
W1
0002
W1
xxxx
W2
0004
W2
xxxx
W3
0006
W3
xxxx
W4
0008
W4
xxxx
W5
000A
W5
xxxx
xxxx
W6
000C
W6
W7
000E
W7
xxxx
W8
0010
W8
xxxx
2013-2014 Microchip Technology Inc.
W9
0012
W9
xxxx
W10
0014
W10
xxxx
W11
0016
W11
xxxx
W12
0018
W12
xxxx
W13
001A
W13
xxxx
W14
001C
W14
xxxx
W15
001E
W15
xxxx
SPLIM
0020
SPLIM
0000
ACCAL
0022
ACCAL
0000
ACCAH
0024
ACCAH
0000
ACCAU
0026
ACCBL
0028
ACCBL
0000
ACCBH
002A
ACCBH
0000
ACCBU
002C
PCL
002E
PCH
0030
—
—
—
—
—
—
DSRPAG
0032
—
—
—
—
—
—
—
—
—
—
—
—
Sign Extension of ACCA
ACCAU
Sign Extension of ACCB
ACCBU
Program Counter Low Word Register
—
—
0034
0036
REPEAT Loop Count Register
DCOUNT
0038
DCOUNT
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
Legend:
0040
Program Counter High Word Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0001
0000
0000
—
—
—
0000
—
0000
DOSTARTH
DOENDL
—
0001
Data Space Write Page Register
DOSTARTL
—
0000
0000
Data Space Read Page Register
DSWPAG
—
0000
—
—
RCOUNT
—
0000
DOENDH
0000
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 46
4.3
2013-2014 Microchip Technology Inc.
TABLE 4-1:
SFR
Name
Addr.
CPU CORE REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
IPL0
RA
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
CORCON
0044
VAR
—
US1
US0
EDT
DL1
DL2
DL0
SATA
SATB
SATDW ACCSAT
MODCON
0046
—
—
BWM3
BWM2
BWM1
BWM0
YWM3
YWM2
YWM1
XMODEN YMODEN
YWM0
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
N
OV
Z
C
IPL3
SFA
RND
IF
0020
XWM3
XWM2
XWM1
XWM0
0000
XMODSRT
0048
XMODSRT
—
0000
XMODEND
004A
XMODEND
—
0001
YMODSRT
004C
YMODSRT
—
0000
YMODEND
004E
YMODEND
—
XBREV
0050
BREN
DISICNT
0052
—
—
TBLPAG
0054
—
—
MSTRPR
Legend:
0058
XBREV
DISICNT
—
—
—
—
—
—
MSTRPR
0001
0000
0000
TBLPAG
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 47
SFR
Name
Addr.
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGM6XX/7XX DEVICES
Bit 15
INTCON1 08C0 NSTDIS
Bit 14
Bit 13
Bit 12
Bit 11
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
2013-2014 Microchip Technology Inc.
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
DMACERR
MATHERR
ADDRERR
STKERR
OSCFAIL
—
0000
INTCON2 08C2
GIE
DISI
SWTRAP
—
—
—
—
—
—
—
—
—
—
INT2EP
INT1EP
INT0EP
0000
INTCON3 08C4
—
—
—
—
—
—
—
—
—
—
DAE
DOOVR
—
—
—
—
0000
INTCON4 08C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SGHT
0000
IFS0
0800
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0802 U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
IC8IF
IC7IF
AD2IF
INT1IF
CNIF
CMPIF
MI2C1IF
SI2C1IF
0000
IFS2
0804
T6IF
—
PMPIF(1)
OC8IF
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
0806
FLT1IF
RTCCIF(2)
—
DCIIF
DCIEIF
QEI1IF
PSEMIF
C2IF
C2RXIF
INT4IF
INT3IF
T9IF
T8IF
MI2C2IF
SI2C2IF
T7IF
0000
IFS4
0808
—
—
CTMUIF
FLT4IF
QEI2IF
FLT3IF
PSESMIF
—
C2TXIF
C1TXIF
—
—
CRCIF
U2EIF
U1EIF
FLT2IF
0000
IFS5
080A PWM2IF
PWM1IF
—
—
SPI3IF
SPI3EIF
U4TXIF
U4RXIF
U4EIF
—
—
—
U3TXIF
U3RXIF
U3EIF
—
0000
IFS6
080C
—
—
—
—
—
—
—
—
—
—
—
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS8
0810 JTAGIF
ICDIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS9
0812
—
—
—
—
—
—
—
—
—
PTG3IF
PTG2IF
PTG1IF
PTG0IF
—
0000
IEC0
0820
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0822 U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
IC8IE
IC7IE
AD2IE
INT1IE
CNIE
CMPIE
MI2C1IE
SI2C1IE
0000
IEC2
0824
—
PMPIE(1)
OC8IE
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
0826
—
DCIIE
DCIEIE
QEI1IE
PSEMIE
C2IE
C2RXIE
INT4IE
INT3IE
T9IE
T8IE
MI2C2IE
SI2C2IE
T7IE
0000
IEC4
0828
CTMUIE
FLT4IE
QEI2IE
FLT3IE
PSESMIE
—
C2TXIE
C1TXIE
—
—
CRCIE
U2EIE
U1EIE
FLT2IE
0000
IEC5
082A PWM2IE PWM1IE
—
—
SPI3IE
SPI3EIE
U4TXIE
U4RXIE
U4EIE
—
—
—
U3TXIE
U3RXIE
U3EIE
—
0000
IEC6
082C
—
—
—
—
—
—
—
—
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC8
0830 JTAGIE
ICDIE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC9
0832
—
—
—
—
—
—
—
—
—
PTG3IE
PTG2IE
PTG1IE
PTG0IE
—
0000
IPC0
0840
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP2
4444
IPC1
0842
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP2
4444
IPC2
0844
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
0846
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
IPC4
0848
—
CNIP2
CNIP1
CNIP0
—
CMPIP2
CMPIP1
CMPIP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
084A
—
IC8IP2
IC8IP1
IC8IP0
—
IC7IP2
IC7IP1
IC7IP0
—
AD2IP2
AD2IP1
AD2IP0
—
INT1IP2
INT1IP1
INT1IP0
4444
IPC6
084C
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
4444
IPC7
084E
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
0850
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
4444
IPC9
0852
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
4444
IPC10
0854
—
OC7IP2
OC7IP1
OC7IP0
—
OC6IP2
OC6IP1
OC6IP0
—
OC5IP2
OC5IP1
OC5IP0
—
IC6IP2
IC6IP1
IC6IP0
4444
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The PMPIF/PMPIE/PMPIPx flags are not available on 44-pin devices.
The RTCCIF/RTCCIE/RTCCIPx flags are not available on 44-pin devices.
—
T6IE
OVAERR OVBERR COVAERR COVBERR
Bit 10
FLT1IE RTCCIE(2)
—
—
—
PTGWDTIF PTGSTEPIF
PTGWDTIE PTGSTEPIE
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 48
TABLE 4-2:
2013-2014 Microchip Technology Inc.
TABLE 4-2:
SFR
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGM6XX/7XX DEVICES (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
PMPIP2(1)
PMPIP1(1)
PMPIP0(1)
—
OC8IP2
OC8IP1
OC8IP0
4444
MI2C2IP1
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
T7IP2
T7IP1
T7IP0
4444
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
T9IP2
T9IP1
T9IP0
4444
QEI1IP2
QEI1IP2
QEI1IP0
—
PCEPIP2
PCEPIP1
PCEPIP0
—
C2IP2
C2IP1
C2IP0
4444
—
RTCCIP2(2)
RTCCIP1(2)
RTCCIP0(2)
—
—
—
—
—
DCIIP2
DCIIP1
DCIIP0
0404
CRCIP0
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
FLT2IP2
FLT2IP1
FLT2IP0
4440
C2TXIP1
C2TXIP0
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
4400
QEI2IP2
QEI2IP1
QEI2IP0
—
FLT3IP2
FLT3IP1
FLT3IP0
—
PCESIP2
PCESIP1
PCESIP0
—
—
—
—
4040
—
—
—
—
—
—
—
—
—
CTMUIP2
CTMUIP1
CTMUIP0
—
FLT4IP2
FLT4IP1
FLT4IP0
4000
0868
—
U3TXIP2
U3TXIP1
U3TXIP0
—
U3RXIP2
U3RXIP1
U3RXIP0
—
U3EIP2
U3EIP1
U3EIP0
—
—
—
—
0000
IPC21
086A
—
U4EIP2
U4EIP1
U4EIP0
—
—
—
—
—
—
—
—
—
—
—
—
0000
IPC22
086C
—
SPI3IP2
SPI3IP1
SPI3IP0
—
SPI3EIP2
SPI3EIP1
SPI3EIP0
—
U4TXIP2
U4TXIP1
U4TXIP0
—
U4RXIP2
U4RXIP1
U4RXIP0
0000
IPC23
086E
—
PGC2IP2 PGC2IP1
PGC2IP0
—
PWM1IP2
PWM1IP1
PWM1IP0
—
—
—
—
—
—
—
—
4400
IPC24
0870
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2
PWM5IP1
PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
4444
IPC35
0886
—
JTAGIP2
JTAGIP1
JTAGIP0
—
ICDIP2
ICDIP1
ICDIP0
—
—
—
—
—
—
—
—
4400
IPC36
0888
—
PTG0IP2
PTG0IP1
PTG0IP0
—
—
—
—
—
4440
IPC37
088A
—
—
—
—
—
PTG3IP2
PTG3IP1
PTG3IP0
—
PTG2IP2
PTG2IP1
PTG2IP0
—
PTG1IP2
PTG1IP1
PTG1IP0
0445
INTTREG 08C8
—
—
—
—
ILR3
ILR2
ILR1
ILR0
VECNUM7
VECNUM6
VECNUM5
VECNUM4
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
IPC11
0856
—
T6IP2
T6IP1
T6IP0
—
—
IPC12
0858
—
T8IP2
T8IP1
T8IP0
—
MI2C2IP2
IPC13
085A
—
C2RXIP2
C2RXIP1
C2RXIP0
—
INT4IP2
IPC14
085C
—
DCIEIP2
DCIEIP1
DCIEIP0
—
IPC15
085E
—
FLT1IP2
FLT1IP1
FLT1IP0
IPC16
0860
—
CRCIP2
CRCIP1
IPC17
0862
—
C2TXIP2
IPC18
0864
—
IPC19
0866
IPC20
Legend:
Note 1:
2:
Bit 10
Bit 9
PTGWDTIP2 PTGWDTIP1 PTGWDTIP0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The PMPIF/PMPIE/PMPIPx flags are not available on 44-pin devices.
The RTCCIF/RTCCIE/RTCCIPx flags are not available on 44-pin devices.
—
PTGSTEPIP2 PTGSTEPIP1 PTGSTEPIP0
VECNUM3 VECNUM2
VECNUM1 VECNUM0
0000
DS70000689D-page 49
dsPIC33EPXXXGM3XX/6XX/7XX
Bit 8
Addr.
SFR
Name
Addr.
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGM3XX DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
2013-2014 Microchip Technology Inc.
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
DMACERR
MATHERR
ADDRERR
STKERR
OSCFAIL
—
0000
INTCON2 08C2
GIE
DISI
SWTRAP
—
—
—
—
—
—
—
—
—
—
INT2EP
INT1EP
INT0EP
0000
INTCON3 08C4
—
—
—
—
—
—
—
—
—
—
DAE
DOOVR
—
—
—
—
0000
INTCON4 08C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SGHT
0000
IFS0
0800
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0802 U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
IC8IF
IC7IF
AD2IF
INT1IF
CNIF
CMPIF
MI2C1IF
SI2C1IF
0000
IFS2
0804
—
PMPIF(1)
OC8IF
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
—
—
SPI2IF
SPI2EIF
0000
IFS3
0806
—
DCIIF
DCIEIF
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
T9IF
T8IF
MI2C2IF
SI2C2IF
T7IF
0000
IFS4
0808
CTMUIF
FLT4IF
QEI2IF
FLT3IF
PSESMIF
—
—
—
—
—
CRCIF
U2EIF
U1EIF
FLT2IF
0000
IFS5
080A PWM2IF PWM1IF
—
—
SPI3IF
SPI3EIF
U4TXIF
U4RXIF
U4EIF
—
—
—
U3TXIF
U3RXIF
U3EIF
—
0000
IFS6
080C
—
—
—
—
—
—
—
—
—
—
—
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS8
0810 JTAGIF
ICDIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS9
0812
—
—
—
—
—
—
—
—
—
PTG3IF
PTG2IF
PTG1IF
PTG0IF
—
0000
IEC0
0820
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0822 U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
IC8IE
IC7IE
AD2IE
INT1IE
CNIE
CMPIE
MI2C1IE
SI2C1IE
0000
IEC2
0824
—
PMPIE(1)
OC8IE
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
—
—
SPI2IE
SPI2EIE
0000
IEC3
0826
—
DCIIE
DCIEIE
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
T9IE
T8IE
MI2C2IE
SI2C2IE
T7IE
0000
IEC4
0828
CTMUIE
FLT4IE
QEI2IE
FLT3IE
PSESMIE
—
—
—
—
—
CRCIE
U2EIE
U1EIE
FLT2IE
0000
IEC5
082A PWM2IE PWM1IE
—
—
SPI3IE
SPI3EIE
U4TXIE
U4RXIE
U4EIE
—
—
—
U3TXIE
U3RXIE
U3EIE
—
0000
IEC6
082C
—
—
—
—
—
—
—
—
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC8
0830 JTAGIE
ICDIE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC9
0832
—
—
—
—
—
—
—
—
—
PTG3IE
PTG2IE
PTG1IE
PTG0IE
—
0000
IPC0
0840
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP2
4444
IPC1
0842
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP2
4444
IPC2
0844
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
0846
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
IPC4
0848
—
CNIP2
CNIP1
CNIP0
—
CMPIP2
CMPIP1
CMPIP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
084A
—
IC8IP2
IC8IP1
IC8IP0
—
IC7IP2
IC7IP1
IC7IP0
—
AD2IP2
AD2IP1
AD2IP0
—
INT1IP2
INT1IP1
INT1IP0
4444
IPC6
084C
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
4444
IPC7
084E
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
0850
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
4444
IPC9
0852
—
IC5IP2
IC5IP1
IC5IP0
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
4444
IPC10
0854
—
OC7IP2
OC7IP1
OC7IP0
—
OC6IP2
OC6IP1
OC6IP0
—
OC5IP2
OC5IP1
OC5IP0
—
IC6IP2
IC6IP1
IC6IP0
4444
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The PMPIF/PMPIE/PMPIPx flags are not available on 44-pin devices.
The RTCCIF/RTCCIE/RTCCIPx flags are not available on 44-pin devices.
T6IF
FLT1IF RTCCIF(2)
—
—
T6IE
—
FLT1IE RTCCIE(2)
—
—
—
—
PTGWDTIF PTGSTEPIF
PTGWDTIE PTGSTEPIE
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 50
TABLE 4-3:
2013-2014 Microchip Technology Inc.
TABLE 4-3:
SFR
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGM3XX DEVICES (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
PMPIP2(1)
PMPIP1(1)
PMPIP0(1)
—
OC8IP2
OC8IP1
OC8IP0
4444
MI2C2IP1
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
T7IP2
T7IP1
T7IP0
4444
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
T9IP2
T9IP1
T9IP0
4444
QEI1IP2
QEI1IP2
QEI1IP0
—
PCEPIP2
PCEPIP1
PCEPIP0
—
—
—
—
4444
—
RTCCIP2(2)
RTCCIP1(2)
RTCCIP0(2)
—
—
—
—
—
DCIIP2
DCIIP1
DCIIP0
0404
CRCIP0
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
FLT2IP2
FLT2IP1
FLT2IP0
4440
C2TXIP1
C2TXIP0
—
FLT3IP2
FLT3IP1
FLT3IP0
—
PCESIP2
PCESIP1
PCESIP0
—
—
—
—
4040
—
—
—
—
—
—
—
—
CTMUIP2
CTMUIP1
CTMUIP0
—
FLT4IP2
FLT4IP1
FLT4IP0
0004
—
U3TXIP2
U3TXIP1
U3TXIP0
—
U3RXIP2
U3RXIP1
U3RXIP0
—
U3EIP2
U3EIP1
U3EIP0
—
—
—
—
0000
086A
—
U4EIP2
U4EIP1
U4EIP0
—
—
—
—
—
—
—
—
—
—
—
—
0000
IPC22
086C
—
SPI3IP2
SPI3IP1
SPI3IP0
—
SPI3EIP2
SPI3EIP1
SPI3EIP0
—
U4TXIP2
U4TXIP1
U4TXIP0
—
U4RXIP2
U4RXIP1
U4RXIP0
0000
IPC23
086E
—
PGC2IP2 PGC2IP1 PGC2IP0
—
PWM1IP2
PWM1IP1
PWM1IP0
—
—
—
—
—
—
—
—
4400
IPC24
0870
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2
PWM5IP1
PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
4444
IPC35
0886
—
JTAGIP2
JTAGIP1
JTAGIP0
—
ICDIP2
ICDIP1
ICDIP0
—
—
—
—
—
—
—
—
4400
IPC36
0888
—
PTG0IP2
PTG0IP1
PTG0IP0
—
—
—
—
—
4440
IPC37
088A
—
—
—
—
—
PTG3IP2
PTG3IP1
PTG3IP0
—
PTG2IP2
PTG2IP1
PTG2IP0
—
PTG1IP2
PTG1IP1
PTG1IP0
0444
INTTREG 08C8
—
—
—
—
ILR3
ILR2
ILR1
ILR0
VECNUM7
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
IPC11
0856
—
T6IP2
T6IP1
T6IP0
—
—
IPC12
0858
—
T8IP2
T8IP1
T8IP0
—
MI2C2IP2
IPC13
085A
—
—
—
—
—
INT4IP2
IPC14
085C
—
DCIEIP2
DCIEIP1
DCIEIP0
—
IPC15
085E
—
FLT1IP2
FLT1IP1
FLT1IP0
IPC16
0860
—
CRCIP2
CRCIP1
IPC18
0864
—
C2TXIP2
IPC19
0866
—
IPC20
0868
IPC21
Legend:
Note 1:
2:
Bit 10
Bit 9
PTGWDTIP2 PTGWDTIP1 PTGWDTIP0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The PMPIF/PMPIE/PMPIPx flags are not available on 44-pin devices.
The RTCCIF/RTCCIE/RTCCIPx flags are not available on 44-pin devices.
—
PTGSTEPIP2 PTGSTEPIP1 PTGSTEPIP0
VECNUM1 VECNUM0
0000
DS70000689D-page 51
dsPIC33EPXXXGM3XX/6XX/7XX
Bit 8
Addr.
SFR
Name
Addr.
TIMERS REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
2013-2014 Microchip Technology Inc.
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
0000
TMR3HLD
0108
Timer3 Holding Register (For 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
TMR4
0114
Timer4 Register
0000
TMR5HLD
0116
Timer5 Holding Register (For 32-bit timer operations only)
xxxx
TMR5
0118
Timer5 Register
0000
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
TMR6
0122
Timer6 Register
0000
TMR7HLD
0124
Timer7 Holding Register (For 32-bit timer operations only)
xxxx
TMR7
0126
Timer7 Register
0000
PR6
0128
Period Register 6
FFFF
PR7
012A
Period Register 7
T6CON
012C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
T7CON
012E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
TMR8
0130
Timer8 Register
0000
TMR9HLD
0132
Timer9 Holding Register (For 32-bit timer operations only)
xxxx
TMR9
0134
Timer9 Register
0000
PR8
0136
Period Register 8
FFFF
PR9
0138
Period Register 9
T8CON
013A
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
T9CON
013C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
TON
—
TSIDL
—
—
—
—
—
—
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
FFFF
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
FFFF
0000
0000
FFFF
0000
0000
FFFF
0000
0000
FFFF
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 52
TABLE 4-4:
2013-2014 Microchip Technology Inc.
TABLE 4-5:
SFR
Name
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 8 REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
IC1CON1
0140
—
—
ICSIDL
IC1CON2
0142
—
—
—
Bit 12
Bit 11
Bit 10
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
Bit 9
Bit 8
—
—
—
IC32
Bit 7
Bit 6
Bit 5
—
ICI1
ICI0
ICTRIG TRIGSTAT
IC1BUF
0144
Input Capture 1 Buffer Register
IC1TMR
0146
Input Capture 1 Timer Register
IC2CON1
0148
—
—
ICSIDL
IC2CON2
014A
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
IC2BUF
014C
Input Capture 2 Buffer Register
IC2TMR
014E
Input Capture 2 Timer Register
IC3CON1
0150
—
—
ICSIDL
IC3CON2
0152
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
0154
Input Capture 3 Buffer Register
0156
Input Capture 3 Timer Register
IC4CON1
0158
—
—
ICSIDL
IC4CON2
015A
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
IC4BUF
015C
Input Capture 4 Buffer Register
IC4TMR
015E
Input Capture 4 Timer Register
IC5CON1
0160
—
—
ICSIDL
IC5CON2
0162
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
IC5BUF
0164
Input Capture 5 Buffer Register
IC5TMR
0166
Input Capture 5 Timer Register
IC6CON1
0168
—
—
ICSIDL
IC6CON2
016A
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
IC6BUF
016C
Input Capture 6 Buffer Register
IC6TMR
016E
Input Capture 6 Timer Register
IC7CON1
0170
—
—
ICSIDL
IC7CON2
0172
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
Bit 3
Bit 2
Bit 1
Bit 0
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
All
Resets
0000
000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
DS70000689D-page 53
IC7BUF
0174
Input Capture 7 Buffer Register
IC7TMR
0176
Input Capture 7 Timer Register
IC8CON1
0178
—
—
ICSIDL
IC8CON2
017A
—
—
—
IC8BUF
017C
Input Capture 8 Buffer Register
xxxx
IC8TMR
017E
Input Capture 8 Timer Register
0000
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
—
—
—
IC32
—
ICI1
ICTRIG TRIGSTAT
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000D
dsPIC33EPXXXGM3XX/6XX/7XX
IC3BUF
IC3TMR
—
Bit 4
SFR
Name
Addr.
OC1CON1 0900
OUTPUT COMPARE REGISTER MAP
Bit 15
Bit 14
Bit 13
—
—
OCSIDL
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN
OC1RS
0904
OC1R
OC1TMR
Bit 11
Bit 10
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
Bit 9
—
—
Bit 8
Bit 7
ENFLTB ENFLTA
OC32
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
OCFLTB
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
0000
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
xxxx
0906
Output Compare 1 Register
xxxx
0908
Output Compare 1 Timer Value Register
—
—
OCSIDL
OC2CON2 090C FLTMD FLTOUT FLTTRIEN
OC2RS
090E
OC2R
OC2TMR
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
ENFLTB ENFLTA
OC32
—
OCFLTB
xxxx
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
Output Compare 2 Secondary Register
xxxx
0910
Output Compare 2 Register
xxxx
0912
Output Compare 2 Timer Value Register
OC3CON1 0914
—
—
OCSIDL
OC3CON2 0916 FLTMD FLTOUT FLTTRIEN
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
0918
ENFLTB ENFLTA
OC32
—
OCFLTB
Output Compare 3 Register
Output Compare 3 Timer Value Register
OCSIDL
OC4CON2 0920 FLTMD FLTOUT FLTTRIEN
OC4RS
0922
OC4R
OC4TMR
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
OCM1
OCM0
0000
000C
xxxx
091A
—
OCM2
xxxx
091C
—
TRIGMODE
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
OC3R
OC4CON1 091E
xxxx
OCFLTA
Output Compare 3 Secondary Register
OC3TMR
ENFLTB ENFLTA
OC32
—
OCFLTB
xxxx
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
Output Compare 4 Secondary Register
xxxx
0924
Output Compare 4 Register
xxxx
0926
Output Compare 4 Timer Value Register
OC5CON1 0928
—
—
OCSIDL
OC5CON2 092A FLTMD FLTOUT FLTTRIEN
2013-2014 Microchip Technology Inc.
OC5RS
092C
OC5R
OC5TMR
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
ENFLTB ENFLTA
OC32
—
OCFLTB
xxxx
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
Output Compare 5 Secondary Register
xxxx
092E
Output Compare 5 Register
xxxx
0930
Output Compare 5 Timer Value Register
OC6CON1 0932
—
—
OCSIDL
OC6CON2 0934 FLTMD FLTOUT FLTTRIEN
OC6RS
000C
Output Compare 1 Secondary Register
OC2CON1 090A
OC3RS
Bit 12
0936
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
ENFLTB ENFLTA
OC32
—
OCFLTB
xxxx
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
Output Compare 6 Secondary Register
xxxx
OC6R
0938
Output Compare 6 Register
xxxx
OC6TMR
093A
Output Compare 6 Timer Value Register
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 54
TABLE 4-6:
2013-2014 Microchip Technology Inc.
TABLE 4-6:
SFR
Name
Addr.
OC7CON1 093C
OUTPUT COMPARE REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
—
—
OCSIDL
OC7CON2 093E FLTMD FLTOUT FLTTRIEN
OC7RS
0940
OC7R
OC7TMR
Bit 11
Bit 10
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
Bit 9
—
—
Bit 8
Bit 7
ENFLTB ENFLTA
OC32
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
OCFLTB
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
0000
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
000C
Output Compare 7 Secondary Register
xxxx
0942
Output Compare 7 Register
xxxx
0944
Output Compare 7 Timer Value Register
OC8CON1 0946
—
—
OCSIDL
OC8CON2 0948 FLTMD FLTOUT FLTTRIEN
OC8RS
094A
OC8R
OC8TMR
Legend:
Bit 12
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
ENFLTB ENFLTA
OC32
—
OCFLTB
xxxx
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
Output Compare 8 Secondary Register
xxxx
094C
Output Compare 8 Register
xxxx
094E
Output Compare 8 Timer Value Register
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 55
PTG REGISTER MAP
2013-2014 Microchip Technology Inc.
SFR
Name
Addr.
PTGCST
0AC0
PTGCON
0AC2
PTGCLK2 PTGCLK1 PTGCLK0 PTGDIV4 PTGDIV3 PTGDIV2 PTGDIV1 PTGDIV0 PTGPWD3 PTGPWD2 PTGPWD1 PTGPWD0
PTGBTE
0AC4
ADCTS4
PTGHOLD
0AC6
PTGHOLD
0000
PTGT0LIM
0AC8
PTGT0LIM
0000
PTGT1LIM
0ACA
PTGT1LIM
0000
PTGSDLIM
0ACC
PTGSDLIM
0000
PTGC0LIM
0ACE
PTGC0LIM
0000
PTGC1LIM
0AD0
PTGC1LIM
0000
PTGADJ
0AD2
PTGADJ
0000
PTGL0
0AD4
PTGL0
PTGQPTR
0AD6
PTGQUE0
0AD8
STEP1
STEP0
0000
PTGQUE1
0ADA
STEP3
STEP2
0000
PTGQUE2
0ADC
STEP5
STEP4
0000
PTGQUE3
0ADE
STEP7
STEP6
0000
PTGQUE4
0AE0
STEP9
STEP8
0000
PTGQUE5
0AE2
STEP11
STEP10
0000
PTGQUE6
0AE4
STEP13
STEP12
0000
PTGQUE7
0AE6
STEP15
STEP14
0000
PTGQUE8
0x0AE8
STEP17
STEP16
0000
PTGQUE9
0x0AEA
STEP19
STEP18
0000
PTGQUE10 0x0AEC
STEP21
STEP20
0000
PTGQUE11 0x0AEE
STEP23
STEP22
0000
PTGQUE12 0x0AF0
STEP25
STEP24
0000
PTGQUE13 0x0AF2
STEP27
STEP26
0000
PTGQUE14 0x0AF4
STEP29
STEP28
0000
PTGQUE15 0x0AF6
STEP31
STEP30
0000
Legend:
Bit 15
Bit 14
PTGEN
—
—
ADCTS3
—
Bit 13
Bit 12
PTGSIDL PTGTOGL
ADCTS2
—
ADCTS1
—
Bit 11
—
IC4TSS
—
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
PTGSWT PTGSSEN PTGIVIS PTGSTRT PTGWDTO
IC3TSS
—
IC2TSS
—
IC1TSS
OC4CS
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
OC3CS
Bit 5
Bit 4
Bit 3
—
—
—
OC2CS
OC1CS
—
OC4TSS
Bit 2
Bit 1
Bit 0
All
Resets
—
PTGITM1
PTGITM0
0000
PTGWDT2 PTGWDT1 PTGWDT0
0000
OC3TSS
OC2TSS
OC1TSS
0000
0000
—
—
PTGQPTR
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 56
TABLE 4-7:
2013-2014 Microchip Technology Inc.
TABLE 4-8:
SFR
Name
PWM REGISTER MAP
Bit 13
Bit 12
Bit 11
Bit
10
Bit 9
Bit 8
Bit 7
SYNCPOL
SYNCOEN
SYNCEN
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SEVTPS3
SEVTPS2
Bit 1
Bit 0
All
Resets
SEVTPS1
SEVTPS0
0000
Addr.
Bit 15
Bit 14
PTCON
0C00
PTEN
—
PTCON2
0C02
—
—
PTPER
0C04
PTPER
00F8
SEVTCMP
0C06
SEVTCMP
0000
MDC
0C0A
MDC
STCON
0C0E
—
—
—
STCON2
0C10
—
—
—
STPER
0C12
PTSIDL SESTAT SEIEN EIPU
—
—
—
—
SESTAT SEIEN EIPU
—
—
—
SYNCPOL
SYNCOEN
SYNCEN
—
—
—
SSEVTCMP 0C14
CHOP
0C1A CHPCLKEN
PWMKEY
0C1E
Legend:
—
—
—
—
—
—
—
—
PCLKDIV
0000
0000
SYNCSRC2 SYNCSRC1 SYNCSRC0
—
—
SEVTPS3
—
SEVTPS2
—
SEVTPS1
SEVTPS0
PCLKDIV
0000
0000
STPER
0000
SSEVTCMP
0000
CHOPCLK9 CHOPCLK8 CHOPCLK7 CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
PWMKEY
0000
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr.
PWM GENERATOR 1 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON1
0C22
FCLCON1
0C24 IFLTMOD CLSRC4
PDC1
0C26
PDC1
FFF8
PHASE1
0C28
PHASE1
0000
DTR1
0C2A
—
—
DTR1
0000
ALTDTR1
0C2C
—
—
ALTDTR1
0000
SDC1
0C2E
SDC1
0000
SPHASE1
0C30
SPHASE1
0000
TRIG1
0C32
TRGCMP
TRGCON1 0C34 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
—
—
—
PWMCAP1 0C38
—
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
PWMCAP1
DS70000689D-page 57
LEBCON1
0C3A
PHR
PHF
PLR
PLF
LEBDLY1
0C3C
—
—
—
—
AUXCON1 0C3E
—
—
—
—
Legend:
—
FLTLEBEN
CLLEBEN
—
—
—
0000
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
—
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 4-9:
SFR
Name
—
SYNCSRC2 SYNCSRC1 SYNCSRC0
SFR
Name
Addr.
PWM GENERATOR 2 REGISTER MAP
Bit 15
PWMCON2 0C40 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
IOCON2
0C42
FCLCON2
0C44 IFLTMOD CLSRC4
PDC2
0C46
PDC2
0000
PHASE2
0C48
PHASE2
0000
DTR2
0C4A
—
—
DTR2
0000
ALTDTR2
0C4C
—
—
ALTDTR2
0000
SDC2
0C4E
SDC2
0000
SPHASE2
0C50
SPHASE2
0000
TRIG2
0C52
TRGCMP
TRGCON2
0C54 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
—
—
—
FLTLEBEN
CLLEBEN
—
PWMCAP2 0C78
0C5A
PHR
PHF
PLR
PLF
LEBDLY2
0C5C
—
—
—
—
AUXCON2
0C5E
—
—
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
Name
Addr.
—
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
PWMCAP2
LEBCON2
TABLE 4-11:
—
—
—
0000
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
Bit 7
Bit 6
DTC1
DTC0
0000
0000
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
PWM GENERATOR 3 REGISTER MAP
Bit 15
PWMCON3 0C60 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
2013-2014 Microchip Technology Inc.
IOCON3
0C62
FCLCON3
0C64 IFLTMOD CLSRC4
PDC3
0C66
PDC3
0000
PHASE3
0C68
PHASE3
0000
DTR3
0C6A
—
—
DTR3
0000
ALTDTR3
0C6C
—
—
ALTDTR3
0000
SDC3
0C6E
SDC3
0000
SPHASE3
0C70
SPHASE3
0000
TRIG3
0C72
TRGCMP
TRGCON3
0C74 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
—
—
—
PWMCAP3 0C78
—
—
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
PWMCAP3
LEBCON3
0C7A
PHR
PHF
PLR
PLF
FLTLEBEN
CLLEBEN
LEBDLY3
0C7C
—
—
—
—
AUXCON3
0C7E
—
—
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
0000
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
0000
—
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 58
TABLE 4-10:
2013-2014 Microchip Technology Inc.
TABLE 4-12:
SFR
Name
Addr.
PWMCON4 0C80
PWM GENERATOR 4 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTSTAT
CLSTAT
TRGSTAT
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
IOCON4
0C82
PENH
PENL
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
FCLCON4
0C84
IFLTMOD
CLSRC4
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
PDC4
0C86
PDC3
0000
PHASE4
0C88
PHASE3
0000
DTR4
0C8A
—
—
DTR3
0000
ALTDTR4
0C8C
—
—
ALTDTR3
0000
SDC4
0C8E
SDC4
0000
SPHASE4
0C90
SPHASE4
0000
TRIG4
0C92
TRGCMP
TRGCON4
0C94
PWMCAP4
0C98
LEBCON4
0C9A
PHR
PHF
PLR
PLF
LEBDLY4
0C9C
—
—
—
—
AUXCON4
0C9E
—
—
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
Name
Addr.
—
—
—
—
—
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
PWMCAP4
FLTLEBEN
CLLEBEN
—
—
—
0000
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
0000
—
—
Bit 7
Bit 6
DTC1
DTC0
0000
0000
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
PWM GENERATOR 5 REGISTER MAP
Bit 15
PWMCON5 0CA0 FLTSTAT
PENH
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
CLSTAT
TRGSTAT
PENL
POLH
CLSRC4
CLSRC3
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
C000
FLTMOD1
FLTMOD0
00F8
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
DS70000689D-page 59
IOCON5
0CA5
FCLCON5
0CA4 IFLTMOD
PDC5
0CA6
PDC5
0000
PHASE5
0CA8
PHASE5
0000
DTR5
0CAA
—
—
DTR5
0000
ALTDTR5
0CAC
—
—
ALTDTR5
0000
SDC5
0CAE
SDC5
0000
SPHASE5
0CB0
SPHASE5
0000
TRIG5
0CB2
TRGCMP
TRGCON5
0CB4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
—
—
—
FLTLEBEN
CLLEBEN
—
PWMCAP5 0CB8
—
—
FLTSRC3
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
PWMCAP5
LEBCON5
0CBA
PHR
PHF
PLR
PLF
LEBDLY5
0CBC
—
—
—
—
AUXCON5
0CBE
—
—
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
0000
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 4-13:
TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
SFR Name Addr.
PWM GENERATOR 6 REGISTER MAP
Bit 15
PWMCON6 0CC0 FLTSTAT
PENH
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
CLSTAT
TRGSTAT
PENL
POLH
CLSRC4
CLSRC3
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
C000
FLTMOD1
FLTMOD0
00F8
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON6
0CC2
FCLCON6
0CC4 IFLTMOD
PDC6
0CC6
PDC6
0000
PHASE6
0CC8
PHASE6
0000
DTR6
0CCA
—
—
DTR6
0000
ALTDTR6
0CCC
—
—
ALTDTR6
0000
SDC6
0CCE
SDC6
0000
SPHASE6
0CD0
SPHASE6
0000
TRIG6
0CD2
TRGCMP
TRGCON6
0CD4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
—
—
—
PWMCAP6 0CD8
—
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
PWMCAP6
LEBCON6
0CDA
PHR
PHF
PLR
PLF
LEBDLY6
0CDC
—
—
—
—
AUXCON6 0CDE
—
—
—
—
Legend:
—
FLTLEBEN
CLLEBEN
—
—
—
0000
—
BCH
BCL
BPHH
BPHL
BPLH
BPLL
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
—
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 60
TABLE 4-14:
2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc.
TABLE 4-15:
QEI1 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
QEI1CON
01C0
QEIEN
—
QEISIDL
PIMOD2
PIMOD1
PIMOD0
IMV1
IMV0
QEI1IOC
01C2 QCAPEN FLTREN
QFDIV2
QFDIV1
QFDIV0
OUTFNC1
OUTFNC0
SWPAB
QEI1STAT
01C4
POS1CNTL
01C6
POSCNT
0000
POS1CNTH
01C8
POSCNT
0000
POS1HLD
01CA
POSHLD
0000
VEL1CNT
01CC
VELCNT
0000
INT1TMRL
01CE
INTTMR
0000
INT1TMRH
01D0
INTTMR
0000
INT1HLDL
01D2
INTHLD
0000
INT1HLDH
01D4
INTHLD
0000
INDX1CNTL
01D6
INDXCNT
0000
INDX1CNTH 01D8
INDXCNT
0000
INDX1HLD
01DA
INDXHLD
0000
QEI1GECL
01DC
QEIGEC
0000
QEI1ICL
01DC
QEIIC
0000
QEI1GECH
01DE
QEIGEC
0000
QEI1ICH
01DE
QEIIC
0000
QEI1LECL
01E0
QEILEC
0000
QEI1LECH
01E2
QEILEC
0000
—
Bit 9
Bit 8
Bit 7
Bit 6
—
INTDIV2
INTDIV1
INTDIV0
HOMPOL IDXPOL
QEBPOL
QEAPOL
PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PCIIRQ
Bit 5
Bit 4
Bit 3
Bit 2
CNTPOL GATEN
HOME
INDEX
Bit 1
Bit 0
All
Resets
CCM1
CCM0
0000
QEB
QEA
000x
PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN
0000
DS70000689D-page 61
dsPIC33EPXXXGM3XX/6XX/7XX
Legend:
—
Bit 10
SFR
Name
QEI2 REGISTER MAP
Bit 8
Bit 7
Bit 6
—
INTDIV2
HOMPOL IDXPOL
Bit 2
Bit 1
Bit 0
All
Resets
INTDIV1
INTDIV0
CNTPOL
GATEN
CCM1
CCM0
0000
QEBPOL
QEAPOL
HOME
INDEX
QEB
QEA
000x
Bit 14
Bit 13
Bit 12
Bit 11
QEI2CON
05C0
QEIEN
—
QEISIDL
PIMOD2
PIMOD1
PIMOD0
IMV1
IMV0
QEI2IOC
05C2 QCAPEN FLTREN
QFDIV2
QFDIV1
QFDIV0
OUTFNC1
OUTFNC0
SWPAB
QEI2STAT
05C4
POS2CNTL
05C6
POSCNT
0000
POS2CNTH
05C8
POSCNT
0000
POS2HLD
05CA
POSHLD
0000
VEL2CNT
05CC
VELCNT
0000
INT2TMRL
05CE
INTTMR
0000
INT2TMRH
05D0
INTTMR
0000
INT2HLDL
05D2
INTHLD
0000
INT2HLDH
05D4
INTHLD
0000
INDX2CNTL
05D6
INDXCNT
0000
INDX2CNTH 05D8
INDXCNT
0000
—
Bit 9
Bit 3
Bit 15
—
Bit 10
Bit 4
Addr.
PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN
PCIIRQ
Bit 5
PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN
0000
INDX2HLD
05DA
INDXHLD
0000
QEI2GECL
05DC
QEIGEC
0000
QEI2ICL
05DC
QEIIC
0000
QEI2GECH
05DE
QEIGEC
0000
QEI2ICH
05DE
QEIIC
0000
QEI2LECL
05E0
QEILEC
0000
QEI2LECH
05E2
QEILEC
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 62
TABLE 4-16:
2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc.
TABLE 4-17:
SFR
Name
I2C1 AND I2C2 REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
I2C1TRN
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
I2C1BRG
0204
I2C1CON
0206
I2C1STAT 0208
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
00FF
Baud Rate Generator Register
0000
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
I2C1ADD
020A
—
—
—
—
—
—
I2C1MSK
020C
—
—
—
—
—
—
I2C2RCV
0210
—
—
—
—
—
—
—
—
I2C2 Receive Register
I2C2TRN
0212
—
—
—
—
—
—
—
—
I2C2 Transmit Register
I2C2BRG
0214
I2C2CON
0216
1000
0000
I2C1 Address Register
0000
I2C1 Address Mask Register
0000
0000
00FF
Baud Rate Generator Register
0000
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
021A
—
—
—
—
—
—
I2C2 Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
I2C2 Address Mask Register
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
I2C2STAT 0218
I2C2ADD
UART1 AND UART2 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
U1MODE
0220
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
WAKE
U1STA
0222 UTXISEL1 UTXINV UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
URXISEL1
Bit 11
Bit 10
Bit 9
U1TXREG 0224
—
—
—
—
—
—
—
U1RXREG 0226
—
—
—
—
—
—
—
U1BRG
0228
U2MODE
0230
U2STA
0232 UTXISEL1 UTXINV UTXISEL0
UARTEN
—
USIDL
Bit 6
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
xxxx
UART1 Receive Register
0000
0000
—
UEN1
UEN0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
—
UTXBRK
UTXEN
UTXBF
TRMT
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
—
—
—
—
—
U2RXREG 0236
—
—
—
—
—
—
—
DS70000689D-page 63
Baud Rate Generator Prescaler
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0110
UART1 Transmit Register
RTSMD
—
Legend:
Bit 7
IREN
—
0238
Bit 8
Baud Rate Generator Prescaler
U2TXREG 0234
U2BRG
0000
0000
0110
UART2 Transmit Register
xxxx
UART2 Receive Register
0000
0000
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 4-18:
1000
UART3 AND UART4 REGISTER MAP
SFR
Name
Addr.
U3MODE
0250
UARTEN
U3STA
0252
UTXISEL1
U3TXREG
0254
—
U3RXREG 0256
—
U3BRG
0258
U4MODE
02B0
Bit 15
Bit 14
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 12
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
WAKE
LPBACK
—
—
—
—
—
—
UART3 Transmit Register
xxxx
—
—
—
—
—
—
UART3 Receive Register
0000
URXISEL1 URXISEL0
Bit 0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
Baud Rate Generator Prescaler
UARTEN
All
Resets
Bit 13
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
TRMT
WAKE
0000
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
U4STA
02B2 UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
U4TXREG
02B4
—
—
—
—
—
—
—
UART4 Transmit Register
xxxx
U4RXREG 02B6
—
—
—
—
—
—
—
UART4 Receive Register
0000
U4BRG
Legend:
02B8
Baud Rate Generator Prescaler
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20:
SPI1, SPI2 AND SPI3 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
SPI1CON1
0242
—
—
—
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
SPI1BUF
0248
SPI2STAT
0260
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPIBEC2
SPIBEC1
SPIBEC0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
—
FRMDLY SPIBEN
0000
SPITBF
SPIRBF
0000
PPRE1
DISSCK DISSDO
—
—
SPI1 Transmit and Receive Buffer Register
SPIEN
—
SPISIDL
2013-2014 Microchip Technology Inc.
SPI2CON1
0262
—
—
—
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
SPI2BUF
0268
SPI3STAT
02A0
—
—
DISSCK DISSDO
—
—
0000
SPIBEC2
SPIBEC1
SPIBEC0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
—
—
—
—
—
—
—
—
—
PPRE0
0000
FRMDLY SPIBEN
0000
SPITBF
SPIRBF
0000
PPRE1
PPRE0
0000
FRMDLY SPIBEN
0000
SPI2 Transmit and Receive Buffer Register
SPIEN
—
SPISIDL
SPI3CON1
02A2
—
—
—
SPI3CON2
02A4
FRMEN
SPIFSD
FRMPOL
SPI3BUF
02A8
Legend:
URXISEL1 URXISEL0
—
—
DISSCK DISSDO
—
—
0000
SPIBEC2
SPIBEC1
SPIBEC0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
—
—
—
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI3 Transmit and Receive Buffer Register
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 64
TABLE 4-19:
2013-2014 Microchip Technology Inc.
TABLE 4-21:
SFR
Name
DCI REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
COFSD
UNFM
Bit 6
Bit 5
Bit 4
CSDOM
DJST
r
COFSG1
COFSG0
r
Bit 2
Bit 1
Bit 0
All
Resets
r
r
COFSM1
COFSM0
0000
WS3
WS2
WS1
WS0
Bit 3
DCICON1
0280
DCIEN
r
DCISIDL
r
DLOOP
CSCKD
CSCKE
DCICON2
0282
r
r
r
r
BLEN1
BLEN0
r
DCICON3
0284
r
r
r
r
DCISTAT
0286
r
r
r
r
TSCON
0288
TSE
0000
RSCON
028C
RSE
0000
RXBUF0
0290
Receive 0 Data Register
uuuu
RXBUF1
0292
Receive 1 Data Register
uuuu
RXBUF2
0294
Receive 2 Data Register
uuuu
RXBUF3
0296
Receive 3 Data Register
uuuu
TXBUF0
0298
Transmit 0 Data Register
0000
TXBUF1
029A
Transmit 1 Data Register
0000
TXBUF2
029C
Transmit 2 Data Register
0000
TXBUF3
029E
Transmit 3 Data Register
0000
BCG
SLOT3
SLOT2
SLOT1
SLOT0
u = unchanged; r = reserved; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
r
r
0000
0000
r
r
ROV
RFUL
TUNF
TMPTY
0000
DS70000689D-page 65
dsPIC33EPXXXGM3XX/6XX/7XX
Legend:
COFSG3 COFSG2
SFR
Name
ADC1 AND ADC2 REGISTER MAP
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADC1BUF0
0300
ADC1 Data Buffer 0
xxxx
ADC1BUF1
0302
ADC1 Data Buffer 1
xxxx
ADC1BUF2
0304
ADC1 Data Buffer 2
xxxx
ADC1BUF3
0306
ADC1 Data Buffer 3
xxxx
ADC1BUF4
0308
ADC1 Data Buffer 4
xxxx
ADC1BUF5
030A
ADC1 Data Buffer 5
xxxx
ADC1BUF6
030C
ADC1 Data Buffer 6
xxxx
ADC1BUF7
030E
ADC1 Data Buffer 7
xxxx
ADC1BUF8
0310
ADC1 Data Buffer 8
xxxx
ADC1BUF9
0312
ADC1 Data Buffer 9
xxxx
ADC1BUFA
0314
ADC1 Data Buffer 10
xxxx
ADC1BUFB
0316
ADC1 Data Buffer 11
xxxx
ADC1BUFC
0318
ADC1 Data Buffer 12
xxxx
ADC1BUFD
031A
ADC1 Data Buffer 13
xxxx
ADC1BUFE
031C
ADC1 Data Buffer 14
xxxx
ADC1BUFF
031E
ADC1 Data Buffer 15
AD1CON1
0320 ADON
AD1CON2
0322 VCFG2 VCFG1
AD1CON3
0324
AD1CHS123 0326
—
ADSIDL
ADDMABM
—
AD12B
FORM1
FORM0
VCFG0
OFFCAL
—
CSCNA
CHPS1
CHPS0
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADRC
—
—
—
—
—
—
CH0SB5
CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0
SAMP
DONE
0000
SMPI4
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
ADCS7 ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
0000
BUFS
—
—
—
CH0NA
—
CH0SA5
CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0
2013-2014 Microchip Technology Inc.
AD1CSSL
0330
CSS
AD1CON4
0332
ADC2BUF0
0340
ADC2 Data Buffer 0
xxxx
ADC2BUF1
0342
ADC2 Data Buffer 1
xxxx
ADC2BUF2
0344
ADC2 Data Buffer 2
xxxx
ADC2BUF3
0346
ADC2 Data Buffer 3
xxxx
ADC2BUF4
0348
ADC2 Data Buffer 4
xxxx
ADC2BUF5
034A
ADC2 Data Buffer 5
xxxx
ADC2BUF6
034C
ADC2 Data Buffer 6
xxxx
ADC2BUF7
034E
ADC2 Data Buffer 7
xxxx
ADC2BUF8
0350
ADC2 Data Buffer 8
xxxx
Legend:
Note 1:
—
—
ADDMAEN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bits 13 and bit 5 are reserved in the AD2CHS0 register, unlike the AD1CHS0 register.
—
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
0000
CSS
—
CH0SB0
ASAM
032E
—
CH0SB1
SIMSAM
AD1CSSH
—
CH0SB2
SSRCG
0328 CH0NB
—
CH0SB3
SSRC0
AD1CHS0
—
CH0SB4
xxxx
SSRC2 SSRC1
0000
0000
0000
—
—
—
—
DMABL2
DMABL1
DMABL0
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 66
TABLE 4-22:
2013-2014 Microchip Technology Inc.
TABLE 4-22:
SFR
Name
ADC1 AND ADC2 REGISTER MAP (CONTINUED)
Addr. Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADC2BUF9
0352
ADC2 Data Buffer 9
xxxx
ADC2BUFA
0354
ADC2 Data Buffer 10
xxxx
ADC2BUFB
0356
ADC2 Data Buffer 11
xxxx
ADC2BUFC
0358
ADC2 Data Buffer 12
xxxx
ADC2BUFD
035A
ADC2 Data Buffer 13
xxxx
ADC2BUFE
035C
ADC2 Data Buffer 14
xxxx
ADC2BUFF
035E
ADC2 Data Buffer 15
AD2CON1
0360 ADON
AD2CON2
0362 VCFG2 VCFG1
AD2CON3
0364
AD2CHS123 0366
—
ADSIDL
ADDMABM
—
AD12B
FORM1
FORM0
VCFG0
OFFCAL
—
CSCNA
CHPS1
CHPS0
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADRC
—
—
—
—
—
—
CH0SB5(1)
CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0
SAMP
DONE
0000
SMPI4
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
ADCS7 ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
0000
BUFS
—
—
—
CH0NA
—
CH0SA5(1)
AD2CSSL
0370
CSS
AD2CON4
0372
Legend:
Note 1:
—
—
ADDMAEN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bits 13 and bit 5 are reserved in the AD2CHS0 register, unlike the AD1CHS0 register.
—
CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
0000
0000
0000
0000
—
—
—
—
DMABL2
DMABL1
DMABL0
0000
DS70000689D-page 67
dsPIC33EPXXXGM3XX/6XX/7XX
CSS
—
CH0SB0
ASAM
036E
—
CH0SB1
SIMSAM
AD2CSSH
—
CH0SB2
SSRCG
0368 CH0NB
—
CH0SB3
SSRC0
AD2CHS0
—
CH0SB4
xxxx
SSRC2 SSRC1
CAN1 REGISTER MAP WHEN WIN (C1CTRL) = 0 OR 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1)
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
C1CTRL1
0400
—
—
CSIDL
ABAT
CANCKS
REQOP2
REQOP1
REQOP0
OPMODE2
OPMODE1
OPMODE0
—
CANCAP
C1CTRL2
0402
—
—
—
—
—
—
—
—
—
—
—
—
—
WIN
0480
C1VEC
0404
—
—
—
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
—
ICODE6
ICODE5
ICODE4
ICODE3
ICODE2
ICODE1
ICODE0
C1FCTRL
0406
DMABS2
DMABS1
DMABS0
—
—
—
—
—
—
—
—
FSA4
0040
FSA3
FSA2
FSA1
FSA0
C1FIFO
0408
—
—
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
—
—
FNRB5
0000
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
C1INTF
040A
—
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
0000
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
C1INTE
040C
—
—
—
—
—
—
—
—
IVRIE
WAKIE
0000
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
C1EC
040E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0
0000
0000
C1CFG1
0410
—
—
—
—
—
—
—
—
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000
C1CFG2
0412
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
SEG2PH0
SEG2PHTS
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000
C1FEN1
0414
DNCNT
0000
FLTEN
FFFF
C1FMSKSEL1 0418
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK0
0000
C1FMSKSEL2 041A
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK0
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
0000
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
TABLE 4-24:
SFR
Name
Addr.
CAN1 REGISTER MAP WHEN WIN (C1CTRL) = 0 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0400041E
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
See definition when WIN = x
C1RXFUL1
0420
RXFUL
0000
C1RXFUL2
0422
RXFUL
0000
2013-2014 Microchip Technology Inc.
C1RXOVF1
0428
RXOVF
0000
C1RXOVF2
042A
RXOVF
0000
C1TR01CON
0430
TXEN1
TXABT1
TXLARB1 TXERR1
TXREQ1
RTREN1
TX1PRI1
TX1PRI0
TXEN0
TXABAT0 TXLARB0 TXERR0
TXREQ0
RTREN0
TX0PRI1
TX0PRI0
0000
C1TR23CON
0432
TXEN3
TXABT3
TXLARB3 TXERR3
TXREQ3
RTREN3
TX3PRI1
TX3PRI0
TXEN2
TXABAT2 TXLARB2 TXERR2
TXREQ2
RTREN2
TX2PRI1
TX2PRI0
0000
C1TR45CON
0434
TXEN5
TXABT5
TXLARB5 TXERR5
TXREQ5
RTREN5
TX5PRI1
TX5PRI0
TXEN4
TXABAT4 TXLARB4 TXERR4
TXREQ4
RTREN4
TX4PRI1
TX4PRI0
0000
C1TR67CON
0436
TXEN7
TXABT7
TXLARB7 TXERR7
TXREQ7
RTREN7
TX7PRI1
TX7PRI0
TXEN6
TXABAT6 TXLARB6 TXERR6
TXREQ6
RTREN6
TX6PRI1
TX6PRI0
xxxx
C1RXD
0440
CAN1 Receive Data Word
xxxx
C1TXD
0442
CAN1 Transmit Data Word
xxxx
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 68
TABLE 4-23:
2013-2014 Microchip Technology Inc.
TABLE 4-25:
SFR
Name
Addr.
CAN1 REGISTER MAP WHEN WIN (C1CTRL) = 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0400041E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
0420
F3BP3
F3BP2
F3BP1
F3BP0
F2BP3
F2BP2
F2BP1
F2BP0
F1BP3
F1BP2
F1BP1
F1BP0
F0BP3
F0BP2
F0BP1
F0BP0
0000
C1BUFPNT2
0422
F7BP3
F7BP2
F7BP1
F7BP0
F6BP3
F6BP2
F6BP1
F6BP0
F5BP3
F5BP2
F5BP1
F5BP0
F4BP3
F4BP2
F4BP1
F4BP0
0000
C1BUFPNT3
0424
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
F9BP3
F9BP2
F9BP1
F9BP0
F8BP3
F8BP2
F8BP1
F8BP0
0000
C1BUFPNT4
0426
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1
F12BP0
0000
C1RXM0SID
0430
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM0EID
0432
C1RXM1SID
0434
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM1EID
0436
C1RXM2SID
0438
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM2EID
043A
C1RXF0SID
0440
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF0EID
0442
C1RXF1SID
0444
C1RXF1EID
0446
C1RXF2SID
0448
C1RXF2EID
044A
C1RXF3SID
044C
C1RXF3EID
044E
C1RXF4SID
0450
C1RXF4EID
0452
C1RXF5SID
0454
C1RXF5EID
0456
C1RXF6SID
0458
C1RXF6EID
045A
C1RXF7SID
045C
C1RXF7EID
045E
C1RXF8SID
0460
C1RXF8EID
0462
C1RXF9SID
0464
C1RXF9EID
0466
C1RXF10SID
0468
C1RXF10EID
046A
Legend:
Note 1:
EID
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
EID
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
xxxx
xxxx
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 69
C1BUFPNT1
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
C1RXF11SID
046C
C1RXF11EID
046E
C1RXF12SID
0470
C1RXF12EID
0472
C1RXF13SID
0474
C1RXF13EID
0476
C1RXF14SID
0478
C1RXF14EID
047A
C1RXF15SID
047C
C1RXF15EID
047E
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
EID
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
TABLE 4-26:
CAN2 REGISTER MAP WHEN WIN (C1CTRL) = 0 OR 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1)
Bit 2
Bit 1
Bit 0
All
Resets
—
—
WIN
0480
ICODE2
ICODE1
ICODE0
0040
FSA3
FSA2
FSA1
FSA0
0000
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
0000
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
0000
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
0000
2013-2014 Microchip Technology Inc.
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
C2CTRL1
0500
—
—
CSIDL
ABAT
CANCKS
REQOP2
REQOP1
REQOP0
OPMODE2
OPMODE1
OPMODE0
—
CANCAP
C2CTRL2
0502
—
—
—
—
—
—
—
—
—
—
—
C2VEC
0504
—
—
—
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
—
ICODE6
ICODE5
ICODE4
ICODE3
C2FCTRL
0506
DMABS2
DMABS1
DMABS0
—
—
—
—
—
—
—
—
FSA4
C2FIFO
0508
—
—
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
—
—
FNRB5
C2INTF
050A
—
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
C2INTE
050C
—
—
—
—
—
—
—
—
IVRIE
WAKIE
C2EC
050E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0
0000
C2CFG1
0510
—
—
—
—
—
—
—
C2CFG2
0512
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
C2FEN1
0514
—
SJW1
SEG2PH0 SEG2PHTS
DNCNT
0000
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000
FLTEN
FFFF
C2FMSKSEL1 0518
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK0
0000
C2FMSKSEL2 051A
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK0
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
0000
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 70
CAN1 REGISTER MAP WHEN WIN (C1CTRL) = 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1) (CONTINUED)
TABLE 4-25:
2013-2014 Microchip Technology Inc.
TABLE 4-27:
SFR
Name
Addr.
CAN2 REGISTER MAP WHEN WIN (C1CTRL) = 0 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0500051E
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
C2RXFUL1
0520
RXFUL
0000
C2RXFUL2
0522
RXFUL
0000
C2RXOVF1
0528
RXOVF
0000
C2RXOVF2
052A
RXOVF
0000
C2TR01CON 0530
TXEN1
TXABT1
TXLARB1
TXERR1
TXREQ1
RTREN1
TX1PRI1
TX1PRI0
TXEN0
TXABAT0 TXLARB0
TXERR0
TXREQ0
RTREN0
TX0PRI1
TX0PRI0
0000
C2TR23CON 0532
TXEN3
TXABT3
TXLARB3
TXERR3
TXREQ3
RTREN3
TX3PRI1
TX3PRI0
TXEN2
TXABAT2 TXLARB2
TXERR2
TXREQ2
RTREN2
TX2PRI1
TX2PRI0
0000
C2TR45CON 0534
TXEN5
TXABT5
TXLARB5
TXERR5
TXREQ5
RTREN5
TX5PRI1
TX5PRI0
TXEN4
TXABAT4 TXLARB4
TXERR4
TXREQ4
RTREN4
TX4PRI1
TX4PRI0
0000
C2TR67CON 0536
TXEN7
TXABT7
TXLARB7
TXERR7
TXREQ7
RTREN7
TX7PRI1
TX7PRI0
TXEN6
TXABAT6 TXLARB6
TXERR6
TXREQ6
RTREN6
TX6PRI1
TX6PRI0
xxxx
C2RXD
0540
CAN2 Receive Data Word Register
xxxx
C2TXD
0542
CAN2 Transmit Data Word Register
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
DS70000689D-page 71
dsPIC33EPXXXGM3XX/6XX/7XX
Legend:
Note 1:
SFR
Name
Addr.
CAN2 REGISTER MAP WHEN WIN (C1CTRL) = 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0500051E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
C2BUFPNT1
0520
F3BP3
F3BP2
F3BP1
F3BP0
F2BP3
F2BP2
F2BP1
F2BP0
F1BP3
F1BP2
F1BP1
F1BP0
F0BP3
F0BP2
F0BP1
F0BP0
0000
C2BUFPNT2
0522
F7BP3
F7BP2
F7BP1
F7BP0
F6BP3
F6BP2
F6BP1
F6BP0
F5BP3
F5BP2
F5BP1
F5BP0
F4BP3
F4BP2
F4BP1
F4BP0
0000
C2BUFPNT3
0524
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
F9BP3
F9BP2
F9BP1
F9BP0
F8BP3
F8BP2
F8BP1
F8BP0
0000
C2BUFPNT4
0526
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1
F12BP0
0000
C2RXM0SID
0530
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
C2RXM0EID
0532
C2RXM1SID
0534
C2RXM1EID
0536
C2RXM2SID
0538
C2RXM2EID
053A
C2RXF0SID
0540
C2RXF0EID
0542
C2RXF1SID
0544
C2RXF1EID
0546
C2RXF2SID
0548
C2RXF2EID
054A
C2RXF3SID
054C
C2RXF3EID
054E
C2RXF4SID
0550
C2RXF4EID
0552
C2RXF5SID
0554
C2RXF5EID
0556
2013-2014 Microchip Technology Inc.
C2RXF6SID
0558
C2RXF6EID
055A
C2RXF7SID
055C
C2RXF7EID
055E
C2RXF8SID
0560
C2RXF8EID
0562
C2RXF9SID
0564
C2RXF9EID
0566
C2RXF10SID
0568
C2RXF10EID
056A
Legend:
Note 1:
EID
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
EID
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
EID
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
xxxx
xxxx
SID1
SID0
—
MIDE
—
EID17
EID16
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
xxxx
xxxx
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
xxxx
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 72
TABLE 4-28:
2013-2014 Microchip Technology Inc.
TABLE 4-28:
CAN2 REGISTER MAP WHEN WIN (C1CTRL) = 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1) (CONTINUED)
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
C2RXF11SID
056C
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
C2RXF11EID
056E
C2RXF12SID
0570
C2RXF12EID
0572
C2RXF13SID
0574
C2RXF13EID
0576
C2RXF14SID
0578
C2RXF14EID
057A
C2RXF15SID
057C
C2RXF15EID
057E
Legend:
Note 1:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
EID
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
xxxx
xxxx
SID1
SID0
—
MIDE
—
EID17
EID16
EID
SID10
xxxx
xxxx
EID
SID10
xxxx
xxxx
EID
SID10
All
Resets
xxxx
xxxx
SID1
SID0
—
MIDE
—
EID17
EID16
EID
xxxx
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These registers are not present on dsPIC33EPXXXGM3XX devices.
SFR
Name
PROGRAMMABLE CRC REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
VWORD4
VWORD3
VWORD2
VWORD1
DWIDTH4 DWIDTH3 DWIDTH2
DWIDTH1
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
VWORD0 CRCFUL CRCMPT CRCISEL
CRCGO
LENDIAN
—
DWIDTH0
PLEN4
PLEN3
PLEN2
Bit 0
All
Resets
—
—
0000
PLEN1
PLEN0
0000
—
0000
Bit 1
CRCCON1
0640
CRCEN
—
CSIDL
CRCCON2
0642
—
—
—
CRCXORL
0644
CRCXORH
0646
X
0000
CRCDATL
0648
CRC Data Input Low Word Register
0000
CRCDATH
064A
CRC Data Input High Word Register
0000
CRCWDATL
064C
CRC Result Low Word Register
0000
CRCWDATH
064E
CRC Result High Word Register
0000
Legend:
—
—
X
— = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the programmable CRC module.
—
DS70000689D-page 73
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 4-29:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGM304/604 DEVICES
SFR
Name
Addr.
Bit 15
Bit 14
RPOR0
0680
—
—
RPOR1
0682
—
—
RPOR2
0684
—
RPOR3
0686
RPOR4
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 7
Bit 6
RP35R
—
—
RP20R
0000
RP37R
—
—
RP36R
0000
—
RP39R
—
—
RP38R
0000
—
—
RP41R
—
—
RP40R
0000
0688
—
—
RP43R
—
—
RP42R
0000
RPOR5
068A
—
—
RP49R
—
—
RP48R
0000
RPOR6
068C
—
—
RP55R
—
—
RP54R
0000
RPOR7
068E
—
—
RP57R
—
—
RP56R
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-31:
Bit 13
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGM306/706 DEVICES
SFR
Name
Addr.
Bit 15
Bit 14
RPOR0
0680
—
—
RPOR1
0682
—
—
RPOR2
0684
—
RPOR3
0686
RPOR4
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 5
2013-2014 Microchip Technology Inc.
Bit 6
RP35R
—
—
RP20R
0000
RP37R
—
—
RP36R
0000
—
RP39R
—
—
RP38R
0000
—
—
RP41R
—
—
RP40R
0000
0688
—
—
RP43R
—
—
RP42R
0000
RPOR5
068A
—
—
RP49R
—
—
RP48R
0000
RPOR6
068C
—
—
RP55R
—
—
RP54R
0000
RPOR7
068E
—
—
RP57R
—
—
RP56R
0000
RPOR8
0690
—
—
RP70R
—
—
RP69R
RPOR9
0692
—
—
RP97R
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
Bit 4
—
Bit 3
—
Bit 2
—
Bit 1
Bit 0
All
Resets
Bit 7
0000
—
—
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 74
TABLE 4-30:
2013-2014 Microchip Technology Inc.
TABLE 4-32:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGM310/710 DEVICES
SFR
Name
Addr.
Bit 15
Bit 14
RPOR0
0680
—
—
RPOR1
0682
—
—
RPOR2
0684
—
RPOR3
0686
RPOR4
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 6
RP35R
—
—
RP20R
0000
RP37R
—
—
RP36R
0000
—
RP39R
—
—
RP38R
0000
—
—
RP41R
—
—
RP40R
0000
0688
—
—
RP43R
—
—
RP42R
0000
RPOR5
068A
—
—
RP49R
—
—
RP48R
0000
RPOR6
068C
—
—
RP55R
—
—
RP54R
0000
RPOR7
068E
—
—
RP57R
—
—
RP56R
0000
RPOR8
0690
—
—
RP70R
—
—
RP69R
0000
RPOR9
0692
—
—
RP97R
—
—
RP81R
0000
RPOR10
0694
—
—
RP118R
—
—
RP113R
0000
RPOR11
0696
—
—
RPR125R
—
—
RPR120R
0000
RPOR12
0698
—
—
RPR127R
—
—
RPR126R
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000689D-page 75
dsPIC33EPXXXGM3XX/6XX/7XX
Bit 7
PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGM60X/7XX DEVICES
SFR
Name
Addr.
Bit 15
RPINR0
06A0
—
RPINR1
06A2
RPINR3
Bit 14
Bit 13
Bit 12
—
—
—
—
06A6
—
—
—
—
RPINR7
06AE
—
RPINR8
06B0
RPINR9
—
0000
2013-2014 Microchip Technology Inc.
INT2R
0000
—
—
—
—
—
T2CKR
0000
IC2R
—
IC1R
0000
—
IC4R
—
IC3R
0000
06B2
—
IC6R
—
IC5R
0000
RPINR10
06B4
—
IC8R
—
IC7R
0000
RPINR11
06B6
—
—
OCFAR
0000
RPINR12
06B8
—
FLT2R
—
FLT1R
0000
RPINR14
06BC
—
QEB1R
—
QEA1R
0000
RPINR15
06BE
—
HOME1R
—
INDX1R
0000
RPINR16
06C0
—
QEB2R
—
QEA2R
0000
RPINR17
06C2
—
HOME2R
—
INDX2R
0000
RPINR18
06C4
—
—
—
—
—
—
—
—
—
U1RXR
0000
RPINR19
06C6
—
—
—
—
—
—
—
—
—
U2RXR
0000
RPINR22
06CC
—
—
SDI2R
0000
RPINR23
06CE
—
—
SS2R
0000
RPINR24
06D0
—
—
CSDIR
0000
RPINR25
06D2
—
—
COFSR
0000
RPINR26
06D4
—
C2RXR
—
C1RXR
0000
RPINR27
06D6
—
U3CTSR
—
U3RXR
0000
RPINR28
06D8
—
U4CTSR
—
U4RXR
0000
RPINR29
06DA
—
SCK3R
—
SDI3R
0000
RPINR30
06DC
—
—
SS3R
RPINR37
06EA
—
SYNCI1R
—
—
—
—
RPINR38
06EC
—
DTCMP1R
—
—
—
—
RPINR39
06EE
—
DTCMP3R
—
DTCMP2R
0000
RPINR40
06F0
—
DTCMP5R
—
DTCMP4R
0000
RPINR41
06F2
—
—
DTCMP6R
0000
—
SCK2R
—
—
—
—
—
—
—
CSCKR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All
Resets
—
—
Bit 4
Bit 0
—
—
Bit 5
Bit 1
Bit 8
—
Bit 6
Bit 2
Bit 9
INT1R
Bit 7
Bit 3
Bit 10
Legend:
Bit 11
0000
—
—
—
—
0000
—
—
—
—
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 76
TABLE 4-33:
2013-2014 Microchip Technology Inc.
TABLE 4-34:
PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGM3XX DEVICES
SFR
Name
Addr.
Bit 15
RPINR0
06A0
—
RPINR1
06A2
RPINR3
Bit 14
Bit 13
Bit 12
—
—
—
—
06A6
—
—
—
—
RPINR7
06AE
—
RPINR8
06B0
RPINR9
—
0000
0000
—
—
—
—
—
T2CKR
0000
IC2R
—
IC1R
0000
—
IC4R
—
IC3R
0000
06B2
—
IC6R
—
IC5R
0000
RPINR10
06B4
—
IC8R
—
IC7R
0000
RPINR11
06B6
—
—
OCFAR
0000
RPINR12
06B8
—
FLT2R
—
FLT1R
0000
RPINR14
06BC
—
QEB1R
—
QEA1R
0000
RPINR15
06BE
—
HOME1R
—
INDX1R
0000
RPINR16
06C0
—
QEB2R
—
QEA2R
0000
RPINR17
06C2
—
HOME2R
—
INDX2R
0000
RPINR18
06C4
—
—
—
—
—
—
—
—
—
U1RXR
0000
RPINR19
06C6
—
—
—
—
—
—
—
—
—
U2RXR
0000
RPINR22
06CC
—
—
SDI2R
0000
RPINR23
06CE
—
—
SS2R
0000
RPINR24
06D0
—
—
CSDIR
0000
RPINR25
06D2
—
—
COFSR
0000
RPINR27
06D6
—
U3CTSR
—
U3RXR
0000
RPINR28
06D8
—
U4CTSR
—
U4RXR
0000
RPINR29
06DA
—
SCK3R
—
SDI3R
0000
RPINR30
06DC
—
—
SS3R
RPINR37
06EA
—
SYNCI1R
—
—
—
—
RPINR38
06EC
—
DTCMP1R
—
—
—
—
RPINR39
06EE
—
DTCMP3R
—
DTCMP2R
0000
RPINR40
06F0
—
DTCMP5R
—
DTCMP4R
0000
RPINR41
06F2
—
—
DTCMP6R
0000
SCK2R
—
—
—
—
—
—
—
CSCKR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
0000
—
—
—
—
0000
—
—
—
—
0000
DS70000689D-page 77
dsPIC33EPXXXGM3XX/6XX/7XX
INT2R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
All
Resets
—
—
Bit 4
Bit 0
—
—
Bit 5
Bit 1
Bit 8
—
Bit 6
Bit 2
Bit 9
INT1R
Bit 7
Bit 3
Bit 10
Legend:
Bit 11
SFR
Name
NVM REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
NVMCON
0728
WR
WREN
WRERR
NVMSIDL
—
—
RPDF
URERR
—
—
—
—
NVMADR
072A
NVMADRU
072C
—
—
—
—
—
—
—
—
NVMADRU
NVMKEY
072E
—
—
—
—
—
—
—
—
NVMKEY
NVMSRCADRL
0730
NVMSRCADRH
0732
Legend:
RCON
All
Resets
NVMOP0
0000
0000
0000
0000
NVMSRCADR
0
NVMSRCADRH
Addr.
Bit 15
Bit 14
Bit 13
0740
TRAPR
IOPUWR
—
COSC2
Bit 12
Bit 11
Bit 10
—
—
VREGSF
COSC1
COSC0
—
Bit 9
Bit 8
—
CM
VREGS
NOSC2
NOSC1
NOSC0
CLKDIV
0744
ROI
DOZE2
DOZE1
DOZE0
DOZEN
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on the type of Reset.
OSCCON register Reset values are dependent on the configuration fuses.
TABLE 4-37:
2013-2014 Microchip Technology Inc.
Legend:
NVMOP3 NVMOP2 NVMOP1
Bit 0
NVMADR
PLLFBD
REFOCON
Bit 1
0000
0000
SYSTEM CONTROL REGISTER MAP
OSCCON 0742
SFR
Name
Bit 2
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-36:
SFR
Name
Bit 3
Bit 7
All
Resets
POR
Note 1
Bit 5
Bit 4
Bit 3
Bit 2
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
CLKLOCK
IOLOCK
LOCK
—
CF
—
LPOSCEN
OSWEN Note 2
PLLPRE1
PLLPRE0
FRCDIV2 FRCDIV1 FRCDIV0 PLLPOST1 PLLPOST0
—
PLLPRE4 PLLPRE3 PLLPRE2
Bit 1
Bit 0
Bit 6
PLLDIV
—
—
—
0030
0030
TUN
0000
REFERENCE CLOCK REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
074E
ROON
—
ROSSLP
Bit 12
Bit 11
ROSEL RODIV3
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RODIV2
RODIV1
RODIV0
—
—
—
—
—
—
—
—
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 78
TABLE 4-35:
2013-2014 Microchip Technology Inc.
PARALLEL MASTER/SLAVE PORT REGISTER MAP(2)
TABLE 4-38:
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
PMCON
0600
PMPEN
—
PSIDL
PMMODE
0602
BUSY
IRQM1
IRQM0
PMADDR(1)
0604
CS2
CS1
Bit 12
Bit 11
Bit 10
ADRMUX1 ADRMUX0 PTBEEN
INCM1
INCM0
MODE16
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PTWREN
PTRDEN
CSF1
CSF0
ALP
CS2P
CS1P
BEP
MODE1
MODE0
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
Bit 0
All
Resets
WRSP
RDSP
0000
WAITE1
WAITE0
Bit 1
Parallel Port Address Register (ADDR)
0000
0000
PMDOUT1(1)
0604
Parallel Port Data Out Register 1 (Buffer Levels 0 and 1)
0000
PMDOUT2
0606
Parallel Port Data Out Register 2 (Buffer Levels 2 and 3)
0000
PMDIN1
0608
Parallel Port Data In Register 1 (Buffer Levels 0 and 1)
0000
PMDIN2
060A
Parallel Port Data In Register 2 (Buffer Levels 2 and 3)
0000
PMAEN
060C
PTEN
PMSTAT
060E
Legend:
Note 1:
2:
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
0000
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
Bit 2
Bit 1
Bit 0
All
Resets
0000
— = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the PMP module.
PMADDR and PMDOUT1 are the same physical register, but are defined differently depending on the module’s operating mode.
PMP is not present on 44-pin devices.
SFR
Addr.
Name
PMD REGISTER MAP FOR dsPIC33EPXXXGM6XX/7XX DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PMD1
0760
T5MD
T4MD
T3MD
T2MD
T1MD
QEIMD
PWMMD
DCIMD
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
C2MD
C1MD
AD1MD
PMD2
0762
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0764
T9MD
T8MD
T7MD
T6MD
—
CMPMD
RTCCMD(1)
PMPMD
CRCMD
DACMD
QEI2MD PWM2MD
U3MD
I2C3MD
I2C2MD
ADC2MD
0000
PMD4
0766
—
—
—
—
—
PMD6
076A
—
—
PWM6MD PWM5MD PWM4MD
—
—
—
—
—
U4MD
—
PWM3MD
PWM2MD
PWM1MD
—
—
—
—
REFOMD CTMUMD
—
—
0000
—
—
—
SPI3MD
0000
PTGMD
—
—
—
0000
DMA0MD
PMD7
076C
—
—
—
—
—
—
—
—
—
—
—
DMA1MD
DMA2MD
DMA3MD
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The RTCCMD bit is not available on 44-pin devices.
DS70000689D-page 79
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 4-39:
SFR
Addr.
Name
PMD REGISTER MAP FOR dsPIC33EPXXXGM3XX DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0760
T5MD
T4MD
T3MD
T2MD
T1MD
QEI1MD
PWMMD
DCIMD
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
—
AD1MD
0000
PMD2
0762
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0764
T9MD
T8MD
T7MD
T6MD
—
CMPMD
RTCCMD(1)
PMPMD
CRCMD
—
QEI2MD
—
U3MD
—
I2C2MD
ADC2MD
0000
PMD4
0766
—
—
—
—
—
—
—
—
—
—
U4MD
—
—
—
0000
PMD6
076A
—
—
PWM3MD
PWM2MD
PWM1MD
—
—
—
—
PWM6MD PWM5MD PWM4MD
REFOMD CTMUMD
—
—
—
SPI3MD
0000
PTGMD
—
—
—
0000
DMA0MD
PMD7
076C
—
—
—
—
—
—
—
—
—
—
—
DMA1MD
DMA2MD
DMA3MD
Legend:
Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The RTCCMD bit is not available on 44-pin devices.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 80
TABLE 4-40:
2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc.
TABLE 4-41:
SFR
Name
OP AMP/COMPARATOR REGISTER MAP
Addr. Bit 15 Bit 14 Bit 13
Bit 12
CMSTAT
0A80 PSIDL
—
—
C5EVT
CVR1CON
0A82
—
—
—
CM1CON
0A84 CON
COE
CPOL
—
—
—
—
—
CM1MSKSRC 0A86
—
—
CM1MSKCON 0A88 HLMS
—
CM1FLTR
0A8A
—
—
CM2CON
0A8C CON
COE
—
CM2MSKSRC 0A8E
—
—
OCEN OCNEN
C3OUT
C2OUT
C1OUT
0000
CVR3
CVR2
CVR1
CVR0
0000
CREF
—
—
CCH1
CCH0
0000
C1EVT
—
—
—
—
CVREN
CVROE
OPMODE
CEVT
COUT
EVPOL1
EVPOL0
—
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0
0000
ABNEN
AAEN
AANEN
0000
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
CPOL
—
—
OPMODE
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
—
—
—
OCEN OCNEN
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0
0000
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
CPOL
—
—
OPMODE
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
—
—
—
OCEN OCNEN
CM3FLTR
0A9A
—
—
CM4CON
0A9C CON
COE
—
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0
0000
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
CPOL
—
—
—
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
—
—
CM4MSKCON 0AA0 HLMS
—
OCEN OCNEN
CM4FLTR
0AA2
—
—
CM5CON
0AA4 CON
COE
—
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0
0000
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
CPOL
—
—
OPMODE
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
—
—
CM5MSKCON 0AA8 HLMS
—
OCEN OCNEN
CM5FLTR
0AAA
—
—
—
CVR2CON
0AB4
—
—
—
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0
0000
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
—
CVRR1
VREFSEL
—
—
CVREN
CVROE
CVRR0
CVRSS
CVR3
CVR2
CVR1
CVR0
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70000689D-page 81
dsPIC33EPXXXGM3XX/6XX/7XX
CM3MSKCON 0A98 HLMS
Legend:
C4OUT
C2EVT
ABEN
COE
—
C5OUT
CVRSS
C3EVT
VREFSEL
ACNEN
0A94 CON
CM5MSKSRC 0AA6
—
CVRR0
C4EVT
CVRR1
ACEN
CM3CON
—
All
Resets
PAGS
—
—
Bit 0
NAGS
—
CM4MSKSRC 0A9E
Bit 1
Bit 5
OANEN
0A92
—
Bit 2
Bit 8
OAEN
CM2FLTR
—
Bit 6
Bit 3
Bit 9
OBNEN
—
CM3MSKSRC 0A96
Bit 7
Bit 4
Bit 10
OBEN
CM2MSKCON 0A90 HLMS
—
Bit 11
SFR
Name
Addr.
CTMUCON1 033A
CTMU REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
—
—
—
—
—
—
Bit 1 Bit 0
All
Resets
—
—
0000
CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
—
—
0000
CTMUICON 033E
—
—
0000
Legend:
ITRIM5
ITRIM4
ITRIM3
ITRIM2
IRNG1
IRNG0
—
—
—
—
—
—
JTAG INTERFACE REGISTER MAP
SFR Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
JDATAH
0FF0
—
—
—
—
JDATAL
0FF2
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
JDATAH
All
Resets
xxxx
JDATAL
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-44:
File Name
Addr.
ALRMVAL
0620
ALCFGRPT
0622
RTCVAL
0624
RCFGCAL
0626
Legend:
ITRIM0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-43:
Legend:
ITRIM1
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
Alarm Value Register Window Based on ALRMPTR
AMASK0 ALRMPTR1 ALRMPTR0
ARPT7
ARPT6
xxxx
RTCC Value Register Window Based on RTCPTR
RTCEN
—
RTCWREN RTCSYNC HALFSEC
RTCOE
RTCPTR1
RTCPTR0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CAL7
CAL6
All
Resets
0000
xxxx
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 82
TABLE 4-42:
2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc.
TABLE 4-45:
SFR Name
Addr.
DMA CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
DMA0CON
0B00
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
DMA0REQ
0B02
FORCE
—
—
—
—
—
—
—
DMA0STAL
0B04
DMA0STAH
0B06
DMA0STBL
0B08
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
MODE1
MODE0
0000
IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0
00FF
Bit 7
Bit 6
—
—
Bit 5
Bit 4
AMODE1 AMODE0
STA
—
—
—
—
—
—
—
0000
—
STA
0000
STB
—
—
—
—
—
—
—
DMA0STBH
0B0A
DMA0PAD
0B0C
DMA0CNT
0B0E
—
—
DMA1CON
0B10
CHEN
SIZE
DIR
HALF
NULLW
—
—
DMA1REQ
0B12
FORCE
—
—
—
—
—
—
DMA1STAL
0B14
DMA1STAH
0B16
DMA1STBL
0B18
0000
—
STB
0000
PAD
0000
CNT
—
—
—
0000
—
AMODE1 AMODE0
—
—
MODE1
MODE0
0000
IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0
00FF
STA
—
—
—
—
—
—
—
0000
—
STA
0000
STB
—
—
—
—
—
—
—
0B1A
DMA1PAD
0B1C
DMA1CNT
0B1E
—
—
DMA2CON
0B20
CHEN
SIZE
DIR
HALF
NULLW
—
—
DMA2REQ
0B22
FORCE
—
—
—
—
—
—
DMA2STAL
0B24
DMA2STAH
0B26
DMA2STBL
0B28
—
STB
0000
PAD
0000
CNT
—
—
—
0000
—
AMODE1 AMODE0
—
—
MODE1
MODE0
0000
IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0
00FF
STA
—
—
—
—
—
—
—
0000
—
STA
0000
STB
DMA2STBH
0B2A
DMA2PAD
0B2C
DMA2CNT
0B2E
—
—
DMA3CON
0B30
CHEN
SIZE
DIR
HALF
NULLW
—
—
DMA3REQ
0B32
FORCE
—
—
—
—
—
—
DMA3STAL
0B34
DMA3STAH
0B36
DMA3STBL
0B38
—
—
—
—
—
—
—
0000
—
STB
0000
PAD
0000
CNT
—
—
—
0000
—
AMODE1 AMODE0
—
—
MODE1
MODE0
0000
IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0
00FF
STA
—
—
—
—
—
—
—
0000
—
STA
0000
STB
—
—
—
—
—
—
—
0000
—
STB
DS70000689D-page 83
DMA3STBH
0B3A
DMA3PAD
0B3C
DMA3CNT
0B3E
—
—
DMAPWC
0BF0
—
—
—
—
—
—
—
—
—
—
—
—
PWCOL3 PWCOL2 PWCOL1 PWCOL0
0000
DMARQC
0BF2
—
—
—
—
—
—
—
—
—
—
—
—
RQCOL3 RQCOL2 RQCOL1 RQCOL0
0000
DMAPPS
0BF4
—
—
—
—
—
—
—
—
—
—
—
—
DMALCA
0BF6
—
—
—
—
—
—
—
—
—
—
—
—
DSADRL
0BF8
DSADRH
0BFA
Legend:
0000
PAD
0000
CNT
0000
PPST3
DSADR
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
PPST2
PPST1
LSTCH
PPST0
0000
000F
0000
DSADR
0000
dsPIC33EPXXXGM3XX/6XX/7XX
DMA1STBH
0000
SFR
Name
Addr.
PORTA REGISTER MAP FOR dsPIC33EPXXXGM310/710 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
0E00
TRISA
—
TRISA
—
—
TRISA4
—
—
TRISA
DF9F
PORTA
0E02
RA
—
RA
—
—
RA4
—
—
RA
0000
LATA
0E04
LATA
—
LATA
—
—
LATA4
—
—
LATA
0000
ODCA
0E06
ODCA
—
ODCA
—
—
ODCA4
—
—
ODCA
0000
CNENA
0E08
CNIEA
—
CNIEA
—
—
CNIEA4
—
—
CNIEA
0000
CNPUA
0E0A
CNPUA
—
CNPUA
—
—
CNPUA4
—
—
CNPUA
0000
CNPDA
0E0C
CNPDA
—
CNPDA
—
—
CNPDA4
—
—
CNPDA
0000
ANSELA
0E0E
ANSA
—
—
—
ANSA4
—
—
ANSA
1813
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Legend:
—
ANSA9
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-47:
SFR
Name
ANSA
PORTA REGISTER MAP FOR dsPIC33EPXXXGM306/706 DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 1
Bit 0
All
Resets
TRISA
0E00
—
—
—
TRISA
—
—
TRISA4
—
—
TRISA
DF9F
PORTA
0E02
—
—
—
RA
—
—
RA4
—
—
RA
0000
LATA
0E04
—
—
—
LATA
—
—
LATA4
—
—
LATA
0000
ODCA
0E06
—
—
—
ODCA
—
—
ODCA4
—
—
ODCA
0000
CNENA
0E08
—
—
—
CNIEA
—
—
CNIEA4
—
—
CNIEA
0000
CNPUA
0E0A
—
—
—
CNPUA
—
—
CNPUA4
—
—
CNPUA
0000
CNPDA
0E0C
—
—
—
CNPDA
—
—
CNPDA4
—
—
CNPDA
0000
ANSELA
0E0E
—
—
—
—
—
ANSA4
—
—
ANSA
1813
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Legend:
—
ANSA9
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-48:
2013-2014 Microchip Technology Inc.
SFR
Name
ANSA
PORTA REGISTER MAP FOR dsPIC33EPXXXGM304/604 DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 1
Bit 0
All
Resets
TRISA
0E00
—
—
—
—
—
TRISA
—
—
TRISA
DF9F
PORTA
0E02
—
—
—
—
—
RA
—
—
RA
0000
LATA
0E04
—
—
—
—
—
LATA
—
—
LATA
0000
ODCA
0E06
—
—
—
—
—
ODCA
—
—
ODCA
0000
CNENA
0E08
—
—
—
—
—
CNIEA
—
—
CNIEA
0000
CNPUA
0E0A
—
—
—
—
—
CNPUA
—
—
CNPUA
0000
CNPDA
0E0C
—
—
—
—
—
CNPDA
—
—
CNPDA
ANSELA
0E0E
—
—
—
—
—
—
—
Legend:
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ANSA9
—
—
ANSA4
—
ANSA
0000
1813
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 84
TABLE 4-46:
2013-2014 Microchip Technology Inc.
TABLE 4-49:
SFR
Name
Addr.
PORTB REGISTER MAP FOR dsPIC33EPXXXGM310/710 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
0E10
TRISB
DF9F
PORTB
0E12
RB
xxxx
LATB
0E14
LATB
xxxx
ODCB
0E16
ODCB
0000
CNENB
0E18
CNIEB
0000
CNPUB
0E1A
CNPUB
0000
CNPDB
0E1C
CNPDB
ANSELB
0E1E
Legend:
—
—
—
—
—
ANSB
0000
—
—
—
Bit 6
Bit 5
Bit 4
ANSB
010F
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-50:
SFR
Name
—
Addr.
PORTB REGISTER MAP FOR dsPIC33EPXXXGM306/706 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0E10
TRISB
DF9F
PORTB
0E12
RB
xxxx
LATB
0E14
LATB
xxxx
ODCB
0E16
ODCB
0000
CNENB
0E18
CNIEB
0000
CNPUB
0E1A
CNPUB
0000
CNPDB
0E1C
CNPDB
ANSELB
0E1E
Legend:
—
—
—
—
—
ANSB
0000
—
—
—
Bit 6
Bit 5
Bit 4
ANSB
010F
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-51:
SFR
Name
—
Addr.
PORTB REGISTER MAP FOR dsPIC33EPXXXGM304/604 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
DS70000689D-page 85
TRISB
0E10
TRISB
FFFF
PORTB
0E12
RB
xxxx
LATB
0E14
LATB
xxxx
ODCB
0E16
ODCB
0000
CNENB
0E18
CNIEB
0000
CNPUB
0E1A
CNPUB
0000
CNPDB
0E1C
CNPDB
ANSELB
0E1E
Legend:
—
—
—
—
—
—
ANSB
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
—
—
—
ANSB
010F
dsPIC33EPXXXGM3XX/6XX/7XX
TRISB
SFR
Name
PORTC REGISTER MAP FOR dsPIC33EPXXXGM310/710 DEVICES
Bit 15
Bit 14
TRISC
0E20
TRISC15
—
TRISC
BFFF
PORTC
0E22
RC15
—
RC
xxxx
LATC
0E24
LATC15
—
LATC
xxxx
ODCC
0E26
ODCC15
—
ODCC
0000
CNENC
0E28
CNIEC15
—
CNIEC
0000
CNPUC
0E2A CNPUC15
—
CNPUC
0000
CNPDC
0E2C CNPDC15
—
CNPDC
ANSELC
0E2E
—
Legend:
Bit 12
—
Bit 11
Bit 10
ANSC
Bit 9
—
Bit 8
Bit 7
—
Bit 6
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000
—
ANSC
0807
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-53:
SFR
Name
—
Bit 13
All
Resets
Addr.
PORTC REGISTER MAP FOR dsPIC33EPXXXGM306/706 DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
0E20
TRISC15
—
TRISC
BFFF
PORTC
0E22
RC15
—
RC
xxxx
LATC
0E24
LATC15
—
LATC
xxxx
ODCC
0E26
ODCC15
—
ODCC
0000
CNENC
0E28
CNIEC15
—
CNIEC
0000
CNPUC
0E2A CNPUC15
—
CNPUC
0000
CNPDC
0E2C CNPDC15
—
CNPDC
ANSELC
0E2E
—
Legend:
—
—
—
—
0000
—
ANSC
0807
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-54:
2013-2014 Microchip Technology Inc.
SFR
Name
—
PORTC REGISTER MAP FOR dsPIC33EPXXXGM304/604 DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
0E20
—
—
—
—
—
—
TRISC
BFFF
PORTC
0E22
—
—
—
—
—
—
RC
xxxx
LATC
0E24
—
—
—
—
—
—
LATC
xxxx
ODCC
0E26
—
—
—
—
—
—
ODCC
0000
CNENC
0E28
—
—
—
—
—
—
CNIEC
0000
CNPUC
0E2A
—
—
—
—
—
—
CNPUC
0000
CNPDC
0E2C
—
—
—
—
—
—
CNPDC6:0>
DCI Clock Input
CSCK
RPINR24
CSCKR
DCI Frame Synchronization Input
COFS
RPINR25
COFSR
CAN1 Receive
(2)
C1RX
RPINR26
C1RXR
CAN2 Receive
(2)
C2RX
RPINR26
C2RXR
U3RX
RPINR27
U3RXR
U3CTS
RPINR27
U3CTSR
U4RX
RPINR28
U4RXR
UART3 Receive
UART3 Clear-to-Send
UART4 Receive
U4CTS
RPINR28
U4CTSR
SPI3 Data Input
SDI3
RPINR29
SDI3R
SPI3 Clock Input
SCK3
RPINR29
SCK3R
SPI3 Slave Select
SS3
RPINR 30
SS3R
UART4 Clear-to-Send
Note 1:
2:
Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
This input is available on dsPIC33EPXXXGM6XX/7XX devices only.
2013-2014 Microchip Technology Inc.
DS70000689D-page 167
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 11-1:
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) (CONTINUED)
Input Name(1)
Function Name
Register
Configuration Bits
PWM Sync Input 1
SYNCI1
RPINR37
SYNCI1R
PWM Dead-Time Compensation 1
DTCMP1
RPINR38
DTCMP1R
PWM Dead-Time Compensation 2
DTCMP2
RPINR39
DTCMP2R
PWM Dead-Time Compensation 3
DTCMP3
RPINR39
DTCMP3R
PWM Dead-Time Compensation 4
DTCMP4
RPINR40
DTCMP4R
PWM Dead-Time Compensation 5
DTCMP5
RPINR40
DTCMP5R
PWM Dead-Time Compensation 6
DTCMP6
RPINR41
DTCMP6R
Note 1:
2:
Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
This input is available on dsPIC33EPXXXGM6XX/7XX devices only.
DS70000689D-page 168
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 11-2:
INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES
Peripheral Pin
Select Input
Register Value
Input/
Output
Pin Assignment
Peripheral Pin
Select Input
Register Value
Input/
Output
Pin Assignment
000 0000
I
VSS
010 1100
I
RPI44
(1)
000 0001
I
CMP1
010 1101
I
RPI45
000 0010
I
CMP2(1)
010 1110
I
RPI46
000 0011
I
CMP3(1)
010 1111
I
RPI47
000 0100
I
CMP4(1)
011 0000
I/O
RP48
000 0101
—
—
011 0001
I/O
RP49
000 0110
I
PTGO30(1)
011 0010
I
RPI50
000 0111
I
PTGO31(1)
011 0011
I
RPI51
000 1000
I
INDX1(1)
011 0100
I
RPI52
000 1001
I
HOME1(1)
011 0101
I
RPI53
000 1010
I
INDX2(1)
011 0110
I/O
RP54
000 1011
I
HOME2(1)
011 0111
I/O
RP55
000 1100
I
CMP5(1)
011 1000
I/O
RP56
000 1101
—
—
011 1001
I/O
RP57
000 1110
—
—
011 1010
I
RPI58
000 1111
—
—
011 1011
—
—
001 0000
I
RPI16
011 1100
I
RPI60
001 0001
I
RPI17
011 1101
I
RPI61
001 0010
I
RPI18
011 1110
—
—
001 0011
I
RPI19
011 1111
I
RPI 63
001 0100
I/O
RP20
100 0000
—
—
001 0101
—
—
100 0001
—
—
001 0110
—
—
100 0010
—
—
001 0111
—
—
100 0011
—
—
001 1000
I
RPI24
100 0100
—
—
001 1001
I
RPI25
100 0101
I/O
RP69
001 1010
—
—
100 0110
I/O
RP70
001 1011
I
RPI27
100 0111
—
—
001 1100
I
RPI28
100 1000
I
RPI72
001 1101
—
—
100 1001
—
—
001 1110
—
—
100 1010
—
—
001 1111
—
—
100 1011
—
—
010 0000
I
RPI32
100 1100
I
RPI76
010 0001
I
RPI33
100 1101
I
RPI77
010 0010
I
RPI34
100 1110
—
—
010 0011
I/O
RP35
100 1111
—
—
010 0100
I/O
RP36
101 0000
I
RPI80
010 0101
I/O
RP37
101 0001
I/O
RP81
010 0110
I/O
RP38
101 0010
—
—
010 0111
I/O
RP39
101 0011
—
—
010 1000
I/O
RP40
101 0100
—
—
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment.
2013-2014 Microchip Technology Inc.
DS70000689D-page 169
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 11-2:
INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED)
Peripheral Pin
Select Input
Register Value
Input/
Output
Pin Assignment
Peripheral Pin
Select Input
Register Value
Input/
Output
Pin Assignment
010 1001
I/O
RP41
101 0101
—
—
010 1010
I/O
RP42
101 0110
—
—
010 1011
I/O
RP43
101 0111
—
—
101 1000
—
—
110 1100
—
—
101 1001
—
—
110 1101
—
—
101 1010
—
—
110 1110
—
—
101 1011
—
—
110 1111
—
—
101 1100
—
—
111 0000
I
RPI112
101 1101
—
—
111 0001
I/O
RP113
101 1110
I
RPI94
111 0010
—
—
101 1111
I
RPI95
111 0011
—
—
110 0000
I
RPI96
111 0100
—
—
110 0001
I/O
RP97
111 0101
—
—
110 0010
—
—
111 0110
I/O
RP118
110 0011
—
—
111 0111
I
RPI119
110 0100
—
—
111 1000
I/O
RP120
110 0101
—
—
111 1001
I
RPI121
110 0110
—
—
111 1010
—
—
110 0111
—
—
111 1011
—
—
110 1000
—
—
111 1100
I
RPI124
110 1001
—
—
111 1101
I/O
RP125
110 1010
—
—
111 1110
I/O
RP126
110 1011
—
—
111 1111
I/O
RP127
Legend: Shaded rows indicate PPS Input register values that are unimplemented.
Note 1: See Section 11.4.4.1 “Virtual Connections” for more information on selecting this pin assignment.
DS70000689D-page 170
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
11.4.5
OUTPUT MAPPING
FIGURE 11-3:
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 6-bit fields, with each set associated with one RPn
pin (see Register 11-30 through Register 11-42). The
value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin
(see Table 11-3 and Figure 11-3).
A null output is associated with the output register
Reset value of ‘0’. This is done to ensure that remappable outputs remain disconnected from all output pins
by default.
MULTIPLEXING REMAPPABLE
OUTPUT FOR RPn
RPnR
Default
U1TX Output
SDO2 Output
0
1
2
Output Data
QEI1CCMP Output
REFCLKO Output
11.4.5.1
RPn
48
49
Mapping Limitations
The control schema of the peripheral select pins is not
limited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced
lockouts between any of the peripheral mapping SFRs.
Literally any combination of peripheral mappings
across any or all of the RPn pins is possible. This
includes both many-to-one and one-to-many mappings
of peripheral inputs and outputs to pins. While such
mappings may be technically possible from a configuration point of view, they may not be supportable from
an electrical point of view.
2013-2014 Microchip Technology Inc.
DS70000689D-page 171
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 11-3:
OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Function
RPnR
Output Name
Default Port
000000
RPn tied to Default Pin
U1TX
000001
RPn tied to UART1 Transmit
U2TX
000011
RPn tied to UART2 Transmit
SDO2
001000
RPn tied to SPI2 Data Output
SCK2
001001
RPn tied to SPI2 Clock Output
SS2
001010
RPn tied to SPI2 Slave Select
CSDO
001011
RPn tied to DCI Data Output
CSCK
001100
RPn tied to DCI Clock Output
COFS
001101
RPn tied to DCI Frame Sync
C1TX
001110
RPn tied to CAN1 Transmit
C2TX
001111
RPn tied to CAN2 Transmit
OC1
010000
RPn tied to Output Compare 1 Output
OC2
010001
RPn tied to Output Compare 2 Output
OC3
010010
RPn tied to Output Compare 3 Output
OC4
010011
RPn tied to Output Compare 4 Output
OC5
010100
RPn tied to Output Compare 5 Output
OC6
010101
RPn tied to Output Compare 6 Output
OC7
010110
RPn tied to Output Compare 7 Output
OC8
010111
RPn tied to Output Compare 8 Output
C1OUT
011000
RPn tied to Comparator Output 1
C2OUT
011001
RPn tied to Comparator Output 2
C3OUT
011010
RPn tied to Comparator Output 3
U3TX
011011
RPn tied to UART3 Transmit
U3RTS
011100
RPn tied to UART3 Ready-to-Send
U4TX
011101
RPn tied to UART4 Transmit
U4RTS
011110
RPn tied to UART4 Ready-to-Send
SDO3
011111
RPn tied to SPI3 Slave Output
SCK3
100000
RPn tied to SPI3 Clock Output
SS3
100001
RPn tied to SPI3 Slave Select
SYNCO1
101101
RPn tied to PWM Primary Time Base Sync Output
SYNCO2
101110
RPn tied to PWM Secondary Time Base Sync Output
QEI1CCMP
101111
RPn tied to QEI1 Counter Comparator Output
QEI2CCMP
110000
RPn tied to QEI2 Counter Comparator Output
REFCLKO
110001
RPn tied to Reference Clock Output
C4OUT
110010
RPn tied to Comparator Output 4
C5OUT
110011
RPn tied to Comparator Output 5
DS70000689D-page 172
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
11.5
High-Voltage Detect
3.
The dsPIC33EPXXXGM3XX/6XX/7XX devices contain
High-Voltage Detection (HVD) which monitors the VCAP
voltage. The HVD is used to monitor the VCAP supply
voltage to ensure that an external connection does not
raise the value above a safe level (~2.4V). If high core
voltage is detected, all I/Os are disabled and put in a
tri-state condition. The device remains in this I/O tristate condition as long as the high-voltage condition is
present.
11.6
1.
2.
I/O Helpful Tips
In some cases, certain pins, as defined in
Table 33-10 under “Injection Current”, have internal protection diodes to VDD and VSS. The term,
“Injection Current”, is also referred to as “Clamp
Current”. On designated pins with sufficient external current-limiting precautions by the user, I/O
pin input voltages are allowed to be greater or
less than the data sheet absolute maximum ratings, with respect to the VSS and VDD supplies.
Note that when the user application forward
biases either of the high or low side internal input
clamp diodes, that the resulting current being
injected into the device that is clamped internally
by the VDD and VSS power rails, may affect the
ADC accuracy by four to six counts.
I/O pins that are shared with any analog input pin
(i.e., ANx) are always analog pins by default after
any Reset. Consequently, configuring a pin as an
analog input pin automatically disables the digital
input pin buffer and any attempt to read the digital
input level by reading PORTx or LATx will always
return a ‘0’, regardless of the digital logic level on
the pin. To use a pin as a digital I/O pin on a
shared ANx pin, the user application needs to
configure the Analog Pin Configuration registers
in the I/O ports module (i.e., ANSELx) by setting
the appropriate bit that corresponds to that I/O
port pin to a ‘0’.
Note:
Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would create
signal contention between the analog
signal and the output pin driver.
2013-2014 Microchip Technology Inc.
4.
5.
Most I/O pins have multiple functions. Referring
to the device pin diagrams in this data sheet, the
priorities of the functions allocated to any pins
are indicated by reading the pin name from leftto-right. The left most function name takes
precedence over any function to its right in the
naming convention. For example: AN16/T2CK/
T7CK/RC1. This indicates that AN16 is the highest priority in this example and will supersede all
other functions to its right in the list. Those other
functions to its right, even if enabled, would not
work as long as any other function to its left was
enabled. This rule applies to all of the functions
listed for a given pin.
Each pin has an internal weak pull-up resistor
and pull-down resistor that can be configured
using the CNPUx and CNPDx registers, respectively. These resistors eliminate the need for
external resistors in certain applications. The
internal pull-up is up to ~(VDD – 0.8), not VDD.
This value is still above the minimum VIH of
CMOS and TTL devices.
When driving LEDs directly, the I/O pin can
source or sink more current than what is
specified in the VOH/IOH and VOL/IOL DC characteristic specifications. The respective IOH and
IOL current rating only applies to maintaining the
corresponding output at or above the VOH and at
or below the VOL levels. However, for LEDs,
unlike digital inputs of an externally connected
device, they are not governed by the same minimum VIH/VIL levels. An I/O pin output can safely
sink or source any current less than that listed in
the absolute maximum rating section of this data
sheet. For example:
VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V
The maximum output current sourced by any 8 mA
I/O pin = 12 mA.
LED source current < 12 mA is technically
permitted. Refer to the VOH/IOH graphs in
Section 33.0 “Electrical Characteristics” for
additional information.
DS70000689D-page 173
dsPIC33EPXXXGM3XX/6XX/7XX
6.
The Peripheral Pin Select (PPS) pin mapping
rules are as follows:
a) Only one “output” function can be active on a
given pin at any time, regardless if it is a
dedicated or remappable function (one pin,
one output).
b) It is possible to assign a “remappable output”
function to multiple pins and externally short
or tie them together for increased current
drive.
c) If any “dedicated output” function is enabled
on a pin, it will take precedence over any
remappable “output” function.
d) If any “dedicated digital” (input or output) function is enabled on a pin, any number of “input”
remappable functions can be mapped to the
same pin.
e) If any “dedicated analog” function(s) are
enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “digital output”, at the user’s cautionary discretion,
can be enabled and active as long as there is
no signal contention with an external analog
input signal. For example, it is possible for the
ADCx to convert the digital output logic level
or to toggle a digital output on a comparator or
ADCx input provided there is no external
analog input, such as for a built-in self-test.
DS70000689D-page 174
f)
g)
h)
Any number of “input” remappable functions
can be mapped to the same pin(s) at the
same time, including to any pin with a single
output from either a dedicated or remappable
“output”.
The TRIS registers control only the digital I/O
output buffer. Any other dedicated or remappable active “output” will automatically override
the TRIS setting. The TRIS register does not
control the digital logic “input” buffer. Remappable digital “inputs” do not automatically
override TRIS settings, which means that the
TRIS bit must be set to input for pins with only
remappable input function(s) assigned.
All analog pins are enabled by default after
any Reset and the corresponding digital input
buffer on the pin is disabled. Only the Analog
Pin Select registers control the digital input
buffer, not the TRIS register. The user must
disable the analog function on a pin using the
Analog Pin Select registers in order to use any
“digital input(s)” on a corresponding pin, no
exceptions.
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
11.7
Peripheral Pin Select Registers
REGISTER 11-1:
U-0
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
INT1R
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
INT1R: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7-0
Unimplemented: Read as ‘0’
2013-2014 Microchip Technology Inc.
DS70000689D-page 175
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 11-2:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
INT2R: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
DS70000689D-page 176
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 11-3:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2CKR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
T2CKR: Assign Timer2 External Clock (T2CK) to the Corresponding RPn pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
2013-2014 Microchip Technology Inc.
DS70000689D-page 177
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 11-4:
U-0
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IC2R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC1R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
IC2R: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
IC1R: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
DS70000689D-page 178
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 11-5:
U-0
RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IC4R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC3R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
IC4R: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
IC3R: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-6:
U-0
RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IC6R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC5R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
IC6R: Assign Input Capture 6 (IC6) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
IC5R: Assign Input Capture 5 (IC5) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-7:
U-0
RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IC8R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC7R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
IC8R: Assign Input Capture 8 (IC8) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
IC7R: Assign Input Capture 7 (IC7) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-8:
RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OCFAR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
OCFAR: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-9:
U-0
RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
FLT2R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT1R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
FLT2R: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
FLT1R: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-10: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
QEB1R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEA1R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
QEB1R: Assign QEI1 Phase B (QEB1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
QEA1R: Assign QEI1 Phase A (QEA1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-11: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
HOME1R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDX1R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
HOME1R: Assign QEI1 HOME (HOME1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
IND1XR: Assign QEI1 INDEX (INDX1) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-12: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
QEB2R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEA2R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
QEB2R: Assign QEI2 Phase B (QEB2) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP127
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
QEA2R: Assign A QEI2 Phase A (QEA2) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP127
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-13: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
HOME2R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDX2R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
HOME2R: Assign QEI2 HOME (HOME2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
IND2XR: Assign QEI2 INDEX (INDX2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-14: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U1RXR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
U1RXR: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
REGISTER 11-15: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2RXR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
U2RXR: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-16: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SCK2R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI2R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
SCK2R: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
SDI2R: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-17: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS2R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
SS2R: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-18: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
CSCK2R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSDIR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
CSCK2R: Assign DCI Clock Input (CSCK) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
CSDIR: Assign DCI Data Input (CSDI) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-19: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
COFSR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
COFSR: Assign DCI Frame Sync Input (COFS) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-20: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26(1)
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
C2RXR
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C1RXR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
C2RXR: Assign CAN2 RX Input (C2RX) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
C1RXR: Assign CAN1 RX Input (C1RX) to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
Note 1:
This register is not available on dsPIC33EPXXXGM3XX devices.
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REGISTER 11-21: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U3CTSR
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U3RXR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
U3CTSR: Assign UART3 Clear-to-Send (U3CTS) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
U3RXR: Assign UART3 Receive (U3RX) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-22: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U4CTSR
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U4RXR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
U4CTSR: Assign UART4 Clear-to-Send (U4CTS) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
U4RXR: Assign UART4 Receive (U4RX) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-23: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SCK3R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI3R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
SCK3R: Assign SPI3 Clock Input (SCK3) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
SDI3R: Assign SPI3 Data Input (SDI3) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-24: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS3R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
SS3R: Assign SPI3 Slave Select Input (SS3) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-25: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SYNCI1R
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
SYNCI1R: Assign PWM Synchronization Input 1 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 11-26: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP1R
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
DTCMP1R: Assign PWM Dead-Time Compensation Input 1 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 11-27: RPINR39: PERIPHERAL PIN SELECT INPUT REGISTER 39
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP3R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP2R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
DTCMP3R: Assign PWM Dead-Time Compensation Input 3 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
DTCMP2R: Assign PWM Dead-Time Compensation Input 2 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-28: RPINR40: PERIPHERAL PIN SELECT INPUT REGISTER 40
U-0
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP5R
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP4R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
DTCMP5R: Assign PWM Dead-Time Compensation Input 5 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
bit 7
Unimplemented: Read as ‘0’
bit 6-0
DTCMP4R: Assign PWM Dead-Time Compensation Input 4 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-29: RPINR41: PERIPHERAL PIN SELECT INPUT REGISTER 41
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTCMP6R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
DTCMP6R: Assign PWM Dead-Time Compensation Input 6 to the Corresponding RPn Pin bits
(see Table 11-2 for input pin selection numbers)
1111100 = Input tied to RPI124
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to VSS
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REGISTER 11-30: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP35R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP20R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP35R: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP20R: Peripheral Output Function is Assigned to RP20 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-31: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP37R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP36R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP37R: Peripheral Output Function is Assigned to RP37 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP36R: Peripheral Output Function is Assigned to RP36 Output Pin bits
(see Table 11-3 for peripheral function numbers)
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REGISTER 11-32: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP39R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP38R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP39R: Peripheral Output Function is Assigned to RP39 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP38R: Peripheral Output Function is Assigned to RP38 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-33: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP41R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP40R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP41R: Peripheral Output Function is Assigned to RP41 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP40R: Peripheral Output Function is Assigned to RP40 Output Pin bits
(see Table 11-3 for peripheral function numbers)
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REGISTER 11-34: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP43R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP42R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP43R: Peripheral Output Function is Assigned to RP43 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP42R: Peripheral Output Function is Assigned to RP42 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-35: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP49R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP48R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP49R: Peripheral Output Function is Assigned to RP49 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP48R: Peripheral Output Function is Assigned to RP48 Output Pin bits
(see Table 11-3 for peripheral function numbers)
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REGISTER 11-36: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP55R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP54R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP55R: Peripheral Output Function is Assigned to RP55 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP54R: Peripheral Output Function is Assigned to RP54 Output Pin bits
(see Table 11-3 for peripheral function numbers)
REGISTER 11-37: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP57R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP56R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP57R: Peripheral Output Function is Assigned to RP57 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP56R: Peripheral Output Function is Assigned to RP56 Output Pin bits
(see Table 11-3 for peripheral function numbers)
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REGISTER 11-38: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP70R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP69R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP70R: Peripheral Output Function is Assigned to RP70 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP69R: Peripheral Output Function is Assigned to RP69 Output Pin bits
(see Table 11-3 for peripheral function numbers)
Note 1:
This register is not available on dsPIC33EPXXXGM304/604 devices.
REGISTER 11-39: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP97R
bit 15
bit 8
U-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP81R(2)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP97R: Peripheral Output Function is Assigned to RP97 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP81R: Peripheral Output Function is Assigned to RP81 Output Pin bits(2)
(see Table 11-3 for peripheral function numbers)
Note 1:
2:
This register is not available on dsPIC33EPXXXGM304/604 devices.
These bits are not available on dsPIC33EPXXXGM306/706 devices.
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REGISTER 11-40: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP118R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP113R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP118R: Peripheral Output Function is Assigned to RP118 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP113R: Peripheral Output Function is Assigned to RP113 Output Pin bits
(see Table 11-3 for peripheral function numbers)
Note 1:
This register is not available on dsPIC33EPXXXGM30X/604/706 devices.
REGISTER 11-41: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP125R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP120R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP125R: Peripheral Output Function is Assigned to RP125 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP120R: Peripheral Output Function is Assigned to RP120 Output Pin bits
(see Table 11-3 for peripheral function numbers)
Note 1:
This register is not available on dsPIC33EPXXXGM30X/604/706 devices.
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REGISTER 11-42: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP127R
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP126R
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP127R: Peripheral Output Function is Assigned to RP127 Output Pin bits
(see Table 11-3 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP126R: Peripheral Output Function is Assigned to RP126 Output Pin bits
(see Table 11-3 for peripheral function numbers)
Note 1:
This register is not available on dsPIC33EPXXXGM30X/604/706 devices.
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NOTES:
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dsPIC33EPXXXGM3XX/6XX/7XX
12.0
The Timer1 module can operate in one of the following
modes:
TIMER1
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Timers” (DS70362),
which is available from the Microchip
web site (www.microchip.com).
•
•
•
•
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON
• Timer Synchronization Control bit (TSYNC):
T1CON
• Timer Gate Control bit (TGATE): T1CON
The Timer1 module is a 16-bit timer that can operate as
a free-running, interval timer/counter.
Timer control bit settings for different operating modes
are given in the Table 12-1.
The Timer1 module has the following unique features
over other timers:
TABLE 12-1:
• Can be operated in Asynchronous Counter mode
from an external clock source
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler
TIMER MODE SETTINGS
Mode
A block diagram of Timer1 is shown in Figure 12-1.
FIGURE 12-1:
Timer mode
Gated Timer mode
Synchronous Counter mode
Asynchronous Counter mode
TCS
TGATE
TSYNC
Timer
0
0
x
Gated Timer
0
1
x
Synchronous
Counter
1
x
1
Asynchronous
Counter
1
x
0
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Gate
Sync
Falling Edge
Detect
1
Set T1IF Flag
0
FP(1)
Prescaler
(/n)
10
T1CLK
TGATE
00
TCKPS
TMR1
Reset
x1
Prescaler
(/n)
TCKPS
Note 1:
Sync
TSYNC
Data
CLK
0
T1CK
Latch
Comparator
1
Equal
CTMU Edge
Control Logic
TGATE
TCS
PR1
FP is the peripheral clock.
2013-2014 Microchip Technology Inc.
DS70000689D-page 211
dsPIC33EPXXXGM3XX/6XX/7XX
12.1
Timer1 Control Register
REGISTER 12-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON(1)
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS1
—
TSYNC(1)
TCS(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timer1 On bit(1)
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge)
0 = Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1:
When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
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2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
13.0
TIMER2/3, TIMER4/5, TIMER6/7
AND TIMER8/9
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Timers” (DS70362),
which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON,
T5CON, T6CON, T7CON, T8CON and T9CON registers. T2CON, T4CON, T6CON and T8CON are shown
in generic form in Register 13-1. T3CON, T5CON,
T7CON and T9CON are shown in Register 13-2.
For 32-bit timer/counter operation, Timer2, Timer4,
Timer6 and Timer8 are the least significant word (lsw);
Timer3, Timer5, Timer7 and Timer9 are the most
significant word (msw) of the 32-bit timers.
Note:
The Timer2/3, Timer4/5, Timer6/7 and Timer8/9
modules are 32-bit timers, which can also be
configured as eight independent 16-bit timers with
selectable operating modes.
As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and
Timer8/9 operate in three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with All 16-Bit Operating modes (except
Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
For 32-bit operation, T3CON, T5CON,
T7CON and T9CON register control bits
are ignored. Only T2CON, T4CON,
T6CON and T8CON register control bits
are used for setup and control. Timer2,
Timer4, Timer6 and Timer8 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3, Timer5, Timer7 and
Timer9 interrupt flags.
A block diagram for an example of a 32-bit timer pair
(Timer2/3 and Timer4/5) is shown in Figure 13-3.
Note:
Only Timer2, 3, 4 and 5 can trigger a DMA
data transfer.
They also support these features:
•
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during Idle and Sleep modes
Interrupt on a 32-Bit Period Register Match
Time Base for Input Capture and Output Compare
modules
• ADC1 Event Trigger (Timer2/3 only)
2013-2014 Microchip Technology Inc.
DS70000689D-page 213
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 13-1:
TYPE B TIMER BLOCK DIAGRAM (x = 2, 4, 6 AND 8)
Gate
Sync
Falling Edge
Detect
1
Set TxIF Flag
0
FP
(1)
Prescaler
(/n)
10
TxCLK
TGATE
00
TCKPS
Reset
TMRx
Data
Latch
CLK
TxCK
Prescaler
(/n)
Sync
x1
Comparator
TGATE
TCKPS
TCS
Note 1:
Equal
PRx
FP is the peripheral clock.
FIGURE 13-2:
TYPE C TIMER BLOCK DIAGRAM (x = 3, 5, 7 AND 9)
Falling Edge
Detect
Gate
Sync
1
Set TxIF Flag
0
FP(1)
Prescaler
(/n)
10
TGATE
00
TCKPS
TMRx
Reset
Data
Latch
CLK
TxCK
Prescaler
(/n)
TCKPS
Sync
x1
Comparator
TGATE
TCS
Note 1:
2:
TxCLK
Equal
ADCx Start of
Conversion
Trigger(2)
PRx
FP is the peripheral clock.
The ADCx trigger is available on TMR3 and TMR5 only.
DS70000689D-page 214
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 13-3:
TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
Falling Edge
Detect
Gate
Sync
1
Set TyIF Flag(4)
PRx(3)
PRy(4)
0
TGATE
Equal
Comparator
FP(1)
TxCK(3)
Prescaler
(/n)
10
TCKPS
00
Prescaler
(/n)
lsw
Sync
Data
msw
TMRx(3)
ADCx(2)
TMRy(4)
Latch
CLK
Reset
x1
TMRyHLD(4)
TCKPS
TGATE
TCS
Data Bus
Note 1:
2:
3:
4:
FP is the peripheral clock.
The ADCX trigger is available only on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs.
Timerx is a Type B timer (x = 2 and 4).
Timery is a Type C timer (x = 3 and 5).
2013-2014 Microchip Technology Inc.
DS70000689D-page 215
dsPIC33EPXXXGM3XX/6XX/7XX
13.1
Timer Control Registers
REGISTER 13-1:
TxCON (T2CON, T4CON, T6CON AND T8CON) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timerx On bit
When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge)
0 = Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1:
The TxCK pin is not available on all timers. Refer to the “Pin Diagrams” section for the available pins.
DS70000689D-page 216
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 13-2:
TyCON (T3CON, T5CON, T7CON AND T9CON) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON(1)
—
TSIDL(2)
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
—
TGATE(1)
TCKPS1(1)
TCKPS0(1)
—
—
TCS(1,3)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timery On bit(1)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timery Stop in Idle Mode bit(2)
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2
Unimplemented: Read as ‘0’
bit 1
TCS: Timery Clock Source Select bit(1,3)
1 = External clock from pin, TyCK (on the rising edge)
0 = Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
x = Bit is unknown
When 32-bit operation is enabled (T2CON = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
The TyCK pin is not available on all timers. See the “Pin Diagrams” section for the available pins.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 218
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
14.0
INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Input Capture”
(DS70000352), which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 14-1:
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33EPXXXGM3XX/6XX/7XX devices support
up to eight input capture channels.
Key features of the input capture module include:
• Hardware configurable for 32-bit operation in all
modes by cascading two adjacent modules
• Synchronous and Trigger modes of output
compare operation, with up to 31 user-selectable
Trigger/Sync sources available
• A 4-level FIFO buffer for capturing and holding
timer values for several events
• Configurable interrupt generation
• Up to six clock sources available for each module,
driving a separate internal 16-bit counter
INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM
Event and
Interrupt
Logic
Edge Detect Logic
and
Clock Synchronizer
Prescaler
Counter
1:1/4/16
ICx Pin
ICI
Increment
Clock
Select
Trigger and
Sync Sources
Trigger and Reset
Sync Logic
16
ICxTMR
4-Level FIFO Buffer
16
16
SYNCSEL
Trigger(1)
ICxBUF
ICOV, ICBNE
Note 1:
Set ICxIF
PTG Trigger
Input
ICTSEL
ICx Clock
Sources
CTMU Edge
Control Logic
System Bus
The Trigger/Sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the Trigger/Sync source must be changed to another source option.
2013-2014 Microchip Technology Inc.
DS70000689D-page 219
dsPIC33EPXXXGM3XX/6XX/7XX
14.1
Input Capture Control Registers
REGISTER 14-1:
ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/HC/HS-0
R/HC/HS-0
R/W-0
R/W-0
R/W-0
—
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
ICSIDL: Input Capture x Stop in Idle Mode Control bit
1 = Input Capture x halts in CPU Idle mode
0 = Input Capture x continues to operate in CPU Idle mode
bit 12-10
ICTSEL: Input Capture x Timer Select bits
111 = Peripheral clock (FP) is the clock source of ICx
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of ICx
010 = T4CLK is the clock source of ICx
001 = T2CLK is the clock source of ICx
000 = T3CLK is the clock source of ICx
bit 9-7
Unimplemented: Read as ‘0’
bit 6-5
ICI: Number of Captures per Interrupt Select bits
(this field is not used if ICM = 001 or 111)
11 = Interrupts on every fourth capture event
10 = Interrupts on every third capture event
01 = Interrupts on every second capture event
00 = Interrupts on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input Capture x buffer overflow occurred
0 = No Input Capture x buffer overflow occurred
bit 3
ICBNE: Input Capture x Buffer Not Empty Status bit (read-only)
1 = Input Capture x buffer is not empty, at least one more capture value can be read
0 = Input Capture x buffer is empty
bit 2-0
ICM: Input Capture x Mode Select bits
111 = Input Capture x functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every edge, rising and falling (Edge Detect mode, ICI), is not used in this
mode)
000 = Input Capture x module is turned off
DS70000689D-page 220
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 14-2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
IC32(1)
bit 15
bit 8
R/W-0
R/W/HS-0
U-0
ICTRIG(2)
TRIGSTAT(3)
—
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7
bit 0
Legend:
HS = Hardware Settable
bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)(1)
1 = Odd ICx and Even ICx form a single 32-bit input capture module
0 = Cascade module operation is disabled
bit 7
ICTRIG: Input Capture x Trigger Operation Select bit(2)
1 = Input source is used to trigger the input capture timer (Trigger mode)
0 = Input source is used to synchronize the input capture timer to the timer of another module
(Synchronization mode)
bit 6
TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
bit 5
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
6:
The IC32 bit in both the Odd and Even ICx must be set to enable Cascade mode.
The input source is selected by the SYNCSEL bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL bits); it can be read, set and
cleared in software.
Do not use the ICx module as its own Sync or Trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
Each Input Capture x module (ICx) has one PTG input source. See Section 25.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO8 = IC1, IC5
PTGO9 = IC2, IC6
PTGO10 = IC3, IC7
PTGO11 = IC4, IC8
2013-2014 Microchip Technology Inc.
DS70000689D-page 221
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 14-2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
SYNCSEL: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = Capture timer is unsynchronized
11110 = Capture timer is unsynchronized
11101 = Capture timer is unsynchronized
11100 = CTMU trigger is the source for the capture timer synchronization
11011 = ADC1 interrupt is the source for the capture timer synchronization(5)
11010 = Analog Comparator 3 is the source for the capture timer synchronization(5)
11001 = Analog Comparator 2 is the source for the capture timer synchronization(5)
11000 = Analog Comparator 1 is the source for the capture timer synchronization(5)
10111 = Input Capture 8 interrupt is the source for the capture timer synchronization
10110 = Input Capture 7 interrupt is the source for the capture timer synchronization
10101 = Input Capture 6 interrupt is the source for the capture timer synchronization
10100 = Input Capture 5 interrupt is the source for the capture timer synchronization
10011 = Input Capture 4 interrupt is the source for the capture timer synchronization
10010 = Input Capture 3 interrupt is the source for the capture timer synchronization
10001 = Input Capture 2 interrupt is the source for the capture timer synchronization
10000 = Input Capture 1 interrupt is the source for the capture timer synchronization
01111 = GP Timer5 is the source for the capture timer synchronization
01110 = GP Timer4 is the source for the capture timer synchronization
01101 = GP Timer3 is the source for the capture timer synchronization
01100 = GP Timer2 is the source for the capture timer synchronization
01011 = GP Timer1 is the source for the capture timer synchronization
01010 = PTGx trigger is the source for the capture timer synchronization(6)
01001 = Capture timer is unsynchronized
01000 = Output Compare 8 is the source for the capture timer synchronization
00111 = Output Compare 7 is the source for the capture timer synchronization
00110 = Output Compare 6 is the source for the capture timer synchronization
00101 = Output Compare 5 is the source for the capture timer synchronization
00100 = Output Compare 4 is the source for the capture timer synchronization
00011 = Output Compare 3 is the source for the capture timer synchronization
00010 = Output Compare 2 is the source for the capture timer synchronization
00001 = Output Compare 1 is the source for the capture timer synchronization
00000 = Capture timer is unsynchronized
bit 4-0
Note 1:
2:
3:
4:
5:
6:
The IC32 bit in both the Odd and Even ICx must be set to enable Cascade mode.
The input source is selected by the SYNCSEL bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL bits); it can be read, set and
cleared in software.
Do not use the ICx module as its own Sync or Trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
Each Input Capture x module (ICx) has one PTG input source. See Section 25.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO8 = IC1, IC5
PTGO9 = IC2, IC6
PTGO10 = IC3, IC7
PTGO11 = IC4, IC8
DS70000689D-page 222
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
15.0
The output compare module can select one of eight
available clock sources for its time base. The module
compares the value of the timer with the value of one or
two Compare registers depending on the operating
mode selected. The state of the output pin changes
when the timer value matches the Compare register
value. The output compare module generates either a
single output pulse, or a sequence of output pulses, by
changing the state of the output pin on the compare
match events. The output compare module can also
generate interrupts on compare match events and
trigger DMA data transfers.
OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24EFamily
Reference Manual”, “Output Compare”
(DS70005157), which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 15-1:
Note:
See the “dsPIC33/PIC24 Family Reference Manual”, “Output Compare”
(DS70005157) for OCxR and OCxRS
register restrictions.
OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1
OCxCON2
OCxR
CTMU Edge
Control Logic
Rollover/Reset
OCxR Buffer
OCx Pin
Clock
Select
OCx Clock
Sources
Increment
Comparator
OCxTMR
Reset
Trigger and
Sync Sources
Trigger and
Sync Logic
Match Event
Comparator
Match
Event
Rollover
OCx Output and
Fault Logic
OCFA
Match
Event
OCxRS Buffer
SYNCSEL
Trigger(1)
OCFB
PTG Trigger Input
Rollover/Reset
OCxRS
OCx Synchronization/Trigger Event
OCx Interrupt
Reset
Note 1:
The Trigger/Sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the Trigger/Sync source must be changed to another source option.
2013-2014 Microchip Technology Inc.
DS70000689D-page 223
dsPIC33EPXXXGM3XX/6XX/7XX
15.1
Output Compare Control Registers
REGISTER 15-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
—
—
OCSIDL
OCTSEL2
OCTSEL1
OCTSEL0
—
ENFLTB
bit 15
bit 8
R/W-0
U-0
R/W-0, HSC
R/W-0, HSC
R/W-0
R/W-0
R/W-0
R/W-0
ENFLTA
—
OCFLTB
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10
OCTSEL: Output Compare x Clock Select bits
111 = Peripheral clock (FP)
110 = Reserved
101 = PTGOx clock(2)
100 = T1CLK is the clock source of OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of OCx
010 = T4CLK is the clock source of OCx
001 = T3CLK is the clock source of OCx
000 = T2CLK is the clock source of OCx
bit 9
Unimplemented: Read as ‘0’
bit 8
ENFLTB: Fault B Input Enable bit
1 = Output Compare x Fault B input (OCFB) is enabled
0 = Output Compare x Fault B input (OCFB) is disabled
bit 7
ENFLTA: Fault A Input Enable bit
1 = Output Compare x Fault A input (OCFA) is enabled
0 = Output Compare x Fault A input (OCFA) is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
OCFLTB: PWM Fault B Condition Status bit
1 = PWM Fault B condition on OCFB pin has occurred
0 = No PWM Fault B condition on OCFB pin has occurred
bit 4
OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on OCFA pin has occurred
0 = No PWM Fault A condition on OCFA pin has occurred
Note 1:
2:
OCxR and OCxRS are double-buffered in PWM mode only.
Each Output Compare x module (OCx) has one PTG clock source. See Section 25.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO4 = OC1, OC5
PTGO5 = OC2, OC6
PTGO6 = OC3, OC7
PTGO7 = OC4, OC8
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 15-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 3
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
bit 2-0
OCM: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output sets high when OCxTMR = OCxR and sets low when
OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output sets high when OCxTMR = 0 and sets low when
OCxTMR = OCxR(1)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces
OCx pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces
OCx pin high
000 = Output compare channel is disabled
Note 1:
2:
OCxR and OCxRS are double-buffered in PWM mode only.
Each Output Compare x module (OCx) has one PTG clock source. See Section 25.0 “Peripheral Trigger
Generator (PTG) Module” for more information.
PTGO4 = OC1, OC5
PTGO5 = OC2, OC6
PTGO6 = OC3, OC7
PTGO7 = OC4, OC8
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 15-2:
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
FLTMD
FLTOUT
FLTTRIEN
OCINV
—
—
—
OC32
bit 15
bit 8
R/W-0
R/W-0, HS
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
SYNCSEL3
SYNCSEL2
SYNCSEL1
SYNCSEL0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTx bit is
cleared in software and a new PWM period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts
bit 14
FLTOUT: Fault Out bit
1 = PWM output is driven high on a Fault
0 = PWM output is driven low on a Fault
bit 13
FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition
0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
bit 12
OCINV: OCx Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 11-9
Unimplemented: Read as ‘0’
bit 8
OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7
OCTRIG: OCx Trigger/Sync Select bit
1 = Triggers OCx from source designated by the SYNCSELx bits
0 = Synchronizes OCx with source designated by the SYNCSELx bits
bit 6
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5
OCTRIS: OCx Output Pin Direction Select bit
1 = Output Compare x is tri-stated
0 = Output Compare x module drives the OCx pin
Note 1:
2:
3:
Do not use the OCx module as its own synchronization or trigger source.
When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
Each Output Compare x module (OCx) has one PTG Trigger/Sync source. See Section 25.0 “Peripheral
Trigger Generator (PTG) Module” for more information.
PTGO4 = OC1, OC5
PTGO5 = OC2, OC6
PTGO6 = OC3, OC7
PTGO7 = OC4, OC8
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 15-2:
bit 4-0
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
SYNCSEL: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization
11110 = INT2 is the source for compare timer synchronization
11101 = INT1 is the source for compare timer synchronization
11100 = CTMU trigger is the source for compare timer synchronization
11011 = ADC1 interrupt is the source for compare timer synchronization
11010 = Analog Comparator 3 is the source for compare timer synchronization
11001 = Analog Comparator 2 is the source for compare timer synchronization
11000 = Analog Comparator 1 is the source for compare timer synchronization
10111 = Input Capture 8 interrupt is the source for compare timer synchronization
10110 = Input Capture 7 interrupt is the source for compare timer synchronization
10101 = Input Capture 6 interrupt is the source for compare timer synchronization
10100 = Input Capture 5 interrupt is the source for compare timer synchronization
10011 = Input Capture 4 interrupt is the source for compare timer synchronization
10010 = Input Capture 3 interrupt is the source for compare timer synchronization
10001 = Input Capture 2 interrupt is the source for compare timer synchronization
10000 = Input Capture 1 interrupt is the source for compare timer synchronization
01111 = GP Timer5 is the source for compare timer synchronization
01110 = GP Timer4 is the source for compare timer synchronization
01101 = GP Timer3 is the source for compare timer synchronization
01100 = GP Timer2 is the source for compare timer synchronization
01011 = GP Timer1 is the source for compare timer synchronization
01010 = PTGx trigger is the source for compare timer synchronization(3)
01001 = Compare timer is unsynchronized
01000 = Output Compare 8 is the source for compare timer synchronization(1,2)
00111 = Output Compare 7 is the source for compare timer synchronization(1,2)
00110 = Output Compare 6 is the source for compare timer synchronization(1,2)
00101 = Output Compare 5 is the source for compare timer synchronization(1,2)
00100 = Output Compare 4 is the source for compare timer synchronization(1,2)
00011 = Output Compare 3 is the source for compare timer synchronization(1,2)
00010 = Output Compare 2 is the source for compare timer synchronization(1,2)
00001 = Output Compare 1 is the source for compare timer synchronization(1,2)
00000 = Compare timer is unsynchronized
Note 1:
2:
3:
Do not use the OCx module as its own synchronization or trigger source.
When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
Each Output Compare x module (OCx) has one PTG Trigger/Sync source. See Section 25.0 “Peripheral
Trigger Generator (PTG) Module” for more information.
PTGO4 = OC1, OC5
PTGO5 = OC2, OC6
PTGO6 = OC3, OC7
PTGO7 = OC4, OC8
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 228
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
16.0
HIGH-SPEED PWM MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “High-Speed PWM”
(DS70645), which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXXGM3XX/6XX/7XX devices support
a dedicated Pulse-Width Modulation (PWM) module
with up to 12 outputs.
The high-speed PWMx module consists of the
following major features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Six PWM generators
Two PWM outputs per PWM generator
Individual period and duty cycle for each PWM pair
Duty cycle, dead time, phase shift and a
frequency resolution of 7.14 ns
Independent Fault and current-limit inputs for
six PWM outputs
Redundant output
Center-Aligned PWM mode
Output override control
Chop mode (also known as Gated mode)
Special Event Trigger
Prescaler for input clock
PWMxL and PWMxH output pin swapping
Independent PWM frequency, duty cycle and
phase-shift changes for each PWM generator
Dead-time compensation
Enhanced Leading-Edge Blanking (LEB)
functionality
Frequency resolution enhancement
PWM capture functionality
Note:
In Edge-Aligned PWM mode, the duty
cycle, dead time, phase shift and
frequency resolution are 7.14 ns.
The high-speed PWMx module contains up to six PWM
generators. Each PWMx generator provides two PWM
outputs: PWMxH and PWMxL. The master time base
generator provides a synchronous signal as a common
time base to synchronize the various PWM outputs.
The individual PWM outputs are available on the output
pins of the device. The input Fault signals and currentlimit signals, when enabled, can monitor and protect
the system by placing the PWM outputs into a known
“safe” state.
Each PWMx can generate a trigger to the ADCx
module to sample the analog signal at a specific
instance during the PWM period. In addition, the highspeed PWMx module also generates a Special Event
Trigger to the ADCx module, based on either of the two
master time bases.
The high-speed PWMx module can synchronize itself
with an external signal or can act as a synchronizing
source to any external device. The SYNCI1 and
SYNCI2 input pins that utilize PPS, can synchronize
the high-speed PWMx module with an external signal.
The SYNCO1 and SYNCO2 pins are output pins that
provides a synchronous signal to an external device.
Figure 16-1 illustrates an architectural overview of the
high-speed PWMx module and its interconnection with
the CPU and other peripherals.
16.1
The PWMx module incorporates multiple external Fault
inputs, which include FLT1 and FLT2. The inputs are
remappable using the PPS feature. FLT3 is available on
44-pin, 64-pin and 100-pin packages; FLT4 through FLT8
are available on specific pins on 64-pin and 100-pin
packages, and FLT32, which has been implemented with
Class B safety features, and is available on a fixed pin on
all devices.
These Faults provide a safe and reliable way to safely
shut down the PWM outputs when the Fault input is
asserted.
16.1.1
PWM FAULTS AT RESET
During any Reset event, the PWMx module maintains
ownership of the Class B Fault, FLT32. At Reset, this
Fault is enabled in Latched mode to ensure the fail-safe
power-up of the application. The application software
must clear the PWM Fault before enabling the highspeed motor control PWMx module. To clear the Fault
condition, the FLT32 pin must first be pulled high
externally or the internal pull-up resistor in the CNPUx
register can be enabled.
Note:
2013-2014 Microchip Technology Inc.
PWM Faults
The Fault mode may be changed using
the FLTMOD bits (FCLCONx),
regardless of the state of FLT32.
DS70000689D-page 229
dsPIC33EPXXXGM3XX/6XX/7XX
16.1.2
WRITE-PROTECTED REGISTERS
On dsPIC33EPXXXGM3XX/6XX/7XX devices, write
protection is implemented for the IOCONx and
FCLCONx registers. The write protection feature
prevents any inadvertent writes to these registers. This
protection feature can be controlled by the PWMLOCK
Configuration bit (FOSCSEL). The default state of
the write protection feature is enabled (PWMLOCK = 1).
The write protection feature can be disabled by
configuring: PWMLOCK = 0.
EXAMPLE 16-1:
To gain write access to these locked registers, the user
application must write two consecutive values of
0xABCD and 0x4321 to the PWMKEY register to
perform the unlock operation. The write access to the
IOCONx or FCLCONx registers must be the next SFR
access following the unlock process. There can be no
other SFR accesses during the unlock process and
subsequent write access. To write to both the IOCONx
and FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in
Example 16-1.
PWM1 WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; FLT32 pin must be pulled high externally in order to clear and disable the fault
; Writing to FCLCON1 register requires unlock sequence
mov
mov
mov
mov
mov
mov
#0xabcd, w10
#0x4321, w11
#0x0000, w0
w10, PWMKEY
w11, PWMKEY
w0, FCLCON1
;
;
;
;
;
;
Load first unlock key to w10 register
Load second unlock key to w11 register
Load desired value of FCLCON1 register in w0
Write first unlock key to PWMKEY register
Write second unlock key to PWMKEY register
Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov
mov
mov
mov
mov
mov
#0xabcd, w10
#0x4321, w11
#0xF000, w0
w10, PWMKEY
w11, PWMKEY
w0, IOCON1
DS70000689D-page 230
;
;
;
;
;
;
Load first unlock key to w10 register
Load second unlock key to w11 register
Load desired value of IOCON1 register in w0
Write first unlock key to PWMKEY register
Write second unlock key to PWMKEY register
Write desired value to IOCON1 register
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 16-1:
HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW
SYNCI1
Data Bus
FOSC
Master Time Base
Synchronization Signal
PWM1 Interrupt
SYNCO1
PWM1H
PWM
Generator 1
PWM1L
Fault, Current-Limit
and Dead-Time Compensation
Synchronization Signal
CPU
PWM2-PWM5
Interrupt
PWM
Generator 2
through
Generator 5
PWM2H-PWM5H
PWM2L-PWM5L
Fault, Current-Limit
and Dead-Time Compensation
Synchronization Signal
PWM6 Interrupt
PWM6H
PWM
Generator 6
Primary Trigger
ADCx Module Primary Special
Event Trigger
PWM6L
Fault, Current-Limit and
Dead-Time Compensation
FLT1-FLT8, FLT32
DTCMP1-DTCMP6
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DS70000689D-page 231
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 16-2:
HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM
FOSC
PTCON, PTCON2
SYNCI1
Module Control and Timing
PTPER
SEVTCMP
Comparator
Comparator
SYNCO1
Special Event Compare Trigger
Special Event
Postscaler
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
PMTMR
PTPER
Comparator
Primary Master Time Base
SYNCO2
Special Event Compare Trigger
SEVTCMP
Special Event
Postscaler
Comparator
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
PMTMR
Duty Cycle Register
PDCx
PWM Generator 1
MUX
Master Period
Synchronization
16-Bit Data Bus
Master Duty Cycle
MDC
Secondary Master Time Base
PWM Output Mode
Control Logic
Comparator
PWMCAPx
ADCx Trigger
PTMRx
Comparator
Current-Limit
Override Logic
TRIGx
Fault Override Logic
PHASEx
SDCx
User Override Logic
Dead-Time
Logic
Pin
Control
Logic
PWM1H
PWM1L
Secondary PWM
MUX
Interrupt
Logic
STMRx
Master Period
SPHASEx
Master Duty Cycle
Synchronization
Comparator
PWMCONx
Fault and
Current-Limit
Logic
FCLCONx
TRGCONx
FLT1
DTCMP1
IOCONx
LEBCONx
ALTDTRx
DTRx
PWMxH
PWM Generator 2-PWM Generator 6
PWMxL
FLTx
DTCMPx
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dsPIC33EPXXXGM3XX/6XX/7XX
16.2
PWMx Control Registers
REGISTER 16-1:
R/W-0
PTCON: PWMx TIME BASE CONTROL REGISTER
U-0
PTEN
R/W-0
—
HS/HC-0
PTSIDL
R/W-0
SESTAT
R/W-0
R/W-0
(1)
SEIEN
R/W-0
(1)
EIPU
SYNCPOL
SYNCOEN(1)
bit 15
bit 8
R/W-0
R/W-0
(1)
SYNCEN
R/W-0
(1)
SYNCSRC2
R/W-0
(1)
SYNCSRC1
R/W-0
(1)
SYNCSRC0
R/W-0
(1)
SEVTPS3
R/W-0
(1)
R/W-0
(1)
SEVTPS2
SEVTPS1
SEVTPS0(1)
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PTEN: PWMx Module Enable bit
1 = PWMx module is enabled
0 = PWMx module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
PTSIDL: PWMx Time Base Stop in Idle Mode bit
1 = PWMx time base halts in CPU Idle mode
0 = PWMx time base runs in CPU Idle mode
bit 12
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10
EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWMx cycle boundaries
bit 9
SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCI1/SYNCO1 polarity is inverted (active-low)
0 = SYNCI1/SYNCO1 is active-high
bit 8
SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
Note 1:
2:
x = Bit is unknown
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2013-2014 Microchip Technology Inc.
DS70000689D-page 233
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-1:
PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)
bit 6-4
SYNCSRC: Synchronous Source Selection bits(1)
111 = Reserved
•
•
•
100 = Reserved
011 = PTGO17(2)
010 = PTGO16(2)
001 = Reserved
000 = SYNCI1
bit 3-0
SEVTPS: PWMx Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates Special Event Trigger on every compare match event
Note 1:
2:
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
DS70000689D-page 234
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-2:
PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
PCLKDIV(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
PCLKDIV: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64
101 = Divide-by-32
100 = Divide-by-16
011 = Divide-by-8
010 = Divide-by-4
001 = Divide-by-2
000 = Divide-by-1, maximum PWMx timing resolution (power-on default)
Note 1:
x = Bit is unknown
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
2013-2014 Microchip Technology Inc.
DS70000689D-page 235
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-3:
R/W-1
PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PTPER
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
PTPER
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PTPER: Primary Master Time Base (PMTMR) Period Value bits
REGISTER 16-4:
R/W-0
SEVTCMP: PWMx PRIMARY SPECIAL EVENT COMPARE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
SEVTCMP: Special Event Compare Count Value bits
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2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-5:
STCON: PWMx SECONDARY TIME BASE CONTROL REGISTER
U-0
U-0
U-0
HS/HC-0
R/W-0
R/W-0
—
—
—
SESTAT
SEIEN
EIPU(1)
R/W-0
R/W-0
SYNCPOL(1) SYNCOEN(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCEN(1) SYNCSRC2(1) SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1)
R/W-0
SEVTPS0(1)
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10
EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9
SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCI2/SYNCO2 polarity is inverted (active-low)
0 = SYNCI2/SYNCO2 is active-high
bit 8
SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4
SYNCSRC: Synchronous Source Selection bits(1)
111 = Reserved
•
•
•
100 = Reserved
011 = PTGO17(2)
010 = PTGO16(2)
001 = Reserved
000 = SYNCI1
Note 1:
2:
x = Bit is unknown
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
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REGISTER 16-5:
STCON: PWMx SECONDARY TIME BASE CONTROL REGISTER (CONTINUED)
SEVTPS: PWMx Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates the Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates the Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates the Special Event Trigger on every compare match event
bit 3-0
Note 1:
2:
These bits should be changed only when PTEN = 0. In addition, when using the SYNCI1 feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
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REGISTER 16-6:
STCON2: PWMx SECONDARY MASTER CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
PCLKDIV(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
PCLKDIV: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64
101 = Divide-by-32
100 = Divide-by-16
011 = Divide-by-8
010 = Divide-by-4
001 = Divide-by-2
000 = Divide-by-1, maximum PWMx timing resolution (power-on default)
Note 1:
x = Bit is unknown
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
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REGISTER 16-7:
R/W-1
STPER: PWMx SECONDARY MASTER TIME BASE PERIOD REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
STPER
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
STPER
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
STPER: PWMx Secondary Master Time Base (PMTMR) Period Value bits
REGISTER 16-8:
R/W-0
SSEVTCMP: PWMx SECONDARY SPECIAL EVENT COMPARE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
SSEVTCMP: PWMx Secondary Special Event Compare Count Value bits
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REGISTER 16-9:
CHOP: PWMx CHOP CLOCK GENERATOR REGISTER
R/W-0
U-0
U-0
U-0
U-0
U-0
CHPCLKEN
—
—
—
—
—
R/W-0
R/W-0
CHOPCLK9 CHOPCLK8
bit 15
bit 8
R/W-0
CHOPCLK7
R/W-0
R/W-0
R/W-0
R/W-0
CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3
R/W-0
CHOPCLK2
R/W-0
R/W-0
CHOPCLK1 CHOPCLK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10
Unimplemented: Read as ‘0’
bit 9-0
CHOPCLK: Chop Clock Divider bits
The frequency of the chop clock signal is given by the following expression:
Chop Frequency = (FP/PCLKDIV)/(CHOP + 1)
REGISTER 16-10: MDC: PWMx MASTER DUTY CYCLE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
MDC: PWMx Master Duty Cycle Value bits
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REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0
FLTSTAT
(1)
HS/HC-0
CLSTAT(1)
HS/HC-0
TRGSTAT
R/W-0
FLTIEN
R/W-0
CLIEN
R/W-0
R/W-0
R/W-0
TRGIEN
ITB(2)
MDCS(2)
bit 15
bit 8
R/W-0
R/W-0
DTC1
DTC0
R/W-0
DTCP
(3)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
MTBS
CAM(2,4)
XPRES(5)
IUE(2)
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting: FLTIEN = 0.
bit 14
CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting: CLIEN = 0.
bit 13
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting: TRGIEN = 0.
bit 12
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9
ITB: Independent Time Base Mode bit(2)
1 = PHASEx register provides the time base period for this PWMx generator
0 = PTPER register provides timing for this PWMx generator
bit 8
MDCS: Master Duty Cycle Register Select bit(2)
1 = MDC register provides duty cycle information for this PWMx generator
0 = PDCx register provides duty cycle information for this PWMx generator
Note 1:
2:
3:
4:
5:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
These bits should not be changed after the PWMx is enabled (PTEN = 1).
DTC = 11 for DTCP to be effective; otherwise, DTCP is ignored.
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
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REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
bit 7-6
DTC: Dead-Time Control bits
11 = Dead-Time Compensation mode
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all Output modes
bit 5
DTCP: Dead-Time Compensation Polarity bit(3)
When Set to ‘1’:
If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.
If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
When Set to ‘0’:
If DTCMPx = 0, PWMHx is shortened and PWMLx is lengthened.
If DTCMPx = 1, PWMLx is shortened and PWMHx is lengthened.
bit 4
Unimplemented: Read as ‘0’
bit 3
MTBS: Master Time Base Select bit
1 = PWMx generator uses the secondary master time base for synchronization and as the clock
source for the PWMx generation logic (if secondary time base is available)
0 = PWMx generator uses the primary master time base for synchronization and as the clock source
for the PWMx generation logic
bit 2
CAM: Center-Aligned Mode Enable bit(2,4)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1
XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWMx generator if it is in Independent Time Base
mode
0 = External pins do not affect the PWMx time base
bit 0
IUE: Immediate Update Enable bit(2)
1 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are immediate
0 = Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are synchronized to the
PWMx period boundary
Note 1:
2:
3:
4:
5:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
These bits should not be changed after the PWMx is enabled (PTEN = 1).
DTC = 11 for DTCP to be effective; otherwise, DTCP is ignored.
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
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REGISTER 16-12: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PDCx: PWMx Generator # Duty Cycle Value bits
REGISTER 16-13: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
SDCx: Secondary Duty Cycle bits for PWMxL Output Pin bits
The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle.
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REGISTER 16-14: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PHASEx: Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits
Note 1: If ITB (PWMCONx) = 0, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output mode (PMOD (IOCONx) = 00, 01 or 10),
PHASEx = Phase-shift value for PWMxH and PWMxL outputs.
2: If ITB (PWMCONx) = 1, the following applies based on the mode of operation:
Complementary, Redundant and Push-Pull Output mode (PMOD (IOCONx) = 00, 01 or 10),
PHASEx = Independent Time Base Period Value for PWMxH and PWMxL.
REGISTER 16-15: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
SPHASEx: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
If ITB (PWMCONx) = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD (IOCONx) = 00, 01
or 10), SPHASEx = Not used.
• True Independent Output mode (PMOD (IOCONx) = 11), SPHASEx = Phase-Shift
Value for PWMxL only.
If ITB (PWMCONx) = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD (IOCONx) = 00, 01
or 10), SPHASEx = Not used.
• True Independent Output mode (PMOD (IOCONx) = 11),
SPHASEx = Independent Time Base Period Value for PWMxL only.
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REGISTER 16-16: DTRx: PWMx DEAD-TIME REGISTER
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-0
DTRx: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 16-17: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-0
ALTDTRx: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
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REGISTER 16-18: TRGCONx: PWMx TRIGGER CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
TRGDIV3
TRGDIV2
TRGDIV1
TRGDIV0
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
(1)
TRGSTRT5
R/W-0
(1)
TRGSTRT5
R/W-0
(1)
TRGSTRT5
R/W-0
(1)
TRGSTRT5
R/W-0
(1)
TRGSTRT5
TRGSTRT5(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
TRGDIV: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event
1110 = Trigger output for every 15th trigger event
1101 = Trigger output for every 14th trigger event
1100 = Trigger output for every 13th trigger event
1011 = Trigger output for every 12th trigger event
1010 = Trigger output for every 11th trigger event
1001 = Trigger output for every 10th trigger event
1000 = Trigger output for every 9th trigger event
0111 = Trigger output for every 8th trigger event
0110 = Trigger output for every 7th trigger event
0101 = Trigger output for every 6th trigger event
0100 = Trigger output for every 5th trigger event
0011 = Trigger output for every 4th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 11-6
Unimplemented: Read as ‘0’
bit 5-0
TRGSTRT: Trigger Postscaler Start Enable Select bits(1)
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled
000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled
000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1:
The secondary PWM generator cannot generate PWM trigger interrupts.
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REGISTER 16-19: IOCONx: PWMx I/O CONTROL REGISTER(2)
R/W-1
R/W-1
PENH
PENL
R/W-0
POLH
R/W-0
R/W-0
POLL
PMOD1
(1)
R/W-0
PMOD0
(1)
R/W-0
R/W-0
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVRDAT1
OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PENH: PWMxH Output Pin Ownership bit
1 = PWMx module controls the PWMxH pin
0 = GPIO module controls the PWMxH pin
bit 14
PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls the PWMxL pin
0 = GPIO module controls the PWMxL pin
bit 13
POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12
POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10
PMOD: PWMx # I/O Pin Mode bits(1)
11 = PWMx I/O pin pair is in the True Independent Output mode
10 = PWMx I/O pin pair is in Push-Pull Output mode
01 = PWMx I/O pin pair is in Redundant Output mode
00 = PWMx I/O pin pair is in Complementary Output mode
bit 9
OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT controls the output on the PWMxH pin
0 = PWMx generator controls the PWMxH pin
bit 8
OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT controls the output on the PWMxL pin
0 = PWMx generator controls the PWMxL pin
bit 7-6
OVRDAT: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, PWMxH is driven to the state specified by OVRDAT.
If OVERENL = 1, PWMxL is driven to the state specified by OVRDAT.
bit 5-4
FLTDAT: Data for PWMxH and PWMxL Pins if FLTMOD is Enabled bits
If Fault is active, PWMxH is driven to the state specified by FLTDAT.
If Fault is active, PWMxL is driven to the state specified by FLTDAT.
bit 3-2
CLDAT: Data for PWMxH and PWMxL Pins if CLMOD is Enabled bits
If current limit is active, PWMxH is driven to the state specified by CLDAT.
If current limit is active, PWMxL is driven to the state specified by CLDAT.
Note 1:
2:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
If the PWMLOCK Configuration bit (FOSCSEL) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
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REGISTER 16-19: IOCONx: PWMx I/O CONTROL REGISTER(2) (CONTINUED)
bit 1
SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0
OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT bits are synchronized to the PWM time base
0 = Output overrides via the OVDDAT bits occur on the next CPU clock boundary
Note 1:
2:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
If the PWMLOCK Configuration bit (FOSCSEL) is a ‘1’, the IOCONx register can only be written after
the unlock sequence has been executed.
REGISTER 16-20: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
TRGCMP: Trigger Control Value bits
When the primary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADCx module.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-21: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFLTMOD
CLSRC4
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL(1)
CLMOD
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
FLTSRC4
FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL(1)
FLTMOD1
FLTMOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IFLTMOD: Independent Fault Mode Enable bit
1 = Independent Fault mode is enabled
0 = Independent Fault mode is disabled
bit 14-10
CLSRC: Current-Limit Control Signal Source Select for the PWMx Generator # bits
11111 = Fault 32
11110 = Reserved
•
•
•
01100 = Op Amp/Comparator 5
01011 = Comparator 4
01010 = Op Amp/Comparator 3
01001 = Op Amp/Comparator 2
01000 = Op Amp/Comparator 1
00111 = Fault 8
00110 = Fault 7
00101 = Fault 6
00100 = Fault 5
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1
bit 9
CLPOL: Current-Limit Polarity for PWMx Generator # bit(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8
CLMOD: Current-Limit Mode Enable for PWMx Generator # bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-21: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED)
bit 7-3
FLTSRC: Fault Control Signal Source Select for PWMx Generator # bits
11111 = Fault 32 (default)
11110 = Reserved
•
•
•
01100 = Op Amp/Comparator 5
01011 = Comparator 4
01010 = Op Amp/Comparator 3
01001 = Op Amp/Comparator 2
01000 = Op Amp/Comparator 1
00111 = Fault 8
00110 = Fault 7
00101 = Fault 6
00100 = Fault 5
00011 = Fault 4
00010 = Fault 3
00001 = Fault 2
00000 = Fault 1
bit 2
FLTPOL: Fault Polarity for PWMx Generator # bit(1)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0
FLTMOD: Fault Mode for PWMx Generator # bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
00 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (latched condition)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-22: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER x
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
PHR
PHF
PLR
PLF
FLTLEBEN
CLLEBEN
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
BCH(1)
BCL(1)
BPHH
BPHL
BPLH
BPLL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxH
bit 14
PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxH
bit 13
PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxL
bit 12
PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxL
bit 11
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected Fault input
0 = Leading-Edge Blanking is not applied to the selected Fault input
bit 10
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected current-limit input
0 = Leading-Edge Blanking is not applied to the selected current-limit input
bit 9-6
Unimplemented: Read as ‘0’
bit 5
BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is high
0 = No blanking when selected blanking signal is high
bit 4
BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when selected blanking signal is low
0 = No blanking when selected blanking signal is low
bit 3
BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is high
0 = No blanking when PWMxH output is high
bit 2
BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxH output is low
0 = No blanking when PWMxH output is low
bit 1
BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is high
0 = No blanking when PWMxL output is high
bit 0
BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when PWMxL output is low
0 = No blanking when PWMxL output is low
Note 1:
The blanking signal is selected via the BLANKSELx bits in the AUXCONx register.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-23: LEBDLYx: LEADING-EDGE BLANKING DELAY REGISTER x
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
LEB
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEB
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-0
LEB: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-24: AUXCONx: PWMx AUXILIARY CONTROL REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
CHOPSEL3 CHOPSEL2 CHOPSEL1
R/W-0
R/W-0
R/W-0
CHOPSEL0
CHOPHEN
CHOPLEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
BLANKSEL: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1001 = Reserved
•
•
•
0110 = PWM6H is selected as state blank source
0101 = PWM5H is selected as state blank source
0100 = PWM4H is selected as state blank source
0011 = PWM3H is selected as state blank source
0010 = PWM2H is selected as state blank source
0001 = PWM1H is selected as state blank source
0000 = No state blanking
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHOPSEL: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (CHOP) the selected PWMx outputs.
1001 = Reserved
•
•
•
0110 = PWM6H is selected as state blank source
0101 = PWM5H is selected as state blank source
0100 = PWM4H is selected as state blank source
0011 = PWM3H is selected as CHOP clock source
0010 = PWM2H is selected as CHOP clock source
0001 = PWM1H is selected as CHOP clock source
0000 = Chop clock generator is selected as CHOP clock source
bit 1
CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0
CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 16-25: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
(1,2)
PWMCAPx
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
PWMCAPx
R-0
R-0
R-0
(1,2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PWMCAPx: PWMx Captured Time Base Value bits(1,2)
The value in this register represents the captured PWMx time base value when a leading edge is
detected on the current-limit input.
The capture feature is only available on a primary output (PWMxH).
This feature is active only after LEB processing on the current-limit input signal is complete.
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dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 256
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
17.0
QUADRATURE ENCODER
INTERFACE (QEI) MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Quadrature
Encoder Interface (QEI)” (DS70601)
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This chapter describes the Quadrature Encoder Interface (QEI) module and associated operational modes.
The QEI module provides the interface to incremental
encoders for obtaining mechanical position data.
The operational features of the QEI module include:
•
•
•
•
•
•
•
•
•
•
•
32-Bit Position Counter
32-Bit Index Pulse Counter
32-Bit Interval Timer
16-Bit Velocity Counter
32-Bit Position Initialization/Capture/Compare
High Register
32-Bit Position Compare Low Register
x4 Quadrature Count mode
External Up/Down Count mode
External Gated Count mode
External Gated Timer mode
Internal Timer mode
Figure 17-1 illustrates the QEIx block diagram.
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DS70000689D-page 257
QEIx BLOCK DIAGRAM
FLTREN
GATEN
FHOMEx
HOMEx
DIR_GATE
FP
QFDIV
INDXx
1
COUNT
COUNT_EN
EXTCNT
0
DIVCLK
FINDXx
CCM
Digital
Filter
Quadrature
Decoder
Logic
QEBx
DIR
DIR_GATE
COUNT
CNT_DIR
1’b0
DIR
CNTPOL
EXTCNT
QEAx
DIR_GATE
PCHGE
PCLLE
CNTCMPx
PCLLE
PCHEQ
PCLEQ
PCHGE
32-Bit Less Than
or Equal Comparator
OUTFNC
32-Bit Greater Than
or Equal Comparator
PCLLE
FP
INTDIV
DIVCLK
32-Bit Less Than or Equal
Compare Register
(QEI1LEC)
COUNT_EN
2013-2014 Microchip Technology Inc.
(INDXxCNT)
32-Bit Index Counter Register
FINDXx
INDXxCNTH INDXxCNTL
CNT_DIR
POSxCNTH POSxCNTL
CNT_DIR
CNT_DIR COUNT_EN
16-Bit Index Counter
Hold Register
(INDXxHLD)
32-Bit Interval Timerx
Hold Register
(INTxHLD)
16-Bit Velocity
Counter Register
(VELxCNT)
Data Bus
Note 1:
32-Bit Greater Than or Equal
Compare Register
(QEI1GEC)(1)
(POSxCNT)
32-Bit Position Counter Register
COUNT_EN
32-Bit Interval
Timerx Register
(INTxTMR)
PCHGE
These registers map to the same memory location.
16-Bit Position Counter
Hold Register
(POSxHLD)
QCAPEN
32-Bit Initialization and
Capture Register
(QEI1IC)(1)
Data Bus
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 258
FIGURE 17-1:
dsPIC33EPXXXGM3XX/6XX/7XX
17.1
QEI Control Registers
REGISTER 17-1:
R/W-0
QEIxCON: QEIx CONTROL REGISTER
U-0
QEIEN
R/W-0
—
R/W-0
QEISIDL
PIMOD2
R/W-0
(1)
R/W-0
(1)
PIMOD1
R/W-0
(1)
PIMOD0
(2,4)
IMV1
R/W-0
IMV0(2,4)
bit 15
bit 8
U-0
R/W-0
—
INTDIV2
R/W-0
(3)
R/W-0
(3)
INTDIV1
INTDIV0
(3)
R/W-0
R/W-0
R/W-0
R/W-0
CNTPOL
GATEN
CCM1
CCM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
QEIEN: QEIx Module Counter Enable bit
1 = Module counters are enabled
0 = Module counters are disabled, but SFRs can be read or written to
bit 14
Unimplemented: Read as ‘0’
bit 13
QEISIDL: QEIx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-10
PIMOD: Position Counter Initialization Mode Select bits(1)
111 = Reserved
110 = Modulo Count mode for position counter
101 = Resets the position counter when the position counter equals the QEIxGEC register
100 = Second index event after home event initializes the position counter with contents of the QEIxIC
register
011 = First index event after home event initializes the position counter with contents of the QEIxIC
register
010 = Next index input event initializes the position counter with contents of the QEIxIC register
001 = Every index input event resets the position counter
000 = Index input event does not affect position counter
bit 9-8
IMV: Index Match Value bits(2,4)
1 = Required state of Phase B input signal for match on index pulse
0 = Required state of Phase A input signal for match on index pulse
bit 7
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD
bits are ignored.
When CCM = 00, and QEAx and QEBx values match the Index Match Value (IMV), the POSCNTH
and POSCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
The match value applies to the A and B inputs after the swap and polarity bits have been applied.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 17-1:
QEIxCON: QEIx CONTROL REGISTER (CONTINUED)
bit 6-4
INTDIV: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter),
velocity counter and index counter internal clock divider select)(3)
111 = 1:128 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
bit 3
CNTPOL: Position and Index Counter/Timer Direction Select bit
1 = Counter direction is negative unless modified by external up/down signal
0 = Counter direction is positive unless modified by external up/down signal
bit 2
GATEN: External Count Gate Enable bit
1 = External gate signal controls position counter operation
0 = External gate signal does not affect position counter/timer operation
bit 1-0
CCM: Counter Control Mode Selection bits
11 = Internal Timer mode with optional external count is selected
10 = External clock count with optional external count is selected
01 = External clock count with external up/down direction is selected
00 = Quadrature Encoder Interface (x4 mode) Count mode is selected
Note 1:
2:
3:
4:
When CCM = 10 or CCM = 11, all of the QEI counters operate as timers and the PIMOD
bits are ignored.
When CCM = 00, and QEAx and QEBx values match the Index Match Value (IMV), the POSCNTH
and POSCNTL registers are reset.
The selected clock rate should be at least twice the expected maximum quadrature count rate.
The match value applies to the A and B inputs after the swap and polarity bits have been applied.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 17-2:
QEIxIOC: QEIx I/O CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QCAPEN
FLTREN
QFDIV2
QFDIV1
QFDIV0
OUTFNC1
OUTFNC0
SWPAB
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R-x
R-x
R-x
HOMPOL
IDXPOL
QEBPOL
QEAPOL
HOME
INDEX
QEB
QEA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
QCAPEN: QEIx Position Counter Input Capture Enable bit
1 = Index match event of home input triggers a position capture event
0 = Index match event (positive edge) does not trigger a position capture event
bit 14
FLTREN: QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit
1 = Input pin digital filter is enabled
0 = Input pin digital filter is disabled (bypassed)
bit 13-11
QFDIV: QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits
111 = 1:128 clock divide
110 = 1:64 clock divide
101 = 1:32 clock divide
100 = 1:16 clock divide
011 = 1:8 clock divide
010 = 1:4 clock divide
001 = 1:2 clock divide
000 = 1:1 clock divide
bit 10-9
OUTFNC: QEIx Module Output Function Mode Select bits
11 = The CNTCMPx pin goes high when QEIxLEC POSxCNT QEIxGEC
10 = The CNTCMPx pin goes high when POSxCNT QEIxLEC
01 = The CNTCMPx pin goes high when POSxCNT QEIxGEC
00 = Output is disabled
bit 8
SWPAB: Swap QEAx and QEBx Inputs bit
1 = QEAx and QEBx are swapped prior to quadrature decoder logic
0 = QEAx and QEBx are not swapped
bit 7
HOMPOL: HOMEx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 6
IDXPOL: INDXx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 5
QEBPOL: QEBx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 4
QEAPOL: QEAx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
bit 3
HOME: Status of HOMEx Input Pin After Polarity Control bit
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 17-2:
QEIxIOC: QEIx I/O CONTROL REGISTER (CONTINUED)
bit 2
INDEX: Status of INDXx Input Pin After Polarity Control bit
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
bit 1
QEB: Status of QEBx Input Pin After Polarity Control and SWPAB Pin Swapping bit
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
bit 0
QEA: Status of QEAx Input Pin After Polarity Control and SWPAB Pin Swapping bit
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 17-3:
QEIxSTAT: QEIx STATUS REGISTER
U-0
U-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
—
—
PCHEQIRQ
PCHEQIEN
PCLEQIRQ
PCLEQIEN
POSOVIRQ
POSOVIEN
bit 15
bit 8
HS, R/C-0
PCIIRQ
(1)
R/W-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
HS, R/C-0
R/W-0
PCIIEN
VELOVIRQ
VELOVIEN
HOMIRQ
HOMIEN
IDXIRQ
IDXIEN
bit 7
bit 0
Legend:
HS = Hardware Settable bit
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
PCHEQIRQ: Position Counter Greater Than or Equal Compare Status bit
1 = POSxCNT ≥ QEIxGEC
0 = POSxCNT < QEIxGEC
bit 12
PCHEQIEN: Position Counter Greater Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 11
PCLEQIRQ: Position Counter Less Than or Equal Compare Status bit
1 = POSxCNT ≤ QEIxLEC
0 = POSxCNT > QEIxLEC
bit 10
PCLEQIEN: Position Counter Less Than or Equal Compare Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 9
POSOVIRQ: Position Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has occurred
bit 8
POSOVIEN: Position Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 7
PCIIRQ: Position Counter (Homing) Initialization Process Complete Status bit(1)
1 = POSxCNT was reinitialized
0 = POSxCNT was not reinitialized
bit 6
PCIIEN: Position Counter (Homing) Initialization Process Complete interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 5
VELOVIRQ: Velocity Counter Overflow Status bit
1 = Overflow has occurred
0 = No overflow has occurred
bit 4
VELOVIEN: Velocity Counter Overflow Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 3
HOMIRQ: Status Flag for Home Event Status bit
1 = Home event has occurred
0 = No home event has occurred
Note 1:
This status bit is only applicable to PIMOD = 011 and 100 modes.
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REGISTER 17-3:
QEIxSTAT: QEIx STATUS REGISTER (CONTINUED)
bit 2
HOMIEN: Home Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 1
IDXIRQ: Status Flag for Index Event Status bit
1 = Index event has occurred
0 = No index event has occurred
bit 0
IDXIEN: Index Input Event Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
Note 1:
This status bit is only applicable to PIMOD = 011 and 100 modes.
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REGISTER 17-4:
R/W-0
POSxCNTH: POSITION COUNTER x HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
POSCNT: High Word Used to Form 32-Bit Position Counter x Register (POSxCNT) bits
REGISTER 17-5:
R/W-0
POSxCNTL: POSITION COUNTER x LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSCNT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
POSCNT: Low Word Used to Form 32-Bit Position Counter x Register (POSxCNT) bits
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REGISTER 17-6:
R/W-0
POSxHLD: POSITION COUNTER x HOLD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSHLD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POSHLD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
POSHLD: Holding Register for Reading and Writing POSxCNT bits
REGISTER 17-7:
R/W-0
VELxCNT: VELOCITY COUNTER x REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VELCNT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
VELCNT: Velocity Counter x bits
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REGISTER 17-8:
R/W-0
INDXxCNTH: INDEX COUNTER x HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INDXCNT: High Word Used to Form 32-Bit Index Counter x Register (INDXxCNT) bits
REGISTER 17-9:
R/W-0
INDXxCNTL: INDEX COUNTER x LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDXCNT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INDXCNT: Low Word Used to Form 32-Bit Index Counter x Register (INDXxCNT) bits
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REGISTER 17-10: INDXxHLD: INDEX COUNTER x HOLD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDXHLD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INDXHLD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INDXHLD: Holding Register for Reading and Writing INDXxCNT bits
REGISTER 17-11: QEIxICH: QEIx INITIALIZATION/CAPTURE HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
QEIIC: High Word Used to Form 32-Bit Initialization/Capture Register (QEIxIC) bits
REGISTER 17-12: QEIxICL: QEIx INITIALIZATION/CAPTURE LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIIC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
QEIIC: Low Word Used to Form 32-Bit Initialization/Capture Register (QEIxIC) bits
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REGISTER 17-13: QEIxLECH: QEIx LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
QEILEC: High Word Used to Form 32-Bit Less Than or Equal Compare Register (QEIxLEC) bits
REGISTER 17-14: QEIxLECL: QEIx LESS THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEILEC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
QEILEC: Low Word Used to Form 32-Bit Less Than or Equal Compare Register (QEIxLEC) bits
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REGISTER 17-15: QEIxGECH: QEIx GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
QEIGEC: High Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEIxGEC) bits
REGISTER 17-16: QEIxGECL: QEIx GREATER THAN OR EQUAL COMPARE LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIGEC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
QEIGEC: Low Word Used to Form 32-Bit Greater Than or Equal Compare Register (QEIxGEC) bits
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 17-17: INTxTMRH: INTERVAL TIMERx HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INTTMR: High Word Used to Form 32-Bit Interval Timerx Register (INTxTMR) bits
REGISTER 17-18: INTxTMRL: INTERVAL TIMERx LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTTMR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INTTMR: Low Word Used to Form 32-Bit Interval Timerx Register (INTxTMR) bits
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REGISTER 17-19: INTxHLDH: INTERVAL TIMERx HOLD HIGH WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INTHLD: Holding Register for Reading and Writing INTxTMRH bits
REGISTER 17-20: INTxHLDL: INTERVAL TIMERx HOLD LOW WORD REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INTHLD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
INTHLD: Holding Register for Reading and Writing INTxTMRL bits
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dsPIC33EPXXXGM3XX/6XX/7XX
18.0
SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Serial Peripheral
Interface (SPI)” (DS70005185), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The SPI module is a synchronous serial interface,
useful for communicating with other peripheral or
microcontroller devices. These peripheral devices can
be serial EEPROMs, shift registers, display drivers,
A/D Converters, etc. The SPI module is compatible
with the Motorola® SPI and SIOP interfaces.
The dsPIC33EPXXXGM3XX/6XX/7XX device family
offers three SPI modules on a single device. These
modules, which are designated as SPI1, SPI2 and
SPI3, are functionally identical. Each SPI module
includes an eight-word FIFO buffer and allows DMA
bus connections. When using the SPI module with
DMA, FIFO operation can be disabled.
Note:
In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1, SPI2 and SPI3. Special Function
Registers follow a similar notation. For
example, SPIxCON refers to the control
register for the SPI1, SPI2 and SPI3
modules.
The SPI1 module uses dedicated pins which allow for
a higher speed when using SPI1. The SPI2 and SPI3
modules take advantage of the Peripheral Pin Select
(PPS) feature to allow for greater flexibility in pin
configuration of these modules, but results in a lower
maximum speed. See Section 33.0 “Electrical
Characteristics” for more information.
The SPIx serial interface consists of four pins, as
follows:
•
•
•
•
SDIx: Serial Data Input
SDOx: Serial Data Output
SCKx: Shift Clock Input or Output
SSx/FSYNCx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPIx module can be configured to operate with
two, three or four pins. In 3-pin mode, SSx is not used.
In 2-pin mode, neither SDOx nor SSx is used.
Figure 18-1 illustrates the block diagram of the SPIx
module in Standard and Enhanced modes.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 18-1:
SPIx MODULE BLOCK DIAGRAM
SCKx
1:1 to 1:8
Secondary
Prescaler
SSx/FSYNCx
Sync
Control
Control
Clock
1:1/4/16/64
Primary
Prescaler
Select
Edge
SPIxCON1
Shift Control
SDOx
SPIxCON1
Enable
Master Clock
bit 0
SDIx
FP
SPIxSR
Transfer
Transfer
8-Level FIFO
Receive Buffer(1)
8-Level FIFO
Transmit Buffer(1)
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
Note 1:
In Standard mode, the FIFO is only one level deep.
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dsPIC33EPXXXGM3XX/6XX/7XX
18.1
1.
3.
In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2) = 1, use a
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on
SSx.
Note:
2.
SPI Helpful Tips
This insures that the first frame transmission after initialization is not shifted or
corrupted.
In Non-Framed 3-Wire mode (i.e., not using SSx
from a master):
a) If CKP (SPIxCON1) = 1, always place a
pull-up resistor on SSx.
b) If CKP = 0, always place a pull-down
resistor on SSx.
Note:
This will insure that during power-up and
initialization, the master/slave will not lose
sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors, for both transmit and receive,
appearing as corrupted data.
2013-2014 Microchip Technology Inc.
FRMEN (SPIxCON2) = 1 and SSEN
(SPIxCON1) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx pin,
which indicates the start of a data frame.
Note:
4.
Not all third-party devices support Frame
mode timing. Refer to the SPIx
specifications in Section 33.0 “Electrical
Characteristics” for details.
In Master mode only, set the SMP bit
(SPIxCON1) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1) is set.
To avoid invalid slave read data to the master, the
user’s master software must ensure enough time for
slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPIx Shift register
and is empty once the data transmission begins.
DS70000689D-page 275
dsPIC33EPXXXGM3XX/6XX/7XX
18.2
SPI Control Registers
REGISTER 18-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
SPIEN
—
SPISIDL
—
—
SPIBEC2
SPIBEC1
SPIBEC0
bit 15
bit 8
R/W-0
R/C-0, HS
R/W-0
R/W-0
R/W-0
R/W-0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
R-0, HS, HC R-0, HS, HC
SPITBF
SPIRBF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
C = Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the module
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the module operation when device enters Idle mode
0 = Continues the module operation in Idle mode
bit 12-11
Unimplemented: Read as ‘0’
bit 10-8
SPIBEC: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPIx transfers are pending.
Slave mode:
Number of SPIx transfers are unread.
bit 7
SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive the data
0 = SPIx Shift register is not empty
bit 6
SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user application has not read the
previous data in the SPIxBUF register
0 = No overflow has occurred
bit 5
SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2
SISEL: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into SPIxSR, and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the SPIx receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the SPIx receive buffer is read, and as a result, the buffer is empty
(SRXMPT bit is set)
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REGISTER 18-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer Mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last
unread buffer location. Automatically cleared in hardware when a buffer location is available for a
transfer from SPIxSR.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 18-2:
SPIXCON1: SPIX CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
(2)
CKP
SSEN
R/W-0
MSTEN
R/W-0
(3)
SPRE2
R/W-0
(3)
SPRE1
R/W-0
SPRE0
(3)
R/W-0
PPRE1
(3)
R/W-0
PPRE0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
DISSCK: Disable SCKx Pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
bit 11
DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7
SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by port function
bit 6
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1:
2:
3:
The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both primary and secondary prescalers to the value of 1:1.
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2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 18-2:
SPIXCON1: SPIX CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0
PPRE: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1:
2:
3:
The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both primary and secondary prescalers to the value of 1:1.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 18-3:
SPIXCON2: SPIX CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
FRMDLY
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as the Frame Sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14
SPIFSD: SPIx Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 13
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
bit 12-2
Unimplemented: Read as ‘0’
bit 1
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with first bit clock
0 = Frame Sync pulse precedes first bit clock
bit 0
SPIBEN: SPIx Enhanced Buffer Enable bit
1 = Enhanced Buffer is enabled
0 = Enhanced Buffer is disabled (Standard mode)
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dsPIC33EPXXXGM3XX/6XX/7XX
19.0
INTER-INTEGRATED
CIRCUIT™ (I2C™)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Inter-Integrated
Circuit™ (I2C™)” (DS70000195), which
is available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXXGM3XX/6XX/7XX family of
devices contains two Inter-Integrated Circuit (I2C)
modules: I2C1 and I2C2.
The I2C module has a 2-pin interface:
• The SCLx pin is clock.
• The SDAx pin is data.
The I2C module offers the following key features:
• I2C Interface Supporting both Master and Slave
modes of Operation.
• I2C Slave mode Supports 7 and
10-Bit Addressing.
• I2C Master mode Supports 7 and
10-Bit Addressing.
• I2C Port Allows Bidirectional Transfers Between
Master and Slaves.
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
• I2C Supports Multi-Master Operation, Detects Bus
Collision and Arbitrates Accordingly.
• Intelligent Platform Management Interface (IPMI)
Support
• System Management Bus (SMBus) Support
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard, with a 16-bit interface.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 19-1:
I2Cx BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
SCLx/ASCLx
Shift
Clock
I2CxRSR
LSb
SDAx/ASDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSb
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
FP/2
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dsPIC33EPXXXGM3XX/6XX/7XX
19.1
I2C Control Registers
REGISTER 19-1:
R/W-0
I2CxCON: I2Cx CONTROL REGISTER
U-0
I2CEN
—
R/W-0
R/W-1, HC
I2CSIDL
SCLREL
R/W-0
IPMIEN
(1)
R/W-0
R/W-0
R/W-0
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions
bit 14
Unimplemented: Read as ‘0’
bit 13
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C™ slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clears
at the beginning of every slave data byte transmission. Hardware clears at the end of every slave
address byte reception. Hardware clears at the end of every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clears at the beginning of every
slave data byte transmission. Hardware clears at the end of every slave address byte reception.
bit 11
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit(1)
1 = IPMI mode is enabled; all addresses are Acknowledged
0 = IPMI mode is disabled
bit 10
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with the SMBus specification
0 = Disables SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for
reception)
0 = General call address is disabled
Note 1:
When performing master operations, ensure that the IPMIEN bit is set to ‘0’.
2013-2014 Microchip Technology Inc.
DS70000689D-page 283
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 19-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
hardware clears at the end of the master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C; hardware clears at the end of the eighth bit of a master receive
data byte
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins; hardware clears at the end of a master Stop
sequence
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware clears at the end of a master
Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins; hardware clears at the end of a master Start
sequence
0 = Start condition is not in progress
Note 1:
When performing master operations, ensure that the IPMIEN bit is set to ‘0’.
DS70000689D-page 284
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 19-2:
I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC
R-0, HSC
U-0
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
bit 15
bit 8
R/C-0, HS
R/C-0, HS
IWCOL
I2COV
R-0, HSC R/C-0, HSC
D_A
P
R/C-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
S
R_W
RBF
TBF
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ACKSTAT: Acknowledge Status bit
(when operating as I2C™ master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware sets or clears at the end of a slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware sets at the beginning of a master transmission. Hardware clears at the end of a slave Acknowledge.
bit 13-11
Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware sets at detection of a bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware sets when address matches the general call address. Hardware clears at Stop detection.
bit 8
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware sets at a match of the 2nd byte of a matched 10-bit address. Hardware clears at Stop detection.
bit 7
IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware sets at an occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware sets at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware clears at a device address match. Hardware sets by reception of a slave byte.
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 19-2:
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware sets or clears when Start, Repeated Start or Stop is detected.
bit 2
R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
Hardware sets or clears after reception of an I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware sets when I2CxRCV is written with a received byte. Hardware clears when software reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware sets when software writes to I2CxTRN. Hardware clears at completion of data transmission.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 19-3:
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
AMSK
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
AMSK: Address Mask Select bits
For 10-Bit Address:
1 = Enables masking for bit, Ax, of incoming message address; bit match is not required in this position
0 = Disables masking for bit, Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK only):
1 = Enables masking for bit, Ax + 1, of incoming message address; bit match is not required in this
position
0 = Disables masking for bit, Ax + 1; bit match is required in this position
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 288
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
20.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24
Family Reference Manual”, “Universal
Asynchronous Receiver Transmitter
(UART)” (DS70000582), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXXGM3XX/6XX/7XX
devices contains four UART modules.
family
of
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the dsPIC33EPXXXGM3XX/6XX/7XX device family.
The UART is a full-duplex, asynchronous system that
can communicate with peripheral devices, such as
personal computers, LIN/J2602, RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins, and also
includes an IrDA® encoder and decoder.
Note:
Hardware flow control using UxRTS and
UxCTS is not available on all pin count
devices. See the “Pin Diagrams” section
for availability.
FIGURE 20-1:
The primary features of the UART module are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop Bits
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
• Baud Rates Ranging from 4.375 Mbps to 67 bps at
16x mode at 70 MIPS
• Baud Rates Ranging from 17.5 Mbps to 267 bps at
4x mode at 70 MIPS
• 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for All UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Support for Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA® Support
A simplified block diagram of the UART module is
shown in Figure 20-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UxRTS/BCLKx
UxCTS
UARTx Receiver
UARTx Transmitter
2013-2014 Microchip Technology Inc.
UxRX
UxTX
DS70000689D-page 289
dsPIC33EPXXXGM3XX/6XX/7XX
20.1
1.
UART Helpful Tips
In multi-node direct connect UART networks,
UART receive inputs react to the complementary
logic level defined by the URXINV bit
(UxMODE), which defines the Idle state, the
default of which is logic high (i.e., URXINV = 0).
Because remote devices do not initialize at the
same time, it is likely that one of the devices,
because the RX line is floating, will trigger a Start
bit detection and will cause the first byte received,
after the device has been initialized, to be invalid.
To avoid this situation, the user should use a pullup or pull-down resistor on the RX pin, depending
on the value of the URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the
RX pin.
b) If URXINV = 1, use a pull-down resistor on
the RX pin.
DS70000689D-page 290
2.
The first character received on wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UART module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid. This is to be
expected.
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
20.2
UART Control Registers
REGISTER 20-1:
R/W-0
UxMODE: UARTx MODE REGISTER
U-0
(1)
UARTEN
—
R/W-0
USIDL
R/W-0
IREN
(2)
R/W-0
U-0
R/W-0
R/W-0
RTSMD
—
UEN1
UEN0
bit 15
bit 8
R/W-0, HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption
is minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches(3)
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used(4)
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches(4)
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin, interrupt is generated on the falling edge; bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
Note 1:
2:
3:
4:
Refer to the “dsPIC33/PIC24 Family Reference Manual”, “Universal Asynchronous Receiver Transmitter
(UART)” (DS70000582) for information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
This feature is only available on 44-pin and 64-pin devices.
This feature is only available on 64-pin devices.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 20-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or has completed
bit 4
URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
3:
4:
Refer to the “dsPIC33/PIC24 Family Reference Manual”, “Universal Asynchronous Receiver Transmitter
(UART)” (DS70000582) for information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
This feature is only available on 44-pin and 64-pin devices.
This feature is only available on 64-pin devices.
DS70000689D-page 292
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 20-2:
R/W-0
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
UTXINV
R/W-0
UTXISEL0
U-0
—
R/W-0, HC
UTXBRK
R/W-0
(1)
UTXEN
R-0
R-1
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
C = Clearable bit
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
least one character open in the transmit buffer)
bit 14
UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop
bit; cleared by hardware upon completion
0 = Sync Break transmission is disabled or has completed
bit 10
UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the PORT
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1:
Refer to the “dsPIC33/PIC24 Family Reference Manual”, “Universal Asynchronous Receiver
Transmitter (UART)” (DS70000582) for information on enabling the UART module for transmit operation.
2013-2014 Microchip Technology Inc.
DS70000689D-page 293
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 20-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive
FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1 0 transition) resets
the receive buffer and the UxRSR to the empty state
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
Refer to the “dsPIC33/PIC24 Family Reference Manual”, “Universal Asynchronous Receiver
Transmitter (UART)” (DS70000582) for information on enabling the UART module for transmit operation.
DS70000689D-page 294
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
21.0
CONTROLLER AREA
NETWORK (CAN) MODULE
(dsPIC33EPXXXGM6XX/7XX
DEVICES ONLY)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Enhanced Controller Area Network (ECAN™)” (DS70353),
which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
21.1
Overview
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other CAN
modules or microcontroller devices. This interface/
protocol was designed to allow communications within
noisy environments. The dsPIC33EPXXXGM6XX/7XX
devices contain two CAN modules.
The CAN module is a communication controller, implementing the CAN 2.0 A/B protocol, as defined in the
BOSCH CAN specification. The module supports
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implementation is a full CAN system. The CAN specification is
not covered within this data sheet. The reader can refer
to the BOSCH CAN specification for further details.
2013-2014 Microchip Technology Inc.
The CAN module features are as follows:
• Implementation of the CAN protocol, CAN 1.2,
CAN 2.0A and CAN 2.0B
• Standard and Extended Data Frames
• 0-8 Bytes of Data Length
• Programmable Bit Rate, up to 1 Mbit/sec
• Automatic Response to Remote Transmission
Requests
• Up to 8 Transmit Buffers with Application
Specified Prioritization and Abort Capability (each
buffer can contain up to 8 bytes of data)
• Up to 32 Receive Buffers (each buffer can contain
up to 8 bytes of data)
• Up to 16 Full (Standard/Extended Identifier)
Acceptance Filters
• Three Full Acceptance Filter Masks
• DeviceNet™ Addressing Support
• Programmable Wake-up Functionality with
Integrated Low-Pass Filter
• Programmable Loopback mode supports
Self-Test Operation
• Signaling via Interrupt Capabilities for all CAN
Receiver and Transmitter Error States
• Programmable Clock Source
• Programmable Link to Input Capture 2 (IC2)
module for Timestamping and Network
Synchronization
• Low-Power Sleep and Idle modes
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
DS70000689D-page 295
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 21-1:
CANx MODULE BLOCK DIAGRAM
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
DMA Controller
RxF11 Filter
RxF10 Filter
RxF9 Filter
RxF8 Filter
TRB7 TX/RX Buffer Control Register
RxF7 Filter
TRB6 TX/RX Buffer Control Register
RxF6 Filter
TRB5 TX/RX Buffer Control Register
RxF5 Filter
TRB4 TX/RX Buffer Control Register
RxF4 Filter
TRB3 TX/RX Buffer Control Register
RxF3 Filter
TRB2 TX/RX Buffer Control Register
RxF2 Filter
RxM2 Mask
TRB1 TX/RX Buffer Control Register
RxF1 Filter
RxM1 Mask
TRB0 TX/RX Buffer Control Register
RxF0 Filter
RxM0 Mask
Transmit Byte
Sequencer
Message Assembly
Buffer
CAN Protocol
Engine
Control
Configuration
Logic
CPU
Bus
Interrupts
CxTX
21.2
CxRX
Modes of Operation
The CANx module can operate in one of several
operation modes selected by the user. These modes
include:
•
•
•
•
•
•
Initialization mode
Disable mode
Normal Operation mode
Listen Only mode
Listen All Messages mode
Loopback mode
DS70000689D-page 296
Modes are requested by setting the REQOP bits
(CxCTRL1). Entry into a mode is Acknowledged
by monitoring the OPMODE bits (CxCTRL1).
The module does not change the mode and the
OPMODEx bits until a change in mode is acceptable,
generally during bus Idle time, which is defined as at least
11 consecutive recessive bits.
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
21.3
CAN Control Registers
REGISTER 21-1:
CxCTRL1: CANx CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
—
—
CSIDL
ABAT
CANCKS
REQOP2
REQOP1
REQOP0
bit 15
bit 8
R-1
R-0
R-0
U-0
R/W-0
U-0
U-0
R/W-0
OPMODE2
OPMODE1
OPMODE0
—
CANCAP
—
—
WIN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CSIDL: CANx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 11
CANCKS: CANx Module Clock (FCAN) Source Select bit
1 = FCAN is equal to 2 * FP
0 = FCAN is equal to FP
bit 10-8
REQOP: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 7-5
OPMODE: Operation Mode bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 4
Unimplemented: Read as ‘0’
bit 3
CANCAP: CANx Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on CAN message receive
0 = Disables CAN capture
bit 2-1
Unimplemented: Read as ‘0’
bit 0
WIN: SFR Map Window Select bit
1 = Uses filter window
0 = Uses buffer window
2013-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000689D-page 297
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-2:
CxCTRL2: CANx CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R-0
R-0
R-0
R-0
R-0
DNCNT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
DNCNT: DeviceNet™ Filter Bit Number bits
10010-11111 = Invalid selection
10001 = Compare up to Data Byte 3, bit 6 with EID
•
•
•
00001 = Compare up to Data Byte 1, bit 7 with EID
00000 = Do not compare data bytes
DS70000689D-page 298
x = Bit is unknown
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-3:
CxVEC: CANx INTERRUPT CODE REGISTER
U-0
U-0
U-0
R-0
R-0
R-0
R-0
R-0
—
—
—
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 15
bit 8
U-0
R-1
R-0
R-0
R-0
R-0
R-0
R-0
—
ICODE6
ICODE5
ICODE4
ICODE3
ICODE2
ICODE1
ICODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
FILHIT: Filter Hit Number bits
10000-11111 = Reserved
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE: Interrupt Flag Code bits
1000101-1111111 = Reserved
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
•
•
•
0010000-0111111 = Reserved
0001111 = RB15 buffer interrupt
•
•
•
0001001 = RB9 buffer interrupt
0001000 = RB8 buffer interrupt
0000111 = TRB7 buffer interrupt
0000110 = TRB6 buffer interrupt
0000101 = TRB5 buffer interrupt
0000100 = TRB4 buffer interrupt
0000011 = TRB3 buffer interrupt
0000010 = TRB2 buffer interrupt
0000001 = TRB1 buffer interrupt
0000000 = TRB0 buffer interrupt
2013-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000689D-page 299
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-4:
R/W-0
DMABS2
bit 15
CxFCTRL: CANx FIFO CONTROL REGISTER
R/W-0
DMABS1
R/W-0
DMABS0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
FSA4
R/W-0
FSA3
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 12-5
bit 4-0
U-0
—
U-0
—
bit 8
U-0
—
bit 15-13
U-0
—
W = Writable bit
‘1’ = Bit is set
R/W-0
FSA2
R/W-0
FSA1
R/W-0
FSA0
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DMABS: DMA Buffer Size bits
111 = Reserved
110 = 32 buffers in RAM
101 = 24 buffers in RAM
100 = 16 buffers in RAM
011 = 12 buffers in RAM
010 = 8 buffers in RAM
001 = 6 buffers in RAM
000 = 4 buffers in RAM
Unimplemented: Read as ‘0’
FSA: FIFO Area Starts with Buffer bits
11111 = Receive Buffer RB31
11110 = Receive Buffer RB30
•
•
•
00001 = Transmit/Receive Buffer TRB1
00000 = Transmit/Receive Buffer TRB0
DS70000689D-page 300
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-5:
CxFIFO: CANx FIFO STATUS REGISTER
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
bit 15
bit 8
U-0
U-0
R-0
R-0
R-0
R-0
R-0
R-0
—
—
FNRB5
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
FBP: FIFO Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
FNRB: FIFO Next Read Buffer Pointer bits
011111 = RB31 buffer
011110 = RB30 buffer
•
•
•
000001 = TRB1 buffer
000000 = TRB0 buffer
2013-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000689D-page 301
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-6:
CxINTF: CANx INTERRUPT FLAG REGISTER
U-0
—
bit 15
U-0
—
R-0
TXBO
R-0
TXBP
R-0
RXBP
R-0
TXWAR
R-0
RXWAR
R-0
EWARN
bit 8
R/C-0
IVRIF
bit 7
R/C-0
WAKIF
R/C-0
ERRIF
U-0
—
R/C-0
FIFOIF
R/C-0
RBOVIF
R/C-0
RBIF
R/C-0
TBIF
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
C = Writable bit, but only ‘0’ can be written to clear the bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state
0 = Transmitter is not in Bus Passive state
RXBP: Receiver in Error State Bus Passive bit
1 = Receiver is in Bus Passive state
0 = Receiver is not in Bus Passive state
TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state
0 = Transmitter is not in Error Warning state
RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state
0 = Receiver is not in Error Warning state
EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state
0 = Transmitter or receiver is not in Error Warning state
IVRIF: Invalid Message Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
WAKIF: Bus Wake-up Activity Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF register)
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
Unimplemented: Read as ‘0’
FIFOIF: FIFO Almost Full Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
RBOVIF: RX Buffer Overflow Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS70000689D-page 302
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-6:
bit 1
CxINTF: CANx INTERRUPT FLAG REGISTER (CONTINUED)
RBIF: RX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
TBIF: TX Buffer Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
REGISTER 21-7:
CxINTE: CANx INTERRUPT ENABLE REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
IVRIE
WAKIE
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7
IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6
WAKIE: Bus Wake-up Activity Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 5
ERRIE: Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
FIFOIE: FIFO Almost Full Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1
RBIE: RX Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0
TBIE: TX Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
2013-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000689D-page 303
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-8:
CxEC: CANx TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
R-0
TERRCNT7
TERRCNT6
R-0
R-0
R-0
TERRCNT5 TERRCNT4 TERRCNT3
R-0
R-0
R-0
TERRCNT2
TERRCNT1
TERRCNT0
bit 15
bit 8
R-0
R-0
RERRCNT7
RERRCNT6
R-0
R-0
R-0
RERRCNT5 RERRCNT4 RERRCNT3
R-0
RERRCNT2
R-0
R-0
RERRCNT1 RERRCNT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
TERRCNT: Transmit Error Count bits
bit 7-0
RERRCNT: Receive Error Count bits
REGISTER 21-9:
x = Bit is unknown
CxCFG1: CANx BAUD RATE CONFIGURATION REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-6
SJW: Synchronization Jump Width bits
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0
BRP: Baud Rate Prescaler bits
11 1111 = TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010 = TQ = 2 x 3 x 1/FCAN
00 0001 = TQ = 2 x 2 x 1/FCAN
00 0000 = TQ = 2 x 1 x 1/FCAN
DS70000689D-page 304
x = Bit is unknown
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-10: CxCFG2: CANx BAUD RATE CONFIGURATION REGISTER 2
U-0
R/W-x
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
SEG2PH0
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEG2PHTS
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14
WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 13-11
Unimplemented: Read as ‘0’
bit 10-8
SEG2PH: Phase Segment 2 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN Bus Line bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3
SEG1PH: Phase Segment 1 bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 2-0
PRSEG: Propagation Time Segment bits
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
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REGISTER 21-11: CxFEN1: CANx ACCEPTANCE FILTER ENABLE REGISTER 1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
FLTEN: Enable Filter n to Accept Messages bits
1 = Enables Filter n
0 = Disables Filter n
REGISTER 21-12: CxBUFPNT1: CANx FILTERS 0-3 BUFFER POINTER REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F3BP3
F3BP2
F3BP1
F3BP0
F2BP3
F2BP2
F2BP1
F2BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F1BP3
F1BP2
F1BP1
F1BP0
F0BP3
F0BP2
F0BP1
F0BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F3BP: RX Buffer Mask for Filter 3 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F2BP: RX Buffer Mask for Filter 2 bits (same values as bits 15-12)
bit 7-4
F1BP: RX Buffer Mask for Filter 1 bits (same values as bits 15-12)
bit 3-0
F0BP: RX Buffer Mask for Filter 0 bits (same values as bits 15-12)
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REGISTER 21-13: CxBUFPNT2: CANx FILTERS 4-7 BUFFER POINTER REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7BP3
F7BP2
F7BP1
F7BP0
F6BP3
F6BP2
F6BP1
F6BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F5BP3
F5BP2
F5BP1
F5BP0
F4BP3
F4BP2
F4BP1
F4BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F7BP: RX Buffer Mask for Filter 7 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F6BP: RX Buffer Mask for Filter 6 bits (same values as bits 15-12)
bit 7-4
F5BP: RX Buffer Mask for Filter 5 bits (same values as bits 15-12)
bit 3-0
F4BP: RX Buffer Mask for Filter 4 bits (same values as bits 15-12)
REGISTER 21-14: CxBUFPNT3: CANx FILTERS 8-11 BUFFER POINTER REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F9BP3
F9BP2
F9BP1
F9BP0
F8BP3
F8BP2
F8BP1
F8BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F11BP: RX Buffer Mask for Filter 11 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F10BP: RX Buffer Mask for Filter 10 bits (same values as bits 15-12)
bit 7-4
F9BP: RX Buffer Mask for Filter 9 bits (same values as bits 15-12)
bit 3-0
F8BP: RX Buffer Mask for Filter 8 bits (same values as bits 15-12)
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REGISTER 21-15: CxBUFPNT4: CANx FILTERS 12-15 BUFFER POINTER REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1
F12BP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
F15BP: RX Buffer Mask for Filter 15 bits
1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
0001 = Filter hits received in RX Buffer 1
0000 = Filter hits received in RX Buffer 0
bit 11-8
F14BP: RX Buffer Mask for Filter 14 bits (same values as bits 15-12)
bit 7-4
F13BP: RX Buffer Mask for Filter 13 bits (same values as bits 15-12)
bit 3-0
F12BP: RX Buffer Mask for Filter 12 bits (same values as bits 15-12)
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REGISTER 21-16: CxRXFnSID: CANx ACCEPTANCE FILTER n STANDARD IDENTIFIER
REGISTER (n = 0-15)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 15
bit 8
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
SID: Standard Identifier bits
1 = Message address bit, SIDx, must be ‘1’ to match filter
0 = Message address bit, SIDx, must be ‘0’ to match filter
bit 4
Unimplemented: Read as ‘0’
bit 3
EXIDE: Extended Identifier Enable bit
If MIDE = 1:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
If MIDE = 0:
Ignores EXIDE bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
REGISTER 21-17: CxRXFnEID: CANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTER (n = 0-15)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
EID: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
0 = Message address bit, EIDx, must be ‘0’ to match filter
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REGISTER 21-18: CxFMSKSEL1: CANx FILTERS 7-0 MASK SELECTION REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
F7MSK: Mask Source for Filter 7 bit
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12
F6MSK: Mask Source for Filter 6 bit (same values as bits 15-14)
bit 11-10
F5MSK: Mask Source for Filter 5 bit (same values as bits 15-14)
bit 9-8
F4MSK: Mask Source for Filter 4 bit (same values as bits 15-14)
bit 7-6
F3MSK: Mask Source for Filter 3 bit (same values as bits 15-14)
bit 5-4
F2MSK: Mask Source for Filter 2 bit (same values as bits 15-14)
bit 3-2
F1MSK: Mask Source for Filter 1 bit (same values as bits 15-14)
bit 1-0
F0MSK: Mask Source for Filter 0 bit (same values as bits 15-14)
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REGISTER 21-19: CxFMSKSEL2: CANx FILTERS 15-8 MASK SELECTION REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
F15MSK: Mask Source for Filter 15 bit
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12
F14MSK: Mask Source for Filter 14 bit (same values as bits 15-14)
bit 11-10
F13MSK: Mask Source for Filter 13 bit (same values as bits 15-14)
bit 9-8
F12MSK: Mask Source for Filter 12 bit (same values as bits 15-14)
bit 7-6
F11MSK: Mask Source for Filter 11 bit (same values as bits 15-14)
bit 5-4
F10MSK: Mask Source for Filter 10 bit (same values as bits 15-14)
bit 3-2
F9MSK: Mask Source for Filter 9 bit (same values as bits 15-14)
bit 1-0
F8MSK: Mask Source for Filter 8 bit (same values as bits 15-14)
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x = Bit is unknown
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REGISTER 21-20: CxRXMnSID: CANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER
REGISTER (n = 0-2)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
bit 15
bit 8
R/W-x
R/W-x
R/W-x
U-0
R/W-x
U-0
R/W-x
R/W-x
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
SID: Standard Identifier bits
1 = Includes bit, SIDx, in filter comparison
0 = Bit, SIDx, is a don’t care in filter comparison
bit 4
Unimplemented: Read as ‘0’
bit 3
MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to the EXIDE bit in
the filter
0 = Matches either standard or extended address message if filters match
(i.e., if (Filter SIDx) = (Message SIDx) or if (Filter SIDx/EIDx) = (Message SIDx/EIDx))
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison
0 = Bit, EIDx, is a don’t care in filter comparison
REGISTER 21-21: CxRXMnEID: CANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER
REGISTER (n = 0-2)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
EID: Extended Identifier bits
1 = Includes bit, EIDx, in filter comparison
0 = Bit, EIDx, is a don’t care in filter comparison
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REGISTER 21-22: CxRXFUL1: CANx RECEIVE BUFFER FULL REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXFUL: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)
REGISTER 21-23: CxRXFUL2: CANx RECEIVE BUFFER FULL REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXFUL: Receive Buffer n Full bits
1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)
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REGISTER 21-24: CxRXOVF1: CANx RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXOVF: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)
REGISTER 21-25: CxRXOVF2: CANx RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RXOVF: Receive Buffer n Overflow bits
1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)
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REGISTER 21-26: CxTRmnCON: CANx TX/RX BUFFER mn CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI1
TXnPRI0
bit 15
bit 8
R/W-0
R-0
TXENm
TXABTm(1)
R-0
R-0
TXLARBm(1) TXERRm(1)
R/W-0
R/W-0
R/W-0
R/W-0
TXREQm
RTRENm
TXmPRI1
TXmPRI0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
See Definition for bits 7-0, controls Buffer n
bit 7
TXENm: TX/RX Buffer Selection bit
1 = Buffer, TRBn, is a transmit buffer
0 = Buffer, TRBn, is a receive buffer
bit 6
TXABTm: Message Aborted bit(1)
1 = Message was aborted
0 = Message completed transmission successfully
bit 5
TXLARBm: Message Lost Arbitration bit(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4
TXERRm: Error Detected During Transmission bit(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3
TXREQm: Message Send Request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent
0 = Clearing the bit to ‘0’ while set requests a message abort
bit 2
RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQx will be set
0 = When a remote transmit is received, TXREQx will be unaffected
bit 1-0
TXmPRI: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1:
Note:
This bit is cleared when TXREQx is set.
The buffers, SIDx, EIDx, DLCx, Data Field, and Receive Status registers, are located in DMA RAM.
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21.4
CAN Message Buffers
CAN Message Buffers are part of RAM memory. They
are not CAN Special Function Registers. The user
application must directly write into the RAM area that is
configured for CAN Message Buffers. The location and
size of the buffer area is defined by the user
application.
BUFFER 21-1:
CANx MESSAGE BUFFER WORD 0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
SID10
SID9
SID8
SID7
SID6
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SID5
SID4
SID3
SID2
SID1
SID0
SRR
IDE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-2
SID: Standard Identifier bits
bit 1
SRR: Substitute Remote Request bit
When IDE = 0:
1 = Message will request remote transmission
0 = Normal message
When IDE = 1:
The SRR bit must be set to ‘1’.
bit 0
IDE: Extended Identifier bit
1 = Message will transmit an Extended Identifier
0 = Message will transmit a Standard Identifier
BUFFER 21-2:
x = Bit is unknown
CANx MESSAGE BUFFER WORD 1
U-0
U-0
U-0
U-0
—
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
EID
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-0
EID: Extended Identifier bits
DS70000689D-page 316
x = Bit is unknown
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
(
BUFFER 21-3:
CANx MESSAGE BUFFER WORD 2
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID5
EID4
EID3
EID2
EID1
EID0
RTR
RB1
bit 15
bit 8
U-x
U-x
U-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
RB0
DLC3
DLC2
DLC1
DLC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
EID: Extended Identifier bits
bit 9
RTR: Remote Transmission Request bit
When IDE = 1:
1 = Message will request remote transmission
0 = Normal message
When IDE = 0:
The RTR bit is ignored.
bit 8
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
bit 7-5
Unimplemented: Read as ‘0’
bit 4
RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
bit 3-0
DLC: Data Length Code bits
BUFFER 21-4:
R/W-x
x = Bit is unknown
CANx MESSAGE BUFFER WORD 3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 1
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 1: CANx Message Byte 1
bit 7-0
Byte 0: CANx Message Byte 0
2013-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000689D-page 317
dsPIC33EPXXXGM3XX/6XX/7XX
BUFFER 21-5:
R/W-x
CANx MESSAGE BUFFER WORD 4
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 3
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 3: CANx Message Byte 3
bit 7-0
Byte 2: CANx Message Byte 2
BUFFER 21-6:
R/W-x
x = Bit is unknown
CANx MESSAGE BUFFER WORD 5
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 5
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 5: CANx Message Byte 5
bit 7-0
Byte 4: CANx Message Byte 4
DS70000689D-page 318
x = Bit is unknown
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
BUFFER 21-7:
R/W-x
CANx MESSAGE BUFFER WORD 6
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 7
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 6
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Byte 7: CANx Message Byte 7
bit 7-0
Byte 6: CANx Message Byte 6
BUFFER 21-8:
x = Bit is unknown
CANx MESSAGE BUFFER WORD 7
U-0
U-0
U-0
—
—
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
FILHIT(1)
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
FILHIT: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
Only written by module for receive buffers, unused for transmit buffers.
2013-2014 Microchip Technology Inc.
DS70000689D-page 319
dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 320
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
22.0
CHARGE TIME
MEASUREMENT UNIT (CTMU)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Charge Time
Measurement Unit (CTMU)” (DS70661),
which is available on the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Charge Time Measurement Unit is a flexible analog
module that provides accurate differential time measurement between pulse sources, as well as asynchronous
pulse generation. Its key features include:
•
•
•
•
•
•
Four edge input trigger sources
Polarity control for each edge source
Control of edge sequence
Control of response to edges
Precise time measurement resolution of 1 ns
Accurate current source suitable for capacitive
measurement
• On-chip temperature measurement using a
built-in diode
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock.
The CTMU module is ideal for interfacing with
capacitive-based sensors. The CTMU is controlled
through three registers: CTMUCON1, CTMUCON2
and CTMUICON. CTMUCON1 and CTMUCON2
enable the module and control edge source selection,
edge source polarity selection and edge sequencing.
The CTMUICON register controls the selection and
trim of the current source.
2013-2014 Microchip Technology Inc.
DS70000689D-page 321
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 22-1:
CTMU BLOCK DIAGRAM
CTMUCON1 or CTMUCON2
CTMUICON
ITRIM
IRNG
Current Source
Edge
Control
Logic
CTED1
CTED2
EDG1STAT
EDG2STAT
Timer1
OC1
IC1
CMP1
Current
Control
TGEN
CTMU
Control
Logic
Pulse
Generator
CTMUI to ADCx
Analog-to-Digital
Trigger
CTPLS
CTMUP
CTMU TEMP
CTMU
Temperature
Sensor
C1IN1CDelay
CMP1
External Capacitor
for Pulse Generation
Current Control Selection
CTMU TEMP
DS70000689D-page 322
TGEN
EDG1STAT, EDG2STAT
0
EDG1STAT = EDG2STAT
CTMUI to ADCx
0
EDG1STAT EDG2STAT
CTMUP
1
EDG1STAT EDG2STAT
No Connect
1
EDG1STAT = EDG2STAT
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
22.1
CTMU Control Registers
REGISTER 22-1:
CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN(1)
CTTRIG
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11
EDGEN: Edge Enable bit
1 = Hardware modules are used to trigger edges (TMRx, CTEDx, etc.)
0 = Software is used to trigger edges (manual set of EDGxSTAT)
bit 10
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9
IDISSEN: Analog Current Source Control bit(1)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8
CTTRIG: ADCx Trigger Control bit
1 = CTMU triggers ADCx start of conversion
0 = CTMU does not trigger ADCx start of conversion
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
The ADCx module Sample-and-Hold (S&H) capacitor is not automatically discharged between
sample/conversion cycles. Any software using the ADCx as part of a capacitance measurement must
discharge the ADCx capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADCx must be sampling while the IDISSEN bit is active to connect the discharge
sink to the capacitor array.
2013-2014 Microchip Technology Inc.
DS70000689D-page 323
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 22-2:
CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG1MOD
EDG1POL
EDG1SEL3
EDG1SEL2
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
EDG2MOD
EDG2POL
EDG2SEL3
EDG2SEL2
EDG2SEL1
EDG2SEL0
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
EDG1MOD: Edge 1 Edge Sampling Mode Selection bit
1 = Edge 1 is edge-sensitive
0 = Edge 1 is level-sensitive
bit 14
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 13-10
EDG1SEL: Edge 1 Source Select bits
1111 = FOSC
1110 = OSCI pin
1101 = FRC oscillator
1100 = Reserved
1011 = Internal LPRC oscillator
1010 = Reserved
100x = Reserved
01xx = Reserved
0011 = CTED1 pin
0010 = CTED2 pin
0001 = OC1 module
0000 = Timer1 module
bit 9
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
bit 8
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
bit 7
EDG2MOD: Edge 2 Edge Sampling Mode Selection bit
1 = Edge 2 is edge-sensitive
0 = Edge 2 is level-sensitive
bit 6
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
Note 1:
If the TGEN bit is set to ‘1’, then the CMP1 module should be selected as the Edge 2 source in the
EDG2SELx bits field; otherwise, the module will not function.
DS70000689D-page 324
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 22-2:
CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED)
bit 5-2
EDG2SEL: Edge 2 Source Select bits
1111 = FOSC
1110 = OSCI pin
1101 = FRC oscillator
1100 = Reserved
1011 = Internal LPRC oscillator
1010 = Reserved
100x = Reserved
0111 = Reserved
0110 = Reserved
0101 = Reserved
0100 = CMP1 module(1)
0011 = CTED2 pin
0010 = CTED1 pin
0001 = OC1 module
0000 = IC1 module
bit 1-0
Unimplemented: Read as ‘0’
Note 1:
If the TGEN bit is set to ‘1’, then the CMP1 module should be selected as the Edge 2 source in the
EDG2SELx bits field; otherwise, the module will not function.
2013-2014 Microchip Technology Inc.
DS70000689D-page 325
dsPIC33EPXXXGM3XX/6XX/7XX
CTMUICON: CTMU CURRENT CONTROL REGISTER(3)
REGISTER 22-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
ITRIM: Current Source Trim bits
011111 = Maximum positive change from nominal current + 62%
011110 = Maximum positive change from nominal current + 60%
•
•
•
000010 = Minimum positive change from nominal current + 4%
000001 = Minimum positive change from nominal current + 2%
000000 = Nominal current output specified by IRNG
111111 = Minimum negative change from nominal current – 2%
111110 = Minimum negative change from nominal current – 4%
•
•
•
100010 = Maximum negative change from nominal current – 60%
100001 = Maximum negative change from nominal current – 62%
bit 9-8
IRNG: Current Source Range Select bits
11 = 100 Base Current(2)
10 = 10 Base Current(2)
01 = Base Current Level(2)
00 = 1000 Base Current(1,2)
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
x = Bit is unknown
This current range is not available for use with the internal temperature measurement diode.
Refer to the CTMU Current Source Specifications (Table 33-55) in Section 33.0 “Electrical
Characteristics” for the current range selection values.
Current sources are not generated when 12-Bit ADC mode is chosen. Current sources are active only
when 10-Bit ADC mode is chosen.
DS70000689D-page 326
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
23.0
10-BIT/12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Analog-to-Digital
Converter (ADC)” (DS70621), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXXGM3XX/6XX/7XX devices have
two ADC modules: ADC1 and ADC2. The ADC1
supports up to 49 analog input channels, while the
ADC2 supports up to 32 analog input channels.
On ADCx, the AD12B bit (ADxCON1) allows each
of the ADC modules to be configured by the user as
either a 10-bit, 4 Sample-and-Hold (S&H) ADC (default
configuration) or a 12-bit, 1 S&H ADC. Both ADC1 and
ADC2 can be operated in 12-bit mode.
Note:
23.1
23.1.1
The ADCx module needs to be disabled
before modifying the AD12B bit.
Key Features
10-BIT ADCx CONFIGURATION
The 10-bit ADCx configuration has the following key
features:
•
•
•
•
•
Successive Approximation (SAR) conversion
Conversion speeds of up to 1.1 Msps
Up to 49 analog input pins
Connections to three internal op amps
Connections to the Charge Time Measurement Unit
(CTMU) and temperature measurement diode
2013-2014 Microchip Technology Inc.
• Channel selection and triggering can be controlled
by the Peripheral Trigger Generator (PTG)
• External voltage reference input pins
• Simultaneous sampling of:
- Up to four analog input pins
- Three op amp outputs
• Combinations of analog inputs and op amp outputs
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
23.1.2
12-BIT ADCx CONFIGURATION
The 12-bit ADCx configuration supports all the features
listed above, with the exception of the following:
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only one S&H amplifier in the 12-bit
configuration; therefore, simultaneous sampling
of multiple channels is not supported.
• Analog inputs, AN32-AN49, are not supported
The ADC1 has up to 49 analog inputs. The analog
inputs, AN32 through AN49, are multiplexed, thus
providing flexibility in using any of these analog inputs in
addition to the analog inputs, AN0 through AN31. Since
AN32 through AN49 are multiplexed, do not use two
channels simultaneously, since it may result in
erroneous output from the module. These analog inputs
are shared with op amp inputs and outputs, comparator
inputs and external voltage references. When op amp/
comparator functionality is enabled, or an external voltage reference is used, the analog input that shares that
pin is no longer available. The actual number of analog
input pins, op amps and external voltage reference input
configuration, depends on the specific device.
A block diagram of the ADCx module is shown in
Figure 23-1. Figure 23-2 provides a diagram of the
ADCx conversion clock period.
DS70000689D-page 327
ADCx MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS
This diagram depicts all of the available
ADCx connection options to the four S&H
amplifiers, which are designated: CH0,
CH1, CH2 and CH3.
The ANx analog pins or op amp outputs are
connected to the CH0-CH3 amplifiers
through the multiplexers, controlled by the
SFR control bits, CH0Sx, CH0Nx, CH123Sx
and CH123Nx.
00000
Channel Scan
AN0-ANx
OA1-OA3, OA5
CTMU TEMP
OPEN
From CTMU
Current Source (CTMUI)
11111
+
CH0
–
CH0Sx
VREFL
CH0SA
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RTCC/RB3
++
CMP1
/OA1
––
PGEC3/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/
RPI33/CTED1/RB1
VREFL
+
CH1
–
010
011
1xx
CH123Sx
AN9/RPI27/RA11
B
CH0NA(3)
A
CH0NB(3)
B
CH123SA
A
CH123SB
B
CH123NA
A
CH123NB
B
CH0SB
+
–
OA2
CH0Sx
S&H2
+
CH2
–
010
011
1xx
CH0Nx
S&H1
0x
10
11
000 CH123Nx
001
OA2IN+/AN1/C2IN3-/C2IN1+/RPI17/RA1
A
(3)
0
000 CH0Nx
001
OA1
0
CSCNA
S&H0
1
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16//RA0
1
(3)
CH123Sx
CH123Nx
Alternate Input
(MUXA/MUXB)
Selection
ALTS
CH123Sx
VREFL
VREF+(1)
0x
AVDD
VREF-(1)
AVSS
10
11
AN10/RPI28/RA12
CH123Nx
000
001
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
2013-2014 Microchip Technology Inc.
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/
PMA13/RC2
+
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
–
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/OCFB/RC0
OA3
VREFL
010
011
1xx
VCFG
S&H3
+
CH3
–
VREFH
VREFL
ADC1BUF0(4)
ADC1BUF1(4)
ADC1BUF2(4)
CH123Sx
0x
SAR ADC
10
11
AN11/C1IN2-/U1CTS/FLT4/PMA12/RC11
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
+
TMS/OA5IN-/AN27/C5IN1-/RP41/RB9
–
CH123Nx
ADC1BUFE(4)
ADC1BUFF(4)
OA5
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
Note 1:
2:
3:
4:
VREF+, VREF- inputs can be multiplexed with other analog inputs.
Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
These bits can be updated with Step commands from the PTG module. For more information, refer to the “Peripheral Trigger Generator (PTG)” chapter in the specific device data sheet.
When ADDMAEN (ADxCON4) = 1, enabling DMA, only ADCxBUF0 is used.
dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 328
FIGURE 23-1:
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 23-2:
ADCx CONVERSION CLOCK PERIOD BLOCK DIAGRAM
AD1CON3
ADCx Internal
RC Clock(2)
1
TAD
AD1CON3
0
6
TP(1)
ADCx Conversion
Clock Multiplier
1, 2, 3, 4, 5,..., 256
Note 1:
2:
TP = 1/FP.
See the ADCx electrical specifications in Section 33.0 “Electrical Characteristics” for the
exact RC clock value.
2013-2014 Microchip Technology Inc.
DS70000689D-page 329
dsPIC33EPXXXGM3XX/6XX/7XX
23.2
1.
2.
ADCx Helpful Tips
The SMPIx control bits in the ADxCON2 registers:
a) Determine when the ADCx interrupt flag is
set and an interrupt is generated, if
enabled.
b) When the CSCNA bit in the ADxCON2 register is set to ‘1’, this determines when the
ADCx analog scan channel list, defined in
the AD1CSSL/AD1CSSH registers, starts
over from the beginning.
c) When the DMA peripheral is not used
(ADDMAEN = 0), this determines when the
ADCx Result Buffer Pointer to ADC1BUF0ADC1BUFF gets reset back to the
beginning at ADC1BUF0.
d) When the DMA peripheral is used
(ADDMAEN = 1), this determines when the
DMA Address Pointer is incremented after a
sample/conversion operation. ADC1BUF0 is
the only ADCx buffer used in this mode. The
ADCx Result Buffer Pointer to ADC1BUF0ADC1BUFF gets reset back to the beginning
at ADC1BUF0. The DMA address is incremented after completion of every 32nd
sample/conversion operation. Conversion
results are stored in the ADC1BUF0
register for transfer to RAM using the DMA
peripheral.
When the DMA module is disabled
(ADDMAEN = 0), the ADCx has 16 result buffers.
ADCx conversion results are stored sequentially
in ADC1BUF0-ADC1BUFF, regardless of which
analog inputs are being used subject to the SMPIx
bits and the condition described in 1.c) above.
There is no relationship between the ANx input
being measured and which ADCx buffer
(ADC1BUF0-ADC1BUFF) that the conversion
results will be placed in.
DS70000689D-page 330
3.
4.
5.
When the DMA module is enabled
(ADDMAEN = 1), the ADCx module has only
1 ADCx result buffer (i.e., ADC1BUF0) per
ADCx peripheral and the ADCx conversion
result must be read, either by the CPU or DMA
Controller, before the next ADCx conversion is
complete to avoid overwriting the previous
value.
The DONE bit (ADxCON1) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely, even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
behavior because the CPU code execution is
faster than the ADCx. As a result, in Manual
Sample mode, particularly where the user’s
code is setting the SAMP bit (ADxCON1),
the DONE bit should also be cleared by the user
application just before setting the SAMP bit.
Enabling op amps, comparator inputs and external voltage references can limit the availability of
analog inputs (ANx pins). For example, when
Op Amp 2 is enabled, the pins for AN0, AN1 and
AN2 are used by the op amp’s inputs and output.
This negates the usefulness of Alternate Input
mode since the MUXA selections use AN0-AN2.
Carefully study the ADCx block diagram to determine the configuration that will best suit your
application. Configuration examples are available
in the “dsPIC33/PIC24 Family Reference
Manual”, “Analog-to-Digital Converter (ADC)”
(DS70621)
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
23.3
ADCx Control Registers
REGISTER 23-1:
ADxCON1: ADCx CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSRC2
SSRC1
SSRC0
SSRCG
SIMSAM
ASAM
R/W-0, HC, HS R/C-0, HC, HS
SAMP
DONE(2)
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
HC = Hardware Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: ADCx Operating Mode bit
1 = ADCx module is operating
0 = ADCx is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: ADCx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
ADDMABM: ADCx DMA Buffer Build Mode bit
1 = DMA buffers are written in the order of conversion; the module provides an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0 = DMA buffers are written in Scatter/Gather mode; the module provides a Scatter/Gather address to
the DMA channel based on the index of the analog input and the size of the DMA buffer
bit 11
Unimplemented: Read as ‘0’
bit 10
AD12B: 10-Bit or 12-Bit ADCx Operation Mode bit
1 = 12-bit, 1-channel ADCx operation
0 = 10-bit, 4-channel ADCx operation
bit 9-8
FORM: Data Output Format bits
For 10-Bit Operation:
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d)
00 = Integer (DOUT = 0000 00dd dddd dddd)
For 12-Bit Operation:
11 = Signed fractional (DOUT = sddd dddd dddd 0000, where s = .NOT.d)
10 = Fractional (DOUT = dddd dddd dddd 0000)
01 = Signed integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d)
00 = Integer (DOUT = 0000 dddd dddd dddd)
Note 1:
2:
See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
Do not clear the DONE bit in software if ADCx Sample Auto-Start bit is enabled (ASAM = 1).
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REGISTER 23-1:
ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)
bit 7-5
SSRC: Sample Clock Source Select bits
If SSRCG = 1:
111 = Reserved
110 = PTGO15 primary trigger compare ends sampling and starts conversion(1)
101 = PTGO14 primary trigger compare ends sampling and starts conversion(1)
100 = PTGO13 primary trigger compare ends sampling and starts conversion(1)
011 = PTGO12 primary trigger compare ends sampling and starts conversion(1)
010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion
001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion
000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion
If SSRCG = 0:
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU ends sampling and starts conversion
101 = PWM secondary Special Event Trigger ends sampling and starts conversion
100 = Timer5 compare ends sampling and starts conversion
011 = PWM primary Special Event Trigger ends sampling and starts conversion
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode)
bit 4
SSRCG: Sample Trigger Source Group bit
See SSRC for details.
bit 3
SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS = 01 or 1x)
In 12-Bit Mode (AD12B = 1), SIMSAM is Unimplemented and is Read as ‘0’:
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS = 1x), or samples CH0 and CH1
simultaneously (when CHPS = 01)
0 = Samples multiple channels individually in sequence
bit 2
ASAM: ADCx Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1
SAMP: ADCx Sample Enable bit
1 = ADCx Sample-and-Hold amplifiers are sampling
0 = ADCx Sample-and-Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If
SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADCx Conversion Status bit(2)
1 = ADCx conversion cycle is completed.
0 = ADCx conversion has not started or is in progress
Automatically set by hardware when A/D conversion is complete. Software can write ‘0’ to clear DONE
status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress.
Automatically cleared by hardware at the start of a new conversion.
Note 1:
2:
See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
Do not clear the DONE bit in software if ADCx Sample Auto-Start bit is enabled (ASAM = 1).
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REGISTER 23-2:
ADxCON2: ADCx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
VCFG2(1)
VCFG1(1)
VCFG0(1)
OFFCAL
—
CSCNA
CHPS1
CHPS0
bit 15
bit 8
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFS
SMPI4
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
x = Bit is unknown
VCFG: Converter Voltage Reference Configuration bits(1)
Value
VREFH
VREFL
000
001
010
011
1xx
AVDD
External VREF+(2)
AVDD
External VREF+(2)
AVDD
AVSS
AVSS
External VREF-(2)
External VREF-(2)
AVSS
bit 12
OFFCAL: Offset Calibration Mode Select bit
1 = + and – inputs of channel Sample-and-Hold are connected to AVSS
0 = + and – inputs of channel Sample-and-Hold are normal
bit 11
Unimplemented: Read as ‘0’
bit 10
CSCNA: Input Scan Select bit
1 = Scans inputs for CH0+ during Sample MUXA
0 = Does not scan inputs
bit 9-8
CHPS: Channel Select bits
In 12-Bit Mode (AD12B = 1), CHPS Bits are Unimplemented and are Read as ‘00’:
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADCx is currently filling the second half of the buffer; the user application should access data in
the first half of the buffer
0 = ADCx is currently filling the first half of the buffer; the user application should access data in the
second half of the buffer
Note 1:
2:
The ‘001’, ‘010’ and ‘011’ bit combinations for VCFG are not applicable on ADC2.
ADC2 does not support external VREF± inputs.
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REGISTER 23-2:
ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED)
bit 6-2
SMPI: Increment Rate bits
When ADDMAEN = 0:
x1111 = Generates interrupt after completion of every 16th sample/conversion operation
x1110 = Generates interrupt after completion of every 15th sample/conversion operation
•
•
•
x0001 = Generates interrupt after completion of every 2nd sample/conversion operation
x0000 = Generates interrupt after completion of every sample/conversion operation
When ADDMAEN = 1:
11111 = Increments the DMA address after completion of every 32nd sample/conversion operation
11110 = Increments the DMA address after completion of every 31st sample/conversion operation
•
•
•
00001 = Increments the DMA address after completion of every 2nd sample/conversion operation
00000 = Increments the DMA address after completion of every sample/conversion operation
bit 1
BUFM: Buffer Fill Mode Select bit
1 = Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer
on the next interrupt
0 = Always starts filling the buffer from the Start address
bit 0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample MUXA on the first sample and Sample MUXB on the next sample
0 = Always uses channel input selects for Sample MUXA
Note 1:
2:
The ‘001’, ‘010’ and ‘011’ bit combinations for VCFG are not applicable on ADC2.
ADC2 does not support external VREF± inputs.
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REGISTER 23-3:
R/W-0
ADxCON3: ADCx CONTROL REGISTER 3
U-0
ADRC
U-0
—
—
R/W-0
SAMC4
(1)
R/W-0
(1)
SAMC3
R/W-0
(1)
SAMC2
R/W-0
SAMC1
(1)
R/W-0
SAMC0(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7(2)
ADCS6(2)
ADCS5(2)
ADCS4(2)
ADCS3(2)
ADCS2(2)
ADCS1(2)
ADCS0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADRC: ADCx Conversion Clock Source bit
1 = ADCX internal RC clock
0 = Clock derived from system clock
bit 14-13
Unimplemented: Read as ‘0’
bit 12-8
SAMC: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD
bit 7-0
ADCS: ADCx Conversion Clock Select bits(2)
11111111 = TP • (ADCS + 1) = TP • 256 = TAD
•
•
•
00000010 = TP • (ADCS + 1) = TP • 3 = TAD
00000001 = TP • (ADCS + 1) = TP • 2 = TAD
00000000 = TP • (ADCS + 1) = TP • 1 = TAD
Note 1:
2:
x = Bit is unknown
This bit is only used if SSRC (AD1CON1) = 111 and SSRCG (AD1CON1) = 0.
This bit is not used if ADRC (AD1CON3) = 1.
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REGISTER 23-4:
ADxCON4: ADCx CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
ADDMAEN
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
DMABL2
DMABL1
DMABL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
ADDMAEN: ADCx DMA Enable bit
1 = Conversion results are stored in the ADC1BUF0 register for transfer to RAM using DMA
0 = Conversion results are stored in the ADC1BUF0 through ADC1BUFF registers; DMA will not be used
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
DMABL: Selects Number of DMA Buffer Locations per Analog Input bits
111 = Allocates 128 words of buffer to each analog input
110 = Allocates 64 words of buffer to each analog input
101 = Allocates 32 words of buffer to each analog input
100 = Allocates 16 words of buffer to each analog input
011 = Allocates 8 words of buffer to each analog input
010 = Allocates 4 words of buffer to each analog input
001 = Allocates 2 words of buffer to each analog input
000 = Allocates 1 word of buffer to each analog input
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REGISTER 23-5:
ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
CH123SB2
CH123SB1
CH123NB1
CH123NB0
CH123SB0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
CH123SA2
CH123SA1
CH123NA1
CH123NA0
CH123SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-11
CH123SB: Channels 1, 2, 3 Positive Input Select for Sample B bits
1xx = CH1 positive input is AN0 (Op Amp 2), CH2 positive input is AN25 (Op Amp 5), CH3 positive
input is AN6 (Op Amp 3)
011 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN25 (Op Amp 5)
010 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN6 (Op Amp 3)
001 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
000 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 10-9
CH123NB: Channels 1, 2, 3 Negative Input Select for Sample B bits
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is VREFL(1)
bit 8
CH123SB0: Channels 1, 2, 3 Positive Input Select for Sample B bit
See bits for bit selections.
bit 7-5
Unimplemented: Read as ‘0’
bit 4-3
CH123SA: Channels 1, 2, 3 Positive Input Select for Sample A bits
1xx = CH1 positive input is AN0 (Op Amp 2), CH2 positive input is AN25 (Op Amp 5), CH3 positive
input is AN6 (Op Amp 3)
011 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN25 (Op Amp 5)
010 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN6 (Op Amp 3)
001 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
000 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 2-1
CH123NA: Channels 1, 2, 3 Negative Input Select for Sample A bits
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is VREFL
bit 0
CH123SA0: Channels 1, 2, 3 Positive Input Select for Sample A bit
See bits for the bit selections.
Note 1:
The negative input to VREFL happens only when VCFG = 2 or 3 in the ADxCON2 register. When
VCFG = 0 or 1, this negative input is internally routed to AVSS.
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REGISTER 23-6:
ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER(3)
R/W-0
CH0NB
bit 15
U-0
—
R/W-0
R/W-0
CH0SB5(1,4,5) CH0SB4(1,5)
R/W-0
CH0SB3(1,5)
R/W-0
CH0SB2(1,5)
R/W-0
CH0SB1(1,5)
R/W-0
CH0SB0(1,5)
bit 8
R/W-0
CH0NA
bit 7
U-0
—
R/W-0
R/W-0
CH0SA5(1,4,5) CH0SA4(1,5)
R/W-0
CH0SA3(1,5)
R/W-0
CH0SA2(1,5)
R/W-0
CH0SA1(1,5)
R/W-0
CH0SA0(1,5)
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-8
Note 1:
2:
3:
4:
5:
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
CH0NB: Channel 0 Negative Input Select for Sample MUXB bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
Unimplemented: Read as ‘0’
CH0SB: Channel 0 Positive Input Select for Sample MUXB bits(1,4,5)
111111 = Channel 0 positive input is (AN63) unconnected
111110 = Channel 0 positive input is (AN62) the CTMU temperature voltage
111101 = Channel 0 positive input is (AN61) reserved
•
•
•
110010 = Channel 0 positive input is (AN50) reserved
110001 = Channel 0 positive input is AN49
110000 = Channel 0 positive input is AN48
101111 = Channel 0 positive input is AN47
101110 = Channel 0 positive input is AN46
•
•
•
011010 = Channel 0 positive input is AN26
011001 = Channel 0 positive input is AN25 or Op Amp 5 output voltage(2)
011000 = Channel 0 positive input is AN24
•
•
•
000111 = Channel 0 positive input is AN7
000110 = Channel 0 positive input is AN6 or Op Amp 3 output voltage(2)
000101 = Channel 0 positive input is AN5
000100 = Channel 0 positive input is AN4
000011 = Channel 0 positive input is AN3 or Op Amp 1 output voltage(2)
000010 = Channel 0 positive input is AN2
000001 = Channel 0 positive input is AN1
000000 = Channel 0 positive input is AN0 or Op Amp 2 output voltage(2)
AN0 through AN7 are repurposed when comparator and op amp functionality are enabled. See Figure 23-1 to
determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
If the op amp is selected (OPMODE bit (CMxCON) = 1), the OAx input is used; otherwise, the ANx
input is used.
See the “Pin Diagrams” section for the available analog channels for each device.
Analog input selections for ADC1 are shown here. AN32-AN63 selections are not available for ADC2. The
CH0SB5 and CH0SA5 bits are ‘Reserved’ for ADC2 and should be programmed to ‘0’.
Analog inputs, AN32-AN49, are available only when the ADCx is working in 10-bit mode.
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REGISTER 23-6:
bit 7
ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER(3) (CONTINUED)
CH0NA: Channel 0 Negative Input Select for Sample MUXA bit
1 = Channel 0 negative input is AN1(1)
0 = Channel 0 negative input is VREFL
Unimplemented: Read as ‘0’
CH0SA: Channel 0 Positive Input Select for Sample MUXA bits(1,4,5)
111111 = Channel 0 positive input is (AN63) unconnected
111110 = Channel 0 positive input is (AN62) the CTMU temperature voltage
111101 = Channel 0 positive input is (AN61) reserved
•
•
•
110010 = Channel 0 positive input is (AN50) reserved
110001 = Channel 0 positive input is AN49
110000 = Channel 0 positive input is AN48
101111 = Channel 0 positive input is AN47
101110 = Channel 0 positive input is AN46
•
•
•
011010 = Channel 0 positive input is AN26
011001 = Channel 0 positive input is AN25 or Op Amp 5 output voltage(2)
011000 = Channel 0 positive input is AN24
•
•
•
000111 = Channel 0 positive input is AN7
000110 = Channel 0 positive input is AN6 or Op Amp 3 output voltage(2)
000101 = Channel 0 positive input is AN5
000100 = Channel 0 positive input is AN4
000011 = Channel 0 positive input is AN3 or Op Amp 1 output voltage(2)
000010 = Channel 0 positive input is AN2
000001 = Channel 0 positive input is AN1
000000 = Channel 0 positive input is AN0 or Op Amp 2 output voltage(2)
bit 6
bit 5-0
Note 1:
2:
3:
4:
5:
AN0 through AN7 are repurposed when comparator and op amp functionality are enabled. See Figure 23-1 to
determine how enabling a particular op amp or comparator affects selection choices for Channels 1, 2 and 3.
If the op amp is selected (OPMODE bit (CMxCON) = 1), the OAx input is used; otherwise, the ANx
input is used.
See the “Pin Diagrams” section for the available analog channels for each device.
Analog input selections for ADC1 are shown here. AN32-AN63 selections are not available for ADC2. The
CH0SB5 and CH0SA5 bits are ‘Reserved’ for ADC2 and should be programmed to ‘0’.
Analog inputs, AN32-AN49, are available only when the ADCx is working in 10-bit mode.
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ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(2)
REGISTER 23-7:
R/W-0
R/W-0
CSS31
CSS30
R/W-0
CSS29
R/W-0
CSS28
R/W-0
CSS27
R/W-0
(1)
CSS26
R/W-0
(1)
CSS25
R/W-0
CSS24(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CSS31: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 14
CSS30: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 13
CSS29: ADCx Input Scan Selection bits
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 12
CSS28: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 11
CSS27: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 10
CSS26: ADCx Input Scan Selection bit(1)
1 = Selects OA3/AN6 for input scan
0 = Skips OA3/AN6 for input scan
bit 9
CSS25: ADCx Input Scan Selection bit(1)
1 = Selects OA2/AN0 for input scan
0 = Skips OA2/AN0 for input scan
bit 8
CSS24: ADCx Input Scan Selection bit(1)
1 = Selects OA1/AN3 for input scan
0 = Skips OA1/AN3 for input scan
bit 7
CSS23: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 6
CSS22: ADCx Input Scan Selection bits
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 5
CSS21: ADCx Input Scan Selection bits
1 = Selects ANx for input scan
0 = Skips ANx for input scan
Note 1:
2:
x = Bit is unknown
If the op amp is selected (OPMODE bit (CMxCON) = 1), the OAx input is used; otherwise, the ANx
input is used.
All bits in this register can be selected by the user application. However, inputs selected for scan without a
corresponding input on the device convert VREFL.
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REGISTER 23-7:
ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(2) (CONTINUED)
bit 4
CSS20: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 3
CSS19: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 2
CSS18: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 1
CSS17: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
bit 0
CSS16: ADCx Input Scan Selection bit
1 = Selects ANx for input scan
0 = Skips ANx for input scan
Note 1:
2:
If the op amp is selected (OPMODE bit (CMxCON) = 1), the OAx input is used; otherwise, the ANx
input is used.
All bits in this register can be selected by the user application. However, inputs selected for scan without a
corresponding input on the device convert VREFL.
2013-2014 Microchip Technology Inc.
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ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW(1,2)
REGISTER 23-8:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
CSS: ADCx Input Scan Selection bits
1 = Selects ANx for input scan
0 = Skips ANx for input scan
On devices with less than 16 analog inputs, all bits in this register can be selected by the user application.
However, inputs selected for scan without a corresponding input on the device convert VREFL.
CSSx = ANx, where ‘x’ = 0-15.
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dsPIC33EPXXXGM3XX/6XX/7XX
24.0
DATA CONVERTER
INTERFACE (DCI) MODULE
24.1
The Data Converter Interface (DCI) module allows
simple interfacing of devices, such as audio coder/
decoders (Codecs), ADC and D/A Converters. The
following interfaces are supported:
Note 1: This data sheet is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Data Converter
Interface (DCI) Module” (DS70356),
which is available from the Microchip web
site (www.microchip.com).
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
• Inter-IC Sound (I2S) Interface
• AC-Link Compliant mode
General features include:
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 24-1:
Module Introduction
• Programmable word size up to 16 bits
• Supports up to 16 time slots, for a maximum
frame size of 256 bits
• Data buffering for up to 4 samples without CPU
overhead
DCI MODULE BLOCK DIAGRAM
BCG Control Bits
SCKD
FP
Sample Rate
Generator
CSCK
FSD
Word Size Selection bits
16-Bit Data Bus
Frame Length Selection bits
DCI Mode Selection bits
Frame
Synchronization
Generator
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
Transmit Buffer
Registers w/Shadow
COFS
0
DCI Shift Register
CSDI
CSDO
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24.2
DCI Control Registers
REGISTER 24-1:
DCICON1: DCI CONTROL REGISTER 1
R/W-0
r-0
R/W-0
r-0
R/W-0
R/W-0
R/W-0
R/W-0
DCIEN
r
DCISIDL
r
DLOOP
CSCKD
CSCKE
COFSD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
r-0
r-0
r-0
R/W-0
R/W-0
UNFM
CSDOM
DJST
r
r
r
COFSM1
COFSM0
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
DCIEN: DCI Module Enable bit
1 = DCI module is enabled
0 = DCI module is disabled
bit 14
Reserved: Read as ‘0’
bit 13
DCISIDL: DCI Stop in Idle Control bit
1 = Module will halt in CPU Idle mode
0 = Module will continue to operate in CPU Idle mode
bit 12
Reserved: Read as ‘0’
bit 11
DLOOP: Digital Loopback Mode Control bit
1 = Digital Loopback mode is enabled; CSDI and CSDO pins are internally connected
0 = Digital Loopback mode is disabled
bit 10
CSCKD: Sample Clock Direction Control bit
1 = CSCK pin is an input when DCI module is enabled
0 = CSCK pin is an output when DCI module is enabled
bit 9
CSCKE: Sample Clock Edge Control bit
1 = Data changes on serial clock falling edge, sampled on serial clock rising edge
0 = Data changes on serial clock rising edge, sampled on serial clock falling edge
bit 8
COFSD: Frame Synchronization Direction Control bit
1 = COFS pin is an input when DCI module is enabled
0 = COFS pin is an output when DCI module is enabled
bit 7
UNFM: Underflow Mode bit
1 = Transmits last value written to the Transmit registers on a transmit underflow
0 = Transmits ‘0’s on a transmit underflow
bit 6
CSDOM: Serial Data Output Mode bit
1 = CSDO pin will be tri-stated during disabled transmit time slots
0 = CSDO pin drives ‘0’s during disabled transmit time slots
bit 5
DJST: DCI Data Justification Control bit
1 = Data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse
0 = Data transmission/reception is begun one serial clock cycle after the frame synchronization pulse
bit 4-2
Reserved: Read as ‘0’
bit 1-0
COFSM: Frame Sync Mode bits
11 = 20-Bit AC-Link mode
10 = 16-Bit AC-Link mode
01 = I2S Frame Sync mode
00 = Multi-Channel Frame Sync mode
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 24-2:
DCICON2: DCI CONTROL REGISTER 2
r-0
r-0
r-0
r-0
R/W-0
R/W-0
r-0
R/W-0
r
r
r
r
BLEN1
BLEN0
r
COFSG3
bit 15
bit 8
R/W-0
R/W-0
R/W-0
r-0
R/W-0
R/W-0
R/W-0
R/W-0
COFSG2
COFSG1
COFSG0
r
WS3
WS2
WS1
WS0
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Reserved: Read as ‘0’
bit 11-10
BLEN: Buffer Length Control bits
11 = Four data words will be buffered between interrupts
10 = Three data words will be buffered between interrupts
01 = Two data words will be buffered between interrupts
00 = One data word will be buffered between interrupts
bit 9
Reserved: Read as ‘0’
bit 8-5
COFSG: Frame Sync Generator Control bits
1111 = Data frame has 16 words
•
•
•
0010 = Data frame has 3 words
0001 = Data frame has 2 words
0000 = Data frame has 1 word
bit 4
Reserved: Read as ‘0’
bit 3-0
WS: DCI Data Word Size bits
1111 = Data word size is 16 bits
•
•
•
0100 = Data word size is 5 bits
0011 = Data word size is 4 bits
0010 = Invalid Selection. Do not use. Unexpected results may occur.
0001 = Invalid Selection. Do not use. Unexpected results may occur.
0000 = Invalid Selection. Do not use. Unexpected results may occur.
2013-2014 Microchip Technology Inc.
x = Bit is unknown
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 24-3:
DCICON3: DCI CONTROL REGISTER 3
r-0
r-0
r-0
r-0
r
r
r
r
R/W-0
R/W-0
R/W-0
R/W-0
BCG
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BCG
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Reserved: Read as ‘0’
bit 11-0
BCG: DCI Bit Clock Generator Control bits
DS70000689D-page 346
x = Bit is unknown
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 24-4:
DCISTAT: DCI STATUS REGISTER
r-0
r-0
r-0
r-0
R-0
R-0
R-0
R-0
r
r
r
r
SLOT3
SLOT2
SLOT1
SLOT0
bit 15
bit 8
r-0
r-0
r-0
r-0
R-0
R-0
R-0
R-0
r
r
r
r
ROV
RFUL
TUNF
TMPTY
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Reserved: Read as ‘0’
bit 11-8
SLOT: DCI Slot Status bits
1111 = Slot 15 is currently active
•
•
•
0010 = Slot 2 is currently active
0001 = Slot 1 is currently active
0000 = Slot 0 is currently active
bit 7-4
Reserved: Read as ‘0’
bit 3
ROV: Receive Overflow Status bit
1 = A receive overflow has occurred for at least one Receive register
0 = A receive overflow has not occurred
bit 2
RFUL: Receive Buffer Full Status bit
1 = New data is available in the Receive registers
0 = The Receive registers have old data
bit 1
TUNF: Transmit Buffer Underflow Status bit
1 = A transmit underflow has occurred for at least one Transmit register
0 = A transmit underflow has not occurred
bit 0
TMPTY: Transmit Buffer Empty Status bit
1 = The Transmit registers are empty
0 = The Transmit registers are not empty
2013-2014 Microchip Technology Inc.
x = Bit is unknown
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 24-5:
R/W-0
RSCON: DCI RECEIVE SLOT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RSE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RSE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
RSE: DCI Receive Slot Enable bits
1 = CSDI data is received during Individual Time Slot n
0 = CSDI data is ignored during Individual Time Slot n
REGISTER 24-6:
R/W-0
TSCON: DCI TRANSMIT SLOT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TSE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TSE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
TSE: DCI Transmit Slot Enable Control bits
1 = Transmit buffer contents are sent during Individual Time Slot n
0 = CSDO pin is tri-stated or driven to logic ‘0’ during the individual time slot, depending on the state
of the CSDOM bit
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dsPIC33EPXXXGM3XX/6XX/7XX
25.0
PERIPHERAL TRIGGER
GENERATOR (PTG) MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Peripheral Trigger
Generator (PTG)” (DS70669), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
25.1
Module Introduction
The Peripheral Trigger Generator (PTG) provides a
means to schedule complex, high-speed peripheral
operations that would be difficult to achieve using software. The PTG module uses 8-bit commands, called
“steps”, that the user writes to the PTG Queue register
(PTGQUE0-PTQUE15), which performs operations,
such as wait for input signal, generate output trigger
and wait for timer.
2013-2014 Microchip Technology Inc.
The PTG module has the following major features:
•
•
•
•
•
Multiple Clock Sources
Two 16-Bit General Purpose Timers
Two 16-Bit General Limit Counters
Configurable for Rising or Falling Edge Triggering
Generates Processor Interrupts to Include:
- Four configurable processor interrupts
- Interrupt on a step event in Single-Step mode
- Interrupt on a PTG Watchdog Timer time-out
• Able to Receive Trigger Signals from these
Peripherals:
- ADC
- PWM
- Output Compare
- Input Capture
- Op Amp/Comparator
- INT2
• Able to Trigger or Synchronize to these
Peripherals:
- Watchdog Timer
- Output Compare
- Input Capture
- ADC
- PWM
- Op Amp/Comparator
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 25-1:
PTG BLOCK DIAGRAM
PTGHOLD
PTGL0
PTGADJ
Step Command
PTGTxLIM
PTG General
Purpose
Timerx
PTGCxLIM
PTGSDLIM
PTG Step
Delay Timer
PTG Loop
Counter x
PTGBTE
PTGCST
Step Command
PTGCON
Trigger Outputs
PTGDIV
FP
TAD
T1CLK
T2CLK
T3CLK
FOSC
Clock Inputs
16-Bit Data Bus
PTGCLK
PTG Control Logic
Step Command
Trigger Inputs
PTG Interrupts
Step Command
PWM
OC1
OC2
IC1
CMPx
ADC
INT2
PTGO0
•
•
•
PTGO31
PTG0IF
•
•
•
PTG3IF
AD1CHS0
PTGQPTR
PTG Watchdog
Timer(1)
PTGQUE0
PTGWDTIF
PTGQUE1
Command
Decoder
PTGQUE6
PTGQUE15
PTGSTEPIF
Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.
DS70000689D-page 350
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dsPIC33EPXXXGM3XX/6XX/7XX
25.2
PTG Control Registers
REGISTER 25-1:
PTGCST: PTG CONTROL/STATUS REGISTER
R/W-0
U-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
PTGEN
—
PTGSIDL
PTGTOGL
—
PTGSWT(2)
PTGSSEN
PTGIVIS
bit 15
bit 8
R/W-0
HS-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
PTGSTRT
PTGWDTO
—
—
—
—
PTGITM1(1)
PTGITM0(1)
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PTGEN: PTG Module Enable bit
1 = PTG module is enabled
0 = PTG module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
PTGSIDL: PTG Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
PTGTOGL: PTG TRIG Output Toggle Mode bit
1 = Toggles the state of the PTGOx for each execution of the PTGTRIG command
0 = Each execution of the PTGTRIG command will generate a single PTGOx pulse determined by the
value in the PTGPWDx bits
bit 11
Unimplemented: Read as ‘0’
bit 10
PTGSWT: PTG Software Trigger bit(2)
1 = Triggers the PTG module
0 = No action (clearing this bit will have no effect)
bit 9
PTGSSEN: PTG Enable Single-Step bit
1 = Enables Single-Step mode
0 = Disables Single-Step mode
bit 8
PTGIVIS: PTG Counter/Timer Visibility Control bit
1 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the current values of their
corresponding Counter/Timer registers (PTGSD, PTGCx, PTGTx)
0 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the value previously written to
those PTG Limit registers
bit 7
PTGSTRT: Start PTG Sequencer bit
1 = Starts to sequentially execute commands (Continuous mode)
0 = Stops executing commands
bit 6
PTGWDTO: PTG Watchdog Timer Time-out Status bit
1 = PTG Watchdog Timer has timed out
0 = PTG Watchdog Timer has not timed out.
bit 5-2
Unimplemented: Read as ‘0’
Note 1:
2:
These bits apply to the PTGWHI and PTGWLO commands only.
This bit is only used with the PTGCTRL Step command software trigger option.
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DS70000689D-page 351
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 25-1:
bit 1-0
Note 1:
2:
PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED)
PTGITM: PTG Input Trigger Command Operating Mode bits(1)
11 = Single level detect with step delay is not executed on exit of command (regardless of PTGCTRL
command)
10 = Single level detect with step delay is executed on exit of command
01 = Continuous edge detect with step delay is not executed on exit of command (regardless of
PTGCTRL command)
00 = Continuous edge detect with step delay is executed on exit of command
These bits apply to the PTGWHI and PTGWLO commands only.
This bit is only used with the PTGCTRL Step command software trigger option.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 25-2:
PTGCON: PTG CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGCLK2
PTGCLK1
PTGCLK0
PTGDIV4
PTGDIV3
PTGDIV2
PTGDIV1
PTGDIV0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
PTGPWD3
PTGPWD2
PTGPWD1
PTGPWD0
—
PTGWDT2
PTGWDT1
PTGWDT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
PTGCLK: Select PTG Module Clock Source bits
111 = Reserved
110 = Reserved
101 = PTG module clock source will be T3CLK
100 = PTG module clock source will be T2CLK
011 = PTG module clock source will be T1CLK
010 = PTG module clock source will be TAD
001 = PTG module clock source will be FOSC
000 = PTG module clock source will be FP
bit 12-8
PTGDIV: PTG Module Clock Prescaler (divider) bits
11111 = Divide-by-32
11110 = Divide-by-31
•
•
•
00001 = Divide-by-2
00000 = Divide-by-1
bit 7-4
PTGPWD: PTG Trigger Output Pulse-Width bits
1111 = All trigger outputs are 16 PTG clock cycles wide
1110 = All trigger outputs are 15 PTG clock cycles wide
•
•
•
0001 = All trigger outputs are 2 PTG clock cycles wide
0000 = All trigger outputs are 1 PTG clock cycle wide
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PTGWDT: Select PTG Watchdog Timer Time-out Count Value bits
111 = Watchdog Timer will time-out after 512 PTG clocks
110 = Watchdog Timer will time-out after 256 PTG clocks
101 = Watchdog Timer will time-out after 128 PTG clocks
100 = Watchdog Timer will time-out after 64 PTG clocks
011 = Watchdog Timer will time-out after 32 PTG clocks
010 = Watchdog Timer will time-out after 16 PTG clocks
001 = Watchdog Timer will time-out after 8 PTG clocks
000 = Watchdog Timer is disabled
2013-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000689D-page 353
dsPIC33EPXXXGM3XX/6XX/7XX
PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2)
REGISTER 25-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCTS4
ADCTS3
ADCTS2
ADCTS1
IC4TSS
IC3TSS
IC2TSS
IC1TSS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OC4CS
OC3CS
OC2CS
OC1CS
OC4TSS
OC3TSS
OC2TSS
OC1TSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADCTS4: Sample Trigger PTGO15 for ADCx bit
1 = Generates trigger when the broadcast command is executed
0 = Does not generate trigger when the broadcast command is executed
bit 14
ADCTS3: Sample Trigger PTGO14 for ADCx bit
1 = Generates trigger when the broadcast command is executed
0 = Does not generate trigger when the broadcast command is executed
bit 13
ADCTS2: Sample Trigger PTGO13 for ADCx bit
1 = Generates trigger when the broadcast command is executed
0 = Does not generate trigger when the broadcast command is executed
bit 12
ADCTS1: Sample Trigger PTGO12 for ADCx bit
1 = Generates trigger when the broadcast command is executed
0 = Does not generate trigger when the broadcast command is executed
bit 11
IC4TSS: Trigger/Synchronization Source for IC4 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 10
IC3TSS: Trigger/Synchronization Source for IC3 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 9
IC2TSS: Trigger/Synchronization Source for IC2 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 8
IC1TSS: Trigger/Synchronization Source for IC1 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 7
OC4CS: Clock Source for OC4 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 6
OC3CS: Clock Source for OC3 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 5
OC2CS: Clock Source for OC2 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
Note 1:
2:
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
This register is only used with the PTGCTRL OPTION = 1111 Step command.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 25-3:
PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED)
bit 4
OC1CS: Clock Source for OC1 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 3
OC4TSS: Trigger/Synchronization Source for OC4 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 2
OC3TSS: Trigger/Synchronization Source for OC3 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 1
OC2TSS: Trigger/Synchronization Source for OC2 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 0
OC1TSS: Trigger/Synchronization Source for OC1 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
Note 1:
2:
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
This register is only used with the PTGCTRL OPTION = 1111 Step command.
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PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1)
REGISTER 25-4:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT0LIM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT0LIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGT0LIM: PTG Timer0 Limit Register bits
General purpose Timer0 Limit register (effective only with a PTGT0 Step command).
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
PTGT1LIM: PTG TIMER1 LIMIT REGISTER(1)
REGISTER 25-5:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT1LIM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT1LIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGT1LIM: PTG Timer1 Limit Register bits
General purpose Timer1 Limit register (effective only with a PTGT1 Step command).
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 25-6:
R/W-0
PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PTGSDLIM: PTG Step Delay Limit Register bits
Holds a PTG step delay value, representing the number of additional PTG clocks, between the start
of a Step command and the completion of a Step command.
A base step delay of one PTG clock is added to any value written to the PTGSDLIM register
(Step Delay = (PTGSDLIM) + 1).
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 25-7:
R/W-0
PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC0LIM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC0LIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGC0LIM: PTG Counter 0 Limit Register bits
May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the
General Purpose Counter 0.
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1)
REGISTER 25-8:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC1LIM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC1LIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGC1LIM: PTG Counter 1 Limit Register bits
May be used to specify the loop count for the PTGJMPC1 Step command, or as a limit register for the
General Purpose Counter 1.
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
PTGHOLD: PTG HOLD REGISTER(1)
REGISTER 25-9:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGHOLD
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGHOLD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGHOLD: PTG General Purpose Hold Register bits
Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 register
with the PTGCOPY command.
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 25-10: PTGADJ: PTG ADJUST REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGADJ
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGADJ
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGADJ: PTG Adjust Register bits
This register holds user-supplied data to be added to the PTGTxLIM, PTGCxLIM, PTGSDLIM or
PTGL0 register with the PTGADD command.
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 25-11: PTGL0: PTG LITERAL 0 REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGL0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
x = Bit is unknown
PTGL0: PTG Literal 0 Register bits
This register holds the 16-bit value to be written to the AD1CHS0 register with the PTGCTRL Step
command.
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
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REGISTER 25-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGQPTR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
PTGQPTR: PTG Step Queue Pointer Register bits
This register points to the currently active Step command in the step queue.
Note 1:
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 25-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-15)(1,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP(2x + 1)(2)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP(2x)(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
STEP(2x + 1): PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x +1) command byte.
bit 7-0
STEP(2x): PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x) command byte.
Note 1:
2:
3:
x = Bit is unknown
This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
Refer to Table 25-1 for the Step command encoding.
The Step registers maintain their values on any type of Reset.
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25.3
Step Commands and Format
TABLE 25-1:
PTG STEP COMMAND FORMAT
Step Command Byte:
STEPx
CMD
OPTION
bit 7
bit 7-4
bit 4 bit 3
CMD
Step
Command
bit 0
Command Description
0000
PTGCTRL
Execute control command as described by OPTION
0001
PTGADD
Add contents of PTGADJ register to target register as described by
OPTION
PTGCOPY
Copy contents of PTGHOLD register to target register as described by
OPTION
001x
PTGSTRB
Copy the value contained in CMD0:OPTION to the CH0SA bits
(AD1CHS0)
0100
PTGWHI
Wait for a low-to-high edge input from selected PTG trigger input as described
by OPTION
0101
PTGWLO
Wait for a high-to-low edge input from selected PTG trigger input as described
by OPTION
0110
Reserved
Reserved
0111
PTGIRQ
Generate individual interrupt request as described by OPTION
100x
PTGTRIG
Generate individual trigger output as described by
101x
PTGJMP
Copy the value indicated in to the Queue Pointer
(PTGQPTR) and jump to that step queue
110x
PTGJMPC0
PTGC0 = PTGC0LIM: Increment the Queue Pointer (PTGQPTR)
PTGC0 PTGC0LIM: Increment Counter 0 (PTGC0) and copy the value
indicated in to the Queue Pointer (PTGQPTR) and
jump to that step queue
111x
PTGJMPC1
PTGC1 = PTGC1LIM: Increment the Queue Pointer (PTGQPTR)
PTGC1 PTGC1LIM: Increment Counter 1 (PTGC1) and copy the value
indicated in to the Queue Pointer (PTGQPTR) and
jump to that step queue
Note 1:
2:
All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
Refer to Table 25-2 for the trigger output descriptions.
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TABLE 25-1:
bit 3-0
PTG STEP COMMAND FORMAT (CONTINUED)
Step
Command
OPTION
PTGCTRL(1)
0000
Reserved
0001
Reserved
0010
Disable Step Delay Timer (PTGSD)
0011
Reserved
0100
Reserved
0101
Reserved
0110
Enable Step Delay Timer (PTGSD)
0111
Reserved
1000
Start and wait for the PTG Timer0 to match Timer0 Limit register
PTGADD(1)
PTGCOPY(1)
Note 1:
2:
Option Description
1001
Start and wait for the PTG Timer1 to match Timer1 Limit register
1010
Reserved
1011
Wait for software trigger bit transition from low-to-high before continuing
(PTGSWT = 0 to 1)
1100
Copy contents of the Counter 0 register to the AD1CHS0 register
1101
Copy contents of the Counter 1 register to the AD1CHS0 register
1110
Copy contents of the Literal 0 register to the AD1CHS0 register
1111
Generate the triggers indicated in the PTG Broadcast Trigger Enable register
(PTGBTE)
0000
Add contents of PTGADJ register to the Counter 0 Limit register (PTGC0LIM)
0001
Add contents of PTGADJ register to the Counter 1 Limit register (PTGC1LIM)
0010
Add contents of PTGADJ register to the Timer0 Limit register (PTGT0LIM)
0011
Add contents of PTGADJ register to the Timer1 Limit register (PTGT1LIM)
0100
Add contents of PTGADJ register to the Step Delay Limit register (PTGSDLIM)
0101
Add contents of PTGADJ register to the Literal 0 register (PTGL0)
0110
Reserved
0111
Reserved
1000
Copy contents of PTGHOLD register to the Counter 0 Limit register
(PTGC0LIM)
1001
Copy contents of PTGHOLD register to the Counter 1 Limit register
(PTGC1LIM)
1010
Copy contents of PTGHOLD register to the Timer0 Limit register (PTGT0LIM)
1011
Copy contents of PTGHOLD register to the Timer1 Limit register (PTGT1LIM)
1100
Copy contents of PTGHOLD register to the Step Delay Limit register
(PTGSDLIM)
1101
Copy contents of PTGHOLD register to the Literal 0 register (PTGL0)
1110
Reserved
1111
Reserved
All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
Refer to Table 25-2 for the trigger output descriptions.
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TABLE 25-1:
bit 3-0
PTG STEP COMMAND FORMAT (CONTINUED)
Step
Command
PTGWHI(1)
or
PTGWLO(1)
PTGIRQ(1)
OPTION
0000
PWM Special Event Trigger
0001
PWM master time base synchronization output
0010
PWM1 interrupt
0011
PWM2 interrupt
0100
PWM3 interrupt
0101
PWM4 interrupt
0110
PWM5 interrupt
0111
OC1 Trigger Event
1000
OC2 Trigger Event
1001
IC1 Trigger Event
1010
CMP1 Trigger Event
1011
CMP2 Trigger Event
1100
CMP3 Trigger Event
1101
CMP4 Trigger Event
1110
ADC conversion done interrupt
1111
INT2 external interrupt
0000
Generate PTG Interrupt 0
0001
Generate PTG Interrupt 1
0010
Generate PTG Interrupt 2
0011
Generate PTG Interrupt 3
0100
Reserved
•
•
•
PTGTRIG(2)
•
•
•
1111
Reserved
00000
PTGO0
00001
PTGO1
•
•
•
Note 1:
2:
Option Description
•
•
•
11110
PTGO30
11111
PTGO31
All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
Refer to Table 25-2 for the trigger output descriptions.
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TABLE 25-2:
PTG OUTPUT DESCRIPTIONS
PTG Output
Number
PTG Output Description
PTGO0
Trigger/Synchronization Source for OC1
PTGO1
Trigger/Synchronization Source for OC2
PTGO2
Trigger/Synchronization Source for OC3
PTGO3
Trigger/Synchronization Source for OC4
PTGO4
Clock Source for OC1
PTGO5
Clock Source for OC2
PTGO6
Clock Source for OC3
PTGO7
Clock Source for OC4
PTGO8
Trigger/Synchronization Source for IC1
PTGO9
Trigger/Synchronization Source for IC2
PTGO10
Trigger/Synchronization Source for IC3
PTGO11
Trigger/Synchronization Source for IC4
PTGO12
Sample Trigger for ADC
PTGO13
Sample Trigger for ADC
PTGO14
Sample Trigger for ADC
PTGO15
Sample Trigger for ADC
PTGO16
PWM Time Base Synchronous Source for PWM
PTGO17
PWM Time Base Synchronous Source for PWM
PTGO18
Mask Input Select for Op Amp/Comparator
PTGO19
Mask Input Select for Op Amp/Comparator
PTGO20
Reserved
PTGO21
Reserved
PTGO22
Reserved
PTGO23
Reserved
PTGO24
Reserved
PTGO25
Reserved
PTGO26
Reserved
PTGO27
Reserved
PTGO28
Reserved
PTGO29
Reserved
PTGO30
PTG Output to PPS Input Selection
PTGO31
PTG Output to PPS Input Selection
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dsPIC33EPXXXGM3XX/6XX/7XX
26.0
OP AMP/COMPARATOR
MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24
Family Reference Manual”, “Op Amp/
Comparator” (DS70000357), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 26-1:
The dsPIC33EPXXXGM3XX/6XX/7XX devices contain
up to five comparators that can be configured in various
ways. Comparators, CMP1, CMP2, CMP3 and CMP5,
also have the option to be configured as op amps, with
the output being brought to an external pin for gain/
filtering connections. As shown in Figure 26-1, individual
comparator options are specified by the comparator
module’s Special Function Register (SFR) control bits.
These options allow users to:
•
•
•
•
Select the edge for trigger and interrupt generation
Configure the comparator voltage reference
Configure output blanking and masking
Configure as a comparator or op amp
(CMP1, CMP2, CMP3 and CMP5 only)
Note:
Not all op amp/comparator input/output
connections are available on all devices.
See the “Pin Diagrams” section for
available connections.
OP AMP/COMPARATOR x MODULE BLOCK DIAGRAM
Op Amp/Comparator 1, 2, 3, 5
(x = 1, 2, 3, 5)
CCH (CMxCON)
CxIN1CxIN2-
00
01
CXIN3CXIN4-
10
11
CxIN1+
0
CVREFIN
1
Op Amp/Comparator
VINVIN+
–
CMPx
+
Blanking
Function
(see Figure 26-3)
Digital
Filter
(see Figure 26-4)
CxOUT(1)
PTG Trigger
Input
OPMODE (CMxCON)
–
Op Amp x
OAxOUT
+
OAx
(to ADCx)
CREF (CMxCON)
CCH (CM4CON)
OA1/AN3
01
OA2/AN0
10
OA3/AN6
11
C4IN1-
00
C4IN1+
0
CVREFIN
1
VINVIN+
–
CMP4
+
Comparator 4
Blanking
Function
(see Figure 26-3)
Digital
Filter
(see Figure 26-4)
C4OUT(1)
Trigger
Output
CREF (CMxCON)
Note 1:
The CxOUT pin is not a dedicated output pin on the device. This must be mapped to a physical pin using
Peripheral Pin Select (PPS). Refer to Section 11.0 “I/O Ports” for more information.
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FIGURE 26-2:
OP AMP/COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREFSEL
(CVR1CON)
AVDD
CVRSS = 1
(CVR1CON)
CVRSRC
1
CVR1CON
CVRSS = 0
8R
(CVR1CON)
CVREN
(CVR1CON)
CVREFIN
CVR3
CVR2
CVR1
CVR0
VREF+
0
R
CVRR1
(CVR1CON)
R
R
16-to-1 MUX
R
16 Steps
R
CVREF1O
CVROE
(CVR1CON)
R
VREFSEL
(CVR2CON)
R
CVRR0
(CVR1CON)
8R
0
AVSS
AVDD
CVRSS = 1
(CVR2CON)
CVRSRC
CVR2CON
CVRSS = 0
8R
(CVR2CON)
CVREN
(CVR2CON)
CVR3
CVR2
CVR1
CVR0
VREF+
1
R
CVRR1
(CVR2CON)
R
R
16-to-1 MUX
R
16 Steps
R
CVREF2O
CVROE
(CVR2CON)
R
R
CVRR0
(CVR2CON)
8R
AVSS
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FIGURE 26-3:
USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM
SELSRCA
(CMxMSKSRC)
MUX A
Comparator Output
Blanking
Signals
MAI
“AND-OR” Function
MAI
MBI
Blanking
Logic
To Digital
Filter
ANDI
AND
SELSRCB
(CMxMSKSRC VIN0 = VIN+ < VINWhen CPOL = 1 (inverted polarity):
1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1:
2:
3:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
The op amp and the comparator can be used simultaneously in these devices. The OPMODE bit only
enables the op amp while the comparator is still functional.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL (CMxCON) = 10 or 01), the Comparator Event bit, CEVT (CMxCON), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1), must be cleared before enabling the
Comparator Interrupt Enable bit, CMPIE (IEC1).
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REGISTER 26-2:
CMxCON: OP AMP/COMPARATOR x CONTROL
REGISTER (x = 1, 2, 3 OR 5) (CONTINUED)
bit 7-6
EVPOL: Trigger/Event/Interrupt Polarity Select bits(3)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled.
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to internal CVREFIN voltage
0 = VIN+ input connects to CxIN1+ pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Op Amp/Comparator Channel Select bits(1)
11 = Inverting input of op amp/comparator connects to CxIN4- pin
10 = Inverting input of op amp/comparator connects to CxIN3- pin
01 = Inverting input of op amp/comparator connects to CxIN2- pin
00 = Inverting input of op amp/comparator connects to CxIN1- pin
Note 1:
2:
3:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
The op amp and the comparator can be used simultaneously in these devices. The OPMODE bit only
enables the op amp while the comparator is still functional.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL (CMxCON) = 10 or 01), the Comparator Event bit, CEVT (CMxCON), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1), must be cleared before enabling the
Comparator Interrupt Enable bit, CMPIE (IEC1).
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REGISTER 26-3:
R/W-0
CM4CON: OP AMP/COMPARATOR 4 CONTROL REGISTER
R/W-0
CON
R/W-0
COE
CPOL
U-0
U-0
—
—
U-0
—
R/W-0
CEVT
(2)
R/W-0
COUT
bit 15
bit 8
R/W-0
EVPOL1
R/W-0
(2)
U-0
(2)
EVPOL0
—
R/W-0
U-0
(1)
CREF
—
U-0
—
R/W-0
CCH1
(1)
R/W-0
CCH0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CON: Op Amp/Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14
COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10
Unimplemented: Read as ‘0’
bit 9
CEVT: Comparator Event bit(2)
1 = Comparator event, according to the EVPOL settings, occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8
COUT: Comparator Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1 (inverted polarity):
1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1:
2:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL (CMxCON) = 10 or 01), the Comparator Event bit, CEVT (CMxCON), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1), must be cleared before enabling the
Comparator Interrupt Enable bit, CMPIE (IEC1).
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REGISTER 26-3:
CM4CON: OP AMP/COMPARATOR 4 CONTROL REGISTER (CONTINUED)
bit 7-6
EVPOL: Trigger/Event/Interrupt Polarity Select bits(2)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to internal CVREFIN voltage
0 = VIN+ input connects to C4IN1+ pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Comparator Channel Select bits(1)
11 = VIN- input of comparator connects to OA3/AN6
10 = VIN- input of comparator connects to OA2/AN0
01 = VIN- input of comparator connects to OA1/AN3
00 = VIN- input of comparator connects to C4IN1-
Note 1:
2:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL (CMxCON) = 10 or 01), the Comparator Event bit, CEVT (CMxCON), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1), must be cleared before enabling the
Comparator Interrupt Enable bit, CMPIE (IEC1).
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REGISTER 26-4:
CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT
CONTROL REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
RW-0
—
—
—
—
SELSRCC3
SELSRCC2
SELSRCC1
SELSRCC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
SELSRCB3
SELSRCB2
SELSRCB1
R/W-0
R/W-0
SELSRCB0 SELSRCA3
R/W-0
R/W-0
R/W-0
SELSRCA2
SELSRCA1
SELSRCA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
SELSRCC: Mask C Input Select bits
1111 = FLT4
1110 = FLT2
1101 = PTGO19
1100 = PTGO18
1011 = PWM6H
1010 = PWM6L
1001 = PWM5H
1000 = PWM5L
0111 = PWM4H
0110 = PWM4L
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
bit 7-4
SELSRCB: Mask B Input Select bits
1111 = FLT4
1110 = FLT2
1101 = PTGO19
1100 = PTGO18
1011 = PWM6H
1010 = PWM6L
1001 = PWM5H
1000 = PWM5L
0111 = PWM4H
0110 = PWM4L
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
2013-2014 Microchip Technology Inc.
x = Bit is unknown
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 26-4:
bit 3-0
CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT
CONTROL REGISTER (CONTINUED)
SELSRCA: Mask A Input Select bits
1111 = FLT4
1110 = FLT2
1101 = PTGO19
1100 = PTGO18
1011 = PWM6H
1010 = PWM6L
1001 = PWM5H
1000 = PWM5L
0111 = PWM4H
0110 = PWM4L
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 26-5:
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
OANEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HLMS: High or Low-Level Masking Select bit
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14
Unimplemented: Read as ‘0’
bit 13
OCEN: OR Gate C Input Enable bit
1 = MCI is connected to the OR gate
0 = MCI is not connected to the OR gate
bit 12
OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to the OR gate
0 = Inverted MCI is not connected to the OR gate
bit 11
OBEN: OR Gate B Input Enable bit
1 = MBI is connected to the OR gate
0 = MBI is not connected to the OR gate
bit 10
OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to the OR gate
0 = Inverted MBI is not connected to the OR gate
bit 9
OAEN: OR Gate A Input Enable bit
1 = MAI is connected to the OR gate
0 = MAI is not connected to the OR gate
bit 8
OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to the OR gate
0 = Inverted MAI is not connected to the OR gate
bit 7
NAGS: AND Gate Output Inverted Enable bit
1 = Inverted ANDI is connected to the OR gate
0 = Inverted ANDI is not connected to the OR gate
bit 6
PAGS: AND Gate Output Enable bit
1 = ANDI is connected to the OR gate
0 = ANDI is not connected to the OR gate
bit 5
ACEN: AND Gate C Input Enable bit
1 = MCI is connected to the AND gate
0 = MCI is not connected to the AND gate
bit 4
ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to the AND gate
0 = Inverted MCI is not connected to the AND gate
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REGISTER 26-5:
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER (CONTINUED)
bit 3
ABEN: AND Gate B Input Enable bit
1 = MBI is connected to the AND gate
0 = MBI is not connected to the AND gate
bit 2
ABNEN: AND Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to the AND gate
0 = Inverted MBI is not connected to the AND gate
bit 1
AAEN: AND Gate A Input Enable bit
1 = MAI is connected to the AND gate
0 = MAI is not connected to the AND gate
bit 0
AANEN: AND Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to the AND gate
0 = Inverted MAI is not connected to the AND gate
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 26-6:
CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
CFSEL: Comparator Filter Input Clock Select bits
111 = T5CLK(1)
110 = T4CLK(2)
101 = T3CLK(1)
100 = T2CLK(2)
011 = SYNCO2
010 = SYNCO1(3)
001 = FOSC(4)
000 = FP(4)
bit 3
CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0
CFDIV: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
Note 1:
2:
3:
4:
x = Bit is unknown
See the Type C Timer Block Diagram (Figure 13-2).
See the Type B Timer Block Diagram (Figure 13-1).
See the PWMx Module Register Interconnect Diagram (Figure 16-2).
See the Oscillator System Diagram (Figure 9-1).
2013-2014 Microchip Technology Inc.
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REGISTER 26-7:
CVR1CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
—
—
—
—
CVRR1
VREFSEL
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR0
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11
CVRR1: Comparator Voltage Reference Range Selection bit
See bit 5.
bit 10
VREFSEL: Voltage Reference Select bit
1 = CVREFIN = VREF+
0 = CVREFIN is generated by the resistor network
bit 9-8
Unimplemented: Read as ‘0’
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6
CVROE: Comparator Voltage Reference Output Enable on CVREF1O Pin bit
1 = Voltage level is output on the CVREF1O pin
0 = Voltage level is disconnected from the CVREF1O pin
bit 11, 5
CVRR: Comparator Voltage Reference Range Selection bits
11 = 0.00 CVRSRC to 0.94, with CVRSRC/16 step-size
10 = 0.33 CVRSRC to 0.96, with CVRSRC/24 step-size
01 = 0.00 CVRSRC to 0.67, with CVRSRC/24 step-size
00 = 0.25 CVRSRC to 0.75, with CVRSRC/32 step-size
bit 4
CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator voltage reference source, CVRSRC = CVREF+ – AVSS
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR Comparator Voltage Reference Value Selection 0 CVR 15 bits
When CVRR = 11:
CVREF = (CVR/16) (CVRSRC)
When CVRR = 10:
CVREF = (1/3) (CVRSRC) + (CVR/24) (CVRSRC)
When CVRR = 01:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 00:
CVREF = (1/4) (CVRSRC) + (CVR/32) (CVRSRC)
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 26-8:
CVR2CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
—
—
—
—
CVRR1
VREFSEL
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CVREN
CVROE
CVRR0
CVRSS
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11
CVRR1: Comparator Voltage Reference Range Selection bit
See bit 5.
bit 10
VREFSEL: Voltage Reference Select bit
1 = Reference source for inverting input is from CVR2
0 = Reference source for inverting input is from CVR1
bit 9-8
Unimplemented: Read as ‘0’
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6
CVROE: Comparator Voltage Reference Output Enable on CVREF2O Pin bit
1 = Voltage level is output on the CVREF2O pin
0 = Voltage level is disconnected from the CVREF2O pin
bit 11, 5
CVRR: Comparator Voltage Reference Range Selection bits
11 = 0.00 CVRSRC to 0.94, with CVRSRC/16 step-size
10 = 0.33 CVRSRC to 0.96, with CVRSRC/24 step-size
01 = 0.00 CVRSRC to 0.67, with CVRSRC/24 step-size
00 = 0.25 CVRSRC to 0.75, with CVRSRC/32 step-size
bit 4
CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator voltage reference source, CVRSRC = CVREF+ – AVSS
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0
CVR Comparator Voltage Reference Value Selection 0 CVR 15 bits
When CVRR = 11:
CVREF = (CVR/16) (CVRSRC)
When CVRR = 10:
CVREF = (1/3) (CVRSRC) + (CVR/24) (CVRSRC)
When CVRR = 01:
CVREF = (CVR/24) (CVRSRC)
When CVRR = 00:
CVREF = (1/4) (CVRSRC) + (CVR/32) (CVRSRC)
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NOTES:
DS70000689D-page 382
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dsPIC33EPXXXGM3XX/6XX/7XX
27.0
REAL-TIME CLOCK AND
CALENDAR (RTCC)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Real-Time Clock
and Calendar (RTCC)” (DS70584), which
is available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This chapter discusses the Real-Time Clock and
Calendar (RTCC) module and its operation.
Some of the key features of this module are:
•
•
•
•
•
•
•
•
•
•
•
•
Time: Hours, Minutes and Seconds
24-Hour Format (military time)
Calendar: Weekday, Date, Month and Year
Alarm Configurable
Year Range: 2000 to 2099
Leap Year Correction
BCD Format for Compact Firmware
Optimized for Low-Power Operation
User Calibration with Auto-Adjust
Calibration Range: ±2.64 Seconds Error per Month
Requirements: External 32.768 kHz Clock Crystal
Alarm Pulse or Seconds Clock Output on RTCC Pin
The RTCC module is intended for applications where
accurate time must be maintained for extended periods
with minimum to no intervention from the CPU. The
RTCC module is optimized for low-power usage to
provide extended battery lifetime while keeping track of
time.
The RTCC module is a 100-year clock and calendar
with automatic leap year detection. The range of the
clock is from 00:00:00 (midnight) on January 1, 2000 to
23:59:59 on December 31, 2099.
The hours are available in 24-hour (military time)
format. The clock provides a granularity of one second
with half-second visibility to the user.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 27-1:
RTCC BLOCK DIAGRAM
RTCPTR
dsPIC33EPXXXGM
RTCC Timer
CAL
SOSCO
32.768 kHz
Oscillator
Prescaler
1 Hz
—
YEAR
11
MONTH
DATE
10
WEEKDAY
HOUR
01
MINUTES
SECONDS
00
RTCVAL
SOSCI
RTCOE
RTCC
Pin
1
0
Toggle
RTSECSEL
Set RTCCIF Flag
ALRMPTR
RTCC Alarm
Note:
MONTH
DATE
10
WEEKDAY
HOUR
01
MINUTES
SECONDS
00
ALRMVAL
The RTCC is only operational on devices which include the SOSC; therefore, the RTCC module is not
available on 44-pin devices.
DS70000689D-page 384
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dsPIC33EPXXXGM3XX/6XX/7XX
27.1
Note:
Writing to the RTCC Timer
To allow the RTCC module to be
clocked by the secondary crystal oscillator, the Secondary Oscillator Enable
(LPOSCEN) bit in the Oscillator Control
(OSCCON) register must be set. For
further details, refer to the “dsPIC33/
PIC24 Family Reference Manual”,
“Oscillator” (DS70580).
The user application can configure the time and
calendar by writing the desired seconds, minutes,
hours, weekday, date, month and year to the RTCC
registers. Under normal operation, writes to the RTCC
Timer registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To write to the RTCC
register, the RTCWREN bit (RCFGCAL) must be
set. Setting the RTCWREN bit allows writes to the
RTCC registers. Conversely, clearing the RTCWREN
bit prevents writes.
To set the RTCWREN bit, the following procedure must
be executed. The RTCWREN bit can be cleared at any
time:
1.
2.
3.
Write 0x55 to NVMKEY.
Write 0xAA to NVMKEY.
Set the RTCWREN bit using a single-cycle
instruction.
27.2
RTCC Resources
Many useful resources related to RTCC are provided
on the main product page of the Microchip web site for
the devices listed in this data sheet. This product page,
which can be accessed using this link, contains the
latest updates and additional information.
Note:
27.2.1
In the event you are not able to access the
product page using the link above, enter
this URL in your browser:
http://www.microchip.com/wwwproducts/
Devices.aspx?dDocName=en554310
KEY RESOURCES
• “Real-Time Clock and Calendar (RTCC)”
(DS70584) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
The RTCC module is enabled by setting the RTCEN bit
(RCFGCAL). To set or clear the RTCEN bit, the
RTCWREN bit (RCFGCAL) must be set.
If the entire clock (hours, minutes and seconds) needs
to be corrected, it is recommended that the RTCC
module should be disabled to avoid coincidental write
operation when the timer increments. Therefore, it
stops the clock from counting while writing to the RTCC
Timer register.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
27.3
RTCC Registers
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
REGISTER 27-1:
R/W-0
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
RTCEN(2)
—
RTCWREN
RTCSYNC
HALFSEC(3)
RTCOE
RTCPTR1
RTCPTR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
RTCWREN: RTCC Value Register Write Enable bit
1 = RTCVAL register can be written to by the user application
0 = RTCVAL register is locked out from being written to by the user application
bit 12
RTCSYNC: RTCC Value Register Read Synchronization bit
1 = A rollover is about to occur in 32 clock edges (approximately 1 ms)
0 = A rollover will not occur
bit 11
HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8
RTCPTR: RTCC Value Register Pointer bits
Points to the corresponding RTCC Value register when reading the RTCVAL register; the
RTCPTR value decrements on every access of the RTCVAL register until it reaches ‘00’.
bit 7-0
CAL: RTCC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTCC clock pulses every one minute
•
•
•
00000001 = Minimum positive adjustment; adds 4 RTCC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTCC clock pulses every one minute
•
•
•
10000000 = Maximum negative adjustment; subtracts 512 RTCC clock pulses every one minute
Note 1:
2:
3:
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only. It is cleared when the lower half of the MINSEC register is written.
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REGISTER 27-2:
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
RTSECSEL(1)
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-2
Unimplemented: Read as ‘0’
bit 1
RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin
0 = RTCC alarm pulse is selected for the RTCC pin
bit 0
Not used by the RTCC module.
Note 1:
x = Bit is unknown
To enable the actual RTCC output, the RTCOE bit (RCFGCAL) must be set.
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REGISTER 27-3:
ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1
ALRMPTR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 0x00 and
CHIME = 0)
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit
1 = Chime is enabled; ARPT bits are allowed to roll over from 0x00 to 0xFF
0 = Chime is disabled; ARPT bits stop once they reach 0x00
bit 13-10
AMASK: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 9-8
ALRMPTR: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading the ALRMVAL register. The
ALRMPTR value decrements on every read or write of ALRMVAL until it reaches ‘00’.
bit 7-0
ARPT: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
•
•
•
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to
0xFF unless CHIME = 1.
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REGISTER 27-4:
RTCVAL (WHEN RTCPTR = 11): YEAR VALUE REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-4
YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0
YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 27-5:
RTCVAL (WHEN RTCPTR = 10): MONTH AND DAY VALUE REGISTER(1)
U-0
U-0
U-0
R-x
R-x
R-x
R-x
R-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8
MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
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RTCVAL (WHEN RTCPTR = 01): WEEKDAY AND HOURS VALUE REGISTER(1)
REGISTER 27-6:
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
WDAY: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 27-7:
RTCVAL (WHEN RTCPTR = 00): MINUTES AND SECONDS VALUE REGISTER
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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REGISTER 27-8:
ALRMVAL (WHEN ALRMPTR = 10): ALARM MONTH AND DAY VALUE
REGISTER(1)
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8
MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
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REGISTER 27-9:
ALRMVAL (WHEN ALRMPTR = 01): ALARM WEEKDAY AND HOURS
VALUE REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
WDAY: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
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REGISTER 27-10: ALRMVAL (WHEN ALRMPTR = 00): ALARM MINUTES AND SECONDS
VALUE REGISTER
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
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NOTES:
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28.0
PARALLEL MASTER PORT
(PMP)
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Parallel Master
Port (PMP)” (DS70576), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
Key features of the PMP module include:
•
•
•
•
•
•
•
•
•
•
FIGURE 28-1:
Eight Data Lines
Up to 16 Programmable Address Lines
Up to 2 Chip Select Lines
Programmable Strobe Options:
- Individual read and write strobes, or
- Read/Write strobe with enable strobe
Address Auto-Increment/Auto-Decrement
Programmable Address/Data Multiplexing
Programmable Polarity on Control Signals
Legacy Parallel Slave Port (PSP) Support
Enhanced Parallel Slave Support:
- Address support
- 4-byte deep auto-incrementing buffer
Programmable Wait States
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
dsPIC33EP
PMA
PMALL
Up to 16-Bit Address
EEPROM
PMA
PMALH
PMA
PMA
PMCS1
Parallel Master Port
Address Bus
Data Bus
Control Lines
PMA
PMCS2
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
PMD
PMA
PMA
Microcontroller
LCD
FIFO
Buffer
8-Bit Data (with or without multiplexed addressing)
Note: Not all PMP port pins are 5V tolerant. Refer to the “Pin Diagrams” section for availability.
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28.1
PMP Control Registers
PMCON: PARALLEL MASTER PORT CONTROL REGISTER(3)
REGISTER 28-1:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPEN
—
PSIDL
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0
R/W-0
R/W-0
CSF1
CSF0
ALP
CS2P
CS1P
BEP
WRSP
RDSP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PMPEN: Parallel Master Port Enable bit
1 = PMP module is enabled
0 = PMP module is disabled, no off-chip access is performed
bit 14
Unimplemented: Read as ‘0’
bit 13
PSIDL: PMP Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-11
ADRMUX: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD pins
01 = Lower eight bits of address are multiplexed on PMD pins, upper eight bits are on PMA
00 = Address and data appear on separate pins
bit 10
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port is enabled
0 = PMBE port is disabled
bit 9
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6
CSF: Chip Select Function bits
11 = Reserved
10 = PMCS1 and PMCS2 function as Chip Select
01 = PMCS2 functions as Chip Select, PMCS1 functions as Address Bit 14
00 = PMCS1 and PMCS2 function as Address Bits 15 and 14
bit 5
ALP: Address Latch Polarity bit(1)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4
CS2P: Chip Select 1 Polarity bit(1)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
Note 1:
2:
3:
These bits have no effect when their corresponding pins are used as address lines.
PMCS1 applies to Master mode and PMCS applies to Slave mode.
This register is not available on 44-pin devices.
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REGISTER 28-1:
PMCON: PARALLEL MASTER PORT CONTROL REGISTER(3) (CONTINUED)
bit 3
CS1P: Chip Select 0 Polarity bit(1)
1 = Active-high (PMCS1/PMCS)(2)
0 = Active-low (PMCS1/PMCS)
bit 2
BEP: Byte Enable Polarity bit
1 = Byte enable is active-high (PMBE)
0 = Byte enable is active-low (PMBE)
bit 1
WRSP: Write Strobe Polarity bit
For Slave Modes and Master Mode 2 (PMMODE = 00, 01, 10):
1 = Write strobe is active-high (PMWR)
0 = Write strobe is active-low (PMWR)
For Master Mode 1 (PMMODE = 11):
1 = Enables strobe active-high (PMENB)
0 = Enables strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave Modes and Master Mode 2 (PMMODE = 00, 01, 10):
1 = Read strobe is active-high (PMRD)
0 = Read strobe is active-low (PMRD)
For Master Mode 1 (PMMODE = 11):
1 = Enables strobe active-high (PMRD/PMWR)
0 = Enables strobe active-low (PMRD/PMWR)
Note 1:
2:
3:
These bits have no effect when their corresponding pins are used as address lines.
PMCS1 applies to Master mode and PMCS applies to Slave mode.
This register is not available on 44-pin devices.
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REGISTER 28-2:
PMMODE: PARALLEL MASTER PORT MODE REGISTER(4)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
bit 15
bit 8
R/W-0
R/W-0
WAITB1(1,2,3) WAITB0(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
WAITM3
WAITM2
WAITM1
WAITM0
R/W-0
R/W-0
WAITE1(1,2,3) WAITE0(1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13
IRQM: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP
mode), or on a read/write operation when PMA = 11 (Addressable PSP mode only)
10 = Reserved
01 = Interrupt is generated at the end of the read/write cycle
00 = No Interrupt is generated
bit 12-11
INCM: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR by 1 every read/write cycle
01 = Increment ADDR by 1 every read/write cycle
00 = No increment or decrement of address
bit 10
MODE16: 8/16-Bit Mode bit
1 = 16-Bit Mode: Data register is 16 bits, a read/write to the Data register invokes two 8-bit transfers
0 = 8-Bit Mode: Data register is 8 bits, a read/write to the Data register invokes one 8-bit transfer
bit 9-8
MODE: Parallel Slave Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA and PMD)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA and PMD)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCSx, PMD and PMA)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx and PMD)
bit 7-6
WAITB: Data Setup to Read/Write/Address Phase Wait State Configuration bits(1,2,3)
11 = Data Wait of 4 TP (demultiplexed/multiplexed); address phase of 4 TP (multiplexed)
10 = Data Wait of 3 TP (demultiplexed/multiplexed); address phase of 3 TP (multiplexed)
01 = Data Wait of 2 TP (demultiplexed/multiplexed); address phase of 2 TP (multiplexed)
00 = Data Wait of 1 TP (demultiplexed/multiplexed); address phase of 1 TP (multiplexed)
Note 1:
2:
3:
4:
The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See
Section 4.1.8 “Wait States” in the “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33/PIC24
Family Reference Manual” for more information.
WAITB and WAITE bits are ignored whenever WAITM = 0000.
TP = 1/FP.
This register is not available on 44-pin devices.
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REGISTER 28-2:
PMMODE: PARALLEL MASTER PORT MODE REGISTER(4) (CONTINUED)
bit 5-2
WAITM: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TP
•
•
•
0001 = Wait of additional 1 TP
0000 = No additional Wait cycles (operation forced into one TP)
bit 1-0
WAITE: Data Hold After Strobe Wait State Configuration bits(1,2,3)
11 = Wait of 4 TP
10 = Wait of 3 TP
01 = Wait of 2 TP
00 = Wait of 1 TP
Note 1:
2:
3:
4:
The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See
Section 4.1.8 “Wait States” in the “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33/PIC24
Family Reference Manual” for more information.
WAITB and WAITE bits are ignored whenever WAITM = 0000.
TP = 1/FP.
This register is not available on 44-pin devices.
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REGISTER 28-3:
PMADDR: PARALLEL MASTER PORT ADDRESS REGISTER
(MASTER MODES ONLY)(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CS2
CS1
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CS2: Chip Select 2 bit
If PMCON = 10 or 01:
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
If PMCON = 11 or 00:
Bit functions as ADDR15.
bit 14
CS1: Chip Select 1 bit
If PMCON = 10:
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
If PMCON = 11 or 0x:
Bit functions as ADDR14.
bit 13-0
ADDR: Destination Address bits
Note 1:
2:
x = Bit is unknown
In Enhanced Slave mode, PMADDR functions as PMDOUT1, one of the two Data Buffer registers.
This register is not available on 44-pin devices.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 28-4:
PMAEN: PARALLEL MASTER PORT ADDRESS ENABLE REGISTER(1)
R/W-0
R/W-0
PTEN15
PTEN14
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN
R/W-0
PTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PTEN15: PMCS2 Strobe Enable bit
1 = PMA15 functions as either PMA or PMCS2
0 = PMA15 functions as port I/O
bit 14
PTEN14: PMCS1 Strobe Enable bit
1 = PMA14 functions as either PMA or PMCS1
0 = PMA14 functions as port I/O
bit 13-2
PTEN: PMP Address Port Enable bits
1 = PMA function as PMP address lines
0 = PMA function as port I/Os
bit 1-0
PTEN: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL
0 = PMA1 and PMA0 function as port I/Os
Note 1:
This register is not available on 44-pin devices.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 28-5:
PMSTAT: PARALLEL MASTER PORT STATUS REGISTER (SLAVE MODE ONLY)(1)
R-0
R/W-0, HS
U-0
U-0
R-0
R-0
R-0
R-0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
bit 15
bit 8
R-1
R/W-0, HS
U-0
U-0
R-1
R-1
R-1
R-1
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IBF: Input Buffer Full Status bit
1 = All writable Input Buffer registers are full
0 = Some or all of the writable Input Buffer registers are empty
bit 14
IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full Input Byte register occurred (must be cleared in software)
0 = No overflow occurred
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
IB3F:IB0F: Input Buffer x Status Full bit
1 = Input Buffer x contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer x does not contain any unread data
bit 7
OBE: Output Buffer Empty Status bit
1 = All readable Output Buffer registers are empty
0 = Some or all of the readable Output Buffer registers are full
bit 6
OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty Output Byte register (must be cleared in software)
0 = No underflow occurred
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
OB3E:OB0E: Output Buffer x Status Empty bit
1 = Output Buffer x is empty (writing data to the buffer will clear this bit)
0 = Output Buffer x contains data that has not been transmitted
Note 1:
This register is not available on 44-pin devices.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 28-6:
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
RTSECSEL
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-2
x = Bit is unknown
Unimplemented: Read as ‘0’
bit 1
Not used by the PMP module.
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
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NOTES:
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dsPIC33EPXXXGM3XX/6XX/7XX
29.0
The programmable CRC generator offers the following
features:
PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
• User-Programmable (up to 32nd order)
polynomial CRC equation
• Interrupt Output
• Data FIFO
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family Reference Manual”, “32-Bit Programmable
Cyclic Redundancy Check (CRC)”
(DS70346), which is available from the
Microchip web site (www.microchip.com).
The programmable CRC generator provides a
hardware-implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
• User-programmable CRC polynomial equation,
up to 32 bits
• Programmable shift direction (little or big-endian)
• Independent data and polynomial lengths
• Configurable interrupt output
• Data FIFO
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 29-1:
A simplified block diagram of the CRC generator is
shown in Figure 29-1. A simple version of the CRC shift
engine is shown in Figure 29-2.
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
Variable FIFO
(4x32, 8x16 or 16x8)
2 * FP Shift Clock
FIFO Empty Event
CRCISEL
Shift Buffer
1
Set CRCIF
0
0
1
LENDIAN
CRC Shift Engine
CRCWDATH
2013-2014 Microchip Technology Inc.
Shift Complete Event
CRCWDATL
DS70000689D-page 405
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 29-2:
CRC SHIFT ENGINE DETAIL
CRCWDATH
CRCWDATL
Read/Write Bus
X(1)(1)
Shift Buffer
Data
Note 1:
2:
29.1
Bit 0
X(n)(1)
X(2)(1)
Bit 1
Bit n(2)
Bit 2
Each XOR stage of the shift engine is programmable. See text for details.
Polynomial Length n is determined by ([PLEN] + 1).
Overview
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN bits
(CRCCON2).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the
equation; functionally, this includes an XOR operation
on the corresponding bit in the CRC engine. Clearing
the bit disables the XOR.
For example, consider two CRC polynomials, one a
16-bit equation and the other a 32-bit equation:
Note that the appropriate positions are set to ‘1’ to
indicate that they are used in the equation (for example,
X26 and X23). The 0 bit required by the equation is
always XORed; thus, X0 is a don’t care. For a polynomial of length N, it is assumed that the Nth bit will
always be used, regardless of the bit setting. Therefore,
for a polynomial length of 32, there is no 32nd bit in the
CRCxOR register.
TABLE 29-1:
CRC SETUP EXAMPLES FOR
16 AND 32-BIT POLYNOMIAL
Bit Values
CRC Control
Bits
PLEN
16-Bit
Polynomial
32-Bit
Polynomial
01111
11111
and
X
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 +
x7 + x5 + x4 + x2 + x + 1
0000 0000
0000 000x
0000 0100
1100 0001
X
0001 0000
0010 000x
0001 1101
1011 011x
x16 + x12 + x5 + 1
To program these polynomials into the CRC generator,
set the register bits as shown in Table 29-1.
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dsPIC33EPXXXGM3XX/6XX/7XX
29.2
Programmable CRC Control
Registers
REGISTER 29-1:
CRCCON1: CRC CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R-0
R-0
R-0
R-0
R-0
CRCEN
—
CSIDL
VWORD4
VWORD3
VWORD2
VWORD1
VWORD0
bit 15
bit 8
R-0
R-1
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CRCFUL
CRCMPT
CRCISEL
CRCGO
LENDIAN
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CRCEN: CRC Enable bit
1 = CRC module is enabled
0 = CRC module is disabled; all state machines, pointers and CRCWDAT/CRCDAT are reset, other
SFRs are not reset
bit 14
Unimplemented: Read as ‘0’
bit 13
CSIDL: CRC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-8
VWORD: Valid Word Pointer Value bits
Indicates the number of valid words in the FIFO; has a maximum value of 8 when PLEN > 7 or
16 when PLEN 7
bit 7
CRCFUL: CRC FIFO Full bit
1 = FIFO is full
0 = FIFO is not full
bit 6
CRCMPT: CRC FIFO Empty Bit
1 = FIFO is empty
0 = FIFO is not empty
bit 5
CRCISEL: CRC Interrupt Selection bit
1 = Interrupt on FIFO empty; final word of data is still shifting through CRC
0 = Interrupt on shift complete and CRCWDAT results are ready
bit 4
CRCGO: CRC Start bit
1 = Start CRC serial shifter
0 = CRC serial shifter is turned off
bit 3
LENDIAN: Data Word Little-Endian Configuration bit
1 = Data word is shifted into the CRC starting with the LSb (little endian)
0 = Data word is shifted into the CRC starting with the MSb (big endian)
bit 2-0
Unimplemented: Read as ‘0’
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 29-2:
CRCCON2: CRC CONTROL REGISTER 2
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DWIDTH4
DWIDTH3
DWIDTH2
DWIDTH1
DWIDTH0
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
PLEN4
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
DWIDTH: Data Width Select bits
These bits set the width of the data word (DWIDTH + 1).
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
PLEN: Polynomial Length Select bits
These bits set the length of the polynomial (Polynomial Length = PLEN + 1).
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 29-3:
R/W-0
CRCXORH: CRC XOR POLYNOMIAL HIGH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
X: XOR of Polynomial Term Xn Enable bits
REGISTER 29-4:
R/W-0
CRCXORL: CRC XOR POLYNOMIAL LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
X
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1
X: XOR of Polynomial Term Xn Enable bits
bit 0
Unimplemented: Read as ‘0’
2013-2014 Microchip Technology Inc.
x = Bit is unknown
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NOTES:
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dsPIC33EPXXXGM3XX/6XX/7XX
30.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of
the dsPIC33EPXXXGM3XX/6XX/7XX family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
•
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection and CodeGuard™ Security
JTAG Boundary Scan Interface
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
30.1
Configuration Bits
In dsPIC33EPXXXGM3XX/6XX/7XX devices, the
Configuration bytes are implemented as volatile
memory. This means that configuration data must be
programmed each time the device is powered up.
Configuration data is stored at the top of the on-chip
program memory space, known as the Flash Configuration bytes. Their specific locations are shown in
Table 30-1. The configuration data is automatically
loaded from the Flash Configuration bytes to the proper
Configuration Shadow registers during device Resets.
Note:
Configuration data is reloaded on all types
of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration bytes for configuration data in their
code for the compiler. This is to make certain that program code is not stored in this address when the code
is compiled.
The upper 2 bytes of all Flash Configuration
Words in program memory should always be
‘1111 1111 1111 1111’. This makes them appear
to be NOP instructions in the remote event that their
locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding
locations, writing ‘1’s to these locations has no effect on
device operation.
Note:
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration bytes, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
The Configuration Flash bytes map is shown in
Table 30-1.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 30-1:
File Name
Reserved
Reserved
FICD
FPOR
FWDT
FOSC
FOSCSEL
FGS
Reserved
Reserved
Legend:
Note 1:
2:
Address
CONFIGURATION BYTE REGISTER MAP
Device
Memory Size Bits 23-8
(Kbytes)
0157EC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved(2)
—
JTAGEN
Reserved(1)
Reserved(2)
—
WDTWIN
ALTI2C2
ALTI2C1
BOREN
—
PLLKEN
WDTPRE
IOL1WAY
—
—
128
02AFEC
256
0557EC
512
0157EE
128
02AFEE
256
0557EE
512
0157F0
128
02AFF0
256
0557F0
512
0157F2
128
02AFF2
256
0557F2
512
0157F4
128
02AFF4
256
0557F4
512
0157F6
128
02AFF6
256
0557F6
512
0157F8
128
02AFF8
256
0557F8
512
0157FA
128
02AFFA
256
0557FA
512
0157FC
128
02AFFC
256
0557FC
512
0157FE
128
02AFFE
256
0557FE
512
—
—
—
FWDTEN
WINDIS
FCKSM
ICS
—
—
WDTPOST
OSCIOFNC
POSCMD
—
IESO
PWMLOCK
—
—
—
FNOSC
—
—
—
—
—
—
—
GCP
GWRP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— = unimplemented, read as ‘1’.
This bit is reserved and must be programmed as ‘0’.
This bit is reserved and must be programmed as ‘1’.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 30-2:
CONFIGURATION BITS DESCRIPTION
Bit Field
Description
GCP
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = Code protection is enabled for the entire program memory space
GWRP
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO
Two-Speed Oscillator Start-up Enable bit(1)
1 = Starts up device with FRC, then automatically switches to the user-selected oscillator
source when ready
0 = Starts up device with user-selected oscillator source
PWMLOCK
PWM Lock Enable bit
1 = Certain PWM registers may only be written after a key sequence
0 = PWM registers may be written without a key sequence
FNOSC
Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Reserved
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is the general purpose digital I/O pin
POSCMD
Primary Oscillator Mode Select bits
11 = Primary Oscillator mode is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
FWDTEN
Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled. Clearing the
SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by
clearing the SWDTEN bit in the RCON register.)
WINDIS
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
PLLKEN
PLL Lock Enable bit
1 = PLL lock is enabled
0 = PLL lock is disabled
Note 1:
The Two-Speed Start-up is not enabled when EC mode is used since the EC clocks will be ready immediately.
2013-2014 Microchip Technology Inc.
DS70000689D-page 413
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 30-2:
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
WDTPRE
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
WDTWIN
Watchdog Timer Window Select bits
11 = WDT Window is 25% of WDT Period
10 = WDT Window is 37.5% of WDT Period
01 = WDT Window is 50% of WDT Period
00 = WDT Window is 75% of WDT Period
ALTI2C1
Alternate I2C1 Pins bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2
Alternate I2C2 Pins bit
1 = I2C2 is mapped to the SDA2/SCL2 pins
0 = I2C2 is mapped to the ASDA2/ASCL2 pins
BOREN
Brown-out Reset (BOR) Detection Enable bit
1 = BOR is enabled
0 = BOR is disabled
JTAGEN
JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS
ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1
10 = Communicates on PGEC2 and PGED2
01 = Communicates on PGEC3 and PGED3
00 = Reserved, do not use
Note 1:
The Two-Speed Start-up is not enabled when EC mode is used since the EC clocks will be ready immediately.
DS70000689D-page 414
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dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 30-1:
R
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
DEVID(1)
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVID(1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID(1)
bit 7
bit 0
Legend: R = Read-Only bit
bit 23-0
Note 1:
DEVID: Device Identifier bits(1)
Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for the list of device ID values.
REGISTER 30-2:
R
U = Unimplemented bit
DEVREV: DEVICE REVISION REGISTER
R
R
R
R
R
R
R
DEVREV(1)
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVREV(1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVREV(1)
bit 7
bit 0
Legend: R = Read-only bit
bit 23-0
Note 1:
U = Unimplemented bit
DEVREV: Device Revision bits(1)
Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for the list of device revision values.
2013-2014 Microchip Technology Inc.
DS70000689D-page 415
dsPIC33EPXXXGM3XX/6XX/7XX
30.2
FIGURE 30-1:
User ID Words
dsPIC33EPXXXGM3XX/6XX/7XX devices contain four
User ID Words, located at addresses, 0x800FF8
through 0x800FFE. The User ID Words can be used for
storing product information, such as serial numbers,
system manufacturing dates, manufacturing lot
numbers and other application-specific information.
3.3V
dsPIC33EP
VDD
The User ID Words register map is shown in
Table 30-3.
VCAP
CEFC
TABLE 30-3:
File Name
USER ID WORDS REGISTER
MAP
Address
Bits
Bits
FUID0
0x800FF8
—
UID0
FUID1
0x800FFA
—
UID1
FUID2
0x800FFC
—
UID2
FUID3
0x800FFE
—
UID3
Legend: — = unimplemented, read as ‘1’.
30.3
On-Chip Voltage Regulator
All of the dsPIC33EPXXXGM3XX/6XX/7XX devices
power their core digital logic at a nominal 1.8V. This can
create a conflict for designs that are required to operate at
a higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33EPXXXGM3XX/6XX/
7XX family incorporate an on-chip regulator that allows
the device to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the VCAP
pin (Figure 30-1). This helps to maintain the stability of
the regulator. The recommended value for the filter
capacitor is provided in Table 33-5, located in
Section 33.0 “Electrical Characteristics”.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
VSS
Note 1: These are typical operating voltages. Refer
to Table 33-5 located in Section 33.1 “DC
Characteristics” for the full operating
ranges of VDD and VCAP.
2: It is important for the low-ESR capacitor to be
placed as close as possible to the VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.
30.4
Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the regulated supply voltage, VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC and
POSCMD).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON) is ‘1’.
Concurrently, the Power-up Timer (PWRT) Time-out
(TPWRT) is applied before the internal Reset is released.
If TPWRT = 0 and a crystal oscillator is being used, then a
nominal delay of TFSCM is applied. The total delay in this
case is TFSCM. Refer to Parameter SY35 in Table 33-21
of Section 33.0 “Electrical Characteristics” for specific
TFSCM values.
The BOR Status bit (RCON) is set to indicate that a
BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle mode and resets the device
should VDD fall below the BOR threshold voltage.
DS70000689D-page 416
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
30.5
30.5.2
Watchdog Timer (WDT)
For dsPIC33EPXXXGM3XX/6XX/7XX devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
30.5.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The
prescaler is set by the WDTPRE Configuration bit. With a
32 kHz input, the prescaler yields a WDT time-out period
(TWDT), as shown in Parameter SY12 in Table 33-21.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST
Configuration bits (FWDT), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 30-2:
SLEEP AND IDLE MODES
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes the device and code execution continues from
where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bit (RCON) needs to be
cleared in software after the device wakes up.
30.5.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software
when the FWDTEN Configuration bit has been
programmed to ‘0’. The WDT is enabled in software
by setting the SWDTEN control bit (RCON). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user application
to enable the WDT for critical code segments and
disable the WDT during non-critical segments for
maximum power savings.
The WDT flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
30.5.4
WDT WINDOW
The Watchdog Timer has an optional Windowed mode
enabled by programming the WINDIS bit in the WDT
Configuration register (FWDT). In the Windowed
mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Window select bits (WDTWIN).
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
WDTPOST
WDTPRE
SWDTEN
FWDTEN
WDT
Wake-up
RS
Prescaler
(Divide-by-N1)
LPRC Clock
Sleep/Idle
1
RS
Postscaler
(Divide-by-N2)
0
WINDIS
WDT
Reset
WDT Window Select
WDTWIN
CLRWDT Instruction
2013-2014 Microchip Technology Inc.
DS70000689D-page 417
dsPIC33EPXXXGM3XX/6XX/7XX
30.6
JTAG Interface
dsPIC33EPXXXGM3XX/6XX/7XX devices implement
a JTAG interface, which supports boundary scan
device testing. Detailed information on this interface is
provided in future revisions of the document.
Note:
30.7
Refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Programming and
Diagnostics” (DS70608) for further
information on usage, configuration and
operation of the JTAG interface.
In-Circuit Serial Programming
The dsPIC33EPXXXGM3XX/6XX/7XX devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data, and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the device just before shipping the
product. Serial programming also allows the most recent
firmware or a custom firmware to be programmed. Refer
to the “dsPIC33E/PIC24E Flash Programming
Specification for Devices with Volatile Configuration
Bits” (DS70663) for details about In-Circuit Serial
Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS70000689D-page 418
30.8
In-Circuit Debugger
When MPLAB® ICD 3 or the REAL ICE™ in-circuit emulator is selected as a debugger, the in-circuit debugging
functionality is enabled. This function allows simple
debugging functions when used with MPLAB X IDE.
Debugging functionality is controlled through the PGECx
(Emulation/Debug Clock) and PGEDx (Emulation/Debug
Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).
30.9
Code Protection and
CodeGuard™ Security
The dsPIC33EPXXXGM3XX/6XX/7XX devices offer
basic implementation of CodeGuard Security that
supports only General Segment (GS) security. This
feature helps protect individual Intellectual Property.
Note:
Refer to the “dsPIC33/PIC24 Family
Reference Manual”, “CodeGuard™
Security”
(DS70634)
for
further
information on usage, configuration and
operation of CodeGuard Security.
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
31.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes the features of
the dsPIC33EPXXXGM3XX/6XX/7XX family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
The dsPIC33EP instruction set is almost identical to
that of the dsPIC30F and dsPIC33F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
•
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 31-1 lists the general symbols used in describing
the instructions.
The dsPIC33E instruction set summary in Table 31-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
2013-2014 Microchip Technology Inc.
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
DS70000689D-page 419
dsPIC33EPXXXGM3XX/6XX/7XX
Most instructions are a single word. Certain double-word
instructions are designed to provide all the required
information in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it executes as a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the
instruction, or a PSV or Table Read is performed. In
these cases, the execution takes multiple instruction
TABLE 31-1:
cycles with the additional instruction cycle(s) executed
as a NOP. Certain instructions that involve skipping over
the subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or twoword instruction. Moreover, double-word moves require
two cycles.
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{}
Optional field or operation
a {b, c, d}
a is selected from the set of values b, c, d
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator write back destination address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0...W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (direct addressing)
DS70000689D-page 420
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0...W15}
Wnd
One of 16 Destination Working registers {W0...W15}
Wns
One of 16 Source Working registers {W0...W15}
WREG
W0 (Working register used in File register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X Data Space Prefetch Address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy
Y Data Space Prefetch Address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
2013-2014 Microchip Technology Inc.
DS70000689D-page 421
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-2:
Base
Instr
#
Assembly
Mnemonic
1
ADD
2
3
4
ADDC
AND
ASR
INSTRUCTION SET OVERVIEW
Assembly Syntax
ADD
# of
# of
Status Flags
Words Cycles
Affected
Description
Acc
Add Accumulators
1
1
OA,OB,SA,
SB
ADD
f
f = f + WREG
1
1
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
OA,OB,SA,
SB
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C,DC,N,OV,Z
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
1
None
None
5
BCLR
BCLR
f,#bit4
Bit Clear f
1
BCLR
Ws,#bit4
Bit Clear Ws
1
1
6
BRA
BRA
C,Expr
Branch if Carry
1
1 (4)
None
BRA
GE,Expr
Branch if greater than or equal
1
1 (4)
None
BRA
GEU,Expr
Branch if unsigned greater than or equal
1
1 (4)
None
BRA
GT,Expr
Branch if greater than
1
1 (4)
None
BRA
GTU,Expr
Branch if unsigned greater than
1
1 (4)
None
BRA
LE,Expr
Branch if less than or equal
1
1 (4)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1
1 (4)
None
BRA
LT,Expr
Branch if less than
1
1 (4)
None
BRA
LTU,Expr
Branch if unsigned less than
1
1 (4)
None
BRA
N,Expr
Branch if Negative
1
1 (4)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (4)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (4)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (4)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (4)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1
1 (4)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1
1 (4)
None
BRA
OV,Expr
Branch if Overflow
1
1 (4)
None
BRA
SA,Expr
Branch if Accumulator A saturated
1
1 (4)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1
1 (4)
None
BRA
Expr
Branch Unconditionally
1
4
None
BRA
Z,Expr
Branch if Zero
1
1 (4)
None
BRA
Wn
Computed Branch
1
4
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
7
Note:
BSET
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70000689D-page 422
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-2:
Base
Instr
#
Assembly
Mnemonic
8
BSW
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles
Affected
BSW.C
Ws,Wb
Write C bit to Ws
1
1
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
None
f,#bit4
Bit Toggle f
1
1
None
9
BTG
BTG
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
10
BTSC
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
11
12
13
14
15
BTSS
BTST
BTSTS
CALL
CLR
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
lit23
Call subroutine
2
4
SFA
CALL
Wn
Call indirect subroutine
1
4
SFA
CALL.L
Wn
Call indirect subroutine (long address)
1
4
SFA
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA,OB,SA,
SB
16
CLRWDT
CLRWDT
Clear Watchdog Timer
1
1
WDTO,Sleep
17
COM
COM
f
f=f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
CP
Wb,#lit8
Compare Wb with lit8
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C,DC,N,OV,Z
CP0
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit8
Compare Wb with lit8, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C,DC,N,OV,Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, skip if =
1
1
(2 or 3)
None
CPBEQ
CPBEQ
Wb,Wn,Expr
Compare Wb with Wn, branch if =
1
1 (5)
None
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, skip if >
1
1
(2 or 3)
None
CPBGT
CPBGT
Wb,Wn,Expr
Compare Wb with Wn, branch if >
1
1 (5)
None
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, skip if <
1
1
(2 or 3)
None
CPBLT
CPBLT
Wb,Wn,Expr
Compare Wb with Wn, branch if <
1
1 (5)
None
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, skip if
1
1
(2 or 3)
None
CPBNE
CPBNE
Wb,Wn,Expr
Compare Wb with Wn, branch if
1
1 (5)
None
18
19
20
21
22
23
24
Note:
CP
CP0
CPB
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2014 Microchip Technology Inc.
DS70000689D-page 423
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-2:
INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
25
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
26
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
27
DEC2
Assembly Syntax
# of
# of
Status Flags
Words Cycles
Affected
Description
DEC2
Ws,Wd
Wd = Ws – 2
1
1
28
DISI
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
29
DIV
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
30
DIVF
DIVF
Wm,Wn
Signed 16/16-bit Fractional Divide
1
18
N,Z,C,OV
31
DO
DO
#lit15,Expr
Do code to PC + Expr, lit15 + 1 times
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
2
2
None
32
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
33
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
35
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
36
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
37
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
38
GOTO
GOTO
Expr
Go to address
2
4
None
GOTO
Wn
Go to indirect
1
4
None
39
40
41
INC
INC2
IOR
GOTO.L
Wn
Go to indirect (long address)
1
4
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
OA,OB,OAB,
SA,SB,SAB
42
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
43
LNK
LNK
#lit14
Link Frame Pointer
1
1
SFA
44
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
45
Note:
MAC
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70000689D-page 424
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-2:
Base
Instr
#
Assembly
Mnemonic
46
MOV
47
MOVPAG
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles
Affected
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
None
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
MOVPAG
#lit10,DSRPAG
Move 10-bit literal to DSRPAG
1
1
None
MOVPAG
#lit9,DSWPAG
Move 9-bit literal to DSWPAG
1
1
None
MOVPAG
#lit8,TBLPAG
Move 8-bit literal to TBLPAG
1
1
None
MOVPAGW
Ws, DSRPAG
Move Ws to DSRPAG
1
1
None
MOVPAGW
Ws, DSWPAG
Move Ws to DSWPAG
1
1
None
MOVPAGW
Ws, TBLPAG
Move Ws to TBLPAG
1
1
None
48
MOVSAC
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
Prefetch and store accumulator
1
1
None
49
MPY
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
50
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
51
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
52
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
signed(Ws)
1
1
None
MUL.SS
Wb,Ws,Acc
Accumulator = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,Ws,Acc
Accumulator = signed(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Acc
Accumulator = signed(Wb) * unsigned(lit5)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
signed(Ws)
1
1
None
MUL.US
Wb,Ws,Acc
Accumulator = unsigned(Wb) *
signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.UU
Wb,#lit5,Acc
Accumulator = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,Ws,Acc
Accumulator = unsigned(Wb) *
unsigned(Ws)
1
1
None
MULW.SS
Wb,Ws,Wnd
Wnd = signed(Wb) * signed(Ws)
1
1
None
MULW.SU
Wb,Ws,Wnd
Wnd = signed(Wb) * unsigned(Ws)
1
1
None
MULW.US
Wb,Ws,Wnd
Wnd = unsigned(Wb) * signed(Ws)
1
1
None
MULW.UU
Wb,Ws,Wnd
Wnd = unsigned(Wb) * unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(lit5)
1
1
None
Note:
MUL.SU
Wb,#lit5,Wnd
Wnd = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
Wnd = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2014 Microchip Technology Inc.
DS70000689D-page 425
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-2:
Base
Instr
#
Assembly
Mnemonic
53
NEG
54
55
NOP
POP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
NEG
Acc
PUSH
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
POP
Pop Shadow Registers
1
1
All
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
1
2
None
POP.S
56
# of
# of
Status Flags
Words Cycles
Affected
Description
PUSH
PUSH.S
Push Shadow Registers
1
1
None
Go into Sleep or Idle mode
1
1
WDTO,Sleep
57
PWRSAV
PWRSAV
58
RCALL
RCALL
Expr
Relative Call
1
4
SFA
RCALL
Wn
Computed Call
1
4
SFA
REPEAT
#lit15
Repeat Next Instruction lit15 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
Software device Reset
1
1
None
59
REPEAT
#lit1
60
RESET
RESET
61
RETFIE
RETFIE
62
RETLW
RETLW
63
RETURN
RETURN
64
RLC
RLC
f
RLC
RLC
65
66
67
RLNC
RRC
RRNC
68
SAC
69
SE
70
SETM
71
Note:
SFTAC
Return from interrupt
1
6 (5)
SFA
Return with literal in Wn
1
6 (5)
SFA
Return from Subroutine
1
6 (5)
SFA
f = Rotate Left through Carry f
1
1
C,N,Z
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
#lit10,Wn
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
SE
Ws,Wnd
Wnd = sign-extended Ws
1
1
C,N,Z
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70000689D-page 426
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 31-2:
Base
Instr
#
Assembly
Mnemonic
72
SL
73
74
75
76
77
SUB
SUBB
SUBR
SUBBR
SWAP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
Description
# of
# of
Status Flags
Words Cycles
Affected
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
SUBB
f
f = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C,DC,N,OV,Z
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
1
1
None
SWAP
Wn
Wn = byte swap Wn
1
1
None
1
5
None
78
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
79
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
5
None
80
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
81
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
82
ULNK
ULNK
Unlink Frame Pointer
1
1
SFA
83
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
1
1
C,Z,N
84
Note:
ZE
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2014 Microchip Technology Inc.
DS70000689D-page 427
dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 428
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
32.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
32.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2013-2014 Microchip Technology Inc.
DS70000689D-page 429
dsPIC33EPXXXGM3XX/6XX/7XX
32.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler
to produce its object file. Notable features of the
assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
32.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
32.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
32.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS70000689D-page 430
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
32.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
32.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2013-2014 Microchip Technology Inc.
32.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
32.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
32.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS70000689D-page 431
dsPIC33EPXXXGM3XX/6XX/7XX
32.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
32.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70000689D-page 432
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
33.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33EPXXXGM3XX/6XX/7XX electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EPXXXGM3XX/6XX/7XX family are listed below. Exposure to these
maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these
or any other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings
(See Note 1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +160°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) ................................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3) ................................................... -0.3V to +3.6V
Voltage on VCAP with respect to VSS ........................................................................................................ 1.62V to 1.98V
Maximum current out of VSS pin ...........................................................................................................................350 mA
Maximum current into VDD pin(2) ...........................................................................................................................350 mA
Maximum current sunk by any I/O pin.....................................................................................................................20 mA
Maximum current sourced by I/O pin ......................................................................................................................18 mA
Maximum current sourced/sunk by all ports(2,4) ....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 33-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
4: Exceptions are: RA3, RA4, RA7, RA9, RA10, RB7-RB15, RC3, RC15, RD1-RD4, which are able to sink
30 mA and source 20 mA.
2013-2014 Microchip Technology Inc.
DS70000689D-page 433
dsPIC33EPXXXGM3XX/6XX/7XX
33.1
DC Characteristics
TABLE 33-1:
OPERATING MIPS vs. VOLTAGE
VDD Range
(in Volts)
Characteristic
Maximum MIPS
Temperature Range
(in °C)
dsPIC33EPXXXGM3XX/6XX/7XX
(1)
I-Temp
3.0V to 3.6V
-40°C to +85°C
70
E-Temp
3.0V to 3.6V(1)
-40°C to +125°C
60
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized. Refer to Parameter BO10 in Table 33-12 for the minimum and maximum BOR values.
TABLE 33-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typ.
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices:
Extended Temperature Devices:
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 33-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ.
Max.
Unit
Notes
Package Thermal Resistance, 121-Pin BGA
JA
40
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP 12x12 mm
JA
43
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP 14x14 mm
JA
—
°C/W
1
Package Thermal Resistance, 64-Pin QFN
JA
28.0
—
°C/W
1
Package Thermal Resistance, 64-Pin TQFP 10x10 mm
JA
48.3
—
°C/W
1
Package Thermal Resistance, 44-Pin QFN
JA
29.0
—
°C/W
1
Package Thermal Resistance, 44-Pin TQFP 10x10 mm
JA
49.8
—
°C/W
1
Package Thermal Resistance, 44-Pin VTLA 6x6 mm
JA
25.2
—
°C/W
1
Package Thermal Resistance, 36-Pin VTLA 5x5 mm
JA
28.5
—
°C/W
1
Package Thermal Resistance, 28-Pin QFN-S
JA
30.0
—
°C/W
1
Package Thermal Resistance, 28-Pin SSOP
JA
71.0
—
°C/W
1
Package Thermal Resistance, 28-Pin SOIC
JA
69.7
—
°C/W
1
Package Thermal Resistance, 28-Pin SPDIP
JA
60.0
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS70000689D-page 434
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions (see Note 3): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.(1)
Max.
Units
3.0
—
3.6
V
Conditions
Operating Voltage
DC10
VDD
Supply Voltage(3)
(2)
DC12
VDR
RAM Data Retention Voltage
1.95
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.03
—
—
DC18
VCORE
VDD Core(3)
Internal Regulator Voltage
1.62
1.8
1.98
Note 1:
2:
3:
V/ms 0V-3.0V in 3 ms
V
Voltage is dependent on
load, temperature and
VDD
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
This is the limit to which VDD may be lowered without losing RAM data.
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized. Refer to Parameter BO10 in Table 33-12 for the minimum and maximum BOR values.
TABLE 33-5:
FILTER CAPACITOR (CEFC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
CEFC
Note 1:
Characteristics
External Filter Capacitor
Value(1)
Min.
Typ.
Max.
Units
Comments
4.7
10
—
F
Capacitor must have a low
series resistance (< 1 Ohm)
Typical VCAP voltage = 1.8 volts when VDD VDDMIN.
2013-2014 Microchip Technology Inc.
DS70000689D-page 435
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param.
Typ.(2)
Operating Current (IDD)
Max.
Units
Conditions
(1)
DC20d
6.0
18.0
mA
-40°C
DC20a
6.0
18.0
mA
+25°C
DC20b
6.0
18.0
mA
+85°C
DC20c
6.0
18.0
mA
+125°C
DC21d
11.0
20.0
mA
-40°C
DC21a
11.0
20.0
mA
+25°C
DC21b
11.0
20.0
mA
+85°C
DC21c
11.0
20.0
mA
+125°C
DC22d
17.0
30.0
mA
-40°C
DC22a
17.0
30.0
mA
+25°C
DC22b
17.0
30.0
mA
+85°C
DC22c
17.0
30.0
mA
+125°C
DC23d
25.0
50.0
mA
-40°C
DC23a
25.0
50.0
mA
+25°C
DC23b
25.0
50.0
mA
+85°C
DC23c
25.0
50.0
mA
+125°C
DC24d
30.0
60.0
mA
-40°C
DC24a
30.0
60.0
mA
+25°C
DC24b
30.0
60.0
mA
+85°C
Note 1:
2:
3.3V
10 MIPS
3.3V
20 MIPS
3.3V
40 MIPS
3.3V
60 MIPS
3.3V
70 MIPS
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• CPU executing
while(1)
{
NOP();
}
• JTAG is disabled
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS70000689D-page 436
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typ.(2)
Max.
Units
Conditions
Idle Current (IIDLE)(1)
DC40d
1.5
8.0
mA
-40°C
DC40a
1.5
8.0
mA
+25°C
DC40b
1.5
8.0
mA
+85°C
DC40c
1.5
8.0
mA
+125°C
DC41d
2.0
12.0
mA
-40°C
DC41a
2.0
12.0
mA
+25°C
DC41b
2.0
12.0
mA
+85°C
DC41c
2.0
12.0
mA
+125°C
DC42d
5.5
15.0
mA
-40°C
DC42a
5.5
15.0
mA
+25°C
DC42b
5.5
15.0
mA
+85°C
DC42c
5.5
15.0
mA
+125°C
DC43d
9.0
20.0
mA
-40°C
DC43a
9.0
20.0
mA
+25°C
DC43b
9.0
20.0
mA
+85°C
DC43c
9.0
20.0
mA
+125°C
DC44d
10.0
25.0
mA
-40°C
DC44a
10.0
25.0
mA
+25°C
DC44b
10.0
25.0
mA
+85°C
Note 1:
2:
3.3V
10 MIPS
3.3V
20 MIPS
3.3V
40 MIPS
3.3V
60 MIPS
3.3V
70 MIPS
Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• The NVMSIDL bit (NVMCON) = 1 (i.e., Flash regulator is set to standby while the device is in
Idle mode)
• The VREGSF bit (RCON) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep
mode)
• JTAG is disabled
Data in the “Typical” column is at 3.3V, +25°C unless otherwise specified.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typ.(2)
Max.
Units
100
A
Conditions
Power-Down Current (IPD) (1)
DC60d
35
-40°C
DC60c
40
200
A
+25°C
DC60b
250
500
A
+85°C
DC60c
1000
2500
A
+125°C
DC61d
8
10
A
-40°C
DC61c
10
15
A
+25°C
DC61b
12
20
A
+85°C
13
25
A
+125°C
DC61c
Note 1:
2:
3:
3.3V
Base Power-Down Current
3.3V
Watchdog Timer Current: IWDT(3)
IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all ones)
• The VREGS bit (RCON) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode)
• The VREGSF bit (RCON) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode)
• JTAG is disabled
Data in the “Typical” column is at 3.3V, +25ºC unless otherwise specified.
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-9:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Doze
Ratio
Typ.(2)
Max.
DC73a
20
53
1:2
mA
DC73g
8
30
1:128
mA
DC70a
19
53
1:2
mA
DC70g
8
30
1:128
mA
DC71a
20
53
1:2
mA
DC71g
10
30
1:128
mA
DC72a
25
42
1:2
mA
DC72g
12
30
1:128
mA
Parameter No.
Units
Conditions
Doze Current (IDOZE)(1)
Note 1:
2:
-40°C
3.3V
70 MIPS
+25°C
3.3V
60 MIPS
+85°C
3.3V
60 MIPS
+125°C
3.3V
50 MIPS
IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• CPU executing
while(1)
{
NOP();
}
• JTAG is disabled
Data in the “Typical” column is at 3.3V, +25°C unless otherwise specified.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Input Low Voltage
DI10
Any I/O Pin and MCLR
VSS
—
0.2 VDD
V
DI18
I/O Pins with SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
I/O Pins with SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
DI19
VIH
DI20
Input High Voltage
I/O Pins Not 5V Tolerant
0.8 VDD
—
VDD
V
(Note 3)
I/O Pins 5V Tolerant and
MCLR
0.8 VDD
—
5.5
V
(Note 3)
I/O Pins with SDAx, SCLx
0.8 VDD
—
5.5
V
SMBus disabled
I/O Pins with SDAx, SCLx
2.1
—
5.5
V
SMBus enabled
150
250
550
A
VDD = 3.3V, VPIN = VSS
20
50
100
A
VDD = 3.3V, VPIN = VDD
ICNPU
Change Notification
Pull-up Current
ICNPD
Change Notification
Pull-Down Current(4)
DI30
DI31
Note 1:
2:
3:
4:
5:
6:
7:
8:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70000689D-page 440
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
Symbol
No.
IIL
Characteristic
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Input Leakage Current(1,2)
DI50
I/O Pins 5V Tolerant(3)
-1
—
+1
A
VSS VPIN 5V,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(3)
-1
—
+1
A
VSS VPIN VDD,
Pin at high-impedance,
-40°C TA +85°C
DI51a
I/O Pins Not 5V Tolerant(3)
-1
—
+1
A
Analog pins shared with
external reference pins,
-40°C TA +85°C
DI51b
I/O Pins Not 5V Tolerant(3)
-1
—
+1
A
VSS VPIN VDD,
Pin at high-impedance,
-40°C TA +125°C
DI51c
I/O Pins Not 5V Tolerant(3)
-1
—
+1
A
Analog pins shared with
external reference pins,
-40°C TA +125°C
DI55
MCLR
-5
—
+5
A
VSS VPIN VDD
DI56
OSC1
-5
—
+5
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
5:
6:
7:
8:
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2013-2014 Microchip Technology Inc.
DS70000689D-page 441
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
DI60c
2:
3:
4:
5:
6:
7:
8:
Max.
Units
Conditions
0
—
-5(4,7)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
0
—
+5(5,6,7)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(6)
-20(8)
—
+20(8)
mA
Absolute instantaneous sum
of all ± input injection
currents from all I/O pins:
( | IICL | + | IICH | ) IICT
Total Input Injection Current
(sum of all I/O and control
pins)
Note 1:
Typ.
Input High Injection Current
DI60b
IICT
Min.
Input Low Injection Current
DI60a
IICH
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70000689D-page 442
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
DO10
DO20
VOL
VOH
DO20A VOH1
Characteristic
Min.
Typ.
Max.
Units
Conditions
Output Low Voltage
4x Sink Driver Pins(1)
—
—
0.4
V
VDD = 3.3V,
IOL 6 mA, -40°C TA +85°C,
IOL 5 mA, +85°C TA +125°C
Output Low Voltage
8x Sink Driver Pins(2)
—
—
0.4
V
VDD = 3.3V,
IOL 12 mA, -40°C TA +85°C,
IOL 8 mA, +85°C TA +125°C
Output High Voltage
4x Source Driver Pins(1)
2.4
—
—
V
IOH -10 mA, VDD = 3.3V
Output High Voltage
8x Source Driver Pins(2)
2.4
—
—
V
IOH -15 mA, VDD = 3.3V
Output High Voltage
4x Source Driver Pins(1)
1.5
—
—
V
IOH -14 mA, VDD = 3.3V
2.0
—
—
IOH -12 mA, VDD = 3.3V
3.0
—
—
IOH -7 mA, VDD = 3.3V
1.5
—
—
2.0
—
—
IOH -18 mA, VDD = 3.3V
3.0
—
—
IOH -10 mA, VDD = 3.3V
Output High Voltage
8x Source Driver Pins(2)
Note 1:
2:
IOH -22 mA, VDD = 3.3V
V
Includes all I/O pins that are not 8x Sink Driver pins (see below).
Includes the following pins:
For 44-pin devices: RA3, RA4, RA7, RA9, RA10, RB7, RB, RC1 and RC
For 64-pin devices: RA4, RA7, RA, RB7, RB, RC1, RC, RC15 and RG
For 100-pin devices: RA4, RA7, RA9, RA10, RB7, RB, RC1, RC, RC15, RD and RG
TABLE 33-12: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.(1)
Typ.
Max.
Units
Conditions
BO10
VBOR
BOR Event on VDD Transition
High-to-Low
2.7
—
2.95
V
VDD
(Note 2, Note 3)
PO10
VPOR
POR Event on VDD Transition
High-to-Low
1.75
—
1.95
V
(Note 2)
Note 1:
2:
3:
Parameters are for design guidance only and are not tested in manufacturing.
The VBOR specification is relative to VDD.
The device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized.
2013-2014 Microchip Technology Inc.
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TABLE 33-13: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: VBOR (min)V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
D131
VPR
VDD for Read
D132b
VPEW
D134
TRETD
D135
10,000
—
—
VBORMIN
—
3.6
VDD for Self-Timed Write
3.0
—
3.6
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated, -40C to +125C
IDDP
Supply Current During
Programming
—
10
—
mA
D138a
TWW
Word Write Cycle Time
46.5
46.9
47.4
µs
TWW = 346 FRC cycles,
TA = +85°C (Note 2)
D138b
TWW
Word Write Cycle Time
46.0
—
47.9
µs
TWW = 346 FRC cycles,
TA = +125°C (Note 2)
D136a
TPE
Row Write Time
0.667
0.673
0.680
ms
TRW = 4965 FRC cycles,
TA = +85°C (Note 2)
D136b
TPE
Row Write Time
0.660
—
0.687
ms
TRW = 4965 FRC cycles,
TA = +125°C (Note 2)
D137a
TPE
Page Erase Time
19.6
20
20.1
ms
TPE = 146893 FRC cycles,
TA = +85°C (Note 2)
D137b
TPE
Page Erase Time
19.5
—
20.3
ms
TPE = 146893 FRC cycles,
TA = +125°C (Note 2)
Note 1:
2:
E/W -40C to +125C
V
V
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Other conditions: FRC = 7.3728 MHz, TUN = b'011111 (for Min), TUN = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 33-19) and the value of the FRC Oscillator
Tuning register.
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dsPIC33EPXXXGM3XX/6XX/7XX
33.2
AC Characteristics and Timing
Parameters
This section defines the dsPIC33EPXXXGM3XX/6XX/
7XX AC characteristics and timing parameters.
TABLE 33-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 33.1 “DC
Characteristics”.
AC CHARACTERISTICS
FIGURE 33-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 33-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
15
pF
In XT and HS modes, when
external clock is used to drive
OSC1
DO50
COSCO
OSC2 Pin
—
—
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKO
OS41
OS40
TABLE 33-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
Min.
Typ.(1)
Max.
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
60
MHz
EC
Oscillator Crystal Frequency
3.5
10
32.4
—
—
32.768
10
25
33.1
MHz
MHz
kHz
XT
HS
SOSC
8.33
—
DC
ns
TA = +125ºC
Symb
FIN
Characteristic
Conditions
OS20
TOSC
TOSC = 1/FOSC
TOSC = 1/FOSC
7.14
—
DC
ns
TA = +85ºC
OS25
TCY
Instruction Cycle Time(2)
16.67
—
DC
ns
TA = +125ºC
14.28
—
DC
ns
TA = +85ºC
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
—
0.625 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
5.2
—
ns
OS41
TckF
CLKO Fall Time(3)
—
5.2
—
ns
OS42
GM
External Oscillator
Transconductance(4)
—
12
—
mA/V
HS, VDD = 3.3V,
TA = +25ºC
—
6
—
mA/V
XT, VDD = 3.3V,
TA = +25ºC
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
This parameter is characterized, but not tested in manufacturing.
DS70000689D-page 446
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-17: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8.0
MHz
OS51
FSYS
On-Chip VCO System
Frequency
120
—
340
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
ms
-3
0.5
3
%
OS53
DCLK
Note 1:
2:
CLKO Stability (Jitter)
(2)
Conditions
ECPLL, XTPLL modes
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = ------------------------------------------------------------------------------------------F OSC
--------------------------------------------------------------------------------------Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows:
D CLK
D CLK
D CLK
Effective Jitter = -------------- = -------------- = -------------3.464
120
12
--------10
TABLE 33-18: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.3728 MHz(1)
F20a
FRC
-1.5
0.5
+1.5
%
-40°C TA +85°C
VDD = 3.0-3.6V
F20b
FRC
-2
1.5
+2
%
-40°C TA +125°C
VDD = 3.0-3.6V
Note 1:
Frequency calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 33-19: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz
F21a
LPRC
-15
5
+15
%
-40°C TA +85°C
VDD = 3.0-3.6V
F21b
LPRC
-30
10
+30
%
-40°C TA +125°C
VDD = 3.0-3.6V
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
—
5
10
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
5
10
ns
DI35
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TCY
Note 1:
Port Output Rise Time
Conditions
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
FIGURE 33-4:
BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
Various Delays (depending on configuration)
Reset Sequence
CPU Starts Fetching Code
DS70000689D-page 448
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-5:
POWER-ON RESET TIMING CHARACTERISTICS
Power-up Timer Disabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
Power-up Sequence
CPU Starts Fetching Code
SY00
(TPU)
(Notes 1,2)
Power-up Timer Disabled – Clock Sources = (HS, HSPLL, XT and XTPLL)
VDD
VPOR
Power-up Sequence
CPU Starts Fetching Code
SY00
(TPU)
(Notes 1,2)
SY10
(TOST)
Power-up Timer Enabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
Power-up Sequence
CPU Starts Fetching Code
SY00 SY11
(TPU) (TPWRT)
(Notes 1,2)
Power-up Timer Enabled – Clock Sources = (HS, HSPLL, XT and XTPLL)
VDD
VPOR
Power-up Sequence
CPU Starts Fetching Code
Greater of
SY00
(TPU) SY10 (TOST)
(Notes 1,2)
or
SY11 (TPWRT)
Note 1:
2:
The power-up period will be extended if the power-up sequence completes before the device exits from
BOR (VDD < VBOR).
The power-up period includes internal voltage regulator stabilization delay.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Min.
Typ.(2)
—
400
Characteristic(1)
Symbol
TPU
Power-up Period
SY10
TOST
Oscillator Start-up Time
SY12
TWDT
Watchdog Timer
Time-out Period
SY00
SY13
TIOZ
I/O High-Impedance
from MCLR Low or
Watchdog Timer Reset
Max. Units
600
µs
—
1024 TOSC
—
—
TOSC = OSC1 period
0.85
—
1.15
ms
WDTPRE = 0,
WDTPOST = 0000,
Using LPRC tolerances indicated
in F21 (see Table 33-19) at +85°C
3.4
—
4.6
ms
WDTPRE = 1,
WDTPOST = 0000,
Using LPRC tolerances indicated
in F21 (see Table 33-19) at +85°C
0.68
0.72
1.2
µs
SY20
TMCLR
MCLR Pulse Width (low)
2
—
—
µs
SY30
TBOR
BOR Pulse Width (low)
1
—
—
µs
SY35
TFSCM
Fail-Safe Clock Monitor
Delay
—
500
900
µs
SY36
TVREG
Voltage Regulator
Standby-to-Active Mode
Transition Time
—
—
30
µs
SY37
TOSCDFRC
FRC Oscillator Start-up
Delay
—
—
29
µs
SY38
TOSCDLPRC LPRC Oscillator Start-up
Delay
—
—
70
µs
Note 1:
2:
Conditions
-40°C to +85°C
These parameters are characterized but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
DS70000689D-page 450
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-6:
TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
Symbol
TTXH
Characteristic(2)
Min.
Typ.
Max.
Units
Conditions
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TA15,
N = Prescaler value
(1, 8, 64, 256)
Asynchronous
35
—
—
ns
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
T1CK High Synchronous
Time
mode
TA11
TTXL
T1CK Low
Time
10
—
—
ns
TA15
TTXP
T1CK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
OS60
Ft1
T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting TCS
(T1CON) bit)
DC
—
50
kHz
TA20
TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Asynchronous
Note 1:
2:
Must also meet
Parameter TA15,
N = Prescaler value
(1, 8, 64, 256)
N = Prescaler value
(1, 8, 64, 256)
Timer1 is a Type A.
These parameters are characterized, but are not tested in manufacturing.
2013-2014 Microchip Technology Inc.
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TABLE 33-23: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TB10
TTXH
TxCK High Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB11
TTXL
TxCK Low Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB15
TTXP
TxCK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = Prescale value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized, but are not tested in manufacturing.
TABLE 33-24: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min.
Typ.
Max.
Units
Conditions
TC10
TTXH
TxCK High Synchronous
Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TTXL
TxCK Low
Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TTXP
TxCK Input Synchronous,
Period
with Prescaler
2 TCY + 40
—
—
ns
N = Prescale value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
Synchronous
These parameters are characterized, but are not tested in manufacturing.
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FIGURE 33-7:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-25: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC11
TCCH
ICx Input High Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC15
TCCP
ICx Input Period
Greater of:
25 + 50 or
(1 TCY/N) + 50
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
2013-2014 Microchip Technology Inc.
N = Prescale value
(1, 4, 16)
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-8:
OUTPUT COMPARE x (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-26: OUTPUT COMPARE x (OCx) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 33-9:
OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 33-27: OCx/PWMx MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
—
—
TCY + 20
ns
TCY + 20
—
—
ns
OC15
TFD
Fault Input to PWMx
I/O Change
OC20
TFLT
Fault Input Pulse Width
Note 1:
These parameters are characterized but not tested in manufacturing.
DS70000689D-page 454
Conditions
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-10:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 33-11:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-28: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
—
ns
See Parameter DO32
See Parameter DO31
MP10
TFPWM
PWMx Output Fall Time
—
—
MP11
TRPWM
PWMx Output Rise Time
—
—
—
ns
MP20
TFD
Fault Input to PWMx
I/O Change
—
—
15
ns
MP30
TFH
Fault Input Pulse Width
15
—
—
ns
Note 1:
Conditions
These parameters are characterized but not tested in manufacturing.
2013-2014 Microchip Technology Inc.
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FIGURE 33-12:
TIMERQ (QEIx MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS
QEBx
TQ11
TQ10
TQ15
TQ20
POSCNT
TABLE 33-29: QEIx MODULE EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TQ10
TtQH
TQCK High Synchronous,
Time
with Prescaler
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
—
ns
Must also meet
Parameter TQ15
TQ11
TtQL
TQCK Low
Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
—
ns
Must also meet
Parameter TQ15
TQ15
TtQP
TQCP Input Synchronous,
Period
with Prescaler
Greater of:
25 + 50 or
(1 TCY/N) + 50
—
—
ns
TQ20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
—
1
TCY
—
Note 1:
Synchronous,
with Prescaler
These parameters are characterized but not tested in manufacturing.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-13:
QEAx/QEBx INPUT CHARACTERISTICS
TQ36
QEAx
(input)
TQ31
TQ30
TQ35
QEBx
(input)
TQ41
TQ40
TQ30
TQ31
TQ35
QEBx
Internal
TABLE 33-30: QUADRATURE DECODER TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Typ.(2)
Max.
Units
Conditions
TQ30
TQUL
Quadrature Input Low Time
6 TCY
—
ns
TQ31
TQUH
Quadrature Input High Time
6 TCY
—
ns
TQ35
TQUIN
Quadrature Input Period
12 TCY
—
ns
TQ36
TQUP
Quadrature Phase Period
3 TCY
—
ns
TQ40
TQUFL
Filter Time to Recognize Low
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
TQ41
TQUFH
Filter Time to Recognize High
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 3)
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
N = Index Channel Digital Filter Clock Divide Select bits. Refer to the “dsPIC33/PIC24 Family Reference
Manual”, “Quadrature Encoder Interface (QEI)” (DS70601). Please see the Microchip web site for the
latest “dsPIC33/PIC24 Family Reference Manual” sections.
3:
2013-2014 Microchip Technology Inc.
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FIGURE 33-14:
QEIx MODULE INDEX PULSE TIMING CHARACTERISTICS
QEAx
(input)
QEBx
(input)
Ungated
Index
TQ50
TQ51
Index Internal
TQ55
Position
Counter Reset
TABLE 33-31: QEIx INDEX PULSE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Max.
Units
Conditions
TQ50
TqIL
Filter Time to Recognize Low
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ51
TqiH
Filter Time to Recognize High
with Digital Filter
3 * N * TCY
—
ns
N = 1, 2, 4, 16, 32, 64,
128 and 256 (Note 2)
TQ55
Tqidxr
Index Pulse Recognized to Position
Counter Reset (ungated index)
3 TCY
—
ns
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Alignment of index pulses to QEAx and QEBx is shown for Position Counter Reset timing only. Shown for
forward direction only (QEAx leads QEBx). Same timing applies for reverse direction (QEAx lags QEBx)
but index pulse recognition occurs on falling edge.
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TABLE 33-32: SPI2 AND SPI3 MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 33-33
—
—
0,1
0,1
0,1
9 MHz
—
Table 33-34
—
1
0,1
1
9 MHz
—
Table 33-35
—
0
0,1
1
15 MHz
—
—
Table 33-36
1
0
0
11 MHz
—
—
Table 33-37
1
1
0
15 MHz
—
—
Table 33-38
0
1
0
11 MHz
—
—
Table 33-39
0
0
0
FIGURE 33-15:
SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 33-1 for load conditions.
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FIGURE 33-16:
SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SDOx
Bit 14 - - - - - -1
MSb
LSb
SP30, SP31
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-33: SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 33-17:
SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP40
SDIx
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-34: SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 33-18:
SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35 SP36
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SDIx
MSb In
LSb
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-35: SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
-40ºC to +125ºC
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 33-19:
SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SCKx
(CKP = 1)
SP36
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP72
MSb In
Bit 14 - - - -1
SP73
LSb
SP30, SP31
SDIx
SP72
SP51
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
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TABLE 33-36: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH
TscL2ssH
SSx after SCKx Edge
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70000689D-page 464
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-20:
SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SCKx
(CKP = 1)
SP72
SP36
SP35
SP72
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
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TABLE 33-37: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH
TscL2ssH
SSx after SCKx Edge
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70000689D-page 466
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-21:
SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35 SP36
SDOX
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-38: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH
TscL2ssH
SSx after SCKx Edge
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70000689D-page 468
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-22:
SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35 SP36
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-39: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH
TscL2ssH
SSx after SCKx Edge
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS70000689D-page 470
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-40: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
25 MHz
Table 33-41
—
—
0,1
0,1
0,1
25 MHz
—
Table 33-42
—
1
0,1
1
25 MHz
—
Table 33-43
—
0
0,1
1
25 MHz
—
—
Table 33-44
1
0
0
25 MHz
—
—
Table 33-45
1
1
0
25 MHz
—
—
Table 33-46
0
1
0
25 MHz
—
—
Table 33-47
0
0
0
FIGURE 33-23:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
MSb
SDO1
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-24:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDO1
LSb
SP30, SP31
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-41: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
25
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDO1 Data Output Setup to
First SCK1 Edge
20
—
—
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70000689D-page 472
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-25:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDO1
SP30, SP31
SP40
SDI1
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-42: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
25
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2sc,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data
Input to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPI1 pins.
2013-2014 Microchip Technology Inc.
DS70000689D-page 473
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-26:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35 SP36
MSb
SDO1
Bit 14 - - - - - -1
SP30, SP31
SD1
MSb In
LSb
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 33-1 for load conditions.
TABLE 33-43: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
25
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data
Input to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
Note 1:
2:
3:
4:
-40ºC to +125ºC
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPI1 pins.
DS70000689D-page 474
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-27:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SCK1
(CKP = 1)
SP72
SP36
SP35
SP72
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
DS70000689D-page 475
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-44: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH
TscL2ssH
SS1 after SCK1 Edge
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
SDO1 Data Output Valid after
SS1 Edge
—
—
50
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70000689D-page 476
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-28:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SCK1
(CKP = 1)
SP72
SP36
SP35
SP72
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
DS70000689D-page 477
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-45: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
—
—
50
ns
Note 1:
2:
3:
4:
SDO1 Data Output Valid after
SS1 Edge
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70000689D-page 478
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dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-29:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35 SP36
MSb
SDO1
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-46: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70000689D-page 480
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-30:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35 SP36
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-47: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter
DO32 (Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter
DO31 (Note 4)
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized, but are not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70000689D-page 482
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-31:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 33-1 for load conditions.
FIGURE 33-32:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM26
IM11
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 33-1 for load conditions.
2013-2014 Microchip Technology Inc.
DS70000689D-page 483
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-48: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note 1:
2:
3:
4:
Characteristic(4)
Min.(1)
Max.
Units
Conditions
—
s
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2)
400 kHz mode TCY/2 (BRG + 2)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
s
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2)
—
s
400 kHz mode TCY/2 (BRG + 2)
—
s
1 MHz mode(2) TCY/2 (BRG + 2)
—
s
TF:SCL
SDAx and SCLx 100 kHz mode
—
300
ns
CB is specified to be
Fall Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(2)
40
—
ns
1 MHz mode
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
0.2
—
s
1 MHz mode(2)
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Only relevant for
Setup Time
Repeated Start
400 kHz mode TCY/2 (BRG + 2)
—
s
condition
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
s
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
After this period, the
Hold Time
first clock pulse is
400 kHz mode
TCY/2 (BRG +2)
—
s
generated
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
s
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Setup Time
400 kHz mode TCY/2 (BRG + 2)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
s
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Hold Time
—
s
400 kHz mode TCY/2 (BRG + 2)
1 MHz mode(2) TCY/2 (BRG + 2)
—
s
TAA:SCL Output Valid
100 kHz mode
—
3500
ns
From Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
TBF:SDA Bus Free Time 100 kHz mode
4.7
—
s
Time the bus must be
free before a new
400 kHz mode
1.3
—
s
transmission can start
(2)
1 MHz mode
0.5
—
s
CB
Bus Capacitive Loading
—
400
pF
Pulse Gobbler Delay
65
390
ns
(Note 3)
TPGD
2
BRG is the value of the I C Baud Rate Generator. Refer to the “dsPIC33/PIC24 Family Reference
Manual”, “Inter-Integrated Circuit™ (I2C™)” (DS70000195). Please see the Microchip web site for the
latest “dsPIC33E/PIC24E Family Reference Manual” sections.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
These parameters are characterized, but not tested in manufacturing.
DS70000689D-page 484
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-33:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 33-34:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS25
IS31
IS26
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-49: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic(3)
IS10
TLO:SCL Clock Low Time
IS11
THI:SCL
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
IS51
Note
Clock High Time
Min.
Max.
Units
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
4.7
1.3
0.5
4.0
—
—
—
—
s
s
s
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.5
—
s
SDAx and SCLx 100 kHz mode
—
300
ns
TF:SCL
Fall Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
Rise Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(1)
1 MHz mode
100
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(1)
0
0.3
s
TSU:STA Start Condition
100 kHz mode
4.7
—
s
Setup Time
400 kHz mode
0.6
—
s
0.25
—
s
1 MHz mode(1)
THD:STA Start Condition
100 kHz mode
4.0
—
s
Hold Time
400 kHz mode
0.6
—
s
0.25
—
s
1 MHz mode(1)
TSU:STO Stop Condition
100 kHz mode
4.7
—
s
Setup Time
400 kHz mode
0.6
—
s
(1)
1 MHz mode
0.6
—
s
100 kHz mode
4
—
s
THD:STO Stop Condition
Hold Time
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
s
100 kHz mode
0
3500
ns
TAA:SCL Output Valid
From Clock
400 kHz mode
0
1000
ns
1 MHz mode(1)
0
350
ns
100 kHz mode
4.7
—
s
TBF:SDA Bus Free Time
400 kHz mode
1.3
—
s
0.5
—
s
1 MHz mode(1)
CB
Bus Capacitive Loading
—
400
pF
TPGD
Pulse Gobbler Delay
65
390
ns
1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: The Typical value for this parameter is 130 ns.
3: These parameters are characterized, but not tested in manufacturing.
DS70000689D-page 486
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
Time the bus must be free
before a new transmission
can start
(Note 2)
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-35:
CANx MODULE I/O TIMING CHARACTERISTICS
CxTX Pin
(output)
New Value
Old Value
CA10 CA11
CxRX Pin
(input)
CA20
TABLE 33-50: CANx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
CA10
Min.
Typ.(2)
Max.
Units
—
—
—
ns
See Parameter DO32
See Parameter DO31
TIOF
Port Output Fall Time
CA11
TIOR
Port Output Rise Time
—
—
—
ns
CA20
TCWF
Pulse Width to Trigger
CAN Wake-up Filter
120
—
—
ns
Note 1:
2:
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
FIGURE 33-36:
UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX
UXTX
MSb In
Bit 6-1
LSb In
UA10
TABLE 33-51: UARTx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +125°C
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
UA10
TUABAUD
UARTx Baud Time
UA11
FBAUD
UARTx Baud Frequency
UA20
TCWF
Start Bit Pulse Width to Trigger
UARTx Wake-up
Note 1:
2:
Min.
Typ.(2)
66.67
—
—
ns
—
—
15
Mbps
500
—
—
ns
Max.
Units
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2013-2014 Microchip Technology Inc.
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dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-52: OP AMP/COMPARATOR SPECIFICATIONS
Standard Operating Conditions (see Note 3): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Min.
Typ.(1)
Max.
Units
Conditions
Response Time
—
19
—
ns
V+ input step of 100 mV,
V- input held at VDD/2
Comparator Mode
Change to Output Valid
—
—
10
µs
Symbol
Characteristic
Comparator AC Characteristics
CM10 TRESP
CM11
TMC2OV
Comparator DC Characteristics
CM30 VOFFSET
Comparator Offset Voltage
—
±20
±75
mV
CM31 VHYST
Input Hysteresis Voltage
—
30
—
mV
CM32 TRISE/
TFALL
Comparator Output
Rise/Fall Time
—
20
—
ns
CM33 VGAIN
Open-Loop Voltage Gain
—
90
—
db
CM34 VICM
Input Common-Mode
Voltage
AVSS
—
AVDD
V
V/µs
1 pF load capacitance
on input
Op Amp AC Characteristics
CM20 SR
Slew Rate
—
9
—
CM21a PM
Phase Margin
—
68
—
CM22 GM
Gain Margin
—
20
—
db
CM23a GBW
Gain Bandwidth
—
10
—
MHz
AVSS
—
AVDD
V
10 pF load
Degree G = 100V/V; 10 pF load
G = 100V/V; 10 pF load
10 pF load
Op Amp DC Characteristics
CM40 VCMR
Common-Mode Input
Voltage Range
CM41 CMRR
Common-Mode
Rejection Ratio
—
40
—
db
CM42 VOFFSET
Op Amp Offset Voltage
—
±20
±70
mV
CM43 VGAIN
Open-Loop Voltage Gain
—
90
—
db
CM44 IOS
Input Offset Current
—
—
—
—
See pad leakage
currents in Table 33-10
CM45 IB
Input Bias Current
—
—
—
—
See pad leakage
currents in Table 33-10
CM46 IOUT
Output Current
—
—
420
µA
With minimum value of
RFEEDBACK (CM48)
8
—
—
k
(Note 2)
AVSS + 0.075
—
AVDD – 0.075
V
IOUT = 420 µA
CM48 RFEEDBACK Feedback Resistance
Value
CM49a VOUT
Note 1:
2:
3:
Output Voltage
VCM = AVDD/2
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Resistances can vary by ±10% between op amps.
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 33-12 for the minimum and
maximum BOR values.
DS70000689D-page 488
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-53: OP AMP/COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
Standard Operating Conditions (see Note 2): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
VR310
Note 1:
2:
Symbol
TSET
Characteristic
Min.
Typ.
Max.
Units
—
1
10
s
Settling Time
Conditions
(Note 1)
Settling time is measured while CVRR = 1 and the CVR bits transition from ‘0000’ to ‘1111’.
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 33-12 for the minimum and
maximum BOR values.
TABLE 33-54: OP AMP/COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (see Note 1): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristics
Min.
Typ.
Max.
Units
CVRSRC/24
—
CVRSRC/32
LSb
Conditions
VRD310 CVRES
Resolution
VRD311 CVRAA
Absolute Accuracy of
Internal DAC Input to
Comparators
—
—
±25
mV
AVDD = CVRSRC = 3.3V
VRD312 CVRAA1
Absolute Accuracy of
CVREFxO pins
—
—
+75/-25
mV
AVDD = CVRSRC = 3.3V
VRD313 CVRSRC
Input Reference Voltage
0
—
AVDD + 0.3
V
VRD314 CVROUT
Buffer Output Resistance
—
1.5k
—
VRD315 CVCL
Permissible Capacitive
Load (CVREFxO pins)
—
—
25
pF
VRD316 IOCVR
Permissible Current
Output (CVREFxO pins)
—
—
1
mA
VRD317 ION
Current Consumed
When Module is Enabled
—
—
500
µA
AVDD = 3.6V
VRD318 IOFF
Current Consumed
When Module is
Disabled
—
—
1
nA
AVDD = 3.6V
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 33-12 for the minimum and
maximum BOR values.
2013-2014 Microchip Technology Inc.
DS70000689D-page 489
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-55: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min.
Typ.
Max.
Units
nA
Conditions
CTMU Current Source
CTMUI1
IOUT1
Base Range
280
550
830
CTMUI2
IOUT2
10x Range
2.8
5.5
8.3
µA
CTMUICON = 10
CTMUI3
IOUT3
100x Range
28
55
83
µA
CTMUICON = 11
CTMUI4
IOUT4
1000x Range
CTMUICON = 00
280
550
830
µA
CTMUFV1 VF
—
0.77
—
V
CTMUFV2 VFVR
—
-1.38
—
mV/°C
Note 1:
CTMUICON = 01
Nominal value at center point of current trim range (CTMUICON = 000000).
FIGURE 33-37:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for All Pins Except OSC2
Load Condition 2 – for OSC2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
DS70000689D-page 490
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-56: ADCx MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions (see Note 1): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 3.0
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
AD05
VREFH
Reference Voltage High
Reference Inputs
AD05a
AD06
VREFL
Reference Voltage Low
AD06a
AVSS + 2.7
—
AVDD
V
(Note 1)
VREFH = VREF+,
VREFL = VREF-
3.0
—
3.6
V
VREFH = AVDD,
VREFL = AVSS = 0
AVSS
—
AVDD – 2.7
V
(Note 1)
0
—
0
V
VREFH = AVDD,
VREFL = AVSS = 0
AD07
VREF
Absolute Reference
Voltage
2.7
—
3.6
V
VREF = VREFH – VREFL
AD08
IREF
Current Drain
—
—
—
—
10
600
A
A
ADC off
ADC on
AD09
IAD
Operating Current
—
5
—
mA
—
2
—
mA
ADC operating in 10-bit mode
(Note 1)
ADC operating in 12-bit mode
(Note 1)
Analog Input
AD12
VINH
Input Voltage Range,
VINH
VINL
—
VREFH
V
This voltage reflects
Sample-and-Hold
Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13
VINL
Input Voltage Range,
VINL
VREFL
—
AVSS + 1V
V
This voltage reflects
Sample-and-Hold
Channels 0, 1, 2 and 3
(CH0-CH3), negative input
AD17
RIN
Recommended
Impedance of Analog
Voltage Source
—
—
200
Impedance to achieve
maximum performance of
ADC
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 33-12 for the minimum and
maximum BOR values.
2013-2014 Microchip Technology Inc.
DS70000689D-page 491
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 33-57: ADCx MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions (see Note 1): 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
ADC Accuracy (12-Bit Mode) – VREFAD20a
Nr
Resolution
12 data bits
bits
AD21a
INL
Integral Nonlinearity
-3
—
+3
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V (Note 2)
AD22a
DNL
Differential Nonlinearity
1
—
| 0 | can affect the ADC results by approximately 4-6 counts.
Input Signal Bandwidth
—
—
200
kHz
TABLE 34-15: ADCx MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
ADC Accuracy (10-Bit Mode)(1)
HAD20b
Nr
Resolution(3)
HAD21b
INL
Integral Nonlinearity
-1.5
—
1.5
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22b
DNL
Differential Nonlinearity
-0.25
—
0.25
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD23b
GERR
Gain Error
-2.5
—
2.5
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD24b
EOFF
Offset Error
-1.25
—
1.25
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
10 Data Bits
bits
Dynamic Performance (10-Bit Mode)(2)
HAD33b
FNYQ
Input Signal Bandwidth
Note 1:
2:
3:
These parameters are characterized, but are tested at 20 ksps only.
These parameters are characterized by similarity, but are not tested in manufacturing.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
2013-2014 Microchip Technology Inc.
—
—
400
kHz
DS70000689D-page 505
dsPIC33EPXXXGM3XX/6XX/7XX
NOTES:
DS70000689D-page 506
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
35.0
PACKAGING INFORMATION
35.1
Package Marking Information
44-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33EP
512GM604
-I/ML e3
1410017
44-Lead QFN (8x8x0.9 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Note:
Example
dsPIC33EP
512GM604
-I/MLe3
1410017
64-Lead QFN (9x9x0.9 mm)
Legend: XX...X
Y
YY
WW
NNN
e3
*
Example
Example
dsPIC33EP
512GM706-I/MRe3
1410017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2013-2014 Microchip Technology Inc.
DS70000689D-page 507
dsPIC33EPXXXGM3XX/6XX/7XX
35.1
Package Marking Information (Continued)
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
100-Lead TQFP (12x12x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
100-Lead TQFP (14x14x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
121-Lead TFBGA (10x10x1.1 mm)
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS70000689D-page 508
Example
dsPIC33EP
512GM706
-I/PT e3
1410017
Example
dsPIC33EP512
GM710-I/PT e3
1410017
Example
dsPIC33EP512
GM710-I/PF e3
1410017
Example
33EP512GM
710-I/BG e3
1410017
2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX
35.2
Package Details
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