dsPIC33EPXXGS202 FAMILY
dsPIC33EPXXGS202 Family
Silicon Errata and Data Sheet Clarification
The dsPIC33EPXXGS202 family devices that you
have received conform functionally to the current
Device Data Sheet (DS70005208C), except for the
anomalies described in this document.
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with a hardware debugger:
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
2.
3.
1.
4.
The errata described in this document will be addressed
in future revisions of dsPIC33EPXXGS202 family silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the issues
indicated in the last column of Table 2
apply to the current silicon revision (A3).
5.
Data Sheet clarifications and corrections start on
Page 15, following the discussion of silicon issues.
Note:
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window > Dashboard and click the Refresh Debug Tool
Status icon (
).
Depending on the development tool used, the
part number and Device Revision ID value
appear in the Output window.
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The DEVREV values for the various silicon revisions of
the dsPIC33EPXXGS202 family are shown in Table 1.
SILICON DEVREV VALUES
Part Number
Device ID(1)
Revision ID for Silicon Revision(2)
A3
dsPIC33EP16GS202
0x6D01
dsPIC33EP32GS202
0x6D11
Note 1:
2:
0x4003
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory
space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the “dsPIC33EPXXGS202 Family Flash Programming Specification” (DS70005192) for detailed information on
Device and Revision IDs for your specific device.
2015-2016 Microchip Technology Inc.
DS80000655C-page 1
dsPIC33EPXXGS202 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY
Feature
Item
Number
Affected
Revisions(1)
Issue Summary
A3
UART
Break Character
Transmission
1.
The Transmit Shift Register Empty (TRMT) bit is unreliable
when there are back-to-back Break character transmissions.
X
PWM
Latched Faults
2.
In PWM Latched Fault mode, the PWM outputs may be
latched on both the rising and the falling edge of the Fault
signal, regardless of the Fault input polarity selection (set
with the FLTPOL bit (FCLCONx) setting).
X
PWM
Immediate Update
3.
Dead time is not asserted when PDCx is updated which
causes an immediate transition on the PWMxH and
PWMxL outputs.
X
PWM
Master Time Base
Mode
4.
Changes to the PHASEx register may result in missing
dead time.
X
CPU
div.sd
5.
When using the div.sd instruction, the Overflow bit does
not always get set when an overflow occurs.
X
CPU
DO Loop
6.
PSV access, including Table Reads or Writes in the last
instruction of a DO loop, is not allowed.
X
PWM
Redundant/
Push-Pull
Output Mode
7.
Changing the duty cycle value from a non-zero value to
zero will produce a glitch pulse equal to 1 PWM clock.
X
PWM
Status Bits
8.
PWM Fault status bits do not function if the associated
PWM Fault interrupts are disabled.
X
PWM
Push-Pull Mode
9.
When EIPU = 1, Period register writes may produce
back-to-back pulses under certain conditions.
X
PWM
Trigger Compare
Match
10.
The first PWM/ADC trigger event on a TRIGx/STRIGx
match may not occur under certain conditions.
X
I2C
Slave Mode
11.
Bus data can get corrupted when it matches with one of the
slave addresses connected to the bus.
X
PWM
Push-Pull Mode
12.
When EIPU = 0, a period update may produce
back-to-back pulses.
X
Auxiliary
PLL
APLL Lock
13.
The APLL lock bit is asserted directly after enabling the
APLL.
X
ADC
ADC Conversion
14.
Under specific conditions, multi-core ADC conversion
cross-talk noise might be present.
X
I2C
Slave Mode
15.
In 10-Bit Addressing Slave mode, on receiving the upper
address byte (A9 and A8 bits), the Acknowledge Time
Status bit (ACKTIM) is not asserted during the
Acknowledgment sequence.
X
I2C
Slave Receive
Mode
16.
The Acknowledge Time Status bit (ACKTIM) is asserted
only if Address Hold Enable (AHEN) or Data Hold Enable
(DHEN) is enabled.
X
PWM
PWM Module
Enable
17.
A glitch may be observed on the PWM pins when the PWM
module is enabled after the assignment of pin ownership to
the PWM module.
X
PWM
Center-Aligned
Complementary
18.
Dead time between transitions of the PWMxH and PWMxL
outputs may not be asserted when SWAP mode is disabled.
X
19.
The Comparator module may generate erroneous triggers/
interrupts.
X
Comparator Comparator Output
Jitter
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
DS80000655C-page 2
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dsPIC33EPXXGS202 FAMILY
TABLE 2:
Module
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Item
Number
Affected
Revisions(1)
Issue Summary
A3
CPU
Variable Interrupt
Latency
20.
When Variable Interrupt Latency is selected (VAR = 1), an
address error trap or incorrect application behavior may
occur.
X
CPU
Context Switching
21.
When nesting more than one interrupt (without an Alternate
Working register set) within the interrupts which are using
Alternate Working register sets, there will be an unexpected
change in the CCTXI bits in the CTXTSTAT register
while returning from the highest priority interrupt.
X
I2C
Address Hold
22.
In Slave mode when AHEN = 1 (Address Hold Enable), if
the ACKDT bit (Acknowledge Data) is set at the beginning
of address reception, clock stretching will not happen after
the 8th clock.
X
I2C
Data Hold
23.
In Slave mode when DHEN = 1 (Data Hold Enable), if the
ACKDT bit (Acknowledge Data) is set at the beginning of
data reception, then the slave interrupt will not occur after
the 8th clock.
X
SPI
SPI Enable
24.
When SPI is enabled for the first time, there may be a
spurious clock on the SCK which causes a mismatch
between the clock and data lines.
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
2015-2016 Microchip Technology Inc.
DS80000655C-page 3
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Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
1. Module: UART
The Transmit Shift Register Empty (TRMT) bit is
unreliable when there are back-to-back Break
character transmissions.
For back-to-back Break characters, the TRMT
bit may not reflect the actual status. If user software is polling for this bit to be set, it may result
in dummy bytes getting transmitted instead of
Break characters.
Work around
Poll the UARTx Transmit Break bit, UTXBRK
(U1STA), to be cleared instead of the
TRMT bit (U1STA) to be set. The UTXBRK
status bit will be cleared after a Break character
transmission.
Affected Silicon Revisions
A3
X
2. Module: PWM
In PWM Latched Fault mode, the PWM outputs
may be latched on both the rising and the falling
edge of the Fault signal, regardless of the Fault
input polarity selection (set with the FLTPOL bit
(FCLCONx) setting).
3. Module: PWM
The PWMx generator may not assert dead time
on the edges of transitions. This has been
observed when all of the following conditions are
present:
• The PWMx generator is configured to operate
in Complementary mode with the
independent time base or master time base
• Immediate update is enabled
• The value in the PDCx register is updated in
such a manner that the PWMxH and PWMxL
outputs make an immediate transition
The current duty cycle, PDCOLD, newly calculated duty cycle, PDCNEW, and the point at
which the write to the Duty Cycle register occurs
within the PWMx time base, will determine if the
PWMxH and PWMxL outputs make an immediate transition. PWMxH and PWMxL outputs
make an immediate transition if the Duty Cycle
register is written with a new value, PDCNEW, at
a point of time when the PWMx time base is
counting a value that is in between PDCNEW and
PDCOLD. Additionally, writing to the Duty Cycle
register close to the instant of time where dead
time is being applied may result in reduced dead
time, effective on the PWMxH and PWMxL
transition edges.
In Figure 1, if the duty cycle write occurred in the
shaded box, then PWMxH and PWMxL will
make an immediate transition without dead
time.
Work around
None. However, in most applications, the duty
cycle update timing can be controlled using the
TRIGx trigger or Special Event Trigger to avoid
the above mentioned conditions.
Affected Silicon Revisions
Work around
None.
Affected Silicon Revisions
A3
X
A3
X
DS80000655C-page 4
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FIGURE 1:
TIMING DIAGRAMS FOR CENTER-ALIGNED AND EDGE-ALIGNED MODES
Period
Period
PTMRx
PHASEx
PTMRx
PHASEx
0
0
PWMxH
PWMxH
PDCOLD
PDCOLD
PWMxL
PWMxL
PWMxH
PWMxH
PDCNEW > PDCOLD
PDCNEW > PDCOLD
PWMxL
PWMxL
PWMxH
PWMxH
PDCNEW < PDCOLD
PDCNEW < PDCOLD
PWMxL
PWMxL
Center-Aligned Mode
2015-2016 Microchip Technology Inc.
Edge-Aligned Mode
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4. Module: PWM
In Edge-Aligned mode, changes to the PHASEx
register under certain circumstances will result
in missing dead time at the PWMxH-to-PWMxL
transition. This has been observed only when all
of the following are true:
• Master Time Base mode is enabled
(PWMCONx = 0)
• PHASEx is changed after the PWMx module
is enabled
• The PHASEx register value is changed, so that
either PHASEx < DTRx or PHASEx > PDCx
Work around
None.
7. Module: PWM
In
the
Redundant
Output
mode
(IOCONx = 0b01) and Push-Pull Output
mode (IOCONx = 0b10), with the
Immediate Update Enable bit disabled
(PWMCONx = 0), when the Duty Cycle
register is updated from a non-zero value to
zero, a glitch pulse of a width equal to 1 PWM
clock will appear at the next PWM period
boundary, as shown in Figure 2 (for the
Redundant Output mode). The Duty Cycle
register refers to the PDCx register if
PWMCONx = 0 or the MDC register if
PWMCONx = 1.
FIGURE 2:
EXAMPLE FOR REDUNDANT
OUTPUT MODE
Affected Silicon Revisions
A3
Duty Cycle > 0
Duty Cycle = 0
X
PWMxH
5. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the Overflow bit does not
always get set when an overflow occurs.
PWMxL
1 PWM Clock
Work around
Test for and handle overflow conditions outside
of the div.sd instruction.
Work around
Affected Silicon Revisions
If the application requires a zero duty cycle output,
there are two possible work around methods:
A3
X
6. Module: CPU
Table Write (TBLWTL, TBLWTH) instructions
cannot be the first or last instruction of a DO loop.
Work around
None.
Affected Silicon Revisions
A3
X
1. Use the PWM override feature to override the
PWM output to a low state instead of writing to
the Duty Cycle register. In order to switch back
to a non-zero duty cycle output, turn off the
PWM override. The override-on and overrideoff events must be timed close to the PWM
period boundary if the IOCONx register has
been configured with IOCONx = 0 (i.e.,
output overrides through the OVDDAT
bits occur on the next CPU clock boundary).
2. Enable the Immediate Update Enable bit
(PWMCONx = 1) while configuring the
PWMx module (i.e., before enabling the
PWMx module, PTCON = 1). With the
Immediate Update enabled, writes to the
Duty Cycle register can have an immediate
effect on the PWM output. Therefore, the
duty cycle write operations must be timed
close to the PWM period boundary in order to
avoid distortions in the PWM output.
Affected Silicon Revisions
A3
X
DS80000655C-page 6
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8. Module: PWM
10. Module: PWM
If PWM Fault interrupts are disabled (FLTIEN = 0
or CLIEN = 0), then associated status bits
(FLTSTAT and CLSTAT) will not function.
Work around
None.
Affected Silicon Revisions
A3
X
9. Module: PWM
When the PWM module is configured for
Push-Pull mode (IOCONx = 0b10)
with the Enable Immediate Period Update bit
enabled (PTCON = 1), a write to the Period
register that coincides with the period rollover
event may cause the push-pull output logic to
produce back-to-back pulses on the PWMx pins
(Figure 3).
FIGURE 3:
The triggers generated by the PWMx Primary
Trigger Compare Value register (TRIGx) and the
PWMx Secondary Trigger Compare Value
register (STRIGx) will not trigger at the point
defined by the TRIGx/STRIGx register values
on the first instance for the configurations listed
below. Subsequent trigger instances are not
affected.
• Trigger compare values for TRIGx and
STRIGx are less than 8 counts
• Trigger Output Divider bits, TRGDIV
(TRGCONx), are greater than ‘0’
• Trigger Postscaler Start Enable Select bits,
TRGSTRT (TRGCONx), are
equal to ‘0’
Work around
Configure the PWMx Primary Trigger Compare
Value Register (TRIGx) and PWMx Secondary
Trigger Compare Value Register (STRIGx)
values to be equal to or greater than 8.
Affected Silicon Revisions
A3
Period Updated at
PWM Rollover
X
FSW
PWMxH
PWMxL
Work around
If the EIPU bit is set (PTCON = 1), ensure
that the update to the PWM Period register
occurs away from the PWM rollover event. Use
either the PWM Special Event Trigger
(SEVTCMP) or the PWM Primary Trigger
(TRIGx) to generate a PWM Interrupt Service
Routine (ISR) near the start of the PWM cycle.
The PWM Period register could be updated
inside this ISR so that the period writes do not
occur near the PWM period rollover event.
Affected Silicon Revisions
A3
11. Module: I2C
In applications with multiple I2C slaves, bus data
can become corrupted when the data payload
sent to an addressed slave device matches the
bus address of another (unaddressed) slave
device.
Work around
Keep track of the bus address and data phases
in software. When Address Hold Enable is used
(the AHEN bit is set), the application can assert
a NACK for any of the received bytes (invalid
addresses and data bytes for other slave
devices) until a Stop bit is received.
Affected Silicon Revisions
A3
X
X
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12. Module: PWM
When the PWM module is configured for PushPull mode (IOCONx = 0b10) with the
Enable
Immediate
Period
Update
bit
(PTCON = 0), and is operating in Master
Time Base mode (ITB (PWMCONx) = 0), a
write to the Period register occurs on PWMx
cycle boundaries. This may cause the push-pull
output logic to produce back-to-back pulses on
the PWMx pins.
Work around
Work around 1: Ensure that the Enable
Immediate Period Updates bit (PTCON = 1)
is set.
Work around 2: Configure the PWM Phase-Shift
Value (PHASEx) with a value higher than
0x0007. When multiple PWM generators are
configured in Push-Pull mode, configure the
PWM Phase Shift Value with a value higher than
0x0007 for respective PWM generators.
14. Module: ADC
When using multiple ADC cores, if one of the
ADC cores completes conversion while other
ADC cores are still converting, the data in the
ADC cores which are converting may be
randomly corrupted.
Work around
Work around 1: When using multiple ADC cores,
the ADC triggers must be sufficiently staggered
in time to ensure that the end of conversion of
one or more cores doesn't occur during the
conversion process of other cores.
Work around 2: For simultaneous conversion
requirements, make sure the following conditions
are met:
1.
All the ADC cores for simultaneous
conversion should have the same
configurations.
Avoid shared ADC core conversion with
any of the dedicated ADC cores; they can
be sequential.
The trigger to initiate ADC conversion
should be from the same source and at the
same time.
2.
Affected Silicon Revisions
A3
3.
X
Affected Silicon Revisions
13. Module: Auxiliary PLL
The Auxiliary PLL Lock bit (ACLKCON) is
asserted directly after enabling the APLL
module (ACLKCON).
A3
X
Work around
Add a 50 µs delay routine after enabling the
APLL lock bit.
Affected Silicon Revisions
A3
X
DS80000655C-page 8
2015-2016 Microchip Technology Inc.
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15. Module: I2C
In I2C10-Bit Slave Addressing mode, on receiving
the upper address byte (A9 and A8 bits), the
Acknowledge Time status bit (ACKTIM) is not
asserted during the Acknowledgment sequence.
This issue is not seen during the reception of the
lower address byte (A7 to A0) and data bytes.
The hardware asserts the ACKTIM on the falling
edge of the eighth clock and deasserts on the
rising edge of the ninth clock. In this case,
ACKTIM is not asserted on upper address byte
reception. When AHEN = 1, the clock is stretched
after the 8th falling edge and the ACKTIM bit is
asserted until the clock is released. If AHEN = 0,
the clock is not stretched and ACKTIM is
asserted during the Acknowledgment sequence,
which is of a short duration. Therefore, the user
application can see this issue of the ACKTIM bit
not getting asserted when AHEN = 1.
16. Module: I2C
In I2C Slave Receive mode, the Acknowledge
Time status bit (ACKTIM) has no effect if the
Address Hold Enable (AHEN) and Data Hold
Enable (DHEN) bits are disabled (AHEN = 0 and
DHEN = 0). The Acknowledge Time status bit
(ACKTIM) is asserted only if the Address Hold
Enable (AHEN) or Data Hold Enable (DHEN) bit
is enabled.
Work around
Instead of polling for the ACKTIM bit to be
asserted, poll for the RBF flag.
Affected Silicon Revisions
A3
X
Work around
Instead of polling for ACKTIM to be asserted,
poll for the RBF flag.
Affected Silicon Revisions
A3
X
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17. Module: PWM
The PENH and PENL bits in the IOCONx
register are used to assign ownership of the pins
to either the PWM module or the GPIO module.
The correct procedure to configure the PWM
module is to first assign pin ownership to the
PWM module and then enable it using the PTEN
bit in the PTCON register.
If the PWM module is enabled using the above
sequence, then a glitch may be observed on the
PWM pins before the actual switching of the
PWM outputs begins. This glitch may cause a
momentary turn-on of power MOSFETs that are
driven by the PWM pins and may cause damage
to the application hardware.
Work around
Perform the following steps to avoid any glitches
from appearing on the PWM outputs at the time
of enabling:
1. Configure the respective PWM pins to digital
inputs using the TRISx registers. This step
will put the PWM pins in a high-impedance
state. The PWM outputs must be maintained
in a safe state by using pull-up or pull-down
resistors.
EXAMPLE 1:
2. Assign pin ownership to the GPIO module by
configuring the PENH bit (IOCONx = 0)
and the PENL bit (IOCONx = 0).
3. Specify the PWM override state to the desired
safe state for the PWM pins using the
OVRDAT bit field in the IOCONx register.
4. Override the PWM outputs by setting the
OVRENH bit (IOCONx = 1) and the
OVRENL bit (IOCONx = 1).
5. Enable the PWM module by setting the
PTEN bit (PTCON = 1).
6. Remove the PWM overrides by configuring the
OVRENH bit (IOCONx = 0) and the
OVRENL bit (IOCONx = 0).
7. Ensure a delay of at least one full PWM cycle.
8. Assign pin ownership to the PWM module by
setting the PENH bit (IOCONx = 1) and
the PENL bit (IOCONx = 1).
The code in Example 1 illustrates the use of this
work around.
Affected Silicon Revisions
A3
X
CONFIGURE PWM MODULE TO PREVENT GLITCHES ON PWM1H AND PWM1L
PINS AT THE TIME OF ENABLING
TRISAbits.TRISA4 = 1;
TRISAbits.TRISA3 = 1;
//
//
//
//
Configure PWM1H/RA4 as digital input
Ensure output is in safe state using pull-up or pull-down resistors
Configure PWM1L/RA3 as digital input
Ensure output is in safe state using pull-up or pull-down resistors
IOCON1bits.PENH = 0;
IOCON1bits.PENL = 0;
// Assign pin ownership of PWM1H/RA4 to GPIO module
// Assign pin ownership of PWM1L/RA3 to GPIO module
IOCON1bits.OVRDAT = 0;
// Configure PWM outputs override state to the desired safe state
IOCON1bits.OVRENH = 1;
IOCON1bits.OVRENL = 1;
// Override PWM1H output
// Override PWM1L output
PTCONbits.PTEN = 1;
// Enable PWM module
IOCON1bits.OVRENH = 0;
IOCON1bits.OVRENL = 0;
// Remove override for PWM1H output
// Remove override for PWM1L output
Delay(x);
// Introduce a delay greater than one full PWM cycle
IOCON1bits.PENH = 1;
IOCON1bits.PENL = 1;
// Assign pin ownership of PWM1H/RA4 to PWM module
// Assign pin ownership of PWM1L/RA3 to PWM module
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18. Module: PWM
In Center-Aligned Complementary mode with
Independent Time Base, the expected dead time
between transitions of the PWMxH and PWMxL
outputs may not be asserted when SWAP
(IOCONx) is disabled under the following
conditions:
• PWMx module is enabled (PTEN = 1)
• SWAP is enabled prior to this event
Work around
None.
Affected Silicon Revisions
20. Module: CPU
An address error trap or incorrect application
behavior may occur if the variable exception
processing latency is enabled by setting the
VAR bit (CORCON = 1).
Work around
Enable the Fixed Interrupt Latency mode by
clearing the VAR bit (CORCON = 0).
Affected Silicon Revisions
A3
X
A3
X
19. Module: Comparator
Analog comparator output may have a jitter when
it is operating and this will generate erroneous
triggers/interrupts. If the PWM module is configured to be controlled by an analog comparator,
the output of the PWM generator may be affected
by jitter in the analog comparator output.
Work around:
Configure the Comparator Hysteresis Select bits,
HYSSEL, as ‘0b11’ (20 mV hysteresis)
and set the Digital Filter Enable bit, FLTREN
(CMPxCON), to ‘1’.
Affected Silicon Revisions
A3
X
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21. Module: CPU
context gets changed. A new context corresponding to the value in the Manual Context
Identifier bits (MCTXI) in the CTXTSTAT
register is selected by the hardware and the
CCTXI bits in the CTXTSTAT register are
modified to reflect this change.
When returning from an Interrupt Service Routine
(ISR) by executing the RETFIE instruction, in the
case of a nested interrupt, the Interrupt Priority bits
(IPC) associated with the lower priority interrupt are compared with the CTXTn bits field in the
FLTREG Configuration register:
When using interrupts with the Alternate Working
Register Set (automatic context assignment), no
more than one ISR without an Alternate Working
Register Set must be nested within an ISR with
an Alternate Working Register Set.
• If there is a match with either of the CTXTn
bits field, then the corresponding Alternate
Working Register Set is chosen and the
Current Context Identifier bits (CCTXI) in
the CTXTSTAT register are updated to reflect
the new Alternate Working Register Set.
• If there is no match with either of the CTXTn
bits field, then the expected behavior is to keep
the context (defined by the value of the Current
Context Identifier bits, CCTXI in the
CTXTSTAT register) unchanged. However, the
FIGURE 4:
Issue and work around are illustrated in Figure 4
and Figure 5, respectively. The figures show the
status bits, CCTXI and MCTXI, after
entering into an ISR from a lower priority ISR
(left pane), and after returning to the same ISR
from a higher priority ISR (right pane).
MISMATCH OF WORKING REGISTER SET WHEN NESTING MORE THAN ONE
INTERRUPT WITHIN INTERRUPTS THAT USE ALTERNATE WORKING REGISTER SETS
ISR1 with IPL of 4
CTXT1 = IPL4
CCTXI = 1
MCTXI = 0
CCTXI = 1
MCTXI = 0
Returns from
ISR2
Enters into
ISR2
ISR2 with IPL of 5
CTXT2 = IPL5
CCTXI = 2
MCTXI = 0
CCTXI = 2
MCTXI = 0
Returns from
ISR3
Enters into
ISR3
ISR3 with IPL of 6
No Preassigned
Alternate Working
Register Set
CCTXI = 2
MCTXI = 0
CCTXI = 0
MCTXI = 0
Enters into
ISR4
DS80000655C-page 12
ISR4 with IPL of 7
No Preassigned
Alternate Working
Register Set
CCTXI = 2
MCTXI = 0
CCTXI = 2
MCTXI = 0
CCTXI bits Mismatch
while Returning from a
High-Priority Interrupt in the
Absence of an Alternate
Working Register Set
Returns from
ISR4
2015-2016 Microchip Technology Inc.
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FIGURE 5:
WORK AROUND FOR MISMATCH OF WORKING REGISTER SET WHEN NESTING
MORE THAN ONE INTERRUPT WITHIN INTERRUPTS THAT USE ALTERNATE
WORKING REGISTER SETS
ISR1 with IPL of 4
CTXT1 = IPL4
CCTXI = 1
MCTXI = 0
CCTXI = 1
MCTXI = 0
Enters into
ISR2
Returns from
ISR2
ISR2 with IPL of 5
CTXT2 = IPL5
CCTXI = 2
MCTXI = 0
CCTXI = 2
MCTXI = 0
Returns from
ISR3
No Preassigned
Alternate Working
Register Set
asm(“CTXTSWP #0”);
Enters into
ISR3
ISR3 with IPL of 6
CCTXI = 0
MCTXI = 0
Enters into
ISR4
CCTXI = 0
MCTXI = 0
No Preassigned
Alternate Working
ISR4 with IPL of 7
Register Set
asm(“CTXTSWP #0”);
CCTXI = 0
MCTXI = 0
Work around
Work around 1: When using interrupts with the
Alternate Working Register Set, at the entry of all
ISRs that do not have an Alternate Working Register Set and have a higher IPL level than the ISRs
with an Alternate Working Register Set, perform a
manual context swap to Context #0 as:
asm(“CTXTSWP #0”);
Note:
Manual Context Swap to a
Default Working Register Set
in the Interrupt Eliminates the
Context Mismatch Issue
Returns from
ISR4
CCTXI = 0
MCTXI = 0
Work around 2: Always assign higher IPLs for the
ISRs that use an Alternate Working Register Set
than for the ISRs that do not use an Alternate
Working Register Set.
Affected Silicon Revisions
A3
X
The application software must not perform
a manual context swap (using the
CTXTSWP instruction) to a context other
than Context #0.
2015-2016 Microchip Technology Inc.
DS80000655C-page 13
dsPIC33EPXXGS202 FAMILY
22. Module: I2C
In Slave mode, when AHEN = 1 (Address Hold
Enable), if the ACKDT bit (Acknowledge Data) is
set at the beginning of address reception, clock
stretching will not happen after the 8th clock.
Work around
In Slave mode, user software should clear
ACKDT on receiving the Start bit.
Affected Silicon Revisions
A3
24. Module: SPI
When SPI is enabled for the first time, there may
be a spurious clock on the SCK. This may result
in one bit of data shifted out on the data line,
resulting in a mismatch between the clock and
data lines.
This issue may also occur when the SPI is disabled during data transmission and enabled
subsequently.
Work around
1.
Disable the SPI module after two SPI cycles
and then re-enable SPI; this will synchronize
the clock and data.
If the SPI is configured on PPS pins, first
enable the SPI without configuring the PPS,
then allow two SPI clocks to pass and then
configure the PPS to connect to the SPI
module. This will prevent the spurious SPI
clock going out on the pin. If the SPI module
is turned off periodically, ensure to turn off
the PPS as well.
X
2.
23. Module: I2C
In Slave mode, when DHEN = 1 (Data Hold
Enable), if the ACKDT bit (Acknowledge Data) is
set at the beginning of data reception then the
slave interrupt will not occur after the 8th clock.
Work around
In Slave mode, user software should clear
ACKDT on receiving the Start bit.
Affected Silicon Revisions
Affected Silicon Revisions
A3
X
A3
X
DS80000655C-page 14
2015-2016 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70005208C):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
None.
2015-2016 Microchip Technology Inc.
DS80000655C-page 15
dsPIC33EPXXGS202 FAMILY
APPENDIX A:
DOCUMENT
REVISION HISTORY
Rev A Document (5/2015)
This version of the document was never released.
Rev B Document (9/2015)
Includes silicon issues: 1 (UART), 2-4 (PWM),
5-6 (CPU), 7-10 (PWM), 11 (I2C), 12 (PWM), 13 (Auxiliary PLL), 14 (ADC), 15-16 (I2C), 17-18 (PWM) and
19 (Comparator).
Rev C Document (3/2016)
Adds new silicon issues 20 (CPU), 21 (CPU), 22 (I2C),
23 (I2C) and 24 (SPI).
DS80000655C-page 16
2015-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2015-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0388-3
DS80000655C-page 17
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DS80000655C-page 18
2015-2016 Microchip Technology Inc.
