dsPIC33EPXXGS202 FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with
Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions
Advanced Analog Features
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
• High-Speed ADC module:
- 12-bit with 2 dedicated SAR ADC cores and
one shared SAR ADC core
- Up to 3.25 Msps conversion rate per ADC core @
12-bit resolution
- Dedicated result buffer for each analog
channel
- Flexible and independent ADC trigger
sources
- Two digital comparators
- One oversampling filter
• Two Rail-to-Rail Comparators with Hysteresis:
- Dedicated 12-bit Digital-to-Analog Converter
(DAC) for each analog comparator
• Two Programmable Gain Amplifiers:
- Single-ended or independent ground
reference
- Five selectable gains (4x, 8x, 16x, 32x
and 64x)
- 40 MHz gain bandwidth
Flash Architecture
• 16 Kbytes-32 Kbytes of Program Flash
Core: 16-Bit dsPIC33E CPU
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL Plus
Hardware Divide
• 32-Bit Multiply Support
• Two Additional Working Register Sets (reduces
context switching)
Clock Management
•
•
•
•
•
±0.9% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep,
Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 0.5 mA/MHz Dynamic Current (typical)
• 10 μA IPD Current (typical)
High-Speed PWM
• Three PWM Generators (two outputs per
generator)
• Individual Time Base and Duty Cycle for each PWM
• 1.04 ns PWM Resolution (frequency, duty cycle,
dead time and phase)
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for:
- AC/DC, DC/DC, inverters, PFC, lighting
2015-2018 Microchip Technology Inc.
Interconnected SMPS Peripherals
• Reduces CPU Interaction to Improve Performance
• Flexible PWM Trigger Options for
ADC Conversions
• High-Speed Comparator Truncates PWM
(15 ns typical):
- Supports Cycle-by-Cycle Current mode control
- Current Reset mode (variable frequency)
Timers/Output Compare/Input Capture
• Three 16-Bit and One 32-Bit Timers/Counters
• One Output Compare (OC) module, Configurable
as Timers/Counters
• One Input Capture (IC) module
DS70005208E-page 1
dsPIC33EPXXGS202 FAMILY
Communication Interfaces
Qualification and Class B Support
• One UART module (15 Mbps):
- Supports LIN/J2602 protocols and IrDA®
• One 4-Wire SPI module (15 Mbps)
• One I2C module (up to 1 Mbaud) with SMBus
Support
• AEC-Q100 REVG (Grade 1, -40°C to +125°C)
• Class B Safety Library, IEC 60730
• 4x4x0.6 mm and 6x6x0.5 mm UQFN Packages
are Designed and Optimized to ease IPC9592B
2nd Level Temperature Cycle Qualification
Input/Output
Debugger Development Support
• Sink/Source up to 12mA/15mA, respectively;
Pin-Specific for Standard VOH/VOL
• 5V Tolerant Pins
• Selectable Open-Drain, Pull-ups and Pull-Downs
• External Interrupts on All I/O Pins
• Peripheral Pin Select (PPS) to allow Function
Remap with Six Virtual I/Os
• In-Circuit and In-Application Programming
• Three Program and One Complex
Data Breakpoint
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
RAM Bytes
Timers(1)
Input Capture
Output Compare
UART
SPI
External Interrupts(2)
PWM
ADC Inputs
I2C
ADC Cores
PGA
Analog Comparator
dsPIC33EP16GS202
28
16K
2K
3
1
1
1
1
3
3x2
12
1
3
2
2
dsPIC33EP32GS202
28
32K
2K
3
1
1
1
1
3
3x2
12
1
3
2
2
Note 1:
2:
Packages
Device
Program Memory Bytes
Remappable Peripherals
General Purpose I/O (GPIO)
dsPIC33EPXXGS202 FAMILY DEVICES
Pins
TABLE 1:
21 SSOP, SOIC, QFN-S,
UQFN (4x4 mm),
21
UQFN (6x6 mm)
The external clock for Timer1, Timer2 and Timer3 is remappable.
INT0 is not remappable; INT1 and INT2 are remappable.
DS70005208E-page 2
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
Pin Diagrams
= Pins are up to 5V tolerant
28-Pin SOIC,
28-Pin SSOP
1
28
AVDD
RA0
2
27
AVSS
RA1
3
26
RA3
RA2
4
25
RA4
RB0
5
RB9
6
RB10
7
VSS
8
RB1
9
RB2(2)
10
RB3
11
RB4
dsPIC33EPXXGS202
MCLR
24
RB14
23
RB13
22
RB12
21
RB11
20
VCAP
19
VSS
18
RB7
12
17
RB6
VDD
13
16
RB5
RB8
14
15
RB15
PIN FUNCTION DESCRIPTIONS
Pin
Pin Function
Pin
Pin Function
1
MCLR
15
PGEC3/RP47/RB15
2
AN0/PGA1P1/CMP1A/RA0
16
TDO/AN9/PGA2N2/RP37/RB5
3
AN1/PGA1P2/PGA2P1/CMP1B/RA1
17
PGED1/TDI/AN10/SCL1/RP38/RB6
4
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
18
PGEC1/AN11/SDA1/RP39/RB7
5
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
19
VSS
6
AN4/CMP2C/RP41/RB9
20
VCAP
7
AN5/CMP2D/RP42/RB10
21
TMS/PWM3H/RP43/RB11
8
VSS
22
TCK/PWM3L/RP44/RB12
9
OSC1/CLKI/AN6/RP33/RB1
23
PWM2H/RP45/RB13
10
OSC2/CLKO/AN7/PGA1N2/RP34/RB2(2)
24
PWM2L/RP46/RB14
PWM1H/RA4
11
PGED2/AN8/INT0/RP35/RB3
25
12
PGEC2/ADTRG31/RP36/RB4
26
PWM1L/RA3
13
VDD
27
AVSS
14
PGED3/FLT31/RP40/RB8
28
AVDD
Legend: Shaded pins are up to 5 VDC tolerant.
Note 1: RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
2: At device power-up, a pulse with an amplitude around 2V and a duration greater than 500 μs, may be observed on this device
pin, independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being driven
can endure this active duration.
2015-2018 Microchip Technology Inc.
DS70005208E-page 3
dsPIC33EPXXGS202 FAMILY
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
RA4
RA3
AVSS
AVDD
MCLR
RA0
RA1
28-Pin UQFN, 28-Pin UQFN,
28-Pin QFN-S
28 27 26 25 24 23 22
RA2
1
21
RB14
RB0
2
20
RB13
RB9
3
19
RB12
RB10
4
18
RB11
VSS
5
17
VCAP
RB1
6
16
VSS
RB2(2)
7
15
RB7
VDD
RB6
RB4
RB5
10 11 12 13 14
RB8
9
RB15
8
RB3
dsPIC33EPXXGS202
PIN FUNCTION DESCRIPTIONS
Pin
Pin Function
Pin
Pin Function
1
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
15
PGEC1/AN11/SDA1/RP39/RB7
2
AN3/PGA2P3/CMP1D/ CMP28/RP32/RB0
16
VSS
3
AN4/CMP2C/RP41/RB9
17
VCAP
4
AN5/CMP2D/RP42/RB10
18
TMS/PWM3H/RP43/RB11
5
VSS
19
TCK/PWM3L/RP44/RB12
6
OSC1/CLKI/AN6/RP33/RB1
20
PWM2H/RP45/RB13
7
OSC2/CLKO/AN7/PGA1N2/RP34/RB2(2)
21
PWM2L/RP46/RB14
8
PGED2/AN8/INT0/RP35/RB3
22
PWM1H/RA4
PWM1L/RA3
9
PGEC2/ADTRG31/RP36/RB4
23
10
VDD
24
AVSS
11
PGED3/FLT31/RP40/RB8
25
AVDD
12
PGEC3/RP47/RB15
26
MCLR
13
TDO/AN9/PGA2N2/RP37/RB5
27
AN0/PGA1P1/CMP1A/RA0
14
PGED1/TDI/AN10/SCL1/RP38/RB6
28
AN1/PGA1P2/PGA2P1/CMP1B/RA1
Legend: Shaded pins are up to 5 VDC tolerant.
Note 1: RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
2: At device power-up, a pulse with an amplitude around 2V and a duration greater than 500 μs, may be observed on this device
pin, independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being driven
can endure this active duration.
DS70005208E-page 4
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 11
3.0 CPU............................................................................................................................................................................................ 17
4.0 Memory Organization ................................................................................................................................................................. 27
5.0 Flash Program Memory.............................................................................................................................................................. 61
6.0 Resets ....................................................................................................................................................................................... 69
7.0 Interrupt Controller ..................................................................................................................................................................... 73
8.0 Oscillator Configuration .............................................................................................................................................................. 87
9.0 Power-Saving Features.............................................................................................................................................................. 97
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer1 ...................................................................................................................................................................................... 131
12.0 Timer2/3 .................................................................................................................................................................................. 135
13.0 Input Capture............................................................................................................................................................................ 139
14.0 Output Compare....................................................................................................................................................................... 143
15.0 High-Speed PWM..................................................................................................................................................................... 149
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 175
17.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 183
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 191
19.0 High-Speed, 12-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 197
20.0 High-Speed Analog Comparator .............................................................................................................................................. 227
21.0 Programmable Gain Amplifier (PGA) ....................................................................................................................................... 233
22.0 Special Features ...................................................................................................................................................................... 239
23.0 Instruction Set Summary .......................................................................................................................................................... 251
24.0 Development Support............................................................................................................................................................... 261
25.0 Electrical Characteristics .......................................................................................................................................................... 265
26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 311
27.0 Packaging Information.............................................................................................................................................................. 315
Appendix A: Revision History............................................................................................................................................................. 331
Index ................................................................................................................................................................................................. 333
The Microchip Web Site ..................................................................................................................................................................... 339
Customer Change Notification Service .............................................................................................................................................. 339
Customer Support .............................................................................................................................................................................. 339
Product Identification System ............................................................................................................................................................ 341
2015-2018 Microchip Technology Inc.
DS70005208E-page 5
dsPIC33EPXXGS202 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS70005208E-page 6
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS202 family of
devices. It is not intended to be a comprehensive resource. To complement the
information in this data sheet, refer to the
related section in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
This document contains device-specific information for
the dsPIC33EPXXGS202 Digital Signal Controller (DSC)
devices.
The dsPIC33EPXXGS202 devices contain extensive
Digital Signal Processor (DSP) functionality with a
high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific
register and bit information.
FIGURE 1-1:
dsPIC33EPXXGS202 FAMILY BLOCK DIAGRAM
CPU
Refer to Figure 3-1 for CPU diagram details.
PORTA
16
Power-up
Timer
Timing
Generation
OSC1/CLKI
PORTB
Oscillator
Start-up
Timer
16
POR/BOR
MCLR
VDD, VSS
AVDD, AVSS
Watchdog
Timer
Peripheral Modules
PGA1,
PGA2
ADC
Input
Capture 1
Output
Compare 1
I2C1
Remappable
Pins
Analog
Comparator
1-2
2015-2018 Microchip Technology Inc.
PWM
3x2
Timers
1-3
SPI1
UART1
Ports
DS70005208E-page 7
dsPIC33EPXXGS202 FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Type
Buffer
PPS
Type
Description
AN0-AN11
I
Analog
No
Analog input channels.
CLKI
I
No
CLKO
O
ST/
CMOS
—
External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
No
OSC2
I/O
ST/
CMOS
—
IC1
I
ST
Yes Capture Input 1.
OCFA
OC1
I
O
ST
—
Yes Compare Fault A input (for compare channels).
Yes Compare Output 1.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No External Interrupt 0.
Yes External Interrupt 1.
Yes External Interrupt 2.
No
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
RA0-RA4
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
No
PORTB is a bidirectional I/O port.
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
Yes Timer1 external clock input.
Yes Timer2 external clock input.
Yes Timer3 external clock input.
U1CTS
U1RTS
U1RX
U1TX
BCLK1
I
O
I
O
O
ST
—
ST
—
ST
Yes
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Request-to-Send.
UART1 receive.
UART1 transmit.
UART1 IrDA® baud clock output.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
I/O
I/O
ST
ST
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
FLT1-FLT8
FLT31
PWM1L-PWM3L
PWM1H-PWM3H
SYNCI1, SYNCI2
SYNCO1, SYNCO2
I
I
O
O
I
O
ST
ST
—
—
ST
—
Yes
No
No
No
Yes
Yes
PWM Fault Inputs 1 through 8.
PWM Fault Input 31.
PWM Low Outputs 1 through 3.
PWM High Outputs 1 through 3.
PWM Synchronization Inputs 1 and 2.
PWM Synchronization Outputs 1 and 2.
CMP1A-CMP2A
CMP1B-CMP2B
CMP1C-CMP2C
CMP1D-CMP2D
I
I
I
I
Analog
Analog
Analog
Analog
No
No
No
No
Comparator Channels 1A through 2A inputs.
Comparator Channels 1B through 2B inputs.
Comparator Channels 1C through 2C inputs.
Comparator Channels 1D through 2D inputs.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
DS70005208E-page 8
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
PPS
Type
Description
PGA1P1-PGA1P3
I
Analog
No
PGA1 Positive Inputs 1 through 3.
PGA1N2
I
Analog
No
PGA1 Negative Input 2.
PGA2P1-PGA2P3
I
Analog
No
PGA2 Positive Inputs 1 through 3.
PGA2N2
I
Analog
No
PGA2 Negative Input 2.
ADTRG31
I
ST
No
External ADC trigger source.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all
times.
AVSS
P
P
No
Ground reference for analog modules. This pin must be connected at
all times.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
2015-2018 Microchip Technology Inc.
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
DS70005208E-page 9
dsPIC33EPXXGS202 FAMILY
NOTES:
DS70005208E-page 10
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT DIGITAL
SIGNAL CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33EPXXGS202 family
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names which must always be
connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins
regardless if ADC module is not used (see
Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins
used for In-Circuit Serial Programming™ (ICSP™)
and debugging purposes (see Section 2.5 “ICSP
Pins”)
• OSC1 and OSC2 pins
when external oscillator source is used (see
Section 2.6 “External Oscillator Pins”)
2015-2018 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, above tens of
MHz, add a second ceramic-type capacitor in
parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
DS70005208E-page 11
dsPIC33EPXXGS202 FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
VDD
The placement of this capacitor should be close to the
VCAP pin. It is recommended that the trace length not
exceeds one-quarter inch (6 mm). See Section 22.4
“On-Chip Voltage Regulator” for details.
R1
VSS
VCAP
VDD
2.4
R
The MCLR
functions:
MCLR
dsPIC33EPXXGS202
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
pin
provides
two
specific
device
• Device Reset
• Device Programming and Debugging.
C
0.1 µF
Ceramic
Master Clear (MCLR) Pin
(i.e., A/D Conversion Rate/2)
2
1
L = ----------------------
2f C
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor, C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components as shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R(1)
R1(2)
2.2.1
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
MCLR
TANK CAPACITORS
CPU Logic Filter Capacitor
Connection (VCAP)
JP
dsPIC33EPXXGS202
C
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR ()(1)
RCOUNT
0000
0000
Extended Data Space (EDS) Read Page Register (DSRPAG)
—
0036
Legend:
Note 1:
0000
—
RCOUNT
DOSTARTL 003A
0000
—
—
0000
—
0000
DO Loop Start Address Register High (DOSTARTH)
0000
dsPIC33EPXXGS202 FAMILY
DS70005208E-page 34
4.5
2015-2018 Microchip Technology Inc.
TABLE 4-2:
File
Name
Addr.
DOENDL
003E
DOENDH
0040
SR
CORCON
CPU CORE REGISTER MAP (CONTINUED)
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 14
Bit 13
Bit 12
Bit 11
—
—
—
—
—
—
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
0000
0044
VAR
—
US1
US0
EDT
DL2
DL1
DL0
SATA
SATB
SATDW
ACCSAT
IPL3
SFA
RND
IF
0020
—
—
BWM3
BWM2
BWM1
BWM0
YWM3
YWM2
YWM1
YWM0
XWM3
XWM2
XWM1
DO Loop End Address Register Low (DOENDL)
—
—
—
—
Bit 0
All
Resets
Bit 15
—
DO Loop End Address Register High (DOENDH)
0000
0000
MODCON
0046 XMODEN YMODEN
XWM0
0000
XMODSRT
0048
X Mode Start Address Register (XMODSRT)
—
0000
XMODEND
004A
X Mode End Address Register (XMODEND)
—
0001
YMODSRT
004C
Y Mode Start Address Register (YMODSRT)
—
0000
YMODEND
004E
Y Mode End Address Register (YMODEND)
—
0001
XBREV
0050
BREN
DISICNT
0052
—
—
TBLPAG
0054
—
—
—
—
—
—
—
—
CTXTSTAT
005A
—
—
—
—
—
CCTXI2
CCTXI1
CCTXI0
0000
DISICNT
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The contents of this register should never be modified. The DSWPAG must always point to the first page.
0000
TBLPAG
—
—
—
—
—
0000
MCTXI2
MCTXI1
MCTXI0
0000
DS70005208E-page 35
dsPIC33EPXXGS202 FAMILY
Legend:
Note 1:
XBREV
INTERRUPT CONTROLLER REGISTER MAP
2015-2018 Microchip Technology Inc.
Bit 0
All
Resets
IC1IF
INT0IF
0000
MI2C1IF
SI2C1IF
0000
—
—
0000
—
U1EIF
—
0000
—
—
—
—
0000
—
—
—
—
PWM3IF
0000
ADCAN7IF
ADCAN6IF
ADCAN5IF
ADCAN4IF
ADCAN3IF
ADCAN2IF
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
ADFL0IF
ADCMP1IF
ADCMP0IF
—
0000
SPI1EIE
T3IE
T2IE
—
—
—
T1IE
OC1IE
IC1IE
INT0IE
0000
—
—
—
—
—
—
INT1IE
CNIE
AC1IF
MI2C1IE
SI2C1IE
0000
—
—
PSEMIE
—
—
—
—
—
—
—
—
—
0000
—
—
—
PSESIE
—
—
—
—
—
—
—
U1EIE
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
ADCAN0IE
—
—
—
—
—
AC3IE
AC2IE
—
—
—
—
—
—
PWM3IE
0000
—
—
—
—
—
—
—
—
—
—
ADCAN7IE
ADCAN6IE
ADCAN5IE
ADCAN4IE
ADCAN3IE
ADCAN2IE
0000
0832
—
—
ADCAN14IE
ADCAN13IE
ADCAN10IE
ADCAN9IE
ADCAN8IE
—
—
—
—
—
—
—
0000
IEC10
0834
—
—
I2C1BCIE
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC11
0836
—
—
—
—
—
—
—
—
—
—
—
—
ADFL0IE
ADCMP1IE
ADCMP0IE
—
0000
IPC0
0840
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
0842
—
T2IP2
T2IP1
T2IP0
—
—
—
—
—
—
—
—
—
—
—
—
4000
IPC2
0844
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
0846
—
NVMIP2
NVMIP1
NVMIP0
—
—
—
—
—
ADCIP2
ADCIP1
ADCIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4044
IPC4
0848
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
084A
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC7
084E
—
—
—
—
—
—
—
—
—
INT2IP2
INT2IP1
INT2IP0
—
—
—
—
0040
IPC14
085C
—
—
—
—
—
—
—
—
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0040
File
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
IFS0
0800
NVMIF
IFS1
0802
—
—
ADCIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
—
—
—
INT2IF
—
—
—
—
—
—
—
—
IFS3
0806
—
—
—
—
—
—
PSEMIF
—
—
—
—
IFS4
0808
—
—
—
—
—
—
PSESIF
—
—
—
IFS5
080A
PWM2IF
PWM1IF
—
—
—
—
—
—
IFS6
080C ADCAN1IF
ADCAN0IF
—
—
—
—
—
—
IFS7
080E
—
—
—
—
—
—
—
IFS9
0812
—
—
ADCAN14IF
ADCAN11IF
IFS10
0814
—
—
I2C1BCIF
—
—
IFS11
0816
—
—
—
—
IEC0
0820
NVMIE
—
ADCIE
IEC1
0822
—
—
IEC3
0826
—
IEC4
0828
IEC5
082A
IEC6
082C ADCAN1IE
IEC7
082E
IEC9
Legend:
Bit 3
Bit 2
—
T1IF
OC1IF
INT1IF
CNIF
AC1IF
—
—
—
—
—
—
—
—
—
AC2IF
—
—
—
—
—
ADCAN10IF
ADCAN9IF
ADCAN8IF
—
—
—
—
—
—
U1TXIE
U1RXIE
SPI1IE
INT2IE
—
—
—
—
—
—
—
—
PWM2IE
PWM1IE
ADCAN13IF ADCAN12IF
ADCAN12IE ADCAN11IE
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 4
Bit 1
dsPIC33EPXXGS202 FAMILY
DS70005208E-page 36
TABLE 4-3:
2015-2018 Microchip Technology Inc.
TABLE 4-3:
File
Name
INTERRUPT CONTROLLER REGISTER MAP (CONTINUED)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
U1EIP1
U1EIP0
—
—
—
—
0040
PSESIP1
PSESIP0
—
—
—
—
0040
—
—
—
—
—
—
4400
—
—
—
—
PWM3IP2
PWM3IP1
PWM3IP0
0004
—
—
—
—
—
—
—
—
4000
ADCAN0IP0
—
—
—
—
—
—
—
—
4400
ADCAN4IP1
ADCAN4IP0
—
ADCAN3IP2
ADCAN3IP1
ADCAN3IP0
—
ADCAN2IP2
ADCAN2IP1
ADCAN2IP0
4444
—
—
—
—
ADCAN7IP2
ADCAN7IP1
ADCAN7IP0
—
ADCAN6IP2
ADCAN6IP1
ADCAN6IP0
0044
—
ICDIP2
ICDIP1
ICDIP0
—
—
—
—
—
—
—
—
0400
ADCAN8IP0
—
—
—
—
—
—
—
—
—
—
—
—
4000
ADCAN12IP2 ADCAN12IP1 ADCAN12IP0
—
ADCAN9IP1
ADCAN9IP0
0444
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
IPC16
0860
—
—
—
—
—
—
—
—
—
U1EIP2
IPC18
0864
—
—
—
—
—
—
—
—
—
PSESIP2
IPC23
086E
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2
PWM1IP1
PWM1IP0
—
—
IPC24
0870
—
—
—
—
—
—
—
—
—
IPC25
0872
—
AC2IP2
AC2IP1
AC2IP0
—
—
—
—
IPC27
0876
—
ADCAN1IP2
ADCAN1IP1
ADCAN1IP0
—
ADCAN0IP2
ADCAN0IP1
IPC28
0878
—
ADCAN5IP2
ADCAN5IP1
ADCAN5IP0
—
ADCAN4IP2
IPC29
087A
—
—
—
—
—
IPC35
0886
—
—
—
—
IPC37
088A
—
ADCAN8IP2
ADCAN8IP1
IPC38
088C
—
IPC39
088E
—
IPC43
0896
—
—
IPC44
0898
—
ADFL0IP2
INTCON1 08C0
NSTDIS
OVAERR
INTCON2 08C2
GIE
INTCON3 08C4
—
Bit 5
—
ADCAN10IP2 ADCAN10IP1 ADCAN10IP0
—
ADCAN9IP2
ADCAN14IP2 ADCAN14IP1 ADCAN14IP0
—
ADCAN13IP2 ADCAN13IP1 ADCAN13IP0 0040
—
—
—
—
—
ADFL0IP1
ADFL0IP0
—
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
—
DISI
SWTRAP
—
—
—
—
AIVTEN
—
—
—
—
—
—
—
—
—
NAE
—
INTCON4 08C6
—
—
—
—
—
—
—
—
INTTREG 08C8
—
—
—
—
ILR3
ILR2
ILR1
ILR0
Legend:
—
ADCAN11IP2 ADCAN11IP1 ADCAN11IP0
Bit 6
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
—
—
I2C1BCIP2
I2C1BCIP0
—
—
—
—
0040
—
ADCMP1IP2 ADCMP1IP1 ADCMP1IP0
—
—
—
—
4440
MATHERR
ADDRERR
STKERR
OSCFAIL
—
0000
—
—
—
INT2EP
INT1EP
INT0EP
8000
—
—
DOOVR
—
—
—
APLL
0000
—
—
—
—
—
—
—
SGHT
0000
VECNUM7
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
0000
ADCMP1IP2 ADCMP1IP1 ADCMP1IP0
I2C1BCIP1
DS70005208E-page 37
dsPIC33EPXXGS202 FAMILY
Addr.
File
Name
Addr.
TIMER1 THROUGH TIMER3 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
xxxx
PR1
0102
Period Register 1
FFFF
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
—
TMR3HLD 0108
—
—
—
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
Timer2 Register
xxxx
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
xxxx
PR2
010C
Period Register 2
FFFF
PR3
010E
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Legend:
FFFF
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-5:
File
Name
Period Register 3
Addr.
INPUT CAPTURE 1 REGISTER MAP
Bit 15
Bit 14
Bit 13
IC1CON1 0140
—
—
ICSIDL
IC1CON2 0142
—
—
—
Bit 12
Bit 11
Bit 10
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
Bit 9
Bit 8
—
—
—
—
Bit 7
Bit 6
Bit 5
—
ICI1
ICI0
ICTRIG TRIGSTAT
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICOV
ICBNE
ICM2
ICM1
ICM0
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
All
Resets
0000
000D
IC1BUF
0144
Input Capture 1 Buffer Register
xxxx
IC1TMR
0146
Input Capture 1 Timer Register
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
OUTPUT COMPARE 1 REGISTER MAP
2015-2018 Microchip Technology Inc.
File
Name
Addr.
Bit 15
Bit 14
Bit 13
OC1CON1
0900
—
—
OCSIDL
OC1CON2
0902 FLTMD FLTOUT FLTTRIEN
Bit 12
Bit 11
Bit 10
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
ENFLTA
—
—
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
—
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
All
Resets
0000
000C
OC1RS
0904
Output Compare 1 Secondary Register
xxxx
OC1R
0906
Output Compare 1 Register
xxxx
OC1TMR
0908
Timer Value 1 Register
xxxx
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXGS202 FAMILY
DS70005208E-page 38
TABLE 4-4:
2015-2018 Microchip Technology Inc.
TABLE 4-7:
File
Name
PWM REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
PTCON
0C00
PTEN
—
PTCON2
0C02
—
—
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
PTSIDL SESTAT SEIEN
EIPU
SYNCPOL
SYNCOEN
SYNCEN
—
—
—
—
PTPER
0C04
SEVTCMP
0C06
MDC
0C0A
STCON
0C0E
—
—
—
STCON2
0C10
—
—
—
STPER
0C12
—
Bit 12
—
Bit 4
SYNCSRC2 SYNCSRC1 SYNCSRC0
—
—
Bit 3
SEVTPS3
—
Bit 2
Bit 1
Bit 0
PCLKDIV
0000
FFF8
—
—
—
MDC
SESTAT SEIEN
—
EIPU
—
SYNCPOL
SYNCOEN
SYNCEN
—
—
—
—
—
—
SEVTPS3
—
SEVTPS2 SEVTPS1 SEVTPS0 0000
—
PCLKDIV
0000
FFF8
PWM Secondary Special Event Compare Register (SSEVTCMP)
PWMKEY
0C1E
—
—
—
—
—
0000
0000
SYNCSRC2 SYNCSRC1 SYNCSRC0
PWM Secondary Master Time Base Period Register (STPER)
0C1A CHPCLKEN
All
Resets
SEVTPS2 SEVTPS1 SEVTPS0 0000
—
PWM Special Event Compare Register (SEVTCMP12:0>)
CHOP
CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
—
—
—
0000
—
—
—
0000
PWM Protection Lock/Unlock Key Value Register (PWMKEY)
0000
Addr.
PWM GENERATOR 1 REGISTER MAP
Bit 15
PWMCON1 0C20 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
DS70005208E-page 39
IOCON1
0C22
FCLCON1
0C24 IFLTMOD CLSRC4
PDC1
0C26
PWM Generator 1 Duty Cycle Register (PDC1)
0000
PHASE1
0C28
PWM Phase-Shift Value or Independent Time Base Period for the PWM Generator 1 Register (PHASE1)
0000
DTR1
0C2A
—
—
DTR1
0000
ALTDTR1
0C2C
—
—
ALTDTR1
0000
SDC1
0C2E
SDC1
SPHASE1
0C30
SPHASE1
TRIG1
0C32
TRGCON1
0C34 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG1
0C36
STRGCMP
—
—
—
0000
PWMCAP1 0C38
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
FLTSRC3
0000
0000
TRGCMP
—
FLTLEBEN
—
LEBCON1
0C3A
PHR
PHF
PLR
PLF
CLLEBEN
LEBDLY1
0C3C
—
—
—
—
AUXCON1
0C3E HRPDIS
HRDDIS
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
dsPIC33EPXXGS202 FAMILY
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
File
Name
Bit 5
PWM Primary Master Time Base Period Register (PTPER)
SSEVTCMP 0C14
Legend:
—
Bit 6
File
Name
Addr.
PWM GENERATOR 2 REGISTER MAP
Bit 15
PWMCON2 0C40 FLTSTAT
PENH
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
CLSTAT
TRGSTAT
PENL
POLH
CLSRC4
CLSRC3
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
C000
FLTMOD1
FLTMOD0
00F8
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON2
0C42
FCLCON2
0C44 IFLTMOD
PDC2
0C46
PWM Generator 2 Duty Cycle Register (PDC2)
0000
PHASE2
0C48
PWM Phase-Shift Value or Independent Time Base Period for the PWM Generator 2 Register (PHASE2)
0000
DTR2
0C4A
—
—
DTR2
0000
ALTDTR2
0C4C
—
—
ALTDTR2
0000
SDC2
0C4E
SDC2
SPHASE2
0C50
SPHASE2
TRIG2
0C52
TRGCON2
0C54 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG2
0C56
STRGCMP
—
—
—
0000
PWMCAP2 0C58
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
0000
0000
TRGCMP
—
FLTLEBEN
—
LEBCON2
0C5A
PHR
PHF
PLR
PLF
CLLEBEN
LEBDLY2
0C5C
—
—
—
—
AUXCON2
0C5E
HRPDIS
HRDDIS
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
dsPIC33EPXXGS202 FAMILY
DS70005208E-page 40
TABLE 4-9:
2015-2018 Microchip Technology Inc.
2015-2018 Microchip Technology Inc.
TABLE 4-10:
File
Name
Addr.
PWM GENERATOR 3 REGISTER MAP
Bit 15
PWMCON3 0C60 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
IOCON3
0C62
FCLCON3
0C64 IFLTMOD CLSRC4
PDC3
0C66
PWM Generator 3 Duty Cycle Value Register (PDC3)
0000
PHASE3
0C68
Phase-Shift Value or Independent Time Base Period for the PWM Generator 3 Register (PHASE3)
0000
DTR3
0C6A
—
—
DTR3
0000
ALTDTR3
0C6C
—
—
ALTDTR3
0000
SDC3
0C6E
SDC3
SPHASE3
0C70
SPHASE3
TRIG3
0C72
TRGCON3
0C74 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG3
0C76
STRGCMP
—
—
—
0000
PWMCAP3 0C78
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
FLTSRC3
0000
0000
TRGCMP
—
LEBCON3
0C7A
PHR
PHF
PLR
PLF
CLLEBEN
LEBDLY3
0C7C
—
—
—
—
AUXCON3
0C7E HRPDIS
HRDDIS
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS70005208E-page 41
dsPIC33EPXXGS202 FAMILY
FLTLEBEN
—
—
I2C1 REGISTER MAP
File
Name
Addr.
Bit 15
Bit 14
Bit 13
I2C1CONL
0200
I2CEN
—
I2CSIDL
I2C1CONH
0202
—
—
—
—
—
I2C1STAT
0204
ACKTIM
—
I2C1ADD
0206
—
—
—
I2C1MSK
0208
—
—
—
I2C1BRG
020A
I2C1TRN
020C
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1RCV
020E
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
Legend:
ACKSTAT TRSTAT
RSEN
SEN
1000
AHEN
DHEN
0000
RBF
TBF
0000
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
—
—
—
—
PCIE
SCIE
BOEN
RCEN
PEN
SDAHT
SBCDE
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
—
—
—
I2C1 Address Register
0000
—
—
—
I2C1 Address Mask Register
0000
0000
UART1 REGISTER MAP
Addr.
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
U1TXREG
0224
—
U1RXREG 0226
—
Bit 15
Bit 14
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 12
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
WAKE
LPBACK
—
—
—
—
—
—
UART1 Transmit Register
xxxx
—
—
—
—
—
—
UART1 Receive Register
0000
URXISEL1 URXISEL0
Bit 0
All
Resets
Bit 13
0228
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
Baud Rate Generator Prescaler Register
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13:
SPI1 REGISTER MAP
2015-2018 Microchip Technology Inc.
File
Name
Addr.
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
SPI1CON1
0242
—
—
—
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
SPI1BUF
0248
Legend:
All
Resets
Bit 9
SCLREL STRICT
Bit 3
Bit 0
Bit 10
Baud Rate Generator Register
File
Name
Legend:
Bit 11
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
U1BRG
Bit 12
All
Resets
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
SPIBEC2
SPIBEC1
SPIBEC0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
FRMDLY SPIBEN
0000
DISSCK DISSDO MODE16
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI1 Transmit and Receive Buffer Register
0000
dsPIC33EPXXGS202 FAMILY
DS70005208E-page 42
TABLE 4-11:
2015-2018 Microchip Technology Inc.
TABLE 4-14:
ADC REGISTER MAP
File
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON1L
0300
ADON
—
ADSIDL
—
—
—
—
—
NRE
ADCON1H
0302
—
—
—
—
—
—
—
—
FORM
ADCON2L
0304
REFCIE
REFERCIE
—
EIEN
—
SHREISEL2
SHREISEL1
SHREISEL0
—
ADCON2H
0306
REFRDY
REFERR
—
—
—
—
SHRSAMC9
SHRSAMC8
ADCON3L
0308
REFSEL2
REFSEL1
REFSEL0
SUSPEND
SUSPCIE
SUSPRDY
SHRSAMP
ADCON3H
030A
CLKSEL1
CLKSEL0
CLKDIV5
CLKDIV4
CLKDIV3
CLKDIV2
ADCON4L
030C
—
—
—
—
—
ADCON4H
030E
—
—
—
—
ADMOD0L
0310
—
SIGN7
—
ADMOD0H
0312
—
—
DIFF14
ADIEL
0320
—
ADSTATL
0330
—
ADCMP0ENL
0338
—
ADCMP0LO
033C
ADC CMPLO Register
ADCMP0HI
033E
ADC CMPHI Register
ADCMP1ENL
0340
ADCMP1LO
0344
ADC CMPLO Register
0000
ADCMP1HI
0346
ADC CMPHI Register
0000
ADFL0DAT
0368
ADC FLDATA Register
ADFL0CON
036A
FLEN
MODE1
MODE0
ADTRIG0L
0380
—
—
—
ADTRIG0H
0382
—
—
ADTRIG1L
0384
—
ADTRIG1H
0386
ADTRIG2L
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
1000
SHRRES1
SHRRES0
—
—
—
—
—
0060
SHRADCS6
SHRADCS5
SHRADCS4
SHRADCS3
SHRADCS2
SHRADCS1
SHRADCS0
0000
SHRSAMC7
SHRSAMC6
SHRSAMC5
SHRSAMC4
SHRSAMC3
SHRSAMC2
SHRSAMC1
SHRSAMC0
0000
CNVRTCH
SWLCTRG
SWCTRG
CNVCHSEL5
CNVCHSEL4 CNVCHSEL3
CNVCHSEL2
CNVCHSEL1
CNVCHSEL0
0000
CLKDIV1
CLKDIV0
SHREN
—
—
—
—
—
C1EN
C0EN
0000
—
r
r
—
—
—
—
—
—
SAMC1EN
SAMC0EN
0000
—
—
—
—
—
—
—
—
C1CHS1
C1CHS0
C0CHS1
C0CHS0
0000
SIGN6
—
SIGN5
—
SIGN4
—
SIGN3
—
SIGN2
DIFF1
SIGN1
DIFF0
SIGN0
0000
SIGN14
—
SIGN13
—
SIGN12
—
SIGN11
—
SIGN10
—
SIGN9
—
SIGN8
0000
AN6RDY
AN5RDY
AN4RDY
AN3RDY
AN2RDY
AN1RDY
AN0RDY
Bit 6
IE
AN14RDY
AN13RDY
AN12RDY
AN11RDY
AN10RDY
AN9RDY
AN8RDY
AN7RDY
0000
CMPEN
CMPEN14
—
0000
0000
0000
—
CMPEN
OVRSAM1
OVRSAM0
IE
RDY
0000
0000
DS70005208E-page 43
—
—
—
TRGSRC1
—
—
—
TRGSRC0
0000
—
TRGSRC3
—
—
—
TRGSRC2
0000
—
—
TRGSRC5
—
—
—
TRGSRC4
0000
—
—
—
TRGSRC7
—
—
—
TRGSRC6
0000
0388
—
—
—
TRGSRC9
—
—
—
TRGSRC8
0000
ADTRIG2H
038A
—
—
—
TRGSRC11
—
—
—
TRGSRC10
0000
ADTRIG3L
038C
—
—
—
TRGSRC13
—
—
—
TRGSRC12
0000
ADTRIG3H
038E
—
—
—
—
—
—
—
—
—
—
—
TRGSRC14
ADCMP0CON 03A0
—
—
—
CHNL4
CHNL3
CHNL2
CHNL1
CHNL0
CMPEN
IE
STAT
BTWN
HIHI
HILO
LOHI
LOLO
0000
ADCMP1CON 03A4
—
—
—
CHNL4
CHNL3
CHNL2
CHNL1
CHNL0
CMPEN
IE
STAT
BTWN
HIHI
HILO
LOHI
LOLO
0000
ADLVLTRGL
03D0
—
ADCORE0L
03D4
—
—
—
—
—
—
ADCORE0H
03D6
—
—
—
EISEL2
EISEL1
EISEL0
ADCORE1L
03D8
—
—
—
—
—
—
ADCORE1H
03DA
—
—
—
EISEL2
EISEL1
EISEL0
ADEIEL
03F0
—
EIEN
1
1
(2 or 3)
None
CPBGT
CPBGT
Wb,Wn,Expr
Compare Wb with Wn, branch if >
1
1 (5)
None
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, skip if <
1
1
(2 or 3)
None
CPBLT
CPBLT
Wb,Wn,Expr
Compare Wb with Wn, branch if <
1
1 (5)
None
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, skip if
1
1
(2 or 3)
None
CPBNE
CPBNE
Wb,Wn,Expr
Compare Wb with Wn, branch if
1
1 (5)
None
22
23
24
25
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2015-2018 Microchip Technology Inc.
DS70005208E-page 255
dsPIC33EPXXGS202 FAMILY
TABLE 23-2:
Base
Instr
#
Assembly
Mnemonic
26
CTXTSWP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
CTXTSWP
#1it3
Switch CPU register context to context
defined by lit3
1
2
None
CTXTSWP
Wn
Switch CPU register context to context
defined by Wn
1
2
None
27
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
28
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C,DC,N,OV,Z
29
DEC2
30
DISI
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
31
DIV
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
32
DIVF
DIVF
Wm,Wn
Signed 16/16-bit Fractional Divide
1
18
N,Z,C,OV
33
DO
DO
#lit15,Expr
Do code to PC + Expr, lit15 + 1 times
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
2
2
None
34
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
35
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
None
36
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
37
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
38
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
39
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
40
GOTO
GOTO
Expr
Go to address
2
4
None
GOTO
Wn
Go to indirect
1
4
None
GOTO.L
Wn
Go to indirect (long address)
1
4
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
C,DC,N,OV,Z
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
1
1
OA,OB,OAB,
SA,SB,SAB
41
42
43
INC
INC2
IOR
44
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
45
LNK
LNK
#lit14
Link Frame Pointer
1
1
SFA
46
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005208E-page 256
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
TABLE 23-2:
Base
Instr
#
Assembly
Mnemonic
47
MAC
48
49
MOV
MOVPAG
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
None
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to
W(nd + 1):W(nd)
1
2
None
MOVPAG
#lit10,DSRPAG
Move 10-bit literal to DSRPAG
1
1
None
MOVPAG
#lit8,TBLPAG
Move 8-bit literal to TBLPAG
1
1
None
MOVPAGW
Ws, DSRPAG
Move Ws to DSRPAG
1
1
None
MOVPAGW
Ws, TBLPAG
Move Ws to TBLPAG
1
1
None
50
MOVSAC
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
Prefetch and store accumulator
1
1
None
51
MPY
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
52
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
53
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
54
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SS
Wb,Ws,Acc
Accumulator = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,Ws,Acc
Accumulator = signed(Wb) * unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Acc
Accumulator = signed(Wb) * unsigned(lit5)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
signed(Ws)
1
1
None
MUL.US
Wb,Ws,Acc
Accumulator = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.UU
Wb,#lit5,Acc
Accumulator = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,Ws,Acc
Accumulator = unsigned(Wb) *
unsigned(Ws)
1
1
None
MULW.SS
Wb,Ws,Wnd
Wnd = signed(Wb) * signed(Ws)
1
1
None
MULW.SU
Wb,Ws,Wnd
Wnd = signed(Wb) * unsigned(Ws)
1
1
None
MULW.US
Wb,Ws,Wnd
Wnd = unsigned(Wb) * signed(Ws)
1
1
None
MULW.UU
Wb,Ws,Wnd
Wnd = unsigned(Wb) * unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(lit5)
1
1
None
MUL.SU
Wb,#lit5,Wnd
Wnd = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
Wnd = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2015-2018 Microchip Technology Inc.
DS70005208E-page 257
dsPIC33EPXXGS202 FAMILY
TABLE 23-2:
Base
Instr
#
Assembly
Mnemonic
55
NEG
56
57
NOP
POP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
PUSH
Status Flags
Affected
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
1
2
None
POP.S
58
# of
# of
Words Cycles
Description
PUSH
Push Shadow Registers
1
1
None
59
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO,SLEEP
60
RCALL
RCALL
Expr
Relative Call
1
4
SFA
RCALL
Wn
Computed Call
1
4
SFA
REPEAT
#lit15
Repeat Next Instruction lit15 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
None
PUSH.S
61
REPEAT
62
RESET
RESET
Software device Reset
1
1
63
RETFIE
RETFIE
Return from interrupt
1
6 (5)
SFA
64
RETLW
RETLW
Return with literal in Wn
1
6 (5)
SFA
65
RETURN
RETURN
Return from Subroutine
1
6 (5)
SFA
66
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
C,N,Z
67
68
69
70
RLNC
RRC
RRNC
SAC
#lit10,Wn
71
SE
SE
Ws,Wnd
Wnd = sign-extended Ws
1
1
72
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
73
SFTAC
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005208E-page 258
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
TABLE 23-2:
Base
Instr
#
Assembly
Mnemonic
74
SL
75
76
77
78
79
SUB
SUBB
SUBR
SUBBR
SWAP
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
SL
f
f = Left Shift f
1
1
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
SUBB
f
f = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C,DC,N,OV,Z
SUBR
f
f = WREG – f
1
1
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
1
1
SWAP
Wn
Wn = byte swap Wn
1
1
None
None
80
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
1
5
None
81
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
5
None
82
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
83
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
84
ULNK
ULNK
Unlink Frame Pointer
1
1
SFA
85
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
1
1
C,Z,N
86
ZE
Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2015-2018 Microchip Technology Inc.
DS70005208E-page 259
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NOTES:
DS70005208E-page 260
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
24.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
24.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2015-2018 Microchip Technology Inc.
DS70005208E-page 261
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24.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other
relocatable object files and archives to create an
executable file. MPLAB XC Compiler uses the
assembler to produce its object file. Notable features of
the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
24.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
24.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
24.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS70005208E-page 262
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
24.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by
simulating the PIC MCUs and dsPIC DSCs on an
instruction level. On any given instruction, the data
areas can be examined or modified and stimuli can be
applied from a comprehensive stimulus controller.
Registers can be logged to files for further run-time
analysis. The trace buffer and logic analyzer display
extend the power of the simulator to record and track
program execution, actions on I/O, most peripherals
and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The
software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory
environment, making it an excellent, economical
software development tool.
24.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2015-2018 Microchip Technology Inc.
24.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the
MPLAB IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
24.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and
programming of PIC and dsPIC Flash microcontrollers
at a most affordable price point using the powerful
graphical user interface of the MPLAB IDE. The
MPLAB PICkit 3 is connected to the design engineer’s
PC using a full-speed USB interface and can be
connected to the target via a Microchip debug (RJ-11)
connector (compatible with MPLAB ICD 3 and MPLAB
REAL ICE). The connector uses two device I/O pins
and the Reset line to implement in-circuit debugging
and In-Circuit Serial Programming™ (ICSP™).
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a
modular, detachable socket assembly to support
various package types. The ICSP cable assembly is
included as a standard item. In Stand-Alone mode, the
MPLAB PM3 Device Programmer can read, verify and
program PIC devices without a PC connection. It can
also set code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS70005208E-page 263
dsPIC33EPXXGS202 FAMILY
24.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide
application firmware and source code for examination
and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
24.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and
demonstration software for analog filter design,
KEELOQ® security ICs, CAN, IrDA®, PowerSmart
battery management, SEEVAL® evaluation system,
Sigma-Delta ADC, flow rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70005208E-page 264
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
25.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33EPXXGS202 family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EPXXGS202 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) ................................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(3)................................................... -0.3V to +3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................300 mA
Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin ..................................................................................................25 mA
Maximum current sunk by all ports(2) ....................................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 25-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
2015-2018 Microchip Technology Inc.
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dsPIC33EPXXGS202 FAMILY
25.1
DC Characteristics
TABLE 25-1:
OPERATING MIPS vs. VOLTAGE
VDD Range
(in Volts)
Characteristic
Maximum MIPS
Temperature Range
(in °C)
dsPIC33EPXXGS202 Family
—
3.0V to 3.6V(1)
-40°C to +85°C
70
—
3.0V to 3.6V(1)
-40°C to +125°C
60
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators)
may have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 25-13 for the minimum and maximum BOR values.
TABLE 25-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typ.
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices
Extended Temperature Devices
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 25-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ.
Max.
Unit
Notes
Package Thermal Resistance, 28-Pin QFN-S
JA
30.0
—
°C/W
1
Package Thermal Resistance, 28-Pin UQFN
JA
26.0
—
°C/W
1
Package Thermal Resistance, 28-Pin SOIC
JA
69.7
—
°C/W
1
Package Thermal Resistance, 28-Pin SSOP
JA
71.0
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
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TABLE 25-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V(1)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
3.0
—
3.6
V
Conditions
Operating Voltage
DC10
VDD
Supply Voltage
(2)
DC12
VDR
RAM Data Retention Voltage
2.0
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
1.0
—
—
Note 1:
2:
V/ms 0V-3V in 3 ms
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators) may
have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 25-13 for the minimum and maximum BOR values.
This is the limit to which VDD may be lowered without losing RAM data.
TABLE 25-5:
FILTER CAPACITOR (CEFC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
CEFC
Note 1:
Characteristics
External Filter Capacitor
Value(1)
Min.
Typ.
Max.
Units
Comments
4.7
10
—
F
Capacitor must have a low
series resistance ( (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
|Injection Currents| > 0 can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
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TABLE 25-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IIL
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
Input Leakage Current(2,3)
DI50
I/O Pins 5V Tolerant(4)
-1
—
+1
A
VSS VPIN VDD,
pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
VSS VPIN VDD,
pin at high-impedance,
-40°C TA +85°C
DI51a
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
Analog pins shared with
external reference pins,
-40°C TA +85°C
DI51b
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
VSS VPIN VDD,
pin at high-impedance,
-40°C TA +125°C
DI51c
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
Analog pins shared with
external reference pins,
-40°C TA +125°C
DI55
MCLR
-5
—
+5
A
VSS VPIN VDD
DI56
OSC1
-5
—
+5
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL Source < (VSS – 0.3). Characterized but not tested.
VIH source > (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
|Injection Currents| > 0 can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
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TABLE 25-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
IICT
3:
4:
5:
6:
7:
8:
9:
Units
Conditions
0
—
-5(5,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
0
—
+5(6,7,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(7)
-20(7)
—
+20(7)
mA
Absolute instantaneous
sum of all ± input injection
currents from all I/O pins
( | IICL | + | IICH | ) IICT
Total Input Injection Current
(sum of all I/O and control
pins)
Note 1:
2:
Max.
Input High Injection Current
DI60b
DI60c
Typ.(1)
Input Low Injection Current
DI60a
IICH
Min.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL Source < (VSS – 0.3). Characterized but not tested.
VIH source > (VDD + 0.3) for non-5V tolerant pins only.
Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
|Injection Currents| > 0 can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
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TABLE 25-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Min.(1)
Typ.
Max.
Units
Output Low Voltage
4x Sink Driver Pins(2)
—
—
0.4
V
VDD = 3.3V,
IOL 6 mA, -40°C TA +85°C,
IOL 5 mA, +85°C < TA +125°C
Output Low Voltage
8x Sink Driver Pins(3)
—
—
0.4
V
VDD = 3.3V,
IOL 12 mA, -40°C TA +85°C,
IOL 8 mA, +85°C < TA +125°C
Output High Voltage
4x Source Driver Pins(2)
2.4
—
—
V
IOH -10 mA, VDD = 3.3V
Output High Voltage
8x Source Driver Pins(3)
2.4
—
—
V
IOH -15 mA, VDD = 3.3V
Output High Voltage
4x Source Driver Pins(2)
1.5
—
—
V
IOH -14 mA, VDD = 3.3V
2.0
—
—
V
IOH -12 mA, VDD = 3.3V
3.0
—
—
V
IOH -7 mA, VDD = 3.3V
Param. Symbol
DO10
VOL
DO20
VOH
DO20A VOH1
Characteristic
Output High Voltage
8x Source Driver Pins(3)
Note 1:
2:
3:
Conditions
1.5
—
—
V
IOH -22 mA, VDD = 3.3V
2.0
—
—
V
IOH -18 mA, VDD = 3.3V
3.0
—
—
V
IOH -10 mA, VDD = 3.3V
Parameters are for design guidance only and are not tested in manufacturing.
4x Drive Pins – RA, RB1, RB.
8x Drive Pins – MCLR, RA, RB0, RB, RB.
TABLE 25-13: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.(2)
Typ.
Max.
Units
BOR Event on VDD Transition
High-to-Low
2.65
—
2.95
V
Conditions
BO10
VBOR
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, PGAs and comparators) may have degraded
performance.
Parameters are for design guidance only and are not tested in manufacturing.
The VBOR specification is relative to VDD.
2:
3:
2015-2018 Microchip Technology Inc.
VDD (Notes 2, 3)
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TABLE 25-14: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.(1)
Max.
10,000
—
—
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
D131
VPR
VDD for Read
3.0
—
3.6
V
D132b
VPEW
VDD for Self-Timed Write
3.0
—
3.6
V
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated, -40C to +125C
D135
IDDP
Supply Current during
Programming(2)
—
10
—
mA
D136
IPEAK
Instantaneous Peak Current
During Start-up
—
—
150
mA
D137a
TPE
Page Erase Time
19.7
—
20.1
ms
TPE = 146893 FRC Cycles,
TA = +85°C (Note 3)
D137b
TPE
Page Erase Time
19.5
—
20.3
ms
TPE = 146893 FRC Cycles,
TA = +125°C (Note 3)
D138a
TWW
Word Write Cycle Time
46.5
—
47.3
µs
TWW = 346 FRC Cycles,
TA = +85°C (Note 3)
D138b
TWW
Word Write Cycle Time
46.0
—
47.9
µs
TWW = 346 FRC Cycles,
TA = +125°C (Note 3)
D139a
TRW
Row Write Time
667
—
679
µs
TRW = 4965 FRC Cycles,
TA = +85°C (Note 3)
D139b
TRW
Row Write Time
660
—
687
µs
TRW = 4965 FRC Cycles,
TA = +125°C (Note 3)
Note 1:
2:
3:
E/W -40C to +125C
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
Parameters are for design guidance only and are not tested in manufacturing.
Other conditions: FRC = 7.37 MHz, TUN = 011111 (for Min.), TUN = 100000 (for Max.). This
parameter depends on the FRC accuracy (see Table 25-20) and the value of the FRC Oscillator Tuning
register (see Register 8-4). For complete details on calculating the Minimum and Maximum time, see
Section 5.3 “Programming Operations”.
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25.2
AC Characteristics and Timing
Parameters
This section defines the dsPIC33EPXXGS202 family
AC characteristics and timing parameters.
TABLE 25-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 25.1 “DC
Characteristics”.
AC CHARACTERISTICS
FIGURE 25-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 25-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
DO50
Characteristic
Min.
Typ.
Max.
Units
Conditions
15
pF
In XT and HS modes, when
external clock is used to drive
OSC1
COSCO
OSC2 Pin
—
—
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCL1, SDA1
—
—
400
pF
In I2C mode
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FIGURE 25-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKO
OS41
OS40
TABLE 25-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
FIN
OS20
TOSC
OS25
Min.
Typ.(1)
Max.
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
60
MHz
EC
Oscillator Crystal Frequency
3.5
10
—
—
10
40
MHz
MHz
XT
HS
TOSC = 1/FOSC
8.33
—
DC
ns
+125°C
TOSC = 1/FOSC
7.14
—
DC
ns
+85°C
Instruction Cycle Time(2)
16.67
—
DC
ns
+125°C
Instruction Cycle Time(2)
14.28
—
DC
ns
+85°C
Symb
TCY
Characteristic
Conditions
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.45 x TOSC
—
0.55 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3,4)
—
5.2
—
ns
(3,4)
OS41
TckF
CLKO Fall Time
—
5.2
—
ns
OS42
GM
External Oscillator
Transconductance(4)
—
12
—
mA/V
HS, VDD = 3.3V,
TA = +25°C
—
6
—
mA/V
XT, VDD = 3.3V,
TA = +25°C
Note 1:
2:
3:
4:
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
Parameters are for design guidance only and are not tested in manufacturing.
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TABLE 25-18: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic
Min.
Typ.(1)
Max.
Units
FPLLI
PLL Voltage Controlled Oscillator
(VCO) Input Frequency Range
0.8
—
8.0
MHz
OS51
FVCO
On-Chip VCO System Frequency
120
—
340
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
ms
-3
0.5
3
%
OS50
OS53
Symbol
DCLK
Note 1:
2:
(2)
CLKO Stability (Jitter)
Conditions
ECPLL, XTPLL modes
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases, or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = ------------------------------------------------------------------------------------------F OSC
--------------------------------------------------------------------------------------Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPI1 Bit Rate = 10 MHz, the effective jitter is as follows:
D CLK
D CLK
D CLK
Effective Jitter = -------------- = -------------- = -------------3.464
120
12
--------10
TABLE 25-19: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ.(1)
Max
Units
OS56
FHPOUT
On-Chip 16x PLL CCO
Frequency
112
118
120
MHz
OS57
FHPIN
On-Chip 16x PLL Phase
Detector Input Frequency
7.0
7.37
7.5
MHz
OS58
TSU
Frequency Generator Lock
Time
—
—
10
µs
Note 1:
Conditions
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
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TABLE 25-20: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1,2)
F20a
FRC
F20b
FRC
Note 1:
2:
-2
0.5
+2
%
-40°C TA -10°C
-0.9
0.5
+0.9
%
-10°C TA +85°C
VDD = 3.0-3.6V
-2
1
+2
%
+85°C TA +125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
Over the lifetime of the 28-Lead 4x4 UQFN package device, the internal FRC accuracy could vary
between ±4%.
TABLE 25-21: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
LPRC
-30
—
+30
%
-40°C TA -10°C
VDD = 3.0-3.6V
-20
—
+20
%
-10°C TA +85°C
VDD = 3.0-3.6V
F21b
LPRC
-30
—
+30
%
+85°C TA +125°C VDD = 3.0-3.6V
Note 1:
This is the change of the LPRC frequency as VDD changes.
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FIGURE 25-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-22: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Typ.(1)
Max.
Units
—
5
10
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
5
10
ns
DI35
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
TRBP
CNx High or Low Time (input)
2
—
—
TCY
DI40
Note 1:
Port Output Rise Time
Min.
Conditions
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
FIGURE 25-4:
BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
Various Delays (depending on configuration)
Reset Sequence
CPU Starts Fetching Code
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TABLE 25-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Min.
Characteristic(1)
Symbol
Typ.(2)
Max. Units
Conditions
SY00
TPU
Power-up Period
—
400
600
s
SY10
TOST
Oscillator Start-up Time
—
1024 TOSC
—
—
TOSC = OSC1 Period
SY12
TWDT
Watchdog Timer
Time-out Period
0.81
—
1.22
ms
WDTPRE = 0,
WDTPOST = 0000,
using LPRC tolerances indicated in
F21a/F21b (see Table 25-21) at +85°C
3.25
—
4.88
ms
WDTPRE = 1,
WDTPOST = 0000,
using LPRC tolerances indicated in
F21a/F21b (see Table 25-21) at +85°C
SY13
TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
0.68
0.72
1.2
s
SY20
TMCLR
MCLR Pulse Width (low)
2
—
—
s
SY30
TBOR
BOR Pulse Width (low)
1
—
—
s
SY35
TFSCM
Fail-Safe Clock Monitor
Delay
—
500
900
s
SY36
TVREG
Voltage Regulator
Standby-to-Active mode
Transition Time
—
—
30
s
SY37
TOSCDFRC FRC Oscillator Start-up
Delay
—
—
29
s
SY38
TOSCDLPRC LPRC Oscillator Start-up
Delay
—
—
70
s
Note 1:
2:
-40°C to +85°C
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
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FIGURE 25-5:
TIMER1-TIMER3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10
Tx11
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
Symbol
TTXH
Characteristic(2)
T1CK High
Time
Min.
Typ.
Max.
Units
Conditions
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TA15,
N = Prescaler Value
(1, 8, 64, 256)
Asynchronous
35
—
—
ns
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
TA11
TTXL
T1CK Low
Time
TA15
TTXP
T1CK Input
Period
OS60
Ft1
T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON))
TA20
TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
Note 1:
2:
Asynchronous
10
—
—
ns
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
DC
—
50
kHz
0.75 TCY + 40
—
1.75 TCY + 40
ns
Must also meet
Parameter TA15,
N = Prescaler Value
(1, 8, 64, 256)
N = Prescale Value
(1, 8, 64, 256)
Timer1 is a Type A timer.
These parameters are characterized but not tested in manufacturing.
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TABLE 25-25: TIMER2 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min.
Typ.
Max.
Units
Conditions
TB10
TtxH
T2CK
High Time
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale Value
(1, 8, 64, 256)
TB11
TtxL
T2CK Low Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale Value
(1, 8, 64, 256)
TB15
TtxP
T2CK
Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = Prescale Value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External T2CK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
TABLE 25-26: TIMER3 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TC10
TtxH
T3CK
Synchronous
High Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TtxL
T3CK
Low Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TtxP
T3CK
Input
Period
Synchronous
with Prescaler
2 TCY + 40
—
—
ns
N = Prescale Value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External
T3CK Clock Edge to
Timer Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
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FIGURE 25-6:
INPUT CAPTURE 1 (IC1) TIMING CHARACTERISTICS
IC1
IC10
IC11
IC15
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-27: INPUT CAPTURE 1 MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
IC1 Input Low Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC11
TCCH
IC1 Input High Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC15
TCCP
IC1 Input Period
Greater of:
25 + 50 or
(1 TCY/N) + 50
—
ns
Note 1:
N = Prescale Value
(1, 4, 16)
These parameters are characterized but not tested in manufacturing.
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FIGURE 25-7:
OUTPUT COMPARE 1 MODULE (OC1) TIMING CHARACTERISTICS
OC1
(Output Compare 1
or PWM Mode)
OC11
OC10
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-28: OUTPUT COMPARE 1 MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC10
TccF
OC1 Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OC1 Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 25-8:
OC1/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OC1
TABLE 25-29: OC1/PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
OC15
TFD
Fault Input to PWMx I/O
Change
—
—
TCY + 20
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
DS70005208E-page 286
Conditions
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FIGURE 25-9:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 25-10:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
—
ns
See Parameter DO32
See Parameter DO31
MP10
TFPWM
PWMx Output Fall Time
—
—
MP11
TRPWM
PWMx Output Rise Time
—
—
—
ns
MP20
TFD
Fault Input to PWMx
I/O Change
—
—
15
ns
MP30
TFH
Fault Input Pulse Width
15
—
—
ns
Note 1:
Conditions
These parameters are characterized but not tested in manufacturing.
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TABLE 25-31: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
15 MHz
9 MHz
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
Table 25-31
—
—
0,1
0,1
0,1
—
Table 25-32
—
1
0,1
1
9 MHz
—
Table 25-33
—
0
0,1
1
15 MHz
—
—
Table 25-34
1
0
0
11 MHz
—
—
Table 25-35
1
1
0
15 MHz
—
—
Table 25-36
0
1
0
11 MHz
—
—
Table 25-37
0
0
0
FIGURE 25-11:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
MSb
SDO1
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 25-1 for load conditions.
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FIGURE 25-12:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
MSb
SDO1
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-32: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
15
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV,
TscL2doV
SDO1 Data Output Valid After
SCK1 Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDO1 Data Output Setup to
First SCK1 Edge
30
—
—
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 25-13:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
MSb
SDO1
LSb
SP30, SP31
SP40
SDI1
Bit 14 - - - - - -1
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-33: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic(1)
Min.
Typ.(2)
SP10 FscP
Maximum SCK1 Frequency
—
SP20 TscF
SCK1 Output Fall Time
—
SP21 TscR
SCK1 Output Rise Time
SP30 TdoF
SP31 TdoR
Max.
Units
—
9
MHz
—
—
ns
See Parameter DO32
(Note 4)
—
—
—
ns
See Parameter DO31
(Note 4)
SDO1 Data Output Fall
Time
—
—
—
ns
See Parameter DO32
(Note 4)
SDO1 Data Output Rise
Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO1 Data Output Valid
TscL2doV After SCK1 Edge
—
6
20
ns
SP36 TdoV2sc, SDO1 Data Output Setup
TdoV2scL to First SCK1 Edge
30
—
—
ns
SP40 TdiV2scH, Setup Time of SDI1 Data
TdiV2scL Input to SCK1 Edge
30
—
—
ns
SP41 TscH2diL, Hold Time of SDI1 Data
TscL2diL Input to SCK1 Edge
30
—
—
ns
Note 1:
2:
3:
4:
Conditions
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 25-14:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35 SP36
MSb
SDO1
Bit 14 - - - - - -1
SP30, SP31
SDI1
MSb In
LSb
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-34: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
-40°C to +125°C
(Note 3)
See Parameter DO32
(Note 4)
See Parameter DO31
(Note 4)
See Parameter DO32
(Note 4)
See Parameter DO31
(Note 4)
SP10
FscP
Maximum SCK1 Frequency
—
—
9
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDO1 Data Output Valid
—
6
20
ns
TscL2doV After SCK1 Edge
TdoV2scH, SDO1 Data Output Setup to
30
—
—
ns
TdoV2scL First SCK1 Edge
TdiV2scH, Setup Time of SDI1 Data
30
—
—
ns
TdiV2scL Input to SCK1 Edge
TscH2diL, Hold Time of SDI1 Data Input
30
—
—
ns
TscL2diL
to SCK1 Edge
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPI1 pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
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FIGURE 25-15:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SCK1
(CKP = 1)
SP72
SP36
SP35
SP72
MSb
SDO1
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
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TABLE 25-35: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input
Frequency
—
—
Lesser of:
FP or 15
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDO1 Data Output Valid After
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
—
—
50
ns
Note 1:
2:
3:
4:
SDO1 Data Output Valid After
SS1 Edge
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 25-16:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SCK1
(CKP = 1)
SP72
SP36
SP35
SP72
MSb
SDO1
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
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TABLE 25-36: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input
Frequency
—
—
Lesser of:
FP or 11
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDO1 Data Output Valid After
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
—
—
50
ns
Note 1:
2:
3:
4:
SDO1 Data Output Valid after
SS1 Edge
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 25-17:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS1
SP50
SP52
SCK1
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35 SP36
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
DS70005208E-page 296
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dsPIC33EPXXGS202 FAMILY
TABLE 25-37: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
15
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDO1 Data Output Valid After
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 After SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
2015-2018 Microchip Technology Inc.
DS70005208E-page 297
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FIGURE 25-18:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS1
SP50
SP52
SCK1
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35 SP36
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
DS70005208E-page 298
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dsPIC33EPXXGS202 FAMILY
TABLE 25-38: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
11
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDO1 Data Output Valid After
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SS1 After SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
2015-2018 Microchip Technology Inc.
DS70005208E-page 299
dsPIC33EPXXGS202 FAMILY
FIGURE 25-19:
I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL1
IM31
IM34
IM30
IM33
SDA1
Stop
Condition
Start
Condition
Note: Refer to Figure 25-1 for load conditions.
FIGURE 25-20:
I2C1 BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL1
IM26
IM11
IM25
IM10
IM33
SDA1
In
IM40
IM40
IM45
SDA1
Out
Note: Refer to Figure 25-1 for load conditions.
DS70005208E-page 300
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dsPIC33EPXXGS202 FAMILY
TABLE 25-39: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note 1:
2:
3:
4:
Characteristic(4)
Min.(1)
Max.
Units
TLO:SCL Clock Low Time 100 kHz mode
TCY (BRG + 1)
—
s
—
s
400 kHz mode
TCY (BRG + 1)
(2)
1 MHz mode
TCY (BRG + 1)
—
s
THI:SCL Clock High Time 100 kHz mode
TCY (BRG + 1)
—
s
—
s
400 kHz mode
TCY (BRG + 1)
1 MHz mode(2)
TCY (BRG + 1)
—
s
TF:SCL
SDA1 and SCL1 100 kHz mode
—
300
ns
Fall Time
300
ns
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
100
ns
TR:SCL SDA1 and SCL1 100 kHz mode
—
1000
ns
Rise Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(2)
1 MHz mode
40
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(2)
0.2
—
s
TSU:STA Start Condition 100 kHz mode
TCY (BRG + 1)
—
s
Setup Time
400 kHz mode
TCY (BRG + 1)
—
s
1 MHz mode(2)
TCY (BRG + 1)
—
s
THD:STA Start Condition 100 kHz mode
TCY (BRG + 1)
—
s
Hold Time
400 kHz mode
TCY (BRG + 1)
—
s
1 MHz mode(2)
TCY (BRG + 1)
—
s
TSU:STO Stop Condition 100 kHz mode
TCY (BRG + 1)
—
s
Setup Time
400 kHz mode
TCY (BRG + 1)
—
s
(2)
1 MHz mode
TCY (BRG + 1)
—
s
THD:STO Stop Condition 100 kHz mode
TCY (BRG + 1)
—
s
Hold Time
400 kHz mode
TCY (BRG + 1)
—
s
1 MHz mode(2)
TCY (BRG + 1)
—
s
TAA:SCL Output Valid
100 kHz mode
—
3500
ns
from Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
TBF:SDA Bus Free Time 100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(2)
0.5
—
s
Bus Capacitive Loading
—
400
pF
CB
TPGD
Pulse Gobbler Delay
65
390
ns
2
BRG is the value of the I C Baud Rate Generator.
Maximum Pin Capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
These parameters are characterized but not tested in manufacturing.
2015-2018 Microchip Technology Inc.
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
(Note 3)
DS70005208E-page 301
dsPIC33EPXXGS202 FAMILY
FIGURE 25-21:
I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL1
IS31
IS34
IS30
IS33
SDA1
Stop
Condition
Start
Condition
FIGURE 25-22:
I2C1 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL1
IS30
IS26
IS31
IS25
IS33
SDA1
In
IS40
IS40
IS45
SDA1
Out
DS70005208E-page 302
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dsPIC33EPXXGS202 FAMILY
TABLE 25-40: I2C1 BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(3)
IS10
TLO:SCL Clock Low Time
IS11
THI:SCL
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
IS51
Note
Clock High Time
Min.
Max.
Units
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
4.7
1.3
0.5
4.0
—
—
—
—
s
s
s
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.5
—
s
TF:SCL
SDA1 and SCL1 100 kHz mode
—
300
ns
Fall Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
TR:SCL SDA1 and SCL1 100 kHz mode
—
1000
ns
Rise Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(1)
1 MHz mode
100
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(1)
0
0.3
s
TSU:STA Start Condition
100 kHz mode
4.7
—
s
Setup Time
400 kHz mode
0.6
—
s
0.25
—
s
1 MHz mode(1)
THD:STA Start Condition
100 kHz mode
4.0
—
s
Hold Time
400 kHz mode
0.6
—
s
0.25
—
s
1 MHz mode(1)
TSU:STO Stop Condition
100 kHz mode
4
—
s
Setup Time
400 kHz mode
0.6
—
s
(1)
1 MHz mode
0.25
—
s
THD:STO Stop Condition
100 kHz mode
4
—
s
Hold Time
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
s
TAA:SCL Output Valid from 100 kHz mode
0
3500
ns
Clock
400 kHz mode
0
1000
ns
1 MHz mode(1)
0
350
ns
TBF:SDA Bus Free Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
0.5
—
s
1 MHz mode(1)
CB
Bus Capacitive Loading
—
400
pF
TPGD
Pulse Gobbler Delay
65
390
ns
1: Maximum Pin Capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.
3: These parameters are characterized but not tested in manufacturing.
2015-2018 Microchip Technology Inc.
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
Time the bus must be free
before a new transmission
can start
(Note 2)
DS70005208E-page 303
dsPIC33EPXXGS202 FAMILY
FIGURE 25-23:
UART1 MODULE I/O TIMING CHARACTERISTICS
UA20
U1RX
U1TX
MSb In
Bits 6-1
LSb In
UA10
TABLE 25-41: UART1 MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +125°C
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
UA10
TUABAUD
UART1 Baud Time
UA11
FBAUD
UART1 Baud Frequency
UA20
TCWF
Start Bit Pulse Width to Trigger
UART1 Wake-up
Note 1:
2:
Min.
Typ.(2)
66.67
—
—
ns
—
—
15
Mbps
500
—
—
ns
Max.
Units
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 25-42: ANALOG CURRENT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +125°C
AC CHARACTERISTICS
Param
No.
AVD01
Note 1:
2:
Symbol
IDD
Characteristic(1)
Analog Modules Current
Consumption
Min.
Typ.(2)
Max.
Units
Conditions
—
9
—
mA
Characterized data with the
following modules enabled:
APLL, 5 ADC Cores, 2 PGAs
and 4 Analog Comparators
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS70005208E-page 304
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dsPIC33EPXXGS202 FAMILY
TABLE 25-43: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(4)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(3)
Min.
Typical
Max.
Units
Conditions
The difference between
AVDD supply and VDD
supply must not exceed
±300 mV at all times,
including device power-up
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 3.0
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS
—
VSS + 0.3
V
Analog Input
AD12
VINH-VINL Full-Scale Input Span
AD14
VIN
Absolute Input Voltage
AVSS
—
AVDD
V
AVSS – 0.3
—
AVDD + 0.3
V
AD15
VIN+
Pseudodifferential
Mode
0
—
3.3
V
VIN- = (VR+ + VR-)/2
±150 mV
AD16
VIN-
Pseudodifferential
Mode
0
—
3.3
V
VIN+ = (VR+ + VR-)/2
±150 mV
AD17
RIN
Recommended
Impedance of Analog
Voltage Source
—
100
—
For minimum sampling
time (Note 1)
AD66
VREF1
Internal Voltage
Reference Source
1.176
1.2
1.224
V
ADC Accuracy: Pseudodifferential Input
AD20a Nr
Resolution
12
bits
AD21a INL
Integral Nonlinearity
> -4
—
-1
—
-5
—
-5
—
-4
—
-1
—
< 1.5
LSb AVSS = 0V, AVDD = 3.3V
(Note 5)
AD23b GERR
Gain Error
(Dedicated Core)
> -5
—
-5
—
-6
—
65
dB
(Notes 2, 3)
10.3
—
—
bits
(Notes 2, 3)
These parameters are not characterized or tested in manufacturing.
These parameters are characterized but not tested in manufacturing.
Characterized with a 1 kHz sine wave.
The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.
No missing codes, limits are based on the characterization results.
DS70005208E-page 306
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dsPIC33EPXXGS202 FAMILY
TABLE 25-44: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS(2)
Param
Symbol
No.
Characteristics
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(2)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.(1)
Max.
Units
Conditions
Clock Parameters
AD50
TAD
ADC Clock Period
14.28
AD51
FTP
ADC Core 0, 1, 2
—
—
—
ns
Throughput Rate
Note 1:
2:
—
3.25
Msps
70 MHz ADC clock, 12 bits,
no pending conversions at time of
trigger
These parameters are characterized but not tested in manufacturing.
The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.
TABLE 25-45: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS
AC/DC
CHARACTERISTICS(2)
Param
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min.
Typ.
Max.
Units
Comments
CM10
VIOFF
Input Offset Voltage
-35
±5
+35
mV
CM11
VICM
Input Common-Mode
Voltage Range(1)
0
—
AVDD
V
CM13
CMRR
Common-Mode
Rejection Ratio
60
—
—
dB
CM14
TRESP
Large Signal Response
—
15
—
ns
V+ input step of 100 mV while
V- input is held at AVDD/2. Delay
measured from analog input pin to
PWMx output pin.
CM15
VHYST
Input Hysteresis
5
10
20
mV
Depends on HYSSEL
CM16
TON
Comparator Enabled to
Valid Output
—
—
1
µs
Note 1:
2:
These parameters are for design guidance only and are not tested in manufacturing.
The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
2015-2018 Microchip Technology Inc.
DS70005208E-page 307
dsPIC33EPXXGS202 FAMILY
TABLE 25-46: DACx MODULE SPECIFICATIONS
AC/DC CHARACTERISTICS(2)
Param
No.
Symbol
Characteristic
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
—
-12
—
LSb
DA02
CVRES
Resolution
DA03
INL
Integral Nonlinearity Error
DA04
DNL
Differential Nonlinearity Error
-1.8
±0.5
1.8
LSb
DA05
EOFF
Offset Error
-8
3
15
LSb
DA06
EG
Gain Error
-0.8
-0.4
—
%
DA07
TSET
Settling Time(1)
—
700
—
ns
Note 1:
2:
12
Comments
bits
Output with 2% of desired
output voltage with a
10-90% or 90-10% step
Parameters are for design guidance only and are not tested in manufacturing.
The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
DS70005208E-page 308
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dsPIC33EPXXGS202 FAMILY
TABLE 25-47: PGAx MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
(1)
AC/DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
PA01
VIN
Input Voltage Range
AVSS – 0.3
—
AVDD + 0.3
V
PA02
VCM
Common-Mode Input
Voltage Range
AVSS
—
AVDD – 1.6
V
Comments
PA03
VOS
Input Offset Voltage
-20
—
+20
mV
PA04
VOS
Input Offset Voltage Drift
with Temperature
—
15
—
µV/C
PA05
RIN+
Input Impedance of
Positive Input
—
>1M || 7 pf
—
|| pF
PA06
RIN-
Input Impedance of
Negative Input
—
10K || 7 pf
—
|| pF
PA07
GERR
Gain Error
-2
—
+2
%
Gain = 4x and 8x
-3
—
+3
%
Gain = 16x
-4
—
+4
%
Gain = 32x and 64x
% of full scale,
Gain = 16x
PA08
LERR
Gain Nonlinearity Error
—
—
0.5
%
PA09
IDD
Current Consumption
—
2.0
—
mA
Small Signal
G = 4x
Bandwidth (-3 dB) G = 8x
—
10
—
MHz
—
5
—
MHz
PA10a BW
PA10b
PA10c
G = 16x
—
2.5
—
MHz
PA10d
G = 32x
—
1.25
—
MHz
G = 64x
PA10e
—
0.625
—
MHz
Output Settling Time to 1%
of Final Value
—
0.4
—
µs
SR
Output Slew Rate
—
40
—
V/µs
TGSEL
Gain Selection Time
—
1
—
µs
TON
Module Turn On/Setting
Time
—
—
10
µs
PA11
OST
PA12
PA13
PA14
Note 1:
Module is enabled with
a 2-volt P-P output
voltage swing
Gain = 16x, 100 mV
input step change
Gain = 16x
The PGAx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
2015-2018 Microchip Technology Inc.
DS70005208E-page 309
dsPIC33EPXXGS202 FAMILY
NOTES:
DS70005208E-page 310
2015-2018 Microchip Technology Inc.
DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 26-1:
FIGURE 26-3:
VOH – 4x DRIVER PINS
VOL(V)
0.050
3.6V
-0.045
3.6V
0.045
-0.040
3.3V
0.035
3V
-0.025
-0.020
Absolute Maximum
3V
0.030
0.025
0.020
Absolute Maximum
0.015
-0.010
0.010
-0.005
0.005
0.000
0.000
0.00
0.50
1.50
2.00
2.50
3.00
3.50
0.00
4.00
VOH – 8x DRIVER PINS
FIGURE 26-2:
-0.080
1.00
FIGURE 26-4:
0.50
1.00
1.50
2.00
3.00
3.6V
0.080
-0.070
0.070
3.3V
-0.060
3.3V
0.060
3V
DS70005208E-page 311
IOL(A)
IOH(A)
-0.050
-0.040
0 030
-0.030
3V
0.050
0.040
0.030
Absolute Maximum
Absolute Maximum
-0.020
0 020
0.020
-0.010
0.010
0.000
0.000
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.00
8X
VOL(V)
3.6V
3.50
VOL – 8x DRIVER PINS
VOH(V)
0.00
2.50
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
dsPIC33EPXXGS202 FAMILY
IOL(A)
IOH(A)
-0.030
-0.015
3.3V
0.040
-0.035
IOH(A)
VOL – 4x DRIVER PINS
VOH (V)
-0.050
IOH(A)
2015-2018 Microchip Technology Inc.
26.0
TYPICAL IPD CURRENT @ VDD = 3.3V
25
23
250
21
IDOZE Current (mA)
IPD Current (μA)
300
200
19
17
150
15
13
100
11
50
0
9
7
-40
-20
0
20
40
60
80
100
5
120
Temperature (Celsius)
FIGURE 26-6:
TYPICAL IDD CURRENT @ VDD = 3.3V, +25°C
IIDLE Current (mA)
2015-2018 Microchip Technology Inc.
IDD Current (mA)
25
20
15
10
10
20
30
40
MIPS
50
60
70
1:1
1:2
9
8
7
6
5
4
3
2
1
0
10
Doze Ratio
1:64
1:128
TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25°C
FIGURE 26-8:
30
5
TYPICAL IDOZE CURRENT @ VDD = 3.3V, +25°C
FIGURE 26-7:
20
30
40
MIPS
50
60
70
dsPIC33EPXXGS202 FAMILY
DS70005208E-page 312
FIGURE 26-5:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 26-10:
LPRC Frequency (kHz)
7350
7300
7250
7200
7150
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
34.4
7400
FRC Frequency (kHz)
2015-2018 Microchip Technology Inc.
FIGURE 26-9:
-40
-20
0
20
40
60
100
120
34
33.8
33.6
33.4
33.2
33
-40
-20
0
20
40
60
Temperature (Celsius)
80
100
120
DS70005208E-page 313
dsPIC33EPXXGS202 FAMILY
Temperature (Celsius)
80
34.2
dsPIC33EPXXGS202 FAMILY
NOTES:
DS70005208E-page 314
2015-2018 Microchip Technology Inc.
dsPIC33EPXXGS202 FAMILY
27.0
PACKAGING INFORMATION
27.1
Package Marking Information
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
dsPIC33EP16
GS202
1610017
28-Lead SOIC (.300”)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead UQFN (4x4x0.6 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
XXXXXXXX
XXXXXXXX
YYWWNNN
Example
Example
33EP32
GS202
1610017
28-Lead QFN-S (6x6x0.9 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
Note:
1610017
33EP32
GS202
1610017
28-Lead UQFN (6x6x0.5 mm)
Legend: XX...X
Y
YY
WW
NNN
dsPIC33EP32GS202
Example
33EP32
GS202
1610017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015-2018 Microchip Technology Inc.
DS70005208E-page 315
dsPIC33EPXXGS202 FAMILY
27.2
Package Details
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