dsPIC33EPXXGS50X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with
Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions
Advanced Analog Features
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
• High-Speed ADC module:
- 12-bit with 4 dedicated SAR ADC cores and
one shared SAR ADC core
- Configurable resolution (up to 12-bit) for each
ADC core
- Up to 3.25 Msps conversion rate per channel
at 12-bit resolution
- 12 to 22 single-ended inputs
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Two digital comparators
- Two oversampling filters for increased
resolution
• Four Rail-to-Rail Comparators with Hysteresis:
- Dedicated 12-bit Digital-to-Analog Converter
(DAC) for each analog comparator
- Up to two DAC reference outputs
- Up to two external reference inputs
• Two Programmable Gain Amplifiers:
- Single-ended or independent ground reference
- Five selectable gains (4x, 8x, 16x, 32x and 64x)
- 40 MHz gain bandwidth
Flash Architecture
• Dual Partition Flash Program Memory with
Live Update (64-Kbyte devices):
- Supports programming while operating
- Supports partition soft swap
Core: 16-Bit dsPIC33E CPU
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL Plus
Hardware Divide
• 32-Bit Multiply Support
• Two Additional Working Register Sets (reduces
context switching)
Clock Management
•
•
•
•
•
±0.9% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep,
Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 0.5 mA/MHz Dynamic Current (typical)
• 10 μA IPD Current (typical)
Interconnected SMPS Peripherals
• Reduces CPU Interaction to Improve Performance
• Flexible PWM Trigger Options for
ADC Conversions
• High-Speed Comparator Truncates PWM
(15 ns typical):
- Supports Cycle-by-Cycle Current mode control
- Current Reset mode (variable frequency)
High-Speed PWM
Timers/Output Compare/Input Capture
• Five PWM Generators (two outputs per generator)
• Individual Time Base and Duty Cycle for each PWM
• 1.04 ns PWM Resolution (frequency, duty cycle,
dead time and phase)
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC
and Lighting
• Five 16-Bit and up to Two 32-Bit Timers/Counters
• Four Output Compare (OC) modules, Configurable
as Timers/Counters
• Four Input Capture (IC) modules
2013-2017 Microchip Technology Inc.
DS70005127D-page 1
dsPIC33EPXXGS50X FAMILY
SPI
PWM(2)
External Interrupts(3)
Reference Clock
Analog Inputs
S&H Circuits
PGA
Analog Comparator
DAC Output
Constant-Current Source
dsPIC33EP16GS502
28
16K
2K
21
5
4
4
2
2
5x2
3
1
2
12
5
2
4
1
1
dsPIC33EP32GS502
28
32K
4K
21
5
4
4
2
2
5x2
3
1
2
12
5
2
4
1
1
dsPIC33EP64GS502
28
64K
8K
21
5
4
4
2
2
5x2
3
1
2
12
5
2
4
1
1
dsPIC33EP16GS504
44
16K
2K
35
5
4
4
2
2
5x2
3
1
2
19
5
2
4
1
1
dsPIC33EP32GS504
44
32K
4K
35
5
4
4
2
2
5x2
3
1
2
19
5
2
4
1
1
dsPIC33EP64GS504
44
64K
8K
35
5
4
4
2
2
5x2
3
1
2
19
5
2
4
1
1
dsPIC33EP16GS505
48
16K
2K
35
5
4
4
2
2
5x2
3
1
2
19
5
2
4
1
1
dsPIC33EP32GS505
48
32K
4K
35
5
4
4
2
2
5x2
3
1
2
19
5
2
4
1
1
dsPIC33EP64GS505
48
64K
8K
35
5
4
4
2
2
5x2
3
1
2
19
5
2
4
1
1
dsPIC33EP16GS506
64
16K
2K
53
5
4
4
2
2
5x2
4
1
2
22
5
2
4
2
1
dsPIC33EP32GS506
64
32K
4K
53
5
4
4
2
2
5x2
4
1
2
22
5
2
4
2
1
dsPIC33EP64GS506
64
64K
8K
53
5
4
4
2
2
5x2
4
1
2
22
5
2
4
2
1
Note 1:
2:
3:
12-Bit
ADC
I2C
Remappable Peripherals
Packages
Device
UART
• In-Circuit and In-Application Programming
• Five Program and Three Complex
Data Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
Output Compare
• Constant-Current Source (10 µA nominal)
• Sink/Source up to 12mA/15mA, respectively;
Pin-Specific for Standard VOH/VOL
• 5V Tolerant Pins
• Selectable, Open-Drain Pull-ups and Pull-Downs
• External Interrupts on All I/O Pins
• Peripheral Pin Select (PPS) to allow Function
Remap with Six Virtual I/Os
Input Capture
Debugger Development Support
Timers(1)
Input/Output
General Purpose I/O (GPIO)
• AEC-Q100 REVG (Grade 1, -40°C to +125°C)
• Class B Safety Library, IEC 60730
• The 6x6x0.5 mm UQFN Package is Designed and
Optimized to ease IPC9592B 2nd Level
Temperature Cycle Qualification
RAM (Bytes)
• Two UART modules (15 Mbps):
- Supports LIN/J2602 protocols and IrDA®
• Two 4-Wire SPI modules (15 Mbps)
• Two I2C modules (up to 1 Mbaud) with SMBus
Support
Program Memory Bytes
Qualification and Class B Support
Pins
Communication Interfaces
SOIC,
QFN-S,
UQFN
QFN,
TQFP
TQFP
TQFP
The external clock for Timer1, Timer2 and Timer3 is remappable.
PWM4 and PWM5 are remappable on all devices except the 64-pin devices.
External interrupts, INT0 and INT4, are not remappable.
DS70005127D-page 2
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Pin Diagrams
28-Pin SOIC
1
28
AVDD
RA0
2
27
AVSS
RA1
3
26
RA3
RA2
4
25
RA4
RB0
5
24
RB14
23
RB13
22
RB12
21
RB11
20
VCAP
RB9
6
RB10
7
VSS
8
RB1
9
RB2
10
RB3
dsPIC33EPXXGS502
Pin
MCLR
19
VSS
11
18
RB7
RB4
12
17
RB6
VDD
13
16
RB5
RB8
14
15
RB15
Pin Function
Pin
Pin Function
1
MCLR
15
PGEC3/SCL2/RP47/RB15
2
AN0/PGA1P1/CMP1A/RA0
16
TDO/AN19/PGA2N2/RP37/RB5
3
AN1/PGA1P2/PGA2P1/CMP1B/RA1
17
PGED1/TDI/AN20/SCL1/RP38/RB6
4
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
18
PGEC1/AN21/SDA1/RP39/RB7
5
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
19
VSS
6
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
20
VCAP
7
AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
21
TMS/PWM3H/RP43/RB11
8
Vss
22
TCK/PWM3L/RP44/RB12
9
OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
23
PWM2H/RP45/RB13
10
OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
24
PWM2L/RP46/RB14
11
PGED2/AN18/DACOUT1/INT0/RP35/RB3
25
PWM1H/RA4
12
PGEC2/ADTRG31/EXTREF1/RP36/RB4
26
PWM1L/RA3
13
VDD
27
AVSS
14
PGED3/SDA2/FLT31/RP40/RB8
28
AVDD
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
2013-2017 Microchip Technology Inc.
DS70005127D-page 3
dsPIC33EPXXGS50X FAMILY
Pin Diagrams (Continued)
Pin
RA1
RA0
MCLR
AVDD
AVSS
RA3
RA4
28
27
26
25
24
23
22
28-Pin QFN-S, UQFN
RA2
1
21
RB14
RB0
2
20
RB13
RB9
3
19
RB12
RB10
4
18
RB11
VSS
5
17
VCAP
RB1
6
16
VSS
RB2
7
15
RB7
8
9
10
11
12
13
14
RB3
RB4
VDD
RB8
RB15
RB5
RB6
dsPIC33EPXXGS502
Pin Function
Pin
Pin Function
1
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
15
PGEC1/AN21/SDA1/RP39/RB7
2
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
16
VSS
3
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
17
VCAP
4
AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
18
TMS/PWM3H/RP43/RB11
5
Vss
19
TCK/PWM3L/RP44/RB12
6
OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
20
PWM2H/RP45/RB13
7
OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
21
PWM2L/RP46/RB14
8
PGED2/AN18/DACOUT1/INT0/RP35/RB3
22
PWM1H/RA4
9
PGEC2/ADTRG31/EXTREF1/RP36/RB4
23
PWM1L/RA3
10
VDD
24
AVSS
11
PGED3/SDA2/FLT31/RP40/RB8
25
AVDD
12
PGEC3/SCL2/RP47/RB15
26
MCLR
13
TDO/AN19/PGA2N2/RP37/RB5
27
AN0/PGA1P1/CMP1A/RA0
14
PGED1/TDI/AN20/SCL1/RP38/RB6
28
AN1/PGA1P2/PGA2P1/CMP1B/RA1
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
DS70005127D-page 4
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Pin Diagrams (Continued)
Pin
1
RB6
RB5
RB15
RB8
VDD
VSS
RC8
RC7
RC2
RB4
RB3
44
43
42
41
40
39
38
37
36
35
34
44-Pin QFN
RB7
1
33
RB2
RC4
2
32
RB1
RC5
3
31
RC1
RC6
4
30
VSS
RC3
5
29
VDD
VSS
6
28
RC10
VCAP
7
27
RC9
RB11
8
26
RB10
RB12
9
25
RB9
RB13
10
24
RB0
RB14
11
23
RA2
Pin Function
PGEC1/AN21/SDA1/RP39/RB7
19
20
21
22
RC11
RC12
RA0
RA1
16
AVSS
18
15
RC13
MCLR
14
RC0
17
13
RA3
AVDD
12
RA4
dsPIC33EPXXGS504
Pin
23
Pin Function
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
2
AN1ALT/RP52/RC4
24
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
3
AN0ALT/RP53/RC5
25
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
4
AN17/RP54/RC6
26
AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
5
RP51/RC3
27
AN11/PGA1N3/RP57/RC9
6
VSS
28
AN10/PGA1P4/EXTREF2/RP58/RC10
7
VCAP
29
VDD
8
TMS/PWM3H/RP43/RB11
30
VSS
AN8/PGA2P4/CMP4C/RP49/RC1
9
TCK/PWM3L/RP44/RB12
31
10
PWM2H/RP45/RB13
32
OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
11
PWM2L/RP46/RB14
33
OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
12
PWM1H/RA4
34
PGED2/AN18/DACOUT1/INT0/RP35/RB3
13
PWM1L/RA3
35
PGEC2/ADTRG31/RP36/RB4
14
FLT12/RP48/RC0
36
AN9/CMP4D/EXTREF1/RP50 /RC2
15
FLT11/RP61/RC13
37
ASDA1/RP55/RC7
16
AVSS
38
ASCL1/RP56/RC8
17
AVDD
39
VSS
18
MCLR
40
VDD
19
AN12/ISRC1/RP59/RC11
41
PGED3/SDA2/FLT31/RP40/RB8
20
AN14/PGA2N3/RP60/RC12
42
PGEC3/SCL2/RP47/RB15
21
AN0/PGA1P1/CMP1A/RA0
43
TDO/AN19/PGA2N2/RP37/RB5
22
AN1/PGA1P2/PGA2P1/CMP1B/RA1
44
PGED1/TDI/AN20/SCL1/RP38/RB6
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
2013-2017 Microchip Technology Inc.
DS70005127D-page 5
dsPIC33EPXXGS50X FAMILY
Pin Diagrams (Continued)
Pin
1
RB6
RB5
RB15
RB8
VDD
VSS
RC8
RC7
RC2
RB4
RB3
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP
RB7
1
33
RB2
RC4
2
32
RB1
RC5
3
31
RC1
RC6
4
30
VSS
RC3
5
29
VDD
VSS
6
28
RC10
VCAP
7
27
RC9
RB11
8
26
RB10
RB12
9
25
RB9
RB13
10
24
RB0
RB14
11
23
RA2
Pin Function
20
21
22
RA0
RA1
17
AVDD
RC12
16
AVSS
19
15
RC13
RC11
14
RC0
18
13
RA3
MCLR
12
RA4
dsPIC33EPXXGS504
Pin
Pin Function
PGEC1/AN21/SDA1/RP39/RB7
23
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
2
AN1ALT/RP52/RC4
24
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
3
AN0ALT/RP53/RC5
25
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
4
AN17/RP54/RC6
26
AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
5
RP51/RC3
27
AN11/PGA1N3/RP57/RC9
6
VSS
28
AN10/PGA1P4/EXTREF2/RP58/RC10
7
VCAP
29
VDD
8
TMS/PWM3H/RP43/RB11
30
VSS
9
TCK/PWM3L/RP44/RB12
31
AN8/PGA2P4/CMP4C/RP49/RC1
10
PWM2H/RP45/RB13
32
OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
11
PWM2L/RP46/RB14
33
OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
12
PWM1H/RA4
34
PGED2/AN18/DACOUT1/INT0/RP35/RB3
13
PWM1L/RA3
35
PGEC2/ADTRG31/RP36/RB4
14
FLT12/RP48/RC0
36
AN9/CMP4D/EXTREF1/RP50 /RC2
15
FLT11/RP61/RC13
37
ASDA1/RP55/RC7
16
AVSS
38
ASCL1/RP56/RC8
17
AVDD
39
VSS
18
MCLR
40
VDD
19
AN12/ISRC1/RP59/RC11
41
PGED3/SDA2/FLT31/RP40/RB8
20
AN14/PGA2N3/RP60/RC12
42
PGEC3/SCL2/RP47/RB15
21
AN0/PGA1P1/CMP1A/RA0
43
TDO/AN19/PGA2N2/RP37/RB5
22
AN1/PGA1P2/PGA2P1/CMP1B/RA1
44
PGED1/TDI/AN20/SCL1/RP38/RB6
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
DS70005127D-page 6
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Pin Diagrams (Continued)
48
47
46
45
44
43
42
41
40
39
38
37
RB6
RB5
RB15
RB8
N/C
VDD
VSS
RC8
RC7
RC2
RB4
RB3
48-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
dsPIC33EPXXGS505
36
35
34
33
32
31
30
29
28
27
26
25
RB2
RB1
RC1
N/C
Vss
VDD
RC10
RC9
RB10
RB9
RB0
RA2
RA4
RA3
RC0
RC13
N/C
AVSS
AVDD
MCLR
RC11
RC12
RA0
RA1
13
14
15
16
17
18
19
20
21
22
23
24
RB7
RC4
RC5
RC6
RC3
VSS
VCAP
N/C
RB11
RB12
RB13
RB14
Pin
Pin Function
Pin
Pin Function
1
PGEC1/AN21/SDA1/RP39/RB7
25
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
2
AN1ALT/RP52/RC4
26
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
3
AN0ALT/RP53/RC5
27
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
4
AN17/RP54/RC6
28
AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
5
RP51/RC3
29
AN11/PGA1N3/RP57/RC9
6
VSS
30
AN10/PGA1P4/EXTREF2/RP58/RC10
7
VCAP
31
VDD
8
N/C
32
VSS
N/C
9
TMS/PWM3H/RP43/RB11
33
10
TCK/PWM3L/RP44/RB12
34
AN8/PGA2P4/CMP4C/RP49/RC1
11
PWM2H/RP45/RB13
35
OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
12
PWM2L/RP46/RB14
36
OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
13
PWM1H/RA4
37
PGED2/AN18/DACOUT1/INT0/RP35/RB3
14
PWM1L/RA3
38
PGEC2/ADTRG31/RP36/RB4
15
FLT12/RP48/RC0
39
AN9/CMP4D/EXTREF1/RP50 /RC2
16
FLT11/RP61/RC13
40
ASDA1/RP55/RC7
17
N/C
41
ASCL1/RP56/RC8
18
AVSS
42
VSS
19
AVDD
43
VDD
20
MCLR
44
N/C
21
AN12/ISRC1/RP59/RC11
45
PGED3/SDA2/FLT31/RP40/RB8
22
AN14/PGA2N3/RP60/RC12
46
PGEC3/SCL2/RP47/RB15
23
AN0/PGA1P1/CMP1A/RA0
47
TDO/AN19/PGA2N2/RP37/RB5
24
AN1/PGA1P2/PGA2P1/CMP1B/RA1
48
PGED1/TDI/AN20/SCL1/RP38/RB6
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
2013-2017 Microchip Technology Inc.
DS70005127D-page 7
dsPIC33EPXXGS50X FAMILY
RD1
RB14
RB13
RB12
RB11
RD15
RD4
VDD
VCAP
RC3
RD6
RD5
RC6
RC5
RC4
RB7
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
64-Pin TQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33EPXXGS506
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB6
RD0
RB5
RD11
RB15
RB8
RD8
Vss
RD9
RD14
VDD
RC8
RC7
RC2
RC14
RB4
RB9
RB10
AVDD
AVSS
RD7
RD13
RC9
RC10
VSS
VDD
RC1
RB1
RB2
RD2
RC15
RB3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RD3
RA4
RA3
RC0
RC13
RD10
MCLR
RD12
VSS
VDD
RC11
RC12
RA0
RA1
RA2
RB0
Pin
Pin Function
Pin
Pin Function
1
PWM4L/RD3
33
PGEC2/ADTRG31/RP36/RB4
2
PWM1H/RA4
34
RP62/RC14
3
PWM1L/RA3
35
AN9/CMP4D/EXTREF1/RP50/RC2
ASDA1/RP55/RC7
4
FLT12/RP48/RC0
36
5
FLT11/RP61/RC13
37
ASCL1/RP56/RC8
6
FLT10/RD10
38
VDD
7
MCLR
39
RD14
8
FLT9/T5CK/RD12
40
RD9
9
VSS
41
VSS
10
VDD
42
RD8
11
AN12/ISRC1/RP59/RC11
43
PGED3/SDA2/FLT31/RP40/RB8
12
AN14/PGA2N3/RP60/RC12
44
PGEC3/SCL2/RP47/RB15
13
AN0/PGA1P1/CMP1A/RA0
45
INT4/RD11
14
AN1/PGA1P2/PGA2P1/CMP1B/RA1
46
TDO/AN19/PGA2N2/RP37/RB5
15
AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
47
T4CK/RD0
16
AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
48
PGED1/TDI/AN20/SCL1/RP38/RB6
17
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
49
PGEC1/AN21/SDA1/RP39/RB7
18
AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
50
AN1ALT/RP52/RC4
19
AVDD
51
AN0ALT/RP53/RC5
20
AVSS
52
AN17/RP54/RC6
21
AN15/RD7
53
RD5
22
AN13/DACOUT2/RD13
54
PWM5H/RD6
23
AN11/PGA1N3/RP57/RC9
55
PWM5L/RP51/RC3
24
AN10/PGA1P4/EXTREF2/RP58/RC10
56
VCAP
25
VSS
57
VDD
26
VDD
58
RD4
27
AN8/PGA2P4/CMP4C/RP49/RC1
59
RD15
28
OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
60
TMS/PWM3H/RP43/RB11
29
OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
61
TCK/PWM3L/RP44/RB12
30
AN16/RD2
62
PWM2H/RP45/RB13
31
ASDA2/RP63/RC15
63
PWM2L/RP46/RB14
32
PGED2/AN18/DACOUT1/ASCL2/INT0/RP35/RB3
64
PWM4H/RD1
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.
DS70005127D-page 8
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 15
3.0 CPU............................................................................................................................................................................................ 21
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 77
6.0 Resets ....................................................................................................................................................................................... 85
7.0 Interrupt Controller ..................................................................................................................................................................... 89
8.0 Oscillator Configuration ............................................................................................................................................................ 103
9.0 Power-Saving Features............................................................................................................................................................ 115
10.0 I/O Ports ................................................................................................................................................................................... 125
11.0 Timer1 ...................................................................................................................................................................................... 163
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 167
13.0 Input Capture............................................................................................................................................................................ 171
14.0 Output Compare....................................................................................................................................................................... 175
15.0 High-Speed PWM..................................................................................................................................................................... 181
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 207
17.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 215
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 223
19.0 High-Speed, 12-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 229
20.0 High-Speed Analog Comparator .............................................................................................................................................. 263
21.0 Programmable Gain Amplifier (PGA) ....................................................................................................................................... 271
22.0 Constant-Current Source ......................................................................................................................................................... 275
23.0 Special Features ...................................................................................................................................................................... 277
24.0 Instruction Set Summary .......................................................................................................................................................... 289
25.0 Development Support............................................................................................................................................................... 299
26.0 Electrical Characteristics .......................................................................................................................................................... 303
27.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 349
28.0 Packaging Information.............................................................................................................................................................. 353
Appendix A: Revision History............................................................................................................................................................. 377
Index ................................................................................................................................................................................................. 379
The Microchip Web Site ..................................................................................................................................................................... 385
Customer Change Notification Service .............................................................................................................................................. 385
Customer Support .............................................................................................................................................................................. 385
Product Identification System ............................................................................................................................................................ 387
2013-2017 Microchip Technology Inc.
DS70005127D-page 9
dsPIC33EPXXGS50X FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70005127D-page 10
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
1.0
This document contains device-specific information for
the dsPIC33EPXXGS50X Digital Signal Controller (DSC)
devices.
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a comprehensive resource. To complement the
information in this data sheet, refer to the
related section of the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
dsPIC33EPXXGS50X devices contain extensive
Digital Signal Processor (DSP) functionality with a
high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific
register and bit information.
FIGURE 1-1:
dsPIC33EPXXGS50X FAMILY BLOCK DIAGRAM
CPU
Refer to Figure 3-1 for CPU diagram details.
PORTA
16
Power-up
Timer
OSC1/CLKI
Timing
Generation
PORTB
Oscillator
Start-up
Timer
16
PORTC
POR/BOR
MCLR
VDD, VSS
AVDD, AVSS
Watchdog
Timer
PORTD
Peripheral Modules
PGA1,
PGA2
ADC
Input
Captures
1-4
Output
Compares
1-4
I2C1,
I2C2
Remappable
Pins
Constant
Current
Source
Analog
Comparators
1-4
2013-2017 Microchip Technology Inc.
PWMs
5x2
Timers
1-5
SPI1,
SPI2
UART1,
UART2
Ports
DS70005127D-page 11
dsPIC33EPXXGS50X FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name(1)
Pin Buffer
PPS
Type Type
Description
AN0-AN21
AN0ALT-AN1ALT
I
I
Analog
Analog
No
No
Analog input channels.
Alternate analog input channels.
CLKI
I
ST/
CMOS
No
CLKO
O
—
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
No
OSC2
I/O
ST/
CMOS
—
REFCLKO
O
—
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Yes Reference clock output.
IC1-IC4
I
ST
Yes Capture Inputs 1 through 4.
OCFA
OC1-OC4
I
O
ST
—
Yes Compare Fault A input (for compare channels).
Yes Compare Outputs 1 through 4.
INT0
INT1
INT2
INT4
I
I
I
I
ST
ST
ST
ST
No
Yes
Yes
No
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
External Interrupt 4.
RA0-RA4
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
No
PORTB is a bidirectional I/O port.
RC0-RC15
I/O
ST
No
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
No
PORTD is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Yes
Yes
Yes
No
No
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1CTS
U1RTS
U1RX
U1TX
BCLK1
I
O
I
O
O
ST
—
ST
—
ST
Yes
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Request-to-Send.
UART1 receive.
UART1 transmit.
UART1 IrDA® baud clock output.
U2CTS
U2RTS
U2RX
U2TX
BCLK2
I
O
I
O
O
ST
—
ST
—
ST
Yes
Yes
Yes
Yes
Yes
UART2 Clear-to-Send.
UART2 Request-to-Send.
UART2 receive.
UART2 transmit.
UART2 IrDA baud clock output.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
1: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
2: These pins are dedicated on 64-pin devices.
DS70005127D-page 12
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name(1)
Pin Buffer
PPS
Type Type
Description
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
SCL2
SDA2
ASCL2
ASDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
Alternate synchronous serial clock input/output for I2C2.
Alternate synchronous serial data input/output for I2C2.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
FLT1-FLT8
FLT9-FLT12
FLT31
PWM1L-PWM3L
PWM1H-PWM3H
PWM4L-PWM5L(2)
PWM4H-PWM5H(2)
SYNCI1, SYNCI2
SYNCO1, SYNCO2
I
I
I
O
O
O
O
I
O
ST
ST
ST
—
—
—
—
ST
—
Yes
No
No
No
No
Yes
Yes
Yes
Yes
PWM Fault Inputs 1 through 8.
PWM Fault Inputs 9 through 12.
PWM Fault Input 31 (Class B Fault).
PWM Low Outputs 1 through 3.
PWM High Outputs 1 through 3.
PWM Low Outputs 4 and 5.
PWM High Outputs 4 and 5.
PWM Synchronization Inputs 1 and 2.
PWM Synchronization Outputs 1 and 2.
CMP1A-CMP4A
CMP1B-CMP4B
CMP1C-CMP4C
CMP1D-CMP4D
I
I
I
I
Analog
Analog
Analog
Analog
No
No
No
No
Comparator Channels 1 through 4 A input.
Comparator Channels 1 through 4 B input.
Comparator Channels 1 through 4 C input.
Comparator Channels 1 through 4 D input.
DACOUT1, DACOUT2
O
—
No
DAC Output Voltages 1 and 2.
EXTREF1, EXTREF2
I
Analog
No
External Voltage Reference Inputs 1 and 2 for the reference DACs.
ISRC1-ISRC4
O
Analog
No
Constant-Current Outputs 1 through 4.
PGA1P1-PGA1P4
I
Analog
No
PGA1 Positive Inputs 1 through 4.
PGA1N1-PGA1N3
I
Analog
No
PGA1 Negative Inputs 1 through 3.
PGA2P1-PGA2P4
I
Analog
No
PGA2 Positive Inputs 1 through 4.
PGA2N1-PGA2N3
I
Analog
No
PGA2 Negative Inputs 1 through 3.
ADTRG31
I
ST
No
External ADC trigger source.
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
1: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
2: These pins are dedicated on 64-pin devices.
2013-2017 Microchip Technology Inc.
DS70005127D-page 13
dsPIC33EPXXGS50X FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name(1)
Pin Buffer
PPS
Type Type
Description
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all
times.
AVSS
P
P
No
Ground reference for analog modules. This pin must be connected at
all times.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
TTL = TTL input buffer
1: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
2: These pins are dedicated on 64-pin devices.
DS70005127D-page 14
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT DIGITAL
SIGNAL CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33EPXXGS50X family
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names which must always be
connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins
regardless if ADC module is not used (see
Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins
used for In-Circuit Serial Programming™ (ICSP™)
and debugging purposes (see Section 2.5 “ICSP
Pins”)
• OSC1 and OSC2 pins
when external oscillator source is used (see
Section 2.6 “External Oscillator Pins”)
2013-2017 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, above tens of
MHz, add a second ceramic-type capacitor in
parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
DS70005127D-page 15
dsPIC33EPXXGS50X FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
VDD
The placement of this capacitor should be close to the
VCAP pin. It is recommended that the trace length not
exceeds one-quarter inch (6 mm). See Section 23.4
“On-Chip Voltage Regulator” for details.
R1
VSS
VCAP
VDD
2.4
R
The MCLR
functions:
MCLR
dsPIC33EP
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
pin
provides
two
specific
device
• Device Reset
• Device Programming and Debugging.
C
0.1 µF
Ceramic
Master Clear (MCLR) Pin
(i.e., ADC Conversion Rate/2)
2
1
L = ----------------------
2f C
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components as shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R(1)
R1(2)
2.2.1
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
MCLR
TANK CAPACITORS
CPU Logic Filter Capacitor
Connection (VCAP)
JP
dsPIC33EP
C
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR ()(1)
RCOUNT
0000
0000
Extended Data Space (EDS) Read Page Register (DSRPAG)
—
0036
DOSTARTH 003C
0000
—
RCOUNT
DOSTARTL 003A
0000
—
—
—
DO Start Address Register High (DOSTARTH)
0000
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 42
4.5
2013-2017 Microchip Technology Inc.
TABLE 4-2:
SFR
Name
Addr.
DOENDL
003E
DOENDH
0040
SR
CORCON
CPU CORE REGISTER MAP (CONTINUED)
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 14
Bit 13
Bit 12
Bit 11
—
—
—
—
—
—
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
0000
0044
VAR
—
US1
US0
EDT
DL2
DL1
DL0
SATA
SATB
SATDW
ACCSAT
IPL3
SFA
RND
IF
0020
—
—
BWM3
BWM2
BWM1
BWM0
YWM3
YWM2
YWM1
YWM0
XWM3
XWM2
XWM1
DO Loop End Address Register Low (DOENDL)
—
—
—
—
Bit 0
All
Resets
Bit 15
—
DO Loop End Address Register High (DOENDH)
0000
0000
MODCON
0046 XMODEN YMODEN
XWM0
0000
XMODSRT
0048
X Mode Start Address Register (XMODSRT)
—
0000
XMODEND 004A
X Mode End Address Register (XMODEND)
—
0001
YMODSRT
004C
Y Mode Start Address Register (YMODSRT)
—
0000
YMODEND 004E
Y Mode End Address Register (YMODEND)
—
0001
0050
BREN
XBREV
DISICNT
0052
—
—
TBLPAG
0054
—
—
—
—
—
—
—
—
CTXTSTAT
005A
—
—
—
—
—
CCTXI2
CCTXI1
CCTXI0
0000
DISICNT
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The contents of this register should never be modified. The DSWPAG must always point to the first page.
0000
TBLPAG
—
—
—
—
—
0000
MCTXI2
MCTXI1
MCTXI0
0000
DS70005127D-page 43
dsPIC33EPXXGS50X FAMILY
XBREV
SFR
Name
Addr.
INTERRUPT CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
2013-2017 Microchip Technology Inc.
IFS0
0800
NVMIF
—
ADCIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0802
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0804
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
0806
—
—
—
—
—
—
PSEMIF
—
—
INT4IF
—
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
0808
—
—
—
—
—
—
PSESIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
080A
PWM2IF
PWM1IF
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS6
080C
ADCAN1IF
ADCAN0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
—
—
—
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
080E
—
—
—
—
—
—
—
—
—
—
ADCAN7IF
ADCAN6IF
ADCAN5IF
ADCAN4IF
ADCAN3IF
ADCAN2IF
0000
IFS8
0810
JTAGIF
ICDIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS9
0812 ADCAN16IF(1)
ADCAN15IF(1)
ADCAN14IF(2)
ADCAN13IF(1)
ADCAN12IF(2)
ADCAN11IF(2)
ADCAN10IF(2)
ADCAN9IF(2)
ADCAN8IF(2)
—
—
—
—
—
—
—
0000
IFS10
0814
—
I2C2BCIF
I2C1BCIF
—
—
—
—
—
—
—
—
ADCAN21IF
ADCAN20IF
ADCAN19IF
ADCAN18IF
ADCAN17IF(2)
0000
IFS11
0816
—
—
—
—
—
—
—
—
—
—
—
ADFLTR1IF
ADFLTR0IF
ADCMP1IF
ADCMP0IF
—
0000
IEC0
0820
NVMIE
—
ADCIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0822
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
AC1IF
MI2C1IE
SI2C1IE
0000
IEC2
0824
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
0826
—
—
—
—
—
—
PSEMIE
—
—
INT4IE
—
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
0828
—
—
—
—
—
—
PSESIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
082A
PWM2IE
PWM1IE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC6
082C
ADCAN1IE
ADCAN0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
—
—
—
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
082E
—
—
—
—
—
—
—
—
—
—
ADCAN7IE
ADCAN6IE
ADCAN5IE
ADCAN4IE
ADCAN3IE
ADCAN2IE
0000
IEC8
0830
JTAGIE
ICDIE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC9
0832 ADCAN16IE(1)
ADCAN15IE(1)
ADCAN14IE(2)
ADCAN10IE(2)
ADCAN9IE(2)
ADCAN8IE(2)
—
—
—
—
—
—
—
0000
IEC10
0834
—
I2C2BCIE
I2C1BCIE
—
—
—
—
—
—
—
—
ADCAN21IE
ADCAN20IE
ADCAN19IE
ADCAN18IE
ADCAN17IE(2)
0000
IEC11
0836
—
—
—
—
—
—
—
—
—
—
—
ADFLTR1IE
ADFLTR0IE
ADCMP1IE
ADCMP0IE
—
0000
IPC0
0840
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
0842
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
0844
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
0846
—
NVMIP2
NVMIP1
NVMIP0
—
—
—
—
—
ADCIP2
ADCIP1
ADCIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4044
IPC4
0848
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
084A
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
084C
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
084E
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
0850
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
0044
IPC9
0852
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
Legend:
Note 1:
2:
ADCAN13IE(1) ADCAN12IE(2) ADCAN11IE(2)
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Only available on dsPIC33EPXXGS506 devices.
Only available on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 44
TABLE 4-3:
2013-2017 Microchip Technology Inc.
TABLE 4-3:
SFR
Name
INTERRUPT CONTROLLER REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
IPC12
0858
—
—
—
—
—
MI2C2IP2
MI2C2IP1
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
085A
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
—
—
—
—
—
—
—
0400
IPC14
085C
—
—
—
—
—
—
—
—
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0040
IPC16
0860
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
0864
—
—
—
—
—
—
—
—
—
PSESIP2
PSESIP1
PSESIP0
—
—
—
—
0040
IPC23
086E
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2
PWM1IP1
PWM1IP0
—
—
—
—
—
—
—
—
4400
IPC24
0870
—
—
—
—
—
PWM5IP2
PWM5IP1
PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
0444
IPC25
0872
—
AC2IP2
AC2IP1
AC2IP0
—
—
—
—
—
—
—
—
—
—
—
—
4000
IPC26
0874
—
—
—
—
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
IPC27
0876
—
ADCAN1IP2
ADCAN1IP1
ADCAN1IP0
—
ADCAN0IP2
ADCAN0IP1
ADCAN0IP0
—
—
—
—
—
—
—
—
4400
IPC28
0878
—
ADCAN5IP2
ADCAN5IP1
ADCAN5IP0
—
ADCAN4IP2
ADCAN4IP1
ADCAN4IP0
—
ADCAN3IP2
ADCAN3IP1
ADCAN3IP0
—
ADCAN2IP2
ADCAN2IP1
ADCAN2IP0
4444
IPC29
087A
—
—
—
—
—
—
—
—
—
ADCAN7IP2
ADCAN7IP1
ADCAN7IP0
—
ADCAN6IP2
ADCAN6IP1
ADCAN6IP0
0044
IPC35
0886
—
JTAGIP2
JTAGIP1
JTAGIP0
—
ICDIP2
ICDIP1
ICDIP0
—
—
—
—
—
—
—
—
4400
IPC37
088A
—
ADCAN8IP2(2)
ADCAN8IP1(2)
ADCAN8IP0(2)
—
—
—
—
—
—
—
—
—
—
—
—
4000
IPC38
088C
—
ADCAN12IP2(2) ADCAN12IP1(2) ADCAN12IP0(2)
—
ADCAN11IP2(2) ADCAN11IP1(2) ADCAN11IP0(2)
—
ADCAN10IP2(2) ADCAN10IP1(2) ADCAN10IP0(2)
—
ADCAN9IP2(2)
ADCAN9IP1(2)
ADCAN9IP0(2)
4444
IPC39
088E
—
ADCAN16IP2(1) ADCAN16IP1(1) ADCAN16IP0(1)
—
ADCAN15IP2(1) ADCAN15IP1(1) ADCAN15IP0(1)
—
ADCAN14IP2(2) ADCAN14IP1(2) ADCAN14IP0(2)
—
ADCAN13IP2(1)
ADCAN13IP1
ADCAN13IP0
4444
IPC40
0890
—
ADCAN20IP2
ADCAN20IP1
ADCAN20IP0
—
ADCAN19IP2
ADCAN19IP1
ADCAN19IP0
—
ADCAN18IP2
ADCAN18IP1
ADCAN18IP0
—
ADCAN17IP2(2) ADCAN17IP1(2) ADCAN17IP0(2)
IPC41
0892
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCAN21IP2
ADCAN21IP1
ADCAN21IP0
0004
IPC43
0896
—
—
—
—
—
I2C2BCIP2
I2C2BCIP1
I2C2BCIP0
—
I2C1BCIP2
I2C1BCIP1
I2C1BCIP0
—
—
—
—
0440
IPC44
0898
—
ADFLTR0IP2
ADFLTR0IP1
ADFLTR0IP0
—
ADCMP1IP2
ADCMP1IP1
ADCMP1IP0
—
ADCMP0IP2
ADCMP0IP1
ADCMP0IP0
—
—
—
—
4440
IPC45
089A
—
—
—
—
—
—
—
—
—
—
—
—
—
ADFLTR1IP2
ADFLTR1IP1
ADFLTR1IP0
0004
INTCON1 08C0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
0000
INTCON2 08C2
GIE
DISI
SWTRAP
—
—
—
—
AIVTEN
—
—
—
INT4EP
—
INT2EP
INT1EP
INT0EP
8000
INTCON3 08C4
—
—
—
—
—
—
—
NAE
—
—
—
DOOVR
—
—
—
APLL
0000
INTCON4 08C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SGHT
0000
INTTREG 08C8
—
—
—
—
ILR3
ILR2
ILR1
ILR0
VECNUM7
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
0000
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Only available on dsPIC33EPXXGS506 devices.
Only available on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices.
4444
DS70005127D-page 45
dsPIC33EPXXGS50X FAMILY
Addr.
SFR
Name
Addr.
TIMER1 THROUGH TIMER5 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
xxxx
PR1
0102
Period Register 1
FFFF
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
010A
—
—
—
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
Timer2 Register
TMR3HLD 0108
TMR3
—
0000
xxxx
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
Timer3 Register
xxxx
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
FFFF
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
TMR4
0114
Timer4 Register
TMR5HLD 0116
TMR5
0000
0000
xxxx
Timer5 Holding Register (for 32-bit operations only)
xxxx
Timer5 Register
xxxx
0118
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
FFFF
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 46
TABLE 4-4:
2013-2017 Microchip Technology Inc.
2013-2017 Microchip Technology Inc.
TABLE 4-5:
INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
IC1CON1
0140
—
—
ICSIDL
IC1CON2
0142
—
—
—
IC1BUF
0144
Input Capture 1 Buffer Register
IC1TMR
0146
Input Capture 1 Timer Register
IC2CON1
0148
—
—
ICSIDL
IC2CON2
014A
—
—
—
IC2BUF
014C
Input Capture 2 Buffer Register
IC2TMR
014E
Input Capture 2 Timer Register
IC3CON1
0150
—
—
ICSIDL
IC3CON2
0152
—
—
—
IC3BUF
0154
Input Capture 3 Buffer Register
IC3TMR
0156
Input Capture 3 Timer Register
IC4CON1
0158
—
—
ICSIDL
IC4CON2
015A
—
—
—
IC4BUF
015C
Input Capture 4 Buffer Register
xxxx
IC4TMR
015E
Input Capture 4 Timer Register
0000
Bit 11
Bit 10
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
ICTSEL2 ICTSEL1 ICTSEL0
—
—
—
Bit 9
Bit 8
—
—
—
IC32
—
—
—
—
—
—
—
IC32
—
IC32
—
IC32
Bit 7
Bit 6
Bit 5
—
ICI1
ICI0
ICTRIG TRIGSTAT
—
ICI1
ICTRIG TRIGSTAT
—
ICI1
ICTRIG TRIGSTAT
—
ICI1
ICTRIG TRIGSTAT
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
xxxx
0000
ICI0
—
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
DS70005127D-page 47
dsPIC33EPXXGS50X FAMILY
Legend:
Bit 12
SFR
Name
Addr.
OC1CON1 0900
OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP
Bit 15
Bit 14
Bit 13
—
—
OCSIDL
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN
Bit 12
Bit 11
Bit 10
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
Bit 9
Bit 8
—
—
—
OC32
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENFLTA
—
—
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
All
Resets
0000
000C
OC1RS
0904
Output Compare 1 Secondary Register
xxxx
OC1R
0906
Output Compare 1 Register
xxxx
OC1TMR
0908
OC2CON1 090A
Timer Value 1 Register
—
—
OCSIDL
OC2CON2 090C FLTMD FLTOUT FLTTRIEN
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
—
OC32
ENFLTA
—
xxxx
—
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
OC2RS
090E
Output Compare 2 Secondary Register
xxxx
OC2R
0910
Output Compare 2 Register
xxxx
OC2TMR
0912
OC3CON1 0914
Timer Value 2 Register
—
—
OCSIDL
OC3CON2 0916 FLTMD FLTOUT FLTTRIEN
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
—
OC32
ENFLTA
—
xxxx
—
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
OC3RS
0918
Output Compare 3 Secondary Register
xxxx
OC3R
091A
Output Compare 3 Register
xxxx
OC3TMR
091C
OC4CON1 091E
Timer Value 3 Register
—
—
OCSIDL
OC4CON2 0920 FLTMD FLTOUT FLTTRIEN
OCTSEL2 OCTSEL1 OCTSEL0
OCINV
—
—
—
—
—
OC32
ENFLTA
—
xxxx
—
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
0000
000C
OC4RS
0922
Output Compare 4 Secondary Register
xxxx
OC4R
0924
Output Compare 4 Register
xxxx
0926
Timer Value 4 Register
xxxx
OC4TMR
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 48
TABLE 4-6:
2013-2017 Microchip Technology Inc.
2013-2017 Microchip Technology Inc.
TABLE 4-7:
SFR
Name
PWM REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
PTCON
0C00
PTEN
—
PTCON2
0C02
—
—
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
PTSIDL SESTAT SEIEN
EIPU
SYNCPOL
SYNCOEN
SYNCEN
—
—
—
—
PTPER
0C04
SEVTCMP
0C06
MDC
0C0A
STCON
0C0E
—
—
—
STCON2
0C10
—
—
—
STPER
0C12
—
Bit 12
—
—
Bit 6
Bit 5
Bit 4
SYNCSRC2 SYNCSRC1 SYNCSRC0
—
—
—
Bit 3
Bit 2
SEVTPS3
SEVTPS2
—
Bit 1
Bit 0
All
Resets
SEVTPS1
SEVTPS0
0000
PCLKDIV
0000
PWMx Primary Master Time Base Period Register (PTPER)
FFF8
PWMx Special Event Compare Register (SEVTCMP12:0>)
—
—
—
SEVTPS2
SEVTPS1
SEVTPS0
PWMx Master Duty Cycle Register (MDC)
SESTAT SEIEN
—
EIPU
SYNCPOL
SYNCOEN
SYNCEN
—
—
—
—
—
0000
SYNCSRC2 SYNCSRC1 SYNCSRC0
—
—
—
SEVTPS3
—
PCLKDIV
FFF8
PWMx Secondary Special Event Compare Register (SSEVTCMP)
0C1A CHPCLKEN
PWMKEY
0C1E
—
—
—
—
—
CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
—
—
—
0000
—
—
—
0000
PWMx Protection Lock/Unlock Key Register (PWMKEY)
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
SFR
Name
Addr.
PWM GENERATOR 1 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
IOCON1
0C22
FCLCON1
0C24 IFLTMOD CLSRC4
PDC1
0C26
PWM1 Generator Duty Cycle Register (PDC1)
0000
PHASE1
0C28
PWM1 Primary Phase-Shift or Independent Time Base Period Register (PHASE1)
0000
DTR1
0C2A
—
—
PWM1 Dead-Time Register (DTR1)
0000
ALTDTR1
0C2C
—
—
PWM1 Alternate Dead-Time Register (ALTDTR1)
0000
SDC1
0C2E
PWM1 Secondary Duty Cycle Register (SDC1)
SPHASE1
0C30
PWM1 Secondary Phase-Shift Register (SPHASE1)
TRIG1
0C32
TRGCON1
0C34 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
0000
0000
PWM1 Primary Trigger Compare Value Register (TRGCMP)
—
—
—
—
DTM
—
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
DS70005127D-page 49
STRIG1
0C36
PWM1 Secondary Trigger Compare Value Register (STRGCMP)
—
—
—
0000
PWMCAP1
0C38
PWM1 Primary Time Base Capture Register (PWMCAP)
—
—
—
0000
LEBCON1
0C3A
PHR
PHF
PLR
PLF
BPHL
BPLH
BPLL
0000
LEBDLY1
0C3C
—
—
—
—
—
—
—
0000
AUXCON1
0C3E
HRPDIS
HRDDIS
—
—
Legend:
FLTLEBEN
CLLEBEN
—
—
—
—
BCH
PWM1 Leading-Edge Blanking Delay Register (LEB)
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
dsPIC33EPXXGS50X FAMILY
CHOP
0000
0000
PWMx Secondary Master Time Base Period Register (STPER)
SSEVTCMP 0C14
0000
SFR
Name
Addr.
PWMCON2 0C40
PWM GENERATOR 2 REGISTER MAP
Bit 15
FLTSTAT
PENH
Bit 14
Bit 13
Bit 12
CLSTAT TRGSTAT FLTIEN
PENL
POLH
POLL
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
IOCON2
0C42
FCLCON2
0C44 IFLTMOD CLSRC4
PDC2
0C46
PWM2 Generator Duty Cycle Register (PDC2)
0000
PHASE2
0C48
PWM2 Primary Phase-Shift or Independent Time Base Period Register (PHASE2)
0000
DTR2
0C4A
—
—
PWM2 Dead-Time Register (DTR2)
0000
ALTDTR2
0C4C
—
—
PWM2 Alternate Dead-Time Register (ALTDTR2)
0000
SDC2
0C4E
PWM2 Secondary Duty Cycle Register (SDC2)
SPHASE2
0C50
PWM2 Secondary Phase-Shift Register (SPHASE2)
TRIG2
0C52
TRGCON2
0C54 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG2
0C56
CLSRC3 CLSRC2
LEBCON2
0C5A
PHR
PHF
PLR
PLF
LEBDLY2
0C5C
—
—
—
—
AUXCON2
0C5E
HRPDIS
HRDDIS
—
—
—
—
—
—
DTM
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
0000
PWM2 Secondary Trigger Compare Value Register (STRGCMP)
—
—
—
0000
PWM2 Primary Time Base Capture Register (PWMCAP)
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
Bit 0
All
Resets
FLTLEBEN
CLLEBEN
—
—
—
—
BCH
BCL
BPHH
PWM2 Leading-Edge Blanking Delay Register (LEB)
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
Bit 7
Bit 6
DTC1
DTC0
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10:
SFR
Name
0000
PWM2 Primary Trigger Compare Value Register (TRGCMP)
PWMCAP2 0C58
Legend:
0000
Addr.
PWMCON3 0C60
PWM GENERATOR 3 REGISTER MAP
Bit 15
FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
2013-2017 Microchip Technology Inc.
IOCON3
0C62
FCLCON3
0C64 IFLTMOD CLSRC4
PDC3
0C66
PWM3 Generator Duty Cycle Register (PDC3)
0000
PHASE3
0C68
PWM3 Primary Phase-Shift or Independent Time Base Period Register (PHASE3)
0000
DTR3
0C6A
—
—
PWM3 Dead-Time Register (DTR3)
0000
ALTDTR3
0C6C
—
—
PWM3 Alternate Dead-Time Register (ALTDTR3)
0000
SDC3
0C6E
PWM3 Secondary Duty Cycle Register (SDC3)
SPHASE3
0C70
PWM3 Secondary Phase-Shift Register (SPHASE3)
TRIG3
0C72
TRGCON3
0C74 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG3
0C76
0000
PWM3 Primary Trigger Compare Value Register (TRGCMP)
PWMCAP3 0C78
LEBCON3
0C7A
PHR
PHF
PLR
PLF
LEBDLY3
0C7C
—
—
—
—
AUXCON3
0C7E
HRPDIS
HRDDIS
—
—
Legend:
0000
—
—
—
—
DTM
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
0000
PWM3 Secondary Trigger Compare Value Register (STRGCMP)
—
—
—
0000
PWM3 Primary Time Base Capture Register (PWMCAP)
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
FLTLEBEN
CLLEBEN
—
—
—
—
BCH
PWM3 Leading-Edge Blanking Delay Register (LEB)
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 50
TABLE 4-9:
2013-2017 Microchip Technology Inc.
TABLE 4-11:
SFR
Name
Addr.
PWMCON4 0C80
PWM GENERATOR 4 REGISTER MAP
Bit 15
FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
IOCON4
0C82
FCLCON4
0C84 IFLTMOD CLSRC4
PDC4
0C86
PWM4 Generator Duty Cycle Register (PDC4)
0000
PHASE4
0C88
PWM4 Primary Phase-Shift or Independent Time Base Period Register (PHASE4)
0000
DTR4
0C8A
—
—
PWM4 Dead-Time Register (DTR4)
0000
ALTDTR4
0C8C
—
—
PWM4 Alternate Dead-Time Register (ALTDTR4)
0000
SDC4
0C8E
PWM4 Secondary Duty Cycle Register (SDC4)
SPHASE4
0C90
PWM4 Secondary Phase-Shift Register (SPHASE4)
TRIG4
0C92
TRGCON4
0C94 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG4
0C96
0C9A
PHR
PHF
PLR
PLF
LEBDLY4
0C9C
—
—
—
—
AUXCON4
0C9E
HRPDIS
HRDDIS
—
—
—
—
—
—
—
DTM
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
PWM4 Secondary Trigger Compare Value Register (STRGCMP)
—
—
—
0000
PWM4 Primary Time Base Capture Register (PWMCAP)
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
FLTLEBEN
CLLEBEN
—
—
—
—
BCH
BCL
BPHH
PWM4 Leading-Edge Blanking Delay Register (LEB)
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
Bit 7
Bit 6
DTC1
DTC0
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
Addr.
PWM GENERATOR 5 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON5 0CA0 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
C000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
00F8
DS70005127D-page 51
IOCON5
0CA2
FCLCON5
0CA4 IFLTMOD CLSRC4
PDC5
0CA6
PWM5 Generator Duty Cycle Register (PDC5)
0000
PHASE5
0CA8
PWM5 Primary Phase-Shift or Independent Time Base Period Register (PHASE5)
0000
DTR5
0CAA
—
—
PWM5 Dead-Time Register (DTR5)
0000
ALTDTR5
0CAC
—
—
PWM5 Alternate Dead-Time Register (ALTDTR5)
0000
SDC5
0CAE
PWM5 Secondary Duty Cycle Register (SDC5)
SPHASE5
0CB0
PWM5 Secondary Phase-Shift Register (SPHASE5)
TRIG5
0CB2
TRGCON5
0CB4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG5
0CB6
0000
PWM5 Primary Trigger Compare Value Register (TRGCMP)
PWMCAP5 0CB8
LEBCON5
0CBA
PHR
PHF
PLR
PLF
LEBDLY5
0CBC
—
—
—
—
AUXCON5
0CBE HRPDIS
HRDDIS
—
—
Legend:
0000
—
—
—
—
DTM
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
0000
PWM5 Secondary Trigger Compare Value Register (STRGCMP)
—
—
—
0000
PWM5 Primary Time Base Capture Register (PWMCAP)
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
FLTLEBEN
CLLEBEN
—
—
—
—
BCH
PWM5 Leading-Edge Blanking Delay Register (LEB)
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
dsPIC33EPXXGS50X FAMILY
LEBCON4
SFR
Name
0000
PWM4 Primary Trigger Compare Value Register (TRGCMP)
PWMCAP4 0C98
Legend:
0000
SFR
Name
I2C1 AND I2C2 REGISTER MAP
Bit 11
RSEN
SEN
1000
AHEN
DHEN
0000
RBF
TBF
0000
Bit 14
Bit 13
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
I2C1CONL
0200
I2CEN
—
I2CSIDL
I2C1CONH
0202
—
—
—
—
—
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
—
—
—
—
PCIE
SCIE
BOEN
I2C1STAT
0204
ACKTIM
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
I2C1ADD
0206
—
—
—
I2C1MSK
0208
—
—
—
—
—
—
I2C1 Address Register
0000
—
—
—
I2C1 Slave Mode Address Mask Register
I2C1BRG
020A
0000
I2C1TRN
020C
—
—
—
—
—
—
—
—
I2C1 Transmit Register
I2C1RCV
020E
—
—
—
—
—
—
—
—
I2C1 Receive Register
I2C2CON1
0210
I2CEN
—
I2CSIDL
A10M
DISSLW
SMEN
I2C2CON2
0212
—
—
I2C2STAT
0214
I2C2ADD
0216
—
I2C2MSK
0218
—
I2C2BRG
021A
I2C2TRN
021C
—
—
—
—
—
—
—
—
I2C2 Transmit Register
00FF
I2C2RCV
021E
—
—
—
—
—
—
—
—
I2C2 Receive Register
0000
SCLREL STRICT
Bit 3
All
Resets
Bit 15
ACKSTAT TRSTAT
Bit 12
Bit 0
Addr.
Bit 2
Bit 1
RCEN
PEN
SDAHT
SBCDE
R_W
Baud Rate Generator Register
SCLREL STRICT
GCEN
0000
00FF
0000
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
—
—
—
—
—
—
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
0000
ACKTIM
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
—
—
—
—
—
I2C2 Address Register
0000
—
—
—
—
—
I2C2 Slave Mode Address Mask Register
0000
ACKSTAT TRSTAT
Baud Rate Generator Register
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
UART1 AND UART2 REGISTER MAP
2013-2017 Microchip Technology Inc.
SFR
Name
Addr.
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
U1TXREG
0224
—
U1RXREG 0226
—
Bit 15
Bit 14
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 12
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
WAKE
LPBACK
—
—
—
—
—
—
UART1 Transmit Register
xxxx
—
—
—
—
—
—
UART1 Receive Register
0000
URXISEL1 URXISEL0
Bit 0
All
Resets
Bit 13
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
U1BRG
0228
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U2TXREG
0234
—
—
—
—
—
—
—
UART2 Transmit Register
xxxx
U2RXREG 0236
—
—
—
—
—
—
—
UART2 Receive Register
0000
U2BRG
0238
Baud Rate Generator Prescaler Register
WAKE
LPBACK
URXISEL1 URXISEL0
Baud Rate Generator Prescaler Register
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 52
TABLE 4-13:
2013-2017 Microchip Technology Inc.
TABLE 4-15:
SPI1 AND SPI2 REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
SPI1CON1
0242
—
—
—
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
SPI1BUF
0248
SPI2STAT
0260
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
SPIBEC2
SPIBEC1
SPIBEC0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
0000
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
FRMDLY SPIBEN
0000
SPITBF
SPIRBF
0000
PPRE1
PPRE0
0000
FRMDLY SPIBEN
0000
DISSCK DISSDO MODE16
—
—
—
SPI1 Transmit and Receive Buffer Register
SPIEN
—
SPISIDL
SPI2CON1
0262
—
—
—
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
SPI2BUF
0268
All
Resets
Bit 12
—
—
SPIBEC2
DISSCK DISSDO MODE16
—
—
—
0000
SPIBEC1
SPIBEC0
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
—
—
—
—
—
—
—
—
SPI2 Transmit and Receive Buffer Register
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 53
SFR
Name
ADC REGISTER MAP
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
0000
SHRRES1
SHRRES0
—
—
—
—
—
0060
SHRADCS6
SHRADCS5
SHRADCS4
SHRADCS3
SHRADCS2
SHRADCS1
SHRADCS0
0000
SHRSAMC8
SHRSAMC7 SHRSAMC6
SHRSAMC5
SHRSAMC4
SHRSAMC3
SHRSAMC2
SHRSAMC1
SHRSAMC0
0000
SHRSAMP
CNVRTCH
SWLCTRG
SWCTRG
CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0
0000
CLKDIV2
CLKDIV1
CLKDIV0
SHREN
—
—
—
C3EN
C2EN
C1EN
C0EN
0000
SYNCTRG3
SYNCTRG2
SYNCTRG1
SYNCTRG0
—
—
—
—
SAMC3EN
SAMC2EN
SAMC1EN
SAMC0EN
0000
—
—
—
—
—
C3CHS1
C3CHS0
C2CHS1
C2CHS0
C1CHS1
C1CHS0
C0CHS1
C0CHS0
0000
DIFF6
SIGN6
DIFF5
SIGN5
DIFF3
SIGN4
DIFF3
SIGN3
DIFF2
SIGN2
DIFF1
SIGN1
DIFF0
SIGN0
0000
SIGN15(1)
DIFF14(2)
SIGN14(2)
DIFF13(1)
SIGN13(1)
DIFF12(2)
SIGN12(2)
DIFF11(2)
SIGN11(2)
DIFF10(2)
SIGN10(2)
DIFF9(2)
SIGN9(2)
DIFF8(2)
SIGN8(2)
0000
—
—
—
—
DIFF21
SIGN21
DIFF20
SIGN20
DIFF19
SIGN19
DIFF18
SIGN18
DIFF17(2)
SIGN17(2)
DIFF16(1)
SIGN16(1)
0000
0320
IE15(1)
IE14(2)
IE13(1)
IE12(2)
IE11(2)
IE10(2)
IE9(2)
IE8(2)
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
0000
ADIEH
0322
—
—
—
—
—
—
—
—
—
—
IE21
IE20
IE19
IE18
IE17(2)
IE16(1)
0000
ADSTATL
0330 AN15RDY(1) AN14RDY(2) AN13RDY(1) AN12RDY(2)
AN11RDY(2)
AN10RDY(2)
AN9RDY(2)
AN8RDY(2)
AN7RDY
AN6RDY
AN5RDY
AN4RDY
AN3RDY
AN2RDY
AN1RDY
AN0RDY
0000
ADSTATH
0332
—
—
—
—
—
—
AN21RDY
AN20RDY
AN19RDY
AN18RDY
AN17RDY(2)
AN16RDY(1)
0000
ADCMP0ENL
0338 CMPEN15(1) CMPEN14(2) CMPEN13(1) CMPEN12(2) CMPEN11(2)
CMPEN10(2)
CMPEN9(2)
CMPEN8(2)
CMPEN7
CMPEN6
CMPEN5
CMPEN4
CMPEN3
CMPEN2
CMPEN1
CMPEN0
0000
—
—
—
—
—
CMPEN21
CMPEN20
CMPEN19
CMPEN18
CMPEN17(2)
CMPEN16(1)
0000
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON1L
0300
ADON
—
ADSIDL
—
—
—
—
—
—
ADCON1H
0302
—
—
—
—
—
—
—
—
FORM
ADCON2L
0304
REFCIE
REFERCIE
—
EIEN
—
SHREISEL2
SHREISEL1
SHREISEL0
—
ADCON2H
0306
REFRDY
REFERR
—
—
—
—
SHRSAMC9
ADCON3L
0308
REFSEL2
REFSEL1
REFSEL0
SUSPEND
SUSPCIE
SUSPRDY
ADCON3H
030A
CLKSEL1
CLKSEL0
CLKDIV5
CLKDIV4
CLKDIV3
ADCON4L
030C
—
—
—
—
ADCON4H
030E
—
—
—
ADMOD0L
0310
DIFF7
SIGN7
ADMOD0H
0312
DIFF15(1)
ADMOD1L
0314
ADIEL
ADCMP0ENH 033A
—
—
—
—
—
—
—
—
—
Bit 7
Bit 6
ADCMP0LO
033C
ADC Comparator 0 Low Value Register
ADCMP0HI
033E
ADC Comparator 0 High Value Register
ADCMP1ENL
0340 CMPEN15(1) CMPEN14(2) CMPEN13(1) CMPEN12(2) CMPEN11(2)
ADCMP1ENH 0342
—
—
—
—
0000
0000
CMPEN10(2)
CMPEN9(2)
CMPEN8(2)
CMPEN7
CMPEN6
CMPEN5
CMPEN4
CMPEN3
CMPEN2
CMPEN1
CMPEN0
0000
—
—
—
—
—
CMPEN21
CMPEN20
CMPEN19
CMPEN18
CMPEN17(2)
CMPEN16(1)
0000
—
2013-2017 Microchip Technology Inc.
ADCMP1LO
0344
ADC Comparator 1 Low Value Register
0000
ADCMP1HI
0346
ADC Comparator 1 High Value Register
0000
ADFLDAT
0368
ADC Filter 0 Results Data Register
ADFL1CON
036A
ADFL1DAT
0368
ADFL0CON
036A
FLEN
MODE1
MODE0
ADTRIG0L
0380
—
—
—
ADTRIG0H
0382
—
—
ADTRIG1L
0384
—
ADTRIG1H
0386
ADTRIG2L
MODE1
MODE0
OVRSAM2
OVRSAM1
OVRSAM0
IE
RDY
—
0000
—
—
FLCHSEL4
FLCHSEL3
FLCHSEL2
FLCHSEL1
FLCHSEL0
—
—
—
FLCHSEL4
FLCHSEL3
FLCHSEL2
FLCHSEL1
FLCHSEL0
TRGSRC1
—
—
—
TRGSRC0
0000
—
TRGSRC3
—
—
—
TRGSRC2
0000
—
—
TRGSRC5
—
—
—
TRGSRC4
0000
—
—
—
TRGSRC7
—
—
—
TRGSRC6
0000
0388
—
—
—
TRGSRC9
—
—
—
TRGSRC8
0000
ADTRIG2H
038A
—
—
—
TRGSRC11
—
—
—
TRGSRC10
0000
ADTRIG3L
038C
—
—
—
TRGSRC13
—
—
—
TRGSRC12
0000
ADTRIG3H
038E
—
—
—
TRGSRC15
—
—
—
TRGSRC14
0000
ADTRIG4L
0390
—
—
—
TRGSRC17
—
—
—
TRGSRC16
0000
ADTRIG4H
0392
—
—
—
TRGSRC19
—
—
—
TRGSRC18
0000
ADTRIG5L
0394
—
—
—
TRGSRC21
—
—
—
TRGSRC20
ADCMP0CON 03A0
—
—
—
CHNL4
CHNL3
CHNL2
CHNL1
CHNL0
CMPEN
IE
STAT
BTWN
HIHI
HILO
LOHI
LOLO
0000
ADCMP1CON 03A4
—
—
—
CHNL4
CHNL3
CHNL2
CHNL1
CHNL0
CMPEN
IE
STAT
BTWN
HIHI
HILO
LOHI
LOLO
0000
Legend:
Note 1:
2:
FLEN
ADC Filter 1 Results Data Register
OVRSAM2
OVRSAM1
OVRSAM0
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Implemented on dsPIC33EPXXGS506 devices only.
Implemented on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices only.
IE
RDY
0000
0000
0000
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 54
TABLE 4-16:
2013-2017 Microchip Technology Inc.
TABLE 4-16:
SFR
Name
ADC REGISTER MAP (CONTINUED)
Bit 3
Bit 2
LVLEN1
LVLEN0
0000
LVLEN17(2)
LVLEN16(1)
0000
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 1
ADLVLTRGL
03D0
LVLEN15(1)
LVLEN14
LVLEN13(1)
LVLEN12(2)
LVLEN11(2)
LVLEN10(2)
LVLEN9(2)
LVLEN8(2)
LVLEN7
LVLEN6
LVLEN5
LVLEN4
LVLEN3
LVLEN2
ADLVLTRGH
03D2
—
—
—
—
—
—
—
—
—
—
LVLEN21
LVLEN20
LVLEN19
LVLEN18
ADCORE0L
03D4
—
—
—
—
—
—
ADCORE0H
03D6
—
—
—
EISEL2
EISEL1
EISEL0
ADCS3
ADCS2
ADCS1
ADCS0
ADCORE1L
03D8
—
—
—
—
—
—
ADCORE1H
03DA
—
—
—
EISEL2
EISEL1
EISEL0
ADCS3
ADCS2
ADCS1
ADCS0
ADCORE2L
03DC
—
—
—
—
—
—
ADCORE2H
03DE
—
—
—
EISEL2
EISEL1
EISEL0
ADCS3
ADCS2
ADCS1
ADCS0
ADCORE3L
03E0
—
—
—
—
—
—
ADCORE3H
03E2
—
—
—
EISEL2
EISEL1
EISEL0
RES1
RES0
—
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
0000
ADEIEL
03F0
EIEN15(1)
EIEN14(2)
EIEN13(1)
EIEN12(2)
EIEN11(2)
EIEN10(2)
EIEN9(2)
EIEN8(2)
EIEN7
EIEN6
EIEN5
EIEN4
EIEN3
EIEN2
EIEN1
EIEN0
0000
ADEIEH
03F2
—
—
—
—
—
—
—
—
—
—
EIEN21
EIEN20
EIEN19
EIEN18
EIEN17(2)
EIEN16(1)
0000
ADEISTATL
03F8 EISTAT15(1) EISTAT14(2) EISTAT13(1) EISTAT12(2)
EISTAT11(2)
EISTAT10(2)
EISTAT9(2)
EISTAT8(2)
EISTAT7
EISTAT6
EISTAT5
EISTAT4
EISTAT3
EISTAT2
EISTAT1
EISTAT0
0000
ADEISTATH
03FA
—
—
—
—
—
—
—
—
—
—
EISTAT21
EISTAT20
EISTAT19
EISTAT18
EISTAT17(2)
EISTAT16(1)
0000
ADCON5L
0400
SHRRDY
—
—
—
C3RDY
C2RDY
C1RDY
C0RDY
SHRPWR
—
—
—
C3PWR
C2PWR
C1PWR
C0PWR
0000
ADCON5H
0402
—
—
—
—
SHRCIE
—
—
—
C3CIE
C2CIE
C1CIE
C0CIE
0000
ADCAL0L
0404
CAL1RDY
—
—
—
—
CAL1DIFF
CAL1EN
CAL1RUN
CAL0RDY
—
—
—
—
CAL0DIFF
CAL0EN
CAL0RUN
0000
ADCAL0H
0406
CAL3RDY
—
—
—
—
CAL3DIFF
CAL3EN
CAL3RUN
CAL2RDY
—
—
—
—
CAL2DIFF
CAL2EN
CAL2RUN
0000
ADCAL1H
040A
CSHRRDY
—
—
—
—
CSHRDIFF
CSHREN
CSHRRUN
—
—
—
—
—
—
—
—
0000
ADCBUF0
040C
ADC Data Buffer 0
0000
ADCBUF1
040E
ADC Data Buffer 1
0000
ADCBUF2
0410
ADC Data Buffer 2
0000
ADCBUF3
0412
ADC Data Buffer 3
0000
ADCBUF4
0414
ADC Data Buffer 4
0000
ADCBUF5
0416
ADC Data Buffer 5
0000
ADCBUF6
041B
ADC Data Buffer 6
0000
ADCBUF7
041A
ADC Data Buffer 7
0000
ADCBUF8
041C
ADC Data Buffer 8
0000
ADCBUF9
041E
ADC Data Buffer 9
0000
ADCBUF10
0420
ADC Data Buffer 10
0000
ADCBUF11
0422
ADC Data Buffer 11
0000
ADCBUF12
0424
ADC Data Buffer 12
0000
ADCBUF13
0426
ADC Data Buffer 13
0000
ADCBUF14
0428
ADC Data Buffer 14
0000
ADCBUF15
042A
ADC Data Buffer 15
0000
ADCBUF16
042C
ADC Data Buffer 16
0000
ADCBUF17
042E
ADC Data Buffer 17
0000
ADCBUF18
0430
ADC Data Buffer 18
0000
ADCBUF19
0432
ADC Data Buffer 19
0000
ADCBUF20
0434
ADC Data Buffer 20
0000
ADCBUF21
0436
ADC Data Buffer 21
0000
SAMC
RES1
RES0
—
ADCS6
ADCS5
0000
ADCS4
SAMC
RES1
RES0
—
ADCS6
ADCS5
0000
ADCS4
SAMC
RES1
RES0
—
ADCS6
ADCS5
0000
0000
ADCS4
SAMC
WARMTIME3 WARMTIME2 WARMTIME1 WARMTIME0
0000
0000
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 55
Bit 14
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Implemented on dsPIC33EPXXGS506 devices only.
Implemented on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices only.
Bit 4
All
Resets
Bit 15
Legend:
Note 1:
2:
Bit 5
Bit 0
Addr.
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXGS502 DEVICES
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RPOR0
0670
—
—
RP33R5
RP33R4
RP33R3
RP33R2
RP33R1
RP33R0
—
—
RP32R5
RP32R4
RP32R3
RP32R2
RP32R1
RP32R0
0000
RPOR1
0672
—
—
RP35R5
RP35R4
RP35R3
RP35R2
RP35R1
RP35R0
—
—
RP34R5
RP34R4
RP34R3
RP34R2
RP34R1
RP34R0
0000
RPOR2
0674
—
—
RP37R5
RP37R4
RP37R3
RP37R2
RP37R1
RP37R0
—
—
RP36R5
RP36R4
RP36R3
RP36R2
RP36R1
RP36R0
0000
RPOR3
0676
—
—
RP39R5
RP39R4
RP39R3
RP39R2
RP39R1
RP39R0
—
—
RP38R5
RP38R4
RP38R3
RP38R2
RP38R1
RP38R0
0000
RPOR4
0678
—
—
RP41R5
RP41R4
RP41R3
RP41R2
RP41R1
RP41R0
—
—
RP40R5
RP40R4
RP40R3
RP40R2
RP40R1
RP40R0
0000
RPOR5
067A
—
—
RP43R5
RP43R4
RP43R3
RP43R2
RP43R1
RP43R0
—
—
RP42R5
RP42R4
RP42R3
RP42R2
RP42R1
RP42R0
0000
RPOR6
067C
—
—
RP45R5
RP45R4
RP45R3
RP45R2
RP45R1
RP45R0
—
—
RP44R5
RP44R4
RP44R3
RP44R2
RP44R1
RP44R0
0000
RPOR7
067E
—
—
RP47R5
RP47R4
RP47R3
RP47R2
RP47R1
RP47R0
—
—
RP46R5
RP46R4
RP46R3
RP46R2
RP46R1
RP46R0
0000
RPOR16
0690
—
—
RP177R5
RP177R4
RP177R3 RP177R2
RP177R1
RP177R0
—
—
RP176R5
RP176R4
RP176R3
RP176R2
RP176R1
RP176R0
0000
RPOR17
0692
—
—
RP179R5
RP179R4
RP179R3 RP179R2
RP179R1
RP179R0
—
—
RP178R5
RP178R4
RP178R3
RP178R2
RP178R1
RP178R0
0000
RPOR18
0694
—
—
RP181R5
RP181R4
RP181R3 RP181R2
RP181R1
RP181R0
—
—
RP180R5
RP180R4
RP180R3
RP180R2
RP180R1
RP180R0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES
2013-2017 Microchip Technology Inc.
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RPOR0
0670
—
—
RP33R5
RP33R4
RP33R3
RP33R2
RP33R1
RP33R0
—
—
RP32R5
RP32R4
RP32R3
RP32R2
RP32R1
RP32R0
0000
RPOR1
0672
—
—
RP35R5
RP35R4
RP35R3
RP35R2
RP35R1
RP35R0
—
—
RP34R5
RP34R4
RP34R3
RP34R2
RP34R1
RP34R0
0000
RPOR2
0674
—
—
RP37R5
RP37R4
RP37R3
RP37R2
RP37R1
RP37R0
—
—
RP36R5
RP36R4
RP36R3
RP36R2
RP36R1
RP36R0
0000
RPOR3
0676
—
—
RP39R5
RP39R4
RP39R3
RP39R2
RP39R1
RP39R0
—
—
RP38R5
RP38R4
RP38R3
RP38R2
RP38R1
RP38R0
0000
RPOR4
0678
—
—
RP41R5
RP41R4
RP41R3
RP41R2
RP41R1
RP41R0
—
—
RP40R5
RP40R4
RP40R3
RP40R2
RP40R1
RP40R0
0000
RPOR5
067A
—
—
RP43R5
RP43R4
RP43R3
RP43R2
RP43R1
RP43R0
—
—
RP42R5
RP42R4
RP42R3
RP42R2
RP42R1
RP42R0
0000
RPOR6
067C
—
—
RP45R5
RP45R4
RP45R3
RP45R2
RP45R1
RP45R0
—
—
RP44R5
RP44R4
RP44R3
RP44R2
RP44R1
RP44R0
0000
RPOR7
067E
—
—
RP47R5
RP47R4
RP47R3
RP47R2
RP47R1
RP47R0
—
—
RP46R5
RP46R4
RP46R3
RP46R2
RP46R1
RP46R0
0000
RPOR8
0680
—
—
RP49R5
RP49R4
RP49R3
RP49R2
RP49R1
RP49R0
—
—
RP48R5
RP48R4
RP48R3
RP48R2
RP48R1
RP48R0
0000
RPOR9
0682
—
—
RP51R5
RP51R4
RP51R3
RP51R2
RP51R1
RP51R0
—
—
RP50R5
RP50R4
RP50R3
RP50R2
RP50R1
RP50R0
0000
RPOR10
0684
—
—
RP53R5
RP53R4
RP53R3
RP53R2
RP53R1
RP53R0
—
—
RP52R5
RP52R4
RP52R3
RP52R2
RP52R1
RP52R0
0000
RPOR11
0686
—
—
RP55R5
RP55R4
RP55R3
RP55R2
RP55R1
RP55R0
—
—
RP54R5
RP54R4
RP54R3
RP54R2
RP54R1
RP54R0
0000
RPOR12
0688
—
—
RP57R5
RP57R4
RP57R3
RP57R2
RP57R1
RP57R0
—
—
RP56R5
RP56R4
RP56R3
RP56R2
RP56R1
RP56R0
0000
RPOR13
068A
—
—
RP59R5
RP59R4
RP59R3
RP59R2
RP59R1
RP59R0
—
—
RP58R5
RP58R4
RP58R3
RP58R2
RP58R1
RP58R0
0000
RPOR14
068C
—
—
RP61R5
RP61R4
RP61R3
RP61R2
RP61R1
RP61R0
—
—
RP60R5
RP60R4
RP60R3
RP60R2
RP60R1
RP60R0
0000
RPOR16
0690
—
—
RP177R5
RP177R4
RP177R3 RP177R2 RP177R1
RP177R0
—
—
RP176R5
RP176R4
RP176R3
RP176R2
RP176R1
RP176R0
0000
RPOR17
0692
—
—
RP179R5
RP179R4
RP179R3 RP179R2 RP179R1
RP179R0
—
—
RP178R5
RP178R4
RP178R3
RP178R2
RP178R1
RP178R0
0000
RPOR18
0694
—
—
RP181R5
RP181R4
RP181R3 RP181R2 RP181R1
RP181R0
—
—
RP180R5
RP180R4
RP180R3
RP180R2
RP180R1
RP180R0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 56
TABLE 4-17:
2013-2017 Microchip Technology Inc.
TABLE 4-19:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RPOR0
0670
—
—
RP33R5
RP33R4
RP33R3
RP33R2
RP33R1
RP33R0
—
—
RP32R5
RP32R4
RP32R3
RP32R2
RP32R1
RP32R0
0000
RPOR1
0672
—
—
RP35R5
RP35R4
RP35R3
RP35R2
RP35R1
RP35R0
—
—
RP34R5
RP34R4
RP34R3
RP34R2
RP34R1
RP34R0
0000
RPOR2
0674
—
—
RP37R5
RP37R4
RP37R3
RP37R2
RP37R1
RP37R0
—
—
RP36R5
RP36R4
RP36R3
RP36R2
RP36R1
RP36R0
0000
RPOR3
0676
—
—
RP39R5
RP39R4
RP39R3
RP39R2
RP39R1
RP39R0
—
—
RP38R5
RP38R4
RP38R3
RP38R2
RP38R1
RP38R0
0000
RPOR4
0678
—
—
RP41R5
RP41R4
RP41R3
RP41R2
RP41R1
RP41R0
—
—
RP40R5
RP40R4
RP40R3
RP40R2
RP40R1
RP40R0
0000
RPOR5
067A
—
—
RP43R5
RP43R4
RP43R3
RP43R2
RP43R1
RP43R0
—
—
RP42R5
RP42R4
RP42R3
RP42R2
RP42R1
RP42R0
0000
RPOR6
067C
—
—
RP45R5
RP45R4
RP45R3
RP45R2
RP45R1
RP45R0
—
—
RP44R5
RP44R4
RP44R3
RP44R2
RP44R1
RP44R0
0000
RPOR7
067E
—
—
RP47R5
RP47R4
RP47R3
RP47R2
RP47R1
RP47R0
—
—
RP46R5
RP46R4
RP46R3
RP46R2
RP46R1
RP46R0
0000
RPOR8
0680
—
—
RP49R5
RP49R4
RP49R3
RP49R2
RP49R1
RP49R0
—
—
RP48R5
RP48R4
RP48R3
RP48R2
RP48R1
RP48R0
0000
RPOR9
0682
—
—
RP51R5
RP51R4
RP51R3
RP51R2
RP51R1
RP51R0
—
—
RP50R5
RP50R4
RP50R3
RP50R2
RP50R1
RP50R0
0000
RPOR10
0684
—
—
RP53R5
RP53R4
RP53R3
RP53R2
RP53R1
RP53R0
—
—
RP52R5
RP52R4
RP52R3
RP52R2
RP52R1
RP52R0
0000
RPOR11
0686
—
—
RP55R5
RP55R4
RP55R3
RP55R2
RP55R1
RP55R0
—
—
RP54R5
RP54R4
RP54R3
RP54R2
RP54R1
RP54R0
0000
RPOR12
0688
—
—
RP57R5
RP57R4
RP57R3
RP57R2
RP57R1
RP57R0
—
—
RP56R5
RP56R4
RP56R3
RP56R2
RP56R1
RP56R0
0000
RPOR13
068A
—
—
RP59R5
RP59R4
RP59R3
RP59R2
RP59R1
RP59R0
—
—
RP58R5
RP58R4
RP58R3
RP58R2
RP58R1
RP58R0
0000
RPOR14
068C
—
—
RP61R5
RP61R4
RP61R3
RP61R2
RP61R1
RP61R0
—
—
RP60R5
RP60R4
RP60R3
RP60R2
RP60R1
RP60R0
0000
RPOR15
068E
—
—
RP63R5
RP63R4
RP63R3
RP63R2
RP63R1
RP63R0
—
—
RP62R5
RP62R4
RP62R3
RP62R2
RP62R1
RP62R0
0000
RPOR16
0690
—
—
RP177R5 RP177R4 RP177R3
RP177R2
RP177R1
RP177R0
—
—
RP176R5
RP176R4
RP176R3
RP176R2
RP176R1
RP176R0
0000
RPOR17
0692
—
—
RP179R5 RP179R4 RP179R3
RP179R2
RP179R1
RP179R0
—
—
RP178R5
RP178R4
RP178R3
RP178R2
RP178R1
RP178R0
0000
RPOR18
0694
—
—
RP181R5 RP181R4 RP181R3
RP181R2
RP181R1
RP181R0
—
—
RP180R5
RP180R4
RP180R3
RP180R2
RP180R1
RP180R0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70005127D-page 57
dsPIC33EPXXGS50X FAMILY
SFR
Name
PERIPHERAL PIN SELECT INPUT REGISTER MAP
SFR
Name
Addr.
RPINR0
06A0
RPINR1
06A2
RPINR2
06A4
RPINR3
06A6
T3CKR7
T3CKR6
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
RPINR7
06AE
IC2R7
IC2R6
IC2R5
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
IC1R7
IC1R6
RPINR8
06B0
IC4R7
IC4R6
IC4R5
IC4R4
IC4R3
IC4R2
IC4R1
IC4R0
IC3R7
IC3R6
RPINR11 06B6
—
—
—
—
—
—
—
—
RPINR12 06B8
FLT2R7
FLT2R6
FLT2R5
FLT2R4
FLT2R3
FLT2R2
FLT2R1
FLT2R0
FLT1R7
FLT1R6
FLT1R5
FLT1R4
RPINR13 06BA
FLT4R7
FLT4R6
FLT4R5
FLT4R4
FLT4R3
FLT4R2
FLT4R1
FLT4R0
FLT3R7
FLT3R6
FLT3R5
U1CTS0
Bit 15
Bit 14
Bit 13
Bit 12
—
—
—
—
Bit 11
Bit 10
Bit 9
Bit 8
—
—
—
INT1R
—
T1CKR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
—
0000
INT2R
—
—
—
0000
—
—
—
—
—
0000
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
0000
IC1R5
IC1R4
IC1R3
IC1R2
IC1R1
IC1R0
0000
IC3R5
IC3R4
IC3R3
IC3R2
IC3R1
IC3R0
0000
FLT1R3
FLT1R2
FLT1R1
FLT1R0
0000
FLT3R4
FLT3R3
FLT3R2
FLT3R1
FLT3R0
0000
T2CKR7 T2CKR6 T2CKR5
OCFAR
0000
RPINR18 06C4 U1CTSR7
U1CTSR6 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1
U1RXR7 U1RXR6 U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
0000
RPINR19 06C6 U2CTSR7
U2CTSR6 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 U2RXR7 U2RXR6 U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
0000
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
0000
SDI2R2
SDI2R1
SDI2R0
—
—
—
RPINR20 06C8 SCK1INR7 SCK1INR6 SCK1INR5 SCK1INR4 SCK1INR3 SCK1INR2 SCK1INR1 SCK1INR0 SDI1R7
RPINR21 06CA
—
—
—
—
—
—
—
—
—
—
RPINR37 06EA
—
—
—
—
SDI1R5
—
SS1R
RPINR22 06CC SCK2INR7 SCK2INR6 SCK2INR5 SCK2INR4 SCK2INR3 SCK2INR2 SCK2INR1 SCK2INR0 SDI2R7
RPINR23 06CE
SDI1R6
SDI2R6
SDI2R5
—
SYNCI1R
SDI2R4
SDI2R3
0000
SS2R
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
RPINR42 06F4
FLT6R7
FLT6R6
FLT6R5
FLT6R4
FLT6R3
FLT6R2
FLT6R1
FLT6R0
FLT5R7
FLT5R6
FLT5R5
FLT5R4
FLT5R3
FLT5R2
FLT5R1
FLT5R0
0000
RPINR43 06F6
FLT8R7
FLT8R6
FLT8R5
FLT8R4
FLT8R3
FLT8R2
FLT8R1
FLT8R0
FLT7R7
FLT7R6
FLT7R5
FLT7R4
FLT7R3
FLT7R2
FLT7R1
FLT7R0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SYNCI2R
0000
RPINR38 06EC
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 58
TABLE 4-20:
2013-2017 Microchip Technology Inc.
2013-2017 Microchip Technology Inc.
TABLE 4-21:
SFR
Name
NVM REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
NVMCON
0728
WR
WREN
WRERR
NVMADR
072A
Bit 12
Bit 11
NVMSIDL SFTSWP
Bit 10
Bit 9
P2ACTIV
RPDF
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
URERR
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
NVMOP3 NVMOP2 NVMOP1 NVMOP0
NVMADR
All
Resets
0000
0000
NVMADRU
072C
—
—
—
—
—
—
—
—
NVMADR
0000
NVMKEY
072E
—
—
—
—
—
—
—
—
NVMKEY
0000
NVMSRCADR
0730
NVMSRCADRH 0732
—
—
—
—
NVM Source Data Address Register, Lower Word (NVMSRCADR)
0000
—
0000
—
—
—
NVM Source Data Address Register, Upper Byte (NVMSRCADR
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22:
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RCON
0740
—
—
VREGSF
—
CM
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
OSCCON
0742
—
COSC2
COSC1
COSC0
—
NOSC2
NOSC1
NOSC0
CLKLOCK
IOLOCK
LOCK
—
CF
—
—
CLKDIV
0744
ROI
DOZE2
DOZE1
DOZE0
DOZEN
FRCDIV2
FRCDIV1
FRCDIV0
PLLFBD
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
LFSR
074C
—
REFOCON 074E
TRAPR IOPUWR
ROON
PLLPOST1 PLLPOST0
—
Bit 0
All
Resets
POR
Note 1
OSWEN Note 2
PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
PLLDIV
—
—
—
TUN
0000
LFSR
—
ROSSLP ROSEL RODIV3
ACLKCON 0750 ENAPLL APLLCK SELACLK
—
—
RODIV2
RODIV1
RODIV0
—
APSTSCLR2 APSTSCLR1 APSTSCLR0 ASRCSEL
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the Configuration fuses.
3040
0030
0000
—
—
—
—
—
—
—
0000
FRCSEL
—
—
—
—
—
—
2740
DS70005127D-page 59
dsPIC33EPXXGS50X FAMILY
SFR
Name
SYSTEM CONTROL REGISTER MAP
SFR
Addr.
Name
PMD REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0760
T5MD
T4MD
T3MD
T2MD
T1MD
—
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
—
—
ADCMD
0000
PMD2
0762
—
—
—
—
IC4MD
IC3MD
IC2MD
IC1MD
—
—
—
—
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0764
—
—
—
—
—
CMPMD
—
—
—
—
—
—
—
—
I2C2MD
—
0000
PMD4
0766
—
—
—
—
—
—
—
—
—
—
—
—
REFOMD
—
—
—
0000
PMD6
076A
—
—
—
PMD7
076C
—
—
—
—
PMD8
076E
—
—
—
—
PWM5MD PWM4MD
PWM3MD
PWM2MD PWM1MD
—
—
—
—
—
—
—
—
0000
CMP4MD
CMP3MD
CMP2MD CMP1MD
—
—
—
—
—
—
PGA1MD
—
0000
—
PGA2MD
—
—
—
—
—
—
CCSMD
—
0000
Bit 0
All
Resets
ABGMD
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24:
CONSTANT-CURRENT SOURCE REGISTER MAP
SFR
Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
ISRCCON
0500
ISRCEN
—
—
—
—
OUTSEL2
OUTSEL1
OUTSEL0
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ISRCCAL5 ISRCCAL4 ISRCCAL3 ISRCCAL2 ISRCCAL1 ISRCCAL0
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25:
SFR
Name
Addr.
PGA1CON 0504
PGA1CAL
0506
PGA2CON 0508
PGA2CAL
050A
PROGRAMMABLE GAIN AMPLIFIER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
PGAEN
PGAOEN
SELPI2
SELPI1
SELPI0
SELNI2
SELNI1
SELNI0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PGAEN
PGAOEN
SELPI2
SELPI1
SELPI0
SELNI2
SELNI1
SELNI0
—
—
—
—
—
—
—
—
—
—
—
—
2013-2017 Microchip Technology Inc.
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 3
Bit 2
Bit 1
Bit 0
—
GAIN2
GAIN1
GAIN0
PGACAL
—
—
—
GAIN2
PGACAL
All
Resets
0000
0000
GAIN1
GAIN0
0000
0000
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 60
TABLE 4-23:
2013-2017 Microchip Technology Inc.
TABLE 4-26:
SFR
Name
Addr.
ANALOG COMPARATOR REGISTER MAP
Bit 15
Bit 14
CMP1CON
0540 CMPON
—
CMP1DAC
0542
—
CMP2CON
0544 CMPON
—
CMP2DAC
0546
—
CMP3CON
0548 CMPON
—
CMP3DAC
054A
—
CMP4CON
054C CMPON
—
CMP4DAC
054E
—
—
—
—
—
Bit 13
Bit 12
Bit 11
CMPSIDL HYSSEL1 HYSSEL0
—
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTREN
FCLKSEL
DACOE
INSEL1
INSEL0
EXTREF
HYSPOL
CMPSTAT
ALTINP
CMPPOL
RANGE
0000
HYSPOL
CMPSTAT
ALTINP
CMPPOL
RANGE
0000
HYSPOL
CMPSTAT
ALTINP
CMPPOL
RANGE
0000
HYSPOL
CMPSTAT
ALTINP
CMPPOL
RANGE
0000
—
CMREF
CMPSIDL HYSSEL1 HYSSEL0
—
FLTREN
FCLKSEL
DACOE
INSEL1
INSEL0
FLTREN
FCLKSEL
DACOE
INSEL1
INSEL0
FLTREN
FCLKSEL
DACOE
INSEL1
INSEL0
—
—
EXTREF
0000
CMREF
CMPSIDL HYSSEL1 HYSSEL0
—
0000
CMREF
CMPSIDL HYSSEL1 HYSSEL0
—
EXTREF
—
EXTREF
0000
CMREF
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
JTAG INTERFACE REGISTER MAP
SFR
Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
JDATAH
0FF0
—
—
—
—
JDATAL
0FF2
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
JDATAH
JDATAL
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
0000
DS70005127D-page 61
dsPIC33EPXXGS50X FAMILY
TABLE 4-27:
SFR
Name
PORTA REGISTER MAP FOR dsPIC33EPXXGS502 DEVICES
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
TRISA
0E00
—
—
—
—
—
—
—
—
—
—
—
TRISA
001F
PORTA
0E02
—
—
—
—
—
—
—
—
—
—
—
RA
0000
LATA
0E04
—
—
—
—
—
—
—
—
—
—
—
LATA
0000
ODCA
0E06
—
—
—
—
—
—
—
—
—
—
—
ODCA
0000
CNENA
0E08
—
—
—
—
—
—
—
—
—
—
—
CNIEA
0000
CNPUA
0E0A
—
—
—
—
—
—
—
—
—
—
—
CNPUA
0000
CNPDA
0E0C
—
—
—
—
—
—
—
—
—
—
—
CNPDA
0000
ANSELA 0E0E
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
ANSA
0007
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-29:
SFR
Name
Addr.
PORTB REGISTER MAP FOR dsPIC33EPXXGS502 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
0E10
TRISB
PORTB
0E12
RB
xxxx
LATB
0E14
LATB
xxxx
ODCB
0E16
ODCB
0000
CNENB
0E18
CNIEB
0000
CNPUB
0E1A
CNPUB
0000
CNPDB
0E1C
ANSELB
0E1E
FFFF
CNPDB
—
—
—
—
—
ANSB
—
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
ANSB
06FF
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 62
TABLE 4-28:
2013-2017 Microchip Technology Inc.
2013-2017 Microchip Technology Inc.
TABLE 4-30:
SFR
Name
PORTA REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES
Bit 4
Bit 3
Bit 2
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
TRISA
0E00
—
—
—
—
—
—
—
—
—
—
—
TRISA
001F
PORTA
0E02
—
—
—
—
—
—
—
—
—
—
—
RA
0000
LATA
0E04
—
—
—
—
—
—
—
—
—
—
—
LATA
0000
ODCA
0E06
—
—
—
—
—
—
—
—
—
—
—
ODCA
0000
CNENA
0E08
—
—
—
—
—
—
—
—
—
—
—
CNIEA
0000
CNPUA
0E0A
—
—
—
—
—
—
—
—
—
—
—
CNPUA
0000
CNPDA
0E0C
—
—
—
—
—
—
—
—
—
—
—
CNPDA
0000
ANSELA 0E0E
—
—
—
—
—
—
—
—
—
—
—
—
Bit 5
Bit 4
—
Bit 1
Bit 0
All
Resets
Addr.
ANSA
0007
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SFR
Name
Addr.
PORTB REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
0E10
TRISB
FFFF
PORTB
0E12
RB
xxxx
LATB
0E14
LATB
xxxx
ODCB
0E16
ODCB
0000
CNENB
0E18
CNIEB
0000
CNPUB
0E1A
CNPUB
0000
CNPDB
0E1C
CNPDB
ANSELB 0E1E
—
—
—
—
—
ANSB
—
0000
ANSB
—
ANSB
06EF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-32:
SFR
Name
PORTC REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
DS70005127D-page 63
TRISC
0E20
—
—
TRISC
3FFF
PORTC
0E22
—
—
RC
xxxx
LATC
0E24
—
—
LATC
xxxx
ODCC
0E26
—
—
ODCC
0000
CNENC
0E28
—
—
CNIEC
0000
CNPUC
0E2A
—
—
CNPUC
0000
CNPDC
0E2C
—
—
CNPDC
ANSELC
0E2E
—
—
—
ANSC
—
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
ANSC
—
ANSC
1E77
dsPIC33EPXXGS50X FAMILY
TABLE 4-31:
SFR
Name
PORTA REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
TRISA
0E00
—
—
—
—
—
—
—
—
—
—
—
TRISA
001F
PORTA
0E02
—
—
—
—
—
—
—
—
—
—
—
RA
0000
LATA
0E04
—
—
—
—
—
—
—
—
—
—
—
LATA
0000
ODCA
0E06
—
—
—
—
—
—
—
—
—
—
—
ODCA
0000
CNENA
0E08
—
—
—
—
—
—
—
—
—
—
—
CNIEA
0000
CNPUA
0E0A
—
—
—
—
—
—
—
—
—
—
—
CNPUA
0000
CNPDA
0E0C
—
—
—
—
—
—
—
—
—
—
—
CNPDA
0000
ANSELA
0E0E
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ANSA
0007
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-34:
SFR
Name
Addr.
PORTB REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
0E10
TRISB
FFFF
PORTB
0E12
RB
xxxx
LATB
0E14
LATB
xxxx
ODCB
0E16
ODCB
0000
CNENB
0E18
CNIEB
0000
CNPUB
0E1A
CNPUB
0000
CNPDB
0E1C
CNPDB
ANSELB 0E1E
—
—
—
—
—
ANSB
—
0000
ANSB
—
ANSB
06EF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2013-2017 Microchip Technology Inc.
TABLE 4-35:
SFR
Name
Addr.
PORTC REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
0E20
TRISC
PORTC
0E22
RC
xxxx
LATC
0E24
LATC
xxxx
0000
FFFF
ODCC
0E26
ODCC
CNENC
0E28
CNIEC
0000
CNPUC
0E2A
CNPUC
0000
CNPDC
0E2C
ANSELC 0E2E
CNPDC
—
—
—
ANSC
—
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
ANSC
—
ANSC
1E77
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 64
TABLE 4-33:
2013-2017 Microchip Technology Inc.
TABLE 4-36:
SFR
Name
Addr.
PORTD REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISD
0E30
TRISD
FFFF
PORTD
0E32
RD
xxxx
LATD
0E34
LATD
xxxx
ODCD
0E36
ODCD
0000
CNEND
0E38
CNIED
0000
CNPUD
0E3A
CNPUD
0000
CNPDD
0E3C
CNPDD
ANSELD 0E3E
—
—
ANSD13
—
—
—
—
—
ANSD7
0000
—
—
—
—
ANSD2
—
—
6084
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 65
dsPIC33EPXXGS50X FAMILY
4.5.1
PAGED MEMORY SCHEME
The paged memory scheme provides access to
multiple 32-Kbyte windows in the PSV memory. The
Data Space Page (DSRPAG) register, in combination
with the upper half of the Data Space address, can
provide up to 8 Mbytes of PSV address space. The
paged data memory space is shown in Figure 4-10.
The dsPIC33EPXXGS50X architecture extends the
available Data Space through a paging scheme,
which allows the available Data Space to be
accessed using MOV instructions in a linear fashion
for pre- and post-modified Effective Addresses (EAs).
The upper half of the base Data Space address is
used in conjunction with the Data Space Page
(DSRPAG) register to form the Program Space
Visibility (PSV) address.
The Program Space (PS) can be accessed with a
DSRPAG of 0x200 or greater. Only reads from PS are
supported using the DSRPAG.
The Data Space Page (DSRPAG) register is located
in the SFR space. Construction of the PSV address is
shown in Figure 4-9. When DSRPAG = 1 and the
base address bit, EA = 1, the DSRPAG bits
are concatenated onto EA to form the 24-bit
PSV read address.
FIGURE 4-9:
PROGRAM SPACE VISIBILITY (PSV) READ ADDRESS GENERATION
16-Bit DS EA
EA = 0
(DSRPAG = don’t care)
No EDS Access
0
Byte
Select
EA
EA
DSRPAG
=1
1
EA
Select
DSRPAG
Generate
PSV Address
1
DSRPAG
9 Bits
15 Bits
24-Bit PSV EA
Byte
Select
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
DS70005127D-page 66
2013-2017 Microchip Technology Inc.
2013-2017 Microchip Technology Inc.
FIGURE 4-10:
PAGED DATA MEMORY SPACE
Table Address Space
(TBLPAG)
Program Space
(Instruction & Data)
DS_Addr
0x0000
Program Memory
(lsw – )
0x00_0000
DS_Addr
0x0000
0x7FFF
PSV
Program
Memory
(lsw)
0x0000
SFR Registers
0x0FFF
0x1000
0x0000
Up to 8-Kbyte
RAM
0x2FFF
0x3000
0x7FFF
0x8000
(DSRPAG = 0x2FF)
No Writes Allowed
0x0000
0x7F_FFFF
0x7FFF
0x0000
0xFFFF
(DSRPAG = 0x300)
No Writes Allowed
0x7FFF
PSV
Program
Memory
(MSB)
32-Kbyte
PSV Window
0xFFFF
0x0000
Program Memory
(MSB – )
0x00_0000
(DSRPAG = 0x3FF)
No Writes Allowed
0x7FFF
DS70005127D-page 67
0x7F_FFFF
(TBLPAG = 0x7F)
lsw Using
TBLRDL/TBLWTL,
MSB Using
TBLRDH/TBLWTH
dsPIC33EPXXGS50X FAMILY
DS_Addr
0xFFFF
(DSRPAG = 0x200)
No Writes Allowed
Local Data Space
(TBLPAG = 0x00)
lsw Using
TBLRDL/TBLWTL,
MSB Using
TBLRDH/TBLWTH
dsPIC33EPXXGS50X FAMILY
When a PSV page overflow or underflow occurs,
EA is cleared as a result of the register indirect EA
calculation. An overflow or underflow of the EA in the
PSV pages can occur at the page boundaries when:
• The initial address, prior to modification,
addresses the PSV page
• The EA calculation uses Pre- or Post-Modified
Register Indirect Addressing; however, this does
not include Register Offset Addressing
In general, when an overflow is detected, the DSRPAG
register is incremented and the EA bit is set to keep
the base address within the PSV window. When an
underflow is detected, the DSRPAG register is
decremented and the EA bit is set to keep the base
TABLE 4-37:
address within the PSV window. This creates a linear
PSV address space, but only when using Register
Indirect Addressing modes.
Exceptions to the operation described above arise
when entering and exiting the boundaries of Page 0
and PSV spaces. Table 4-37 lists the effects of overflow
and underflow scenarios at different boundaries.
In the following cases, when overflow or underflow
occurs, the EA bit is set and the DSRPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
• Register Indirect with Register Offset Addressing
• Modulo Addressing
• Bit-Reversed Addressing
OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0 AND
PSV SPACE BOUNDARIES(2,3,4)
Before
O/U,
Operation
R/W
O,
Read
O,
Read
[++Wn]
or
[Wn++]
U,
Read
U,
Read
U,
Read
[--Wn]
or
[Wn--]
Legend:
Note 1:
2:
3:
4:
DSxPAG
DS
EA
DSRPAG = 0x2FF
1
DSRPAG = 0x3FF
After
Page
Description
DSxPAG
DS
EA
Page
Description
PSV: Last lsw
page
DSRPAG = 0x300
1
PSV: First MSB
page
1
PSV: Last MSB
page
DSRPAG = 0x3FF
0
See Note 1
DSRPAG = 0x001
1
PSV page
DSRPAG = 0x001
0
See Note 1
DSRPAG = 0x200
1
PSV: First lsw
page
DSRPAG = 0x200
0
See Note 1
DSRPAG = 0x300
1
PSV: First MSB
page
DSRPAG = 0x2FF
1
PSV: Last lsw
page
O = Overflow, U = Underflow, R = Read, W = Write
The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x7FFF).
An EDS access, with DSRPAG = 0x000, will generate an address error trap.
Only reads from PS are supported using DSRPAG.
Pseudolinear Addressing is not supported for large offsets.
DS70005127D-page 68
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
4.5.2
EXTENDED X DATA SPACE
The lower portion of the base address space range,
between 0x0000 and 0x7FFF, is always accessible,
regardless of the contents of the Data Space Page register. It is indirectly addressable through the register
indirect instructions. It can be regarded as being
located in the default EDS Page 0 (i.e., EDS address
range of 0x000000 to 0x007FFF with the base address
bit, EA = 0, for this address range). However,
Page 0 cannot be accessed through the upper
32 Kbytes, 0x8000 to 0xFFFF, of base Data Space in
combination with DSRPAG = 0x00. Consequently,
DSRPAG is initialized to 0x001 at Reset.
Note 1: DSRPAG should not be used to access
Page 0. An EDS access with DSRPAG
set to 0x000 will generate an address
error trap.
When the PC is pushed onto the stack, PC are
pushed onto the first available stack word, then
PC are pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in Figure 4-11. During exception processing,
the MSB of the PC is concatenated with the lower 8 bits
of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
Note 1: To maintain system Stack Pointer (W15)
coherency, W15 is never subject to
(EDS) paging, and is therefore, restricted
to an address range of 0x0000 to
0xFFFF. The same applies to the W14
when used as a Stack Frame Pointer
(SFA = 1).
2: As the stack can be placed in, and can
access X and Y spaces, care must be
taken regarding its use, particularly with
regard to local automatic variables in a C
development environment
2: Clearing the DSRPAG in software has no
effect.
The remaining PSV pages are only accessible using
the DSRPAG register in combination with the upper
32 Kbytes, 0x8000 to 0xFFFF, of the base address,
where base address bit, EA = 1.
SOFTWARE STACK
The W15 register serves as a dedicated Software
Stack Pointer (SSP), and is automatically modified by
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
the same manner as all other W registers. This simplifies reading, writing and manipulating the Stack Pointer
(for example, creating stack frames).
Note:
To protect against misaligned stack
accesses, W15 is fixed to ‘0’ by the
hardware.
FIGURE 4-11:
0x0000
CALL STACK FRAME
15
0
CALL SUBR
Stack Grows Toward
Higher Address
4.5.3
PC
W15 (before CALL)
b‘000000000’ PC
W15 (after CALL)
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SSP points to valid RAM in all
dsPIC33EPXXGS50X devices and permits stack availability for non-maskable trap exceptions. These can
occur before the SSP is initialized by the user software.
You can reprogram the SSP during initialization to any
location within Data Space.
The Software Stack Pointer always points to the first
available free word and fills the software stack,
working from lower toward higher addresses.
Figure 4-11 illustrates how it pre-decrements for a
stack pop (read) and post-increments for a stack push
(writes).
2013-2017 Microchip Technology Inc.
DS70005127D-page 69
dsPIC33EPXXGS50X FAMILY
4.6
Instruction Addressing Modes
The addressing modes shown in Table 4-38 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.6.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a Working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire Data Space.
TABLE 4-38:
4.6.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a Working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W
register fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-Bit or 10-Bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual instructions can support different
subsets of these addressing modes.
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn form the Effective Address (EA).
Register Indirect Post-Modified
The contents of Wn form the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
DS70005127D-page 70
The sum of Wn and a literal forms the EA.
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
4.6.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions, and the DSP accumulator class
of instructions, provide a greater degree of addressing flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. However, the 4-bit Wb (Register Offset) field is
shared by both source and destination (but
typically only used by one).
4.6.4
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the Data Pointers through register indirect
tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must therefore, be valid addresses within
X Data Space for W8 and W9, and Y Data Space for
W10 and W11.
Note:
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-Bit Literal
16-Bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
2013-2017 Microchip Technology Inc.
MAC INSTRUCTIONS
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.6.5
OTHER INSTRUCTIONS
Besides the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ULNK, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as a NOP, do not have
any operands.
DS70005127D-page 71
dsPIC33EPXXGS50X FAMILY
4.7
4.7.1
Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either Data or
Program Space (since the Data Pointer mechanism is
essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the pointers into Program Space) and Y Data Spaces. Modulo
Addressing can operate on any W Register Pointer. However, it is not advisable to use W14 or W15 for Modulo
Addressing since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be configured to operate in only one direction, as there are certain
restrictions on the buffer start address (for incrementing
buffers) or end address (for decrementing buffers),
based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a Bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-2).
Note:
Y space Modulo Addressing EA calculations assume word-sized data (LSb of
every EA is always clear).
The length of a circular buffer is not directly specified. It is
determined by the difference between the corresponding
start and end addresses. The maximum possible length of
the circular buffer is 32K words (64 Kbytes).
4.7.2
W ADDRESS REGISTER SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON, contains enable flags, as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that
operate with Modulo Addressing:
• If XWM = 1111, X RAGU and X WAGU Modulo
Addressing is disabled
• If YWM = 1111, Y AGU Modulo Addressing is
disabled
The X Address Space Pointer W (XWM) register, to
which Modulo Addressing is to be applied, is stored in
MODCON (see Table 4-2). Modulo Addressing is
enabled for X Data Space when XWM is set to any
value other than ‘1111’ and the XMODEN bit is set
(MODCON).
The Y Address Space Pointer W (YWM) register, to
which Modulo Addressing is to be applied, is stored in
MODCON. Modulo Addressing is enabled for Y
Data Space when YWM is set to any value other than
‘1111’ and the YMODEN bit (MODCON) is set.
FIGURE 4-12:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
DS70005127D-page 72
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
MOV
#0x0000, W0
;W0 holds buffer fill value
MOV
#0x1110, W1
;point W1 to buffer
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations
;fill the next location
;increment the fill value
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
4.7.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
4.8
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (such as
[W7 + W2]) is used, Modulo Addressing
correction is performed, but the contents of
the register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.8.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled when all of
these situations are met:
• BWMx bits (W register selection) in the MODCON
register are any value other than ‘1111’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB is the Bit-Reversed Addressing modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It
does not function for any other addressing mode or for
byte-sized data and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB) and the offset associated with the
Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of
the EA is ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed
Addressing can be enabled simultaneously
using the same W register, but BitReversed Addressing operation will always
take precedence for data writes when
enabled.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
2013-2017 Microchip Technology Inc.
DS70005127D-page 73
dsPIC33EPXXGS50X FAMILY
FIGURE 4-13:
BIT-REVERSED ADDRESSING EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
TABLE 4-39:
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
DS70005127D-page 74
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
4.9
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
Interfacing Program and Data
Memory Spaces
The dsPIC33EPXXGS50X family architecture uses a
24-bit wide Program Space (PS) and a 16-bit wide Data
Space (DS). The architecture is also a modified
Harvard scheme, meaning that data can also be
present in the Program Space. To use this data successfully, it must be accessed in a way that preserves
the alignment of information in both spaces.
Aside from normal execution, the architecture of the
dsPIC33EPXXGS50X family devices provides two
methods by which Program Space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
TABLE 4-40:
PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
TBLPAG
Configuration
TBLPAG
0xxx
xxxx
xxxx
0xxx xxxx
0
xxxx
xxxx
xxx0
Data EA
xxxx xxxx xxxx xxxx
1xxx xxxx
FIGURE 4-14:
PC
0
Data EA
xxxx xxxx xxxx xxxx
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 Bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
User/Configuration
Space Select
Note 1:
2:
Byte Select
The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain
word alignment of data in the Program and Data Spaces.
Table operations are not required to be word-aligned. Table Read operations are permitted in the
configuration memory space.
2013-2017 Microchip Technology Inc.
DS70005127D-page 75
dsPIC33EPXXGS50X FAMILY
4.9.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the Program Space without going
through Data Space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a Program Space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses.
Program memory can thus be regarded as two 16-bit
wide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDH and TBLWTH access the space that
contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from Program Space.
Both function as either byte or word operations.
• TBLRDL (Table Read Low):
- In Word mode, this instruction maps the lower
word of the Program Space location (P)
to a data address (D)
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 4-15:
• TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P)
to a data address. The ‘phantom’ byte
(D) is always ‘0’.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D
of the data address in the TBLRDL instruction. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a Program Space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user application
and configuration spaces. When TBLPAG = 0, the
table page is located in the user memory space. When
TBLPAG = 1, the page is located in configuration
space.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
0x020000
0x030000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
0x800000
DS70005127D-page 76
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
5.0
device just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
“Flash Programming” (DS70005156) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com)
Enhanced In-Circuit Serial Programming uses an
on-board bootloader, known as the Program Executive,
to manage the programming process. Using an SPI data
frame format, the Program Executive can erase,
program and verify program memory. For more information on Enhanced ICSP, see the device programming
specification.
RTSP is accomplished using TBLRD (Table Read) and
TBLWT (Table Write) instructions. With RTSP, the user
application can write program memory data with a
single program memory word and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes)
at a time.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
The dsPIC33EPXXGS50X family devices contain
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits of the TBLPAG register and the
Effective Address (EA) from a W register, specified in
the table instruction, as shown in Figure 5-1. The
TBLRDL and the TBLWTL instructions are used to read
or write to bits of program memory. TBLRDL and
TBLWTL can access program memory in both Word
and Byte modes. The TBLRDH and TBLWTH
instructions are used to read or write to bits of
program memory. TBLRDH and TBLWTH can also
access program memory in Word or Byte mode.
Flash memory can be programmed in three ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
• Run-Time Self-Programming (RTSP)
ICSP allows for a dsPIC33EPXXGS50X family device
to be serially programmed while in the end application
circuit. This is done with a programming clock and programming data (PGECx/PGEDx) line, and three other
lines for power (VDD), ground (VSS) and Master Clear
(MCLR). This allows customers to manufacture boards
with unprogrammed devices and then program the
FIGURE 5-1:
Table Instructions and Flash
Programming
ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 Bits
User/Configuration
Space Select
2013-2017 Microchip Technology Inc.
16 Bits
24-Bit EA
Byte
Select
DS70005127D-page 77
dsPIC33EPXXGS50X FAMILY
The dsPIC33EPXXGS50X family Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user application to erase
a single page (8 rows or 512 instructions) of memory at
a time and to program one row at a time. It is possible
to program two instructions at a time as well.
The page erase and single row write blocks are edgealigned, from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively. Figure 26-14 in Section 26.0 “Electrical
Characteristics” lists the typical erase and
programming times.
Row programming is performed by loading 192 bytes
into data memory and then loading the address of the
first byte in that row into the NVMSRCADR register.
Once the write has been initiated, the device will
automatically load the write latches and increment the
NVMSRCADR and the NVMADR(U) registers until all
bytes have been programmed. The RPDF bit
(NVMCON) selects the format of the stored data in
RAM to be either compressed or uncompressed. See
Figure 5-2 for data formatting. Compressed data helps
to reduce the amount of required RAM by using the
upper byte of the second word for the MSB of the
second instruction.
The basic sequence for RTSP word programming is to
use the TBLWTL and TBLWTH instructions to load two of
the 24-bit instructions into the write latches found in
configuration memory space. Refer to Figure 4-1
through Figure 4-4 for write latch addresses. Programming is performed by unlocking and setting the control
bits in the NVMCON register.
All erase and program operations may optionally use
the NVM interrupt to signal the successful completion
of the operation. For example, when performing Flash
write operations on the Inactive Partition in Dual
Partition mode, where the CPU remains running, it is
necessary to wait for the NVM interrupt before
programming the next block of Flash program memory.
DS70005127D-page 78
FIGURE 5-2:
UNCOMPRESSED/
COMPRESSED FORMAT
15
0
7
LSW1
Increasing
Address
RTSP Operation
0x00
Even Byte
Address
MSB1
LSW2
0x00
MSB2
UNCOMPRESSED FORMAT (RPDF = 0)
15
Increasing
Address
5.2
0
7
LSW1
MSB2
Even Byte
Address
MSB1
LSW2
COMPRESSED FORMAT (RPDF = 1)
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the programming operation is finished. Setting the WR bit
(NVMCON) starts the operation and the WR bit is
automatically cleared when the operation is finished.
5.3.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
Programmers can program two adjacent words
(24 bits x 2) of program Flash memory at a time on every
other word address boundary (0x000000, 0x000004,
0x000008, etc.). To do this, it is necessary to erase the
page that contains the desired address of the location
the user wants to change. For protection against
accidental operations, the write initiate sequence for
NVMKEY must be used to allow any erase or program
operation to proceed. After the programming command
has been executed, the user application must wait for
the programming time until programming is complete.
The two instructions following the start of the
programming sequence should be NOPs.
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
5.4
Dual Partition Flash Configuration
For dsPIC33EP64GS50X devices operating in Dual
Partition Flash Program Memory modes, the Inactive
Partition can be erased and programmed without stalling the processor. The same programming algorithms
are used for programming and erasing the Flash in the
Inactive Partition, as described in Section 5.2 “RTSP
Operation”. On top of the page erase option, the entire
Flash memory of the Inactive Partition can be erased
by configuring the NVMOP bits in the NVMCON
register.
Note 1: The application software to be loaded
into the Inactive Partition will have the
address of the Active Partition. The
bootloader firmware will need to offset
the address by 0x400000 in order to write
to the Inactive Partition.
5.4.1
FLASH PARTITION SWAPPING
The Boot Sequence Number is used for determining
the Active Partition at start-up and is encoded within
the FBTSEQ Configuration register bits. Unlike most
Configuration registers, which only utilize the lower
16 bits of the program memory, FBTSEQ is a 24-bit
Configuration Word. The Boot Sequence Number
(BSEQ) is a 12-bit value and is stored in FBTSEQ
twice. The true value is stored in bits, FBTSEQ,
and its complement is stored in bits, FBTSEQ.
At device Reset, the sequence numbers are read and
the partition with the lowest sequence number
becomes the Active Partition. If one of the Boot
Sequence Numbers is invalid, the device will select the
partition with the valid Boot Sequence Number, or
default to Partition 1 if both sequence numbers are
invalid. See Section 23.0 “Special Features” for more
information.
The BOOTSWP instruction provides an alternative
means of swapping the Active and Inactive Partitions
(soft swap) without the need for a device Reset. The
BOOTSWP must always be followed by a GOTO instruction. The BOOTSWP instruction swaps the Active and
Inactive Partitions, and the PC vectors to the location
specified by the GOTO instruction in the newly Active
Partition.
It is important to note that interrupts should temporarily
be disabled while performing the soft swap sequence
and that after the partition swap, all peripherals and
interrupts which were enabled remain enabled. Additionally, the RAM and stack will maintain state after the
switch. As a result, it is recommended that applications
using soft swaps jump to a routine that will reinitialize
the device in order to ensure the firmware runs as
expected. The Configuration registers will have no
effect during a soft swap.
2013-2017 Microchip Technology Inc.
For robustness of operation, in order to execute the
BOOTSWP instruction, it is necessary to execute the
NVM unlocking sequence as follows:
1.
2.
3.
Write 0x55 to NVMKEY.
Write 0xAA to NVMKEY.
Execute the BOOTSWP instruction.
If the unlocking sequence is not performed, the
BOOTSWP instruction will be executed as a forced NOP
and a GOTO instruction, following the BOOTSWP instruction, will be executed, causing the PC to jump to that
location in the current operating partition.
The SFTSWP and P2ACTIV bits in the NVMCON
register are used to determine a successful swap of the
Active and Inactive Partitions, as well as which partition
is active. After the BOOTSWP and GOTO instructions, the
SFTSWP bit should be polled to verify the partition
swap has occurred and then cleared for the next panel
swap event.
5.4.2
DUAL PARTITION MODES
While
operating
in
Dual
Partition
mode,
dsPIC33EP64GS50X family devices have the option for
both partitions to have their own defined security segments, as shown in Figure 23-4. Alternatively, the device
can operate in Protected Dual Partition mode, where
Partition 1 becomes permanently erase/write-protected.
Protected Dual Partition mode allows for a “Factory
Default” mode, which provides a fail-safe backup image
to be stored in Partition 1.
dsPIC33EP64GS50X family devices can also operate
in Privileged Dual Partition mode, where additional
security protections are implemented to allow for protection of intellectual property when multiple parties
have software within the device. In Privileged Dual Partition mode, both partitions place additional restrictions
on the BSLIM register. These prevent changes to the
size of the Boot Segment and General Segment,
ensuring that neither segment will be altered.
5.5
Flash Memory Resources
Many useful resources are provided on the main
product page of the Microchip web site for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
5.5.1
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005127D-page 79
dsPIC33EPXXGS50X FAMILY
5.6
Control Registers
Five SFRs are used to write and erase the program
Flash memory: NVMCON, NVMKEY, NVMADR,
NVMADRU and NVMSRCADR/H.
The NVMCON register (Register 5-1) selects the
operation to be performed (page erase, word/row
program, Inactive Partition erase), initiates the program
or erase cycle and is used to determine the Active
Partition in Dual Partition modes.
NVMKEY (Register 5-4) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must
consecutively write 0x55 and 0xAA to the NVMKEY
register.
DS70005127D-page 80
There are two NVM Address registers: NVMADRU and
NVMADR. These two registers, when concatenated,
form the 24-bit Effective Address (EA) of the selected
word/row for programming operations, or the selected
page for erase operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA.
For row programming operation, data to be written to
program Flash memory is written into data memory
space (RAM) at an address defined by the
NVMSRCADR register (location of first element in row
programming data).
2013-2017 Microchip Technology Inc.
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REGISTER 5-1:
R/SO-0(1)
NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/W-0(1)
WR
WREN
R/W-0(1)
R/W-0
WRERR
NVMSIDL(2)
R/C-0
R-0
(6)
SFTSWP
(6)
P2ACTIV
R/W-0
R/C-0
RPDF
URERR
bit 15
bit 8
U-0
U-0
—
—
U-0
—
U-0
—
R/W-0(1)
(3,4)
NVMOP3
R/W-0(1)
NVMOP2
(3,4)
R/W-0(1)
NVMOP1
(3,4)
R/W-0(1)
NVMOP0(3,4)
bit 7
bit 0
Legend:
C = Clearable bit
SO = Settable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12
NVMSIDL: NVM Stop in Idle Control bit(2)
1 = Flash voltage regulator goes into Standby mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
bit 11
SFTSWP: Partition Soft Swap Status bit(6)
1 = Partitions have been successfully swapped using the BOOTSWP instruction (soft swap)
0 = Awaiting successful partition swap using the BOOTSWP instruction or a device Reset will determine
the Active Partition based on FBTSEQ
bit 10
P2ACTIV: Partition 2 Active Status bit(6)
1 = Partition 2 Flash is mapped into the active region
0 = Partition 1 Flash is mapped into the active region
bit 9
RPDF: Row Programming Data Format bit
1 = Row data to be stored in RAM in compressed format
0 = Row data to be stored in RAM in uncompressed format
Note 1:
2:
3:
4:
5:
6:
7:
These bits can only be reset on a POR.
If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
All other combinations of NVMOP are unimplemented.
Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
Two adjacent words on a 4-word boundary are programmed during execution of this operation.
Only available on dsPIC33EP64GS50X devices operating in Dual Partition mode. For all other devices,
this bit is reserved.
The specific Boot mode depends on bits of the programmed data:
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode
00 = Reserved
2013-2017 Microchip Technology Inc.
DS70005127D-page 81
dsPIC33EPXXGS50X FAMILY
REGISTER 5-1:
NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)
bit 8
URERR: Row Programming Data Underrun Error bit
1 = Indicates row programming operation has been terminated
0 = No data underrun error is detected
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation Select bits(1,3,4)
1111 = Reserved
1110 = User memory Bulk Erase operation
1010 = Reserved
1001 = Reserved
1000 = Boot memory Double-Word Program operation in a Dual Partition Flash mode(7)
0101 = Reserved
0100 = Inactive Partition Memory Erase operation
0011 = Memory Page Erase operation
0010 = Memory Row Program operation
0001 = Memory Double-Word Program operation(5)
0000 = Reserved
Note 1:
2:
3:
4:
5:
6:
7:
These bits can only be reset on a POR.
If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
All other combinations of NVMOP are unimplemented.
Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
Two adjacent words on a 4-word boundary are programmed during execution of this operation.
Only available on dsPIC33EP64GS50X devices operating in Dual Partition mode. For all other devices,
this bit is reserved.
The specific Boot mode depends on bits of the programmed data:
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode
00 = Reserved
DS70005127D-page 82
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 5-2:
R/W-x
NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
NVMADR: Nonvolatile Memory Lower Write Address bits
Selects the lower 16 bits of the location to program or erase in program Flash memory. This register
may be read or written to by the user application.
REGISTER 5-3:
NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
NVMADRU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
NVMADRU: Nonvolatile Memory Upper Write Address bits
Selects the upper 8 bits of the location to program or erase in program Flash memory. This register
may be read or written to by the user application.
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REGISTER 5-4:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
NVMKEY: NVM Key Register bits (write-only)
REGISTER 5-5:
R/W-0
x = Bit is unknown
NVMSRCADR: NVM SOURCE DATA ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADR
R/W-0
R/W-0
R/W-0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADR
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
NVMSRCADR: NVM Source Data Address bits
The RAM address of the data to be programmed into Flash when the NVMOP bits are set to row
programming.
DS70005127D-page 84
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
6.0
A simplified block diagram of the Reset module is
shown in Figure 6-1.
RESETS
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Reset” (DS70602) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com)
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
•
•
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: RESET Instruction
WDTO: Watchdog Timer Time-out Reset
CM: Configuration Mismatch Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
FIGURE 6-1:
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 4.0 “Memory Organization” of
this manual for register Reset states.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
A POR clears all the bits, except for the BOR and POR
bits (RCON) that are set. The user application
can set or clear any bit, at any time, during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
For all Resets, the default clock source is determined
by the FNOSC bits in the FOSCSEL Configuration register. The value of the FNOSCx bits is loaded
into the NOSC (OSCCON) bits on Reset,
which in turn, initializes the system clock.
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
VDD
BOR
Internal
Regulator
SYSRST
VDD Rise
Detect
POR
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
Configuration Mismatch
2013-2017 Microchip Technology Inc.
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dsPIC33EPXXGS50X FAMILY
6.1
Reset Resources
Many useful resources are provided on the main
product page of the Microchip web site for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
DS70005127D-page 86
6.1.1
KEY RESOURCES
• “Reset” (DS70602) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
RCON: RESET CONTROL REGISTER(1)
REGISTER 6-1:
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
TRAPR
IOPUWR
—
—
VREGSF
—
CM
VREGS
bit 15
bit 8
R/W-0
R/W-0
EXTR
SWR
R/W-0
(2)
SWDTEN
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
bit 13-12
Unimplemented: Read as ‘0’
bit 11
VREGSF: Flash Voltage Regulator Standby During Sleep bit
1 = Flash voltage regulator is active during Sleep
0 = Flash voltage regulator goes into Standby mode during Sleep
bit 10
Unimplemented: Read as ‘0’
bit 9
CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred.
0 = A Configuration Mismatch Reset has not occurred
bit 8
VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6
SWR: Software RESET (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5
SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1:
2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the WDTEN Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.
2013-2017 Microchip Technology Inc.
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REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1:
2:
All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the WDTEN Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.
DS70005127D-page 88
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to “Interrupts” (DS70000600) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
7.1.1
The Alternate Interrupt Vector Table (AIVT), shown in
Figure 7-2, is available only when the Boot Segment is
defined and the AIVT has been enabled. To enable the
Alternate Interrupt Vector Table, the Configuration bit,
AIVTDIS in the FSEC register, must be programmed
and the AIVTEN bit must be set (INTCON2 = 1).
When the AIVT is enabled, all interrupt and exception
processes use the alternate vectors instead of the
default vectors. The AIVT begins at the start of the last
page of the Boot Segment, defined by BSLIM.
The second half of the page is no longer usable space.
The Boot Segment must be at least 2 pages to enable
the AIVT.
Note:
The dsPIC33EPXXGS50X family interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
dsPIC33EPXXGS50X family CPU.
The interrupt controller has the following features:
• Six processor exceptions and software traps
• Seven user-selectable priority levels
• Interrupt Vector Table (IVT) with a unique vector
for each interrupt or exception source
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies
• Alternate Interrupt Vector Table (AIVT) for debug
support
7.1
Interrupt Vector Table
The dsPIC33EPXXGS50X family Interrupt Vector
Table (IVT), shown in Figure 7-1, resides in program
memory, starting at location, 000004h. The IVT
contains six non-maskable trap vectors and up to
246 sources of interrupts. In general, each interrupt
source has its own vector. Each interrupt vector
contains a 24-bit wide address. The value programmed
into each interrupt vector location is the starting
address of the associated Interrupt Service Routine
(ISR).
ALTERNATE INTERRUPT VECTOR
TABLE
Although the Boot Segment must be
enabled in order to enable the AIVT,
application code does not need to be
present inside of the Boot Segment. The
AIVT (and IVT) will inherit the Boot
Segment code protection.
The AIVT supports debugging by providing a means to
switch between an application and a support environment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time.
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXGS50X family devices clear their
registers in response to a Reset, which forces the PC
to zero. The device then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
Any unimplemented or unused vector
locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.
2013-2017 Microchip Technology Inc.
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dsPIC33EPXXGS50X FAMILY
dsPIC33EPXXGS50X FAMILY INTERRUPT VECTOR TABLE
IVT
Decreasing Natural Order Priority
FIGURE 7-1:
Note:
Reset – GOTO Instruction
Reset – GOTO Address
Oscillator Fail Trap Vector
Address Error Trap Vector
Generic Hard Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Generic Soft Trap Vector
Reserved
Interrupt Vector 0
Interrupt Vector 1
:
:
:
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
:
:
:
Interrupt Vector 116
Interrupt Vector 117
Interrupt Vector 118
Interrupt Vector 119
Interrupt Vector 120
:
:
:
Interrupt Vector 244
Interrupt Vector 245
START OF CODE
0x000000
0x000002
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000014
0x000016
:
:
:
0x00007C
0x00007E
0x000080
:
:
:
0x0000FC
0x0000FE
0x000100
0x000102
0x000104
:
:
:
0x0001FC
0x0001FE
0x000200
See Table 7-1 for
Interrupt Vector Details
In Dual Partition modes, each partition has a dedicated Interrupt Vector Table.
DS70005127D-page 90
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
AIVT
Decreasing Natural Order Priority
FIGURE 7-2:
Note 1:
2:
dsPIC33EPXXGS50X ALTERNATE INTERRUPT VECTOR TABLE(2)
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Generic Hard Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Generic Soft Trap Vector
Reserved
Interrupt Vector 0
Interrupt Vector 1
:
:
:
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
:
:
:
Interrupt Vector 116
Interrupt Vector 117
Interrupt Vector 118
Interrupt Vector 119
Interrupt Vector 120
:
:
:
Interrupt Vector 244
Interrupt Vector 245
BSLIM(1) + 0x000000
BSLIM(1) + 0x000002
BSLIM(1) + 0x000004
BSLIM(1) + 0x000006
BSLIM(1) + 0x000008
BSLIM(1) + 0x00000A
BSLIM(1) + 0x00000C
BSLIM(1) + 0x00000E
BSLIM(1) + 0x000010
BSLIM(1) + 0x000012
BSLIM(1) + 0x000014
BSLIM(1) + 0x000016
:
:
:
BSLIM(1) + 0x00007C
BSLIM(1) + 0x00007E
BSLIM(1) + 0x000080
:
:
:
BSLIM(1) + 0x0000FC
BSLIM(1) + 0x0000FE
BSLIM(1) + 0x000100
BSLIM(1) + 0x000102
BSLIM(1) + 0x000104
:
:
:
BSLIM(1) + 0x0001FC
BSLIM(1) + 0x0001FE
See Table 7-1 for
Interrupt Vector Details
The address depends on the size of the Boot Segment defined by BSLIM.
[(BSLIM – 1) x 0x400] + Offset.
In Dual Partition modes, each partition has a dedicated Alternate Interrupt Vector Table (if
enabled).
2013-2017 Microchip Technology Inc.
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dsPIC33EPXXGS50X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS
Interrupt Source
Vector
#
IRQ
#
Interrupt Bit Location
IVT Address
Flag
Enable
Priority
Highest Natural Order Priority
INT0 – External Interrupt 0
8
0
0x000014
IFS0
IEC0
IPC0
IC1 – Input Capture 1
9
1
0x000016
IFS0
IEC0
IPC0
OC1 – Output Compare 1
10
2
0x000018
IFS0
IEC0
IPC0
T1 – Timer1
11
3
0x00001A
IFS0
IEC0
IPC0
Reserved
12
4
0x00001C
—
—
—
IC2 – Input Capture 2
13
5
0x00001E
IFS0
IEC0
IPC1
OC2 – Output Compare 2
14
6
0x000020
IFS0
IEC0
IPC1
T2 – Timer2
15
7
0x000022
IFS0
IEC0
IPC1
IPC2
T3 – Timer3
16
8
0x000024
IFS0
IEC0
SPI1E – SPI1 Error
17
9
0x000026
IFS0
IEC0
IPC2
SPI1 – SPI1 Transfer Done
18
10
0x000028
IFS0
IEC0
IPC2
U1RX – UART1 Receiver
19
11
0x00002A
IFS0
IEC0
IPC2
U1TX – UART1 Transmitter
20
12
0x00002C
IFS0
IEC0
IPC3
ADC – ADC Global Convert Done
21
13
0x00002E
IFS0
IEC0
IPC3
Reserved
22
14
0x000030
—
—
—
NVM – NVM Write Complete
23
15
0x000032
IFS0
IEC0
IPC3
SI2C1 – I2C1 Slave Event
24
16
0x000034
IFS1
IEC1
IPC4
MI2C1 – I2C1 Master Event
25
17
0x000036
IFS1
IEC1
IPC4
CMP1 – Analog Comparator 1 Interrupt
26
18
0x000038
IFS1
IEC1
IPC4
CN – Input Change Interrupt
27
19
0x00003A
IFS1
IEC1
IPC4
IPC5
INT1 – External Interrupt 1
28
20
0x00003C
IFS1
IEC1
29-32
21-24
0x00003E-0x000044
—
—
—
OC3 – Output Compare 3
33
25
0x000046
IFS1
IEC1
IPC6
OC4 – Output Compare 4
34
26
0x000048
IFS1
IEC1
IPC6
T4 – Timer4
35
27
0x00004A
IFS1
IEC1
IPC6
T5 – Timer5
36
28
0x00004C
IFS1
IEC1
IPC7
INT2 – External Interrupt 2
37
29
0x00004E
IFS1
IEC1
IPC7
U2RX – UART2 Receiver
38
30
0x000050
IFS1
IEC1
IPC7
IPC7
Reserved
U2TX – UART2 Transmitter
39
31
0x000052
IFS1
IEC1
SPI2E – SPI2 Error
40
32
0x000054
IFS2
IEC2
IPC8
SPI2 – SPI2 Transfer Done
41
33
0x000056
IFS2
IEC2
IPC8
42-44
34-36
0x000058-0x00005C
—
—
—
IC3 – Input Capture 3
45
37
0x00005E
IFS2
IEC2
IPC9
IC4 – Input Capture 4
46
38
0x000060
IFS2
IEC2
IPC9
47-56
39-48
0x000062-0x000074
—
—
—
57
49
0x000076
IFS3
IEC3
IPC12
IPC12
Reserved
Reserved
SI2C2 – I2C2 Slave Event
MI2C2 – I2C2 Master Event
Reserved
INT4 – External Interrupt 4
Reserved
PSEM – PWM Special Event Match
58
50
0x000078
IFS3
IEC3
59-61
51-53
0x00007A-0x00007E
—
—
—
62
54
0x000080
IFS3
IEC3
IPC13
63-64
55-54
0x000082-0x000084
—
—
—
IPC14
65
57
0x000086
IFS3
IEC3
66-72
58-64
0x000088-0x000094
—
—
—
U1E – UART1 Error Interrupt
73
65
0x000096
IFS4
IEC4
IPC16
U2E – UART2 Error Interrupt
74
66
0x000098
IFS4
IEC4
IPC16
75-80
67-72
0x00009A-0x0000A4
—
—
—
Reserved
Reserved
DS70005127D-page 92
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Source
PWM Secondary Special Event Match
Reserved
PWM1 – PWM1 Interrupt
Interrupt Bit Location
Vector
#
IRQ
#
IVT Address
81
73
0x0000A6
82-101
74-93
0x0000A8-0x0000CE
—
—
—
102
94
0x0000D0
IFS5
IEC5
IPC23
Flag
Enable
Priority
IFS4
IEC4
IPC18
PWM2 – PWM2 Interrupt
103
95
0x0000D2
IFS5
IEC5 IPC23
PWM3 – PWM3 Interrupt
104
96
0x0000D4
IFS6
IEC6
PWM4 – PWM4 Interrupt
105
97
0x0000D6
IFS6
IEC6
IPC24
PWM5 – PWM5 Interrupt
106
98
0x0000D8
IFS6
IEC6
IPC24
Reserved
0x0000DA-0x0000E0
—
—
—
CMP2 – Analog Comparator 2 Interrupt
111
103
0x0000E2
IFS6
IEC6
IPC25
CMP3 – Analog Comparator 3 Interrupt
112
104
0x0000E4
IFS6
IEC6
IPC26
CMP4 – Analog Comparator 4 Interrupt
113
105
0x0000E6
IFS6
IEC6
IPC26
—
—
—
IPC27
Reserved
AN0 Conversion Done
106-110 99-102
IPC24
114-117 106-109 0x0000E8-0x0000EE
118
110
0x0000F0
IFS6
IEC6
AN1 Conversion Done
119
111
0x0000F2
IFS6
IEC6 IPC27
AN2 Conversion Done
120
112
0x0000F4
IFS7
IEC7
AN3 Conversion Done
121
113
0x0000F6
IFS7
IEC7
IPC28
AN4 Conversion Done
122
114
0x0000F8
IFS7
IEC7
IPC28
AN5 Conversion Done
123
115
0x0000FA
IFS7
IEC7
IPC28
AN6 Conversion Done
124
116
0x0000FC
IFS7
IEC7
IPC29
AN7 Conversion Done
125
117
0x0000FE
IFS7
IEC7
IPC29
—
—
—
IPC35
Reserved
126-149 118-141 0x000100-0x00012E
IPC28
ICD – ICD Application
150
142
0x000130
IFS8
IEC8
JTAG – JTAG Programming
151
143
0x000132
IFS8
IEC8 IPC35
Reserved
—
—
—
AN8 Conversion Done
159
151
0x000142
IFS9
IEC9
IPC37
AN9 Conversion Done
160
152
0x000144
IFS9
IEC9
IPC38
AN10 Conversion Done
161
153
0x000146
IFS9
IEC9
IPC38
AN11 Conversion Done
162
154
0x000148
IFS9
IEC9
IPC38
AN12 Conversion Done
163
155
0x00014A
IFS9
IEC9 IPC38
AN13 Conversion Done
164
156
0x00014C
IFS9
IEC9
AN14 Conversion Done
165
157
0x00014E
IFS9
IEC9
IPC39
AN15 Conversion Done
166
158
0x000150
IFS9
IEC9
IPC39
AN16 Conversion Done
167
159
0x000152
IFS9
IEC9 IPC39
AN17 Conversion Done
168
160
0x000154
IFS10
IEC10
AN18 Conversion Done
169
161
0x000156
IFS10
IEC10
IPC40
AN19 Conversion Done
170
162
0x000158
IFS10
IEC10
IPC40
AN20 Conversion Done
171
163
0x00015A
IFS10
IEC10 IPC40
172
164
0x00015C
IFS10
IEC10
—
—
AN21 Conversion Done
Reserved
152-158 144-150 0x000134-0x000140
173-180 165-172 0x00015C-0x00016C
IPC39
IPC40
IPC41
—
I2C1 – I2C1 Bus Collision
181
173
0x00016E
IFS10 IEC10
I2C2 – I2C2 Bus Collision
182
174
0x000170
IFS10 IEC10 IPC43
Reserved
ADCMP0 – ADC Digital Comparator 0
183-184 175-176 0x000172-0x000174
185
177
0x000176
IPC43
—
—
—
IFS11
IEC11
IPC44
IPC44
ADCMP1 – ADC Digital Comparator 1
186
178
0x000178
IFS11
IEC11
ADFLTR0 – ADC Filter 0
187
179
0x00017A
IFS11
IEC11 IPC44
188
180
0x00017C
IFS11
IEC11
IPC45
—
—
—
ADFLTR1 – ADC Filter 1
Reserved
2013-2017 Microchip Technology Inc.
189-253 181-245 0x00017E-0x0001FE
DS70005127D-page 93
dsPIC33EPXXGS50X FAMILY
7.3
7.4.3
Interrupt Resources
IECx
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
7.3.1
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt sources can be assigned to one of seven
priority levels.
KEY RESOURCES
• “Interrupts” (DS70000600) in the “dsPIC33/
PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
7.4
Interrupt Control and Status
Registers
dsPIC33EPXXGS50X family devices implement the
following registers for the interrupt controller:
•
•
•
•
•
INTCON1
INTCON2
INTCON3
INTCON4
INTTREG
7.4.1
Global interrupt control functions are controlled from
INTCON1, INTCON2, INTCON3 and INTCON4.
INTCON1 contains the Interrupt Nesting Disable bit
(NSTDIS), as well as the control and status flags for the
processor trap sources.
The INTCON2 register controls external interrupt
request signal behavior, contains the Global Interrupt
Enable bit (GIE) and the Alternate Interrupt Vector Table
Enable bit (AIVTEN).
INTCON3 contains the status flags for the Auxiliary
PLL and DO stack overflow status trap sources.
7.4.2
Software
IFSx
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
DS70005127D-page 94
7.4.5
IPCx
INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number (VECNUM) and Interrupt Level bits
(ILR) fields in the INTTREG register. The new
Interrupt Priority Level is the priority of the pending
interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0, the INT0IE bit in IEC0 and the
INT0IP bits in the first position of IPC0
(IPC0).
7.4.6
INTCON1 THROUGH INTCON4
The INTCON4 register contains the
Generated Hard Trap Status bit (SGHT).
7.4.4
STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers refer to
“CPU” (DS70359) in the “dsPIC33/PIC24 Family
Reference Manual”.
• The CPU STATUS Register, SR, contains the
IPL bits (SR). These bits indicate the
current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
• The CORCON register contains the IPL3 bit
which, together with IPL, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt registers are described in Register 7-3
through Register 7-7 in the following pages.
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
SR: CPU STATUS REGISTER(1)
REGISTER 7-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/C-0
R/C-0
R-0
R/W-0
OA
OB
SA
SB
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
IPL2(2)
IPL1
(2)
R/W-0(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’= Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
IPL: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 7-5
Note 1:
2:
3:
For complete register details, see Register 3-1.
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when the NSTDIS bit (INTCON1) = 1.
2013-2017 Microchip Technology Inc.
DS70005127D-page 95
dsPIC33EPXXGS50X FAMILY
CORCON: CORE CONTROL REGISTER(1)
REGISTER 7-2:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-0
VAR
—
US1
US0
EDT
DL2
DL1
DL0
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-0
R/C-0
R-0
R/W-0
R/W-0
SATA
SATB
SATDW
ACCSAT
IPL3(2)
SFA
RND
IF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’= Bit is set
‘0’ = Bit is cleared
bit 15
VAR: Variable Exception Processing Latency Control bit
1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1:
2:
x = Bit is unknown
For complete register details, see Register 3-2.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level.
DS70005127D-page 96
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SFTACERR
DIV0ERR
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap is disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B is enabled
0 = Trap is disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 5
Unimplemented: Read as ‘0’
bit 4
MATHERR: Math Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 97
dsPIC33EPXXGS50X FAMILY
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as ‘0’
DS70005127D-page 98
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
GIE
DISI
SWTRAP
—
—
—
—
AIVTEN
bit 15
bit 8
U-0
U-0
U-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
INT4EP
—
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
GIE: Global Interrupt Enable bit
1 = Interrupts and associated IE bits are enabled
0 = Interrupts are disabled, but traps are still enabled
bit 14
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13
SWTRAP: Software Trap Status bit
1 = Software trap is enabled
0 = Software trap is disabled
bit 12-9
Unimplemented: Read as ‘0’
bit 8
AIVTEN: Alternate Interrupt Vector Table Enable
1 = Uses Alternate Interrupt Vector Table
0 = Uses standard Interrupt Vector Table
bit 7-5
Unimplemented: Read as ‘0’
bit 4
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 3
Unimplemented: Read as ‘0’
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 99
dsPIC33EPXXGS50X FAMILY
REGISTER 7-5:
INTCON3: INTERRUPT CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
NAE
bit 15
bit 8
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
R/W-0
—
—
—
DOOVR
—
—
—
APLL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-9
Unimplemented: Read as ‘0’
bit 8
NAE: NVM Address Error Soft Trap Status bit
1 = NVM address error soft trap has occurred
0 = NVM address error soft trap has not occurred
bit 7-5
Unimplemented: Read as ‘0’
bit 4
DOOVR: DO Stack Overflow Soft Trap Status bit
1 = DO stack overflow soft trap has occurred
0 = DO stack overflow soft trap has not occurred
bit 3-1
Unimplemented: Read as ‘0’
bit 0
APLL: Auxiliary PLL Loss of Lock Soft Trap Status bit
1 = APLL lock soft trap has occurred
0 = APLL lock soft trap has not occurred
REGISTER 7-6:
x = Bit is unknown
INTCON4: INTERRUPT CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
SGHT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1
Unimplemented: Read as ‘0’
bit 0
SGHT: Software Generated Hard Trap Status bit
1 = Software generated hard trap has occurred
0 = Software generated hard trap has not occurred
DS70005127D-page 100
x = Bit is unknown
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 7-7:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM7
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
ILR: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7-0
VECNUM: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use
•
•
•
00001001 = 9, IC1 – Input Capture 1
00001000 = 8, INT0 – External Interrupt 0
00000111 = 7, Reserved; do not use
00000110 = 6, Generic soft error trap
00000101 = 5, Reserved; do not use
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 101
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 102
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
8.0
OSCILLATOR CONFIGURATION
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer
to “Oscillator Module” (DS70005131) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2013-2017 Microchip Technology Inc.
The dsPIC33EPXXGS50X family oscillator system
provides:
• On-chip Phase-Locked Loop (PLL) to boost
internal operating frequency on select internal and
external oscillator sources
• On-the-fly clock switching between various clock
sources
• Doze mode for system power savings
• Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or
shutdown
• Configuration bits for clock source selection
• Auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 8-1.
DS70005127D-page 103
dsPIC33EPXXGS50X FAMILY
FIGURE 8-1:
OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator (POSC)
DOZE
POSCCLK
XT, HS, EC
S3
FPLLO
PLL
S1
OSC2
F
XTPLL, HSPLL,
ECPLL, FRCPLL
S2
S1/S3
DOZE
OSC1
VCO(1)
FCY(2)
POSCMD
FP(2)
FRCCLK
÷2
FRCDIV
FRC
Oscillator
FRCDIVN
FOSC
S7
REFERENCE CLOCK OUTPUT
TUN
FRCDIV
÷ 16
FRCDIV16
FRC
LPRC
LPRC
Oscillator
S6
S0
POSCCLK
REFCLKO
÷N
RPn
FOSC
ROSEL
S5
Clock Fail
Clock Switch
Reset
S0
NOSC
FNOSC
RODIV
WDT, PWRT,
FSCM
AUXILIARY CLOCK GENERATOR CIRCUIT BLOCK DIAGRAM
FRCCLK
POSCCLK
FVCO(1)
1
APLL x 16
1
Note 1:
ACLK
PWM/ADC
to LFSR
0
0
ASRCSEL
÷N
1
0
GND
0
1
FRCSEL
ENAPLL
SELACLK APSTSCLR(4)
See Figure 8-2 for the source of the FVCO signal.
2:
FP refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will
be different when Doze mode is used in any ratio other than 1:1.
3:
The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR = 111) for proper operation of
the PWM and ADC modules.
DS70005127D-page 104
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
8.1
Instruction execution speed or device operating
frequency, FCY, is given by Equation 8-1.
CPU Clocking System
The dsPIC33EPXXGS50X family of devices provides
six system clock options:
EQUATION 8-1:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop
(FRCPLL)
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
FIGURE 8-2:
FCY = FOSC/2
Figure 8-2 is a block diagram of the PLL module.
Equation 8-2 provides the relationship between Input
Frequency (FIN) and Output Frequency (FPLLO).
Equation 8-3 provides the relationship between Input
Frequency (FIN) and VCO Frequency (FVCO).
PLL BLOCK DIAGRAM
0.8 MHz < FPLLI(1) < 8.0 MHz
FIN
DEVICE OPERATING
FREQUENCY
FPLLI
÷ N1
FPLLO(1) 120 MHz @ +125ºC
FPLLO(1) 140 MHz @ +85ºC
120 MHZ < FVCO(1) < 340 MHZ
PFD
VCO
FVCO
PLLPRE
FOSC
÷ N2
PLLPOST
÷M
PLLDIV
Note 1:
This frequency range must be met at all times.
EQUATION 8-2:
FPLLO CALCULATION
FPLLO = FIN
(
PLLDIV + 2
M
= FIN (PLLPRE + 2) 2(PLLPOST + 1)
N1
)
(
)
Where:
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
EQUATION 8-3:
FVCO CALCULATION
FVCO = FIN
2013-2017 Microchip Technology Inc.
PLLDIV + 2
M
= FIN (PLLPRE + 2)
N1
()
(
)
DS70005127D-page 105
dsPIC33EPXXGS50X FAMILY
TABLE 8-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
See
Notes
POSCMD FNOSC
Fast RC Oscillator with Divide-by-n (FRCDIVN)
Internal
xx
111
1, 2
Fast RC Oscillator with Divide-by-16
Internal
xx
110
1
Low-Power RC Oscillator (LPRC)
Internal
xx
101
1
Primary Oscillator (HS) with PLL (HSPLL)
Primary
10
011
Primary Oscillator (XT) with PLL (XTPLL)
Primary
01
011
Primary Oscillator (EC) with PLL (ECPLL)
Primary
00
011
Primary Oscillator (HS)
Primary
10
010
Primary Oscillator (XT)
Primary
01
010
Primary Oscillator (EC)
Primary
00
010
1
Fast RC Oscillator (FRC) with Divide-by-N and
PLL (FRCPLL)
Internal
xx
001
1
Fast RC Oscillator (FRC)
Internal
xx
000
1
Note 1:
2:
8.2
1
OSC2 pin function is determined by the OSCIOFNC Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
Auxiliary Clock Generation
The auxiliary clock generation is used for peripherals
that need to operate at a frequency unrelated to the
system clock, such as PWM or ADC.
The primary oscillator and internal FRC oscillator
sources can be used with an Auxiliary PLL (APLL) to
obtain the auxiliary clock. The Auxiliary PLL has a fixed
16x multiplication factor.
The auxiliary clock has the following configuration
restrictions:
• For proper PWM operation, auxiliary clock
generation must be configured for 120 MHz (see
Parameter OS56 in Section 26.0 “Electrical Characteristics”). If a slower frequency is desired, the
PWM Input Clock Prescaler (Divider) Select bits
(PCLKDIV) should be used.
• To achieve 1.04 ns PWM resolution, the auxiliary
clock must use the 16x Auxiliary PLL (APLL). All
other clock sources will have a minimum PWM
resolution of 8 ns.
• If the primary PLL is used as a source for the
auxiliary clock, the primary PLL should be configured up to a maximum operation of 30 MIPS or
less.
DS70005127D-page 106
8.3
Reference Clock Generation
The reference clock output logic provides the user with
the ability to output a clock signal based on the system
clock or the crystal oscillator on a device pin. The user
application can specify a wide range of clock scaling
prior to outputting the reference clock.
8.4
Oscillator Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
8.4.1
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
8.5
Oscillator Control Registers
OSCCON: OSCILLATOR CONTROL REGISTER(1)
REGISTER 8-1:
U-0
R-0
R-0
R-0
U-0
R/W-y
R/W-y
R/W-y
—
COSC2
COSC1
COSC0
—
NOSC2(2)
NOSC1(2)
NOSC0(2)
bit 15
bit 8
R/W-0
R/W-0
R-0
U-0
R/W-0
U-0
U-0
R/W-0
CLKLOCK
IOLOCK
LOCK
—
CF(3)
—
—
OSWEN
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit
1 = If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and
PLL configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
bit 6
IOLOCK: I/O Lock Enable bit
1 = I/O lock is active
0 = I/O lock is not active
bit 5
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1:
2:
3:
Writes to this register require an unlock sequence.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.
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REGISTER 8-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 4
Unimplemented: Read as ‘0’
bit 3
CF: Clock Fail Detect bit(3)
1 = FSCM has detected a clock failure
0 = FSCM has not detected a clock failure
bit 2-1
Unimplemented: Read as ‘0’
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to the selection specified by the NOSC bits
0 = Oscillator switch is complete
Note 1:
2:
3:
Writes to this register require an unlock sequence.
Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.
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REGISTER 8-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
ROI
DOZE2(1)
DOZE1(1)
DOZE0(1)
DOZEN(2,3)
FRCDIV2
FRCDIV1
FRCDIV0
bit 15
bit 8
R/W-0
R/W-1
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST1
PLLPOST0
—
PLLPRE4
PLLPRE3
PLLPRE2
PLLPRE1
PLLPRE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE: Processor Clock Reduction Select bits(1)
111 = FCY divided by 128
110 = FCY divided by 64
101 = FCY divided by 32
100 = FCY divided by 16
011 = FCY divided by 8 (default)
010 = FCY divided by 4
001 = FCY divided by 2
000 = FCY divided by 1
bit 11
DOZEN: Doze Mode Enable bit(2,3)
1 = DOZE field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio is forced to 1:1
bit 10-8
FRCDIV: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
bit 7-6
PLLPOST: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
bit 5
Unimplemented: Read as ‘0’
Note 1:
2:
3:
The DOZE bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE are ignored.
This bit is cleared when the ROI bit is set and an interrupt occurs.
The DOZEN bit cannot be set if DOZE = 000. If DOZE = 000, any attempt by user software to
set the DOZEN bit is ignored.
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REGISTER 8-2:
bit 4-0
CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
PLLPRE: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
Note 1:
2:
3:
The DOZE bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE are ignored.
This bit is cleared when the ROI bit is set and an interrupt occurs.
The DOZEN bit cannot be set if DOZE = 000. If DOZE = 000, any attempt by user software to
set the DOZEN bit is ignored.
REGISTER 8-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
PLLDIV8
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PLLDIV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8-0
PLLDIV: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2
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REGISTER 8-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
TUN: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation of 1.457% (7.477 MHz)
011110 = Center frequency + 1.41% (7.474 MHz)
•
•
•
000001 = Center frequency + 0.047% (7.373 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency – 0.047% (7.367 MHz)
•
•
•
100001 = Center frequency – 1.457% (7.263 MHz)
100000 = Minimum frequency deviation of -1.5% (7.259 MHz)
Note 1:
x = Bit is unknown
OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
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REGISTER 8-5:
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
R/W-0
R-0
ENAPLL
APLLCK
R/W-1
U-0
U-0
SELACLK
—
—
R/W-1
R/W-1
R/W-1
APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 15
bit 8
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
ASRCSEL
FRCSEL
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ENAPLL: Auxiliary PLL Enable bit
1 = APLL is enabled
0 = APLL is disabled
bit 14
APLLCK: APLL Locked Status bit (read-only)
1 = Indicates that Auxiliary PLL is in lock
0 = Indicates that Auxiliary PLL is not in lock
bit 13
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary oscillators provide the source clock for the auxiliary clock divider
0 = Primary PLL (FVCO) provides the source clock for the auxiliary clock divider
bit 12-11
Unimplemented: Read as ‘0’
bit 10-8
APSTSCLR: Auxiliary Clock Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256
bit 7
ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary oscillator is the clock source
0 = No clock input is selected
bit 6
FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1 = Selects the FRC clock for Auxiliary PLL
0 = Input clock source is determined by the ASRCSEL bit setting
bit 5-0
Unimplemented: Read as ‘0’
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REGISTER 8-6:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ROON
—
ROSSLP
ROSEL
RODIV3(1)
RODIV2(1)
RODIV1(1)
RODIV0(1)
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ROON: Reference Oscillator Output Enable bit
1 = Reference oscillator output is enabled on the RPn pin(2)
0 = Reference oscillator output is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep
0 = Reference oscillator output is disabled in Sleep
bit 12
ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8
RODIV: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768
1110 = Reference clock divided by 16,384
1101 = Reference clock divided by 8,192
1100 = Reference clock divided by 4,096
1011 = Reference clock divided by 2,048
1010 = Reference clock divided by 1,024
1001 = Reference clock divided by 512
1000 = Reference clock divided by 256
0111 = Reference clock divided by 128
0110 = Reference clock divided by 64
0101 = Reference clock divided by 32
0100 = Reference clock divided by 16
0011 = Reference clock divided by 8
0010 = Reference clock divided by 4
0001 = Reference clock divided by 2
0000 = Reference clock
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
This pin is remappable. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.
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REGISTER 8-7:
U-0
LFSR: LINEAR FEEDBACK SHIFT REGISTER
R/W-0
R/W-0
R/W-0
—
R/W-0
R/W-0
R/W-0
R/W-0
LFSR
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LFSR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-0
LFSR: Pseudorandom Data bits
DS70005127D-page 114
x = Bit is unknown
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dsPIC33EPXXGS50X FAMILY
9.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Watchdog Timer and
Power-Saving Modes” (DS70615) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXGS50X family devices provide the
ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals.
In general, a lower clock frequency and a reduction
in the number of peripherals being clocked
constitutes lower consumed power.
9.1
The dsPIC33EPXXGS50X family devices allow a wide
range of clock frequencies to be selected under application control. If the system clock configuration is not
locked, users can choose low-power or high-precision
oscillators by simply changing the NOSCx bits
(OSCCON). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in Section 8.0
“Oscillator Configuration”.
9.2
Clock Frequency
Instruction-Based Sleep and Idle modes
Software-Controlled Doze mode
Selective Peripheral Control in Software
Instruction-Based Power-Saving
Modes
The dsPIC33EPXXGS50X family devices have two
special power-saving modes that are entered
through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all
code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 9-1.
Note:
dsPIC33EPXXGS50X family devices can manage
power consumption in four ways:
•
•
•
•
Clock Frequency and Clock
Switching
SLEEP_MODE and IDLE_MODE are constants defined in the assembler include
file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
EXAMPLE 9-1:
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into Sleep mode
; Put the device into Idle mode
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9.2.1
SLEEP MODE
9.2.2
IDLE MODE
The following occurs in Sleep mode:
The following occurs in Idle mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals can continue
to operate. This includes items such as the Input
Change Notification on the I/O ports or peripherals
that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled.
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 9.4
“Peripheral Module Disable”).
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device wakes up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
For optimal power savings, the internal regulator and
the Flash regulator can be configured to go into standby when Sleep mode is entered by clearing the VREGS
(RCON) and VREGSF (RCON) bits (default
configuration).
The device wakes from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAV instruction or the first instruction in the ISR.
All peripherals also have the option to discontinue
operation when Idle mode is entered to allow for
increased power savings. This option is selectable in
the control register of each peripheral (for example, the
TSIDL bit in the Timer1 Control register (T1CON).
9.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
If the application requires a faster wake-up time, and
can accept higher current requirements, the VREGS
(RCON) and VREGSF (RCON) bits can be set
to keep the internal regulator and the Flash regulator
active during Sleep mode.
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9.3
Doze Mode
9.4
Peripheral Module Disable
The preferred strategies for reducing power consumption are changing clock speed and invoking one of the
power-saving modes. In some circumstances, this
cannot be practical. For example, it may be necessary
for an application to maintain uninterrupted synchronous communication, even while it is doing nothing
else. Reducing system clock speed can introduce
communication errors, while using a power-saving
mode can stop communications completely.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have any effect and
read values are invalid.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
A peripheral module is enabled only if both the associated bit in the PMD register is cleared and the peripheral
is supported by the specific dsPIC® DSC variant. If the
peripheral is present in the device, it is enabled in the
PMD register by default.
Doze mode is enabled by setting the DOZEN bit
(CLKDIV). The ratio between peripheral and core
clock speed is determined by the DOZE bits
(CLKDIV). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default
setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV). By default, interrupt events
have no effect on Doze mode operation.
2013-2017 Microchip Technology Inc.
Note:
9.5
If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control registers are already configured to enable
module operation).
Power-Saving Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
9.5.1
KEY RESOURCES
• “Watchdog Timer and Power-Saving Modes”
(DS70615) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005127D-page 117
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REGISTER 9-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0
T5MD
bit 15
R/W-0
T4MD
R/W-0
I2C1MD
bit 7
R/W-0
U2MD
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
R/W-0
T2MD
R/W-0
T1MD
U-0
—
R/W-0
PWMMD
U-0
—
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 15
R/W-0
T3MD
R/W-0
U1MD
R/W-0
SPI2MD
W = Writable bit
‘1’ = Bit is set
R/W-0
SPI1MD
U-0
—
U-0
—
R/W-0
ADCMD
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
T5MD: Timer5 Module Disable bit
1 = Timer5 module is disabled
0 = Timer5 module is enabled
T4MD: Timer4 Module Disable bit
1 = Timer4 module is disabled
0 = Timer4 module is enabled
T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled
0 = Timer3 module is enabled
T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled
0 = Timer2 module is enabled
T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled
0 = Timer1 module is enabled
Unimplemented: Read as ‘0’
PWMMD: PWMx Module Disable bit
1 = PWMx module is disabled
0 = PWMx module is enabled
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
U2MD: UART2 Module Disable bit
1 = UART2 module is disabled
0 = UART2 module is enabled
U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
SPI2MD: SPI2 Module Disable bit
1 = SPI2 module is disabled
0 = SPI2 module is enabled
SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
Unimplemented: Read as ‘0’
ADCMD: ADC Module Disable bit
1 = ADC module is disabled
0 = ADC module is enabled
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REGISTER 9-2:
PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
IC4MD
IC3MD
IC2MD
IC1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11
IC4MD: Input Capture 4 Module Disable bit
1 = Input Capture 4 module is disabled
0 = Input Capture 4 module is enabled
bit 10
IC3MD: Input Capture 3 Module Disable bit
1 = Input Capture 3 module is disabled
0 = Input Capture 3 module is enabled
bit 9
IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-4
Unimplemented: Read as ‘0’
bit 3
OC4MD: Output Compare 4 Module Disable bit
1 = Output Compare 4 module is disabled
0 = Output Compare 4 module is enabled
bit 2
OC3MD: Output Compare 3 Module Disable bit
1 = Output Compare 3 module is disabled
0 = Output Compare 3 module is enabled
bit 1
OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0
OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 119
dsPIC33EPXXGS50X FAMILY
REGISTER 9-3:
PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
—
—
—
—
—
CMPMD
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
I2C2MD
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
bit 9-2
Unimplemented: Read as ‘0’
bit 1
I2C2MD: I2C2 Module Disable bit
1 = I2C2 module is disabled
0 = I2C2 module is enabled
bit 0
Unimplemented: Read as ‘0’
REGISTER 9-4:
x = Bit is unknown
PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
—
—
—
—
REFOMD
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
REFOMD: Reference Clock Module Disable bit
1 = Reference clock module is disabled
0 = Reference clock module is enabled
bit 2-0
Unimplemented: Read as ‘0’
DS70005127D-page 120
x = Bit is unknown
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 9-5:
PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
PWM5MD
PWM4MD
PWM3MD
PWM2MD
PWM1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12
PWM5MD: PWM5 Module Disable bit
1 = PWM5 module is disabled
0 = PWM5 module is enabled
bit 11
PWM4MD: PWM4 Module Disable bit
1 = PWM4 module is disabled
0 = PWM4 module is enabled
bit 10
PWM3MD: PWM3 Module Disable bit
1 = PWM3 module is disabled
0 = PWM3 module is enabled
bit 9
PWM2MD: PWM2 Module Disable bit
1 = PWM2 module is disabled
0 = PWM2 module is enabled
bit 8
PWM1MD: PWM1 Module Disable bit
1 = PWM1 module is disabled
0 = PWM1 module is enabled
bit 7-0
Unimplemented: Read as ‘0’
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 121
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REGISTER 9-6:
PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
CMP4MD
CMP3MD
CMP2MD
CMP1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
PGA1MD
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11
CMP4MD: CMP4 Module Disable bit
1 = CMP4 module is disabled
0 = CMP4 module is enabled
bit 10
CMP3MD: CMP3 Module Disable bit
1 = CMP3 module is disabled
0 = CMP3 module is enabled
bit 9
CMP2MD: CMP2 Module Disable bit
1 = CMP2 module is disabled
0 = CMP2 module is enabled
bit 8
CMP1MD: CMP1 Module Disable bit
1 = CMP1 module is disabled
0 = CMP1 module is enabled
bit 7-2
Unimplemented: Read as ‘0’
bit 1
PGA1MD: PGA1 Module Disable bit
1 = PGA1 module is disabled
0 = PGA1 module is enabled
bit 0
Unimplemented: Read as ‘0’
DS70005127D-page 122
x = Bit is unknown
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dsPIC33EPXXGS50X FAMILY
REGISTER 9-7:
PMD8: PERIPHERAL MODULE DISABLE CONTROL REGISTER 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
—
—
PGA2MD
ABGMD
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
CCSMD
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
PGA2MD: PGA2 Module Disable bit
1 = PGA2 module is disabled
0 = PGA2 module is enabled
bit 9
ABGMD: Band Gap Reference Voltage Disable bit
1 = Band gap reference voltage is disabled
0 = Band gap reference voltage is enabled
bit 8-2
Unimplemented: Read as ‘0’
bit 1
CCSMD: Constant-Current Source Module Disable bit
1 = Constant-current source module is disabled
0 = Constant-current source module is enabled
bit 0
Unimplemented: Read as ‘0’
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 123
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NOTES:
DS70005127D-page 124
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dsPIC33EPXXGS50X FAMILY
10.0
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 10-1 illustrates how ports are shared with other peripherals and
the associated I/O pin to which they are connected.
I/O PORTS
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer
to “I/O Ports” (DS70000598) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com).
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin can
be read, but the output driver for the parallel port bit is
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin can be driven by a port.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Many of the device pins are shared among the peripherals and the Parallel I/O ports. All I/O input ports feature
Schmitt Trigger inputs for improved noise immunity.
10.1
Parallel I/O (PIO) Ports
Generally, a Parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
FIGURE 10-1:
All port pins have eight registers directly associated with
their operation as digital I/Os. The Data Direction register
(TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. Reads
from the latch (LATx), read the latch. Writes to the latch,
write the latch. Reads from the port (PORTx), read the
port pins, while writes to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device are disabled.
This means the corresponding LATx and TRISx
registers, and the port pin are read as zeros.
When a pin is shared with another peripheral or function that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs.
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
I/O
1
Peripheral Output Data
Output Enable
0
PIO Module
WR TRISx
Output Data
0
Read TRISx
Data Bus
1
D
Q
I/O Pin
CK
TRISx Latch
D
WR LATx +
WR PORTx
Q
CK
Data Latch
Read LATx
Input Data
Read PORTx
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10.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx and TRISx registers
for data control, port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control x register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of outputs other than VDD by using external pull-up resistors.
The maximum open-drain voltage allowed on any pin
is the same as the maximum VIH specification for that
particular pin.
See the “Pin Diagrams” section for the available
5V tolerant pins and Table 26-11 for the maximum
VIH specification for each pin.
10.2
Configuring Analog and Digital
Port Pins
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs or outputs must have their corresponding
ANSELx and TRISx bits set. In order to use port pins for
I/O functionality with digital modules, such as timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
10.3
The Input Change Notification function of the I/O ports
allows devices to generate interrupt requests to the
processor in response to a Change-of-State (COS) on
selected input pins. This feature can detect input
Change-of-States, even in Sleep mode, when the
clocks are disabled. Every I/O port pin can be selected
(enabled) for generating an interrupt request on a
Change-of-State.
Three control registers are associated with the ICN
functionality of each I/O port. The CNENx registers
contain the ICN interrupt enable control bits for each of
the input pins. Setting any of these bits enables an ICN
interrupt for the corresponding pins.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups and pulldowns act as a current source, or sink source,
connected to the pin, and eliminate the need for
external resistors when push button or keypad
devices are connected. The pull-ups and pull-downs
are enabled separately, using the CNPUx and the
CNPDx registers, which contain the control bits for
each of the pins. Setting any of the control bits
enables the weak pull-ups and/or pull-downs for the
corresponding pins.
Note:
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
Pins with analog functions affected by the ANSELx
registers are listed with a buffer type of analog in the
Pinout I/O Descriptions (see Table 1-1).
If the TRISx bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
comparator module.
When the PORTx register is read, all pins configured as
analog input channels are read as cleared (a low level).
Input Change Notification (ICN)
Pull-ups and pull-downs on Input Change
Notification pins should always be
disabled when the port pin is configured
as a digital output.
EXAMPLE 10-1:
MOV
0xFF00, W0
MOV
W0, TRISB
NOP
BTSS
PORTB, #13
PORT WRITE/READ
EXAMPLE
;
;
;
;
;
;
Configure PORTB
as inputs
and PORTB
as outputs
Delay 1 cycle
Next Instruction
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin, defined as a
digital input (including the ANx pins), can cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP, as shown in Example 10-1.
DS70005127D-page 126
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10.4
Peripheral Pin Select (PPS)
A major challenge in general purpose devices is
providing the largest possible set of peripheral features,
while minimizing the conflict of features on I/O pins.
The challenge is even greater on low pin count devices.
In an application where more than one peripheral
needs to be assigned to a single pin, inconvenient
work arounds in application code, or a complete
redesign, may be the only option.
Peripheral Pin Select configuration provides an alternative to these choices by enabling peripheral set
selection and placement on a wide range of I/O pins.
By increasing the pinout options available on a particular device, users can better tailor the device to their
entire application, rather than trimming the application
to fit the device.
The Peripheral Pin Select configuration feature
operates over a fixed subset of digital I/O pins. Users
may independently map the input and/or output of most
digital peripherals to any one of these I/O pins. Hardware safeguards are included that prevent accidental
or spurious changes to the peripheral mapping once it
has been established.
10.4.1
AVAILABLE PINS
The number of available pins is dependent on the particular device and its pin count. Pins that support the
Peripheral Pin Select feature include the label, “RPn”,
in their full pin designation, where “n” is the remappable
pin number. “RP” is used to designate pins that support
both remappable input and output functions.
10.4.2
AVAILABLE PERIPHERALS
The peripherals managed by the Peripheral Pin Select
are all digital only peripherals. These include general
serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.
2013-2017 Microchip Technology Inc.
In comparison, some digital only peripheral modules
are never included in the Peripheral Pin Select feature.
This is because the peripheral’s function requires
special I/O circuitry on a specific port and cannot be
easily connected to multiple pins. One example
includes I2C modules. A similar requirement excludes
all modules with analog inputs, such as the ADC
Converter.
A key difference between remappable and nonremappable peripherals is that remappable peripherals
are not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/O and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
10.4.3
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select features are controlled through
two sets of SFRs: one to map peripheral inputs and one
to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the
peripheral has both) can be placed on any selectable
function pin without constraint.
The association of a peripheral to a peripheralselectable pin is handled in two different ways,
depending on whether an input or output is being
mapped.
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10.4.4
10.4.4.1
INPUT MAPPING
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. That is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 10-1
through Register 10-19). Each register contains sets of
8-bit fields, with each set associated with one of the
remappable peripherals. Programming a given peripheral’s bit field with an appropriate 8-bit value maps the
RPn pin with the corresponding value to that peripheral.
For any given device, the valid range of values for any
bit field corresponds to the maximum number of
Peripheral Pin Selections supported by the device.
Virtual Connections
The dsPIC33EPXXGS50X devices support six virtual
RPn pins (RP176-RP181), which are identical in
functionality to all other RPn pins, with the exception of
pinouts. These six pins are internal to the devices and
are not connected to a physical device pin.
These pins provide a simple way for inter-peripheral
connection without utilizing a physical pin. For
example, the output of the analog comparator can be
connected to RP176 and the PWM Fault input can be
configured for RP176 as well. This configuration allows
the analog comparator to trigger PWM Faults without
the use of an actual physical pin on the device.
For example, Figure 10-2 illustrates remappable pin
selection for the U1RX input.
FIGURE 10-2:
REMAPPABLE INPUT FOR
U1RX
U1RXR
0
RP0
1
RP1
2
U1RX Input
to Peripheral
RP2
n
RPn
Note:
For input only, Peripheral Pin Select functionality does not have priority over TRISx
settings. Therefore, when configuring an
RPn pin for input, the corresponding bit in
the TRISx register must also be configured
for input (set to ‘1’).
DS70005127D-page 128
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TABLE 10-1:
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Input Name(1)
Function Name
Register
Configuration Bits
External Interrupt 1
INT1
RPINR0
INT1R
External Interrupt 2
INT2
RPINR1
INT2R
Timer1 External Clock
T1CK
RPINR2
T1CKR
Timer2 External Clock
T2CK
RPINR3
T2CKR
Timer3 External Clock
T3CK
RPINR3
T3CKR
Input Capture 1
IC1
RPINR7
IC1R
Input Capture 2
IC2
RPINR7
IC2R
Input Capture 3
IC3
RPINR8
IC3R
Input Capture 4
IC4
RPINR8
IC4R
Output Compare Fault A
OCFA
RPINR11
OCFAR
PWM Fault 1
FLT1
RPINR12
FLT1R
PWM Fault 2
FLT2
RPINR12
FLT2R
PWM Fault 3
FLT3
RPINR13
FLT3R
PWM Fault 4
FLT4
RPINR13
FLT4R
UART1 Receive
UART1 Clear-to-Send
UART2 Receive
U1RX
RPINR18
U1RXR
U1CTS
RPINR18
U1CTSR
U2RX
RPINR19
U2RXR
U2CTS
RPINR19
U2CTSR
SPI1 Data Input
SDI1
RPINR20
SDI1R
SPI1 Clock Input
SCK1
RPINR20
SCK1R
SPI1 Slave Select
SS1
RPINR21
SS1R
SPI2 Data Input
SDI2
RPINR22
SDI2R
SPI2 Clock Input
SCK2
RPINR22
SCK2R
SPI2 Slave Select
SS2
RPINR23
SS2R
PWM Synch Input 1
SYNCI1
RPINR37
SYNCI1R
PWM Synch Input 2
SYNCI2
RPINR38
SYNCI2R
PWM Fault 5
FLT5
RPINR42
FLT5R
PWM Fault 6
FLT6
RPINR42
FLT6R
PWM Fault 7
FLT7
RPINR43
FLT7R
PWM Fault 8
FLT8
RPINR43
FLT8R
UART2 Clear-to-Send
Note 1:
Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
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10.4.5
10.4.5.1
OUTPUT MAPPING
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains sets of 6-bit fields, with each set
associated with one RPn pin (see Register 10-20
through Register 10-38). The value of the bit field corresponds to one of the peripherals and that peripheral’s
output is mapped to the pin (see Table 10-2 and
Figure 10-3).
Mapping Limitations
The control schema of the peripheral select pins is not
limited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced
lockouts between any of the peripheral mapping SFRs.
Literally any combination of peripheral mappings,
across any or all of the RPn pins, is possible. This
includes both many-to-one and one-to-many mappings
of peripheral inputs, and outputs to pins. While such
mappings may be technically possible from a configuration point of view, they may not be supportable from
an electrical point of view.
A null output is associated with the output register
Reset value of ‘0’. This is done to ensure that remappable outputs remain disconnected from all output pins
by default.
FIGURE 10-3:
MULTIPLEXING REMAPPABLE
OUTPUTS FOR RPn
RPnR
Default
U1TX Output
SDO2 Output
0
1
2
Output Data
PWM5H Output
PWM5L Output
DS70005127D-page 130
RPn
53
54
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TABLE 10-2:
Function
Default PORT
OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
RPnR
000000
Output Name
RPn tied to Default Pin
U1TX
000001
RPn tied to UART1 Transmit
U1RTS
000010
RPn tied to UART1 Request-to-Send
U2TX
000011
RPn tied to UART2 Transmit
U2RTS
000100
RPn tied to UART2 Request-to-Send
SDO1
000101
RPn tied to SPI1 Data Output
SCK1
000110
RPn tied to SPI1 Clock Output
SS1
000111
RPn tied to SPI1 Slave Select
SDO2
001000
RPn tied to SPI2 Data Output
SCK2
001001
RPn tied to SPI2 Clock Output
SS2
001010
RPn tied to SPI2 Slave Select
OC1
010000
RPn tied to Output Compare 1 Output
OC2
010001
RPn tied to Output Compare 2 Output
OC3
010010
RPn tied to Output Compare 3 Output
OC4
010011
RPn tied to Output Compare 4 Output
ACMP1
011000
RPn tied to Analog Comparator 1 Output
ACMP2
011001
RPn tied to Analog Comparator 2 Output
ACMP3
011010
RPn tied to Analog Comparator 3 Output
SYNCO1
101101
RPn tied to PWM Primary Master Time Base Sync Output
SYNCO2
101110
RPn tied to PWM Secondary Master Time Base Sync Output
REFCLKO
110001
RPn tied to Reference Clock Output
ACMP4
110010
RPn tied to Analog Comparator 4 Output
PWM4H
110011
RPn tied to PWM Output Pins Associated with PWM Generator 4
PWM4L
110100
RPn tied to PWM Output Pins Associated with PWM Generator 4
PWM5H
110101
RPn tied to PWM Output Pins Associated with PWM Generator 5
PWM5L
110110
RPn tied to PWM Output Pins Associated with PWM Generator 5
2013-2017 Microchip Technology Inc.
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10.5
1.
2.
I/O Helpful Tips
In some cases, certain pins, as defined in
Table 26-11 under “Injection Current”, have internal protection diodes to VDD and VSS. The term,
“Injection Current”, is also referred to as “Clamp
Current”. On designated pins, with sufficient external current-limiting precautions by the user, I/O pin
input voltages are allowed to be greater or less
than the data sheet absolute maximum ratings,
with respect to the VSS and VDD supplies. Note
that when the user application forward biases
either of the high or low side internal input clamp
diodes, that the resulting current being injected
into the device, that is clamped internally by the
VDD and VSS power rails, may affect the ADC
accuracy by four to six counts.
I/O pins that are shared with any analog input pin
(i.e., ANx) are always analog pins by default after
any Reset. Consequently, configuring a pin as an
analog input pin automatically disables the digital
input pin buffer and any attempt to read the digital
input level by reading PORTx or LATx will always
return a ‘0’, regardless of the digital logic level on
the pin. To use a pin as a digital I/O pin on a shared
ANx pin, the user application needs to configure the
Analog Pin Configuration registers in the I/O ports
module (i.e., ANSELx) by setting the appropriate bit
that corresponds to that I/O port pin to a ‘0’.
Note:
Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would
create signal contention between the
analog signal and the output pin driver.
DS70005127D-page 132
3.
4.
5.
Most I/O pins have multiple functions. Referring to
the device pin diagrams in this data sheet, the priorities of the functions allocated to any pins are
indicated by reading the pin name from left-to-right.
The left most function name takes precedence over
any function to its right in the naming convention.
For example: AN16/T2CK/T7CK/RC1; this indicates that AN16 is the highest priority in this
example and will supersede all other functions to its
right in the list. Those other functions to its right,
even if enabled, would not work as long as any
other function to its left was enabled. This rule
applies to all of the functions listed for a given pin.
Each pin has an internal weak pull-up resistor and
pull-down resistor that can be configured using the
CNPUx and CNPDx registers, respectively. These
resistors eliminate the need for external resistors
in certain applications. The internal pull-up is up to
~(VDD – 0.8), not VDD. This value is still above the
minimum VIH of CMOS and TTL devices.
When driving LEDs directly, the I/O pin can source
or sink more current than what is specified in the
VOH/IOH and VOL/IOL DC characteristics specification. The respective IOH and IOL current rating only
applies to maintaining the corresponding output at
or above the VOH, and at or below the VOL levels.
However, for LEDs, unlike digital inputs of an externally connected device, they are not governed by
the same minimum VIH/VIL levels. An I/O pin output
can safely sink or source any current less than that
listed in the Absolute Maximum Ratings in
Section 26.0 “Electrical Characteristics”of this
data sheet. For example:
VOH = 2.4v @ IOH = -8 mA and VDD = 3.3V
The maximum output current sourced by any 8 mA
I/O pin = 12 mA.
LED source current < 12 mA is technically permitted.
Refer to the VOH/IOH graphs in Section 27.0 “DC
and AC Device Characteristics Graphs” for
additional information.
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
6.
The Peripheral Pin Select (PPS) pin mapping rules
are as follows:
a) Only one “output” function can be active on a
given pin at any time, regardless if it is a
dedicated or remappable function (one pin,
one output).
b) It is possible to assign a “remappable output”
function to multiple pins and externally short or
tie them together for increased current drive.
c) If any “dedicated output” function is enabled
on a pin, it will take precedence over any
remappable “output” function.
d) If any “dedicated digital” (input or output) function is enabled on a pin, any number of “input”
remappable functions can be mapped to the
same pin.
e) If any “dedicated analog” function(s) are
enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “digital output”, at the user’s cautionary discretion,
can be enabled and active as long as there is
no signal contention with an external analog
input signal. For example, it is possible for the
ADC to convert the digital output logic level, or
to toggle a digital output on a comparator or
ADC input, provided there is no external
analog input, such as for a built-in self-test.
f) Any number of “input” remappable functions
can be mapped to the same pin(s) at the same
time, including to any pin with a single output
from either a dedicated or remappable “output”.
g) The TRISx registers control only the digital I/O
output buffer. Any other dedicated or remappable active “output” will automatically override
the TRISx setting. The TRISx register does not
control the digital logic “input” buffer. Remappable digital “inputs” do not automatically
override TRISx settings, which means that the
TRISx bit must be set to input for pins with only
remappable input function(s) assigned.
h) All analog pins are enabled by default after any
Reset and the corresponding digital input buffer
on the pin has been disabled. Only the Analog
Pin Select x (ANSELx) registers control the digital input buffer, not the TRISx register. The user
must disable the analog function on a pin using
the Analog Pin Select x registers in order to use
any “digital input(s)” on a corresponding pin, no
exceptions.
2013-2017 Microchip Technology Inc.
10.6
I/O Ports Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
10.6.1
KEY RESOURCES
• “I/O Ports” (DS70000598) in the “dsPIC33/PIC24
Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005127D-page 133
dsPIC33EPXXGS50X FAMILY
10.7
Peripheral Pin Select Registers
REGISTER 10-1:
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT1R7
INT1R6
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
INT1R: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
Unimplemented: Read as ‘0’
REGISTER 10-2:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2R7
INT2R6
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
INT2R: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
DS70005127D-page 134
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REGISTER 10-3:
RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKR7
T1CKR6
T1CKR5
T1CKR4
T1CKR3
T1CKR2
T1CKR1
T1CKR0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
T1CKR: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
Unimplemented: Read as ‘0’
2013-2017 Microchip Technology Inc.
DS70005127D-page 135
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REGISTER 10-4:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CKR7
T3CKR6
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2CKR7
T2CKR6
T2CKR5
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
T3CKR: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
0000001 = Input tied to RP1
0000000 = Input tied to VSS
bit 7-0
T2CKR: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
DS70005127D-page 136
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REGISTER 10-5:
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC2R7
IC2R6
IC2R5
IC2R4
IC2R3
IC2R2
IC2R1
IC2R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC1R7
IC1R6
IC1R5
IC1R4
IC1R3
IC1R2
IC1R1
IC1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
IC2R: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
IC1R: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
2013-2017 Microchip Technology Inc.
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REGISTER 10-6:
RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC4R7
IC4R6
IC4R5
IC4R4
IC4R3
IC4R2
IC4R1
IC4R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IC3R7
IC3R6
IC3R5
IC3R4
IC3R3
IC3R2
IC3R1
IC3R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
IC4R: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
IC3R: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
DS70005127D-page 138
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REGISTER 10-7:
RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OCFAR7
OCFAR6
OCFAR5
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
OCFAR: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
2013-2017 Microchip Technology Inc.
DS70005127D-page 139
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REGISTER 10-8:
RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT2R7
FLT2R6
FLT2R5
FLT2R4
FLT2R3
FLT2R2
FLT2R1
FLT2R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT1R7
FLT1R6
FLT1R5
FLT1R4
FLT1R3
FLT1R2
FLT1R1
FLT1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
FLT2R: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
FLT1R: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
DS70005127D-page 140
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REGISTER 10-9:
RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT4R7
FLT4R6
FLT4R5
FLT4R4
FLT4R3
FLT4R2
FLT4R1
FLT4R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT3R7
FLT3R6
FLT3R5
FLT3R4
FLT3R3
FLT3R2
FLT3R1
FLT3R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
FLT4R: Assign PWM Fault 4 (FLT4) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
FLT3R: Assign PWM Fault 3 (FLT3) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
2013-2017 Microchip Technology Inc.
DS70005127D-page 141
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REGISTER 10-10: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U1CTSR7
U1CTSR6
U1CTSR5
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U1RXR7
U1RXR6
U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
U1CTSR: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
U1RXR: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
DS70005127D-page 142
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REGISTER 10-11: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2CTSR7
U2CTSR6
U2CTSR5
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
U2CTSR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2RXR7
U2RXR6
U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
U2CTSR: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
U2RXR: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
2013-2017 Microchip Technology Inc.
DS70005127D-page 143
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REGISTER 10-12: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCK1INR7
SCK1INR6
SCK1INR5
SCK1INR4
SCK1INR3
SCK1INR2
SCK1INR1
SCK1INR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI1R7
SDI1R6
SDI1R5
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
SCK1INR: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
SDI1R: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
DS70005127D-page 144
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REGISTER 10-13: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS1R7
SS1R6
SS1R5
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
SS1R: Assign SPI1 Slave Select (SS1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
2013-2017 Microchip Technology Inc.
DS70005127D-page 145
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REGISTER 10-14: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCK2INR7
SCK2INR6
SCK2INR5
SCK2INR4
SCK2INR3
SCK2INR2
SCK2INR1
SCK2INR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI2R7
SDI2R6
SDI2R5
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
SCK2INR: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
SDI2R: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
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REGISTER 10-15: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS2R7
SS2R6
SS2R5
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
SS2R: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
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REGISTER 10-16: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCI1R7
SYNCI1R6
SYNCI1R5
SYNCI1R4
SYNCI1R3
SYNCI1R2
SYNCI1R1
SYNCI1R0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
SYNCI1R: Assign PWM Synchronization Input 1 to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 10-17: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCI2R7
SYNCI2R6
SYNCI2R5
SYNCI2R4
SYNCI2R3
SYNCI2R2
SYNCI2R1
SYNCI2R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
SYNCI2R: Assign PWM Synchronization Input 2 to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
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REGISTER 10-18: RPINR42: PERIPHERAL PIN SELECT INPUT REGISTER 42
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT6R7
FLT6R6
FLT6R5
FLT6R4
FLT6R3
FLT6R2
FLT6R1
FLT6R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT5R7
FLT5R6
FLT5R5
FLT5R4
FLT5R3
FLT5R2
FLT5R1
FLT5R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
FLT6R: Assign PWM Fault 6 (FLT6) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
FLT5R: Assign PWM Fault 5 (FLT5) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
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REGISTER 10-19: RPINR43: PERIPHERAL PIN SELECT INPUT REGISTER 43
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT8R7
FLT8R6
FLT8R5
FLT8R4
FLT8R3
FLT8R2
FLT8R1
FLT8R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT7R7
FLT7R6
FLT7R5
FLT7R4
FLT7R3
FLT7R2
FLT7R1
FLT7R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
FLT8R: Assign PWM Fault 8 (FLT8) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
bit 7-0
FLT7R: Assign PWM Fault 7 (FLT7) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
10110100 = Input tied to RP180
•
•
•
00000001 = Input tied to RP1
00000000 = Input tied to VSS
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REGISTER 10-20: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP33R5
RP33R4
RP33R3
RP33R2
RP33R1
RP33R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP32R5
RP32R4
RP32R3
RP32R2
RP32R1
RP32R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP33R: Peripheral Output Function is Assigned to RP33 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP32R: Peripheral Output Function is Assigned to RP32 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-21: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP35R5
RP35R4
RP35R3
RP35R2
RP35R1
RP35R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP34R5
RP34R4
RP34R3
RP34R2
RP34R1
RP34R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP35R: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP34R: Peripheral Output Function is Assigned to RP34 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-22: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP37R5
RP37R4
RP37R3
RP37R2
RP37R1
RP37R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP36R5
RP36R4
RP36R3
RP36R2
RP36R1
RP36R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP37R: Peripheral Output Function is Assigned to RP37 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP36R: Peripheral Output Function is Assigned to RP36 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-23: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP39R5
RP39R4
RP39R3
RP39R2
RP39R1
RP39R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP38R5
RP38R4
RP38R3
RP38R2
RP38R1
RP38R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP39R: Peripheral Output Function is Assigned to RP39 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP38R: Peripheral Output Function is Assigned to RP38 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-24: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP41R5
RP41R4
RP41R3
RP41R2
RP41R1
RP41R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP40R5
RP40R4
RP40R3
RP40R2
RP40R1
RP40R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP41R: Peripheral Output Function is Assigned to RP41 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP40R: Peripheral Output Function is Assigned to RP40 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-25: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP43R5
RP43R4
RP43R3
RP43R2
RP43R1
RP43R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP42R5
RP42R4
RP42R3
RP42R2
RP42R1
RP42R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP43R: Peripheral Output Function is Assigned to RP43 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP42R: Peripheral Output Function is Assigned to RP42 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-26: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP45R5
RP45R4
RP45R3
RP45R2
RP45R1
RP45R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP44R5
RP44R4
RP44R3
RP44R2
RP44R1
RP44R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP45R: Peripheral Output Function is Assigned to RP45 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP44R: Peripheral Output Function is Assigned to RP44 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-27: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP47R5
RP47R4
RP47R3
RP47R2
RP47R1
RP47R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP46R5
RP46R4
RP46R3
RP46R2
RP46R1
RP46R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP47R: Peripheral Output Function is Assigned to RP47 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP46R: Peripheral Output Function is Assigned to RP46 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-28: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP49R5
RP49R4
RP49R3
RP49R2
RP49R1
RP49R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP48R5
RP48R4
RP48R3
RP48R2
RP48R1
RP48R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP49R: Peripheral Output Function is Assigned to RP49 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP48R: Peripheral Output Function is Assigned to RP48 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-29: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP51R5
RP51R4
RP51R3
RP51R2
RP51R1
RP51R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP50R5
RP50R4
RP50R3
RP50R2
RP50R1
RP50R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP51R: Peripheral Output Function is Assigned to RP51 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP50R: Peripheral Output Function is Assigned to RP50 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-30: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP53R5
RP53R4
RP53R3
RP53R2
RP53R1
RP53R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP52R5
RP52R4
RP52R3
RP52R2
RP52R1
RP52R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP53R: Peripheral Output Function is Assigned to RP53 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP52R: Peripheral Output Function is Assigned to RP52 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-31: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP55R5
RP55R4
RP55R3
RP55R2
RP55R1
RP55R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP54R5
RP54R4
RP54R3
RP54R2
RP54R1
RP54R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP55R: Peripheral Output Function is Assigned to RP55 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP54R: Peripheral Output Function is Assigned to RP54 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-32: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP57R5
RP57R4
RP57R3
RP57R2
RP57R1
RP57R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP56R5
RP56R4
RP56R3
RP56R2
RP56R1
RP56R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP57R: Peripheral Output Function is Assigned to RP57 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP56R: Peripheral Output Function is Assigned to RP56 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-33: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP59R5
RP59R4
RP59R3
RP59R2
RP59R1
RP59R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP58R5
RP58R4
RP58R3
RP58R2
RP58R1
RP58R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP59R: Peripheral Output Function is Assigned to RP59 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP58R: Peripheral Output Function is Assigned to RP58 Output Pin bits
(see Table 10-2 for peripheral function numbers)
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REGISTER 10-34: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP61R5
RP61R4
RP61R3
RP61R2
RP61R1
RP61R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP60R5
RP60R4
RP60R3
RP60R2
RP60R1
RP60R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP61R: Peripheral Output Function is Assigned to RP61 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP60R: Peripheral Output Function is Assigned to RP60 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-35: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP63R5
RP63R4
RP63R3
RP63R2
RP63R1
RP63R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP62R5
RP62R4
RP62R3
RP62R2
RP62R1
RP62R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP63R: Peripheral Output Function is Assigned to RP63 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP62R: Peripheral Output Function is Assigned to RP62 Output Pin bits
(see Table 10-2 for peripheral function numbers)
2013-2017 Microchip Technology Inc.
DS70005127D-page 159
dsPIC33EPXXGS50X FAMILY
REGISTER 10-36: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP177R5
RP177R4
RP177R3
RP177R2
RP177R1
RP177R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP176R5
RP176R4
RP176R3
RP176R2
RP176R1
RP176R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP177R: Peripheral Output Function is Assigned to RP177 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP176R: Peripheral Output Function is Assigned to RP176 Output Pin bits
(see Table 10-2 for peripheral function numbers)
REGISTER 10-37: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP179R5
RP179R4
RP179R3
RP179R2
RP179R1
RP179R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP178R5
RP178R4
RP178R3
RP178R2
RP178R1
RP178R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP179R: Peripheral Output Function is Assigned to RP179 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP178R: Peripheral Output Function is Assigned to RP178 Output Pin bits
(see Table 10-2 for peripheral function numbers)
DS70005127D-page 160
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 10-38: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP181R5
RP181R4
RP181R3
RP181R2
RP181R1
RP181R0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
RP180R5
RP180R4
RP180R3
RP180R2
RP180R1
RP180R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-8
RP181R: Peripheral Output Function is Assigned to RP181 Output Pin bits
(see Table 10-2 for peripheral function numbers)
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
RP180R: Peripheral Output Function is Assigned to RP180 Output Pin bits
(see Table 10-2 for peripheral function numbers)
2013-2017 Microchip Technology Inc.
DS70005127D-page 161
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 162
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
11.0
The Timer1 module can operate in one of the following
modes:
TIMER1
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70362) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
•
•
•
•
Timer mode
Gated Timer mode
Synchronous Counter mode
Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON
• Timer Synchronization Control bit (TSYNC):
T1CON
• Timer Gate Control bit (TGATE): T1CON
The Timer1 module is a 16-bit timer that can operate as
a free-running interval timer/counter.
Timer control bit settings for different operating modes
are provided in Table 11-1.
The Timer1 module has the following unique features
over other timers:
TABLE 11-1:
• Can be Operated in Asynchronous Counter mode
from an External Clock Source
• The External Clock Input (T1CK) can Optionally be
Synchronized to the Internal Device Clock and the
Clock Synchronization is Performed after the
Prescaler
Mode
A block diagram of Timer1 is shown in Figure 11-1.
FIGURE 11-1:
TIMER MODE SETTINGS
TCS
TGATE
TSYNC
Timer
0
0
x
Gated Timer
0
1
x
Synchronous
Counter
1
x
1
Asynchronous
Counter
1
x
0
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Falling Edge
Detect
Gate
Sync
1
Set T1IF Flag
0
FP(1)
Prescaler
(/n)
10
T1CLK
TGATE
00
TCKPS
TMR1
Reset
CLK
0
T1CK
x1
Prescaler
(/n)
Sync
TCKPS
Note 1:
Comparator
1
TSYNC
Latch
Data
ADC Trigger
Equal
TGATE
TCS
PR1
FP is the peripheral clock.
2013-2017 Microchip Technology Inc.
DS70005127D-page 163
dsPIC33EPXXGS50X FAMILY
11.1
Timer1 Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
DS70005127D-page 164
11.1.1
KEY RESOURCES
• “Timers” (DS70362) in the “dsPIC33/PIC24
Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
11.2
Timer1 Control Register
REGISTER 11-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON(1)
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
—
TSYNC(1)
TCS(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timer1 On bit(1)
1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
Unimplemented: Read as ‘0’
bit 2
TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge)
0 = Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
2013-2017 Microchip Technology Inc.
DS70005127D-page 165
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 166
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
12.0
TIMER2/3 AND TIMER4/5
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70362) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent
16-bit timers with selectable operating modes.
As 32-bit timers, Timer2/3 and Timer4/5 operate in
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with All 16-Bit Operating modes (except
Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
•
•
•
•
•
Timer Gate Operation
Selectable Prescaler Settings
Timer Operation during Idle and Sleep modes
Interrupt on a 32-Bit Period Register Match
Time Base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
2013-2017 Microchip Technology Inc.
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON
and T5CON registers. T2CON and T4CON are shown
in generic form in Register 12-1. T3CON and T5CON
are shown in Register 12-2.
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word (lsw); Timer3 and Timer5
are the most significant word (msw) of the 32-bit timers.
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
A block diagram for an example 32-bit timer pair
(Timer2/3 and Timer4/5) is shown in Figure 12-2.
12.1
Timer Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
12.1.1
KEY RESOURCES
• “Timers” (DS70362) in the “dsPIC33/PIC24
Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005127D-page 167
dsPIC33EPXXGS50X FAMILY
FIGURE 12-1:
TIMERx BLOCK DIAGRAM (x = 2 THROUGH 5)
Falling Edge
Detect
Gate
Sync
1
Set TxIF Flag
0
FP(1)
Prescaler
(/n)
10
TxCLK
TGATE
TMRx
00
TCKPS
Data
Latch
CLK
TxCK
Prescaler
(/n)
Sync
x1
Comparator
ADC
Trigger(2)
Equal
TGATE
TCKPS
TCS
Note 1:
2:
Reset
PRx
FP is the peripheral clock.
The ADC trigger is only available on TMR2.
FIGURE 12-2:
TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
Falling Edge
Detect
Gate
Sync
1
Set TyIF Flag
PRx
PRy
0
Equal
Comparator
FP(1)
TxCK
Prescaler
(/n)
10
TCKPS
00
Prescaler
(/n)
Data
lsw
Sync
msw
TMRx
TGATE
TMRy
Latch
CLK
Reset
x1
TMRyHLD
TCKPS
TGATE
TCS
Data Bus
Note 1:
2:
Timerx is a Type B timer (x = 2 and 4).
Timery is a Type C timer (y = 3 and 5).
DS70005127D-page 168
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
12.2
Timer Control Registers
REGISTER 12-1:
TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON
—
TSIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
TON: Timerx On bit
When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timerx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 2
Unimplemented: Read as ‘0’
bit 1
TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge)
0 = Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
The TxCK pin is not available on all devices. Refer to the “Pin Diagrams” section for the available pins.
2013-2017 Microchip Technology Inc.
DS70005127D-page 169
dsPIC33EPXXGS50X FAMILY
REGISTER 12-2:
TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
TON(1)
—
TSIDL(2)
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
—
TGATE(1)
TCKPS1(1)
TCKPS0(1)
—
—
TCS(1,3)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TON: Timery On bit(1)
1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 14
Unimplemented: Read as ‘0’
bit 13
TSIDL: Timery Stop in Idle Mode bit(2)
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4
TCKPS: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3-2
Unimplemented: Read as ‘0’
bit 1
TCS: Timery Clock Source Select bit(1,3)
1 = External clock is from pin, TyCK (on the rising edge)
0 = Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
When 32-bit operation is enabled (TxCON = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
The TyCK pin is not available on all devices. See the “Pin Diagrams” section for the available pins.
DS70005127D-page 170
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
13.0
INPUT CAPTURE
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in this
data sheet, refer to “Input Capture”
(DS70000352) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The input capture module is useful in applications
requiring frequency (period) and pulse measurements.
The dsPIC33EPXXGS50X family devices support four
input capture channels.
Key features of the input capture module include:
• Hardware-Configurable for 32-Bit Operation in All
modes by Cascading Two Adjacent Modules
FIGURE 13-1:
• Synchronous and Trigger modes of Output
Compare Operation, with up to 21 User-Selectable
Trigger/Sync Sources Available
• A 4-Level FIFO Buffer for Capturing and Holding
Timer Values for Several Events
• Configurable Interrupt Generation
• Up to Six Clock Sources Available for Each Module,
Driving a Separate Internal 16-Bit Counter
13.1
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
13.1.1
KEY RESOURCES
• “Input Capture” (DS70000352) in the “dsPIC33/
PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM
ICI
Event and
Interrupt
Logic
Edge Detect Logic
and
Clock Synchronizer
Prescaler
Counter
1:1/4/16
ICx Pin
Input Capture Resources
Set ICxIF
ICTSEL
Increment
Clock
Select
ICx Clock
Sources
Trigger and
Sync Sources
Trigger and Reset
Sync Logic
SYNCSEL(1)
Note 1:
16
ICxTMR
4-Level FIFO Buffer
16
16
ICxBUF
ICOV, ICBNE
System Bus
The trigger/sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the trigger/sync source must be changed to another source option.
2013-2017 Microchip Technology Inc.
DS70005127D-page 171
dsPIC33EPXXGS50X FAMILY
13.2
Input Capture Registers
REGISTER 13-1:
ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R-0, HC, HS
R-0, HC, HS
R/W-0
R/W-0
R/W-0
—
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
ICSIDL: Input Capture x Stop in Idle Control bit
1 = Input capture will halt in CPU Idle mode
0 = Input capture will continue to operate in CPU Idle mode
bit 12-10
ICTSEL: Input Capture x Timer Select bits
111 = Peripheral clock (FP) is the clock source of the ICx
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the ICx
010 = T4CLK is the clock source of the ICx
001 = T2CLK is the clock source of the ICx
000 = T3CLK is the clock source of the ICx
bit 9-7
Unimplemented: Read as ‘0’
bit 6-5
ICI: Number of Captures per Interrupt Select bits (this field is not used if ICM = 001 or 111)
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture buffer overflow has occurred
0 = No input capture buffer overflow has occurred
bit 3
ICBNE: Input Capture x Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0
ICM: Input Capture x Mode Select bits
111 = Input Capture x functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every rising and falling edge (Edge Detect mode, ICI, is not used in this mode)
000 = Input Capture x is turned off
DS70005127D-page 172
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 13-2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
IC32
bit 15
bit 8
R/W-0
R/W-0, HS
U-0
ICTRIG(2)
TRIGSTAT(3)
—
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented: Read as ‘0’
bit 8
IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)
1 = Odd ICx and even ICx form a single 32-bit input capture module(1)
0 = Cascade module operation is disabled
bit 7
ICTRIG: Input Capture x Trigger Operation Select bit(2)
1 = Input source is used to trigger the input capture timer (Trigger mode)
0 = Input source is used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
bit 6
TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
bit 5
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
5:
The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
The input source is selected by the SYNCSEL bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL bits); it can be read, set and
cleared in software.
Do not use the ICx module as its own sync or trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
2013-2017 Microchip Technology Inc.
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REGISTER 13-2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
SYNCSEL: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = No sync or trigger source for ICx
11110 = Reserved
11101 = Reserved
11100 = Reserved
11011 = CMP4 module synchronizes or triggers ICx(5)
11010 = CMP3 module synchronizes or triggers ICx(5)
11001 = CMP2 module synchronizes or triggers ICx(5)
11000 = CMP1 module synchronizes or triggers ICx(5)
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 module interrupt synchronizes or triggers ICx
10010 = IC3 module interrupt synchronizes or triggers ICx
10001 = IC2 module interrupt synchronizes or triggers ICx
10000 = IC1 module interrupt synchronizes or triggers ICx
01111 = Timer5 synchronizes or triggers ICx
01110 = Timer4 synchronizes or triggers ICx
01101 = Timer3 synchronizes or triggers ICx (default)
01100 = Timer2 synchronizes or triggers ICx
01011 = Timer1 synchronizes or triggers ICx
01010 = Reserved
01001 = Reserved
01000 = IC4 module synchronizes or triggers ICx
00111 = IC3 module synchronizes or triggers ICx
00110 = IC2 module synchronizes or triggers ICx
00101 = IC1 module synchronizes or triggers ICx
00100 = OC4 module synchronizes or triggers ICx
00011 = OC3 module synchronizes or triggers ICx
00010 = OC2 module synchronizes or triggers ICx
00001 = OC1 module synchronizes or triggers ICx
00000 = No sync or trigger source for ICx
bit 4-0
Note 1:
2:
3:
4:
5:
The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
The input source is selected by the SYNCSEL bits of the ICxCON2 register.
This bit is set by the selected input source (selected by SYNCSEL bits); it can be read, set and
cleared in software.
Do not use the ICx module as its own sync or trigger source.
This option should only be selected as a trigger source and not as a synchronization source.
DS70005127D-page 174
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
14.0
single output pulse, or a sequence of output pulses, by
changing the state of the output pin on the compare
match events. The output compare module can also
generate interrupts on compare match events.
OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Output Compare with
Dedicated Timer” (DS70005159) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
14.1
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
14.1.1
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
KEY RESOURCES
• “Output Compare with Dedicated Timer”
(DS70005159) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
The output compare module can select one of six
available clock sources for its time base. The module
compares the value of the timer with the value of one or
two Compare registers, depending on the operating
mode selected. The state of the output pin changes
when the timer value matches the Compare register
value. The output compare module generates either a
FIGURE 14-1:
Output Compare Resources
OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1
OCxCON2
OCxR
Rollover/Reset
OCxR Buffer
Clock
Select
OCx Clock
Sources
Increment
Comparator
OCxTMR
Reset
Trigger and
Sync Sources
Trigger and
Sync Logic
Match Event
Comparator
OCx Pin
Match
Event
Rollover
OCx Output and
Fault Logic
OCFA
Match
Event
OCxRS Buffer
SYNCSEL
Trigger(1)
Rollover/Reset
OCxRS
OCx Synchronization/Trigger Event
OCx Interrupt
Reset
Note 1:
The trigger/sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the trigger/sync source must be changed to another source option.
2013-2017 Microchip Technology Inc.
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14.2
Output Compare Control Registers
REGISTER 14-1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
—
—
OCSIDL
OCTSEL2
OCTSEL1
OCTSEL0
—
—
bit 15
bit 8
R/W-0
U-0
U-0
R/W-0, HSC
R/W-0
R/W-0
R/W-0
R/W-0
ENFLTA
—
—
OCFLTA
TRIGMODE
OCM2
OCM1
OCM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10
OCTSEL: Output Compare x Clock Select bits
111 = Peripheral clock (FP)
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the OCx
010 = T4CLK is the clock source of the OCx
001 = T3CLK is the clock source of the OCx
000 = T2CLK is the clock source of the OCx
bit 9-8
Unimplemented: Read as ‘0’
bit 7
ENFLTA: Fault A Input Enable bit
1 = Output Compare Fault A input (OCFA) is enabled
0 = Output Compare Fault A input (OCFA) is disabled
bit 6-5
Unimplemented: Read as ‘0’
bit 4
OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on the OCFA pin has occurred
0 = No PWM Fault A condition on the OCFA pin has occurred
bit 3
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
Note 1:
OCxR and OCxRS are double-buffered in PWM mode only.
DS70005127D-page 176
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 14-1:
bit 2-0
Note 1:
OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
OCM: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output is set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output is set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces OCx
pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces OCx
pin high
000 = Output compare channel is disabled
OCxR and OCxRS are double-buffered in PWM mode only.
2013-2017 Microchip Technology Inc.
DS70005127D-page 177
dsPIC33EPXXGS50X FAMILY
REGISTER 14-2:
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
FLTMD
FLTOUT
FLTTRIEN
OCINV
—
—
—
OC32
bit 15
bit 8
R/W-0
R/W-0, HS
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
OCTRIG
TRIGSTAT
OCTRIS
SYNCSEL4
SYNCSEL3
SYNCSEL2
SYNCSEL1
SYNCSEL0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTMD: Fault Mode Select bit
1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTA bit is
cleared in software and a new PWMx period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWMx period starts
bit 14
FLTOUT: Fault Out bit
1 = PWMx output is driven high on a Fault
0 = PWMx output is driven low on a Fault
bit 13
FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition
0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
bit 12
OCINV: Output Compare x Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 11-9
Unimplemented: Read as ‘0’
bit 8
OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7
OCTRIG: Output Compare x Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits
0 = Synchronizes OCx with the source designated by the SYNCSELx bits
bit 6
TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5
OCTRIS: Output Compare x Output Pin Direction Select bit
1 = OCx is tri-stated
0 = OCx module drives the OCx pin
Note 1:
2:
Do not use the OCx module as its own synchronization or trigger source.
When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
DS70005127D-page 178
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dsPIC33EPXXGS50X FAMILY
REGISTER 14-2:
bit 4-0
Note 1:
2:
OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
SYNCSEL: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization
11110 = INT2 pin synchronizes or triggers OCx
11101 = INT1 pin synchronizes or triggers OCx
11100 = Reserved
11011 = CMP4 module synchronizes or triggers OCx
11010 = CMP3 module synchronizes or triggers OCx
11001 = CMP2 module synchronizes or triggers OCx
11000 = CMP1 module synchronizes or triggers OCx
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 input capture interrupt event synchronizes or triggers OCx
10010 = IC3 input capture interrupt event synchronizes or triggers OCx
10001 = IC2 input capture interrupt event synchronizes or triggers OCx
10000 = IC1 input capture interrupt event synchronizes or triggers OCx
01111 = Timer5 synchronizes or triggers OCx
01110 = Timer4 synchronizes or triggers OCx
01101 = Timer3 synchronizes or triggers OCx
01100 = Timer2 synchronizes or triggers OCx (default)
01011 = Timer1 synchronizes or triggers OCx
01010 = Reserved
01001 = Reserved
01000 = IC4 input capture event synchronizes or triggers OCx
00111 = IC3 input capture event synchronizes or triggers OCx
00110 = IC2 input capture event synchronizes or triggers OCx
00101 = IC1 input capture event synchronizes or triggers OCx
00100 = OC4 module synchronizes or triggers OCx(1,2)
00011 = OC3 module synchronizes or triggers OCx(1,2)
00010 = OC2 module synchronizes or triggers OCx(1,2)
00001 = OC1 module synchronizes or triggers OCx(1,2)
00000 = No sync or trigger source for OCx
Do not use the OCx module as its own synchronization or trigger source.
When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
2013-2017 Microchip Technology Inc.
DS70005127D-page 179
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NOTES:
DS70005127D-page 180
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
15.0
Note:
HIGH-SPEED PWM
This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “High-Speed PWM
Module” (DS70000323) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com).
The high-speed PWM module on dsPIC33EPXXGS50X
devices supports a wide variety of PWM modes and
output formats. This PWM module is ideal for power
conversion applications, such as:
•
•
•
•
•
•
•
AC/DC Converters
DC/DC Converters
Power Factor Correction
Uninterruptible Power Supply (UPS)
Inverters
Battery Chargers
Digital Lighting
15.1
Features Overview
The high-speed PWM module incorporates the
following features:
• Five PWMx Generators with Two Outputs
per Generator
• Two Master Time Base Modules
• Individual Time Base and Duty Cycle for
Each PWM Output
• Duty Cycle, Dead Time, Phase Shift and a
Frequency Resolution of 1.04 ns
• Independent Fault and Current-Limit Inputs
• Redundant Output
• True Independent Output
• Center-Aligned PWM mode
• Output Override Control
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Dual Trigger from PWMx to Analog-to-Digital
Converter (ADC)
• PWMxL and PWMxH Output Pin Swapping
• Independent PWMx Frequency, Duty Cycle and
Phase-Shift Changes
• Enhanced Leading-Edge Blanking (LEB) Functionality
• PWM Capture Functionality
Note:
Figure 15-1 conceptualizes the PWM module in a
simplified block diagram. Figure 15-2 illustrates how
the module hardware is partitioned for each PWMx
output pair for the Complementary PWM mode.
The PWM module contains five PWM generators. The
module has up to 10 PWMx output pins: PWM1H/
PWM1L through PWM5H/PWM5L. For complementary
outputs, these 10 I/O pins are grouped into high/low
pairs.
15.2
Feature Description
The PWM module is designed for applications that
require:
• High resolution at high PWM frequencies
• The ability to drive Standard, Edge-Aligned,
Center-Aligned Complementary mode and
Push-Pull mode outputs
• The ability to create multiphase PWM outputs
Two common, medium power converter topologies are
push-pull and half-bridge. These designs require the
PWM output signal to be switched between alternate
pins, as provided by the Push-Pull PWM mode.
Phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
relationship between the generator outputs is
specifiable and changeable.
Multiphase PWM is often used to improve DC/DC
converter load transient response, and reduce the size
of output filter capacitors and inductors. Multiple DC/DC
converters are often operated in parallel, but phase
shifted in time. A single PWM output, operating at
250 kHz, has a period of 4 s but an array of four PWM
channels, staggered by 1 s each, yields an effective
switching frequency of 1 MHz. Multiphase PWM
applications typically use a fixed-phase relationship.
Variable phase PWM is useful in Zero Voltage
Transition (ZVT) power converters. Here, the PWM
duty cycle is always 50% and the power flow is
controlled by varying the relative phase shift between
the two PWM generators.
Duty cycle, dead time, phase shift and
frequency resolution is 8.32 ns in
Center-Aligned PWM mode.
2013-2017 Microchip Technology Inc.
DS70005127D-page 181
dsPIC33EPXXGS50X FAMILY
15.2.1
WRITE-PROTECTED REGISTERS
On dsPIC33EPXXGS50X family devices, write protection
is implemented for the IOCONx and FCLCONx registers.
The write protection feature prevents any inadvertent
writes to these registers. This protection feature can be
controlled by the PWMLOCK Configuration bit
(FDEVOPT). The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protection
feature can be disabled by configuring PWMLOCK = 0.
EXAMPLE 15-1:
To gain write access to these locked registers, the user
application must write two consecutive values (0xABCD
and 0x4321) to the PWMKEY register to perform the
unlock operation. The write access to the IOCONx or
FCLCONx registers must be the next SFR access
following the unlock process. There can be no other SFR
accesses during the unlock process and subsequent
write access. To write to both the IOCONx and
FCLCONx registers requires two unlock operations.
The correct unlocking sequence is described in
Example 15-1.
PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; Writing to FCLCON1 register requires unlock sequence
mov
mov
mov
mov
mov
mov
#0xabcd, w10
#0x4321, w11
#0x0000, w0
w10, PWMKEY
w11, PWMKEY
w0, FCLCON1
;
;
;
;
;
;
Load first unlock key to w10 register
Load second unlock key to w11 register
Load desired value of FCLCON1 register in w0
Write first unlock key to PWMKEY register
Write second unlock key to PWMKEY register
Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov
mov
mov
mov
mov
mov
15.3
#0xabcd, w10
#0x4321, w11
#0xF000, w0
w10, PWMKEY
w11, PWMKEY
w0, IOCON1
;
;
;
;
;
;
Load first unlock key to w10 register
Load second unlock key to w11 register
Load desired value of IOCON1 register in w0
Write first unlock key to PWMKEY register
Write second unlock key to PWMKEY register
Write desired value to IOCON1 register
PWM Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
DS70005127D-page 182
15.3.1
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
FIGURE 15-1:
HIGH-SPEED PWM MODULE ARCHITECTURAL DIAGRAM
SYNCI1/SYNCI2
Data Bus
Primary and Secondary
Master Time Base
Synchronization Signal
PWM1 Interrupt
SYNCO1/SYNCO2
PWM1H
PWM
Generator 1
PWM1L
Fault, Current Limit
Synchronization Signal
PWM2 Interrupt
PWM2H
PWM
Generator 2
PWM2L
CPU
Fault, Current Limit
PWM3 through PWM4
Synchronization Signal
PWM5 Interrupt
PWM5H
PWM
Generator 5
PWM5L
Primary Trigger
ADC Module
Secondary Trigger
Special Event Trigger
2013-2017 Microchip Technology Inc.
Fault and
Current Limit
DS70005127D-page 183
dsPIC33EPXXGS50X FAMILY
FIGURE 15-2:
SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWM
PTCON, PTCON2
STCON, STCON2
Module Control and Timing
SYNCI1
SYNCI2
PWMKEY
PTPER
SEVTCMP
Comparator
Comparator
SYNCO1
Special Event Compare Trigger
Special Event
Postscaler
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
PMTMR
STPER
SEVTCMP
Comparator
Comparator
Primary Master Time Base
SYNCO2
Special Event Compare Trigger
Special Event
Postscaler
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
SMTMR
Master Duty Cycle Register
PDCx
PWMx Generator 1
MUX
Master Period
Synchronization
Master Duty Cycle
16-Bit Data Bus
MDC
Secondary Master Time Base
PWMx Output Mode
Control Logic
Comparator
PWMCAPx
ADC Trigger
PTMRx
Comparator
Current-Limit
Override Logic
TRIGx
Fault Override Logic
PHASEx
SDCx
User Override Logic
Dead-Time
Logic
Pin
Control
Logic
PWM1H
PWM1L
Secondary PWMx
MUX
Comparator
Interrupt
Logic
Fault and
Current-Limit
Logic
FLTx
Master Period
SPHASEx
Master Duty Cycle
Synchronization
ADC Trigger
STMRx
Comparator
STRIGx
PWMCONx
AUXCONx
TRGCONx
FCLCONx
IOCONx
LEBCONx
ALTDTRx
DTRx
PWMxH
PWMx Generator 2 – PWMx Generator 5
PWMxL
FLTx
DS70005127D-page 184
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 15-1:
R/W-0
PTCON: PWMx TIME BASE CONTROL REGISTER
U-0
R/W-0
—
PTEN
R-0, HSC
PTSIDL
R/W-0
SESTAT
R/W-0
R/W-0
(1)
SEIEN
EIPU
R/W-0
SYNCPOL
(1)
SYNCOEN(1)
bit 15
bit 8
R/W-0
R/W-0
(1)
SYNCEN
R/W-0
(1)
SYNCSRC2
R/W-0
(1)
SYNCSRC1
R/W-0
(1)
SYNCSRC0
R/W-0
(1)
SEVTPS3
SEVTPS2
R/W-0
(1)
R/W-0
(1)
SEVTPS1
SEVTPS0(1)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PTEN: PWMx Module Enable bit
1 = PWMx module is enabled
0 = PWMx module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
PTSIDL: PWMx Time Base Stop in Idle Mode bit
1 = PWMx time base halts in CPU Idle mode
0 = PWMx time base runs in CPU Idle mode
bit 12
SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11
SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10
EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWMx cycle boundaries
bit 9
SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCIx/SYNCO1 polarity is inverted (active-low)
0 = SYNCIx/SYNCO1 is active-high
bit 8
SYNCOEN: Primary Time Base Synchronization Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4
SYNCSRC: Synchronous Source Selection bits(1)
111 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = SYNCI2
000 = SYNCI1
Note 1:
x = Bit is unknown
These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
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REGISTER 15-1:
bit 3-0
Note 1:
PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)
SEVTPS: PWMx Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates a Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event
These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
REGISTER 15-2:
PTCON2: PWMx CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
U-0
—
U-0
—
U-0
R/W-0
R/W-0
R/W-0
PCLKDIV(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
PCLKDIV: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
101 = Divide-by-32, maximum PWM timing resolution
100 = Divide-by-16, maximum PWM timing resolution
011 = Divide-by-8, maximum PWM timing resolution
010 = Divide-by-4, maximum PWM timing resolution
001 = Divide-by-2, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
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REGISTER 15-3:
R/W-1
PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER(1,2)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PTPER
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
PTPER
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PTPER: Primary Master Time Base (PMTMR) Period Value bits
The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).
REGISTER 15-4:
R/W-0
SEVTCMP: PWMx SPECIAL EVENT COMPARE REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
SEVTCMP: Special Event Compare Count Value bits
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.
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REGISTER 15-5:
STCON: PWMx SECONDARY MASTER TIME BASE CONTROL REGISTER
U-0
U-0
U-0
R-0, HSC
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
SESTAT
SEIEN
EIPU(1)
SYNCPOL
SYNCOEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCEN
SYNCSRC2
SYNCSRC1
SYNCSRC0
SEVTPS3
SEVTPS2
SEVTPS1
SEVTPS0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
SESTAT: Special Event Interrupt Status bit
1 = Secondary special event interrupt is pending
0 = Secondary special event interrupt is not pending
bit 11
SEIEN: Special Event Interrupt Enable bit
1 = Secondary special event interrupt is enabled
0 = Secondary special event interrupt is disabled
bit 10
EIPU: Enable Immediate Period Updates bit(1)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWMx cycle boundaries
bit 9
SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCIx/SYNCO2 polarity is inverted (active-low)
0 = SYNCIx/SYNCO2 polarity is active-high
bit 8
SYNCOEN: Secondary Master Time Base Synchronization Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7
SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4
SYNCSRC: Secondary Time Base Sync Source Selection bits
111 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = SYNCI2
000 = SYNCI1
bit 3-0
SEVTPS: PWMx Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postcale
0001 = 1:2 Postcale
•
•
•
0000 = 1:1 Postscale
Note 1:
This bit only applies to the secondary master time base period.
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REGISTER 15-6:
STCON2: PWMx SECONDARY CLOCK DIVIDER SELECT REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
R/W-0
PCLKDIV(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
PCLKDIV: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
101 = Divide-by-32, maximum PWM timing resolution
100 = Divide-by-16, maximum PWM timing resolution
011 = Divide-by-8, maximum PWM timing resolution
010 = Divide-by-4, maximum PWM timing resolution
001 = Divide-by-2, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1:
These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 15-7:
R/W-1
STPER: PWMx SECONDARY MASTER TIME BASE PERIOD REGISTER(1,2)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
STPER
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
STPER
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
STPER: Secondary Master Time Base (SMTMR) Period Value bits
The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).
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SSEVTCMP: PWMx SECONDARY SPECIAL EVENT COMPARE REGISTER(1)
REGISTER 15-8:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
SSEVTCMP: Special Event Compare Count Value bits
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.
CHOP: PWMx CHOP CLOCK GENERATOR REGISTER(1)
REGISTER 15-9:
R/W-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
CHPCLKEN
—
—
—
—
—
CHOPCLK6
CHOPCLK5
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
CHOPCLK4
CHOPCLK3
CHOPCLK2
CHOPCLK1
CHOPCLK0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CHPCLKEN: Enable Chop Clock Generator bit
1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 14-10
Unimplemented: Read as ‘0’
bit 9-3
CHOPCLK: Chop Clock Divider bits
Value is in 8.32 ns increments. The frequency of the chop clock signal is given by:
Chop Frequency = 1/(16.64 * (CHOP + 1) * Primary Master PWM Input Clock Period)
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
The chop clock generator operates with the primary PWMx clock prescaler (PCLKDIV) in the
PTCON2 register (Register 15-2).
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REGISTER 15-10: MDC: PWMx MASTER DUTY CYCLE REGISTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MDC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
MDC: PWMx Master Duty Cycle Value bits
The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
As the duty cycle gets closer to 0% or 100% of the PWMx period (0 to 40 ns, depending on the mode of
operation), PWMx duty cycle resolution will increase from 1 to 3 LSBs.
REGISTER 15-11: PWMKEY: PWMx PROTECTION LOCK/UNLOCK KEY REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWMKEY
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWMKEY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
PWMKEY: PWMx Protection Lock/Unlock Key Value bits
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REGISTER 15-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 5)
R-0, HSC
R-0, HSC
R-0, HSC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTSTAT(1)
CLSTAT(1)
TRGSTAT
FLTIEN
CLIEN
TRGIEN
ITB(3)
MDCS(3)
bit 15
bit 8
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
DTC1
DTC0
—
—
MTBS
CAM(2,3,4)
XPRES(5)
IUE
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLTSTAT: Fault Interrupt Status bit(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14
CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13
TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12
FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11
CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10
TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9
ITB: Independent Time Base Mode bit(3)
1 = PHASEx/SPHASEx registers provide the time base period for this PWMx generator
0 = PTPER register provides timing for this PWMx generator
bit 8
MDCS: Master Duty Cycle Register Select bit(3)
1 = MDC register provides duty cycle information for this PWMx generator
0 = PDCx and SDCx registers provide duty cycle information for this PWMx generator
Note 1:
2:
3:
4:
5:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
These bits should not be changed after the PWMx is enabled by setting PTEN = 1 (PTCON).
Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
Configure CLMOD = 0 (FCLCONx) and ITB = 1 (PWMCONx) to operate in External Period
Reset mode.
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REGISTER 15-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 5) (CONTINUED)
bit 7-6
DTC: Dead-Time Control bits
11 = Reserved
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all Output modes
bit 5-4
Unimplemented: Read as ‘0’
bit 3
MTBS: Master Time Base Select bit
1 = PWMx generator uses the secondary master time base for synchronization and the clock source
for the PWMx generation logic (if secondary time base is available)
0 = PWMx generator uses the primary master time base for synchronization and the clock source for
the PWMx generation logic
bit 2
CAM: Center-Aligned Mode Enable bit(2,3,4)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1
XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWMx generator if it is in Independent Time Base
mode
0 = External pins do not affect the PWMx time base
bit 0
IUE: Immediate Update Enable bit
1 = Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers
are immediate
0 = Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers
are synchronized to the local PWMx time base
Note 1:
2:
3:
4:
5:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
These bits should not be changed after the PWMx is enabled by setting PTEN = 1 (PTCON).
Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
Configure CLMOD = 0 (FCLCONx) and ITB = 1 (PWMCONx) to operate in External Period
Reset mode.
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REGISTER 15-13: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER (x = 1 to 5)(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PDCx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
PDCx: PWMx Generator Duty Cycle Value bits
In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the
Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both
the PWMxH and PWMxL.
The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
As the duty cycle gets closer to 0% or 100% of the PWMx period (0 to 40 ns, depending on the mode of
operation), PWMx duty cycle resolution will increase from 1 to 3 LSBs.
REGISTER 15-14: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER (x = 1 to 5)(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
3:
x = Bit is unknown
SDCx: PWMx Secondary Duty Cycle for PWMxL Output Pin bits
The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle.
The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
As the duty cycle gets closer to 0% or 100% of the PWMx period (0 to 40 ns, depending on the mode of
operation), PWMx duty cycle resolution will increase from 1 to 3 LSBs.
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REGISTER 15-15: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER (x = 1 to 5)(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
PHASEx: PWMx Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits
If PWMCONx = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx = 00, 01 or 10);
PHASEx = Phase-shift value for PWMxH and PWMxL outputs
• True Independent Output mode (IOCONx = 11); PHASEx = Phase-shift value for
PWMxH only
• When the PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;
therefore, the valid range is 0x0000 through period
If PWMCONx = 1, the following applies based on the mode of operation:
• Complementary, Redundant, and Push-Pull Output mode (IOCONx = 00, 01 or 10);
PHASEx = Independent time base period value for PWMxH and PWMxL
• True Independent Output mode (IOCONx = 11); PHASEx = Independent time base
period value for PWMxH only
• When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000 through
0xFFF8
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REGISTER 15-16: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER (x = 1 to 5)(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
Note 1:
2:
x = Bit is unknown
SPHASEx: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
If PWMCONx = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx = 00, 01 or 10);
SPHASEx = Not used
• True Independent Output mode (IOCONx = 11), PHASEx = Phase-shift value for
PWMxL only
If PWMCONx = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx = 00, 01 or 10);
SPHASEx = Not used
• True Independent Output mode (IOCONx = 11); PHASEx = Independent time base
period value for PWMxL only
• When the PHASEx/SPHASEx registers provide the local period, the valid range of values is
0x0010-0xFFF8
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REGISTER 15-17: DTRx: PWMx DEAD-TIME REGISTER (x = 1 to 5)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTRx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-0
DTRx: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 15-18: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER (x = 1 to 5)
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
Unimplemented: Read as ‘0’
bit 13-0
ALTDTRx: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
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REGISTER 15-19: TRGCONx: PWMx TRIGGER CONTROL REGISTER (x = 1 to 5)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
TRGDIV3
TRGDIV2
TRGDIV1
TRGDIV0
—
—
—
—
bit 15
bit 8
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DTM(1)
—
TRGSTRT5
TRGSTRT4
TRGSTRT3
TRGSTRT2
TRGSTRT1
TRGSTRT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
TRGDIV: Trigger # Output Divider bits
1111 = Trigger output for every 16th trigger event
1110 = Trigger output for every 15th trigger event
1101 = Trigger output for every 14th trigger event
1100 = Trigger output for every 13th trigger event
1011 = Trigger output for every 12th trigger event
1010 = Trigger output for every 11th trigger event
1001 = Trigger output for every 10th trigger event
1000 = Trigger output for every 9th trigger event
0111 = Trigger output for every 8th trigger event
0110 = Trigger output for every 7th trigger event
0101 = Trigger output for every 6th trigger event
0100 = Trigger output for every 5th trigger event
0011 = Trigger output for every 4th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
x = Bit is unknown
bit 11-8
Unimplemented: Read as ‘0’
bit 7
DTM: Dual Trigger Mode bit(1)
1 = Secondary trigger event is combined with the primary trigger event to create a PWM trigger
0 = Secondary trigger event is not combined with the primary trigger event to create a PWM trigger;
two separate PWM triggers are generated
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TRGSTRT: Trigger Postscaler Start Enable Select bits
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010 = Wait 2 PWM cycles before generating the first trigger event after the module is enabled
000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled
000000 = Wait 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1:
The secondary PWMx generator cannot generate PWM trigger interrupts.
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REGISTER 15-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 5)
R/W-1
R/W-1
PENH
PENL
R/W-0
R/W-0
POLH
POLL
R/W-0
(1)
PMOD1
R/W-0
(1)
PMOD0
R/W-0
R/W-0
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
OVRDAT1
OVRDAT0
R/W-0
FLTDAT1
(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLTDAT0(2)
CLDAT1(2)
CLDAT0(2)
SWAP
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PENH: PWMxH Output Pin Ownership bit
1 = PWMx module controls the PWMxH pin
0 = GPIO module controls the PWMxH pin
bit 14
PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls the PWMxL pin
0 = GPIO module controls the PWMxL pin
bit 13
POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12
POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10
PMOD: PWMx I/O Pin Mode bits(1)
11 = PWMx I/O pin pair is in the True Independent Output mode
10 = PWMx I/O pin pair is in the Push-Pull Output mode
01 = PWMx I/O pin pair is in the Redundant Output mode
00 = PWMx I/O pin pair is in the Complementary Output mode
bit 9
OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT1 provides data for output on the PWMxH pin
0 = PWMx generator provides data for the PWMxH pin
bit 8
OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT0 provides data for output on the PWMxL pin
0 = PWMx generator provides data for the PWMxL pin
bit 7-6
OVRDAT: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, OVRDAT1 provides data for the PWMxH pin
If OVERENL = 1, OVRDAT0 provides data for the PWMxL pin
bit 5-4
FLTDAT: State for PWMxH and PWMxL Pins if FLTMOD are Enabled bits(2)
IFLTMOD (FCLCONx) = 0: Normal Fault Mode:
If Fault is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx) = 1: Independent Fault Mode:
If current limit is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
Note 1:
2:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.
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REGISTER 15-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 5) (CONTINUED)
bit 3-2
CLDAT: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2)
IFLTMOD (FCLCONx) = 0: Normal Fault Mode:
If current limit is active, then CLDAT1 provides the state for the PWMxH pin.
If current limit is active, then CLDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx) = 1: Independent Fault Mode:
CLDAT bits are ignored.
bit 1
SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0
OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT bits are synchronized to the PWMx time base
0 = Output overrides via the OVRDAT bits occur on the next CPU clock boundary
Note 1:
2:
These bits should not be changed after the PWMx module is enabled (PTEN = 1).
State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.
REGISTER 15-21: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 5)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
TRGCMP: Trigger Compare Value bits
When the primary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 15-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 5)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFLTMOD
CLSRC4
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL(1)
CLMOD
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
FLTSRC4
FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL(1)
FLTMOD1
FLTMOD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
IFLTMOD: Independent Fault Mode Enable bit
1 = Independent Fault mode: Current-limit input maps FLTDAT1 to the PWMxH output and the Fault
input maps FLTDAT0 to the PWMxL output; the CLDAT bits are not used for override functions
0 = Normal Fault mode: Current-Limit mode maps CLDAT bits to the PWMxH and PWMxL
outputs; the PWM Fault mode maps FLTDAT to the PWMxH and PWMxL outputs
bit 14-10
CLSRC: Current-Limit Control Signal Source Select for PWMx Generator bits
11111 = Reserved
10001 = Reserved
10000 = Analog Comparator 4
01111 = Analog Comparator 3
01110 = Analog Comparator 2
01101 = Analog Comparator 1
01100 = Fault 12
01011 = Fault 11
01010 = Fault 10
01001 = Fault 9
01000 = Fault 8
00111 = Fault 7
00110 = Fault 6
00101 = Fault 5
00100 = Fault 4
00011 = Fault 3
00010 = Fault 2
00001 = Fault 1
00000 = Reserved
bit 9
CLPOL: Current-Limit Polarity for PWMx Generator bit(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8
CLMOD: Current-Limit Mode Enable for PWMx Generator bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
Note 1:
These bits should be changed only when PTEN = 0 (PTCON).
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REGISTER 15-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 5) (CONTINUED)
bit 7-3
FLTSRC: Fault Control Signal Source Select for PWMx Generator bits
11111 = Fault 31 (Default)
10001 = Reserved
10000 = Analog Comparator 4
01111 = Analog Comparator 3
01110 = Analog Comparator 2
01101 = Analog Comparator 1
01100 = Fault 12
01011 = Fault 11
01010 = Fault 10
01001 = Fault 9
01000 = Fault 8
00111 = Fault 7
00110 = Fault 6
00101 = Fault 5
00100 = Fault 4
00011 = Fault 3
00010 = Fault 2
00001 = Fault 1
00000 = Reserved
bit 2
FLTPOL: Fault Polarity for PWMx Generator bit(1)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0
FLTMOD: Fault Mode for PWMx Generator bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
00 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (latched condition)
Note 1:
These bits should be changed only when PTEN = 0 (PTCON).
REGISTER 15-23: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 5)(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRGCMP
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRGCMP
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
STRGCMP: Secondary Trigger Compare Value bits
When the secondary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
STRIGx cannot generate the PWM trigger interrupts.
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REGISTER 15-24:
LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
(x = 1 to 5)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
PHR
PHF
PLR
PLF
FLTLEBEN
CLLEBEN
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
BPHH
BPHL
BPLH
BPLL
BCH
BCL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxH
bit 14
PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxH
bit 13
PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxL
bit 12
PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxL
bit 11
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected Fault input
0 = Leading-Edge Blanking is not applied to the selected Fault input
bit 10
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected current-limit input
0 = Leading-Edge Blanking is not applied to the selected current-limit input
bit 9-6
Unimplemented: Read as ‘0’
bit 5
BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is high
0 = No blanking when the selected blanking signal is high
bit 4
BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is low
0 = No blanking when the selected blanking signal is low
bit 3
BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is high
0 = No blanking when the PWMxH output is high
bit 2
BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is low
0 = No blanking when the PWMxH output is low
Note 1:
The blanking signal is selected via the BLANKSEL bits in the AUXCONx register.
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REGISTER 15-24:
LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
(x = 1 to 5) (CONTINUED)
bit 1
BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is high
0 = No blanking when the PWMxL output is high
bit 0
BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is low
0 = No blanking when the PWMxL output is low
Note 1:
The blanking signal is selected via the BLANKSEL bits in the AUXCONx register.
REGISTER 15-25: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER (x = 1 to 5)
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
LEB
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEB
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-3
LEB: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
The value is in 8.32 ns increments.
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 15-26: AUXCONx: PWMx AUXILIARY CONTROL REGISTER (x = 1 to 5)
R/W-0
R/W-0
U-0
U-0
HRPDIS
HRDDIS
—
—
R/W-0
R/W-0
R/W-0
R/W-0
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CHOPSEL3
CHOPSEL2
CHOPSEL1
CHOPSEL0
CHOPHEN
CHOPLEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HRPDIS: High-Resolution PWMx Period Disable bit
1 = High-resolution PWMx period is disabled to reduce power consumption
0 = High-resolution PWMx period is enabled
bit 14
HRDDIS: High-Resolution PWMx Duty Cycle Disable bit
1 = High-resolution PWMx duty cycle is disabled to reduce power consumption
0 = High-resolution PWMx duty cycle is enabled
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
BLANKSEL: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM5H is selected as the state blank source
0100 = PWM4H is selected as the state blank source
0011 = PWM3H is selected as the state blank source
0010 = PWM2H is selected as the state blank source
0001 = PWM1H is selected as the state blank source
0000 = No state blanking
bit 7-6
Unimplemented: Read as ‘0’
bit 5-2
CHOPSEL: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (chop) the selected PWMx outputs.
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM5H is selected as the chop clock source
0100 = PWM4H is selected as the chop clock source
0011 = PWM3H is selected as the chop clock source
0010 = PWM2H is selected as the chop clock source
0001 = PWM1H is selected as the chop clock source
0000 = Chop clock generator is selected as the chop clock source
bit 1
CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0
CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled
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REGISTER 15-27: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER (x = 1 to 5)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PWMCAP(1,2,3,4)
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
PWMCAP(1,2,3,4)
U-0
U-0
U-0
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-3
PWMCAP: PWMx Primary Time Base Capture Value bits(1,2,3,4)
The value in this register represents the captured PWMx time base value when a leading edge is
detected on the current-limit input.
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
4:
The capture feature is only available on a primary output (PWMxH).
This feature is active only after LEB processing on the current-limit input signal is complete.
The minimum capture resolution is 8.32 ns.
This feature can be used when the XPRES bit (PWMCONx) is set to ‘0’.
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16.0
The dsPIC33EPXXGS50X device family offers two SPI
modules on a single device. These modules, which are
designated as SPI1 and SPI2, are functionally identical.
SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Serial Peripheral
Interface (SPI)” (DS70005185) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com).
Note:
The SPIx module takes advantage of the Peripheral
Pin Select (PPS) feature to allow for greater flexibility in
pin configuration.
The SPIx serial interface consists of four pins, as follows:
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
•
•
•
•
The SPI module is a synchronous serial interface,
useful for communicating with other peripherals or
microcontroller devices. These peripheral devices can
be serial EEPROMs, shift registers, display drivers,
ADC Converters, etc. The SPI module is compatible
with Motorola® SPI and SIOP interfaces.
FIGURE 16-1:
SDIx: Serial Data Input
SDOx: Serial Data Output
SCKx: Shift Clock Input or Output
SSx/FSYNCx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPIx module can be configured to operate with
two, three or four pins. In 3-Pin mode, SSx is not used.
In 2-Pin mode, neither SDOx nor SSx is used.
Figure 16-1 illustrates the block diagram of the SPIx
module in Standard and Enhanced modes.
SPIx MODULE BLOCK DIAGRAM
SCKx
SSx/FSYNCx
In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 and SPI2. Special Function
Registers follow a similar notation. For
example, SPIxCON refers to the control
register for the SPI1 and SPI2 modules.
1:1 to 1:8
Secondary
Prescaler
Sync
Control
Control
Clock
1:1/4/16/64
Primary
Prescaler
Select
Edge
SPIxCON1
Shift Control
SDOx
SPIxCON1
Enable
Master Clock
bit 0
SDIx
FP
SPIxSR
Transfer
Transfer
8-Level FIFO
8-Level FIFO
Receive Buffer(1) Transmit Buffer(1)
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
Internal Data Bus
Note 1:
In Standard mode, the FIFO is only one-level deep.
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16.1
1.
In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2) = 1, use a
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on
SSx.
Note:
2.
This will ensure that during power-up and
initialization, the master/slave will not lose
synchronization due to an errant SCKx
transition that would cause the slave to
accumulate data shift errors for both
transmit and receive, appearing as
corrupted data.
FRMEN (SPIxCON2) = 1 and SSEN
(SPIxCON1) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
frame sync pulse is active on the SSx pin, which
indicates the start of a data frame.
Note:
4.
This ensures that the first frame
transmission after initialization is not
shifted or corrupted.
In Non-Framed 3-Wire mode (i.e., not using SSx
from a master):
a) If CKP (SPIxCON1) = 1, always place a
pull-up resistor on SSx.
b) If CKP = 0, always place a pull-down
resistor on SSx.
Note:
3.
SPI Helpful Tips
To avoid invalid slave read data to the master, the
user’s master software must ensure enough time for
slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPIx Shift register
and is empty once the data transmission begins.
16.2
SPI Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
16.2.1
KEY RESOURCES
• “Serial Peripheral Interface (SPI)”
(DS70005185) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
Not all third-party devices support Frame
mode timing. Refer to the SPIx
specifications in Section 26.0 “Electrical
Characteristics” for details.
In Master mode only, set the SMP bit
(SPIxCON1) to a ‘1’ for the fastest SPIx data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit (SPIxCON1)
is set.
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16.3
SPI Control Registers
REGISTER 16-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
SPIEN
—
SPISIDL
—
—
SPIBEC2
SPIBEC1
SPIBEC0
bit 15
bit 8
R/W-0
R/C-0, HS
R/W-0
R/W-0
R/W-0
R/W-0
R-0, HS, HC
R-0, HS, HC
SRMPT
SPIROV
SRXMPT
SISEL2
SISEL1
SISEL0
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
HC = Hardware Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the module
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the module operation when device enters Idle mode
0 = Continues the module operation in Idle mode
bit 12-11
Unimplemented: Read as ‘0’
bit 10-8
SPIBEC: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master Mode:
Number of SPIx transfers that are pending.
Slave Mode:
Number of SPIx transfers that are unread.
bit 7
SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive the data
0 = SPIx Shift register is not empty
bit 6
SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user application has not read the previous
data in the SPIxBUF register
0 = No overflow has occurred
bit 5
SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2
SISEL: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty
(SRXMPT bit is set)
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REGISTER 16-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer Mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.
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REGISTER 16-2:
SPIxCON1: SPIx CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEN(2)
CKP
MSTEN
SPRE2(3)
SPRE1(3)
SPRE0(3)
PPRE1(3)
PPRE0(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
DISSCK: Disable SCKx Pin bit (SPIx Master modes only)
1 = Internal SPIx clock is disabled, pin functions as I/O
0 = Internal SPIx clock is enabled
bit 11
DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit
Master Mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave Mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7
SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by port function
bit 6
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1:
2:
3:
The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both primary and secondary prescalers to the value of 1:1.
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REGISTER 16-2:
SPIxCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
•
•
•
000 = Secondary prescale 8:1
bit 1-0
PPRE: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1:
2:
3:
The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both primary and secondary prescalers to the value of 1:1.
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REGISTER 16-3:
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
FRMDLY
SPIBEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as the frame sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 12-2
Unimplemented: Read as ‘0’
bit 1
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
bit 0
SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Standard mode)
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NOTES:
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17.0
INTER-INTEGRATED CIRCUIT
(I2C)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Inter-Integrated Circuit
(I2C)” (DS70000195) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXGS50X family of devices contains
two Inter-Integrated Circuit (I2C) modules: I2C1 and
I2C2.
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard, with a 16-bit interface.
The I2C module has a 2-pin interface:
• The SCLx/ASCLx pin is clock
• The SDAx/ASDAx pin is data
2013-2017 Microchip Technology Inc.
The I2C module offers the following key features:
• I2C Interface Supporting Both Master and Slave
modes of Operation
• I2C Slave mode Supports 7 and 10-Bit Addressing
• I2C Master mode Supports 7 and 10-Bit Addressing
• I2C Port allows Bidirectional Transfers between
Master and Slaves
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
• I2C Supports Multi-Master Operation, Detects Bus
Collision and Arbitrates accordingly
• System Management Bus (SMBus) Support
• Alternate I2C Pin Mapping (ASCLx/ASDAx)
17.1
I2C Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
17.1.1
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005127D-page 215
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FIGURE 17-1:
I2Cx BLOCK DIAGRAM (x = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
SCLx/ASCLx
Shift
Clock
I2CxRSR
LSb
SDAx/ASDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCONH
Acknowledge
Generation
Read
Write
Clock
Stretching
I2CxCONL
Read
Write
I2CxTRN
LSb
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
FP/2
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17.2
I2C Control Registers
REGISTER 17-1:
I2CxCONL: I2Cx CONTROL REGISTER LOW
R/W-0
U-0
R/W-0
R/W-1, HC
R/W-0
R/W-0
R/W-0
R/W-0
I2CEN
—
I2CSIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
R/W-0, HC
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C pins are controlled by port functions
bit 14
Unimplemented: Read as ‘0’
bit 13
I2CSIDL: I2Cx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave
address byte reception. Hardware is clear at the end of every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at the beginning of every
slave data byte transmission. Hardware is clear at the end of every slave address byte reception.
bit 11
STRICT: Strict I2Cx Reserved Address Enable bit
1 = Strict Reserved Addressing is Enabled:
In Slave mode, the device will NACK any reserved address. In Master mode, the device is allowed
to generate addresses within the reserved address space.
0 = Reserved Addressing is Acknowledged:
In Slave mode, the device will ACK any reserved address. In Master mode, the device should not
address a slave device with a reserved address.
bit 10
A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8
SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception)
0 = General call address is disabled
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REGISTER 17-1:
I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; hardware
is clear at the end of the master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C; hardware is clear at the end of the eighth bit of the master receive
data byte
0 = Receive sequence is not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins; hardware is clear at the end of the master Stop
sequence
0 = Stop condition is not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware is clear at the end of the
master Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins; hardware is clear at the end of the master Start
sequence
0 = Start condition is not in progress
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REGISTER 17-2:
I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6
PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5
SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4
BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of
the I2COV only if the RBF bit = 0
0 = I2CxRCV is only updated when I2COV is clear
bit 3
SDAHT: SDAx Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1 = Enables slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
If the rising edge of SCLx and SDAx is sampled low when the module is in a high state, the BCL bit is
set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
bit 1
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte, the SCLREL
(I2CxCONL) bit will be cleared and SCLx will be held low
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte, the slave hardware clears the
SCLREL (I2CxCONL) bit and SCLx is held low
0 = Data holding is disabled
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REGISTER 17-3:
I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC
R-0, HSC
R-0, HSC
U-0
U-0
R/C-0, HS
R-0, HSC
R-0, HSC
ACKSTAT
TRSTAT
ACKTIM
—
—
BCL
GCSTAT
ADD10
bit 15
bit 8
R/C-0, HS
R/C-0, HS
IWCOL
I2COV
R-0, HSC R/C-0, HSC R/C-0, HSC
D_A
P
S
R-0, HSC
R-0, HSC
R-0, HSC
R_W
RBF
TBF
bit 7
bit 0
Legend:
C = Clearable bit
HS = Hardware Settable bit
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
1 = NACK was received from slave
0 = ACK was received from slave
Hardware is set or clear at the end of a slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
bit 13
ACKTIM: Acknowledge Time Status bit (I2C Slave mode only)
1 = I2C bus is an Acknowledge sequence, set on the 8th falling edge of SCLx
0 = Not an Acknowledge sequence, cleared on the 9th rising edge of SCLx
bit 12-11
Unimplemented: Read as ‘0’
bit 10
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No bus collision detected
Hardware is set at detection of a bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches the general call address. Hardware is clear at Stop detection.
bit 8
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop
detection.
bit 7
IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A: Data/Address bit (I2C Slave mode only)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by reception of a slave byte.
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REGISTER 17-3:
I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 4
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
bit 3
S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
bit 2
R_W: Read/Write Information bit (I2C Slave mode only)
1 = Read – Indicates data transfer is output from the slave
0 = Write – Indicates data transfer is input to the slave
Hardware is set or clear after reception of an I 2C device address byte.
bit 1
RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads
I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.
2013-2017 Microchip Technology Inc.
DS70005127D-page 221
dsPIC33EPXXGS50X FAMILY
REGISTER 17-4:
I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
AMSK
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
AMSK: Address Mask Select bits
For 10-Bit Address:
1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK only):
1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax + 1; bit match is required in this position
DS70005127D-page 222
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
18.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Universal Asynchronous Receiver Transmitter (UART)”
(DS70000582) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXGS50X family of devices contains
two UART modules.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33EPXXGS50X device family.
The UART is a full-duplex, asynchronous system that
can communicate with peripheral devices, such as
personal computers, LIN/J2602, RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins, and
also includes an IrDA® encoder and decoder.
FIGURE 18-1:
The primary features of the UARTx module are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
• Baud Rates Ranging from 4.375 Mbps to 67 bps in
16x mode at 70 MIPS
• Baud Rates Ranging from 17.5 Mbps to 267 bps in
4x mode at 70 MIPS
• 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit Mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UARTx Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Support for Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UARTx module is
shown in Figure 18-1. The UARTx module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
UxRTS/BCLKx
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
2013-2017 Microchip Technology Inc.
DS70005127D-page 223
dsPIC33EPXXGS50X FAMILY
18.1
1.
2.
UART Helpful Tips
In multi-node, direct connect UART networks,
UART receive inputs react to the complementary logic level defined by the URXINV bit
(UxMODE), which defines the Idle state, the
default of which is logic high (i.e., URXINV = 0).
Because remote devices do not initialize at the
same time, it is likely that one of the devices,
because the RX line is floating, will trigger a Start
bit detection and will cause the first byte received,
after the device has been initialized, to be invalid.
To avoid this situation, the user should use a pullup or pull-down resistor on the RX pin depending
on the value of the URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the
UxRX pin.
b) If URXINV = 1, use a pull-down resistor on
the UxRX pin.
The first character received on a wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UARTx module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid; this is to be
expected.
DS70005127D-page 224
18.2
UART Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
18.2.1
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
18.3
UART Control Registers
REGISTER 18-1:
UxMODE: UARTx MODE REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
UARTEN(1)
—
USIDL
IREN(2)
RTSMD
—
UEN1
UEN0
bit 15
bit 8
R/W-0, HC
R/W-0
R/W-0, HC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
URXINV
BRGH
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
USIDL: UARTx Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin, interrupt is generated on the falling edge; bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
Note 1:
2:
Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the
“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
2013-2017 Microchip Technology Inc.
DS70005127D-page 225
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REGISTER 18-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4
URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the
“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
DS70005127D-page 226
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 18-2:
R/W-0
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
UTXINV
R/W-0
UTXISEL0
U-0
—
R/W-0, HC
UTXBRK
R/W-0
(1)
UTXEN
R-0
R-1
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL1
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
C = Clearable bit
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15,13
UTXISEL: UARTx Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14
UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA® encoded, UxTX Idle state is ‘1’
0 = IrDA encoded, UxTX Idle state is ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10
UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1:
Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.
2013-2017 Microchip Technology Inc.
DS70005127D-page 227
dsPIC33EPXXGS50X FAMILY
REGISTER 18-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1 0 transition) resets the
receiver buffer and the UxRSR to the empty state
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.
DS70005127D-page 228
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
19.0
HIGH-SPEED, 12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “12-Bit High-Speed,
Multiple SARs A/D Converter (ADC)”
(DS70005213) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33EPXXGS50X devices have a high-speed,
12-bit Analog-to-Digital Converter (ADC) that features
a low conversion latency, high resolution and oversampling capabilities to improve performance in
AC/DC, DC/DC power converters.
19.1
Features Overview
The High Speed, 12-Bit Multiple SARs Analog-to-Digital
Converter (ADC) includes the following features:
• Five ADC Cores: Four Dedicated Cores and
One Shared (Common) Core
• User-Configurable Resolution of up to 12 Bits for
each Core
• Up to 3.25 Msps Conversion Rate per Channel at
12-Bit Resolution
• Low-Latency Conversion
• Up to 22 Analog Input Channels, with a Separate
16-Bit Conversion Result Register for each Input
• Conversion Result can be Formatted as Unsigned
or Signed Data, on a per Channel Basis, for All
Channels
• Single-Ended and Pseudodifferential
Conversions are available on All ADC Cores
2013-2017 Microchip Technology Inc.
• Simultaneous Sampling of up to 5 Analog Inputs
• Channel Scan Capability
• Multiple Conversion Trigger Options for each
Core, including:
- PWM1 through PWM5 (primary and
secondary triggers, and current-limit event
trigger)
- PWM Special Event Trigger
- Timer1/Timer2 period match
- Output Compare 1 and event trigger
- External pin trigger event (ADTRG31)
- Software trigger
• Two Integrated Digital Comparators with
Dedicated Interrupts:
- Multiple comparison options
- Assignable to specific analog inputs
• Two Oversampling Filters with Dedicated
Interrupts:
- Provide increased resolution
- Assignable to a specific analog input
The module consists of five independent SAR ADC
cores. Simplified block diagrams of the Multiple SARs
12-Bit ADC are shown in Figure 19-1, Figure 19-2 and
Figure 19-3.
The analog inputs (channels) are connected through
multiplexers and switches to the Sample-and-Hold
(S&H) circuit of each ADC core. The core uses the
channel information (the output format, the measurement mode and the input number) to process the analog
sample. When conversion is complete, the result is
stored in the result buffer for the specific analog input,
and passed to the digital filter and digital comparator if
they were configured to use data from this particular
channel.
The ADC module can sample up to five inputs at a time
(four inputs from the dedicated SAR cores and one
from the shared SAR core). If multiple ADC inputs
request conversion on the shared core, the module will
convert them in a sequential manner, starting with the
lowest order input.
The ADC provides each analog input the ability to
specify its own trigger source. This capability allows the
ADC to sample and convert analog inputs that are
associated with PWM generators operating on
independent time bases.
DS70005127D-page 229
dsPIC33EPXXGS50X FAMILY
FIGURE 19-1:
ADC MODULE BLOCK DIAGRAM
AVDD AVSS
Voltage Reference
(REFSEL)
AN0
Reference
AN7
PGA1
AN0ALT
(1)
Dedicated
ADC Core 0(2)
Output Data
Digital Comparator 0
Clock
ADCMP0 Interrupt
(3)
Digital Comparator 1
AN1
AN18
PGA2(1)
ADCMP1 Interrupt
Reference
Dedicated
ADC Core 1(2)
Output Data
Clock
AN1ALT(3)
Reference
AN2
VBG Reference(1)
Dedicated
ADC Core 2(2)
AN11
Digital Filter 0
ADFL0DAT
Digital Filter 1
ADFL1DAT
Output Data
ADFLTR0 Interrupt
ADFLTR1 Interrupt
Clock
Reference
AN3
AN15
Dedicated
ADC Core 3(2)
ADCBUF0
ADCBUF1
Output Data
Clock
ADCBUF21
ADCAN21 Interrupt
Reference
AN4
Shared
ADC Core
AN21
ADCAN0 Interrupt
ADCAN1 Interrupt
Output Data
Clock
Divider
(CLKDIV)
Clock Selection
(CLKSEL)
Instruction FRC
Clock
Note 1:
2:
3:
AUX
Clock
PGA1, PGA2 and Band Gap Reference (VBG) are internal analog inputs and are not available on device pins.
If the dedicated core uses an alternate channel, then shared core function cannot be used.
AN0ALT and AN1ALT are not available on dsPIC33EPXXGS502 devices.
DS70005127D-page 230
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
FIGURE 19-2:
DEDICATED CORES 0 TO 3 BLOCK DIAGRAM
Positive Input
PGAx
Alternate
Positive Input
Positive Input
+
Selection
(CxCHS)
12-Bit SAR
ADC
Negative Input
–
Selection
(1)
(DIFFx)
Negative Input
Trigger Stops
Sampling
AVSS
Note 1:
Reference
Sampleand-Hold
ADC Core
Clock Divider
(ADCS bits)
Output Data
Clock
The DIFFx bit for the corresponding positive input channel must be set in order to use the negative
differential input.
FIGURE 19-3:
SHARED CORE BLOCK DIAGRAM
AN4
+
AN21
Analog Channel Number
from Current Trigger
AN9(1)
Negative Input
Selection
(DIFFx)(1)
Shared
Sampleand-Hold
12-Bit
SAR
ADC
ADC Core
Clock Divider
(SHRADC bits)
–
Sampling Time
Reference
Output Data
Clock
SHRSAMC
AVSS
Note 1:
Differential-mode conversion is not available for the shared ADC core in dsPIC33EPXXGS502 devices.
For all other devices, the DIFFx bit for the corresponding positive input channel must be set to use AN9
as the negative differential input.
2013-2017 Microchip Technology Inc.
DS70005127D-page 231
dsPIC33EPXXGS50X FAMILY
19.2
19.2.1
Analog-to-Digital Converter
Resources
Many useful resources are provided on the main
product page of the Microchip web site for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
REGISTER 19-1:
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
ADCON1L: ADC CONTROL REGISTER 1 LOW
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
ADON(1)
—
ADSIDL
—
—
—
—
—
bit 15
bit 8
U-0
r-0
r-0
r-0
r-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADON: ADC Enable bit(1)
1 = ADC module is enabled
0 = ADC module is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: ADC Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6-3
Reserved: Maintain as ‘0’
bit 2-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
Set the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when
ADON = 1 will result in unpredictable behavior.
DS70005127D-page 232
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 19-2:
ADCON1H: ADC CONTROL REGISTER 1 HIGH
r-0
r-0
r-0
r-0
r-0
r-0
r-0
r-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-1
R/W-1
r-0
r-0
r-0
r-0
r-0
FORM
SHRRES1
SHRRES0
—
—
—
—
—
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Reserved: Maintain as ‘0’
bit 7
FORM: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 6-5
SHRRES: Shared ADC Core Resolution Selection bits
11 = 12-bit resolution
10 = 10-bit resolution
01 = 8-bit resolution
00 = 6-bit resolution
bit 4-0
Reserved: Maintain as ‘0’
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 233
dsPIC33EPXXGS50X FAMILY
REGISTER 19-3:
ADCON2L: ADC CONTROL REGISTER 2 LOW
R/W-0
R/W-0
r-0
R/W-0
r-0
REFCIE
REFERCIE
—
EIEN
—
R/W-0
R/W-0
R/W-0
SHREISEL2(1) SHREISEL1(1) SHREISEL0(1)
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SHRADCS6 SHRADCS5 SHRADCS4 SHRADCS3
R/W-0
R/W-0
R/W-0
SHRADCS2
SHRADCS1
SHRADCS0
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
REFCIE: Band Gap and Reference Voltage Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when the band gap will become ready
0 = Common interrupt is disabled for the band gap ready event
bit 14
REFERCIE: Band Gap or Reference Voltage Error Common Interrupt Enable bit
1 = Common interrupt will be generated when a band gap or reference voltage error is detected
0 = Common interrupt is disabled for the band gap and reference voltage error event
bit 13
Reserved: Maintain as ‘0’
bit 12
EIEN: Early Interrupts Enable bit
1 = The early interrupt feature is enabled for the input channel interrupts (when the EISTATx flag is set)
0 = The individual interrupts are generated when conversion is done (when the ANxRDY flag is set)
bit 11
Reserved: Maintain as ‘0’
bit 10-8
SHREISEL: Shared Core Early Interrupt Time Selection bits(1)
111 = Early interrupt is set and interrupt is generated 8 TADCORE clocks prior to when the data is ready
110 = Early interrupt is set and interrupt is generated 7 TADCORE clocks prior to when the data is ready
101 = Early interrupt is set and interrupt is generated 6 TADCORE clocks prior to when the data is ready
100 = Early interrupt is set and interrupt is generated 5 TADCORE clocks prior to when the data is ready
011 = Early interrupt is set and interrupt is generated 4 TADCORE clocks prior to when the data is ready
010 = Early interrupt is set and interrupt is generated 3 TADCORE clocks prior to when the data is ready
001 = Early interrupt is set and interrupt is generated 2 TADCORE clocks prior to when the data is ready
000 = Early interrupt is set and interrupt is generated 1 TADCORE clock prior to when the data is ready
bit 7
Unimplemented: Read as ‘0’
bit 6-0
SHRADCS: Shared ADC Core Input Clock Divider bits
These bits determine the number of TCORESRC (Source Clock Periods) for one shared TADCORE (Core
Clock Period).
1111111 = 254 Source Clock Periods
•
•
•
0000011 = 6 Source Clock Periods
0000010 = 4 Source Clock Periods
0000001 = 2 Source Clock Periods
0000000 = 2 Source Clock Periods
Note 1:
For the 6-bit shared ADC core resolution (SHRRES = 00), the SHREISEL settings,
from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution
(SHRRES = 01), the SHREISEL settings, ‘110’ and ‘111’, are not valid and should not be used.
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REGISTER 19-4:
ADCON2H: ADC CONTROL REGISTER 2 HIGH
R-0, HSC
R-0, HSC
r-0
r-0
r-0
r-0
REFRDY
REFERR
—
—
—
—
R/W-0
bit 15
bit 8
R/W-0
SHRSAMC7
R/W-0
SHRSAMC9 SHRSAMC8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SHRSAMC6 SHRSAMC5 SHRSAMC4 SHRSAMC3 SHRSAMC2 SHRSAMC1 SHRSAMC0
bit 7
bit 0
Legend:
r = Reserved bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
REFRDY: Band Gap and Reference Voltage Ready Flag bit
1 = Band gap is ready
0 = Band gap is not ready
bit 14
REFERR: Band Gap or Reference Voltage Error Flag bit
1 = Band gap was removed after the ADC module was enabled (ADON = 1)
0 = No band gap error was detected
bit 13-10
Reserved: Maintain as ‘0’
bit 9-0
SHRSAMC: Shared ADC Core Sample Time Selection bits
These bits specify the number of shared ADC Core Clock Periods (TADCORE) for the shared ADC core
sample time.
1111111111 = 1025 TADCORE
•
•
•
0000000001 = 3 TADCORE
0000000000 = 2 TADCORE
2013-2017 Microchip Technology Inc.
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REGISTER 19-5:
ADCON3L: ADC CONTROL REGISTER 3 LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0, HSC
R/W-0
R-0, HSC
REFSEL2
REFSEL1
REFSEL0
SUSPEND
SUSPCIE
SUSPRDY
SHRSAMP
CNVRTCH
bit 15
bit 8
R/W-0
R/W-0, HSC
SWLCTRG
SWCTRG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
R/W-0
CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0
x = Bit is unknown
REFSEL: ADC Reference Voltage Selection bits
Value
VREFH
VREFL
000
AVDD
AVSS
001-111 = Unimplemented: Do not use
bit 12
SUSPEND: All ADC Cores Triggers Disable bit
1 = All new trigger events for all ADC cores are disabled
0 = All ADC cores can be triggered
bit 11
SUSPCIE: Suspend All ADC Cores Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC core triggers are suspended (SUSPEND bit = 1)
and all previous conversions are finished (SUSPRDY bit becomes set)
0 = Common interrupt is not generated for suspend ADC cores event
bit 10
SUSPRDY: All ADC Cores Suspended Flag bit
1 = All ADC cores are suspended (SUSPEND bit = 1) and have no conversions in progress
0 = ADC cores have previous conversions in progress
bit 9
SHRSAMP: Shared ADC Core Sampling Direct Control bit
This bit should be used with the individual channel conversion trigger controlled by the CNVRTCH bit.
It connects an analog input, specified by the CNVCHSEL bits, to the shared ADC core and allows
extending the sampling time. This bit is not controlled by hardware and must be cleared before the
conversion starts (setting CNVRTCH to ‘1’).
1 = Shared ADC core samples an analog input specified by the CNVCHSEL bits
0 = Sampling is controlled by the shared ADC core hardware
bit 8
CNVRTCH: Software Individual Channel Conversion Trigger bit
1 = Single trigger is generated for an analog input specified by the CNVCHSEL bits; when the bit
is set, it is automatically cleared by hardware on the next instruction cycle
0 = Next individual channel conversion trigger can be generated
bit 7
SWLCTRG: Software Level-Sensitive Common Trigger bit
1 = Triggers are continuously generated for all channels with the software, level-sensitive common
trigger selected as a source in the ADTRIGxL and ADTRIGxH registers
0 = No software, level-sensitive common triggers are generated
bit 6
SWCTRG: Software Common Trigger bit
1 = Single trigger is generated for all channels with the software, common trigger selected as a source
in the ADTRIGxL and ADTRIGxH registers; when the bit is set, it is automatically cleared by
hardware on the next instruction cycle
0 = Ready to generate the next software, common trigger
bit 5-0
CNVCHSEL : Channel Number Selection for Software Individual Channel Conversion Trigger bits
These bits define a channel to be converted when the CNVRTCH bit is set.
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REGISTER 19-6:
ADCON3H: ADC CONTROL REGISTER 3 HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLKSEL1
CLKSEL0
CLKDIV5
CLKDIV4
CLKDIV3
CLKDIV2
CLKDIV1
CLKDIV0
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SHREN
—
—
—
C3EN
C2EN
C1EN
C0EN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
CLKSEL: ADC Module Clock Source Selection bits
11 = APLL
10 = FRC
01 = FOSC (System Clock x 2)
00 = FSYS (System Clock)
bit 13-8
CLKDIV: ADC Module Clock Source Divider bits
The divider forms a TCORESRC clock used by all ADC cores (shared and dedicated) from the TSRC ADC
module clock source selected by the CLKSEL bits. Then, each ADC core individually divides the
TCORESRC clock to get a core-specific TADCORE clock using the ADCS bits in the ADCORExH
register or the SHRADCS bits in the ADCON2L register.
111111 = 64 Source Clock Periods
•
•
•
000011 = 4 Source Clock Periods
000010 = 3 Source Clock Periods
000001 = 2 Source Clock Periods
000000 = 1 Source Clock Period
bit 7
SHREN: Shared ADC Core Enable bit
1 = Shared ADC core is enabled
0 = Shared ADC core is disabled
bit 6-4
Unimplemented: Read as ‘0’
bit 3
C3EN: Dedicated ADC Core 3 Enable bits
1 = Dedicated ADC Core 3 is enabled
0 = Dedicated ADC Core 3 is disabled
bit 2
C2EN: Dedicated ADC Core 2 Enable bits
1 = Dedicated ADC Core 2 is enabled
0 = Dedicated ADC Core 2 is disabled
bit 1
C1EN: Dedicated ADC Core 1 Enable bits
1 = Dedicated ADC Core 1 is enabled
0 = Dedicated ADC Core 1 is disabled
bit 0
C0EN: Dedicated ADC Core 0 Enable bits
1 = Dedicated ADC Core 0 is enabled
0 = Dedicated ADC Core 0 is disabled
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REGISTER 19-7:
ADCON4L: ADC CONTROL REGISTER 4 LOW
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
SYNCTRG3
SYNCTRG2
SYNCTRG1
SYNCTRG0
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
SAMC3EN
SAMC2EN
SAMC1EN
SAMC0EN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11
SYNCTRG3: Dedicated ADC Core 3 Trigger Synchronization bit
1 = All triggers are synchronized with the core source clock (TCORESRC)
0 = The ADC core triggers are not synchronized
bit 10
SYNCTRG2: Dedicated ADC Core 2 Trigger Synchronization bit
1 = All triggers are synchronized with the core source clock (TCORESRC)
0 = The ADC core triggers are not synchronized
bit 9
SYNCTRG1: Dedicated ADC Core 1 Trigger Synchronization bit
1 = All triggers are synchronized with the core source clock (TCORESRC)
0 = The ADC core triggers are not synchronized
bit 8
SYNCTRG0: Dedicated ADC Core 0 Trigger Synchronization bit
1 = All triggers are synchronized with the core source clock (TCORESRC)
0 = The ADC core triggers are not synchronized
bit 7-4
Unimplemented: Read as ‘0’
bit 3
SAMC3EN: Dedicated ADC Core 3 Conversion Delay Enable bit
1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC bits in the ADCORE3L register
0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
bit 2
SAMC2EN: Dedicated ADC Core 2 Conversion Delay Enable bit
1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC bits in the ADCORE2L register
0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
bit 1
SAMC1EN: Dedicated ADC Core 1 Conversion Delay Enable bit
1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC bits in the ADCORE1L register
0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
bit 0
SAMC0EN: Dedicated ADC Core 0 Conversion Delay Enable bit
1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC bits in the ADCORE0L register
0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
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REGISTER 19-8:
ADCON4H: ADC CONTROL REGISTER 4 HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C3CHS1
C3CHS0
C2CHS1
C2CHS0
C1CHS1
C1CHS0
C0CHS1
C0CHS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-6
C3CHS: Dedicated ADC Core 3 Input Channel Selection bits
1x = Reserved
01 = AN15 (differential negative input when DIFF3 (ADMOD0L) = 1)
00 = AN3
bit 5-4
C2CHS: Dedicated ADC Core 2 Input Channel Selection bits
11 = Reserved
10 = VREF Band Gap
01 = AN11 (differential negative input when DIFF2 (ADMOD0L) = 1)
00 = AN2
bit 3-2
C1CHS: Dedicated ADC Core 1 Input Channel Selection bits
11 = AN1ALT
10 = PGA2
01 = AN18 (differential negative input when DIFF1 (ADMOD0L) = 1)
00 = AN1
bit 1-0
C0CHS: Dedicated ADC Core 0 Input Channel Selection bits
11 = AN0ALT
10 = PGA1
01 = AN7 (differential negative input when DIFF0 (ADMOD0L) = 1)
00 = AN0
2013-2017 Microchip Technology Inc.
x = Bit is unknown
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REGISTER 19-9:
ADCON5L: ADC CONTROL REGISTER 5 LOW
R-0, HSC
U-0
U-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
SHRRDY
—
—
—
C3RDY
C2RDY
C1RDY
C0RDY
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SHRPWR
—
—
—
C3PWR
C2PWR
C1PWR
C0PWR
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
SHRRDY: Shared ADC Core Ready Flag bit
1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 14-12
Unimplemented: Read as ‘0’
bit 11
C3RDY: Dedicated ADC Core 3 Ready Flag bit
1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 10
C2RDY: Dedicated ADC Core 2 Ready Flag bit
1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 9
C1RDY: Dedicated ADC Core 1 Ready Flag bit
1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 8
C0RDY: Dedicated ADC Core 0 Ready Flag bit
1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 7
SHRPWR: Shared ADC Core x Power Enable bit
1 = ADC Core x is powered
0 = ADC Core x is off
bit 6-4
Unimplemented: Read as ‘0’
bit 3
C3PWR: Dedicated ADC Core 3 Power Enable bit
1 = ADC core is powered
0 = ADC core is off
bit 2
C2PWR: Dedicated ADC Core 2 Power Enable bit
1 = ADC core is powered
0 = ADC core is off
bit 1
C1PWR: Dedicated ADC Core 1 Power Enable bit
1 = ADC core is powered
0 = ADC core is off
bit 0
C0PWR: Dedicated ADC Core 0 Power Enable bit
1 = ADC core is powered
0 = ADC core is off
DS70005127D-page 240
x = Bit is unknown
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REGISTER 19-10: ADCON5H: ADC CONTROL REGISTER 5 HIGH
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
WARMTIME3 WARMTIME2 WARMTIME1 WARMTIME0
bit 15
bit 8
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
SHRCIE
—
—
—
C3CIE
C2CIE
C1CIE
C0CIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
WARMTIME: ADC Dedicated Core x Power-up Delay bits
These bits determine the power-up delay in the number of the Core Source Clock Periods (TCORESRC)
for all ADC cores.
1111 = 32768 Source Clock Periods
1110 = 16384 Source Clock Periods
1101 = 8192 Source Clock Periods
1100 = 4096 Source Clock Periods
1011 = 2048 Source Clock Periods
1010 = 1024 Source Clock Periods
1001 = 512 Source Clock Periods
1000 = 256 Source Clock Periods
0111 = 128 Source Clock Periods
0110 = 64 Source Clock Periods
0101 = 32 Source Clock Periods
0100 = 16 Source Clock Periods
00xx = 16 Source Clock Periods
bit 7
SHRCIE: Shared ADC Core Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC core is powered and ready for operation
0 = Common interrupt is disabled for an ADC core ready event
bit 6-4
Unimplemented: Read as ‘0’
bit 3
C3CIE: Dedicated ADC Core 3 Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC Core 3 is powered and ready for operation
0 = Common interrupt is disabled for an ADC Core 3 ready event
bit 2
C2CIE: Dedicated ADC Core 2 Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC Core 2 is powered and ready for operation
0 = Common interrupt is disabled for an ADC Core 2 ready event
bit 1
C1CIE: Dedicated ADC Core 1 Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC Core 1 is powered and ready for operation
0 = Common interrupt is disabled for an ADC Core 1 ready event
bit 0
C0CIE: Dedicated ADC Core 0 Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC Core 0 is powered and ready for operation
0 = Common interrupt is disabled for an ADC Core 0 ready event
2013-2017 Microchip Technology Inc.
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REGISTER 19-11: ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW (x = 0 to 3)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
R/W-0
R/W-0
SAMC
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-10
Unimplemented: Read as ‘0’
bit 9-0
SAMC: Dedicated ADC Core x Conversion Delay Selection bits
These bits determine the time between the trigger event and the start of conversion in the number of
the Core Clock Periods (TADCORE). During this time, the ADC Core x still continues sampling. This
feature is enabled by the SAMCxEN bits in the ADCON4L register.
1111111111 = 1025 TADCORE
•
•
•
0000000001 = 3 TADCORE
0000000000 = 2 TADCORE
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REGISTER 19-12: ADCORExH: DEDICATED ADC CORE x CONTROL REGISTER HIGH (x = 0 to 3)(1)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
—
—
—
EISEL2
EISEL1
EISEL0
RES1
RES0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-10
EISEL: ADC Core x Early Interrupt Time Selection bits
111 = Early interrupt is set and an interrupt is generated 8 TADCORE clocks prior to when the data is ready
110 = Early interrupt is set and an interrupt is generated 7 TADCORE clocks prior to when the data is ready
101 = Early interrupt is set and an interrupt is generated 6 TADCORE clocks prior to when the data is ready
100 = Early interrupt is set and an interrupt is generated 5 TADCORE clocks prior to when the data is ready
011 = Early interrupt is set and an interrupt is generated 4 TADCORE clocks prior to when the data is ready
010 = Early interrupt is set and an interrupt is generated 3 TADCORE clocks prior to when the data is ready
001 = Early interrupt is set and an interrupt is generated 2 TADCORE clocks prior to when the data is ready
000 = Early interrupt is set and an interrupt is generated 1 TADCORE clock prior to when the data is ready
bit 9-8
RES: ADC Core x Resolution Selection bits
11 = 12-bit resolution
10 = 10-bit resolution
01 = 8-bit resolution
00 = 6-bit resolution
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ADCS: ADC Core x Input Clock Divider bits
These bits determine the number of Source Clock Periods (TCORESRC) for one Core Clock Period
(TADCORE).
1111111 = 254 Source Clock Periods
•
•
•
0000011 = 6 Source Clock Periods
0000010 = 4 Source Clock Periods
0000001 = 2 Source Clock Periods
0000000 = 2 Source Clock Periods
Note 1:
For the 6-bit ADC core resolution (RES = 00), the EISEL bits settings, from ‘100’ to ‘111’, are
not valid and should not be used. For the 8-bit ADC core resolution (RES = 01), the EISEL bits
settings, ‘110’ and ‘111’, are not valid and should not be used.
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REGISTER 19-13: ADLVLTRGL: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER LOW
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
LVLEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LVLEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
LVLEN: Level Trigger for Corresponding Analog Input Enable bits
1 = Input trigger is level-sensitive
0 = Input trigger is edge-sensitive
REGISTER 19-14: ADLVLTRGH: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LVLEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
LVLEN: Level Trigger for Corresponding Analog Input Enable bits
1 = Input trigger is level-sensitive
0 = Input trigger is edge-sensitive
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REGISTER 19-15: ADEIEL: ADC EARLY INTERRUPT ENABLE REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EIEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EIEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
EIEN: Early Interrupt Enable for Corresponding Analog Inputs bits
1 = Early interrupt is enabled for the channel
0 = Early interrupt is disabled for the channel
REGISTER 19-16: ADEIEH: ADC EARLY INTERRUPT ENABLE REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EIEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
EIEN: Early Interrupt Enable for Corresponding Analog Inputs bits
1 = Early interrupt is enabled for the channel
0 = Early interrupt is disabled for the channel
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REGISTER 19-17: ADEISTATL: ADC EARLY INTERRUPT STATUS REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EISTAT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EISTAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
EISTAT: Early Interrupt Status for Corresponding Analog Inputs bits
1 = Early interrupt was generated
0 = Early interrupt was not generated since the last ADCBUFx read
REGISTER 19-18: ADEISTATH: ADC EARLY INTERRUPT STATUS REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EISTAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
EISTAT: Early Interrupt Status for Corresponding Analog Inputs bits
1 = Early interrupt was generated
0 = Early interrupt was not generated since the last ADCBUFx read
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REGISTER 19-19: ADMOD0L: ADC INPUT MODE CONTROL REGISTER 0 LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF7
SIGN7
DIFF6
SIGN6
DIFF5
SIGN5
DIFF4
SIGN4
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF3
SIGN3
DIFF2
SIGN2
DIFF1
SIGN1
DIFF0
SIGN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1(odd)
x = Bit is unknown
DIFF: Differential-Mode for Corresponding Analog Inputs bits
1 = Channel is differential
0 = Channel is single-ended
bit 14-0 (even) SIGN: Output Data Sign for Corresponding Analog Inputs bits
1 = Channel output data is signed
0 = Channel output data is unsigned
REGISTER 19-20: ADMOD0H: ADC INPUT MODE CONTROL REGISTER 0 HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF15
SIGN15
DIFF14
SIGN14
DIFF13
SIGN13
DIFF12
SIGN12
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF11
SIGN11
DIFF10
SIGN10
DIFF9
SIGN9
DIFF8
SIGN8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-1(odd)
x = Bit is unknown
DIFF: Differential-Mode for Corresponding Analog Inputs bits
1 = Channel is differential
0 = Channel is single-ended
bit 14-0 (even) SIGN: Output Data Sign for Corresponding Analog Inputs bits
1 = Channel output data is signed
0 = Channel output data is unsigned
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REGISTER 19-21: ADMOD1L: ADC INPUT MODE CONTROL REGISTER 1 LOW
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
—
DIFF21
SIGN21
DIFF20
SIGN20
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF19
SIGN19
DIFF18
SIGN18
DIFF17
SIGN17
DIFF16
SIGN16
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-1(odd)
DIFF: Differential-Mode for Corresponding Analog Inputs bits
1 = Channel is differential
0 = Channel is single-ended
bit 10-0 (even) SIGN: Output Data Sign for Corresponding Analog Inputs bits
1 = Channel output data is signed
0 = Channel output data is unsigned
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REGISTER 19-22: ADIEL: ADC INTERRUPT ENABLE REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
IE: Common Interrupt Enable bits
1 = Common and individual interrupts are enabled for the corresponding channel
0 = Common and individual interrupts are disabled for the corresponding channel
REGISTER 19-23: ADIEH: ADC INTERRUPT ENABLE REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
IE: Common Interrupt Enable bits
1 = Common and individual interrupts are enabled for the corresponding channel
0 = Common and individual interrupts are disabled for the corresponding channel
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REGISTER 19-24: ADSTATL: ADC DATA READY STATUS REGISTER LOW
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
ANRDY
bit 15
R-0, HSC
bit 8
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
ANRDY
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
ANRDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1 = Channel conversion result is ready in the corresponding ADCBUFx register
0 = Channel conversion result is not ready
REGISTER 19-25: ADSTATH: ADC DATA READY STATUS REGISTER HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
ANRDY
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
ANRDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1 = Channel conversion result is ready in the corresponding ADCBUFx register
0 = Channel conversion result is not ready
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REGISTER 19-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
(x = 0 to 5)
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC(4x+1)
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC(4x)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
TRGSRC(4x+1): Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
11100 = PWM Generator 5 current-limit trigger
11011 = PWM Generator 4 current-limit trigger
11010 = PWM Generator 3 current-limit trigger
11001 = PWM Generator 2 current-limit trigger
11000 = PWM Generator 1 current-limit trigger
10111 = Output Compare 2 trigger
10110 = Output Compare 1 trigger
10101 = Reserved
10100 = Reserved
10011 = PWM Generator 5 secondary trigger
10010 = PWM Generator 4 secondary trigger
10001 = PWM Generator 3 secondary trigger
10000 = PWM Generator 2 secondary trigger
01111 = PWM Generator 1 secondary trigger
01110 = PWM secondary Special Event Trigger
01101 = Timer2 period match
01100 = Timer1 period match
01011 = Reserved
01010 = Reserved
01001 = PWM Generator 5 primary trigger
01000 = PWM Generator 4 primary trigger
00111 = PWM Generator 3 primary trigger
00110 = PWM Generator 2 primary trigger
00101 = PWM Generator 1 primary trigger
00100 = PWM Special Event Trigger
00011 = Reserved
00010 = Level software trigger
00001 = Common software trigger
00000 = No trigger is enabled
bit 7-5
Unimplemented: Read as ‘0’
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REGISTER 19-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
(x = 0 to 5) (CONTINUED)
bit 4-0
TRGSRC(4x): Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
11100 = PWM Generator 5 current-limit trigger
11011 = PWM Generator 4 current-limit trigger
11010 = PWM Generator 3 current-limit trigger
11001 = PWM Generator 2 current-limit trigger
11000 = PWM Generator 1 current-limit trigger
10111 = Output Compare 2 trigger
10110 = Output Compare 1 trigger
10101 = Reserved
10100 = Reserved
10011 = PWM Generator 5 secondary trigger
10010 = PWM Generator 4 secondary trigger
10001 = PWM Generator 3 secondary trigger
10000 = PWM Generator 2 secondary trigger
01111 = PWM Generator 1 secondary trigger
01110 = PWM secondary Special Event Trigger
01101 = Timer2 period match
01100 = Timer1 period match
01011 = Reserved
01010 = Reserved
01001 = PWM Generator 5 primary trigger
01000 = PWM Generator 4 primary trigger
00111 = PWM Generator 3 primary trigger
00110 = PWM Generator 2 primary trigger
00101 = PWM Generator 1 primary trigger
00100 = PWM Special Event Trigger
00011 = Reserved
00010 = Level software trigger
00001 = Common software trigger
00000 = No trigger is enabled
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REGISTER 19-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
(x = 0 to 5)
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC(4x+3)
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC(4x+2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
TRGSRC(4x+3): Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
11100 = PWM Generator 5 current-limit trigger
11011 = PWM Generator 4 current-limit trigger
11010 = PWM Generator 3 current-limit trigger
11001 = PWM Generator 2 current-limit trigger
11000 = PWM Generator 1 current-limit trigger
10111 = Output Compare 2 trigger
10110 = Output Compare 1 trigger
10101 = Reserved
10100 = Reserved
10011 = PWM Generator 5 secondary trigger
10010 = PWM Generator 4 secondary trigger
10001 = PWM Generator 3 secondary trigger
10000 = PWM Generator 2 secondary trigger
01111 = PWM Generator 1 secondary trigger
01110 = PWM secondary Special Event Trigger
01101 = Timer2 period match
01100 = Timer1 period match
01011 = Reserved
01010 = Reserved
01001 = PWM Generator 5 primary trigger
01000 = PWM Generator 4 primary trigger
00111 = PWM Generator 3 primary trigger
00110 = PWM Generator 2 primary trigger
00101 = PWM Generator 1 primary trigger
00100 = PWM Special Event Trigger
00011 = Reserved
00010 = Level software trigger
00001 = Common software trigger
00000 = No trigger is enabled
bit 7-5
Unimplemented: Read as ‘0’
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REGISTER 19-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
(x = 0 to 5) (CONTINUED)
bit 4-0
TRGSRC(4x+2): Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
11100 = PWM Generator 5 current-limit trigger
11011 = PWM Generator 4 current-limit trigger
11010 = PWM Generator 3 current-limit trigger
11001 = PWM Generator 2 current-limit trigger
11000 = PWM Generator 1 current-limit trigger
10111 = Output Compare 2 trigger
10110 = Output Compare 1 trigger
10101 = Reserved
10100 = Reserved
10011 = PWM Generator 5 secondary trigger
10010 = PWM Generator 4 secondary trigger
10001 = PWM Generator 3 secondary trigger
10000 = PWM Generator 2 secondary trigger
01111 = PWM Generator 1 secondary trigger
01110 = PWM secondary Special Event Trigger
01101 = Timer2 period match
01100 = Timer1 period match
01011 = Reserved
01010 = Reserved
01001 = PWM Generator 5 primary trigger
01000 = PWM Generator 4 primary trigger
00111 = PWM Generator 3 primary trigger
00110 = PWM Generator 2 primary trigger
00101 = PWM Generator 1 primary trigger
00100 = PWM Special Event Trigger
00011 = Reserved
00010 = Level software trigger
00001 = Common software trigger
00000 = No trigger is enabled
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REGISTER 19-28: ADCAL0L: ADC CALIBRATION REGISTER 0 LOW
R-0, HSC
U-0
U-0
U-0
r-0
R/W-0
R/W-0
R/W-0
CAL1RDY
—
—
—
—
CAL1DIFF
CAL1EN
CAL1RUN
bit 15
bit 8
R-0, HSC
U-0
U-0
U-0
r-0
R/W-0
R/W-0
R/W-0
CAL0RDY
—
—
—
—
CAL0DIFF
CAL0EN
CAL0RUN
bit 7
bit 0
Legend:
r = Reserved bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CAL1RDY: Dedicated ADC Core 1 Calibration Status Flag bit
1 = Dedicated ADC Core 1 calibration is finished
0 = Dedicated ADC Core 1 calibration is in progress
bit 14-12
Unimplemented: Read as ‘0’
bit 11
Reserved: Must be written as ‘0’
bit 10
CAL1DIFF: Dedicated ADC Core 1 Differential-Mode Calibration bit
1 = Dedicated ADC Core 1 will be calibrated in Differential Input mode
0 = Dedicated ADC Core 1 will be calibrated in Single-Ended Input mode
bit 9
CAL1EN: Dedicated ADC Core 1 Calibration Enable bit
1 = Dedicated ADC Core 1 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0 = Dedicated ADC Core 1 calibration bits are disabled
bit 8
CAL1RUN: Dedicated ADC Core 1 Calibration Start bit
1 = If this bit is set by software, the dedicated ADC Core 1 calibration cycle is started; this bit is
automatically cleared by hardware
0 = Software can start the next calibration cycle
bit 7
CAL0RDY: Dedicated ADC Core 0 Calibration Status Flag bit
1 = Dedicated ADC Core 0 calibration is finished
0 = Dedicated ADC Core 0 calibration is in progress
bit 6-4
Unimplemented: Read as ‘0’
bit 3
Reserved: Must be written as ‘0’
bit 2
CAL0DIFF: Dedicated ADC Core 0 Differential-Mode Calibration bit
1 = Dedicated ADC Core 0 will be calibrated in Differential Input mode
0 = Dedicated ADC Core 0 will be calibrated in Single-Ended Input mode
bit 1
CAL0EN: Dedicated ADC Core 0 Calibration Enable bit
1 = Dedicated ADC Core 0 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0 = Dedicated ADC Core 0 calibration bits are disabled
bit 0
CAL0RUN: Dedicated ADC Core 0 Calibration Start bit
1 = If this bit is set by software, the dedicated ADC Core 0 calibration cycle is started; this bit is
automatically cleared by hardware
0 = Software can start the next calibration cycle
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REGISTER 19-29: ADCAL0H: ADC CALIBRATION REGISTER 0 HIGH
R-0, HSC
U-0
U-0
U-0
r-0
R/W-0
R/W-0
R/W-0
CAL3RDY
—
—
—
—
CAL3DIFF
CAL3EN
CAL3RUN
bit 15
bit 8
R-0, HSC
U-0
U-0
U-0
r-0
R/W-0
R/W-0
R/W-0
CAL2RDY
—
—
—
—
CAL2DIFF
CAL2EN
CAL2RUN
bit 7
bit 0
Legend:
r = Reserved bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CAL3RDY: Dedicated ADC Core 3 Calibration Status Flag bit
1 = Dedicated ADC Core 3 calibration is finished
0 = Dedicated ADC Core 3 calibration is in progress
bit 14-12
Unimplemented: Read as ‘0’
x = Bit is unknown
bit 11
Reserved: Must be written as ‘0’
bit 10
CAL3DIFF: Dedicated ADC Core 3 Differential-Mode Calibration bit
1 = Dedicated ADC Core 3 will be calibrated in Differential Input mode
0 = Dedicated ADC Core 3 will be calibrated in Single-Ended Input mode
bit 9
CAL3EN: Dedicated ADC Core 3 Calibration Enable bit
1 = Dedicated ADC Core 3 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0 = Dedicated ADC Core 3 calibration bits are disabled
bit 8
CAL3RUN: Dedicated ADC Core 3 Calibration Start bit
1 = If this bit is set by software, the dedicated ADC Core 3 calibration cycle is started; this bit is
automatically cleared by hardware
0 = Software can start the next calibration cycle
bit 7
CAL2RDY: Dedicated ADC Core 2 Calibration Status Flag bit
1 = Dedicated ADC Core 2 calibration is finished
0 = Dedicated ADC Core 2 calibration is in progress
bit 6-4
Unimplemented: Read as ‘0’
bit 3
Reserved: Must be written as ‘0’
bit 2
CAL2DIFF: Dedicated ADC Core 2 Differential-Mode Calibration bit
1 = Dedicated ADC Core 2 will be calibrated in Differential Input mode
0 = Dedicated ADC Core 2 will be calibrated in Single-Ended Input mode
bit 1
CAL2EN: Dedicated ADC Core 2 Calibration Enable bit
1 = Dedicated ADC Core 2 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0 = Dedicated ADC Core 2 calibration bits are disabled
bit 0
CAL2RUN: Dedicated ADC Core 2 Calibration Start bit
1 = If this bit is set by software, the dedicated ADC Core 2 calibration cycle is started; this bit is
automatically cleared by hardware
0 = Software can start the next calibration cycle
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REGISTER 19-30: ADCAL1H: ADC CALIBRATION REGISTER 1 HIGH
R/W-0, HS
U-0
U-0
U-0
r-0
R/W-0
R/W-0
R/W-0
CSHRRDY
—
—
—
—
CSHRDIFF
CSHREN
CSHRRUN
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
r = Reserved bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HS = Hardware Settable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CSHRRDY: Shared ADC Core Calibration Status Flag bit
1 = Shared ADC core calibration is finished
0 = Shared ADC core calibration is in progress
bit 14-12
Unimplemented: Read as ‘0’
bit 11
Reserved: Must be written as ‘0’
bit 10
CSHRDIFF: Shared ADC Core Differential-Mode Calibration bit
1 = Shared ADC core will be calibrated in Differential Input mode
0 = Shared ADC core will be calibrated in Single-Ended Input mode
bit 9
CSHREN: Shared ADC Core Calibration Enable bit
1 = Shared ADC core calibration bits (CSHRRDY, CSHRDIFF and CSHRRUN) can be accessed by
software
0 = Shared ADC core calibration bits are disabled
bit 8
CSHRRUN: Shared ADC Core Calibration Start bit
1 = If this bit is set by software, the shared ADC core calibration cycle is started; this bit is cleared
automatically by hardware
0 = Software can start the next calibration cycle
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 19-31: ADCMPxCON: ADC DIGITAL COMPARATOR x CONTROL REGISTER (x = 0 or 1)
U-0
U-0
U-0
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
R-0, HSC
—
—
—
CHNL4
CHNL3
CHNL2
CHNL1
CHNL0
bit 15
bit 8
R/W-0
R/W-0
R-0, HC, HS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN
IE
STAT
BTWN
HIHI
HILO
LOHI
LOLO
bit 7
bit 0
Legend:
HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
CHNL: Input Channel Number bits
If the comparator has detected an event for a channel, this channel number is written to these bits.
11111 = Reserved
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
00001 = AN1
00000 = AN0
bit 7
CMPEN: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and the STAT status bit is cleared
bit 6
IE: Comparator Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated if the comparator detects a comparison event
0 = Common ADC interrupt will not be generated for the comparator
bit 5
STAT: Comparator Event Status bit
This bit is cleared by hardware when the channel number is read from the CHNL bits.
1 = A comparison event has been detected since the last read of the CHNL bits
0 = A comparison event has not been detected since the last read of the CHNL bits
bit 4
BTWN: Between Low/High Comparator Event bit
1 = Generates a comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
bit 3
HIHI: High/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxHI
bit 2
HILO: High/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxHI
bit 1
LOHI: Low/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxLO
bit 0
LOLO: Low/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxLO
DS70005127D-page 258
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 19-32: ADCMPxENL: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER
LOW (x = 0 or 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN
bit 15
bit 8
R/W/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-0
x = Bit is unknown
CMPEN: Comparator Enable for Corresponding Input Channels bits
1 = Conversion result for corresponding channel is used by the comparator
0 = Conversion result for corresponding channel is not used by the comparator
REGISTER 19-33: ADCMPxENH: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER
HIGH (x = 0 or 1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
CMPEN: Comparator Enable for Corresponding Input Channels bits
1 = Conversion result for corresponding channel is used by the comparator
0 = Conversion result for corresponding channel is not used by the comparator
2013-2017 Microchip Technology Inc.
DS70005127D-page 259
dsPIC33EPXXGS50X FAMILY
REGISTER 19-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0, HSC
FLEN
MODE1
MODE0
OVRSAM2
OVRSAM1
OVRSAM0
IE
RDY
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
FLCHSEL4
FLCHSEL3
FLCHSEL2
FLCHSEL1
FLCHSEL0
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FLEN: Filter Enable bit
1 = Filter is enabled
0 = Filter is disabled and the RDY bit is cleared
bit 14-13
MODE: Filter Mode bits
11 = Averaging mode
10 = Reserved
01 = Reserved
00 = Oversampling mode
bit 12-10
OVRSAM: Filter Averaging/Oversampling Ratio bits
If MODE = 00:
111 = 128x (16-bit result in the ADFLxDAT register is in 12.4 format)
110 = 32x (15-bit result in the ADFLxDAT register is in 12.3 format)
101 = 8x (14-bit result in the ADFLxDAT register is in 12.2 format)
100 = 2x (13-bit result in the ADFLxDAT register is in 12.1 format)
011 = 256x (16-bit result in the ADFLxDAT register is in 12.4 format)
010 = 64x (15-bit result in the ADFLxDAT register is in 12.3 format)
001 = 16x (14-bit result in the ADFLxDAT register is in 12.2 format)
000 = 4x (13-bit result in the ADFLxDAT register is in 12.1 format)
If MODE = 11 (12-bit result in the ADFLxDAT register in all instances):
111 = 256x
110 = 128x
101 = 64x
100 = 32x
011 = 16x
010 = 8x
001 = 4x
000 = 2x
bit 9
IE: Filter Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated when the filter result will be ready
0 = Common ADC interrupt will not be generated for the filter
bit 8
RDY: Oversampling Filter Data Ready Flag bit
This bit is cleared by hardware when the result is read from the ADFLxDAT register.
1 = Data in the ADFLxDAT register is ready
0 = The ADFLxDAT register has been read and new data in the ADFLxDAT register is not ready
bit 7-5
Unimplemented: Read as ‘0’
DS70005127D-page 260
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 19-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1) (CONTINUED)
bit 4-0
FLCHSEL: Oversampling Filter Input Channel Selection bits
11111 = Reserved
•
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
•
00001 = AN1
00000 = AN0
2013-2017 Microchip Technology Inc.
DS70005127D-page 261
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 262
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
20.0
HIGH-SPEED ANALOG
COMPARATOR
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “High-Speed Analog
Comparator Module” (DS70005128) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The high-speed analog comparator module monitors
current and/or voltage transients that may be too fast
for the CPU and ADC to capture.
2013-2017 Microchip Technology Inc.
20.1
Features Overview
The SMPS comparator module offers the following
major features:
• Four Rail-to-Rail Analog Comparators
• Dedicated 12-Bit DAC for each Analog
Comparator
• Up to Six Selectable Input Sources per
Comparator:
- Four external inputs
- Two internal inputs from the PGAx module
• Programmable Comparator Hysteresis
• Programmable Output Polarity
• Up to Two DAC Outputs to Device Pins
• Multiple Voltage References for the DAC:
- External References (EXTREF1 or
EXTREF2)
- AVDD
• Interrupt Generation Capability
• Functional Support for PWMx:
- PWMx duty cycle control
- PWMx period control
- PWMx Fault detected
DS70005127D-page 263
dsPIC33EPXXGS50X FAMILY
20.2
The analog comparator input pins are typically shared
with pins used by the Analog-to-Digital Converter (ADC)
module. Both the comparator and the ADC can use the
same pins at the same time. This capability enables a
user to measure an input voltage with the ADC and
detect voltage transients with the comparator.
Module Description
Figure 20-1 shows a functional block diagram of one
analog comparator from the high-speed analog
comparator module. The analog comparator provides
high-speed operation with a typical delay of 15 ns. The
negative input of the comparator is always connected
to the DACx circuit. The positive input of the comparator is connected to an analog multiplexer that selects
the desired source pin.
FIGURE 20-1:
HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM
INSELx
ALTINP
PGA1OUT
PGA2OUT
MUX
CMPxA(1)
CMPxB(1)
CMPxC(1)
CMPxD(1)
PWM Trigger
(remappable I/O)
CMPx(1)
0
1
EXTREF
RANGE
Pulse Stretcher
and
Digital Filter
Status
Interrupt
Request
CMPPOL
AVDD
MUX
EXTREF1(2)
DACx(1)
DACOE
EXTREF2(2,3)
12
DAC1/
DAC3
Output
Buffer
CMREFx
DACOUT1
PGA1OUT
DBCC Bit
FDEVOPT
PGAOEN
DACOE
DAC2/
DAC4
Output
Buffer
DACOUT2(3)
PGA2OUT
PGAOEN
Note 1:
2:
3:
x = 1-4
EXTREF1 is connected to DAC1/DAC3. EXTREF2 is connected to DAC2/DAC4.
Not available on all devices.
DS70005127D-page 264
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
20.3
Module Applications
This module provides a means for the SMPS dsPIC®
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
The comparator module has a high-speed comparator
and an associated 12-bit DAC that provides a
programmable reference voltage to the inverting input
of the comparator. The polarity of the comparator output is user-programmable. The output of the module
can be used in the following modes:
•
•
•
•
•
Generate an Interrupt
Trigger an ADC Sample and Convert Process
Truncate the PWMx Signal (current limit)
Truncate the PWMx Period (current minimum)
Disable the PWMx Outputs (Fault latch)
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and convert it, and 3) truncate the PWMx output in response to
a voltage being detected beyond its expected value.
The comparator module can also be used to wake-up the
system from Sleep or Idle mode when the analog input
voltage exceeds the programmed threshold voltage.
20.4
Each DACx has an output enable bit, DACOE, in the
CMPxCON register that enables the DACx reference
voltage to be routed to an external output pin
(DACOUTx). Refer to Figure 20-1 for connecting the
DACx output voltage to the DACOUTx pins.
Note 1: Ensure that multiple DACOE bits are not
set in software. The output on the
DACOUTx pin will be indeterminate if
multiple comparators enable the DACx
output.
2: DACOUT2 is not available on all devices.
20.5
Pulse Stretcher and Digital Logic
The analog comparator can respond to very fast transient signals. After the comparator output is given the
desired polarity, the signal is passed to a pulse
stretching circuit. The pulse stretching circuit has an
asynchronous set function and a delay circuit that
ensures the minimum pulse width is three system clock
cycles wide to allow the attached circuitry to properly
respond to a narrow pulse event.
The pulse stretcher circuit is followed by a digital filter.
The digital filter is enabled via the FLTREN bit in the
CMPxCON register. The digital filter operates with the
clock specified via the FCLKSEL bit in the CMPxCON
register. The comparator signal must be stable in a high
or low state, for at least three of the selected clock
cycles, for it to pass through the digital filter.
Digital-to-Analog Comparator (DAC)
Each analog comparator has a dedicated 12-bit DAC
that is used to program the comparator threshold voltage
via the CMPxDAC register. The DAC voltage reference
source is selected using the EXTREF and RANGE bits
in the CMPxCON register.
The EXTREF bit selects either the external voltage reference, EXTREFx, or an internal source as the voltage
reference source. The EXTREFx input enables users to
connect to a voltage reference that better suits their
application. The RANGE bit enables AVDD as the
voltage reference source for the DAC when an internal
voltage reference is selected.
Note:
EXTREF2 is not available on all devices.
2013-2017 Microchip Technology Inc.
DS70005127D-page 265
dsPIC33EPXXGS50X FAMILY
20.6
Hysteresis
20.7
An additional feature of the module is hysteresis control. Hysteresis can be enabled or disabled and its
amplitude can be controlled by the HYSSEL bits
in the CMPxCON register. Three different values are
available: 5 mV, 10 mV and 20 mV. It is also possible to
select the edge (rising or falling) to which hysteresis is
to be applied.
Hysteresis control prevents the comparator output from
continuously changing state because of small
perturbations (noise) at the input (see Figure 20-2).
FIGURE 20-2:
HYSTERESIS CONTROL
Output
Analog Comparator Resources
Many useful resources are provided on the main product page of the Microchip web site for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
20.7.1
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
Hysteresis Range
(5 mV/10 mV/20 mV)
Input
DS70005127D-page 266
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REGISTER 20-1:
CMPxCON: COMPARATOR x CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPON
—
CMPSIDL
HYSSEL1
HYSSEL0
FLTREN
FCLKSEL
DACOE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
HC-0, HS
R/W-0
R/W-0
R/W-0
INSEL1
INSEL0
EXTREF
HYSPOL
CMPSTAT
ALTINP
CMPPOL
RANGE
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CMPON: Comparator Operating Mode bit
1 = Comparator module is enabled
0 = Comparator module is disabled (reduces power consumption)
x = Bit is unknown
bit 14
Unimplemented: Read as ‘0’
bit 13
CMPSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode.
0 = Continues module operation in Idle mode
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables all comparators while in Idle mode.
bit 12-11
HYSSEL: Comparator Hysteresis Select bits
11 = 20 mV hysteresis
10 = 10 mV hysteresis
01 = 5 mV hysteresis
00 = No hysteresis is selected
bit 10
FLTREN: Digital Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 9
FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit
1 = Digital filter and pulse stretcher operate with the PWM clock
0 = Digital filter and pulse stretcher operate with the system clock
bit 8
DACOE: DACx Output Enable bit
1 = DACx analog voltage is connected to the DACOUTx pin(1)
0 = DACx analog voltage is not connected to the DACOUTx pin
bit 7-6
INSEL: Input Source Select for Comparator bits
If ALTINP = 0, Select from Comparator Inputs:
11 = Selects CMPxD input pin
10 = Selects CMPxC input pin
01 = Selects CMPxB input pin
00 = Selects CMPxA input pin
If ALTINP = 1, Select from Alternate Inputs:
11 = Reserved
10 = Reserved
01 = Selects PGA2 output
00 = Selects PGA1 output
Note 1:
DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.
2013-2017 Microchip Technology Inc.
DS70005127D-page 267
dsPIC33EPXXGS50X FAMILY
REGISTER 20-1:
CMPxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
bit 5
EXTREF: Enable External Reference bit
1 = External source provides reference to DACx (maximum DAC voltage is determined by the external
voltage source)
0 = AVDD provides reference to DACx (maximum DAC voltage is AVDD)
bit 4
HYSPOL: Comparator Hysteresis Polarity Select bit
1 = Hysteresis is applied to the falling edge of the comparator output
0 = Hysteresis is applied to the rising edge of the comparator output
bit 3
CMPSTAT: Comparator Current State bit
Reflects the current output state of Comparator x, including the setting of the CMPPOL bit.
bit 2
ALTINP: Alternate Input Select bit
1 = INSEL bits select alternate inputs
0 = INSEL bits select comparator inputs
bit 1
CMPPOL: Comparator Output Polarity Control bit
1 = Output is inverted
0 = Output is non-inverted
bit 0
RANGE: DACx Output Voltage Range Select bit
1 = AVDD is the maximum DACx output voltage
0 = Unimplemented, do not use
Note 1:
DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.
DS70005127D-page 268
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dsPIC33EPXXGS50X FAMILY
REGISTER 20-2:
CMPxDAC: COMPARATOR x DAC CONTROL REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
CMREF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMREF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-0
CMREF: Comparator Reference Voltage Select bits
111111111111
•
•
•
= ([CMREF] * (AVDD)/4096) volts (EXTREF = 0)
•
or ([CMREF] * (EXTREF)/4096) volts (EXTREF = 1)
•
•
000000000000
2013-2017 Microchip Technology Inc.
DS70005127D-page 269
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NOTES:
DS70005127D-page 270
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
21.0
PROGRAMMABLE GAIN
AMPLIFIER (PGA)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Programmable Gain
Amplifier (PGA)” (DS70005146) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 21-1:
The dsPIC33EPXXGS50X family devices have two
Programmable Gain Amplifiers (PGA1, PGA2). The
PGA is an op amp-based, non-inverting amplifier with
user-programmable gains. The output of the PGA can
be connected to a number of dedicated Sample-andHold inputs of the Analog-to-Digital Converter and/or to
the high-speed analog comparator module. The PGA
has five selectable gains and may be used as a ground
referenced amplifier (single-ended) or used with an
independent ground reference point.
Key features of the PGA module include:
•
•
•
•
•
Single-Ended or Independent Ground Reference
Selectable Gains: 4x, 8x, 16x, 32x and 64x
High Gain Bandwidth
Rail-to-Rail Output Voltage
Wide Input Voltage Range
PGAx MODULE BLOCK DIAGRAM
GAIN = 6
GAIN = 5
GAIN = 4
GAIN = 3
GAIN = 2
Gain of 64x
Gain of 32x
Gain of 16x
Gain of 8x
Gain of 4x
–
PGAx Negative Input
PGAxOUT
AMPx
+
PGAx Positive Input
PGAx Calibrations
Note 1:
x = 1 and 2.
2013-2017 Microchip Technology Inc.
DS70005127D-page 271
dsPIC33EPXXGS50X FAMILY
21.1
input source. To provide an independent ground
reference, PGAxN2 and PGAxN3 pins are available as
the negative input source to the PGAx module.
Module Description
The Programmable Gain Amplifiers are used to amplify
small voltages (i.e., voltages across burden/shunt
resistors) to improve the signal-to-noise ratio of the
measured signal. The PGAx output voltage can be
read by any of the four dedicated Sample-and-Hold
circuits on the ADC module. The output voltage can
also be fed to the comparator module for overcurrent/
voltage protection. Figure 21-2 shows a functional
block diagram of the PGAx module. Refer to
Section 19.0 “High-Speed, 12-Bit Analog-to-Digital
Converter (ADC)” and Section 20.0 “High-Speed
Analog Comparator” for more interconnection details.
Note 1: Not all PGA positive/negative inputs are
available on all devices. Refer to the
specific device pinout for available input
source pins.
The output voltage of the PGAx module can be
connected to the DACOUTx pin by setting the
PGAOEN bit in the PGAxCON register. When the
PGAOEN bit is enabled, the output voltage of PGA1 is
connected to DACOUT1 and PGA2 is connected to
DACOUT2. For devices with a single DACOUTx pin,
the output voltage of PGA2 can be connected to
DACOUT1 by configuring the DBCC Configuration bit
in the FDEVOPT register (FDEVOPT).
The gain of the PGAx module is selectable via the
GAIN bits in the PGAxCON register. There are
five selectable gains, ranging from 4x to 64x. The
SELPI and SELNI bits in the PGAxCON
register select one of four positive/negative inputs to
the PGAx module. For single-ended applications, the
SELNI bits will select the ground as the negative
FIGURE 21-2:
If both the DACx output voltage and PGAx output voltage are connected to the DACOUTx pin, the resulting
output voltage would be a combination of signals.
There is no assigned priority between the PGAx
module and the DACx module.
PGAx FUNCTIONAL BLOCK DIAGRAM
INSEL
(CMPxCON)
SELPI
PGAxCAL(1)
PGAxCON(1)
+
–
PGAEN GAIN
PGAxP1(1)
DACx
PGAxP2(1)
PGACAL
PGAxP3(1)
CxCHS
(ADCON4H)
PGAxP4(1)
ADC
+
S&H
PGAx(1)
GND
–
PGAxN2(1)
PGAxN3(1,3)
GND
PGAOEN
SELNI
Note 1:
2:
3:
To DACOUTx Pin(2)
x = 1 and 2.
The DACOUT2 device pin is only available on 64-pin devices.
The PGAxN3 input is not available on 28-pin devices.
DS70005127D-page 272
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
21.2
21.2.1
PGA Resources
Many useful resources are provided on the main product page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
REGISTER 21-1:
KEY RESOURCES
•
•
•
•
•
Code Samples
Application Notes
Software Libraries
Webinars
All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
PGAxCON: PGAx CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PGAEN
PGAOEN
SELPI2
SELPI1
SELPI0
SELNI2
SELNI1
SELNI0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
GAIN2
GAIN1
GAIN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
PGAEN: PGAx Enable bit
1 = PGAx module is enabled
0 = PGAx module is disabled (reduces power consumption)
bit 14
PGAOEN: PGAx Output Enable bit
1 = PGAx output is connected to the DACOUTx pin
0 = PGAx output is not connected to the DACOUTx pin
bit 13-11
SELPI: PGAx Positive Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = PGAxP4
010 = PGAxP3
001 = PGAxP2
000 = PGAxP1
bit 10-8
SELNI: PGAx Negative Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Ground (Single-Ended mode)
010 = PGAxN3
001 = PGAxN2
000 = Ground (Single-Ended mode)
bit 7-3
Unimplemented: Read as ‘0’
2013-2017 Microchip Technology Inc.
x = Bit is unknown
DS70005127D-page 273
dsPIC33EPXXGS50X FAMILY
REGISTER 21-1:
bit 2-0
PGAxCON: PGAx CONTROL REGISTER (CONTINUED)
GAIN: PGAx Gain Selection bits
111 = Reserved
110 = Gain of 64x
101 = Gain of 32x
100 = Gain of 16x
011 = Gain of 8x
010 = Gain of 4x
001 = Reserved
000 = Reserved
REGISTER 21-2:
PGAxCAL: PGAx CALIBRATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PGACAL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
PGACAL: PGAx Offset Calibration bits
The calibration values for PGA1 and PGA2 must be copied from Flash addresses, 0x800E48 and
0x800E4C, respectively, into these bits before the module is enabled. Refer to the calibration data
address table (Table 23-3) in Section 23.0 “Special Features” for more information.
DS70005127D-page 274
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dsPIC33EPXXGS50X FAMILY
22.0
CONSTANT-CURRENT
SOURCE
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The constant-current source module is a precision
current generator and is used in conjunction with the
ADC module to measure the resistance of external
resistors connected to device pins.
FIGURE 22-1:
22.1
Features Overview
The constant-current source module offers the following
major features:
• Constant-Current Generator (10 µA nominal)
• Internal Selectable Connection to One of Four Pins
• Enable/Disable Bit
22.2
Module Description
Figure 22-1 shows a functional block diagram of the
constant-current source module. It consists of a precision current generator with a nominal value of 10 µA.
The module can be enabled and disabled using the
ISRCEN bit in the ISRCCON register. The output of
the current generator is internally connected to a
device pin. The dsPIC33EPXXGS50X family can have
up to 4 selectable current source pins. The
OUTSEL bits in the ISRCCON register allow
selection of the target pin.
The current source is calibrated during testing.
CONSTANT-CURRENT SOURCE MODULE BLOCK DIAGRAM
Constant-Current Source
ISRC1
ISRC2
M
U
X
ISRC3
ISRC4
ISRCEN
OUTSEL
2013-2017 Microchip Technology Inc.
DS70005127D-page 275
dsPIC33EPXXGS50X FAMILY
22.3
Current Source Control Register
REGISTER 22-1:
ISRCCON: CONSTANT-CURRENT SOURCE CONTROL REGISTER
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
ISRCEN
—
—
—
—
OUTSEL2
OUTSEL1
OUTSEL0
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
ISRCCAL5
ISRCCAL4
ISRCCAL3
ISRCCAL2
ISRCCAL1
ISRCCAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ISRCEN: Constant-Current Source Enable bit
1 = Current source is enabled
0 = Current source is disabled
bit 14-11
Unimplemented: Read as ‘0’
bit 10-8
OUTSEL: Output Constant-Current Select bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Input pin, ISRC4 (AN4)
011 = Input pin, ISRC3 (AN5)
010 = Input pin, ISRC2 (AN6)
001 = Input pin, ISRC1 (AN12)
000 = No output is selected
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
ISRCCAL: Constant-Current Source Calibration bits
The calibration value must be copied from Flash address, 0x800E78, into these bits before the
module is enabled. Refer to the calibration data address table (Table 23-3) in Section 23.0 “Special
Features” for more information.
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dsPIC33EPXXGS50X FAMILY
23.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the dsPIC33EPXXGS50X family of
devices. It is not intended to be a comprehensive reference source. To complement
the information in this data sheet, refer to
the related section of the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
The dsPIC33EPXXGS50X family devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
•
•
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection and CodeGuard™ Security
JTAG Boundary Scan Interface
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
Brown-out Reset (BOR)
23.1
In dsPIC33EPXXGS50X family devices, the Configuration Words are implemented as volatile memory. This
means that configuration data must be programmed
each time the device is powered up. Configuration data
is stored at the end of the on-chip program memory
space, known as the Flash Configuration Words. Their
specific locations are shown in Table 23-1 with detailed
descriptions in Table 23-2. The configuration data is
automatically loaded from the Flash Configuration
Words to the proper Configuration Shadow registers
during device Resets.
For devices operating in Dual Partition modes, the
BSEQx bits (FBTSEQ) determine which panel is
the Active Partition at start-up and the Configuration
Words from that panel are loaded into the Configuration
Shadow registers.
Note:
Configuration data is reloaded on all types
of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Words for configuration data in
their code for the compiler. This is to make certain that
program code is not stored in this address when the
code is compiled. Program code executing out of
configuration space will cause a device Reset.
Note:
2013-2017 Microchip Technology Inc.
Configuration Bits
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words.
DS70005127D-page 277
Name
FSEC
CONFIGURATION REGISTER MAP(3)
Address
Device
Memory
Size
(Kbytes)
002B80
16
005780
32
00AF80
64
002B90
16
005790
32
00AF90
64
002B94
16
005794
32
00AF94
64
002B98
16
FOSCSEL 005798
32
FBSLIM
FSIGN
FOSC
FWDT
2013-2017 Microchip Technology Inc.
FPOR
FICD
Note 1:
2:
3:
4:
00AF98
64
002B9C
16
00579C
32
00AF9C
64
002BA0
16
0057A0
32
00AFA0
64
002BA4
16
0057A4
32
00AFA4
64
002BA8
16
0057A8
32
00AFA8
64
Bits 23-16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
AIVTDIS
—
—
—
—
—
—
—
—
Reserved(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IESO
—
—
—
—
—
—
—
—
—
PLLKEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BTSWP
—
—
—
—
—
—
—
Reserved(1)
—
JTAGEN
—
—
—
CSS
Bit 8
CWRP
Bit 7
Bit 6
GSS
Bit 5
Bit 4
Bit 3
GWRP
—
BSEN
—
—
—
—
—
—
IOL1WAY
—
—
Bit 2
Bit 1
Bit 0
BSS
BWRP
BSLIM
WDTWIN
FCKSM
WINDIS
WDTEN
WDTPRE
—
—
—
FNOSC
OSCIOFNC
POSCMD
WDTPOST
—
Reserved(1)
ICS
These bits are reserved and must be programmed as ‘1’.
This bit is reserved and must be programmed as ‘0’.
When operating in Dual Partition mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft
swap condition, the configuration settings of the newly Active Partition are ignored.
FBOOT resides in configuration memory space.
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 278
TABLE 23-1:
2013-2017 Microchip Technology Inc.
TABLE 23-1:
Name
Address
CONFIGURATION REGISTER MAP(3) (CONTINUED)
Device
Memory
Size
(Kbytes)
FDEVOPT 002BAC
16
0057AC
32
00AFAC
64
FALTREG 002BB0
16
0057B0
32
00AFB0
64
002BFC
16
FBTSEQ
Note 1:
2:
3:
4:
32
64
801000
—
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
—
—
—
—
—
—
—
—
—
—
DBCC
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 3
Bit 2
ALTI2C2 ALTI2C1 Reserved(1)
CTXT2
IBSEQ
—
Bit 4
—
Bit 1
Bit 0
—
PWMLOCK
CTXT1
BSEQ
—
—
—
—
—
—
—
—
—
—
—
—
BTMODE
These bits are reserved and must be programmed as ‘1’.
This bit is reserved and must be programmed as ‘0’.
When operating in Dual Partition mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft
swap condition, the configuration settings of the newly Active Partition are ignored.
FBOOT resides in configuration memory space.
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dsPIC33EPXXGS50X FAMILY
FBOOT(4)
0057FC
00AFFC
Bits 23-16
dsPIC33EPXXGS50X FAMILY
TABLE 23-2:
CONFIGURATION BITS DESCRIPTION
Bit Field
Description
BSS
Boot Segment Code-Protect Level bits
11 = Boot Segment is not code-protected other than BWRP
10 = Standard security
0x = High security
BSEN
Boot Segment Control bit
1 = No Boot Segment is enabled
0 = Boot Segment size is determined by the BSLIM bits
BWRP
Boot Segment Write-Protect bit
1 = Boot Segment can be written
0 = Boot Segment is write-protected
BSLIM
Boot Segment Flash Page Address Limit bits
Contains the last active Boot Segment page. The value to be programmed is the inverted
page address, such that programming additional ‘0’s can only increase the Boot Segment
size (i.e., 0x1FFD = 2 Pages or 1024 IW).
GSS
General Segment Code-Protect Level bits
11 = User program memory is not code-protected
10 = Standard security
0x = High security
GWRP
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
CWRP
Configuration Segment Write-Protect bit
1 = Configuration data is not write-protected
0 = Configuration data is write-protected
CSS
Configuration Segment Code-Protect Level bits
111 = Configuration data is not code-protected
110 = Standard security
10x = Enhanced security
0xx = High security
BTSWP
BOOTSWP Instruction Enable/Disable bit
1 = BOOTSWP instruction is disabled
0 = BOOTSWP instruction is enabled
BSEQ
Boot Sequence Number bits (Dual Partition modes only)
Relative value defining which partition will be active after device Reset; the partition
containing a lower boot number will be active.
IBSEQ
Inverse Boot Sequence Number bits (Dual Partition modes only)
The one’s complement of BSEQ; must be calculated by the user and written for
device programming. If BSEQx and IBSEQx are not complements of each other, the Boot
Sequence Number is considered to be invalid.
AIVTDIS(1)
Alternate Interrupt Vector Table bit
1 = Alternate Interrupt Vector Table is disabled
0 = Alternate Interrupt Vector Table is enabled if INTCON2 = 1
IESO
Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the user-selected oscillator
source when ready
0 = Starts up device with the user-selected oscillator source
PWMLOCK
PWMx Lock Enable bit
1 = Certain PWMx registers may only be written after a key sequence
0 = PWMx registers may be written without a key sequence
Note 1:
The Boot Segment must be present to use the Alternate Interrupt Vector Table.
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dsPIC33EPXXGS50X FAMILY
TABLE 23-2:
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
FNOSC
Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved; do not use
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
000 = Fast RC Oscillator (FRC)
FCKSM
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is a general purpose digital I/O pin
POSCMD
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
WDTEN
Watchdog Timer Enable bits
11 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the
SWDTEN bit in the RCON register will have no effect)
10 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by
clearing the SWDTEN bit in the RCON register)
01 = Watchdog Timer is enabled only while device is active and is disabled while in Sleep
mode; software control is disabled in this mode
00 = Watchdog Timer and SWDTEN bit are disabled
WINDIS
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
PLLKEN
PLL Lock Enable bit
1 = PLL lock is enabled
0 = PLL lock is disabled
WDTPRE
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
Note 1:
The Boot Segment must be present to use the Alternate Interrupt Vector Table.
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TABLE 23-2:
CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
WDTWIN
Watchdog Timer Window Select bits
11 = WDT window is 25% of the WDT period
10 = WDT window is 37.5% of the WDT period
01 = WDT window is 50% of the WDT period
00 = WDT window is 75% of the WDT period
ALTI2C1
Alternate I2C1 Pin bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2
Alternate I2C2 Pin bit
1 = I2C2 is mapped to the SDA2/SCL2 pins
0 = I2C2 is mapped to the ASDA2/ASCL2 pins
JTAGEN
JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS
ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1
10 = Communicates on PGEC2 and PGED2
01 = Communicates on PGEC3 and PGED3
00 = Reserved, do not use
DBCC
DACx Output Cross Connection Select bit
1 = No cross connection between DAC outputs
0 = Interconnects DACOUT1 and DACOUT2
CTXT1
Alternate Working Register Set 1 Interrupt Priority Level (IPL) Select bits
111 = Reserved
110 = Assigned to IPL of 7
101 = Assigned to IPL of 6
100 = Assigned to IPL of 5
011 = Assigned to IPL of 4
010 = Assigned to IPL of 3
001 = Assigned to IPL of 2
000 = Assigned to IPL of 1
CTXT2
Alternate Working Register Set 2 Interrupt Priority Level (IPL) Select bits
111 = Reserved
110 = Assigned to IPL of 7
101 = Assigned to IPL of 6
100 = Assigned to IPL of 5
011 = Assigned to IPL of 4
010 = Assigned to IPL of 3
001 = Assigned to IPL of 2
000 = Assigned to IPL of 1
BTMODE
Boot Mode Configuration bits
11 = Single Partition mode
10 = Dual Partition mode
01 = Protected Dual Partition mode
00 = Privileged Dual Partition mode
Note 1:
The Boot Segment must be present to use the Alternate Interrupt Vector Table.
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dsPIC33EPXXGS50X FAMILY
23.2
The dsPIC33EPXXGS50X devices have two identification registers near the end of configuration memory
space that store the Device ID (DEVID) and Device
Revision (DEVREV). These registers are used to determine the mask, variant and manufacturing information
about the device. These registers are read-only and
are shown in Register 23-1 and Register 23-2.
Device Calibration and
Identification
The PGAx and current source modules on the
dsPIC33EPXXGS50X family devices require Calibration Data registers to improve performance of the
module over a wide operating range. These Calibration
registers are read-only and are stored in configuration
memory space. Prior to enabling the module, the
calibration data must be read (TBLPAG and Table
Read instruction) and loaded into its respective SFR
registers. The device calibration addresses are shown
in Table 23-3.
TABLE 23-3:
DEVICE CALIBRATION ADDRESSES(1)
Calibration
Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Name
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PGA1CAL
800E48
—
—
—
—
—
—
—
—
—
—
—
PGA1 Calibration Data
PGA2CAL
800E4C
—
—
—
—
—
—
—
—
—
—
—
PGA2 Calibration Data
800E78
—
—
—
—
—
—
—
—
—
—
—
Current Source Calibration Data
ISRCCAL
Note 1:
The calibration data must be copied into its respective registers prior to enabling the module.
2013-2017 Microchip Technology Inc.
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dsPIC33EPXXGS50X FAMILY
REGISTER 23-1:
R
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
DEVID
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVID
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID
bit 7
bit 0
Legend: R = Read-Only bit
bit 23-0
DEVID: Device Identifier bits
REGISTER 23-2:
R
U = Unimplemented bit
DEVREV: DEVICE REVISION REGISTER
R
R
R
R
R
R
R
DEVREV
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVREV
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVREV
bit 7
bit 0
Legend: R = Read-only bit
bit 23-0
U = Unimplemented bit
DEVREV: Device Revision bits
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dsPIC33EPXXGS50X FAMILY
23.3
User OTP Memory
23.5
Brown-out Reset (BOR)
dsPIC33EPXXGS50X family devices contain 64 words
of User One-Time-Programmable (OTP) memory,
located at addresses, 0x800F80 through 0x800FFE.
The User OTP Words can be used for storing checksum,
code revisions, product information, such as serial numbers, system manufacturing dates, manufacturing lot
numbers and other application-specific information.
These words can only be written once at program time
and not at run time; they can be read at run time.
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the regulated supply voltage, VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
23.4
A BOR generates a Reset pulse which resets the
device. The BOR selects the clock source based on the
device Configuration bit values (FNOSC and
POSCMD).
On-Chip Voltage Regulator
All the dsPIC33EPXXGS50X family devices power their
core digital logic at a nominal 1.8V. This can create a
conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33EPXXGS50X family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the VCAP
pin (Figure 23-1). This helps to maintain the stability of
the regulator. The recommended value for the filter
capacitor is provided in Table 26-5, located in
Section 26.0 “Electrical Characteristics”.
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
Note:
FIGURE 23-1:
If an Oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON) is ‘1’.
Concurrently, the PWRT Time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and a
crystal oscillator is being used, then a nominal delay of
TFSCM is applied. The total delay in this case is TFSCM.
Refer to Parameter SY35 in Table 26-23 of Section 26.0
“Electrical Characteristics” for specific TFSCM values.
The BOR status bit (RCON) is set to indicate that a
BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
3.3V
dsPIC33EP
VDD
VCAP
CEFC
Note 1:
2:
3:
VSS
These are typical operating voltages.
Refer to Table 26-5 located in
Section 26.0 “Electrical Characteristics” for the full operating ranges of VDD
and VCAP.
It is important for the low-ESR capacitor
to be placed as close as possible to the
VCAP pin.
Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.
2013-2017 Microchip Technology Inc.
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dsPIC33EPXXGS50X FAMILY
23.6
23.6.2
Watchdog Timer (WDT)
For dsPIC33EPXXGS50X family devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
23.6.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration
bit. With a 32 kHz input, the prescaler yields a WDT
Time-out Period (TWDT), as shown in Parameter SY12
in Table 26-23.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST
Configuration bits (FWDT), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods, ranges from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 23-2:
SLEEP AND IDLE MODES
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes and code execution continues from where the
PWRSAV instruction was executed. The corresponding
SLEEP or IDLE bit (RCON) needs to be cleared in
software after the device wakes up.
23.6.3
ENABLING WDT
The WDT is enabled or disabled by the WDTEN
Configuration bits in the FWDT Configuration register.
When the WDTEN Configuration bits have been
programmed to ‘0b11’, the WDT is always enabled.
The WDT can be optionally controlled in software
when the WDTEN Configuration bits have been
programmed to ‘0b10’. The WDT is enabled in software by setting the SWDTEN control bit (RCON).
The SWDTEN control bit is cleared on any device
Reset. The software WDT option allows the user application to enable the WDT for critical code segments
and disables the WDT during non-critical segments for
maximum power savings.
The WDT Time-out flag bit, WDTO (RCON), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
23.6.4
WDT WINDOW
The Watchdog Timer has an optional Windowed mode,
enabled by programming the WINDIS bit in the WDT
Configuration register (FWDT). In the Windowed
mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Window select bits (WDTWIN).
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
SWDTEN
WDTEN
WDT
Wake-up
RS
Prescaler
(Divide-by-N1)
LPRC Clock
Sleep/Idle
WDTPOST
WDTPRE
1
RS
Postscaler
(Divide-by-N2)
0
WINDIS
WDTWIN
WDT
Reset
WDT Window Select
CLRWDT Instruction
DS70005127D-page 286
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
23.7
JTAG Interface
The dsPIC33EPXXGS50X family devices implement a
JTAG interface, which supports boundary scan device
testing. Detailed information on this interface is
provided in future revisions of the document.
Note:
23.8
Refer to “Programming and Diagnostics”
(DS70608) in the “dsPIC33/PIC24 Family
Reference Manual” for further information on
usage, configuration and operation of the
JTAG interface.
In-Circuit Serial Programming™
The dsPIC33EPXXGS50X family devices can be serially programmed while in the end application circuit. This
is done with two lines for clock and data, and three other
lines for power, ground and the programming sequence.
Serial programming allows customers to manufacture
boards with unprogrammed devices and then program
the device just before shipping the product. Serial
programming also allows the most recent firmware or a
custom firmware to be programmed. Refer to the
“dsPIC33E/PIC24E Flash Programming Specification
for Devices with Volatile Configuration Bits” (DS70663)
for details about In-Circuit Serial Programming™
(ICSP™).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
23.9
In-Circuit Debugger
When MPLAB® ICD 3 or REAL ICE™ emulator is
selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging
functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/
Debug Clock) and PGEDx (Emulation/Debug Data) pin
functions.
Any of the three pairs of debugging clock/data pins can
be used:
23.10 Code Protection and
CodeGuard™ Security
dsPIC33EPXXGS50X devices offer multiple levels of
security for protecting individual intellectual property. The
program Flash protection can be broken up into three
segments: Boot Segment (BS), General Segment (GS)
and Configuration Segment (CS). Boot Segment has the
highest security privilege and can be thought to have
limited restrictions when accessing other segments.
General Segment has the least security and is intended
for the end user system code. Configuration Segment
contains only the device user configuration data which is
located at the end of the program memory space.
The code protection features are controlled by the
Configuration registers, FSEC and FBSLIM. The FSEC
register controls the code-protect level for each
segment and if that segment is write-protected. The
size of BS and GS will depend on the BSLIM
setting and if the Alternate Interrupt Vector Table (AIVT)
is enabled. The BSLIM bits define the number of
pages for BS with each page containing 512 IW. The
smallest BS size is one page, which will consist of the
Interrupt Vector Table (IVT) and 256 IW of code
protection.
If the AIVT is enabled, the last page of BS will contain
the AIVT and will not contain any BS code. With AIVT
enabled, the smallest BS size is now two pages
(1024 IW), with one page for the IVT and BS code, and
the other page for the AIVT. Write protection of the BS
does not cover the AIVT. The last page of BS can
always be programmed or erased by BS code. The
General Segment will start at the next page and will
consume the rest of program Flash except for the Flash
Configuration Words. The IVT will assume GS security
only if BS is not enabled. The IVT is protected from
being programmed or page erased when either
security segment has enabled write protection.
Note:
Refer to “CodeGuard™ Intermediate
Security” (DS70005182) in the “dsPIC33/
PIC24 Family Reference Manual” for further
information on usage, configuration and
operation of CodeGuard Security.
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).
2013-2017 Microchip Technology Inc.
DS70005127D-page 287
dsPIC33EPXXGS50X FAMILY
The different device security segments are shown in
Figure 23-3. Here, all three segments are shown but
are not required. If only basic code protection is
required, then GS can be enabled independently or
combined with CS, if desired.
Privileged Dual Partition mode performs the same
function as Protected Dual Partition mode, except
additional constraints are applied in an effort to prevent
code in the Boot Segment and General Segment from
being used against each other.
FIGURE 23-3:
FIGURE 23-4:
SECURITY SEGMENTS
EXAMPLE FOR
dsPIC33EP64GS50X
DEVICES
0x000000
IVT
SECURITY SEGMENTS
EXAMPLE FOR
dsPIC33EP64GS50X
DEVICES (DUAL
PARTITION MODES)
0x000000
0x000200
IVT
0x000200
IVT and AIVT
Assume
BS Protection
BS
IVT and AIVT
Assume
BS Protection
AIVT + 256 IW(2)
BS
AIVT + 256IW(2)
BSLIM
BSLIM
GS
GS
CS(1) 0x00B000
Note 1:
2:
If CS is write-protected, the last page (GS
+ CS) of program memory will be protected
from an erase condition.
The last half (256 IW) of the last page of
BS is unusable program memory.
dsPIC33EP64GS50X family devices can be operated
in Dual Partition mode, where security is required for
each partition. When operating in Dual Partition mode,
the Active and Inactive Partitions both contain unique
copies of the Reset vector, Interrupt Vector Tables (IVT
and AIVT, if enabled) and the Flash Configuration
Words. Both partitions have the three security
segments described previously. Code may not be
executed from the Inactive Partition, but it may be
programmed by, and read from, the Active Partition,
subject to defined code protection. Figure 23-4 shows
the different security segments for a device operating in
Dual Partition mode.
The device may also operate in a Protected Dual
Partition mode or in Privileged Dual Partition mode. In
Protected Dual Partition mode, Partition 1 is permanently erase/write-protected. This implementation
allows for a “Factory Default” mode, which provides a
fail-safe backup image to be stored in Partition 1. For
example, a fail-safe bootloader can be placed in
Partition 1, along with a fail-safe backup code image,
which can be used or rewritten into Partition 2 in the
event of a failed Flash update to Partition 2.
DS70005127D-page 288
CS(1)
0x005800
Unimplemented
(Read ‘0’s)
0x400000
IVT
0x400200
IVT and AIVT
Assume
BS Protection
BS
AIVT + 256 IW(2)
BSLIM
GS
CS(1)
Note 1:
2:
0x405800
If CS is write-protected, the last page
(GS + CS) of program memory will be
protected from an erase condition.
The last half (256 IW) of the last page of
BS is unusable program memory.
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
24.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes the
features of the dsPIC33EPXXGS50X
family of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24
Family
Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The dsPIC33EP instruction set is almost identical to
that of the dsPIC30F and dsPIC33F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
•
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 24-1 lists the general symbols used in describing
the instructions.
The dsPIC33E instruction set summary in Table 24-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
2013-2017 Microchip Technology Inc.
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
DS70005127D-page 289
dsPIC33EPXXGS50X FAMILY
Most instructions are a single word. Certain double-word
instructions are designed to provide all the required
information in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it executes as a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the
instruction, or a PSV or table read is performed. In these
cases, the execution takes multiple instruction cycles,
TABLE 24-1:
with the additional instruction cycle(s) executed as a
NOP. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles.
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{}
Optional field or operation
a {b, c, d}
a is selected from the set of values b, c, d
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator write-back destination address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0...W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (direct addressing)
DS70005127D-page 290
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 24-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0...W15}
Wnd
One of 16 Destination Working registers {W0...W15}
Wns
One of 16 Source Working registers {W0...W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X Data Space Prefetch Address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy
Y Data Space Prefetch Address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
2013-2017 Microchip Technology Inc.
DS70005127D-page 291
dsPIC33EPXXGS50X FAMILY
TABLE 24-2:
Base
Instr
#
1
2
3
4
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
Assembly Syntax
# of
# of
Words Cycles(1)
Description
Status Flags
Affected
ADD
Acc
Add Accumulators
1
1
OA,OB,SA,SB
ADD
f
f = f + WREG
1
1
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
OA,OB,SA,SB
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C,DC,N,OV,Z
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
5
BCLR
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
6
BOOTSWP
BOOTSWP
Swap the active and inactive program
Flash Space
1
2
None
7
BRA
BRA
C,Expr
Branch if Carry
1
1 (4)
None
BRA
GE,Expr
Branch if greater than or equal
1
1 (4)
None
BRA
GEU,Expr
Branch if unsigned greater than or equal
1
1 (4)
None
BRA
GT,Expr
Branch if greater than
1
1 (4)
None
BRA
GTU,Expr
Branch if unsigned greater than
1
1 (4)
None
BRA
LE,Expr
Branch if less than or equal
1
1 (4)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1
1 (4)
None
BRA
LT,Expr
Branch if less than
1
1 (4)
None
BRA
LTU,Expr
Branch if unsigned less than
1
1 (4)
None
BRA
N,Expr
Branch if Negative
1
1 (4)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (4)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (4)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (4)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (4)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1
1 (4)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1
1 (4)
None
BRA
OV,Expr
Branch if Overflow
1
1 (4)
None
BRA
SA,Expr
Branch if Accumulator A saturated
1
1 (4)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1
1 (4)
None
BRA
Expr
Branch Unconditionally
1
4
None
BRA
Z,Expr
Branch if Zero
1
1 (4)
None
BRA
Wn
Computed Branch
1
4
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
8
BSET
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005127D-page 292
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 24-2:
Base
Instr
#
9
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BSW
Assembly Syntax
Description
# of
# of
Words Cycles(1)
Status Flags
Affected
BSW.C
Ws,Wb
Write C bit to Ws
1
1
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
None
f,#bit4
Bit Toggle f
1
1
None
10
BTG
BTG
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
11
BTSC
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
12
13
14
15
16
BTSS
BTST
BTSTS
CALL
CLR
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
lit23
Call subroutine
2
4
SFA
CALL
Wn
Call indirect subroutine
1
4
SFA
CALL.L
Wn
Call indirect subroutine (long address)
1
4
SFA
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA,OB,SA,SB
17
CLRWDT
CLRWDT
Clear Watchdog Timer
1
1
WDTO,Sleep
18
COM
COM
f
f=f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
CP
Wb,#lit8
Compare Wb with lit8
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C,DC,N,OV,Z
CP0
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit8
Compare Wb with lit8, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C,DC,N,OV,Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, skip if =
1
1
(2 or 3)
None
CPBEQ
CPBEQ
Wb,Wn,Expr
Compare Wb with Wn, branch if =
1
1 (5)
None
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, skip if >
1
1
(2 or 3)
None
CPBGT
CPBGT
Wb,Wn,Expr
Compare Wb with Wn, branch if >
1
1 (5)
None
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, skip if <
1
1
(2 or 3)
None
CPBLT
CPBLT
Wb,Wn,Expr
Compare Wb with Wn, branch if <
1
1 (5)
None
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, skip if
1
1
(2 or 3)
None
CPBNE
CPBNE
Wb,Wn,Expr
Compare Wb with Wn, branch if
1
1 (5)
None
19
20
21
22
23
24
25
CP
CP0
CPB
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2017 Microchip Technology Inc.
DS70005127D-page 293
dsPIC33EPXXGS50X FAMILY
TABLE 24-2:
Base
Instr
#
26
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
CTXTSWP
Assembly Syntax
# of
# of
Words Cycles(1)
Description
Status Flags
Affected
CTXTSWP
#1it3
Switch CPU register context to context
defined by lit3
1
2
None
CTXTSWP
Wn
Switch CPU register context to context
defined by Wn
1
2
None
27
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
28
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C,DC,N,OV,Z
29
DEC2
30
DISI
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
31
DIV
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
N,Z,C,OV
32
DIVF
DIVF
Wm,Wn
Signed 16/16-bit Fractional Divide
1
18
33
DO
DO
#lit15,Expr
Do code to PC + Expr, lit15 + 1 time
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 time
2
2
None
34
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
35
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
36
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
37
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
38
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
39
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
40
GOTO
GOTO
Expr
Go to address
2
4
None
GOTO
Wn
Go to indirect
1
4
None
41
42
43
INC
INC2
IOR
GOTO.L
Wn
Go to indirect (long address)
1
4
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
C,DC,N,OV,Z
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
OA,OB,OAB,
SA,SB,SAB
44
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
45
LNK
LNK
#lit14
Link Frame Pointer
1
1
SFA
46
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
47
MAC
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005127D-page 294
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 24-2:
Base
Instr
#
48
49
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
MOV
MOVPAG
Assembly Syntax
Description
# of
# of
Words Cycles(1)
Status Flags
Affected
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
None
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
MOVPAG
#lit10,DSRPAG
Move 10-bit literal to DSRPAG
1
1
None
MOVPAG
#lit8,TBLPAG
Move 8-bit literal to TBLPAG
1
1
None
MOVPAGW
Ws, DSRPAG
Move Ws to DSRPAG
1
1
None
MOVPAGW
Ws, TBLPAG
Move Ws to TBLPAG
1
1
None
50
MOVSAC
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
Prefetch and store accumulator
1
1
None
51
MPY
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
52
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
53
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
54
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
signed(Ws)
1
1
None
MUL.SS
Wb,Ws,Acc
Accumulator = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,Ws,Acc
Accumulator = signed(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Acc
Accumulator = signed(Wb) * unsigned(lit5)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
signed(Ws)
1
1
None
MUL.US
Wb,Ws,Acc
Accumulator = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.UU
Wb,#lit5,Acc
Accumulator = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,Ws,Acc
Accumulator = unsigned(Wb) *
unsigned(Ws)
1
1
None
MULW.SS
Wb,Ws,Wnd
Wnd = signed(Wb) * signed(Ws)
1
1
None
MULW.SU
Wb,Ws,Wnd
Wnd = signed(Wb) * unsigned(Ws)
1
1
None
MULW.US
Wb,Ws,Wnd
Wnd = unsigned(Wb) * signed(Ws)
1
1
None
MULW.UU
Wb,Ws,Wnd
Wnd = unsigned(Wb) * unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(lit5)
1
1
None
MUL.SU
Wb,#lit5,Wnd
Wnd = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
Wnd = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2017 Microchip Technology Inc.
DS70005127D-page 295
dsPIC33EPXXGS50X FAMILY
TABLE 24-2:
Base
Instr
#
55
56
57
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
NEG
NOP
POP
Assembly Syntax
PUSH
Status Flags
Affected
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
1
2
None
POP.S
58
# of
# of
Words Cycles(1)
Description
PUSH
Push Shadow Registers
1
1
None
59
PWRSAV
PWRSAV
#lit1
Go into Sleep or Idle mode
1
1
WDTO,Sleep
60
RCALL
RCALL
Expr
Relative Call
1
4
SFA
RCALL
Wn
Computed Call
1
4
SFA
REPEAT
#lit15
Repeat Next Instruction lit15 + 1 time
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 time
1
1
None
None
PUSH.S
61
REPEAT
62
RESET
RESET
Software device Reset
1
1
63
RETFIE
RETFIE
Return from interrupt
1
6 (5)
SFA
64
RETLW
RETLW
Return with literal in Wn
1
6 (5)
SFA
65
RETURN
RETURN
Return from Subroutine
1
6 (5)
SFA
66
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
None
67
68
69
RLNC
RRC
RRNC
#lit10,Wn
70
SAC
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
71
SE
SE
Ws,Wnd
Wnd = sign-extended Ws
1
1
C,N,Z
72
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
73
SFTAC
Note 1:
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005127D-page 296
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 24-2:
Base
Instr
#
74
75
76
77
78
79
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
SL
SUB
SUBB
SUBR
SUBBR
SWAP
Assembly Syntax
Description
# of
# of
Words Cycles(1)
Status Flags
Affected
SL
f
f = Left Shift f
1
1
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
SUBB
f
f = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C,DC,N,OV,Z
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C,DC,N,OV,Z
SWAP.b
Wn
Wn = nibble swap Wn
1
1
None
SWAP
Wn
Wn = byte swap Wn
1
1
None
80
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
1
5
None
81
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
5
None
82
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
83
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
84
ULNK
ULNK
Unlink Frame Pointer
1
1
SFA
85
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
1
1
C,Z,N
86
ZE
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2017 Microchip Technology Inc.
DS70005127D-page 297
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 298
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
25.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
25.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2013-2017 Microchip Technology Inc.
DS70005127D-page 299
dsPIC33EPXXGS50X FAMILY
25.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
25.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
25.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
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dsPIC33EPXXGS50X FAMILY
25.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
25.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2013-2017 Microchip Technology Inc.
25.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the
MPLAB IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
25.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
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dsPIC33EPXXGS50X FAMILY
25.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
25.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
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dsPIC33EPXXGS50X FAMILY
26.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33EPXXGS50X family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EPXXGS50X family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) ................................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3) ................................................... -0.3V to +3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................300 mA
Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin ..................................................................................................25 mA
Maximum current sunk by all ports(2) ....................................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
2013-2017 Microchip Technology Inc.
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26.1
DC Characteristics
TABLE 26-1:
OPERATING MIPS vs. VOLTAGE
VDD Range
(in Volts)
Characteristic
Maximum MIPS
Temperature Range
(in °C)
dsPIC33EPXXGS50X Family
—
3.0V to 3.6V(1)
-40°C to +85°C
70
—
3.0V to 3.6V(1)
-40°C to +125°C
60
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators)
may have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 26-13 for the minimum and maximum BOR values.
TABLE 26-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typ.
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices
Extended Temperature Devices
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 26-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ.
Max.
Unit
Notes
Package Thermal Resistance, 64-Pin TQFP 10x10x1 mm
JA
49.0
—
°C/W
1
Package Thermal Resistance, 48-Pin TQFP 7x7x1.0 mm
JA
63.0
—
°C/W
1
Package Thermal Resistance, 44-Pin QFN 8x8 mm
JA
29.0
—
°C/W
1
Package Thermal Resistance, 44-Pin TQFP 10x10x1 mm
JA
50.0
—
°C/W
1
Package Thermal Resistance, 28-Pin QFN-S 6x6x0.9 mm
JA
30.0
—
°C/W
1
Package Thermal Resistance, 28-Pin UQFN 6x6x0.5 mm
JA
26.0
—
°C/W
1
Package Thermal Resistance, 28-Pin SOIC 7.50 mm
JA
70.0
—
°C/W
1
Note 1:
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS70005127D-page 304
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dsPIC33EPXXGS50X FAMILY
TABLE 26-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
3.0
—
3.6
V
1.8
—
—
V
2
—
—
Conditions
Operating Voltage
DC10
VDD
DC12
VDR
Supply Voltage
(2)
RAM Retention Voltage
+25ºC, +85ºC, +125ºC
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
1.0
—
—
V/ms
Note 1:
2:
-40ºC
0V-3V in 3 ms
Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators) may
have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 26-13 for the minimum and maximum BOR values.
This is the limit to which VDD may be lowered and the RAM contents will always be retained.
TABLE 26-5:
FILTER CAPACITOR (CEFC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
CEFC
Note 1:
Characteristics
External Filter Capacitor
Value(1)
Min.
Typ.
Max.
Units
Comments
4.7
10
—
F
Capacitor must have a low
series resistance ( (VDD + 0.3) for pins that are not 5V tolerant only.
Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
Injection Currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70005127D-page 310
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dsPIC33EPXXGS50X FAMILY
TABLE 26-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IIL
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
Input Leakage Current(2,3)
DI50
I/O Pins 5V Tolerant(4)
-1
—
+1
A
VSS VPIN VDD,
pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
VSS VPIN VDD,
pin at high-impedance,
-40°C TA +85°C
DI51a
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
Analog pins shared with
external reference pins,
-40°C TA +85°C
DI51b
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
VSS VPIN VDD,
pin at high-impedance,
-40°C TA +125°C
DI51c
I/O Pins Not 5V Tolerant(4)
-1
—
+1
A
Analog pins shared with
external reference pins,
-40°C TA +125°C
DI55
MCLR
-5
—
+5
A
VSS VPIN VDD
DI56
OSC1
-5
—
+5
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL Source < (VSS – 0.3). Characterized but not tested.
VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
Injection Currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2013-2017 Microchip Technology Inc.
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TABLE 26-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
IICT
3:
4:
5:
6:
7:
8:
9:
Units
Conditions
0
—
-5(5,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
0
—
+5(6,7,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(7)
-20(9)
—
+20(9)
mA
Absolute instantaneous
sum of all ± input injection
currents from all I/O pins
( | IICL | + | IICH | ) IICT
Total Input Injection Current
(sum of all I/O and control
pins)
Note 1:
2:
Max.
Input High Injection Current
DI60b
DI60c
Typ.(1)
Input Low Injection Current
DI60a
IICH
Min.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL Source < (VSS – 0.3). Characterized but not tested.
VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
Injection Currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70005127D-page 312
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dsPIC33EPXXGS50X FAMILY
TABLE 26-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
DO10
VOL
DO20
VOH
DO20A VOH1
Characteristic
Min.
Typ.
Max.
Units
Output Low Voltage
4x Sink Driver Pins(2)
—
—
0.4
V
VDD = 3.3V,
IOL 6 mA, -40°C TA +85°C,
IOL 5 mA, +85°C TA +125°C
Output Low Voltage
8x Sink Driver Pins(3)
—
—
0.4
V
VDD = 3.3V,
IOL 12 mA, -40°C TA +85°C,
IOL 8 mA, +85°C TA +125°C
Output High Voltage
4x Source Driver Pins(2)
2.4
—
—
V
IOH -10 mA, VDD = 3.3V
Output High Voltage
8x Source Driver Pins(3)
2.4
—
—
V
IOH -15 mA, VDD = 3.3V
Output High Voltage
4x Source Driver Pins(2)
1.5(1)
—
—
2.0(1)
—
—
3.0(1)
—
—
IOH -7 mA, VDD = 3.3V
1.5(1)
—
—
IOH -22 mA, VDD = 3.3V
2.0(1)
—
—
3.0(1)
—
—
Output High Voltage
8x Source Driver Pins(3)
Note 1:
2:
3:
Conditions
IOH -14 mA, VDD = 3.3V
V
V
IOH -12 mA, VDD = 3.3V
IOH -18 mA, VDD = 3.3V
IOH -10 mA, VDD = 3.3V
Parameters are characterized but not tested.
Includes RA0-RA2, RB0-RB1, RB9-RB10, RC1-RC2, RC9-RC10, RC12 and RD7 pins.
Includes all I/O pins that are not 4x driver pins (see Note 2).
TABLE 26-13: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.(2)
Typ.
Max.
Units
BOR Event on VDD Transition
High-to-Low
2.65
—
2.95
V
Conditions
BO10
VBOR
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, PGAs and comparators) may have degraded
performance.
Parameters are for design guidance only and are not tested in manufacturing.
The VBOR specification is relative to VDD.
2:
3:
2013-2017 Microchip Technology Inc.
VDD
(Notes 2 and 3)
DS70005127D-page 313
dsPIC33EPXXGS50X FAMILY
TABLE 26-14: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.(1)
Max.
10,000
—
—
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
D131
VPR
VDD for Read
3.0
—
3.6
V
D132b
VPEW
VDD for Self-Timed Write
3.0
—
3.6
V
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated, -40C to +125C
D135
IDDP
Supply Current during
Programming(2)
—
10
—
mA
D136
IPEAK
Instantaneous Peak Current
During Start-up
—
—
150
mA
D137a
TPE
Page Erase Time
19.7
—
20.1
ms
TPE = 146893 FRC cycles,
TA = +85°C (Note 3)
D137b
TPE
Page Erase Time
19.5
—
20.3
ms
TPE = 146893 FRC cycles,
TA = +125°C (Note 3)
D138a
TWW
Word Write Cycle Time
46.5
—
47.3
µs
TWW = 346 FRC cycles,
TA = +85°C (Note 3)
D138b
TWW
Word Write Cycle Time
46.0
—
47.9
µs
TWW = 346 FRC cycles,
TA = +125°C (Note 3)
D139a
TRW
Row Write Time
667
—
679
µs
TRW = 4965 FRC cycles,
TA = +85°C (Note 3)
D139b
TRW
Row Write Time
660
—
687
µs
TRW = 4965 FRC cycles,
TA = +125°C (Note 3)
Note 1:
2:
3:
E/W -40C to +125C
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
Parameter characterized but not tested in manufacturing.
Other conditions: FRC = 7.37 MHz, TUN = 011111 (for Minimum), TUN = 100000 (for
Maximum). This parameter depends on the FRC accuracy (see Table 26-20) and the value of the FRC
Oscillator Tuning register (see Register 8-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.
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dsPIC33EPXXGS50X FAMILY
26.2
AC Characteristics and Timing
Parameters
This section defines the dsPIC33EPXXGS50X family
AC characteristics and timing parameters.
TABLE 26-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
AC CHARACTERISTICS
FIGURE 26-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 26-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
DO50
Characteristic
Min.
Typ.
Max.
Units
Conditions
15
pF
In XT and HS modes, when
external clock is used to drive
OSC1
COSCO
OSC2 Pin
—
—
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C mode
2013-2017 Microchip Technology Inc.
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FIGURE 26-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS25
OS31
OS31
CLKO
OS41
OS40
TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
FIN
OS20
TOSC
OS25
Min.
Typ.(1)
Max.
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
60
MHz
EC
Oscillator Crystal Frequency
3.5
10
—
—
10
40
MHz
MHz
XT
HS
TOSC = 1/FOSC
8.33
—
DC
ns
+125°C
TOSC = 1/FOSC
7.14
—
DC
ns
+85°C
Instruction Cycle Time(2)
16.67
—
DC
ns
+125°C
Instruction Cycle Time(2)
14.28
—
DC
ns
+85°C
Symb
TCY
Characteristic
Conditions
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.45 x TOSC
—
0.55 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3,4)
—
5.2
—
ns
(3,4)
OS41
TckF
CLKO Fall Time
—
5.2
—
ns
OS42
GM
External Oscillator
Transconductance(4)
—
12
—
mA/V
HS, VDD = 3.3V,
TA = +25°C
—
6
—
mA/V
XT, VDD = 3.3V,
TA = +25°C
Note 1:
2:
3:
4:
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
This parameter is characterized but not tested in manufacturing.
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TABLE 26-18: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic
Min.
Typ.(1)
Max.
Units
FPLLI
PLL Voltage Controlled Oscillator
(VCO) Input Frequency Range
0.8
—
8.0
MHz
OS51
FVCO
On-Chip VCO System Frequency
120
—
340
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
ms
-3
0.5
3
%
OS50
OS53
Symbol
DCLK
Note 1:
2:
(2)
CLKO Stability (Jitter)
Conditions
ECPLL, XTPLL modes
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases, or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = ------------------------------------------------------------------------------------------F OSC
--------------------------------------------------------------------------------------Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows:
D CLK
D CLK
D CLK
Effective Jitter = -------------- = -------------- = -------------3.464
120
12
--------10
TABLE 26-19: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
OS56
FHPOUT
On-Chip 16x PLL CCO
Frequency
112
118
120
MHz
OS57
FHPIN
On-Chip 16x PLL Phase
Detector Input Frequency
7.0
7.37
7.5
MHz
OS58
TSU
Frequency Generator Lock
Time
—
—
10
µs
Note 1:
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
2013-2017 Microchip Technology Inc.
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TABLE 26-20: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a
FRC
F20b
FRC
Note 1:
-2
0.5
+2
%
-40°C TA -10°C
-0.9
0.5
+0.9
%
-10°C TA +85°C
VDD = 3.0-3.6V
-2
1
+2
%
+85°C TA +125°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 26-21: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
LPRC
-30
—
+30
%
-40°C TA -10°C
VDD = 3.0-3.6V
-20
—
+20
%
-10°C TA +85°C
VDD = 3.0-3.6V
F21b
LPRC
-30
—
+30
%
+85°C TA +125°C VDD = 3.0-3.6V
Note 1:
This is the change of the LPRC frequency as VDD changes.
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FIGURE 26-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-22: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Typ.(1)
Max.
Units
—
5
10
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
5
10
ns
DI35
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
TRBP
CNx High or Low Time (input)
2
—
—
TCY
DI40
Note 1:
Port Output Rise Time
Min.
Conditions
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
FIGURE 26-4:
BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
Various Delays (depending on configuration)
Reset Sequence
CPU Starts Fetching Code
2013-2017 Microchip Technology Inc.
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TABLE 26-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.(2)
Max. Units
Conditions
SY00
TPU
Power-up Period
—
400
600
s
SY10
TOST
Oscillator Start-up Time
—
1024 TOSC
—
—
TOSC = OSC1 period
SY12
TWDT
Watchdog Timer
Time-out Period
0.81
—
1.22
ms
WDTPRE = 0,
WDTPOST = 0000,
using LPRC tolerances indicated in
F21 (see Table 26-21) at +85°C
3.25
—
4.88
ms
WDTPRE = 1,
WDTPOST = 0000,
using LPRC tolerances indicated in
F21 (see Table 26-21) at +85°C
0.68
0.72
1.2
s
SY13
TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
SY20
TMCLR
MCLR Pulse Width (low)
2
—
—
s
SY30
TBOR
BOR Pulse Width (low)
1
—
—
s
SY35
TFSCM
Fail-Safe Clock Monitor
Delay
—
500
900
s
SY36
TVREG
Voltage Regulator
Standby-to-Active mode
Transition Time
—
—
30
s
SY37
TOSCDFRC FRC Oscillator Start-up
Delay
—
48
—
s
SY38
TOSCDLPRC LPRC Oscillator Start-up
Delay
—
—
70
s
Note 1:
2:
-40°C to +85°C
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
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FIGURE 26-5:
TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10
Tx11
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
Symbol
TTXH
Characteristic(2)
T1CK High
Time
Min.
Typ.
Max.
Units
Conditions
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TA15,
N = Prescale Value
(1, 8, 64, 256)
Asynchronous
35
—
—
ns
Greater of:
20 or
(TCY + 20)/N
—
—
ns
TA11
TTXL
T1CK Low
Time
Synchronous
mode
Asynchronous
10
—
—
ns
TA15
TTXP
T1CK Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
OS60
Ft1
T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON))
DC
—
50
kHz
TA20
TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
2:
Must also meet
Parameter TA15,
N = Prescale Value
(1, 8, 64, 256)
N = Prescale Value
(1, 8, 64, 256)
Timer1 is a Type A timer.
These parameters are characterized but not tested in manufacturing.
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TABLE 26-25: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TB10
TtxH
TxCK High Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale Value
(1, 8, 64, 256)
TB11
TtxL
TxCK Low Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale Value
(1, 8, 64, 256)
TB15
TtxP
TxCK
Input
Period
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = Prescale Value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
TABLE 26-26: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min.
Typ.
Max.
Units
Conditions
TC10
TtxH
TxCK High
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TtxL
TxCK Low
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TtxP
TxCK Input
Period
Synchronous
with Prescaler
2 TCY + 40
—
—
ns
N = Prescale Value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
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FIGURE 26-6:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-27: INPUT CAPTURE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC11
TCCH
ICx Input High Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC15
TCCP
ICx Input Period
Greater of:
25 + 50 or
(1 TCY/N) + 50
—
ns
Note 1:
N = Prescale Value
(1, 4, 16)
These parameters are characterized but not tested in manufacturing.
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FIGURE 26-7:
OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-28: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 26-8:
OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 26-29: OCx/PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
OC15
TFD
Fault Input to PWMx I/O
Change
—
—
TCY + 20
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
DS70005127D-page 324
Conditions
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FIGURE 26-9:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 26-10:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
—
ns
See Parameter DO32
See Parameter DO31
MP10
TFPWM
PWMx Output Fall Time
—
—
MP11
TRPWM
PWMx Output Rise Time
—
—
—
ns
MP20
TFD
Fault Input to PWMx
I/O Change
—
—
15
ns
MP30
TFH
Fault Input Pulse Width
15
—
—
ns
Note 1:
Conditions
These parameters are characterized but not tested in manufacturing.
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TABLE 26-31: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 26-31
—
—
0,1
0,1
0,1
9 MHz
—
Table 26-32
—
1
0,1
1
9 MHz
—
Table 26-33
—
0
0,1
1
15 MHz
—
—
Table 26-34
1
0
0
11 MHz
—
—
Table 26-35
1
1
0
15 MHz
—
—
Table 26-36
0
1
0
11 MHz
—
—
Table 26-37
0
0
0
FIGURE 26-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
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FIGURE 26-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-32: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid After
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 26-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SDOx
MSb
LSb
SP30, SP31
SP40
SDIx
Bit 14 - - - - - -1
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32 (Note 4)
(Note 3)
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31 (Note 4)
SP30
TdoF
SDOx Data Output Fall
Time
—
—
—
ns
See Parameter DO32 (Note 4)
SP31
TdoR
SDOx Data Output Rise
Time
—
—
—
ns
See Parameter DO31 (Note 4)
SP35
TscH2doV, SDOx Data Output Valid
TscL2doV After SCKx Edge
—
6
20
ns
SP36
TdoV2sc, SDOx Data Output Setup
TdoV2scL to First SCKx Edge
30
—
—
ns
SP40
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
30
—
—
ns
SP41
TscH2diL, Hold Time of SDIx Data
TscL2diL Input to SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 26-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35 SP36
SDOx
MSb
Bit 14 - - - - - -1
SP30, SP31
SDIx
MSb In
LSb
SP30, SP31
Bit 14 - - - -1
LSb In
SP40 SP41
Note:Refer
RefertotoFigure
Figure26-1
26-1for
forload
loadconditions.
conditions.
Note:
TABLE 26-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
-40°C to +125°C
(Note 3)
See Parameter DO32
(Note 4)
See Parameter DO31
(Note 4)
See Parameter DO32
(Note 4)
See Parameter DO31
(Note 4)
SP10
FscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid After
—
6
20
ns
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
2013-2017 Microchip Technology Inc.
DS70005127D-page 329
dsPIC33EPXXGS50X FAMILY
FIGURE 26-15:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SCKx
(CKP = 1)
SP72
SP36
SP35
SP72
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70005127D-page 330
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input
Frequency
—
—
Lesser of:
FP or 15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid After
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
—
—
50
ns
Note 1:
2:
3:
4:
SDOx Data Output Valid After
SSx Edge
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2013-2017 Microchip Technology Inc.
DS70005127D-page 331
dsPIC33EPXXGS50X FAMILY
FIGURE 26-16:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SCKx
(CKP = 1)
SP72
SP36
SP35
SP72
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP73
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70005127D-page 332
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input
Frequency
—
—
Lesser of:
FP or 11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid After
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
SP60
TssL2doV
—
—
50
ns
Note 1:
2:
3:
4:
SDOx Data Output Valid after
SSx Edge
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2013-2017 Microchip Technology Inc.
DS70005127D-page 333
dsPIC33EPXXGS50X FAMILY
FIGURE 26-17:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SSx
SP50
SP52
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35 SP36
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70005127D-page 334
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid After
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SSx After SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2013-2017 Microchip Technology Inc.
DS70005127D-page 335
dsPIC33EPXXGS50X FAMILY
FIGURE 26-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SSx
SP50
SP52
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35 SP36
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70005127D-page 336
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-38: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
(Note 4)
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
(Note 4)
SP35
TscH2doV, SDOx Data Output Valid After
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx
Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
(Note 4)
SP52
TscH2ssH, SSx After SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
(Note 4)
Note 1:
2:
3:
4:
(Note 3)
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2013-2017 Microchip Technology Inc.
DS70005127D-page 337
dsPIC33EPXXGS50X FAMILY
FIGURE 26-19:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 26-1 for load conditions.
FIGURE 26-20:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26 IM25
IM10
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 26-1 for load conditions.
DS70005127D-page 338
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-39: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note 1:
2:
3:
4:
Characteristic(4)
Min.(1)
Max.
Units
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2)
—
s
—
s
400 kHz mode TCY/2 (BRG + 2)
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
s
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2)
—
s
—
s
400 kHz mode TCY/2 (BRG + 2)
1 MHz mode(2) TCY/2 (BRG + 2)
—
s
TF:SCL
SDAx and SCLx 100 kHz mode
—
300
ns
Fall Time
300
ns
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
Rise Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(2)
1 MHz mode
40
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(2)
0.2
—
s
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Setup Time
400 kHz mode TCY/2 (BRG + 2)
—
s
1 MHz mode(2) TCY/2 (BRG + 2)
—
s
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Hold Time
400 kHz mode
TCY/2 (BRG +2)
—
s
1 MHz mode(2) TCY/2 (BRG + 2)
—
s
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Setup Time
400 kHz mode TCY/2 (BRG + 2)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
s
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
—
s
Hold Time
400 kHz mode TCY/2 (BRG + 2)
—
s
1 MHz mode(2) TCY/2 (BRG + 2)
—
s
TAA:SCL Output Valid
100 kHz mode
—
3500
ns
from Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
TBF:SDA Bus Free Time 100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(2)
0.5
—
s
Bus Capacitive Loading
—
400
pF
CB
TPGD
Pulse Gobbler Delay
65
390
ns
2
BRG is the value of the I C Baud Rate Generator.
Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
These parameters are characterized but not tested in manufacturing.
2013-2017 Microchip Technology Inc.
Conditions
CB is specified to be
from 10 to 400 pF
CB is specified to be
from 10 to 400 pF
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
(Note 3)
DS70005127D-page 339
dsPIC33EPXXGS50X FAMILY
FIGURE 26-21:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31
IS34
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 26-22:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26 IS25
IS31
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
DS70005127D-page 340
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-40: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(3)
IS10
TLO:SCL Clock Low Time
IS11
THI:SCL
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
IS51
Note
Clock High Time
Min.
Max.
Units
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
4.7
1.3
0.5
4.0
—
—
—
—
s
s
s
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.5
—
s
TF:SCL
SDAx and SCLx 100 kHz mode
—
300
ns
Fall Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
Rise Time
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(1)
1 MHz mode
100
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(1)
0
0.3
s
TSU:STA Start Condition
100 kHz mode
4.7
—
s
Setup Time
400 kHz mode
0.6
—
s
0.25
—
s
1 MHz mode(1)
THD:STA Start Condition
100 kHz mode
4.0
—
s
Hold Time
400 kHz mode
0.6
—
s
0.25
—
s
1 MHz mode(1)
TSU:STO Stop Condition
100 kHz mode
4
—
s
Setup Time
400 kHz mode
0.6
—
s
(1)
1 MHz mode
0.25
—
s
THD:STO Stop Condition
100 kHz mode
4
—
s
Hold Time
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
s
TAA:SCL Output Valid from 100 kHz mode
0
3500
ns
Clock
400 kHz mode
0
1000
ns
1 MHz mode(1)
0
350
ns
TBF:SDA Bus Free Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
0.5
—
s
1 MHz mode(1)
CB
Bus Capacitive Loading
—
400
pF
TPGD
Pulse Gobbler Delay
65
390
ns
1: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.
3: These parameters are characterized but not tested in manufacturing.
2013-2017 Microchip Technology Inc.
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
Time the bus must be free
before a new transmission
can start
(Note 2)
DS70005127D-page 341
dsPIC33EPXXGS50X FAMILY
FIGURE 26-23:
UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX
UXTX
MSb In
Bit 6-1
LSb In
UA10
TABLE 26-41: UARTx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +125°C
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
UA10
TUABAUD
UARTx Baud Time
UA11
FBAUD
UARTx Baud Frequency
UA20
TCWF
Start Bit Pulse Width to Trigger
UARTx Wake-up
Note 1:
2:
Typ.(2)
Max.
Units
66.67
—
—
ns
—
—
15
Mbps
500
—
—
ns
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 26-42: ANALOG CURRENT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +125°C
AC CHARACTERISTICS
Param
Symbol
No.
AVD01 IDD
Note 1:
2:
Characteristic(1)
Analog Modules Current
Consumption
Min.
—
Typ.(2) Max.
9
—
Units
mA
Conditions
Characterized data with the
following modules enabled:
APLL, 5 ADC Cores, 2 PGAs
and 4 Analog Comparators
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS70005127D-page 342
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-43: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(5)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics
Min.
Typical
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 3.0
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
VSS
—
VSS + 0.3
V
The difference between
AVDD supply and VDD
supply must not exceed
±300 mV at all times,
including during device
power-up
Reference Inputs
AD06
VREFL
Reference Voltage Low
—
AVSS
—
V
(Note 1)
AD07
VREF
Absolute Reference
Voltage (VREFH – VREFL)
2.7
—
AVDD
V
(Note 3)
AD08
IREF
Reference Input Current
—
5
10
A
ADC operating or in standby
AD12
VINH-VINL Full-Scale Input Span
—
AVDD
V
Analog Input
AVSS
AD14
VIN
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
AD17
RIN
Recommended
Impedance of Analog
Voltage Source
—
100
—
AD66
VBG
Internal Voltage
Reference Source
—
1.2
—
V
For minimum sampling
time (Note 1)
ADC Accuracy: Pseudo-Differential Input
AD20a Nr
Resolution
12
bits
AD21a INL
Integral Nonlinearity
> -3
—
-1
—
5
13
< 20
LSb AVSS = 0V, AVDD = 3.3V
Gain Error
(Shared Core)
> -1
5
< 10
LSb
Offset Error
(Dedicated Core)
>2
7
< 12
LSb AVSS = 0V, AVDD = 3.3V
Offset Error
(Shared Core)
> -2
3
-3
—
-1
—
< 1.5
LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23b GERR
Gain Error
(Dedicated Core)
>5
13
< 20
LSb AVSS = 0V, AVDD = 3.3V
Gain Error
(Shared Core)
> -1
5
< 10
LSb
Offset Error
(Dedicated Core)
>2
10
< 18
LSb AVSS = 0V, AVDD = 3.3V
Offset Error
(Shared Core)
>2
8
< 15
LSb
—
—
—
—
Guaranteed
AD24b EOFF
AD25b
—
Monotonicity
12
bits
Dynamic Performance
AD31b SINAD
Signal-to-Noise and
Distortion
AD34b ENOB
Effective Number of Bits
Note 1:
2:
3:
4:
5:
63
—
> 65
dB
(Notes 3, 4)
10.3
—
—
bits
(Notes 3, 4)
These parameters are not characterized or tested in manufacturing.
No missing codes, limits based on characterization results.
These parameters are characterized but not tested in manufacturing.
Characterized with a 1 kHz sine wave.
The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.
DS70005127D-page 344
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-44: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS(2)
Param
Symbol
No.
Characteristics
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.(1) Max.
Units
Conditions
Clock Parameters
AD50
TAD
ADC Clock Period
14.28
—
—
ns
Throughput Rate
AD51
FTP
Note 1:
2:
SH0-SH3
—
—
3.25
SH4
—
—
3.25
Msps 70 MHz ADC clock, 12 bits, no pending
Msps conversion at time of trigger
These parameters are characterized but not tested in manufacturing.
The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.
TABLE 26-45: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS
AC/DC
CHARACTERISTICS(2)
Param
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min.
Typ.
Max.
Units
-35
±5
+35
mV
Comments
CM10
VIOFF
Input Offset Voltage
CM11
VICM
Input Common-Mode
Voltage Range(1)
0
—
AVDD
V
CM13
CMRR
Common-Mode
Rejection Ratio
60
—
—
dB
CM14
TRESP
Large Signal Response
—
15
—
ns
V+ input step of 100 mV while
V- input is held at AVDD/2. Delay
measured from analog input pin to
PWMx output pin.
CM15
VHYST
Input Hysteresis
5
10
20
mV
Depends on HYSSEL
CM16
TON
Comparator Enabled to
Valid Output
—
—
1
µs
Note 1:
2:
These parameters are for design guidance only and are not tested in manufacturing.
The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
2013-2017 Microchip Technology Inc.
DS70005127D-page 345
dsPIC33EPXXGS50X FAMILY
TABLE 26-46: DACx MODULE SPECIFICATIONS
AC/DC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
(2)
Characteristic
DA01
EXTREF External Voltage Reference(1)
DA02
CVRES
Min.
Typ.
Max.
Units
0
—
AVDD
V
Resolution
12
bits
DA03
INL
Integral Nonlinearity Error
-16
-12
0
LSB
DA04
DNL
Differential Nonlinearity Error
-1.8
±1
1.8
LSB
DA05
EOFF
Offset Error
-8
3
15
LSB
DA06
EG
Gain Error
-1.2
-0.5
0
%
DA07
TSET
Settling Time(1)
—
700
—
ns
Note 1:
2:
Comments
Output with 2% of desired
output voltage with a
10-90% or 90-10% step
Parameters are for design guidance only and are not tested in manufacturing.
The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
TABLE 26-47: DACx OUTPUT (DACOUTx PIN) SPECIFICATIONS
DC
CHARACTERISTICS(1)
Param
Symbol
No.
DA11
RLOAD
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
Min.
Typ.
Max.
Units
Resistive Output Load
Impedance
10K
—
—
Ohm
Comments
DA11a CLOAD
Output Load
Capacitance
—
—
35
pF
Including output pin
capacitance
DA12
IOUT
Output Current Drive
Strength
—
300
—
µA
Sink and source
DA13
VRANGE
Output Drive Voltage
Range at Current
Drive of 300 µA
AVSS + 250 mV
—
AVDD – 900 mV
V
DA14
VLRANGE Output Drive Voltage
AVSS + 50 mV
Range at Reduced
Current Drive of 50 µA
—
AVDD – 500 mV
V
DA15
IDD
Current Consumed
when Module is
Enabled
—
—
1.3 x IOUT
µA
DA30
VOFFSET
Input Offset Voltage
—
5
—
mV
Note 1:
Module will always
consume this current,
even if no load is
connected to the output
The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
DS70005127D-page 346
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
TABLE 26-48: PGAx MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
(1)
AC/DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
Comments
PA01
VIN
Input Voltage Range
AVSS – 0.3
—
AVDD + 0.3
V
PA02
VCM
Common-Mode Input
Voltage Range
AVSS
—
AVDD – 1.6
V
PA03
PA04
VOS
VOS
Input Offset Voltage
Input Offset Voltage Drift
with Temperature
-10
—
—
15
10
—
mV
µV/C
PA05
RIN+
Input Impedance of
Positive Input
—
>1M || 7 pF
—
|| pF
PA06
RIN-
Input Impedance of
Negative Input
—
10K || 7 pF
—
|| pF
PA07
GERR
Gain Error
-2
-3
—
—
2
3
%
%
Gain = 4x, 8x
Gain = 16x
PA08
LERR
Gain Nonlinearity Error
-4
—
—
—
4
0.5
%
%
Gain = 32x, 64x
% of full scale,
Gain = 16x
PA09
IDD
Current Consumption
—
2.0
—
mA
Small Signal
G = 4x
Bandwidth (-3 dB) G = 8x
G = 16x
—
10
—
MHz
PA10b
PA10c
—
—
5
2.5
—
—
MHz
MHz
PA10d
PA10e
G = 32x
G = 64x
—
—
1.25
0.625
—
—
MHz
MHz
PA10a BW
PA11
OST
PA12
PA13
PA14
Note 1:
—
0.4
—
µs
SR
Output Settling Time to 1%
of Final Value
Output Slew Rate
—
40
—
V/µs
TGSEL
TON
Gain Selection Time
Module Turn On/Setting Time
—
—
1
—
—
10
µs
µs
Module is enabled with
a 2-volt P-P output
voltage swing
Gain = 16x, 100 mV
input step change
Gain = 16x
The PGAx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
TABLE 26-49: CONSTANT-CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS(1)
Param
Symbol
No.
CC01
CC02
IDD
IREG
Characteristic
Current Consumption
Regulation of Current with
Voltage On
Min.
Typ.
Max.
Units
—
—
30
±3
—
—
µA
%
Conditions
CC03 IOUT
Current Output at Terminal
—
10
—
µA
Note 1: The constant-current source module is functional at VBORMIN < VDD < VDDMIN, but with degraded
performance. Unless otherwise stated, module functionality is tested, but not characterized.
2013-2017 Microchip Technology Inc.
DS70005127D-page 347
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 348
2013-2017 Microchip Technology Inc.
DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 27-1:
FIGURE 27-3:
VOH – 4x DRIVER PINS
VOL(V)
0.050
3.6V
-0.045
3.6V
0.045
-0.040
3.3V
0.035
3V
-0.025
-0.020
Absolute Maximum
3V
0.030
0.025
0.020
Absolute Maximum
0.015
-0.010
0.010
-0.005
0.005
0.000
0.000
0.00
0.50
1.50
2.00
2.50
3.00
3.50
0.00
4.00
VOH – 8x DRIVER PINS
FIGURE 27-2:
-0.080
1.00
FIGURE 27-4:
0.50
1.00
1.50
2.00
3.00
3.6V
0.080
-0.070
0.070
3.3V
-0.060
3.3V
0.060
3V
DS70005127D-page 349
IOL(A)
IOH(A)
-0.050
-0.040
0 030
-0.030
3V
0.050
0.040
0.030
Absolute Maximum
Absolute Maximum
-0.020
0 020
0.020
-0.010
0.010
0.000
0.000
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.00
8X
VOL(V)
3.6V
3.50
VOL – 8x DRIVER PINS
VOH(V)
0.00
2.50
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
dsPIC33EPXXGS50X FAMILY
IOL(A)
IOH(A)
-0.030
-0.015
3.3V
0.040
-0.035
IOH(A)
VOL – 4x DRIVER PINS
VOH (V)
-0.050
IOH(A)
2013-2017 Microchip Technology Inc.
27.0
TYPICAL IDOZE CURRENT @ VDD = 3.3V, +25°C
FIGURE 27-7:
300
30.0
250
25.0
200
20.0
IDOZE (mA)
IPD (µA)
TYPICAL IPD CURRENT @ VDD = 3.3V
150
100
50
15.0
10.0
5.0
0
0.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
1:1
120
1:2
Temperature (°C)
FIGURE 27-6:
1:64
1:128
Doze Ratio
TYPICAL IDD CURRENT @ VDD = 3.3V, +25°C
FIGURE 27-8:
TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25°C
12.0
30
10.0
25
IDD (mA)
2013-2017 Microchip Technology Inc.
IIDLE (mA)
8.0
20
15
6.0
4.0
10
2.0
0.0
5
10
20
30
40
MIPS
50
60
70
10
20
30
40
MIPS
50
60
70
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 350
FIGURE 27-5:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 27-10:
7400
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
34.4
34.2
Frequency (kHz)
7350
Frequency (kHz)
2013-2017 Microchip Technology Inc.
FIGURE 27-9:
7300
7250
34
33.8
33.6
33.4
7200
33
7150
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
-20
0
20
40
Temperature (°C)
60
80
100
120
DS70005127D-page 351
dsPIC33EPXXGS50X FAMILY
33.2
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 352
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
28.0
PACKAGING INFORMATION
28.1
Package Marking Information
28-Lead SOIC (.300”)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead UQFN (6x6x0.55 mm)
XXXXXXXX
XXXXXXXX
YYWWNNN
XXXXXXXX
XXXXXXXX
YYWWNNN
Note:
1710017
Example
33EP64GS
502
1710017
28-Lead QFN-S (6x6x0.9 mm)
Legend: XX...X
Y
YY
WW
NNN
dsPIC33EP64GS502
Example
33EP64GS
502
1710017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2013-2017 Microchip Technology Inc.
DS70005127D-page 353
dsPIC33EPXXGS50X FAMILY
28.1
Package Marking Information (Continued)
44-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
44-Lead QFN (8x8 mm)
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
48-Lead TQFP (7x7x1.0 mm)
1
XXXXXXX
XXXYYWW
NNN
64-Lead TQFP (10x10x1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS70005127D-page 354
Example
dsPIC33EP
64GS504
1710017
Example
dsPIC33EP
64GS504
1710017
Example
1
EP64GS
5051710
017
Example
dsPIC33EP
64GS506
1710017
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
28.2
Note:
Package Details
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2017 Microchip Technology Inc.
DS70005127D-page 355
dsPIC33EPXXGS50X FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70005127D-page 356
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2017 Microchip Technology Inc.
DS70005127D-page 357
dsPIC33EPXXGS50X FAMILY
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW
A
C
A1
0.10 C
SEATING
PLANE
(A3)
28X
SIDE VIEW
8X b1
0.08 C
0.10
C A B
D2
0.10
C A B
8X b2
E2
2
1
28X K
2X P
N
e
NOTE 1
L
28X b
BOTTOM VIEW
0.10
0.05
C A B
C
Microchip Technology Drawing C04-385B Sheet 1 of 2
DS70005127D-page 358
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Width
E
Exposed Pad Width
E2
Overall Length
D
Exposed Pad Length
D2
Exposed Pad Corner Chamfer
P
b
Terminal Width
b1
Corner Anchor Pad
Corner Pad, Metal Free Zone
b2
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.45
0.00
4.55
4.55
0.25
0.35
0.15
0.30
0.20
MILLIMETERS
NOM
28
0.65 BSC
0.50
0.02
0.127 REF
6.00 BSC
4.65
6.00 BSC
4.65
0.35
0.30
0.40
0.20
0.40
-
MAX
0.55
0.05
4.75
4.75
0.35
0.43
0.25
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-385B Sheet 2 of 2
2013-2017 Microchip Technology Inc.
DS70005127D-page 359
dsPIC33EPXXGS50X FAMILY
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C2
Y2
EV
28
Y3
X1
1
ØV
2
Y4
G1
C1
EV
G2
Y1
X4
X3
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X28)
X1
Contact Pad Length (X28)
Y1
Corner Anchor (X4)
X3
Y3
Corner Anchor (X4)
Corner Anchor Chamfer (X4)
X4
Corner Anchor Chamfer (X4)
Y4
Contact Pad to Pad (X28)
G1
Contact Pad to Center Pad (X28)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
4.75
4.75
6.00
6.00
0.35
0.80
1.00
1.00
0.35
0.35
0.20
0.20
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2385B
Note:
Corner anchor pads are not connected internally and are designed as mechanical features when the
package is soldered to the PCB.
DS70005127D-page 360
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
2013-2017 Microchip Technology Inc.
DS70005127D-page 361
dsPIC33EPXXGS50X FAMILY
DS70005127D-page 362
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
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ZLWKPP&RQWDFW/HQJWK
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)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
2013-2017 Microchip Technology Inc.
DS70005127D-page 363
dsPIC33EPXXGS50X FAMILY
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
D1
NOTE 2
B
(DATUM A)
(DATUM B)
E1
A
NOTE 1
2X
0.20 H A B
E
A
N
2X
1 2 3
0.20 H A B
TOP VIEW
4X 11 TIPS
0.20 C A B
A
A2
C
SEATING PLANE
0.10 C
SIDE VIEW
A1
1 2 3
N
NOTE 1
44 X b
0.20
e
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2
DS70005127D-page 364
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44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
L
θ
(L1)
SECTION A-A
Notes:
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
A
Overall Height
Standoff
A1
A2
Molded Package Thickness
Overall Width
E
Molded Package Width
E1
D
Overall Length
D1
Molded Package Length
b
Lead Width
c
Lead Thickness
Lead Length
L
Footprint
L1
Foot Angle
θ
MIN
0.05
0.95
0.30
0.09
0.45
0°
MILLIMETERS
NOM
44
0.80 BSC
1.00
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.37
0.60
1.00 REF
3.5°
MAX
1.20
0.15
1.05
0.45
0.20
0.75
7°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exact shape of each corner is optional.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076C Sheet 2 of 2
2013-2017 Microchip Technology Inc.
DS70005127D-page 365
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Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70005127D-page 366
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44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
C
SEATING
PLANE
A1
A
44X
A3
0.08 C
SIDE VIEW
L
0.10
C A B
D2
0.10
C A B
E2
K
2
1
NOTE 1
N
44X b
0.07
0.05
e
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2
2013-2017 Microchip Technology Inc.
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44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.80
0.00
6.25
6.25
0.20
0.30
0.20
MILLIMETERS
NOM
44
0.65 BSC
0.90
0.02
0.20 REF
8.00 BSC
6.45
8.00 BSC
6.45
0.30
0.40
-
MAX
1.00
0.05
6.60
6.60
0.35
0.50
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103D Sheet 2 of 2
DS70005127D-page 368
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
44
G2
1
2
ØV
EV
C2
Y2
G1
Y1
E
SILK SCREEN
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X44)
X1
Contact Pad Length (X44)
Y1
Contact Pad to Contact Pad (X40)
G1
Contact Pad to Center Pad (X44)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
6.60
6.60
8.00
8.00
0.35
0.85
0.30
0.28
0.33
1.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-2103C
2013-2017 Microchip Technology Inc.
DS70005127D-page 369
dsPIC33EPXXGS50X FAMILY
48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48X TIPS
0.20 C A-B D
D
D1
D1
2
D
A
B
E1 E
A
E1
4
NOTE 1
A
E1
2
N
1 2
4X
0.20 H A-B D
D1
4
48x b
0.08
e
C A-B D
TOP VIEW
0.10 C
C
SEATING
PLANE
A
H
A2
0.08 C
A1
SIDE VIEW
Microchip Technology Drawing C04-300-Y8 Rev A Sheet 1 of 2
DS70005127D-page 370
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48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
H
c
E
L
T
(L1)
SECTION A-A
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Standoff
A1
A2
Molded Package Thickness
L
Foot Length
Footprint
L1
I
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
c
Lead Thickness
b
Lead Width
D
Mold Draft Angle Top
E
Mold Draft Angle Bottom
MIN
0.05
0.95
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
48
0.50 BSC
1.00
0.60
1.00 REF
3.5°
9.00 BSC
9.00 BSC
7.00 BSC
7.00 BSC
0.22
12°
12°
MAX
1.20
0.15
1.05
0.75
7°
0.16
0.27
13°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A-B and D to be determined at center line between leads where leads exit
plastic body at datum plane H
Microchip Technology Drawing C04-300-Y8 Rev A Sheet 2 of 2
2013-2017 Microchip Technology Inc.
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48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
SILK SCREEN
48
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X48)
X1
Contact Pad Length (X48)
Y1
Distance Between Pads
G
MIN
MILLIMETERS
NOM
0.50 BSC
8.40
8.40
MAX
0.30
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2300-Y8 Rev A
DS70005127D-page 372
2013-2017 Microchip Technology Inc.
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64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
A
B
E1/2
E1
A
E
A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D
1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
0.08 C
64 X b
0.08
e
A1
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
2013-2017 Microchip Technology Inc.
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64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
E
L
(L1)
T
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Notes:
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Molded Package Thickness
A2
Standoff
A1
Foot Length
L
Footprint
L1
I
Foot Angle
Overall Width
E
Overall Length
D
Molded Package Width
E1
Molded Package Length
D1
c
Lead Thickness
b
Lead Width
D
Mold Draft Angle Top
E
Mold Draft Angle Bottom
MIN
0.95
0.05
0.45
0°
0.09
0.17
11°
11°
MILLIMETERS
NOM
64
0.50 BSC
1.00
0.60
1.00 REF
3.5°
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
0.22
12°
12°
MAX
1.20
1.05
0.15
0.75
7°
0.20
0.27
13°
13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
DS70005127D-page 374
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2017 Microchip Technology Inc.
DS70005127D-page 375
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NOTES:
DS70005127D-page 376
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
APPENDIX A:
REVISION HISTORY
Revision A (June 2013)
This is the initial released version of the document.
Revision B (May 2015)
Adds dsPIC33EPXXGS505 (48-pin) devices to the
document:
• Amends the table on page 2 to add the three new
devices of this group
• Adds the 48-pin TQFP pin diagram on page 7
• Amends Table 26-3 to include thermal packaging
characteristics for 48-pin packages
• Updates Section 28.1 “Package Marking Information” to include package marking details for
48-pin TQFP devices
• Updates Section 28.2 “Package Details” to
include Microchip Drawings C04-183A and
C04-2183A (7x7x1.0 mm 48-lead TQFP)
Changes all references to Dual Boot Flash Program
Memory throughout the text to “Dual Partition Flash
Program Memory”. In addition, all accompanying references to “panels” and “Boot modes” are changed to
“partitions” and “Partition modes”. This includes, but is
not limited, to:
• Section 4.1 “Program Address Space”
• Section 5.4 “Dual Partition Flash Configuration”,
and Register 5-1
• Section 23.10 “Code Protection and CodeGuard™
Security”, and Table 23-2
Replaces the high-speed pipeline A/D Converter
present in pre-production samples with a high-speed,
multiple SAR A/D Converter in production devices:
• Replaces Section 19.0 “High-Speed, 12-Bit
Analog-to-Digital Converter (ADC)” with an
entirely new section of the same title, replacing all
previous figures and registers
• Updates the summary bullet points under
“High-Speed ADC Module” on Page 1 to reflect
the feature set of the new module
• Updates Table 4-3 and Table 7-1 to reflect the
new module’s interrupt structure
• Replaces Table 4-16 with a new register map
• Removes Table 4-16 (“ADC Calibration Register
Map”); subsequent tables are renumbered
accordingly
• Updates Section 23.2 “Device Calibration and
Identification” and Table 23-3 to remove the
ADCAL registers from the Calibration register
table
• Removes all references to the internal temperature sensor, including Table 26-44 (Temperature
Sensor Specifications) and Figure 27-11 (Typical
Temperature Sensor Voltage vs. Current)
Changes the ESR specification of the VCAP filter
capacitor from < 4Ω to < 0.5Ω.
2013-2017 Microchip Technology Inc.
Removes the internal voltage reference in all occurrences. For analog modules, the internal band gap
reference is substituted as a replacement source.
Changes the following register
occurrences throughout the text:
•
•
•
•
names
in
all
“CMPCONx” to “CMPxCON”
“CMPDACx” to “CMPxDAC”
“I2CxCON1” to “I2CxCONL”
“I2CxCON2” to “I2CxCONH”
Updates the text of Section 5.4.2 “Dual Partition
Modes” to change “Untrusted Dual Panel mode” to
“Privileged Dual Partition mode” and clarifies the
mode’s code security features.
Changes the BSS2 Configuration bit to “BSEN”
throughout the text.
Replaces Section 23.3 “User OTP Memory” with new
text to describe the 64-word User OTP Memory space;
also removes Table 23-4.
Amends Table 24-2 with a footnote indicating an
increase of instruction execution cycles for most
instructions under certain conditions.
Updates the following tables in Section 26.0 “Electrical
Characteristics” (in addition to changes previously
noted):
• Table 26-4, with new specification DC12 (and
accompanying footnote)
• Table 26-6, with updated Typical and new Maximum data throughout, and the addition of
Parameter DC27 (with accompanying footnote)
• Table 26-7, Table 26-8 and Table 26-10 with
updated Typical and Maximum data throughout
• Table 26-9 with updated Typical and Maximum
data for Parameters DC61a and DC61b
• Footnotes 6 and 7 of Table 26-11 to clarify the
behavior of 5V tolerant pins
• The “ADC Accuracy” specifications of Table 26-43
• Table 26-45 (Table 26-45 in Revision A) with
updated specifications for Parameter CM15
• Table 26-46 (Table 26-46 in Revision A) with
updated specifications for Parameters DA03
through DA06
Clarifies the text of Footnotes 6 and 7 in Table 26-11
(I/O Pin Input Specifications).
Removes the “Reference Inputs” specifications from
Table 26-43 in their entirety.
Replaces Figure 27-5 through Figure 27-10 with new
characterization graphs to reflect the most current data
and removes “TBD” watermarks.
Updates Section 28.1 “Package Marking Information” to reflect the removal of redundant temperature
and package code information from all package
markings; this is in addition to the new 48-pin package
markings previously described.
Other minor typographic corrections throughout the
document.
DS70005127D-page 377
dsPIC33EPXXGS50X FAMILY
Revision C (October 2015)
Revision D (May 2017)
Updates Note 2 in Table 1-1.
Updates Pin 14 Function on page 3, updates Pin 11
Function on page 4, updates Pin 41 Function on
page 5, updates Pin 41 Function on page 6, updates
Pin 45 Function on page 7 and updates Pin 43
Function on page 8.
Updates Figure 2-5.
Inserts new Section 4.2 “Unique Device Identifier
(UDID)” and adds Table 4-1. Subsequent tables were
renumbered accordingly. Updates Table 4-3 (which
was Table 4-2), Table 4-5 (which was Table 4-4),
Table 4-10 (which was Table 4-9), Table 4-11 (which
was Table 4-10), Table 4-21 (which was Table 4-20),
Table 4-32 (which was Table 4-31), Table 4-36 (which
was Table 4-35) and Table 4-37 (which was Table 4-36).
Updates Section 4.8.1 “Bit-Reversed Addressing
Implementation” (which was Section 4.7.1).
Updates Register 9-1.
Updates Figure 12-2 and Register 12-2.
Updates Register 13-1.
Updates Note 1 in Section 14.0 “Output Compare”.
Updates Register 15-1, Register 15-6, Register 15-20
and Register 15-22.
Updates Table 1-1, Table 4-8, Table 4-9, Table 4-10,
Table 4-11, Table 4-12, Table 4-16, Table 26-4,
Table 26-40, Table 26-43 and Table 26-45.
Updates Register 5-1, Register 8-4, Register 15-22,
Register 19-5,
Register 19-6,
Register 19-26,
Register 19-27, Register 19-28, Register 19-29 and
Register 19-30.
Updates Figure 20-2, Figure 26-20 and Figure 26-22.
Adds 48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm
Body TQFP drawings to Section 28.0 “Packaging
Information” section.
Updates Section 20.6 “Hysteresis”
Updates Figure 17-1.
Updates Register 18-2.
Updates Figure 19-2 and Figure 19-3. Updates
Register 19-1,
Register 19-2,
Register 19-3,
Register 19-4, Register 19-26 and Register 19-33. Adds
Register 19-27.
Updates Figure 21-2.
Updates Section 23.6.2 “Sleep and Idle Modes”.
Updates Table 26-8, Table 26-11, Table 26-29. Adds
new Table 26-42. Subsequent tables were renumbered
accordingly. Updates Table 26-43 (which was
Table 26-42), Table 26-46 (which was Table 26-45) and
Table 26-48 (which was Table 26-47).
Updated diagrams in Section 28.0 “Packaging
Information”.
Updates the Product Identification System section.
Other minor typographic corrections throughout the
document.
DS70005127D-page 378
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
INDEX
A
Absolute Maximum Ratings .............................................. 303
AC Characteristics ............................................................ 315
ADC Specifications ................................................... 343
Analog Current Specifications................................... 342
Analog-to-Digital Conversion Requirements............. 345
Auxiliary PLL Clock ................................................... 317
Capacitive Loading Requirements on
Output Pins ....................................................... 315
External Clock Requirements ................................... 316
High-Speed PWMx Requirements ............................ 325
I/O Requirements...................................................... 319
I2Cx Bus Data Requirements (Master Mode) ........... 339
I2Cx Bus Data Requirements (Slave Mode) ............. 341
Input Capture x Requirements .................................. 323
Internal FRC Accuracy.............................................. 318
Internal LPRC Accuracy............................................ 318
Load Conditions ........................................................ 315
OCx/PWMx Module Requirements ........................... 324
Output Compare x Requirements ............................. 324
PLL Clock.................................................................. 317
Reset, WDT, OST, PWRT Requirements ................. 320
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements .................... 329
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements .................... 328
SPIx Master Mode (Half-Duplex,
Transmit Only) Requirements ........................... 327
SPIx Maximum Data/Clock Rate Summary .............. 326
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements .................... 337
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements .................... 335
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements .................... 331
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) Requirements .................... 333
Temperature and Voltage Specifications .................. 315
Timer1 External Clock Requirements ....................... 321
Timer2/Timer4 External Clock Requirements ........... 322
Timer3/Timer5 External Clock Requirements ........... 322
UARTx I/O Requirements ......................................... 342
AC/DC Characteristics
DACx Specifications ................................................. 346
High-Speed Analog Comparator Specifications........ 345
PGAx Specifications ................................................. 347
Analog-to-Digital Converter. See ADC.
Arithmetic Logic Unit (ALU)................................................. 30
Assembler
MPASM Assembler................................................... 300
MPLAB Assembler, Linker, Librarian ........................ 300
B
Bit-Reversed Addressing .................................................... 73
Example ...................................................................... 74
Implementation ........................................................... 73
Sequence Table (16-Entry)......................................... 74
Block Diagrams
16-Bit Timer1 Module................................................ 163
ADC Module.............................................................. 230
ADC Shared Core ..................................................... 231
2013-2017 Microchip Technology Inc.
Addressing for Table Registers .................................. 77
CALL Stack Frame ..................................................... 69
Connections for On-Chip Voltage Regulator ............ 285
Constant-Current Source.......................................... 275
CPU Core ................................................................... 22
Data Access from Program Space
Address Generation............................................ 75
Dedicated ADC Cores 0-3 ........................................ 231
dsPIC33EPXXGS50X Family ..................................... 11
High-Speed Analog Comparator x............................ 264
High-Speed PWM Architecture................................. 183
Hysteresis Control .................................................... 266
I2Cx Module ............................................................. 216
Input Capture x ......................................................... 171
Interleaved PFC.......................................................... 18
MCLR Pin Connections .............................................. 16
Multiplexing Remappable Outputs for RPn .............. 130
Off-Line UPS .............................................................. 20
Oscillator System...................................................... 104
Output Compare x Module ....................................... 175
PGAx Functions........................................................ 272
PGAx Module ........................................................... 271
Phase-Shifted Full-Bridge Converter.......................... 19
PLL Module .............................................................. 105
Programmer’s Model .................................................. 24
PSV Read Address Generation.................................. 66
Recommended Minimum Connection ........................ 16
Remappable Input for U1RX .................................... 128
Reset System ............................................................. 85
Security Segments for dsPIC33EP64GS50X ........... 288
Security Segments for dsPIC33EP64GS50X
(Dual Partition Modes)...................................... 288
Shared Port Structure............................................... 125
Simplified Conceptual of High-Speed PWM ............. 184
SPIx Module ............................................................. 207
Suggested Oscillator Circuit Placement ..................... 17
Timerx (x = 2 through 5) ........................................... 168
Type B/Type C Timer Pair (32-Bit Timer) ................. 168
UARTx Module ......................................................... 223
Watchdog Timer (WDT)............................................ 286
Brown-out Reset (BOR)............................................ 277, 285
C
C Compilers
MPLAB XC ............................................................... 300
Code Examples
Port Write/Read ........................................................ 126
PWM Write-Protected Register
Unlock Sequence ............................................. 182
PWRSAV Instruction Syntax .................................... 115
Code Protection ........................................................ 277, 287
CodeGuard Security ................................................. 277, 287
Configuration Bits ............................................................. 277
Description................................................................ 280
Constant-Current Source.................................................. 275
Control Register........................................................ 276
Description................................................................ 275
Features Overview ................................................... 275
DS70005127D-page 379
dsPIC33EPXXGS50X FAMILY
CPU
Addressing Modes ...................................................... 21
Clocking System Options .......................................... 105
Fast RC (FRC) Oscillator .................................. 105
FRC Oscillator with PLL (FRCPLL)................... 105
FRC Oscillator with Postscaler ......................... 105
Low-Power RC (LPRC) Oscillator..................... 105
Primary (XT, HS, EC) Oscillator........................ 105
Primary Oscillator with PLL............................... 105
Control Registers ........................................................ 26
Data Space Addressing .............................................. 21
Instruction Set ............................................................. 21
Registers ..................................................................... 21
Resources ................................................................... 25
Customer Change Notification Service ............................. 384
Customer Notification Service........................................... 384
Customer Support ............................................................. 384
D
Data Address Space ........................................................... 37
Memory Map for dsPIC33EP16GS50X Devices ......... 38
Memory Map for dsPIC33EP32GS50X Devices ......... 39
Memory Map for dsPIC33EP64GS50X Devices ......... 40
Near Data Space ........................................................ 37
Organization, Alignment.............................................. 37
SFR Space.................................................................. 37
Width ........................................................................... 37
Data Space
Extended X ................................................................. 69
Paged Data Memory Space (figure) ........................... 67
Paged Memory Scheme ............................................. 66
DC Characteristics
Brown-out Reset (BOR) ............................................ 313
Constant-Current Source Specifications ................... 347
DACx Output (DACOUTx Pin) Specifications ........... 346
Doze Current (IDOZE) ................................................ 309
I/O Pin Input Specifications ....................................... 310
I/O Pin Output Specifications .................................... 313
Idle Current (IIDLE) .................................................... 307
Operating Current (IDD)............................................. 306
Operating MIPS vs. Voltage...................................... 304
Power-Down Current (IPD) ........................................ 308
Program Memory ...................................................... 314
Temperature and Voltage Specifications .................. 305
Watchdog Timer Delta Current (IWDT) .................... 308
DC/AC Characteristics
Graphs and Tables ................................................... 349
Demo/Development Boards, Evaluation and
Starter Kits ................................................................ 302
Development Support ....................................................... 299
Device Calibration ............................................................. 283
Addresses ................................................................. 283
and Identification ....................................................... 283
Device Programmer
MPLAB PM3 ............................................................. 301
Doze Mode........................................................................ 117
DSP Engine......................................................................... 30
E
Electrical Characteristics................................................... 303
AC ............................................................................. 315
Equations
Device Operating Frequency .................................... 105
FPLLO Calculation...................................................... 105
FVCO Calculation....................................................... 105
Errata .................................................................................. 10
DS70005127D-page 380
F
Filter Capacitor (CEFC) Specifications .............................. 305
Flash Program Memory ...................................................... 77
and Table Instructions ................................................ 77
Control Registers ........................................................ 80
Dual Partition Flash Configuration .............................. 79
Operations .................................................................. 78
Resources .................................................................. 79
RTSP Operation ......................................................... 78
Flexible Configuration ....................................................... 277
G
Getting Started Guidelines.................................................. 15
Connection Requirements .......................................... 15
CPU Logic Filter Capacitor Connection (VCAP) .......... 16
Decoupling Capacitors................................................ 15
External Oscillator Pins............................................... 17
ICSP Pins ................................................................... 17
Master Clear (MCLR) Pin ........................................... 16
Oscillator Value Conditions on Start-up...................... 18
Targeted Applications ................................................. 18
Unused I/Os................................................................ 18
H
High-Speed Analog Comparator
Applications .............................................................. 265
Description................................................................ 264
Digital-to-Analog Comparator (DAC) ........................ 265
Features Overview.................................................... 263
Hysteresis ................................................................. 266
Pulse Stretcher and Digital Logic.............................. 265
Resources ................................................................ 266
High-Speed PWM
Description................................................................ 181
Features ................................................................... 181
Resources ................................................................ 182
Write-Protected Registers......................................... 182
High-Speed, 12-Bit Analog-to-Digital
Converter (ADC) ....................................................... 229
Control Registers ...................................................... 232
Features Overview.................................................... 229
Resources ................................................................ 232
I
I/O Ports............................................................................ 125
Configuring Analog/Digital Port Pins......................... 126
Helpful Tips............................................................... 132
Open-Drain Configuration......................................... 126
Parallel I/O (PIO) ...................................................... 125
Resources ................................................................ 133
Write/Read Timing .................................................... 126
In-Circuit Debugger........................................................... 287
MPLAB ICD 3 ........................................................... 301
PICkit 3 Programmer ................................................ 301
In-Circuit Emulation .......................................................... 277
In-Circuit Serial Programming (ICSP)....................... 277, 287
Input Capture .................................................................... 171
Control Registers ...................................................... 172
Resources ................................................................ 171
Input Change Notification (ICN)........................................ 126
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
Instruction Addressing Modes............................................. 70
File Register Instructions ............................................ 70
Fundamental Modes Supported.................................. 70
MAC Instructions......................................................... 71
MCU Instructions ........................................................ 70
Move and Accumulator Instructions............................ 71
Other Instructions........................................................ 71
Instruction Set Summary................................................... 289
Overview ................................................................... 292
Symbols Used in Opcode Descriptions..................... 290
Instruction-Based Power-Saving Modes ........................... 115
Idle ............................................................................ 116
Sleep......................................................................... 116
Inter-Integrated Circuit (I2C).............................................. 215
Control Registers ...................................................... 217
Resources................................................................. 215
Inter-Integrated Circuit. See I2C.
Internet Address................................................................ 384
Interrupt Controller
Alternate Interrupt Vector Table (AIVT) ...................... 89
Control and Status Registers ...................................... 94
INTCON1 ............................................................ 94
INTCON2 ............................................................ 94
INTCON3 ............................................................ 94
INTCON4 ............................................................ 94
INTTREG ............................................................ 94
Interrupt Vector Details ............................................... 92
Interrupt Vector Table (IVT) ........................................ 89
Reset Sequence ......................................................... 89
Resources................................................................... 94
Interrupts Coincident with Power Save Instructions.......... 116
J
JTAG Boundary Scan Interface ........................................ 277
JTAG Interface .................................................................. 287
L
Leading-Edge Blanking (LEB)........................................... 181
LPRC Oscillator
Use with WDT ........................................................... 286
M
Memory Organization.......................................................... 31
Resources................................................................... 41
Microchip Internet Web Site .............................................. 384
Modulo Addressing ............................................................. 72
Applicability ................................................................. 73
Operation Example ..................................................... 72
Start and End Address................................................ 72
W Address Register Selection .................................... 72
MPLAB REAL ICE In-Circuit Emulator System................. 301
MPLAB X Integrated Development
Environment Software............................................... 299
MPLINK Object Linker/MPLIB Object Librarian ................ 300
O
Oscillator
Control Registers ...................................................... 107
Resources................................................................. 106
Output Compare ............................................................... 175
Control Registers ...................................................... 176
Resources................................................................. 175
2013-2017 Microchip Technology Inc.
P
Packaging ......................................................................... 353
Details....................................................................... 355
Marking..................................................................... 353
Peripheral Module Disable (PMD) .................................... 117
Peripheral Pin Select (PPS).............................................. 127
Available Peripherals................................................ 127
Available Pins ........................................................... 127
Control ...................................................................... 127
Control Registers...................................................... 134
Input Mapping........................................................... 128
Output Mapping ........................................................ 130
Output Selection for Remappable Pins .................... 131
Selectable Input Sources.......................................... 129
PGA
Pinout I/O Descriptions (table)............................................ 12
Power-Saving Features .................................................... 115
Clock Frequency and Switching ............................... 115
Resources ................................................................ 117
Program Address Space..................................................... 31
Construction ............................................................... 75
Data Access from Program Memory Using
Table Instructions ............................................... 76
Memory Map (dsPIC33EP16GS50X Devices) ........... 32
Memory Map (dsPIC33EP32GS50X Devices) ........... 33
Memory Map (dsPIC33EP64GS50X Devices,
Dual Partition)..................................................... 35
Memory Map (dsPIC33EP64GS50X Devices) ........... 34
Table Read High Instructions (TBLRDH) ................... 76
Table Read Low Instructions (TBLRDL) ..................... 76
Program Memory
Interfacing with Data Memory Spaces........................ 75
Organization ............................................................... 36
Reset Vector............................................................... 36
Programmable Gain Amplifier (PGA)................................ 271
Description................................................................ 272
Resources ................................................................ 273
Programmable Gain Amplifier. See PGA.
Programmer’s Model .......................................................... 23
Register Descriptions ................................................. 23
R
Register Maps
ADC ............................................................................ 54
Analog Comparator .................................................... 61
Configuration Registers ............................................ 278
Constant-Current Source............................................ 60
CPU Core ................................................................... 42
I2C1 and I2C2 ............................................................ 52
Input Capture 1 through Input Capture 4.................... 47
Interrupt Controller...................................................... 44
JTAG Interface ........................................................... 61
NVM............................................................................ 59
Output Compare 1 through Output Compare 4 .......... 48
Peripheral Pin Select Input ......................................... 58
Peripheral Pin Select Output
(dsPIC33EPXXGS502 Devices)......................... 56
Peripheral Pin Select Output
(dsPIC33EPXXGS504/505 Devices).................. 56
Peripheral Pin Select Output
(dsPIC33EPXXGS506 Devices)......................... 57
DS70005127D-page 381
dsPIC33EPXXGS50X FAMILY
PMD ............................................................................ 60
PORTA (dsPIC33EPXXGS502 Devices) .................... 62
PORTA (dsPIC33EPXXGS504/505 Devices) ............. 63
PORTA (dsPIC33EPXXGS506 Devices) .................... 64
PORTB (dsPIC33EPXXGS502 Devices) .................... 62
PORTB (dsPIC33EPXXGS504/505 Devices) ............. 63
PORTB (dsPIC33EPXXGS506 Devices) .................... 64
PORTC (dsPIC33EPXXGS504/505 Devices)............. 63
PORTC (dsPIC33EPXXGS506 Devices).................... 64
PORTD (dsPIC33EPXXGS506 Devices).................... 65
Programmable Gain Amplifier ..................................... 60
PWM ........................................................................... 49
PWM Generator 1 ....................................................... 49
PWM Generator 2 ....................................................... 50
PWM Generator 3 ....................................................... 50
PWM Generator 4 ....................................................... 51
PWM Generator 5 ....................................................... 51
SPI1 and SPI2 ............................................................ 53
System Control ........................................................... 59
Timer1 through Timer5 ............................................... 46
UART1 and UART2 .................................................... 52
Registers
ACLKCON (Auxiliary Clock Divisor Control) ............. 112
ADCAL0H (ADC Calibration 0 High) ......................... 256
ADCAL0L (ADC Calibration 0 Low) .......................... 255
ADCAL1H (ADC Calibration 1 High) ......................... 257
ADCMPxCON (ADC Digital Comparator x
Control) ............................................................. 258
ADCMPxENH (ADC Digital Comparator x
Channel Enable High)....................................... 259
ADCMPxENL (ADC Digital Comparator x
Channel Enable Low)........................................ 259
ADCON1H (ADC Control 1 High) ............................. 233
ADCON1L (ADC Control 1 Low) ............................... 232
ADCON2H (ADC Control 2 High) ............................. 235
ADCON2L (ADC Control 2 Low) ............................... 234
ADCON3H (ADC Control 3 High) ............................. 237
ADCON3L (ADC Control 3 Low) ............................... 236
ADCON4H (ADC Control 4 High) ............................. 239
ADCON4L (ADC Control 4 Low) ............................... 238
ADCON5H (ADC Control 5 High) ............................. 241
ADCON5L (ADC Control 5 Low) ............................... 240
ADCORExH (Dedicated ADC Core x
Control High)..................................................... 243
ADCORExL (Dedicated ADC Core x
Control Low)...................................................... 242
ADEIEH (ADC Early Interrupt Enable High) ............. 245
ADEIEL (ADC Early Interrupt Enable Low) ............... 245
ADEISTATH (ADC Early Interrupt Status High)........ 246
ADEISTATL (ADC Early Interrupt Status Low) ......... 246
ADFLxCON (ADC Digital Filter x Control)................. 260
ADIEH (ADC Interrupt Enable High) ......................... 249
ADIEL (ADC Interrupt Enable Low) .......................... 249
ADLVLTRGH (ADC Level-Sensitive Trigger
Control High)..................................................... 244
ADLVLTRGL (ADC Level-Sensitive Trigger
Control Low)...................................................... 244
ADMOD0H (ADC Input Mode Control 0 High) .......... 247
ADMOD0L (ADC Input Mode Control 0 Low) ........... 247
ADMOD1L (ADC Input Mode Control 1 Low) ........... 248
ADSTATH (ADC Data Ready Status High)............... 250
ADSTATL (ADC Data Ready Status Low) ................ 250
ADTRIGxH (ADC Channel Trigger x
Selection High).................................................. 253
DS70005127D-page 382
ADTRIGxL (ADC Channel Trigger x
Selection Low) .................................................. 251
ALTDTRx (PWMx Alternate Dead-Time).................. 197
AUXCONx (PWMx Auxiliary Control) ....................... 205
CHOP (PWMx Chop Clock Generator)..................... 190
CLKDIV (Clock Divisor) ............................................ 109
CMPxCON (Comparator x Control) .......................... 267
CMPxDAC (Comparator x DAC Control) .................. 269
CORCON (Core Control) ...................................... 28, 96
CTXTSTAT (CPU W Register Context Status)........... 29
DEVID (Device ID).................................................... 284
DEVREV (Device Revision)...................................... 284
DTRx (PWMx Dead-Time)........................................ 197
FCLCONx (PWMx Fault Current-Limit Control)........ 201
I2CxCONH (I2Cx Control High) ................................ 219
I2CxCONL (I2Cx Control Low) ................................. 217
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 222
I2CxSTAT (I2Cx Status) ........................................... 220
ICxCON1 (Input Capture x Control 1)....................... 172
ICxCON2 (Input Capture x Control 2)....................... 173
INTCON1 (Interrupt Control 1).................................... 97
INTCON2 (Interrupt Control 2).................................... 99
INTCON3 (Interrupt Control 3).................................. 100
INTCON4 (Interrupt Control 4).................................. 100
INTTREG (Interrupt Control and Status) .................. 101
IOCONx (PWMx I/O Control).................................... 199
ISRCCON (Constant-Current Source Control) ......... 276
LEBCONx (PWMx Leading-Edge
Blanking Control) .............................................. 203
LEBDLYx (PWMx Leading-Edge
Blanking Delay) ................................................ 204
LFSR (Linear Feedback Shift) .................................. 114
MDC (PWMx Master Duty Cycle) ............................. 191
NVMADR (Nonvolatile Memory
Lower Address) .................................................. 83
NVMADRU (Nonvolatile Memory
Upper Address) .................................................. 83
NVMCON (Nonvolatile Memory (NVM) Control)......... 81
NVMKEY (Nonvolatile Memory Key) .......................... 84
NVMSRCADR (NVM Source Data Address) .............. 84
OCxCON1 (Output Compare x Control 1) ................ 176
OCxCON2 (Output Compare x Control 2) ................ 178
OSCCON (Oscillator Control) ................................... 107
OSCTUN (FRC Oscillator Tuning)............................ 111
PDCx (PWMx Generator Duty Cycle)....................... 194
PGAxCAL (PGAx Calibration) .................................. 274
PGAxCON (PGAx Control) ....................................... 273
PHASEx (PWMx Primary Phase-Shift)..................... 195
PLLFBD (PLL Feedback Divisor).............................. 110
PMD1 (Peripheral Module Disable Control 1)........... 118
PMD2 (Peripheral Module Disable Control 2)........... 119
PMD3 (Peripheral Module Disable Control 3)........... 120
PMD4 (Peripheral Module Disable Control 4)........... 120
PMD6 (Peripheral Module Disable Control 6)........... 121
PMD7 (Peripheral Module Disable Control 7)........... 122
PMD8 (Peripheral Module Disable Control 8)........... 123
PTCON (PWMx Time Base Control) ........................ 185
PTCON2 (PWMx Clock Divider Select 2) ................. 186
PTPER (PWMx Primary Master
Time Base Period)............................................ 187
PWMCAPx (PWMx Primary
Time Base Capture) ......................................... 206
PWMCONx (PWMx Control)..................................... 192
PWMKEY (PWMx Protection Lock/Unlock Key)....... 191
RCON (Reset Control)................................................ 87
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
REFOCON (Reference Oscillator Control) ............... 113
RPINR0 (Peripheral Pin Select Input 0).................... 134
RPINR1 (Peripheral Pin Select Input 1).................... 134
RPINR11 (Peripheral Pin Select Input 11)................ 139
RPINR12 (Peripheral Pin Select Input 12)................ 140
RPINR13 (Peripheral Pin Select Input 13)................ 141
RPINR18 (Peripheral Pin Select Input 18)................ 142
RPINR19 (Peripheral Pin Select Input 19)................ 143
RPINR2 (Peripheral Pin Select Input 2).................... 135
RPINR20 (Peripheral Pin Select Input 20)................ 144
RPINR21 (Peripheral Pin Select Input 21)................ 145
RPINR22 (Peripheral Pin Select Input 22)................ 146
RPINR23 (Peripheral Pin Select Input 23)................ 147
RPINR3 (Peripheral Pin Select Input 3).................... 136
RPINR37 (Peripheral Pin Select Input 37)................ 148
RPINR38 (Peripheral Pin Select Input 38)................ 149
RPINR42 (Peripheral Pin Select Input 42)................ 150
RPINR43 (Peripheral Pin Select Input 43)................ 151
RPINR7 (Peripheral Pin Select Input 7).................... 137
RPINR8 (Peripheral Pin Select Input 8).................... 138
RPOR0 (Peripheral Pin Select Output 0).................. 152
RPOR1 (Peripheral Pin Select Output 1).................. 152
RPOR10 (Peripheral Pin Select Output 10).............. 157
RPOR11 (Peripheral Pin Select Output 11).............. 157
RPOR12 (Peripheral Pin Select Output 12).............. 158
RPOR13 (Peripheral Pin Select Output 13).............. 158
RPOR14 (Peripheral Pin Select Output 14).............. 159
RPOR15 (Peripheral Pin Select Output 15).............. 159
RPOR16 (Peripheral Pin Select Output 16).............. 160
RPOR17 (Peripheral Pin Select Output 17).............. 160
RPOR18 (Peripheral Pin Select Output 18).............. 161
RPOR2 (Peripheral Pin Select Output 2).................. 153
RPOR3 (Peripheral Pin Select Output 3).................. 153
RPOR4 (Peripheral Pin Select Output 4).................. 154
RPOR5 (Peripheral Pin Select Output 5).................. 154
RPOR6 (Peripheral Pin Select Output 6).................. 155
RPOR7 (Peripheral Pin Select Output 7).................. 155
RPOR8 (Peripheral Pin Select Output 8).................. 156
RPOR9 (Peripheral Pin Select Output 9).................. 156
SDCx (PWMx Secondary Duty Cycle) ...................... 194
SEVTCMP (PWMx Special Event Compare)............ 187
SPHASEx (PWMx Secondary Phase-Shift).............. 196
SPIxCON1 (SPIx Control 1)...................................... 211
SPIxCON2 (SPIx Control 2)...................................... 213
SPIxSTAT (SPIx Status and Control) ....................... 209
SR (CPU STATUS)............................................... 26, 95
SSEVTCMP (PWMx Secondary
Special Event Compare) ................................... 190
STCON (PWMx Secondary Master
Time Base Control) ........................................... 188
STCON2 (PWMx Secondary Clock Divider
Select 2)............................................................ 189
STPER (PWMx Secondary Master
Time Base Period) ............................................ 189
STRIGx (PWMx Secondary Trigger
Compare Value)................................................ 202
T1CON (Timer1 Control)........................................... 165
TRGCONx (PWMx Trigger Control).......................... 198
TRIGx (PWMx Primary Trigger
Compare Value)................................................ 200
TxCON (Timer2/4 Control)........................................ 169
TyCON (Timer3/5 Control)........................................ 170
UxMODE (UARTx Mode).......................................... 225
UxSTA (UARTx Status and Control)......................... 227
2013-2017 Microchip Technology Inc.
Resets ................................................................................ 85
Brown-out Reset (BOR).............................................. 85
Configuration Mismatch Reset (CM) .......................... 85
Illegal Condition Reset (IOPUWR) ............................. 85
Illegal Opcode .................................................... 85
Security .............................................................. 85
Uninitialized W Register ..................................... 85
Master Clear (MCLR) Pin Reset................................. 85
Power-on Reset (POR)............................................... 85
RESET Instruction (SWR) .......................................... 85
Resources .................................................................. 86
Trap Conflict Reset (TRAPR) ..................................... 85
Watchdog Timer Time-out Reset (WDTO) ................. 85
Revision History................................................................ 377
S
Serial Peripheral Interface (SPI) ....................................... 207
Serial Peripheral Interface. See SPI.
Software Simulator
MPLAB X SIM........................................................... 301
Special Features of the CPU ............................................ 277
SPI
Control Registers...................................................... 209
Helpful Tips............................................................... 208
Resources ................................................................ 208
T
Thermal Operating Conditions.......................................... 304
Thermal Packaging Characteristics .................................. 304
Third-Party Development Tools ........................................ 302
Timer1 .............................................................................. 163
Control Register........................................................ 165
Mode Settings........................................................... 163
Resources ................................................................ 164
Timer2/3 and Timer4/5 ..................................................... 167
Control Registers...................................................... 169
Resources ................................................................ 167
Timing Diagrams
BOR and Master Clear Reset Characteristics .......... 319
External Clock .......................................................... 316
High-Speed PWMx Fault Characteristics ................. 325
High-Speed PWMx Module Characteristics ............. 325
I/O Characteristics .................................................... 319
I2Cx Bus Data (Master Mode) .................................. 338
I2Cx Bus Data (Slave Mode) .................................... 340
I2Cx Bus Start/Stop Bits (Master Mode)................... 338
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 340
Input Capture x (ICx) Characteristics ....................... 323
OCx/PWMx Characteristics ...................................... 324
Output Compare x (OCx) Characteristics ................. 324
SPIx Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) ........................................... 329
SPIx Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ........................................... 328
SPIx Master Mode (Half-Duplex,
Transmit Only, CKE = 0) .................................. 326
SPIx Master Mode (Half-Duplex,
Transmit Only, CKE = 1) .................................. 327
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 336
SPIx Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 334
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 330
DS70005127D-page 383
dsPIC33EPXXGS50X FAMILY
SPIx Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 332
Timer1-Timer5 External Clock Characteristics.......... 321
UARTx I/O Characteristics ........................................ 342
U
Unique Device Identifier (UDID).......................................... 31
Universal Asynchronous Receiver
Transmitter (UART)................................................... 223
Control Registers ...................................................... 225
Helpful Tips ............................................................... 224
Resources ................................................................. 224
Universal Asynchronous Receiver Transmitter. See UART.
User OTP Memory ............................................................ 285
DS70005127D-page 384
V
Voltage Regulator (On-Chip) ............................................ 285
W
Watchdog Timer (WDT)............................................ 277, 286
Programming Considerations ................................... 286
WWW Address ................................................................. 384
WWW, On-Line Support ..................................................... 10
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2013-2017 Microchip Technology Inc.
DS70005127D-page 385
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 386
2013-2017 Microchip Technology Inc.
dsPIC33EPXXGS50X FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 EP 64 GS5 04 T - I / PT XXX
Examples:
dsPIC33EP64GS504-I/PT:
dsPIC33, Enhanced Performance,
64-Kbyte Program Memory, SMPS,
44-Pin, Industrial Temperature,
TQFP Package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (Kbyte)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
= 16-Bit Digital Signal Controller
Flash Memory Family:
EP
= Enhanced Performance
Product Group:
GS = SMPS Family
Pin Count:
02
04
05
06
=
=
=
=
Temperature Range:
I
E
= -40C to +85C (Industrial)
= -40C to +125C (Extended)
Package:
2N
ML
MM
PT
PT
SO
Y8
=
=
=
=
=
=
=
28-pin
44-pin
48-pin
64-pin
Ultra Thin Quad Flat, No Lead – (28-pin) 6x6 mm (UQFN)
Plastic Quad Flat, No Lead – (44-pin) 8x8 mm body (QFN)
Plastic Quad Flat, No Lead – (28-pin) 6x6 mm body (QFN-S)
Plastic Thin Quad Flatpack – (44-pin) 10x10 mm body (TQFP)
Plastic Thin Quad Flatpack – (64-pin) 10x10 mm body (TQFP)
Plastic Small Outline, Wide – (28-pin) 7.50 mm body (SOIC)
Thin Quad Flatpack – (48-pin) 7x7 mm (TQFP)
2013-2017 Microchip Technology Inc.
DS70005127D-page 387
dsPIC33EPXXGS50X FAMILY
NOTES:
DS70005127D-page 388
2013-2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2013-2017 Microchip Technology Inc.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013-2017, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-1714-9
DS70005127D-page 389
Worldwide Sales and Service
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Technical Support:
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DS70005127D-page 390
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2013-2017 Microchip Technology Inc.
11/07/16
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