dsPIC33EVXXXGM00X/10X FAMILY
16-Bit, 5V Digital Signal Controllers with
PWM, SENT, Op Amps and Advanced Analog Features
Operating Conditions
PWM
• 4.5V to 5.5V, 0°C to +85°C, DC to 70 MIPS
• 4.5V to 5.5V, -40°C to +125°C, DC to 60 MIPS
• 4.5V to 5.5V, -40°C to +150°C, DC to 40 MIPS
• Up to Six Pulse-Width Modulation (PWM) Outputs
(three generators)
• Primary Master Time Base Inputs allow
Time Base Synchronization from Internal/External
Sources
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, inverters, Power Factor
Correction (PFC) and lighting
- Brushless Direct Current (BLDC), Permanent
Magnet Synchronous Motor (PMSM),
AC Induction Motor (ACIM), Switched
Reluctance Motor (SRM)
- Programmable Fault inputs
- Flexible trigger configurations for
Analog-to-Digital conversion
- Supports PWM lock, PWM output chopping
and dynamic phase shifting
Core: 16-Bit dsPIC33E CPU
•
•
•
•
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
16-Bit Wide Data Path
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle, Mixed-Sign MUL plus Hardware
Divide
32-Bit Multiply Support
Intermediate Security for Memory:
- Provides a Boot Flash Segment in addition to
the existing General Flash Segment
Error Code Correction (ECC) for Flash
Added Two Alternate Register Sets for Fast
Context Switching
Clock Management
Advanced Analog Features
•
•
•
•
•
•
• ADC module:
- Configurable as 10-bit, 1.1 Msps with
four S&H or 12-bit, 500 ksps with one S&H
- Up to 36 analog inputs
• Flexible and Independent ADC Trigger Sources
• Up to Four Op Amp/Comparators with Direct
Connection to the ADC module:
- Additional dedicated comparator and
7-bit Digital-to-Analog Converter (DAC)
- Two comparator voltage reference outputs
- Programmable references with 128 voltage
points
- Programmable blanking and filtering
• Charge Time Measurement Unit (CTMU):
- Supports mTouch® capacitive touch sensing
- Provides high-resolution time
measurement (1 ns)
- On-chip temperature measurement
- Temperature sensor diode
- Nine sources of edge input triggers (CTED1,
CTED2, OCPWM, TMR1, SYSCLK, OSCLK,
FRC, BFRC and LPRC)
Internal, 15% Low-Power RC (LPRC) – 32 kHz
Internal, 1% Fast RC (FRC) – 7.37 MHz
Internal, 10% Backup FRC (BFRC) – 7.37 MHz
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Additional FSCM Source (BFRC), Intended to
Provide a Clock Fail Switch Source for the
System Clock
• Independent Watchdog Timer (WDT)
• System Windowed Watchdog Timer (DMT)
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle
and Doze)
• Power Consumption Minimized Executing
NOP String
• Integrated Power-on Reset (POR) and Brown-out
Reset (BOR)
• 0.5 mA/MHz Dynamic Current (typical)
• 50 µA at +25°C IPD Current (typical)
2013-2019 Microchip Technology Inc.
DS70005144H-page 1
dsPIC33EVXXXGM00X/10X FAMILY
Timers/Output Compare/Input Capture
Input/Output
• Nine General Purpose Timers:
- Five 16-bit and up to two 32-bit timers/
counters; Timer3 can provide ADC trigger
• Four Output Compare modules Configurable as
Timers/Counters
• Four Input Capture modules
• GPIO Registers to Support Selectable
Slew Rate I/Os
• Peripheral Pin Select (PPS) to allow Function
Remap
• Sink/Source: 8 mA or 12 mA, Pin-Specific for
Standard VOH/VOL
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Change Notice Interrupts on All I/O Pins
Communication Interfaces
• Two Enhanced Addressable Universal
Asynchronous Receiver/Transmitter (UART)
modules (6.25 Mbps):
- With support for LIN/J2602 bus and IrDA®
- High and low speed (SCI)
• Two SPI modules (15 MHz):
- 25 MHz data rate without using PPS
• One I2C module (up to 1 Mbaud) with SMBus
Support
• Two SENT J2716 (Single-Edge Nibble
Transmission-Transmit/Receive) module for
Automotive Applications
• One CAN module:
- 32 buffers, 16 filters and 3 masks
Direct Memory Access (DMA)
• Four-Channel DMA with User-Selectable Priority
Arbitration
• UART, Serial Peripheral Interface (SPI), ADC,
Input Capture, Output Compare and Controller
Area Network (CAN)
DS70005144H-page 2
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
Compliant
• AEC-Q100 REVG (Grade 0: -40°C to +150°C)
Compliant
• Class B Safety Library, IEC 60730
Class B Fault Handling Support
• Backup FRC
• Windowed WDT uses LPRC
• Windowed Deadman Timer (DMT) uses System
Clock (System Windowed Watchdog Timer)
• H/W Clock Monitor Circuit
• Oscillator Frequency Monitoring through CTMU
(OSCI, SYSCLK, FRC, BFRC, LPRC)
• Dedicated PWM Fault Pin
• Lockable Clock Configuration
Debugger Development Support
• In-Circuit and In-Application Programming
• Three Complex and Five Simple Breakpoints
• Trace and Run-Time Watch
2013-2019 Microchip Technology Inc.
The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. The following pages show the devices’ pinout diagrams.
dsPIC33EV64GM104
dsPIC33EV128GM004
dsPIC33EV128GM104
dsPIC33EV256GM004
dsPIC33EV256GM104
4K
64K
8K
128K
8K
256K
16K
Pins
DS70005144H-page 3
dsPIC33EV64GM004
32K
External Interrupts
dsPIC33EV32GM104
16K
General Purpose I/O (GPIO)
dsPIC33EV32GM004
256K
Peripheral Pin Select (PPS)
dsPIC33EV256GM103
8K
Security
dsPIC33EV256GM003
128K
CTMU
dsPIC33EV128GM103
8K
Op Amp/Comparators
dsPIC33EV128GM003
64K
ADC Inputs
dsPIC33EV64GM103
4K
10/12-Bit ADC
dsPIC33EV64GM003
32K
SENT
dsPIC33EV32GM103
16K
I2C
dsPIC33EV32GM003
256K
SPI
dsPIC33EV256GM102
8K
UART
dsPIC33EV256GM002
128K
PWM
dsPIC33EV128GM102
8K
Output Compare
dsPIC33EV128GM002
64K
Input Capture
dsPIC33EV64GM102
4K
32-Bit Timers
dsPIC33EV64GM002
32K
16-Bit Timers (T1)
dsPIC33EV32GM102
4
5
2
4
4
3x2
2
2
1
2
1
11
3/4
1
Intermediate
Y
21
3
28
4
5
2
4
4
3x2
2
2
1
2
1
13
3/4
1
Intermediate
Y
25
3
36
4
5
2
4
4
3x2
2
2
1
2
1
24
4/5
1
Intermediate
Y
35
3
44, 48
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
dsPIC33EVXXXGM00X/10X FAMILY
dsPIC33EV32GM002
DMA Channels
Device
CAN
dsPIC33EVXXXGM00X/10X FAMILY DEVICES
SRAM Bytes
TABLE 1:
Program Memory Bytes
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X PRODUCT FAMILIES
dsPIC33EV128GM106
dsPIC33EV256GM006
dsPIC33EV256GM106
128K
8K
256K
16K
UART
SPI
I2C
SENT
10/12-Bit ADC
ADC Inputs
Op Amp/Comparators
CTMU
Security
Peripheral Pin Select (PPS)
General Purpose I/O (GPIO)
External Interrupts
Pins
CAN
PWM
8K
Output Compare
dsPIC33EV128GM006
64K
Input Capture
dsPIC33EV64GM106
4K
32-Bit Timers
dsPIC33EV64GM006
32K
16-Bit Timers (T1)
dsPIC33EV32GM106
DMA Channels
dsPIC33EV32GM006
SRAM Bytes
Device
Program Memory Bytes
dsPIC33EVXXXGM00X/10X FAMILY DEVICES (CONTINUED)
4
5
2
4
4
3x2
2
2
1
2
1
36
4/5
1
Intermediate
Y
53
3
64
0
1
0
1
0
1
0
1
dsPIC33EVXXXGM00X/10X FAMILY
DS70005144H-page 4
TABLE 1:
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1,2,3)
1
28
AVDD
2
27
AVSS
OA2IN+/AN1/C2IN1+/RPI17/RA1
3
26
RPI47/PWM1L/T5CK/RB15
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
4
25
RPI46/PWM1H/T3CK/RB14
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
5
24
RPI45/PWM2L/CTPLS/RB13
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
6
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
7
VSS
8
OSC1/CLKI/AN32/RPI18/RA2
9
dsPIC33EV32GM002/102
dsPIC33EV64GM002/102
dsPIC33EV128GM002/102
dsPIC33EV256GM002/102
MCLR
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
23
RPI44/PWM2H/RB12
22
RP43/PWM3L/RB11
21
RP42/PWM3H/RB10
20
VCAP
19
VSS
18
OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
12
17
AN26/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
13
16
OA5OUT/AN25/C5IN4-/C4IN1+/SCK1/RP39/INT0/RB7
14
15
PGEC2/SCL1/RP38/RB6
OSC2/CLKO/RPI19/RA3
10
FLT32/RP36/RB4
11
OA5IN+/AN24/C5IN3-/C5IN1+/RP20/T1CK/RA4
VDD
PGED2/SDA1/RP37/RB5
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
2013-2019 Microchip Technology Inc.
DS70005144H-page 5
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
28-Pin QFN-S(1,2,3,4)
28 27 26 25 24 23 22
PGED3/OA2IN-/AN2/C21N1-/SS1/RPI32/CTED2/RB0
1
21
RPI45/PWM2L/CTPLS/RB13
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
2
20
RPI44/PWM2H/RB12
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
3
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
4
VSS
5
dsPIC33EV 32GM002/102 19
dsPIC33EV 64GM002/102
dsPIC33EV 128GM002/102 18
dsPIC33EV256GM002/102 17
OSC1/CLKI/AN32/RPI18/RA2
6
16
VSS
OSC2/CLKO/RPI19/RA3
7
15
OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
VCAP
AN26/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
OA5OUT/AN25/C5IN4-/C4IN1+/SCK1/RP39/INT0/RB7
PGEC2/SCL1/RP38/RB6
PGED2/SDA1/RP37/RB5
VDD
FLT32/RP36/RB4
RP42/PWM3H/RB10
9 10 11 12 13 14
OA 5 IN+/AN24/C5IN3-/C5 IN1+/RP20/T1CK/RA4
8
RP43/PWM3L/RB11
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS70005144H-page 6
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AVSS
AVDD
MCLR
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
36-Pin UQFN(1,2,3,4)
36 35 34 33 32 31 30 29 28
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
1
27
RPI45/PWM2L/CTPLS/RB13
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RB3
2
26
RPI44/PWM2H/RB12
AN6/C3IN4-/C4IN4-/C4IN1+/RP48RC0
3
25
RP43/PWM3L/RB11
AN7/C3IN1-/C4IN1-/RP49/RC1
4
24
RP42/PWM3H/RB10
VDD
5
23
VDD
VSS
6
22
VCAP
OSC1/CLK1/AN32/RPI18/RA2
7
21
VSS
OSC2/CLKO/RPI19/RA3
8
20
RP56/RC8
RPI24/RA8
9
19
OA5IN-/AN27/C5IN1-/ASDA1/SDI1/RP41/RB9
dsPIC33EV32GM003/103
dsPIC33EV64GM003/103
dsPIC33EV128GM003/103
dsPIC33EV256GM003/103
AN26/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
OA5OUT/AN25/C5IN4-/SCK1/RP39/INT0/RB7
PGEC2/SCL1/RP38/RB6
PGED2/SDA1/RP37/RB5
VDD
VSS
VDD
FLT32/RP36/RB4
OA5IN+/AN24/C5IN3-/C5IN1+/RP20/T1CK/RA4
10 11 12 13 14 15 16 17 18
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports”
for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS
externally.
2013-2019 Microchip Technology Inc.
DS70005144H-page 7
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
PGEC2/SCL1/RP38/RB6
PGED2/SDA1/RP37/RB5
VDD
VSS
AN31/CVREF2O/RPI53/RC5
AN30/CVREF+/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
44
43
42
41
40
39
38
37
36
35
34
44-Pin TQFP(1,2,3)
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9
1
33
FLT32/RP36/RB4
AN53/RP54/RC6
2
32
RPI24/RA8
AN52/RP55/RC7
3
31
OSC2/CLKO/RPI19/RA3
AN51/RP56/RC8
4
30
OSC1/CLKI/AN32/RPI18/RA2
AN54/RP57/RC9
5
29
VSS
VSS
6
VCAP
7
RP42/PWM3H/RB10
RP43/PWM3L/RB11
dsPIC33EV32GM004/104
dsPIC33EV64GM004/104
dsPIC33EV128GM004/104
dsPIC33EV256GM004/104
18
19
20
21
22
MCLR
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
17
23
AVDD
11
16
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM2L/CTPLS/RB13
AVSS
24
15
10
RPI47/PWM1L/T5CK/RB15
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
RPI44/PWM2H/RB12
14
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
25
RPI46/PWM1H/T3CK/RB14
26
9
13
8
12
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN55/RA7
VDD
27
AN56/RA10
28
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
DS70005144H-page 8
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
AN28/SDI1/RPI25/RA9
AN29/SCK1/RPI51/RC3
AN31/CVREF2O/RPI53/RC5
AN30/CVREF+/RPI52/RC4
VSS
VDD
PGED2/SDA1/RP37/RB5
PGEC2/SCL1/RP38/RB6
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
44-Pin QFN(1,2,3,4)
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
Pin Diagrams (Continued)
44 43 42 41 40 39 38 37 36 35 34
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9
1
33
FLT32/RP36/RB4
AN53/RP54/RC6
2
32
RPI24/RA8
AN52/RP55/RC7
3
31
OSC2/CLKO/RPI19/RA3
AN51/RP56/RC8
4
30
OSC1/CLKI/AN32/RPI18/RA2
AN54/RP57/RC9
5
VSS
6
VCAP
7
dsPIC33EV32GM004/104
dsPIC33EV64GM004/104
dsPIC33EV128GM004/104
dsPIC33EV256GM004/104
29
VSS
28
VDD
27
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
RP42/PWM3H/RB10
8
26
RP43/PWM3L/RB11
9
25
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
RPI44/PWM2H/RB12
10
24
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM2L/CTPLS/RB13
11
23
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
MCLR
AVDD
AVSS
RPI47/PWM1L/T5CK/RB15
RPI46/PWM1H/T3CK/RB14
AN55/RA7
AN56/RA10
12 13 14 15 16 17 18 19 20 21 22
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2013-2019 Microchip Technology Inc.
DS70005144H-page 9
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
PGED2/SDA1/RP37/RB5
NC
VDD
VSS
AN31/CVREF2O/RPI53/RC5
AN30/CVREF+/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
43
42
41
40
39
38
37
PGEC2/SCL1/RP38/RB6
46
44
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
47
45
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
48
48-Pin TQFP(1,2,3)
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9
1
36
FLT32/RP36/RB4
AN53/RP54/RC6
2
35
RPI24/RA8
AN52/RP55/RC7
3
34
OSC2/CLKO/RPI19/RA3
AN51/RP56/RC8
4
33
OSC1/CLKI/AN32/RPI18/RA2
AN54/RP57/RC9
5
32
VSS
6
NC
VSS
VCAP
7
30
VDD
NC
8
29
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
RP42/PWM3H/RB10
9
28
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
RP43/PWM3L/RB11
10
27
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
RPI44/PWM2H/RB12
11
26
PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3
RPI45/PWM2L/CTPLS/RB13
12
25
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
21
22
23
24
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
20
NC
17
AVSS
19
16
RPI47/PWM1L/T5CK/RB15
18
15
RPI46/PWM1H/T3CK/RB14
AVDD
14
AN55/RA7
31
MCLR
13
AN56/RA10
dsPIC33EV32GM004/104
dsPIC33EV64GM004/104
dsPIC33EV128GM004/104
dsPIC33EV256GM004/104
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
DS70005144H-page 10
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AN56/RA10
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
RP97/RF1
RPI96/RF0
VDD
VCAP
AN54/RP57/RC9
RP70/RD6
RP69/RD5
AN51/RP56/RC8
AN52/RP55/RC7
AN53/RP54/RC6
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9
64-Pin TQFP(1,2,3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33EV32GM006/106
dsPIC33EV64GM006/106
dsPIC33EV128GM006/106
dsPIC33EV256GM006/106
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI61/RC13
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN48/CVREF2O/RPI58/RC10
PGEC2/SCL1/RP38/RB6
PGED2/SDA1/RP37/RB5
RPI72/RD8
VSS
OSC2/CLKO/RPI63/RC15
OSC1/CLKI/AN49/RPI60/RC12
VDD
AN31/RPI53/RC5
AN30/CVREF+/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RB3
AVDD
AVSS
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-/U1CTS/FLT4/RC11
VSS
VDD
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/RE12
AN13/C3IN2-/U2CTS/FLT6/RE13
AN14/RPI94/FLT7/RE14
AN15/RPI95/FLT8/RE15
RPI24/RA8
FLT32/RP36/RB4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AN55/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AN19/RP118/RG6
AN18/RPI119/RG7
AN17/RP120/RG8
MCLR
AN16/RPI121/RG9
VSS
VDD
AN10/RPI28/RA12
AN9/RPI27/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
2013-2019 Microchip Technology Inc.
DS70005144H-page 11
dsPIC33EVXXXGM00X/10X FAMILY
Pin Diagrams (Continued)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AN56/RA10
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
RP43/PWM3L/RB11
RP42/PWM3H/RB10
RP97/RF1
RPI96/RF0
VDD
VCAP
AN54/ RP57/RC9
RP70/RD6
RP69/RD5
AN51/RP56/RC8
AN52/RP55/RC7
AN53/RP54/RC6
OA5IN-/AN27/C5IN1-/ASDA1/RP41/RB9
64-Pin QFN(1,2,3,4)
dsPIC33EV32GM006/106
dsPIC33EV64GM006/106
dsPIC33EV128GM006/106
dsPIC33EV256GM006/106
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AN26/CVREF1O/ASCL1/RP40/T4CK/RB8
RPI61/RC13
OA5OUT/AN25/C5IN4-/RP39/INT0/RB7
AN48/CVREF2O/RPI58/RC10
PGEC2/SCL1/RP38/RB6
PGED2/SDA1/RP37/RB5
RPI72/RD8
VSS
OSC2/CLKO/RPI63/RC15
OSC1/CLKI/AN49/RPI60/RC12
VDD
AN31/RPI53/RC5
AN30/CVREF+/RPI52/RC4
AN29/SCK1/RPI51/RC3
AN28/SDI1/RPI25/RA9
OA5 IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4
PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2
PGED1/OA1IN-/AN5/C1IN1-/(CTMUC)/RP35/RB3
AVDD
AVSS
OA3OUT/AN6/C3IN4-/C4IN4-/C4IN1+/RP48/RC0
OA3IN-/AN7/C3IN1-/C4IN1-/RP49/RC1
OA3IN+/AN8/C3IN3-/C3IN1+/RPI50/U1RTS/BCLK1/FLT3/RC2
AN11/C1IN2-/U1CTS/FLT4/RC11
VSS
VDD
AN12/C2IN2-/C5IN2-/U2RTS/BCLK2/FLT5/RE12
AN13/C3IN2-/U2CTS/FLT6/RE13
AN14/RPI94/FLT7/RE14
AN15/RPI95/FLT8/RE15
RPI24/RA8
FLT32/RP36/RB4
AN55/RA7
RPI46/PWM1H/T3CK/RB14
RPI47/PWM1L/T5CK/RB15
AN19/RP118/RG6
AN18/RPI119/RG7
AN17/RP120/RG8
MCLR
AN16/RPI121/RG9
VSS
VDD
AN10/RPI28/RA12
AN9/RPI27/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
OA2IN+/AN1/C2IN1+/RPI17/RA1
PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.5 “Peripheral
Pin Select (PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
3: If the op amp is selected when OPAEN (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is
used.
4: The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS70005144H-page 12
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 21
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization ................................................................................................................................................................. 35
5.0 Flash Program Memory.............................................................................................................................................................. 87
6.0 Resets ....................................................................................................................................................................................... 95
7.0 Interrupt Controller ..................................................................................................................................................................... 99
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 113
9.0 Oscillator Configuration ............................................................................................................................................................ 127
10.0 Power-Saving Features............................................................................................................................................................ 137
11.0 I/O Ports ................................................................................................................................................................................... 147
12.0 Timer1 ...................................................................................................................................................................................... 177
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 179
14.0 Deadman Timer (DMT) ............................................................................................................................................................ 185
15.0 Input Capture............................................................................................................................................................................ 193
16.0 Output Compare....................................................................................................................................................................... 197
17.0 High-Speed PWM Module ....................................................................................................................................................... 203
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 225
19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 233
20.0 Single-Edge Nibble Transmission (SENT) ............................................................................................................................... 241
21.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 251
22.0 Controller Area Network (CAN) Module (dsPIC33EVXXXGM10X Devices Only).................................................................... 257
23.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 283
24.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 289
25.0 Op Amp/Comparator Module ................................................................................................................................................... 305
26.0 Comparator Voltage Reference................................................................................................................................................ 317
27.0 Special Features ...................................................................................................................................................................... 321
28.0 Instruction Set Summary .......................................................................................................................................................... 331
29.0 Development Support............................................................................................................................................................... 341
30.0 Electrical Characteristics .......................................................................................................................................................... 343
31.0 High-Temperature Electrical Characteristics............................................................................................................................ 405
32.0 Characteristics for Industrial/Extended Temperature Devices (-40°C to +125°C) ................................................................... 415
33.0 Characteristics for High-Temperature Devices (+150°C) ......................................................................................................... 441
34.0 Packaging Information.............................................................................................................................................................. 463
Appendix A: Revision History............................................................................................................................................................. 493
Index ................................................................................................................................................................................................. 495
The Microchip Website ...................................................................................................................................................................... 501
Customer Change Notification Service .............................................................................................................................................. 501
Customer Support .............................................................................................................................................................................. 501
Product Identification System ............................................................................................................................................................ 503
2013-2019 Microchip Technology Inc.
DS70005144H-page 13
dsPIC33EVXXXGM00X/10X FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our website at www.microchip.com to receive the most current information on all of our products.
DS70005144H-page 14
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”, which are available from the
Microchip website (www.microchip.com). The following
documents should be considered as the general
reference for the operation of a particular module or
device feature:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“Introduction” (www.microchip.com/DS70573)
“CPU” (www.microchip.com/DS70359)
“Data Memory” (www.microchip.com/DS70595)
“dsPIC33/PIC24 Program Memory” (www.microchip.com/DS70000613)
“Flash Programming” (www.microchip.com/DS70000609)
“Interrupts” (www.microchip.com/DS70000600)
“Oscillator” (www.microchip.com/DS70580)
“Reset” (www.microchip.com/DS70602)
“Watchdog Timer and Power-Saving Modes” (www.microchip.com/DS70615)
“I/O Ports” (www.microchip.com/DS70000598)
“Timers” (www.microchip.com/DS70362)
“CodeGuard™ Intermediate Security” (www.microchip.com/DS70005182)
“Deadman Timer” (www.microchip.com/DS70005155)
“Input Capture with Dedicated Timer” (www.microchip.com/DS70000352)
“Output Compare with Dedicated Timer” (www.microchip.com/DS70005159)
“High-Speed PWM” (www.microchip.com/DS70645)
“Analog-to-Digital Converter (ADC)” (www.microchip.com/DS70621)
“Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582)
“Serial Peripheral Interface (SPI)” (www.microchip.com/DS70005185)
“Inter-Integrated Circuit (I2C)” (www.microchip.com/DS70000195)
“Enhanced Controller Area Network (ECAN™)” (www.microchip.com/DS70353)
“Direct Memory Access (DMA)” (www.microchip.com/DS70348)
“Programming and Diagnostics” (www.microchip.com/DS70608)
“Op Amp/Comparator” (www.microchip.com/DS70000357)
“Device Configuration” (www.microchip.com/DS70000618)
“Charge Time Measurement Unit (CTMU) and CTMU Operation with Threshold Detect”
(www.microchip.com/DS30009743)
• “Single-Edge Nibble Transmission (SENT) Module” (www.microchip.com/DS70005145)
2013-2019 Microchip Technology Inc.
DS70005144H-page 15
dsPIC33EVXXXGM00X/10X FAMILY
NOTES:
DS70005144H-page 16
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the dsPIC33EVXXXGM00X/10X family Digital Signal
Controller (DSC) devices.
Note 1: This data sheet summarizes the features
of the dsPIC33EVXXXGM00X/10X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
website (www.microchip.com).
dsPIC33EVXXXGM00X/10X family devices contain
extensive Digital Signal Processor (DSP) functionality
with a high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 1-1:
dsPIC33EVXXXGM00X/10X FAMILY BLOCK DIAGRAM
PORTA
CPU
16
Refer to Figure 3-1 for CPU diagram details.
PORTB
PORTC
Power-up
Timer
OSC1/CLKI
Timing
Generation
MCLR
VDD, VSS
AVDD, AVSS
SENT1/2
CAN1(1)
ADC
Oscillator
Start-up
Timer
PORTD
POR/BOR
PORTE
Watchdog
Timer/
Deadman
Timer
Input
Capture
Output
Compare
16
PORTF
I2C1
PORTG
Remappable
Pins
CTMU
PWM
Timers
Op Amp/
Comparator
SPI1/2
UART1/2
PORTS
Peripheral Modules
Note 1:
This feature or peripheral is only available on dsPIC33EVXXXGM10X devices.
2013-2019 Microchip Technology Inc.
DS70005144H-page 17
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin Buffer
PPS
Type Type
Description
AN0-AN19
AN24-AN32
AN48, AN49
AN51-AN56
I
Analog
No
Analog input channels.
CLKI
I
No
CLKO
O
ST/
CMOS
—
External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
No
OSC2
I/O
ST/
CMOS
—
REFCLKO
O
—
Yes Reference clock output.
IC1-IC4
I
ST
Yes Capture Inputs 1 to 4.
OCFA
OC1-OC4
I
O
ST
—
Yes Compare Fault A input (for compare channels).
Yes Compare Outputs 1 to 4.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No External Interrupt 0.
Yes External Interrupt 1.
Yes External Interrupt 2.
No
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
RA0-RA4, RA7-RA12
I/O
ST
Yes PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
Yes PORTB is a bidirectional I/O port.
RC0-RC13, RC15
I/O
ST
Yes PORTC is a bidirectional I/O port.
RD5-RD6, RD8
I/O
ST
Yes PORTD is a bidirectional I/O port.
RE12-RE15
I/O
ST
Yes PORTE is a bidirectional I/O port.
RF0-RF1
I/O
ST
No
RG6-RG9
PORTF is a bidirectional I/O port.
I/O
ST
Yes PORTG is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
No
Yes
No
No
No
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
CTPLS
CTED1
CTED2
O
I
I
ST
ST
ST
No
No
No
CTMU pulse output.
CTMU External Edge Input 1.
CTMU External Edge Input 2.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
UART1 transmit.
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART2 Clear-to-Send.
UART2 Ready-to-Send.
UART2 receive.
UART2 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
No
No
No
No
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
DS70005144H-page 18
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Buffer
PPS
Type Type
Description
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
C1RX
C1TX
I
O
ST
—
Yes CAN1 bus receive pin.
Yes CAN1 bus transmit pin.
SENT1TX
SENT1RX
SENT2TX
SENT2RX
O
I
O
I
—
—
—
—
Yes
Yes
Yes
Yes
SENT1 transmit pin.
SENT1 receive pin.
SENT2 transmit pin.
SENT2 receive pin.
CVREF
O
Analog
No
Comparator Voltage Reference output.
C1IN1+, C1IN2-,
C1IN1-, C1IN3C1OUT
I
Analog
No
Comparator 1 inputs.
O
—
I
Analog
O
—
I
Analog
O
—
I
Analog
O
—
C2IN1+, C2IN2-,
C2IN1-, C2IN3C2OUT
C3IN1+, C3IN2-,
C2IN1-, C3IN3C3OUT
C4IN1+, C4IN2-,
C4IN1-, C4IN3C4OUT
Yes Comparator 1 output.
No
Comparator 2 inputs.
Yes Comparator 2 output.
No
Comparator 3 inputs.
Yes Comparator 3 output.
No
Comparator 4 inputs.
Yes Comparator 4 output.
C5IN1+, C5IN2-,
C5IN1-, C5IN3C5OUT
I
Analog
No
Comparator 5 inputs.
O
—
Yes Comparator 5 output.
FLT1-FLT2
FLT3-FLT8
FLT32
DTCMP1-DTCMP3
PWM1L-PWM3L
PWM1H-PWM3H
SYNCI1
SYNCO1
I
I
I
I
O
O
I
O
ST
ST
ST
ST
—
—
ST
—
Yes
NO
NO
Yes
No
No
Yes
Yes
PWM Fault Inputs 1 and 2.
PWM Fault Inputs 3 to 8.
PWM Fault Input 32.
PWM Dead-Time Compensation Inputs 1 to 3.
PWM Low Outputs 1 to 3.
PWM High Outputs 1 to 3.
PWM Synchronization Input 1.
PWM Synchronization Output 1.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
2013-2019 Microchip Technology Inc.
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
DS70005144H-page 19
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Buffer
PPS
Type Type
Description
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all
times.
AVSS
P
P
No
Ground reference for analog modules.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
DS70005144H-page 20
Analog = Analog input
O = Output
TTL = TTL input buffer
P = Power
I = Input
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33EVXXXGM00X/10X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33EVXXXGM00X/10X
family of 16-bit microcontrollers (MCUs) requires
attention to a minimal set of device pin connections
before proceeding with development. The following is a
list of pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Note:
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10V-20V is recommended. This
capacitor should be a Low Equivalent Series
Resistance (low-ESR), and have resonance
frequency in the range of 20 MHz and higher. It is
recommended to use ceramic capacitors.
• Placement on the Printed Circuit Board (PCB):
The decoupling capacitors should be placed as
close to the pins as possible. It is recommended
to place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, above tens of
MHz, add a second ceramic-type capacitor in
parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing the PCB track
inductance.
The AVDD and AVSS pins must be
connected, regardless of the ADC voltage
reference source.
2013-2019 Microchip Technology Inc.
DS70005144H-page 21
dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
MCLR
dsPIC33EV
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
provides
two
specific
device
For example, as shown in Figure 2-1, it is
recommended that the capacitor, C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components as shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that
connects the power supply source to the device, and
the maximum current drawn by the device in the application. In other words, select the tank capacitor so that
it meets the acceptable voltage sag at the device.
Typical values range from 4.7 µF to 47 µF.
2.3
pin
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
(i.e., ADC Conversion Rate/2)
2
1
L = ----------------------
2f C
2.2.1
Master Clear (MCLR) Pin
• Device Reset
• Device Programming and Debugging
C
0.1 µF
Ceramic
2.4
The MCLR
functions:
VSS
VDD
R
R1
0.1 µF
Ceramic
VCAP
10 µF
Tantalum
VDD
The placement of this capacitor should be close to the
VCAP pin. It is recommended that the trace length
should not exceed one-quarter inch (6 mm).
CPU Logic Filter Capacitor
Connection (VCAP)
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R(1)
R1(2)
JP
MCLR
dsPIC33EV
C
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R1 470 will limit any current flow into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown due to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR ( VIN-
Note 1:
2:
Reflects the value of the of the CEVT bit in the respective Op Amp/Comparator Control register,
CMxCON[9].
Reflects the value of the COUT bit in the respective Op Amp/Comparator Control register, CMxCON[8].
2013-2019 Microchip Technology Inc.
DS70005144H-page 307
dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 25-2:
CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2, 3 OR 5)
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R-0
CON
COE
CPOL
—
—
OPAEN(2)
CEVT
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EVPOL1(3)
EVPOL0(3)
—
CREF(1)
—
—
CCH1(1)
CCH0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CON: Op Amp/Comparator x Enable bit
1 = Op Amp/Comparator x is enabled
0 = Op Amp/Comparator x is disabled
bit 14
COE: Comparator x Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator x Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-11
Unimplemented: Read as ‘0’
bit 10
OPAEN: Op Amp x Enable bit(2)
1 = Op Amp x is enabled
0 = Op Amp x is disabled
bit 9
CEVT: Comparator x Event bit
1 = Comparator event, according to EVPOL[1:0] settings, occurred; disables future triggers and interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8
COUT: Comparator x Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1 (inverted polarity):
1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1:
2:
3:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
The op amp and the comparator can be used simultaneously in these devices. The OPAEN bit only
enables the op amp while the comparator is still functional.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL[1:0] (CMxCON[7:6]) = 10 or 01), the Comparator x Event bit, CEVT (CMxCON[9]), and the
Comparator Interrupt Flag, CMPIF (IFS1[2]), must be cleared before enabling the Comparator Interrupt
Enable bit, CMPIE (IEC1[2]).
DS70005144H-page 308
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dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 25-2:
CMxCON: COMPARATOR x CONTROL REGISTER (x = 1, 2, 3 OR 5) (CONTINUED)
bit 7-6
EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits(3)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator x Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to the internal CVREFIN voltage
0 = VIN+ input connects to the CxIN1+ pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH[1:0]: Op Amp/Comparator x Channel Select bits(1)
11 = Inverting input of op amp/comparator connects to the CxIN4- pin
10 = Inverting input of op amp/comparator connects to the CxIN3- pin
01 = Inverting input of op amp/comparator connects to the CxIN2- pin
00 = Inverting input of op amp/comparator connects to the CxIN1- pin
Note 1:
2:
3:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
The op amp and the comparator can be used simultaneously in these devices. The OPAEN bit only
enables the op amp while the comparator is still functional.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL[1:0] (CMxCON[7:6]) = 10 or 01), the Comparator x Event bit, CEVT (CMxCON[9]), and the
Comparator Interrupt Flag, CMPIF (IFS1[2]), must be cleared before enabling the Comparator Interrupt
Enable bit, CMPIE (IEC1[2]).
2013-2019 Microchip Technology Inc.
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dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 25-3:
CM4CON: COMPARATOR 4 CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R-0
CON
COE
CPOL
—
—
—
CEVT
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EVPOL1(2)
EVPOL0(2)
—
CREF(1)
—
—
CCH1(1)
CCH0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CON: Op Amp/Comparator 4 Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14
COE: Comparator 4 Output Enable bit
1 = Comparator output is present on the C4OUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator 4 Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-10
Unimplemented: Read as ‘0’
bit 9
CEVT: Comparator 4 Event bit
1 = Comparator event, according to EVPOL[1:0] settings, occurred; disables future triggers and interrupts
until the bit is cleared
0 = Comparator event did not occur
bit 8
COUT: Comparator 4 Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1 (inverted polarity):
1 = VIN+ < VIN0 = VIN+ > VIN-
Note 1:
2:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL[1:0] (CMxCON[7:6]) = 10 or 01), the comparator Event bit, CEVT (CMxCON[9]), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1[2]), must be cleared before enabling the Comparator
Interrupt Enable bit, CMPIE (IEC1[2]).
DS70005144H-page 310
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 25-3:
CM4CON: COMPARATOR 4 CONTROL REGISTER (CONTINUED)
bit 7-6
EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits(2)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
bit 4
CREF: Comparator 4 Reference Select bit (VIN+ input)(1)
1 = VIN+ input connects to the internal CVREFIN voltage
0 = VIN+ input connects to the C4IN1+ pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH[1:0]: Comparator 4 Channel Select bits(1)
11 = VIN- input of comparator connects to the C4IN4- pin
10 = VIN- input of comparator connects to the C4IN3- pin
01 = VIN- input of comparator connects to the C4IN2- pin
00 = VIN- input of comparator connects to the C4IN1- pin
Note 1:
2:
Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL[1:0] (CMxCON[7:6]) = 10 or 01), the comparator Event bit, CEVT (CMxCON[9]), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1[2]), must be cleared before enabling the Comparator
Interrupt Enable bit, CMPIE (IEC1[2]).
2013-2019 Microchip Technology Inc.
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REGISTER 25-4:
CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT
CONTROL REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
RW-0
—
—
—
—
SELSRCC3
SELSRCC2
SELSRCC1
SELSRCC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SELSRCB3
SELSRCB2
SELSRCB1
SELSRCB0
SELSRCA3
SELSRCA2
SELSRCA1
SELSRCA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
SELSRCC[3:0]: Mask C Input Select bits
1111 = FLT4
1110 = FLT2
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
bit 7-4
SELSRCB[3:0]: Mask B Input Select bits
1111 = FLT4
1110 = FLT2
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
DS70005144H-page 312
x = Bit is unknown
2013-2019 Microchip Technology Inc.
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REGISTER 25-4:
bit 3-0
CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT
CONTROL REGISTER (CONTINUED)
SELSRCA[3:0]: Mask A Input Select bits
1111 = FLT4
1110 = FLT2
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM3H
0100 = PWM3L
0011 = PWM2H
0010 = PWM2L
0001 = PWM1H
0000 = PWM1L
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REGISTER 25-5:
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
OANEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HLMS: High or Low-Level Masking Select bit
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14
Unimplemented: Read as ‘0’
bit 13
OCEN: OR Gate C Input Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
bit 12
OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
bit 11
OBEN: OR Gate B Input Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
bit 10
OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
bit 9
OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
bit 8
OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
bit 7
NAGS: AND Gate Output Inverted Enable bit
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
bit 6
PAGS: AND Gate Output Enable bit
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
bit 5
ACEN: AND Gate C Input Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
bit 4
ACNEN: AND Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate
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REGISTER 25-5:
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER (CONTINUED)
bit 3
ABEN: AND Gate B Input Enable bit
1 = MBI is connected to AND gate
0 = MBI is not connected to AND gate
bit 2
ABNEN: AND Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate
0 = Inverted MBI is not connected to AND gate
bit 1
AAEN: AND Gate A Input Enable bit
1 = MAI is connected to AND gate
0 = MAI is not connected to AND gate
bit 0
AANEN: AND Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate
0 = Inverted MAI is not connected to AND gate
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REGISTER 25-6:
CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
CFSEL[2:0]: Comparator x Filter Input Clock Select bits
111 = T5CLK(1)
110 = T4CLK(2)
101 = T3CLK(1)
100 = T2CLK(2)
011 = Reserved
010 = SYNCO1(3)
001 = FOSC(4)
000 = FP(4)
bit 3
CFLTREN: Comparator x Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0
CFDIV[2:0]: Comparator x Filter Clock Divide Select bits
111 = Clock divide 1:128
110 = Clock divide 1:64
101 = Clock divide 1:32
100 = Clock divide 1:16
011 = Clock divide 1:8
010 = Clock divide 1:4
001 = Clock divide 1:2
000 = Clock divide 1:1
Note 1:
2:
3:
4:
x = Bit is unknown
See the Type C Timer Block Diagram (Figure 13-2).
See the Type B Timer Block Diagram (Figure 13-1).
See the High-Speed PWMx Module Register Interconnection Diagram (Figure 17-2).
See the Oscillator System Diagram (Figure 9-1).
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26.0
COMPARATOR VOLTAGE
REFERENCE
Note 1: This data sheet summarizes the features
of the dsPIC33EVXXXGM00X/10X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Op Amp/Comparator”
(www.microchip.com/DS70000357) in the
“dsPIC33/PIC24 Family Reference
Manual”.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2013-2019 Microchip Technology Inc.
26.1
Configuring the Comparator
Voltage Reference
The comparator voltage reference module is controlled
through the CVRxCON registers (Register 26-1 and
Register 26-2). The comparator voltage reference
provides a range of output voltages with 128 distinct
levels. The comparator reference supply voltage can
come from either VDD and VSS, or the external CVREF+
and AVSS pins. The voltage source is selected by the
CVRSS bit (CVRxCON[11]). The settling time of the
comparator voltage reference must be considered
when changing the CVREF output.
DS70005144H-page 317
dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 26-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREFSEL
(CVR1CON[10])
AVDD
CVRSS = 1
(CVR1CON[11])
CVRSRC
CVRSS = 0
(CVR1CON[11])
1
CVR1CON[6:0]
CVREFIN
CVR6
CVR5
CVR4
CVR3
CVR2
CVR1
CVR0
CVREF+
CVREN
(CVR1CON[15])
0
R
R
R
128 Steps
R
128-to-1 MUX
R
R
CVREF1O
CVROE
(CVR1CON[14])
VREFSEL
(CVR2CON[10])
R
0
AVSS
AVDD
CVRSS = 1
(CVR2CON[11])
CVRSRC
CVR2CON[6:0]
CVRSS = 0
(CVR2CON[11])
CVREN
(CVR2CON[15])
CVR6
CVR5
CVR4
CVR3
CVR2
CVR1
CVR0
CVREF+
1
R
R
R
128 Steps
R
R
128-to-1 MUX
R
CVREF2O
CVROE
(CVR2CON[14])
R
AVSS
Note 1: CVREF2O and CVROE (CVR2CON[14]) are not available on the 28-pin and 36-pin devices.
2: Set the respective TRISx bit to ‘1’ to get the CVREF1O/CVREF2O output voltage on the pins.
3: CVREF+ is not available on the 28-pin or 36-pin package devices.
DS70005144H-page 318
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
26.2
Comparator Voltage Reference Registers
REGISTER 26-1:
CVR1CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 1
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
CVREN
CVROE
—
—
CVRSS
VREFSEL
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CVR6
CVR5
CVR4
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 14
CVROE: Comparator Voltage Reference Output Enable (CVREF1O Pin) bit
1 = Voltage level is output on the CVREF1O pin
0 = Voltage level is disconnected from the CVREF1O pin
bit 13-12
Unimplemented: Read as ‘0’
bit 11
CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator reference source, CVRSRC = CVREF+ – AVSS
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 10
VREFSEL: Voltage Reference Select bit
1 = CVREFIN = CVREF+
0 = CVREFIN is generated by the resistor network
bit 9-7
Unimplemented: Read as ‘0’
bit 6-0
CVR[6:0]: Comparator Voltage Reference Value Selection bits
1111111 = 127/128 x VREF input voltage
•
•
•
0000000 = 0.0 volts
2013-2019 Microchip Technology Inc.
DS70005144H-page 319
dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 26-2:
CVR2CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 2
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
U-0
U-0
CVREN
CVROE(1)
—
—
CVRSS
VREFSEL
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CVR6
CVR5
CVR4
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 14
CVROE: Comparator Voltage Reference Output Enable (CVREF2O Pin) bit(1)
1 = Voltage level is output on the CVREF2O pin
0 = Voltage level is disconnected from the CVREF2O pin
bit 13-12
Unimplemented: Read as ‘0’
bit 11
CVRSS: Comparator Voltage Reference Source Selection bit
1 = Comparator reference source, CVRSRC = CVREF+ – AVSS
0 = Comparator reference source, CVRSRC = AVDD – AVSS
bit 10
VREFSEL: Voltage Reference Select bit
1 = Comparator Reference Source 2 (CVR2) provides inverting input voltage when VREFSEL
(CVR1CON[10]) = 0
0 = Comparator Reference Source 1 (CVR1) provides inverting input voltage when VREFSEL
(CVR1CON[10]) = 0
bit 9-7
Unimplemented: Read as ‘0’
bit 6-0
CVR[6:0]: Comparator Voltage Reference Value Selection bits
1111111 = 127/128 x VREF input voltage
•
•
•
0000000 = 0.0 volts
Note 1:
CVROE (CVR2CON[14]) is not available on the 28-pin and 36-pin devices.
DS70005144H-page 320
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
27.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of
the dsPIC33EVXXXGM00X/10X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com).
The dsPIC33EVXXXGM00X/10X family devices
include several features intended to maximize
application flexibility and reliability, and minimize cost
through elimination of external components. These are:
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection and CodeGuard™ Security
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
27.1
Configuration Bits
In dsPIC33EVXXXGM00X/10X family devices, the
Configuration bytes are implemented as volatile
memory. This means that configuration data must be
programmed each time the device is powered up.
Configuration data are stored at the top of the on-chip
program memory space, known as the Flash Configuration bytes. Their specific locations are shown in
Table 27-1. The configuration data are automatically
loaded from the Flash Configuration bytes to the proper
Configuration Shadow registers during device Resets.
Note:
Configuration data are reloaded on all
types of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration bytes for configuration data in their
code for the compiler. This is to ensure that program
code is not stored in this address when the code is
compiled.
The upper two bytes of all Flash Configuration
Words in program memory should always be
‘1111 1111 1111 1111’. This makes them appear to
be NOP instructions in the remote event that their
locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding
locations, writing ‘1’s to these locations has no effect on
device operation.
Note:
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration bytes, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
The Configuration Flash bytes map is shown in
Table 27-1.
2013-2019 Microchip Technology Inc.
DS70005144H-page 321
File Name
FSEC
FBSLIM
Reserved
FOSCSEL
FOSC
FWDT
2013-2019 Microchip Technology Inc.
FPOR
FICD
CONFIGURATION WORD REGISTER MAP
Address
005780
Device
Memory Bits
Size
23-16
(Kbytes)
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSS0
CWRP
GSS1
GSS0
GWRP
—
BSEN
BSS1
BSS0
BWRP
32
00AB80
64
015780
128
02AB80
256
005790
32
00AB90
64
015790
128
02AB90
256
005794
32
00AB94
64
015794
128
02AB94
256
005798
32
00AB98
64
015798
128
02AB98
256
00579C
32
00AB9C
64
01579C
128
02AB9C
256
0057A0
32
00ABA0
64
0157A0
128
02ABA0
256
0057A4
32
00ABA4
64
0157A4
128
02ABA4
256
0057A8
32
00ABA8
64
0157A8
128
02ABA8
256
—
AIVTDIS
—
—
—
—
—
—
—
Reserved(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IESO
—
—
—
—
FNOSC2
FNOSC1
FNOSC0
—
—
—
—
—
—
—
—
PLLKEN
FCKSM1
FCKSM0
IOL1WAY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved(2)
—
—
—
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved and must be programmed as ‘0’.
2: This bit is reserved and must be programmed as ‘1’.
—
CSS2 CSS1
BSLIM[12:0]
WDTWIN1 WDTWIN0
WINDIS
FWDTEN1 FWDTEN0 WDTPRE WDTPS3
OSCIOFNC POSCMD1 POSCMD0
WDTPS2
WDTPS1
WDTPS0
—
—
—
BOREN
—
—
ICS1
ICS0
dsPIC33EVXXXGM00X/10X FAMILY
DS70005144H-page 322
TABLE 27-1:
2013-2019 Microchip Technology Inc.
TABLE 27-1:
File Name
FDMTINTVL
FDMTINTVH
FDMTCNTL
FDMT
FDEVOPT
FALTREG
Address
0057AC
Device
Memory Bits
Size
23-16
(Kbytes)
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
DMTEN
—
PWMLOCK
32
00ABAC
64
0157AC
128
02ABAC
256
0057B0
32
00ABB0
64
0157B0
128
02ABB0
256
0057B4
32
00ABB4
64
0157B4
128
02ABB4
256
0057B8
32
00AB8
64
0157B8
128
02ABB8
256
0057BC
32
00ABBC
64
0157BC
128
02ABBC
256
0057C0
32
00ABC0
64
0157C0
128
02ABC0
256
0057C4
32
DS70005144H-page 323
00ABC4
64
0157C4
128
02ABC4
256
—
DMTIVT[15:0]
—
DMTIVT[31:16]
—
DMTCNT[15:0]
—
DMTCNT[31:16]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘1’.
Note 1: This bit is reserved and must be programmed as ‘0’.
2: This bit is reserved and must be programmed as ‘1’.
CTXT2[2:0]
ALTI2C1 Reserved(2)
—
CTXT1[2:0]
dsPIC33EVXXXGM00X/10X FAMILY
FDMTCNTH
CONFIGURATION WORD REGISTER MAP (CONTINUED)
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 27-2:
dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
BWRP
FSEC
Boot Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
BSS[1:0]
FSEC
Boot Segment Code Flash Protection Level bits
11 = No protection (other than BWRP write protection)
10 = Standard security
0x = High security
BSEN
FSEC
Boot Segment Control bit
1 = No Boot Segment
0 = Boot Segment size is determined by BSLIM[12:0]
GWRP
FSEC
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
GSS[1:0]
FSEC
General Segment Code Flash Protection Level bits
11 = No protection (other than GWRP write protection)
10 = Standard security
0x = High security
CWRP
FSEC
Configuration Segment Write-Protect bit
1 = Configuration Segment is not write-protected
0 = Configuration Segment is write-protected
CSS[2:0]
FSEC
Configuration Segment Code Flash Protection Level bits
111 = No protection (other than CWRP write protection)
110 = Standard security
10x = Enhanced security
0xx = High security
AIVTDIS
FSEC
Alternate Interrupt Vector Table Disable bit
1 = Disables AIVT
0 = Enables AIVT
BSLIM[12:0]
FBSLIM
FNOSC[2:0]
FOSCSEL
Initial Oscillator Source Selection bits
111 = Internal Fast RC (FRC) Oscillator with Postscaler
110 = Internal Fast RC (FRC) Oscillator with Divide-by-16
101 = LPRC Oscillator
100 = Reserved
011 = Primary (XT, HS, EC) Oscillator with PLL
010 = Primary (XT, HS, EC) Oscillator
001 = Internal Fast RC (FRC) Oscillator with PLL
000 = FRC Oscillator
IESO
FOSCSEL
Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the
user-selected oscillator source when ready
0 = Starts up device with user-selected oscillator source
POSCMD[1:0]
DS70005144H-page 324
FOSC
Boot Segment Code Flash Page Address Limit bits
Contains the page address of the first active General Segment page. The
value to be programmed is the inverted page address, such that
programming additional ‘0’s can only increase the Boot Segment size.
For example, 0x1FFD = 2 pages or 1024 instruction words.
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 27-2:
Bit Field
dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION (CONTINUED)
Register
Description
OSCIOFNC
FOSC
OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is the general purpose digital I/O pin
IOL1WAY
FOSC
Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
FCKSM[1:0]
FOSC
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
PLLKEN
FOSC
PLL Lock Wait Enable bit
1 = Clock switches to the PLL source; will wait until the PLL lock signal is valid
0 = Clock switch will not wait for PLL lock
WDTPS[3:0]
FWDT
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
WDTPRE
FWDT
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
FWDTEN[1:0]
FWDT
Watchdog Timer Enable bits
11 = WDT is enabled in hardware
10 = WDT is controlled through the SWDTEN bit
01 = WDT is enabled only while device is active and disabled in Sleep; the
SWDTEN bit is disabled
00 = WDT and the SWDTEN bit are disabled
WINDIS
FWDT
Watchdog Timer Window Enable bit
1 = Watchdog Timer is in Non-Window mode
0 = Watchdog Timer is in Window mode
WDTWIN[1:0]
FWDT
Watchdog Timer Window Select bits
11 = WDT window is 25% of WDT period
10 = WDT window is 37.5% of WDT period
01 = WDT window is 50% of WDT period
00 = WDT window is 75% of WDT period
BOREN
FPOR
Brown-out Reset (BOR) Detection Enable bit
1 = BOR is enabled
0 = BOR is disabled
ICS[1:0]
FICD
ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1
10 = Communicates on PGEC2 and PGED2
01 = Communicates on PGEC3 and PGED3
00 = Reserved, do not use
DMTIVT[15:0]
FDMTINTVL
DMTIVT[31:16]
FDMTINTVH
Upper 16 Bits of 32-Bit Field that Configures the DMT Window Interval bits
DMTCNT[15:0]
FDMTCNTL
Lower 16 Bits of 32-Bit Field that Configures the DMT Instruction Count
Time-out Value bits
2013-2019 Microchip Technology Inc.
Lower 16 Bits of 32-Bit Field that Configures the DMT Window Interval bits
DS70005144H-page 325
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 27-2:
dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
DMTCNT[31:16]
DMTEN
Register
FDMCNTH
Description
Upper 16 Bits of 32-Bit Field that Configures the DMT Instruction Count
Time-out Value bits
FDMT
Deadman Timer Enable bit
1 = Deadman Timer is enabled and cannot be disabled by software
0 = Deadman Timer is disabled and can be enabled by software
PWMLOCK
FDEVOPT
PWM Lock Enable bit
1 = Certain PWM registers may only be written after a key sequence
0 = PWM registers may be written without a key sequence
ALTI2C1
FDEVOPT
Alternate I2C Pins for I2C1 bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
CTXT1[2:0]
FALTREG
Specifies the Alternate Working Register Set 1 Association with
Interrupt Priority Level (IPL) bits
111 = Not assigned
110 = Alternate Register Set 1 is assigned to IPL Level 7
101 = Alternate Register Set 1 is assigned to IPL Level 6
100 = Alternate Register Set 1 is assigned to IPL Level 5
011 = Alternate Register Set 1 is assigned to IPL Level 4
010 = Alternate Register Set 1 is assigned to IPL Level 3
001 = Alternate Register Set 1 is assigned to IPL Level 2
000 = Alternate Register Set 1 is assigned to IPL Level 1
CTXT2[2:0]
FALTREG
Specifies the Alternate Working Register Set 2 Association with
Interrupt Priority Level (IPL) bits
111 = Not assigned
110 = Alternate Register Set 2 is assigned to IPL Level 7
101 = Alternate Register Set 2 is assigned to IPL Level 6
100 = Alternate Register Set 2 is assigned to IPL Level 5
011 = Alternate Register Set 2 is assigned to IPL Level 4
010 = Alternate Register Set 2 is assigned to IPL Level 3
001 = Alternate Register Set 2 is assigned to IPL Level 2
000 = Alternate Register Set 2 is assigned to IPL Level 1
DS70005144H-page 326
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
REGISTER 27-1:
R
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
DEVID[23:16](1)
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVID[15:8](1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID[7:0](1)
bit 7
bit 0
Legend: R = Read-Only bit
bit 23-0
Note 1:
DEVID[23:0]: Device Identifier bits(1)
Refer to “dsPIC33EVXXXGM00X/10X Families Flash Programming Specification” (DS70005137) for the
list of Device ID values.
REGISTER 27-2:
R
U = Unimplemented bit
DEVREV: DEVICE REVISION REGISTER
R
R
R
R
R
R
R
DEVREV[23:16](1)
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVREV[15:8](1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVREV[7:0](1)
bit 7
bit 0
Legend: R = Read-only bit
bit 23-0
Note 1:
U = Unimplemented bit
DEVREV[23:0]: Device Revision bits(1)
Refer to “dsPIC33EVXXXGM00X/10X Families Flash Programming Specification” (DS70005137) for the
list of device revision values.
2013-2019 Microchip Technology Inc.
DS70005144H-page 327
dsPIC33EVXXXGM00X/10X FAMILY
27.2
User OTP Memory
Locations, 800F80h-800FFEh, are a One-TimeProgrammable (OTP) memory area. The user OTP
words can be used for storing product information, such
as serial numbers, system manufacturing dates, manufacturing lot numbers and other application-specific
information.
27.3
On-Chip Voltage Regulator
All of the dsPIC33EVXXXGM00X/10X family devices
power their core digital logic at a nominal 1.8V. This can
create a conflict for designs that are required to operate at
a higher typical voltage, such as 5.0V. To simplify system
design, all devices in the dsPIC33EVXXXGM00X/10X
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the VCAP
pin (see Figure 27-1). This helps to maintain the stability
of the regulator. The recommended value for the filter
capacitor is provided in Table 30-5, located in
Section 30.0 “Electrical Characteristics”.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
27.4
Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the regulated supply voltage, VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source based on the
device Configuration bit values (FNOSC[2:0] and
POSCMD[1:0]).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON[5]) is ‘1’.
Concurrently, the Power-up Timer (PWRT) Time-out
(TPWRT) is applied before the internal Reset is released.
If TPWRT = 0 and a crystal oscillator is being used, then a
nominal delay of TFSCM is applied. The total delay in this
case is TFSCM. Refer to Parameter SY35 in Table 30-22
of Section 30.0 “Electrical Characteristics” for specific
TFSCM values.
The BOR status bit (RCON[1]) is set to indicate that a
BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle mode and resets the device
should VDD fall below the BOR threshold voltage.
5.0V
dsPIC33EV
VDD
AVDD
CEFC
VCAP
VSS
AVSS
Note 1:
2:
3:
These are typical operating voltages.
Refer to Table 30-4 located in
Section 30.1 “DC Characteristics” for
the full operating ranges of VDD and VCAP.
It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP pin.
Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.
DS70005144H-page 328
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
27.5
Watchdog Timer (WDT)
27.5.2
For dsPIC33EVXXXGM00X/10X family devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
27.5.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The
prescaler is set by the WDTPRE Configuration bit. With a
32 kHz input, the prescaler yields a WDT Time-out Period
(TWDT), as shown in Parameter SY12 in Table 30-22.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST[3:0]
Configuration bits (FWDT[3:0]), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 27-2:
SLEEP AND IDLE MODES
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes the device and code execution continues from
where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bit (RCON[3:2]) needs to be
cleared in software after the device wakes up.
27.5.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN[1:0]
Configuration bits in the FWDT Configuration register.
When the FWDTEN[1:0] Configuration bits are set, the
WDT is always enabled.
The WDT can be optionally controlled in software
when the FWDTENx Configuration bits have been
programmed to ‘00’. The WDT is enabled in software
by setting the SWDTEN control bit (RCON[5]). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user application
to enable the WDT for critical code segments and
disable the WDT during non-critical segments for
maximum power savings.
The WDT flag bit, WDTO (RCON[4]), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
27.5.4
WDT WINDOW
The Watchdog Timer has an optional Windowed mode
enabled by programming the WINDIS bit in the WDT
Configuration register (FWDT[7]). In the Windowed
mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Window (WDTWIN[1:0]) select bits.
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
Sleep/Idle
WDTPOST[3:0]
WDTPRE
SWDTEN
FWDTEN[1:0]
WDT
Wake-up
RS
Prescaler
(Divide-by-N1)
LPRC Clock
WINDIS
WDTWIN[1:0]
1
RS
Postscaler
(Divide-by-N2)
0
WDT
Reset
WDT Window Select
CLRWDT Instruction
2013-2019 Microchip Technology Inc.
DS70005144H-page 329
dsPIC33EVXXXGM00X/10X FAMILY
27.6
In-Circuit Serial Programming
The dsPIC33EVXXXGM00X/10X family devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data, and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the device just before shipping the
product. Serial programming also allows the most recent
firmware or a custom firmware to be programmed.
Refer to “dsPIC33EVXXXGM00X/10X Families Flash
Programming Specification” (DS70005137) for details
about In-Circuit Serial Programming™ (ICSP™).
Any of the following three pairs of programming clock/
data pins can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
27.7
In-Circuit Debugger
When MPLAB® ICD 3 or REAL ICE™ is selected as a
debugger, the in-circuit debugging functionality is
enabled. This function allows simple debugging functions
when used with MPLAB X IDE. Debugging functionality
is controlled through the PGECx (Emulation/Debug
Clock) and PGEDx (Emulation/Debug Data) pin
functions.
DS70005144H-page 330
Any of the following three pairs of debugging clock/data
pins can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).
27.8
Code Protection and
CodeGuard™ Security
The dsPIC33EVXXXGM00X/10X family devices offer
Intermediate CodeGuard Security that supports
General Segment (GS) security, Boot Segment (BS)
security and Configuration Segment (CS) security. This
feature helps protect individual Intellectual Properties.
Note:
Refer to “CodeGuard™ Intermediate
Security”
(www.microchip.com/
DS70005182) in the “dsPIC33/PIC24
Family Reference Manual” for further
information on usage, configuration and
operation of CodeGuard Security.
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
28.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes the features of
the dsPIC33EVXXXGM00X/10X family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
The dsPIC33EV instruction set is almost identical to
that of the dsPIC30F and dsPIC33F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into following five basic categories:
•
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 28-1 lists the general symbols used in describing
the instructions.
The dsPIC33E instruction set summary in Table 28-2
lists all the instructions, along with the Status Flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have the following
three operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
2013-2019 Microchip Technology Inc.
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
DS70005144H-page 331
dsPIC33EVXXXGM00X/10X FAMILY
Most instructions are a single word. Certain double-word
instructions are designed to provide all the required
information in these 48 bits. In the second word, the
eight MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it executes as a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the
instruction, or a PSV or Table Read is performed. In
TABLE 28-1:
these cases, the execution takes multiple instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Certain instructions that involve skipping over
the subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or twoword instruction. Moreover, double-word moves require
two cycles.
Note:
For more details on the instruction set, refer
to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70000157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{}
Optional field or operation
a {b, c, d}
a is selected from the set of values b, c, d
[n:m]
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word-addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0...W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (Direct Addressing)
DS70005144H-page 332
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 28-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0...W15}
Wnd
One of 16 Destination Working registers {W0...W15}
Wns
One of 16 Source Working registers {W0...W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X Data Space Prefetch Address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy
Y Data Space Prefetch Address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
2013-2019 Microchip Technology Inc.
DS70005144H-page 333
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 28-2:
Base
Instr
#
1
2
3
4
5
6
7
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
Note 1:
Assembly Syntax
Description
# of
Words
# of
Cycles(1)
Status Flags
Affected
1
1
OA,OB,SA,
SB
ADD
Acc
Add Accumulators
ADD
f
f = f + WREG
1
1
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
OA,OB,SA,
SB
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C,DC,N,OV,Z
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (4)
None
BRA
GE,Expr
Branch if Greater Than or Equal
1
1 (4)
None
BRA
GEU,Expr
Branch if Unsigned Greater Than or Equal
1
1 (4)
None
BRA
GT,Expr
Branch if Greater Than
1
1 (4)
None
BRA
GTU,Expr
Branch if Unsigned Greater Than
1
1 (4)
None
BRA
LE,Expr
Branch if Less Than or Equal
1
1 (4)
None
BRA
LEU,Expr
Branch if Unsigned Less Than or Equal
1
1 (4)
None
BRA
LT,Expr
Branch if Less Than
1
1 (4)
None
BRA
LTU,Expr
Branch if Unsigned Less Than
1
1 (4)
None
BRA
N,Expr
Branch if Negative
1
1 (4)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (4)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (4)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (4)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (4)
None
BRA
OA,Expr
Branch if Accumulator A Overflow
1
1 (4)
None
BRA
OB,Expr
Branch if Accumulator B Overflow
1
1 (4)
None
BRA
OV,Expr
Branch if Overflow
1
1 (4)
None
BRA
SA,Expr
Branch if Accumulator A Saturated
1
1 (4)
None
BRA
SB,Expr
Branch if Accumulator B Saturated
1
1 (4)
None
BRA
Expr
Branch Unconditionally
1
4
None
BRA
Z,Expr
Branch if Zero
1
1 (4)
None
BRA
Wn
Computed Branch
1
4
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005144H-page 334
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 28-2:
Base
Instr
#
8
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BSW
Assembly Syntax
Description
# of
Words
# of
Cycles(1)
Status Flags
Affected
None
BSW.C
Ws,Wb
Write C bit to Ws[Wb]
1
1
BSW.Z
Ws,Wb
Write Z bit to Ws[Wb]
1
1
None
f,#bit4
Bit Toggle f
1
1
None
9
BTG
BTG
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
10
BTSC
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws[Wb] to C
1
1
C
11
12
13
14
15
BTSS
BTST
BTSTS
CALL
CLR
BTST.Z
Ws,Wb
Bit Test Ws[Wb] to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
CALL
lit23
Call Subroutine
2
4
SFA
CALL
Wn
Call Indirect Subroutine
1
4
SFA
CALL.L
Wn
Call Indirect Subroutine (long address)
1
4
SFA
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA,OB,SA,
SB
16
CLRWDT
CLRWDT
Clear Watchdog Timer
1
1
WDTO,Sleep
17
COM
COM
f
f=f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
CP
Wb,#lit8
Compare Wb with lit8
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C,DC,N,OV,Z
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
18
CP
19
CP0
CP0
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
20
CPB
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit8
Compare Wb with lit8, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C,DC,N,OV,Z
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
1
(2 or 3)
None
CPBEQ
CPBEQ
Wb,Wn,Expr
Compare Wb with Wn, Branch if =
1
1 (5)
None
CPSGT
CPSGT
Wb,Wn
Compare Wb with Wn, Skip if >
1
1
(2 or 3)
None
CPBGT
CPBGT
Wb,Wn,Expr
Compare Wb with Wn, Branch if >
1
1 (5)
None
CPSLT
CPSLT
Wb,Wn
Compare Wb with Wn, Skip if <
1
1
(2 or 3)
None
CPBLT
CPBLT
Wb,Wn,Expr
Compare Wb with Wn, Branch if <
1
1 (5)
None
CPSNE
CPSNE
Wb,Wn
Compare Wb with Wn, Skip if
1
1
(2 or 3)
None
CPBNE
CPBNE
Wb,Wn,Expr
Compare Wb with Wn, Branch if
1
1 (5)
None
21
22
23
24
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2019 Microchip Technology Inc.
DS70005144H-page 335
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TABLE 28-2:
Base
Instr
#
25
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
CTXTSWP
Assembly Syntax
Description
# of
Words
# of
Cycles(1)
Status Flags
Affected
CTXTSWP
#lit3
Switch CPU Register Context to Context
Defined by lit3
1
2
None
CTXTSWP
Wn
Switch CPU Register Context to Context
Defined by Wn
1
2
None
26
DAW
DAW
Wn
Wn = Decimal Adjust Wn
1
1
C
27
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
28
DEC2
DEC2
Ws,Wd
Wd = Ws – 2
1
1
29
DISI
DISI
#lit14
Disable Interrupts for k Instruction Cycles
1
1
None
30
DIV
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
Wm,Wn
Signed 16/16-bit Fractional Divide
1
18
N,Z,C,OV
31
DIVF
DIVF
32
DO
DO
#lit15,Expr
Do Code to PC + Expr, lit15 + 1 Times
2
2
None
DO
Wn,Expr
Do Code to PC + Expr, (Wn) + 1 Times
2
2
None
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
34
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
35
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
36
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
37
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
38
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
39
GOTO
GOTO
Expr
Go to Address
2
4
None
GOTO
Wn
Go to Indirect
1
4
None
GOTO.L
Wn
Go to Indirect (long address)
1
4
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
40
41
42
INC
INC2
IOR
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
OA,OB,OAB,
SA,SB,SAB
43
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
44
LNK
LNK
#lit14
Link Frame Pointer
1
1
SFA
45
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005144H-page 336
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 28-2:
Base
Instr
#
46
47
48
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
MAC
MOV
MOVPAG
Assembly Syntax
Description
# of
Words
# of
Cycles(1)
Status Flags
Affected
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
None
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit Literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit Literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
MOVPAG
#lit10,DSRPAG
Move 10-bit Literal to DSRPAG
1
1
None
MOVPAG
#lit9,DSWPAG
Move 9-bit Literal to DSWPAG
1
1
None
MOVPAG
#lit8,TBLPAG
Move 8-bit Literal to TBLPAG
1
1
None
MOVPAGW
Ws, DSRPAG
Move Ws[9:0] to DSRPAG
1
1
None
MOVPAGW
Ws, DSWPAG
Move Ws[8:0] to DSWPAG
1
1
None
MOVPAGW
Ws, TBLPAG
Move Ws[7:0] to TBLPAG
1
1
None
49
MOVSAC
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
Prefetch and Store Accumulator
1
1
None
50
MPY
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
51
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
52
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2019 Microchip Technology Inc.
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TABLE 28-2:
Base
Instr
#
53
54
55
56
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
MUL
NEG
NOP
POP
Assembly Syntax
PUSH
# of
Cycles(1)
Status Flags
Affected
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SS
Wb,Ws,Acc
Accumulator = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,Ws,Acc
Accumulator = signed(Wb) * unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Acc
Accumulator = signed(Wb) * unsigned(lit5)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
signed(Ws)
1
1
None
MUL.US
Wb,Ws,Acc
Accumulator = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.UU
Wb,#lit5,Acc
Accumulator = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,Ws,Acc
Accumulator = unsigned(Wb) *
unsigned(Ws)
1
1
None
MULW.SS
Wb,Ws,Wnd
Wnd = signed(Wb) * signed(Ws)
1
1
None
MULW.SU
Wb,Ws,Wnd
Wnd = signed(Wb) * unsigned(Ws)
1
1
None
MULW.US
Wb,Ws,Wnd
Wnd = unsigned(Wb) * signed(Ws)
1
1
None
MULW.UU
Wb,Ws,Wnd
Wnd = unsigned(Wb) * unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) *
unsigned(lit5)
1
1
None
MUL.SU
Wb,#lit5,Wnd
Wnd = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
Wnd = unsigned(Wb) * unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
PUSH
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
1
2
None
Push Shadow Registers
1
1
None
Go into Sleep or Idle mode
1
1
WDTO,Sleep
POP.S
57
# of
Words
Description
PUSH.S
58
PWRSAV
PWRSAV
59
RCALL
RCALL
Expr
Relative Call
1
4
SFA
RCALL
Wn
Computed Call
1
4
SFA
REPEAT
#lit15
Repeat Next Instruction lit15 + 1 Times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 Times
1
1
None
60
REPEAT
#lit1
61
RESET
RESET
Software Device Reset
1
1
None
62
RETFIE
RETFIE
Return from Interrupt
1
6 (5)
SFA
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005144H-page 338
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 28-2:
Base
Instr
#
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
Assembly Syntax
63
RETLW
RETLW
64
RETURN
RETURN
65
RLC
RLC
66
67
68
69
RLNC
RRC
RRNC
SAC
Description
# of
Words
# of
Cycles(1)
Status Flags
Affected
SFA
Return with Literal in Wn
1
6 (5)
Return from Subroutine
1
6 (5)
SFA
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
#lit10,Wn
70
SE
SE
Ws,Wnd
Wnd = Sign-Extended Ws
1
1
C,N,Z
71
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
SUBB
f
f = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
C,DC,N,OV,Z
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
C,DC,N,OV,Z
72
73
74
75
76
77
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2013-2019 Microchip Technology Inc.
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TABLE 28-2:
Base
Instr
#
78
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
SWAP
Assembly Syntax
Description
# of
Words
# of
Cycles(1)
Status Flags
Affected
SWAP.b
Wn
Wn = Nibble Swap Wn
1
1
None
SWAP
Wn
Wn = Byte Swap Wn
1
1
None
79
TBLRDH
TBLRDH
Ws,Wd
Read Prog[23:16] to Wd[7:0]
1
5
None
80
TBLRDL
TBLRDL
Ws,Wd
Read Prog[15:0] to Wd
1
5
None
81
TBLWTH
TBLWTH
Ws,Wd
Write Ws[7:0] to Prog[23:16]
1
2
None
82
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog[15:0]
1
2
None
83
ULNK
ULNK
Unlink Frame Pointer
1
1
SFA
84
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-Extend Ws
1
1
C,Z,N
85
ZE
Note 1:
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005144H-page 340
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
29.0
DEVELOPMENT SUPPORT
Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip
tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs)
in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools.
Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work
seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application,
while our line of third party tools round out our comprehensive development tool solutions.
Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which support multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible
with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows.
Go to the following website for more information and details:
https://www.microchip.com/development-tools/
2013-2019 Microchip Technology Inc.
DS70005144H-page 341
dsPIC33EVXXXGM00X/10X FAMILY
NOTES:
DS70005144H-page 342
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
30.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33EVXXXGM00X/10X family electrical characteristics. Additional
information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EVXXXGM00X/10X family are listed below. Exposure to these maximum
rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any
other conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +160°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +6.0V
Voltage on VCAP with respect to VSS ........................................................................................................ 1.62V to 1.98V
Maximum current out of VSS pin ...........................................................................................................................350 mA
Maximum current into VDD pin(2) ...........................................................................................................................350 mA
Maximum current sunk by any I/O pin.....................................................................................................................20 mA
Maximum current sourced by I/O pin ......................................................................................................................18 mA
Maximum current sourced/sunk by all ports(2) ......................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
2013-2019 Microchip Technology Inc.
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dsPIC33EVXXXGM00X/10X FAMILY
30.1
DC Characteristics
TABLE 30-1:
OPERATING MIPS vs. VOLTAGE
VDD Range
(in Volts)
Characteristic
2:
-40°C to 0°C
60
0°C to +85°C
70
-40°C to +125°C
60
(1,2)
E-Temp
Note 1:
dsPIC33EVXXXGM00X/10X Family
4.5V to 5.5V(1,2)
I-Temp
Maximum MIPS
Temperature Range
(in °C)
4.5V to 5.5V
< VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
Device is functional at
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized. Refer to Parameter BO10 in Table 30-12 for the minimum and maximum BOR values.
When BOR is enabled, the device will work from 4.7V to 5.5V.
VBORMIN
Note 1: Customer operating voltage range is specified as: 4.5V to 5.5V.
TABLE 30-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typ.
Max.
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices:
Extended Temperature Devices:
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 30-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ.
Max.
Unit
Package Thermal Resistance, 64-Pin QFN, 9x9x0.9 mm
JA
28.0
—
°C/W
1
Package Thermal Resistance, 64-Pin TQFP, 10x10x1 mm
JA
48.3
—
°C/W
1
Package Thermal Resistance, 44-Pin QFN, 8x8 mm
JA
29.0
—
°C/W
1
Package Thermal Resistance, 44-Pin TQFP, 10x10x1 mm
JA
49.8
—
°C/W
1
Package Thermal Resistance, 48-pin TQFP, 7x7x1 mm
JA
62.76
—
°C/W
1
Package Thermal Resistance, 36-Pin UQFN, 5x5 mm
JA
29.2
—
°C/W
1
Package Thermal Resistance, 28-Pin QFN-S, 6x6x0.9 mm
JA
30.0
—
°C/W
1
Package Thermal Resistance, 28-Pin SOIC, 7.50 mm
JA
69.7
—
°C/W
1
Package Thermal Resistance, 28-Pin SSOP, 5.30 mm
JA
71.0
—
°C/W
1
Package Thermal Resistance, 28-Pin SPDIP, 300 mil
JA
60.0
—
°C/W
1
Note 1:
Notes
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
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TABLE 30-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions (see Note 3): 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.(1)
Max.
Units
VBOR
—
5.5
V
Conditions
Operating Voltage
DC10
VDD
Supply Voltage(3)
(2)
DC12
VDR
RAM Data Retention Voltage
1.8
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
—
VSS
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
1.0
—
—
DC18
VCORE
VDD Core
Internal Regulator Voltage
1.62
1.8
1.98
Note 1:
2:
3:
V/ms 0V-5.0V in 5 ms
V
Voltage is dependent on
load, temperature and
VDD
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
This is the limit to which VDD may be lowered without losing RAM data.
VDD voltage must remain at VSS for a minimum of 200 µs to ensure POR.
TABLE 30-5:
FILTER CAPACITOR (CEFC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
CEFC
Note 1:
Characteristics
External Filter Capacitor
Value(1)
Min.
Typ.
Max.
Units
Comments
4.7
10
—
µF
Capacitor must have a low
series resistance (< 1)
Typical VCAP Voltage = 1.8 volts when VDD VDDMIN.
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TABLE 30-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param.
Typ.(2)
Operating Current (IDD)
Max.
Units
Conditions
(1)
DC20d
4.5
5.5
mA
-40°C
DC20a
4.65
5.6
mA
+25°C
DC20b
4.85
6.0
mA
+85°C
DC20c
5.6
7.2
mA
+125°C
DC22d
8.6
10.6
mA
-40°C
DC22a
8.8
10.8
mA
+25°C
DC22b
9.1
11.1
mA
+85°C
DC22c
9.8
12.6
mA
+125°C
DC23d
16.8
18.5
mA
-40°C
DC23a
17.2
19.0
mA
+25°C
DC23b
17.55
19.2
mA
+85°C
DC23c
18.3
21.0
mA
+125°C
DC24d
25.15
28.0
mA
-40°C
DC24a
25.5
28.0
mA
+25°C
DC24b
25.5
28.0
mA
+85°C
DC24c
25.55
28.5
mA
+125°C
DC25d
29.0
31.0
mA
-40°C
DC25a
28.5
31.0
mA
+25°C
DC25b
28.3
31.0
mA
+85°C
Note 1:
2:
5.0V
10 MIPS
5.0V
20 MIPS
5.0V
40 MIPS
5.0V
60 MIPS
5.0V
70 MIPS
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• CPU executing
while(1)
{
NOP();
}
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
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TABLE 30-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typ.(2)
Max.
Units
Conditions
2
mA
-40°C
Idle Current (IIDLE)(1)
DC40d
1.25
DC40a
1.25
2
mA
+25°C
DC40b
1.5
2.6
mA
+85°C
DC40c
1.5
2.6
mA
+125°C
DC42d
2.3
3
mA
-40°C
DC42a
2.3
3
mA
+25°C
DC42b
2.6
3.45
mA
+85°C
DC42c
2.6
3.85
mA
+125°C
DC44d
6.9
8
mA
-40°C
DC44a
6.9
8
mA
+25°C
DC44b
7.25
8.6
mA
+85°C
Note 1:
2:
5.0V
10 MIPS
5.0V
20 MIPS
5.0V
70 MIPS
Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active, OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• The NVMSIDL bit (NVMCON[12]) = 1 (i.e., Flash regulator is set to standby while the device is in Idle
mode)
• The VREGSF bit (RCON[11]) = 0 (i.e., Flash regulator is set to standby while the device is in
Sleep mode)
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
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TABLE 30-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typ.
Max.
Units
Conditions
Power-Down Current (IPD) – dsPIC33EVXXXGM00X/10X
9.25
35
µA
9.25
60
µA
15.75
40
µA
15.75
75
µA
67.75
300
µA
67.75
425
µA
DC60c
270
820
DC61d
1
7
DC61a
1.25
8
µA
+25°C
DC61b
3.5
12
µA
+85°C
DC61c
5
15
µA
+125°C
DC60d
DC60a
DC60b
DS70005144H-page 348
Grade 3 Mission Profile
-40°C
5.0V
+25°C
5.0V
+85°C
5.0V
µA
+125°C
5.0V
Grade 1 Mission Profile
µA
-40°C
5.0V
Watchdog Timer Current: IWDT
Grade 1 Mission Profile
Grade 3 Mission Profile
Grade 1 Mission Profile
Grade 3 Mission Profile
Base Power-Down
Current
Grade 1 Mission Profile
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TABLE 30-9:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Doze
Ratio
Units
18.25
1:2
mA
8.0
1:128
mA
18.5
1:2
mA
8.2
1:128
mA
19.0
1:2
mA
8.9
1:128
mA
Typ.(2)
Max.
DC73a
16.0
DC73g
7.1
DC70a
16.25
DC70g
7.3
DC71a
17.0
DC71g
7.5
DC72a
17.75
19.95
1:2
mA
DC72g
8.25
9.32
1:128
mA
Parameter No.
Conditions
Doze Current (IDOZE)(1)
Note 1:
2:
-40°C
5.0V
70 MIPS
+25°C
5.0V
70 MIPS
+85°C
5.0V
70 MIPS
+125°C
5.0V
60 MIPS
IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as outputs and driving low
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• CPU executing
while(1)
{
NOP();
}
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
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TABLE 30-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
DI10
Characteristic
VIH
Typ.(1)
Max.
Units
VSS
—
0.2 VDD
V
0.75 VDD
—
5.5
V
Conditions
Input Low Voltage
I/O Pins
DI20
Min.
Input High Voltage
I/O Pins
DI30
ICNPU
Change Notification Pull-up
Current
200
375
600
µA
VDD = 5.0V, VPIN = VSS
DI31
ICNPD
Change Notification
Pull-Down Current(7)
175
400
625
µA
VDD = 5.0V, VPIN = VDD
IIL
Input Leakage Current(2,3)
DI50
I/O Pins
-100
—
100
nA
VSS VPIN VDD,
pin at high-impedance
DI55
MCLR
-700
—
700
nA
VSS VPIN VDD
DI56
OSC1
-200
—
200
nA
VSS VPIN VDD,
XT and HS modes
DI60a
IICL
Input Low Injection Current
0
—
-5(4,6)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP and RB7
DI60b
IICH
Input High Injection Current
0
—
+5(5,6)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, RB7 and all 5V
tolerant pins(5)
DI60c
IICT
Total Input Injection Current
(sum of all I/O and control
pins)
-20(7)
—
+20(7)
mA
Absolute instantaneous
sum of all ± input
injection currents from all
I/O pins
( | IICL |+ | IICH | ) IICT
Note 1:
2:
3:
4:
5:
6:
7:
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
VIL source < (VSS – 0.3). Characterized but not tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Non-zero injection currents can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
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TABLE 30-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
Characteristic
Min.(1)
Typ.
Max.
Units
Conditions
DO16
VOL
Output Low Voltage
4x Sink Driver Pins(2)
—
—
0.4
V
IOL = 8.8 mA, VDD = 5.0V
DO10
VOL
Output Low Voltage
8x Sink Driver Pins(3)
—
—
0.4
V
IOL = 10.8 mA, VDD = 5.0V
Output High Voltage
4x Sink Driver Pins(2)
VDD – 0.6
—
—
V
IOH = -8.3 mA, VDD = 5.0V
Output High Voltage
8x Sink Driver Pins
VDD – 0.6
—
—
V
IOH = -12.3 mA, VDD = 5.0V
DO26
VOH
DO20
VOH
Note 1:
2:
3:
Parameters are characterized, but not tested.
Includes all I/O pins that are not 8x sink driver pins (see below).
Includes pins, such as RA3, RA4 and RB[15:10] for 28-pin and 36-pin devices, RA3, RA4, RA9 and
RB[15:10] for 44-pin and 48-pin devices, RA4, RA7, RA9, RB[15:10] and RC15 for 64-pin devices.
TABLE 30-12: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.(1)
Typ.
Max.
Units
BOR Event on VDD Transition
High-to-Low
4.15
4.285
4.4
V
Conditions
VDD (see Note 2, Note 3
and Note 4)
BO10
VBOR
Note 1:
2:
3:
Parameters are for design guidance only and are not tested in manufacturing.
The VBOR specification is relative to the VDD.
The device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and
comparator voltage reference will have degraded performance. Device functionality is tested but not
characterized.
The start-up VDD must rise above 4.6V.
4:
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TABLE 30-13: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.(1)
Max.
10,000
—
—
Units
Conditions
Program Flash Memory
EP
Cell Endurance
D131
VPR
VDD for Read
4.5
—
5.5
V
D132b
VPEW
VDD for Self-Timed Write
4.5
—
5.5
V
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated, -40C to +125C
D135
IDDP
Supply Current During
Programming
—
10
—
mA
D136a
TRW
Row Write Cycle Time
0.657
—
0.691
ms
TRW = 4965 FRC cycles,
TA = +85°C (see Note 2)
D136b
TRW
Row Write Cycle Time
0.651
—
0.698
ms
TRW = 4965 FRC cycles,
TA = +125°C (see Note 2)
D137a
TPE
Page Erase Time
19.44
—
20.44
ms
TPE = 146893 FRC cycles,
TA = +85°C (see Note 2)
D137b
TPE
Page Erase Time
19.24
—
20.65
ms
TPE = 146893 FRC cycles,
TA = +125°C (see Note 2)
D138a
TWW
Word Write Cycle Time
45.78
—
48.15
µs
TWW = 346 FRC cycles,
TA = +85°C (see Note 2)
D138b
TWW
Word Write Cycle Time
45.33
—
48.64
µs
TWW = 346 FRC cycles,
TA = +125°C (see Note 2)
D130
Note 1:
2:
E/W -40C to +125C
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
Other conditions: FRC = 7.3728 MHz, TUN[5:0] = b'011111 (for Min), TUN[5:0] = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 30-20) and the value of the FRC Oscillator
Tuning register.
TABLE 30-14: ELECTRICAL CHARACTERISTICS: INTERNAL BAND GAP REFERENCE VOLTAGE
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
DVR10
Symbol
VBG
DS70005144H-page 352
Characteristic
Min.
Typ.
Max.
Units
Internal Band Gap Reference
Voltage
1.14
1.2
1.26
V
Conditions
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30.2
AC Characteristics and Timing
Parameters
This section defines the dsPIC33EVXXXGM00X/10X family AC characteristics and timing parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 30.1 “DC
Characteristics”.
AC CHARACTERISTICS
FIGURE 30-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for All Pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
15
pF
In XT and HS modes, when
external clock is used to drive
OSC1
DO50
COSCO
OSC2 Pin
—
—
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C mode
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FIGURE 30-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
OS20
OS30
OS25
OS30
OS31
OS31
CLKO
OS40
OS41
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
FIN
OS20
Min.
Typ.(1)
Max.
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz
EC
Oscillator Crystal Frequency
3.5
10
—
—
10
25
MHz
MHz
XT
HS
TOSC = 1/FOSC
12.5
—
DC
ns
Sym
TOSC
Characteristic
Time(2)
Conditions
TA = +125°C
OS25
TCY
Instruction Cycle
25
—
DC
ns
TA = +125°C
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
—
0.625 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
5.2
—
ns
OS41
TckF
CLKO Fall Time(3)
—
5.2
—
ns
OS42
GM
External Oscillator
Transconductance(4)
—
12
—
mA/V
HS, VDD = 5.0V,
TA = +25°C
—
6
—
mA/V
XT, VDD = 5.0V,
TA = +25°C
Note 1:
2:
3:
4:
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
This parameter is characterized but not tested in manufacturing.
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TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8.0
MHz
OS51
FSYS
On-Chip VCO System
Frequency
120
—
340
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
ms
OS53
DCLK
CLKO Stability (Jitter)(2)
-3
0.5
3
%
Note 1:
2:
Conditions
ECPLL, XTPLL modes
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = ------------------------------------------------------------------------------------------F OSC
--------------------------------------------------------------------------------------Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPI bit rate = 10 MHz, the effective jitter is as follows:
D CLK
D CLK
D CLK
Effective Jitter = -------------- = -------------- = -------------3.464
120
12
--------10
TABLE 30-19: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 4.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a
FRC
-1
0.5
+1
%
-40°C TA +85°C
VDD = 4.5-5.5V
F20b
FRC
-2
1
+2
%
-40°C TA +125°C
VDD = 4.5-5.5V
Note 1:
Frequency calibrated at +25°C and 5.0V. TUN[5:0] bits can be used to compensate for temperature drift.
TABLE 30-20: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 4.5V to 5.5V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
LPRC
-15
5
+15
%
-40°C TA +85°C
VDD = 4.5-5.5V
F21b
LPRC
-30
10
+30
%
-40°C TA +125°C
VDD = 4.5-5.5V
Note 1:
Change of LPRC frequency as VDD changes.
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FIGURE 30-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Typ.(1)
Max.
Units
—
5
10
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
5
10
ns
DI35
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TCY
Note 1:
Port Output Rise Time
Min.
Conditions
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
FIGURE 30-4:
BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
Various Delays (depending on configuration)
Reset Sequence
CPU Starts Fetching Code
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FIGURE 30-5:
POWER-ON RESET TIMING CHARACTERISTICS
Power-up Timer – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
Power-up Sequence
CPU Starts Fetching Code
SY00 SY11
(TPU) (TPWRT)
(Notes 1,2)
Power-up Timer – Clock Sources = (HS, HSPLL, XT and XTPLL)
VDD
VPOR
Power-up Sequence
CPU Starts Fetching Code
Greater of
SY00
(TPU) SY10 (TOST)
(Notes 1,2)
or
SY11 (TPWRT)
Note 1:
2:
The power-up period will be extended if the power-up sequence completes before the device exits from
BOR (VDD < VBOR).
The power-up period includes internal voltage regulator stabilization delay.
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TABLE 30-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Min.
Characteristic(1)
Symbol
Typ.(2)
Max. Units
Conditions
SY00
TPU
Power-up Period
—
400
600
µs
SY10
TOST
Oscillator Start-up
Time
—
1024 TOSC
—
—
TOSC = OSC1 period
SY11
TPWRT
Power-up Timer
Period
—
1
—
ms
Using LPRC parameters indicated in
F21a/F21b (see Table 30-20)
SY12
TWDT
Watchdog Timer
Time-out Period
0.8
—
1.2
ms
WDTPRE = 0, WDTPS[3:0] = 0000,
using LPRC tolerances indicated in
F21a/F21b (see Table 30-20) at
+85°C
3.2
—
4.8
ms
WDTPRE = 1, WDTPS[3:0] = 0000,
using LPRC tolerances indicated in
F21a/F21b (see Table 30-20) at
+85°C
0.68
0.72
1.2
µs
SY13
TIOZ
I/O High-Impedance
from MCLR Low or
Watchdog Timer Reset
SY20
TMCLR
MCLR Pulse Width
(low)
2
—
—
µs
SY30
TBOR
BOR Pulse Width
(low)
1
—
—
µs
SY35
TFSCM
Fail-Safe Clock
Monitor Delay
—
500
900
µs
SY36
TVREG
Voltage Regulator
Standby-to-Active
mode Transition Time
—
—
30
µs
SY37
TOSCDFRC
FRC Oscillator
Start-up Delay
46
48
54
µs
SY38
TOSCDLPRC LPRC Oscillator
Start-up Delay
—
—
70
µs
Note 1:
2:
-40°C to +85°C
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
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FIGURE 30-6:
TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10
Tx11
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
TA11
Symbol
TTXH
TTXL
Characteristic(2)
Min.
Typ.
Max.
Units
Conditions
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TA15,
N = Prescaler Value
(1, 8, 64, 256)
Asynchronous
mode
35
—
—
ns
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Asynchronous
mode
10
—
—
ns
T1CK High Synchronous
Time
mode
T1CK Low
Time
TA15
TTXP
T1CK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
OS60
Ft1
T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting TCS
(T1CON[1]) bit)
DC
—
50
kHz
TA20
TCKEXTMRL Delay from External T1CK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
2:
Must also meet
Parameter TA15,
N = Prescaler Value
(1, 8, 64, 256)
N = Prescaler Value
(1, 8, 64, 256)
Timer1 is a Type A.
These parameters are characterized but not tested in manufacturing.
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TABLE 30-24: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TB10
TTXH
TxCK High Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescaler Value
(1, 8, 64, 256)
TB11
TTXL
TxCK Low Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescaler Value
(1, 8, 64, 256)
TB15
TTXP
TxCK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = Prescaler Value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
TABLE 30-25: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min.
Typ.
Max.
Units
Conditions
TC10
TTXH
TxCK High Synchronous
Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TTXL
TxCK Low
Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TTXP
TxCK Input Synchronous,
Period
with Prescaler
2 TCY + 40
—
—
ns
N = Prescaler Value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
Synchronous
These parameters are characterized but not tested in manufacturing.
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FIGURE 30-7:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note 1: Refer to Figure 30-1 for load conditions.
TABLE 30-26: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC11
TCCH
ICx Input High Time
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC15
TCCP
ICx Input Period
Greater of:
25 + 50 or
(1 TCY/N) + 50
—
ns
Note 1:
N = Prescaler
Value (1, 4, 16)
These parameters are characterized but not tested in manufacturing.
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FIGURE 30-8:
OUTPUT COMPARE x (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-27: OUTPUT COMPARE x (OCx) TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
FIGURE 30-9:
OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 30-28: OCx/PWMx MODE TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
OC15
TFD
Fault Input to PWMx I/O
Change
—
—
TCY + 20
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
DS70005144H-page 362
Conditions
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FIGURE 30-10:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 30-11:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
—
ns
See Parameter DO32
See Parameter DO31
MP10
TFPWM
PWMx Output Fall Time
—
—
MP11
TRPWM
PWMx Output Rise Time
—
—
—
ns
MP20
TFD
Fault Input to PWMx
I/O Change
—
—
15
ns
MP30
TFH
Fault Input Pulse Width
15
—
—
ns
Note 1:
Conditions
These parameters are characterized but not tested in manufacturing.
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TABLE 30-30: SPI2 MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 30-31
—
—
0,1
0,1
0,1
9 MHz
—
Table 30-32
—
1
0,1
1
9 MHz
—
Table 30-33
—
0
0,1
1
15 MHz
—
—
Table 30-34
1
0
0
11 MHz
—
—
Table 30-35
1
1
0
15 MHz
—
—
Table 30-36
0
1
0
11 MHz
—
—
Table 30-37
0
0
0
FIGURE 30-12:
SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS
SCK2
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK2
(CKP = 1)
SP35
SDO2
MSb
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
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FIGURE 30-13:
SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS
SP36
SCK2
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK2
(CKP = 1)
SP35
MSb
SDO2
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-31: SPI2 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK2 Frequency
—
—
15
MHz
SP20
TscF
SCK2 Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCK2 Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDO2 Data Output Valid after
SCK2 Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI2 pins.
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FIGURE 30-14:
SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SP36
SCK2
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK2
(CKP = 1)
SP35
SDO2
MSb
LSb
SP30, SP31
SP40
SDI2
Bit 14 - - - - - -1
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-32: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK2 Frequency
—
—
9
MHz
SP20
TscF
SCK2 Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCK2 Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO2 Data Output Valid after
TscL2doV SCK2 Edge
—
6
20
ns
SP36
TdoV2sc,
TdoV2scL
SDO2 Data Output Setup to
First SCK2 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data
Input to SCK2 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPI2 pins.
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FIGURE 30-15:
SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SCK2
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK2
(CKP = 1)
SP35 SP36
SDO2
MSb
Bit 14 - - - - - -1
SP30, SP31
SDI2
MSb In
LSb
SP30, SP31
Bit 14 - - - -1
LSb In
SP40 SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-33: SPI2 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK2 Frequency
—
—
9
MHz
-40ºC to +125ºC and
see Note 3
SP20
TscF
SCK2 Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCK2 Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO2 Data Output Valid after
TscL2doV SCK2 Edge
—
6
20
ns
SP36
TdoV2scH, SDO2 Data Output Setup to
TdoV2scL First SCK2 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data
Input to SCK2 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPI2 pins.
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FIGURE 30-16:
SS2
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SP60
SP52
SP50
SCK2
(CKP = 0)
SP70
SP73
SCK2
(CKP = 1)
SP36
SP35
MSb
SDO2
Bit 14 - - - - - -1
SP72
MSb In
Bit 14 - - - -1
SP73
LSb
SP30, SP31
SDI2
SP72
SP51
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
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TABLE 30-34: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK2 Input Frequency
—
—
15
MHz
SP72
TscF
SCK2 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK2 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO2 Data Output Valid after
TscL2doV SCK2 Edge
—
6
20
ns
SP36
TdoV2scH, SDO2 Data Output Setup to
TdoV2scL First SCK2 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120
—
—
ns
SP51
TssH2doZ
SS2 to SDO2 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH
TscL2ssH
SS2 after SCK2 Edge
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV
SDO2 Data Output Valid after
SS2 Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI2 pins.
2013-2019 Microchip Technology Inc.
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FIGURE 30-17:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SP60
SS2
SP52
SP50
SCK2
(CKP = 0)
SP70
SP73
SCK2
(CKP = 1)
SP36
SP35
MSb
SDO2
Bit 14 - - - - - -1
SP72
MSb In
Bit 14 - - - -1
SP73
LSb
SP30, SP31
SDI2
SP72
SP51
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
DS70005144H-page 370
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dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-35: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK2 Input Frequency
—
—
11
MHz
SP72
TscF
SCK2 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK2 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO2 Data Output Valid after
TscL2doV SCK2 Edge
—
6
20
ns
SP36
TdoV2scH, SDO2 Data Output Setup to
TdoV2scL First SCK2 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120
—
—
ns
SP51
TssH2doZ
SS2 to SDO2 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH
TscL2ssH
SS2 after SCK2 Edge
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV
SDO2 Data Output Valid after
SS2 Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI2 pins.
2013-2019 Microchip Technology Inc.
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FIGURE 30-18:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SS2
SP52
SP50
SCK2
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK2
(CKP = 1)
SP35 SP36
SDO2
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDI2
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
DS70005144H-page 372
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dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-36: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK2 Input Frequency
—
—
15
MHz
SP72
TscF
SCK2 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK2 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO2 Data Output Valid after
TscL2doV SCK2 Edge
—
6
20
ns
SP36
TdoV2scH, SDO2 Data Output Setup to
TdoV2scL First SCK2 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120
—
—
ns
SP51
TssH2doZ
SS2 to SDO2 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH
TscL2ssH
SS2 after SCK2 Edge
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 66.7 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI2 pins.
2013-2019 Microchip Technology Inc.
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FIGURE 30-19:
SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SS2
SP52
SP50
SCK2
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK2
(CKP = 1)
SP35 SP36
SDO2
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
SDI2
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
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TABLE 30-37: SPI2 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK2 Input Frequency
—
—
11
MHz
SP72
TscF
SCK2 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK2 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO2 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO2 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO2 Data Output Valid after
TscL2doV SCK2 Edge
—
6
20
ns
SP36
TdoV2scH, SDO2 Data Output Setup to
TdoV2scL First SCK2 Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI2 Data Input
to SCK2 Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SS2 to SCK2 or SCK2
Input
120
—
—
ns
SP51
TssH2doZ
SS2 to SDO2 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH
TscL2ssH
SS2 after SCK2 Edge
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK2 is 91 ns. Therefore, the SCK2 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI2 pins.
2013-2019 Microchip Technology Inc.
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TABLE 30-38: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
25 MHz
Table 30-39
—
—
0,1
0,1
0,1
25 MHz
—
Table 30-40
—
1
0,1
1
25 MHz
—
Table 30-41
—
0
0,1
1
25 MHz
—
—
Table 30-42
1
0
0
25 MHz
—
—
Table 30-43
1
1
0
25 MHz
—
—
Table 30-44
0
1
0
25 MHz
—
—
Table 30-45
0
0
0
FIGURE 30-20:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
SDO1
MSb
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
DS70005144H-page 376
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dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 30-21:
SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-39: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
25
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDO1 Data Output Valid after
SCK1 Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDO1 Data Output Setup to
First SCK1 Edge
20
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI1 pins.
2013-2019 Microchip Technology Inc.
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FIGURE 30-22:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35
MSb
SDO1
LSb
SP30, SP31
SP40
SDI1
Bit 14 - - - - - -1
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-40: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
25
MHz
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2sc,
TdoV2scL
SDO1 Data Output Setup to
First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data
Input to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70005144H-page 378
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 30-23:
SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCK1
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK1
(CKP = 1)
SP35 SP36
SDO1
MSb
Bit 14 - - - - - -1
SP30, SP31
SD1
MSb In
LSb
SP30, SP31
Bit 14 - - - -1
LSb In
SP40 SP41
Note: Refer to Figure 30-1 for load conditions.
2013-2019 Microchip Technology Inc.
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TABLE 30-41: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
FscP
Maximum SCK1 Frequency
—
—
25
MHz
-40°C to +125°C and
see Note 3
SP20
TscF
SCK1 Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCK1 Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data
Input to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70005144H-page 380
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 30-24:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SS1
SP50
SP52
SCK1
(CKP = 0)
SP70
SP73
SCK1
(CKP = 1)
SP36
SP35
SDO1
MSb
Bit 14 - - - - - -1
SP72
MSb In
Bit 14 - - - -1
SP73
LSb
SP30, SP31
SDI1
SP72
SP51
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
2013-2019 Microchip Technology Inc.
DS70005144H-page 381
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-42: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH
TscL2ssH
SS1 after SCK1 Edge
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV
SDO1 Data Output Valid after
SS1 Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
DS70005144H-page 382
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 30-25:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SS1
SP52
SP50
SCK1
(CKP = 0)
SP73
SP70
SCK1
(CKP = 1)
SP36
SP35
MSb
SDO1
Bit 14 - - - - - -1
SP72
MSb In
Bit 14 - - - -1
SP73
LSb
SP30, SP31
SDI1
SP72
SP51
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
2013-2019 Microchip Technology Inc.
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dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-43: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV
—
—
50
ns
Note 1:
2:
3:
4:
SDO1 Data Output Valid after
SS1 Edge
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 30-26:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35 SP36
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
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DS70005144H-page 385
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TABLE 30-44: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 30-27:
SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SS1
SP52
SP50
SCK1
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCK1
(CKP = 1)
SP35 SP36
SDO1
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDI1
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 30-1 for load conditions.
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TABLE 30-45: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP70
FscP
Maximum SCK1 Input Frequency
—
—
25
MHz
SP72
TscF
SCK1 Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCK1 Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDO1 Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDO1 Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDO1 Data Output Valid after
TscL2doV SCK1 Edge
—
6
20
ns
SP36
TdoV2scH, SDO1 Data Output Setup to
TdoV2scL First SCK1 Edge
20
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDI1 Data Input
to SCK1 Edge
20
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDI1 Data Input
to SCK1 Edge
15
—
—
ns
SP50
TssL2scH,
TssL2scL
SS1 to SCK1 or SCK1
Input
120
—
—
ns
SP51
TssH2doZ
SS1 to SDO1 Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH, SS1 after SCK1 Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
The minimum clock period for SCK1 is 40 ns. Therefore, the SCK1 clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPI1 pins.
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FIGURE 30-28:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM34
IM31
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-29:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM26
IM11
IM25
IM10
SDAx
In
IM40
IM40
IM33
IM45
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
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DS70005144H-page 389
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-46: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note 1:
2:
3:
4:
Characteristic(4)
Min.(1)
Max.
Units
Conditions
—
µs
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2)
400 kHz mode TCY/2 (BRG + 2)
—
µs
1 MHz mode(2) TCY/2 (BRG + 2)
—
µs
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2)
—
µs
400 kHz mode TCY/2 (BRG + 2)
—
µs
1 MHz mode(2) TCY/2 (BRG + 2)
—
µs
TF:SCL
SDAx and SCLx 100 kHz mode
—
300
ns
CB is specified to be
Fall Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
1 MHz mode(2)
40
—
ns
THD:DAT Data Input
100 kHz mode
0
—
µs
Hold Time
400 kHz mode
0
0.9
µs
1 MHz mode(2)
0.2
—
µs
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
µs
Only relevant for
Setup Time
Repeated
Start
—
µs
400 kHz mode TCY/2 (BRG + 2)
condition
(2)
1 MHz mode
TCY/2 (BRG + 2)
—
µs
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
µs
After this period, the
Hold Time
first clock pulse is
—
µs
400 kHz mode
TCY/2 (BRG +2)
generated
1 MHz mode(2) TCY/2 (BRG + 2)
—
µs
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
—
µs
Setup Time
400 kHz mode TCY/2 (BRG + 2)
—
µs
—
µs
1 MHz mode(2) TCY/2 (BRG + 2)
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
—
µs
Hold Time
400 kHz mode TCY/2 (BRG + 2)
—
µs
—
µs
1 MHz mode(2) TCY/2 (BRG + 2)
TAA:SCL Output Valid
100 kHz mode
—
3500
ns
From Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
TBF:SDA Bus Free Time 100 kHz mode
4.7
—
µs
Time the bus must be
free before a new
400 kHz mode
1.3
—
µs
transmission can start
0.5
—
µs
1 MHz mode(2)
CB
Bus Capacitive Loading
—
400
pF
TPGD
Pulse Gobbler Delay
65
390
ns
See Note 3
BRG is the value of the I2C Baud Rate Generator. Refer to “Inter-Integrated Circuit (I2C)”
(www.microchip.com/DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the
Microchip website for the latest “dsPIC33/PIC24 Family Reference Manual” sections.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
These parameters are characterized but not tested in manufacturing.
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FIGURE 30-30:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 30-31:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS25
IS31
SDAx
In
IS40
IS40
IS26
IS33
IS45
SDAx
Out
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DS70005144H-page 391
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TABLE 30-47: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic(3)
IS10
TLO:SCL Clock Low Time
IS11
THI:SCL
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
IS51
Note
Clock High Time
Min.
Max.
Units
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
4.7
1.3
0.5
4.0
—
—
—
—
µs
µs
µs
µs
400 kHz mode
0.6
—
µs
0.5
—
µs
1 MHz mode(1)
SDAx and SCLx 100 kHz mode
—
300
ns
TF:SCL
Fall Time
300
ns
400 kHz mode
20 + 0.1 CB
(1)
1 MHz mode
—
100
ns
—
1000
ns
TR:SCL SDAx and SCLx 100 kHz mode
Rise Time
300
ns
400 kHz mode
20 + 0.1 CB
1 MHz mode(1)
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
1 MHz mode(1)
100
—
ns
THD:DAT Data Input
100 kHz mode
0
—
µs
Hold Time
400 kHz mode
0
0.9
µs
1 MHz mode(1)
0
0.3
µs
TSU:STA Start Condition
100 kHz mode
4.7
—
µs
Setup Time
400 kHz mode
0.6
—
µs
(1)
1 MHz mode
0.25
—
µs
THD:STA Start Condition
100 kHz mode
4.0
—
µs
Hold Time
400 kHz mode
0.6
—
µs
1 MHz mode(1)
0.25
—
µs
TSU:STO Stop Condition
100 kHz mode
4.7
—
µs
Setup Time
400 kHz mode
0.6
—
µs
1 MHz mode(1)
0.6
—
µs
THD:STO Stop Condition
100 kHz mode
4
—
µs
Hold Time
400 kHz mode
0.6
—
µs
1 MHz mode(1)
0.25
µs
TAA:SCL Output Valid
100 kHz mode
0
3500
ns
From Clock
400 kHz mode
0
1000
ns
(1)
1 MHz mode
0
350
ns
TBF:SDA Bus Free Time
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
1 MHz mode(1)
0.5
—
µs
CB
Bus Capacitive Loading
—
400
pF
TPGD
Pulse Gobbler Delay
65
390
ns
1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: The typical value for this parameter is 130 ns.
3: These parameters are characterized but not tested in manufacturing.
DS70005144H-page 392
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
Time the bus must be free
before a new transmission
can start
See Note 2
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FIGURE 30-32:
CANx MODULE I/O TIMING CHARACTERISTICS
CxTX Pin
(output)
Old Value
New Value
CA10, CA11
CxRX Pin
(input)
CA20
TABLE 30-48: CANx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
CA10
Min.
Typ.(2)
Max.
Units
—
—
—
ns
See Parameter DO32
See Parameter DO31
TIOF
Port Output Fall Time
CA11
TIOR
Port Output Rise Time
—
—
—
ns
CA20
TCWF
Pulse Width to Trigger
CAN Wake-up Filter
120
—
—
ns
Note 1:
2:
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 30-33:
UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX
UxTX
MSb In
Bits 6-1
LSb In
UA10
TABLE 30-49: UARTx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature
-40°C TA +125°C
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
UA10
TUABAUD
UARTx Baud Time
UA11
FBAUD
UARTx Baud Frequency
UA20
TCWF
Start Bit Pulse Width to Trigger
UARTx Wake-up
Note 1:
2:
Min.
Typ.(2)
66.67
—
—
ns
—
—
15
Mbps
500
—
—
ns
Max.
Units
Conditions
These parameters are characterized but not tested in manufacturing.
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2013-2019 Microchip Technology Inc.
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TABLE 30-50: OP AMP/COMPARATOR x SPECIFICATIONS
Standard Operating Conditions (see Note 3): 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
V+ input step of 100 mV,
V- input held at VDD/2
Comparator AC Characteristics
CM10 TRESP
Response Time
—
19
80
ns
CM11
Comparator Mode
Change to Output Valid
—
—
10
µs
TMC2OV
Comparator DC Characteristics
CM30 VOFFSET
Comparator Offset
Voltage
-80
±60
80
mV
CM31 VHYST
Input Hysteresis Voltage
—
30
—
mV
CM32 TRISE/
TFALL
Comparator Output
Rise/Fall Time
—
20
—
ns
CM33 VGAIN
Open-Loop Voltage Gain
—
90
—
db
CM34 VICM
Input Common-Mode
Voltage
AVSS
—
AVDD
V
1 pF load capacitance
on input
Op Amp AC Characteristics
CM20 SR
Slew Rate
—
9
—
V/µs
CM21 PM
Phase Margin
—
35
—
°C
G = 100V/V, 10 pF load
CM22 GM
Gain Margin
—
20
—
db
G = 100V/V, 10 pF load
CM23 GBW
Gain Bandwidth
—
10
—
MHz
10 pF load
10 pF load
Op Amp DC Characteristics
CM40 VCMR
Common-Mode Input
Voltage Range
AVSS
—
AVDD
V
CM41 CMRR
Common-Mode
Rejection Ratio
—
45
—
db
CM42 VOFFSET
Op Amp Offset Voltage
-50
±6
50
mV
CM43 VGAIN
Open-Loop Voltage Gain
—
90
—
db
CM44 IOS
Input Offset Current
—
—
—
—
See pad leakage
currents in Table 30-10
CM45 IB
Input Bias Current
—
—
—
—
See pad leakage
currents in Table 30-10
CM46 IOUT
Output Current
—
—
420
µA
With minimum value of
RFEEDBACK (CM48)
8
—
—
k
See Note 2
AVSS + 0.075
—
AVDD – 0.075
V
IOUT = 420 µA
CM48 RFEEDBACK Feedback Resistance
Value
CM49a VOUT
Note 1:
2:
3:
Output Voltage
VCM = AVDD/2
Data in “Typ.” column are at 5.0V, +25°C unless otherwise stated.
Resistances can vary by ±10% between op amps.
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 30-12 for the minimum and
maximum BOR values.
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TABLE 30-51: OP AMP/COMPARATOR x VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS
Standard Operating Conditions (see Note 2): 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
VRD310 TSET
Note 1:
2:
Characteristic
Settling Time
Min.
Typ.
Max.
Units
—
1
10
µs
Conditions
See Note 1
Settling time measured while CVRSS = 1 and the CVR[6:0] bits transition from ‘0000000’ to ‘1111111’.
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 30-12 for the minimum and
maximum BOR values.
TABLE 30-52: OP AMP/COMPARATOR x VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (see Note 1): 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristics
Min.
Typ.
Max.
Units
Conditions
VRD311 CVRAA
Absolute Accuracy of
Internal DAC Input to
Comparators
—
±25
—
mV
AVDD = CVRSRC = 5.0V
VRD312 CVRAA1
Absolute Accuracy of
CVREFxO Pins
—
—
+35/-65
mV
AVDD = CVRSRC = 5.0V
VRD313 CVRSRC
Input Reference Voltage
0
—
AVDD + 0.3
V
VRD314 CVROUT
Buffer Output Resistance
—
1.5k
—
VRD315 CVCL
Permissible Capacitive
Load (CVREFxO pins)
—
—
25
pF
VRD316 IOCVR
Permissible Current
Output (CVREFxO pins)
—
—
1
mA
VRD317 ION
Current Consumed when
Module is Enabled
—
—
500
µA
AVDD = 5.0V
VRD318 IOFF
Current Consumed when
Module is Disabled
—
—
1
nA
AVDD = 5.0V
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 30-12 for the minimum and
maximum BOR values.
2013-2019 Microchip Technology Inc.
DS70005144H-page 395
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-53: CTMU CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
—
nA
Conditions
CTMU Current Source
CTMUI1
IOUT1
Base Range
CTMUI2
IOUT2
CTMUI3
IOUT3
CTMUI4
IOUT4
CTMUFV1 VF
CTMUFV2 VFVR
Note 1:
2:
—
550
10x Range
—
5.5
—
µA
CTMUICON[9:8] = 10
100x Range
—
55
—
µA
CTMUICON[9:8] = 11
1000x Range
—
550
—
µA
CTMUICON[9:8] = 00
Temperature Diode Forward
Voltage(1,2)
—
0.525
—
V
TA = +25°C,
CTMUICON[9:8] = 01
—
0.585
—
V
TA = +25°C,
CTMUICON[9:8] = 10
—
0.645
—
V
TA = +25°C,
CTMUICON[9:8] = 11
—
-1.92
—
mV/°C
CTMUICON[9.8] = 01
—
-1.74
—
mV/°C
CTMUICON[9:8] = 10
—
-1.56
—
mV/°C
CTMUICON[9:8] = 11
Temperature Diode Rate of
Change(1,2)
CTMUICON[9:8] = 01
Nominal value at center point of current trim range (CTMUICON[15:10] = 000000).
Parameters are characterized but not tested in manufacturing. Measurements are taken with the following
conditions:
• VREF = AVDD = 5.0V
• ADC configured for 10-bit mode
• ADC configured for conversion speed of 500 ksps
• All PMDx bits are cleared (PMDx = 0)
• CPU executing
while(1)
{
NOP();
}
• Device operating from the FRC with no PLL
DS70005144H-page 396
2013-2019 Microchip Technology Inc.
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-54: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions (see Note 1): 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or VBOR
—
Lesser of:
VDD + 0.3
or 5.5
V
AD02
AVSS
Module VSS Supply
VSS – 0.3
—
VSS + 0.3
V
AD05
VREFH
Reference Voltage High
4.5
—
5.5
V
AD06
VREFL
Reference Voltage Low
AVSS
—
AVDD – VBORMIN
V
See Note 1
0
—
0
V
VREFH = AVDD,
VREFL = AVSS = 0
Reference Inputs
AD06a
VREFH = AVDD,
VREFL = AVSS = 0
AD07
VREF
Absolute Reference
Voltage
4.5
—
5.5
V
VREF = VREFH – VREFL
AD08
IREF
Current Drain
—
—
—
—
10
600
µA
µA
ADC off
ADC on
AD09
IAD
Operating Current
—
5
—
mA
—
2
—
mA
ADC operating in 10-bit
mode (see Note 1)
ADC operating in 12-bit
mode (see Note 1)
Analog Input
AD12
VINH
Input Voltage Range VINH
VINL
—
VREFH
V
This voltage reflects
Sample-and-Hold
Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13
VINL
Input Voltage Range VINL
VREFL
—
AVSS + 1V
V
This voltage reflects
Sample-and-Hold
Channels 0, 1, 2 and 3
(CH0-CH3), negative input
AD17
RIN
Recommended
Impedance of Analog
Voltage Source
—
—
200
Impedance to achieve
maximum performance of
ADC
Note 1:
Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but is not characterized. Analog modules: ADC, op amp/comparator and comparator voltage
reference, will have degraded performance. Refer to Parameter BO10 in Table 30-12 for the minimum and
maximum BOR values.
2013-2019 Microchip Technology Inc.
DS70005144H-page 397
dsPIC33EVXXXGM00X/10X FAMILY
TABLE 30-55: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions (see Note 1): 4.5V to 5.5V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
ADC Accuracy (12-Bit Mode)
AD20a
Nr
Resolution
12 data bits
AD21a
INL
Integral Nonlinearity
AD22a
DNL
AD23a
bits
-2
—
+2
LSb
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 5.5V
Differential Nonlinearity
-1
—
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