dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302
16-Bit Microcontrollers and Digital Signal Controllers with
High-Speed PWM, ADC and Comparators
Operating Conditions
Advanced Analog Features (Continued)
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• ADC module:
- 10-bit resolution with Successive Approximation
Register (SAR) converter (2 Msps) and three
Sample-and-Hold (S&H) circuits
- Up to 8 input channels grouped into four conversion
pairs, plus two inputs for monitoring voltage references
- Flexible and independent ADC trigger sources
- Dedicated Result register for each
analog channel
Core: 16-Bit dsPIC33F CPU
•
•
•
•
•
Code Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Clock Management
Timers/Output Compare/Input Capture
•
•
•
•
•
•
•
•
•
±2% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
2.0 mA/MHz Dynamic Current (typical)
135 µA IPD Current (typical)
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 1.04 ns PWM Resolution for Dead Time, Duty Cycle,
Phase and Frequency
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC and Lighting
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• Two High-Speed Comparators with Direct Connection to
the PWM module:
- Buffered/amplified output drive
- Independent 10-bit DAC for each comparator
- Rail-to-rail comparator operation
- DACOUT amplifier (1x, 1.8x)
- Selectable hysteresis
- Programmable output polarity
- Interrupt generation capability
2011-2012 Microchip Technology Inc.
Two 16-Bit General Purpose Timers/Counters
Input Capture module
Output Compare module
Peripheral Pin Select (PPS) to allow Function Remap
Communication Interfaces
• UART module (10 Mbps):
- With support for LIN/J2602 protocols and IrDA®
• 4-Wire SPI module
• I2C™ module (up to 1 Mbaud) with SMBus Support
• PPS to allow Function Remap
Input/Output
• Constant Current Source:
- Constant current generator (10 µA nominal)
• Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• External Interrupts on 16 I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Two Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
DS75018C-page 1
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 PRODUCT
FAMILIES
The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. The
following pages show their pinout diagrams.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES
Input Capture
Output Compare
UART
SPI
PWM(2)
Analog Comparator
External Interrupts(1)
DAC Output
Constant Current Source
Reference Clock
I2C™
SARs
Sample-and-Hold (S&H) Circuit
Analog-to-Digital Inputs
256
8
2
0
0
0
0
2x2
2
3
0
0
0
1
1
2
6
PDIP,
13 SOIC
SSOP
6
256
8
2
0
1
1
1
2x2
0
3
0
0
1
1
1
3
6
PDIP,
13 SOIC
SSOP
20
dsPIC33FJ06GS101A
18
20
dsPIC33FJ06GS102A
28
6
256 16
2
0
1
1
1
2x2
0
3
0
0
1
1
1
3
6
36
dsPIC33FJ06GS202A
28
28
6
1K
16
2
1
1
1
1
2x2
2
3
1
0
1
1
1
3
6
9
1K
16
2
1
1
1
1
3x2
2
3
1
1
1
1
1
3
8
SPDIP,
SOIC,
21 SSOP,
QFN-S
VTLA
1:
INT0 is not remappable.
2:
The PWM4 pair is remappable and only available on dsPIC33FJ06GS001/101A and dsPIC33FJ09GS302 devices.
DS75018C-page 2
SPDIP,
SOIC,
21 SSOP,
QFN-S
VTLA
36
Note
SPDIP,
SOIC,
21 SSOP,
QFN-S
VTLA
36
dsPIC33FJ09GS302
Packages
16-Bit Timer
6
I/O Pins
Remappable Pins
18
ADC
RAM (Bytes)
dsPIC33FJ06GS001
Remappable Peripherals
Program Flash Memory (Kbytes)
Device
Pins
TABLE 1:
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams
= Pins are up to 5V tolerant
18-Pin SOIC, PDIP
1
18
2
17
VSS
AN1/CMP1B/RA1
3
16
PWM1L/RA3
15
PWM1H/RA4
14
VCAP
13
VSS
12
11
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
dsPIC33FJ06GS001
MCLR
AN0/CMP1A/RA0
AN2/CMP1C/CMP2A/RA2
4
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
5
OSC1/CLKI/AN6/RP1(1)/CN1/RB1
6
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
PGED2/TCK/INT0/RP3(1)/CN3/RB3
7
8
PGEC2/TMS/EXTREF/RP4(1)/CN4/RB4
9
10
VDD
1
18
VDD
2
17
VSS
AN1/RA1
3
16
PWM1L/RA3
AN2/RA2
4
15
PWM1H/RA4
AN3/RP0(1)/CN0/RB0
5
14
VCAP
OSC1/CLKI/AN6/RP1(1)/CN1/RB1
6
OSC2/CLKO/AN7/RP2(1)/CN2/RB2
PGED2/TCK/INT0/RP3(1)/CN3/RB3
7
8
PGEC2/TMS/RP4(1)/CN4/RB4
9
dsPIC33FJ06GS101A
MCLR
AN0/RA0
13
VSS
12
11
PGEC1/SDA1/RP7(1)/CN7/RB7
10
TDO/RP5(1)/CN5/RB5
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
= Pins are up to 5V tolerant
20-Pin SSOP
20
AVDD
2
19
AVSS
AN1/CMP1B/RA1
3
18
PWM1L/RA3
AN2/CMP1C/CMP2A/RA2
4
PWM1H/RA4
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
5
17
16
VSS
6
15
VCAP
OSCI/CLKI/AN6/RP1(1)/CN1/RB1
OSCO/CLKO/AN7/RP2(1)/CN2/RB2
7
8
14
13
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
MCLR
PGED2/TCK/INT0/RP3(1)/CN3/RB3
(1)
PGEC2/TMS/EXTREF/RP4 /CN4/RB4
VDD
12
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
10
11
TDO/RP5(1)/CN5/RB5
9
1
20
AVDD
2
19
AVSS
AN1/RA1
3
18
PWM1L/RA3
AN2/RA2
4
PWM1H/RA4
AN3/RP0(1)/CN0/RB0
5
17
16
VSS
6
15
VCAP
OSCI/CLKI/AN6/RP1(1)/CN1/RB1
OSCO/CLKO/AN7/RP2(1)/CN2/RB2
7
8
14
13
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED2/TCK/INT0/RP3(1)/CN3/RB3
9
12
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
11
TDO/RP5(1)/CN5/RB5
PGEC2/TMS/RP4 /CN4/RB4
10
dsPIC33FJ06GS101A
MCLR
AN0/RA0
(1)
Note 1:
dsPIC33FJ06GS001
1
AN0/CMP1A/RA0
VDD
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2011-2012 Microchip Technology Inc.
DS75018C-page 3
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
28-Pin SOIC, SPDIP, SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ06GS102A
MCLR
AN0/RA0
AN1/RA1
AN2/RA2
(1)
AN3/RP0 /CN0/RB0
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
VSS
OSC1/CLKI/RP1(1)/CN1/RB1
(1)
OSC2/CLKO/RP2 /CN2/RB2
PGED2/INT0/RP3(1)/CN3/RB3
PGEC2/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
= Pins are up to 5V tolerant
28-Pin SPDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ06GS202A
MCLR
AN0/CMP1A/RA0
AN1/CMP1B/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN4/CMP2C/RP9(1)/CN9/RB9
AN5/CMP2D/RP10(1)/CN10/RB10
VSS
OSC1/CLKI/RP1(1)/CN1/RB1
OSC2/CLKO/RP2(1)/CN2/RB2
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
PGEC2/EXTREF/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin SPDIP, SOIC, SSOP
Note 1:
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VCAP
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15(1)/CN15/RB15
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ09GS302
MCLR
AN0/CMP1A/RA0
AN1/CMP1B1/RA1
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN4/ISRC4/CMP2C/RP9(1)/CN9/RB9
AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10
VSS
OSC1/CLKI/AN6/ISRC2/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/ISRC1/RP2(1)/CN2/RB2
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
PGEC2/EXTREF/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VCAP
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED1/TDI/1SCL1/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15(1)/CN15/RB15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VCAP
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
TDO/RP5(1)/CN5/RB5
PGEC3/RP15/CN15/RB15
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
DS75018C-page 4
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
AN1/RA1
AN0/RA0
MCLR
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
28-Pin QFN-S(2)
28 27 26 25 24 23 22
AN2/RA2
AN3/RP0(1)/CN0/RB0
AN4/RP9(1)/CN9/RB9
AN5/RP10(1)/CN10/RB10
VSS
OSC1/CLKI/RP1(1)/CN1/RB1
OSC2/CLKO/RP2(1)/CN2/RB2
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VCAP
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PWM1L/RA3
PWM1H/RA4
AVDD
AVSS
= Pins are up to 5V tolerant
MCLR
AN1/CMP1B/RA1
28-Pin QFN-S(2)
AN0/CMP1A/RA0
PGED2/INT0/RP3(1)/CN3/RB3
PGEC2/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
PGEC3/RP15(1)/CN15/RB15
TDO/RP5(1)/CN5/RB5
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
1
21
2
20
3
19
4 dsPIC33FJ06GS102A 18
5
17
6
16
7
15
8 9 10 11 12 13 14
28 27 26 25 24 23 22
AN2/CMP1C/CMP2A/RA2
1
21
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
2
20
AN4/CMP2C/RP9(1)/CN9/RB9
3
AN5/CMP2D/RP10(1)/CN10/RB10
VSS
4
OSC1/CLKI/RP1(1)/CN1/RB1
OSC2/CLKO/RP2(1)/CN2/RB2
7
19
TCK/RP12(1)/CN12/RB12
18
TMS/RP11(1)/CN11/RB11
5
17
6
16
VCAP
VSS
15
PGEC1/SDA1/RP7(1)/CN7/RB7
dsPIC33FJ06GS202A
TDO/RP5(1)/CN5/RB5
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
PGEC3/RP15(1)/CN15/RB15
PGED3/RP8(1)/CN8/RB8
9 10 11 12 13 14
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
PGEC2/EXTREF/RP4(1)/CN4/RB4
VDD
8
Note 1:
2:
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2011-2012 Microchip Technology Inc.
DS75018C-page 5
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
28-Pin QFN-S(2)
AN1/CMP1B/RA1
AN0/CMP1A/RA0
MCLR
AVDD
AVSS
PWM1L/RA3
PWM1H/RA4
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
1
2
3
4 dsPIC33FJ09GS302
5
6
7
8 9 10 11 12 13 14
21
20
19
18
17
16
15
PWM2L/RP14(1)/CN14/RB14
PWM2H/RP13(1)/CN13/RB13
TCK/RP12(1)/CN12/RB12
TMS/RP11(1)/CN11/RB11
VCAP
VSS
PGEC1/SDA1/RP7(1)/CN7/RB7
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
PGEC2/EXTREF/RP4(1)/CN4/RB4
VDD
PGED3/RP8(1)/CN8/RB8
PGEC3/RP15(1)/CN15/RB15
TDO/RP5(1)/CN5/RB5
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
AN2/CMP1C/CMP2A/RA2
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN4/ISRC4/CMP2C/RP9(1)/CN9/RB9
AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10
VSS
OSC1/CLKI/AN6/ISRC2/RP1(1)/CN1/RB1
OSC2/CLKO/AN7/ISRC1//RP2(1)/CN2/RB2
Note 1:
2:
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS75018C-page 6
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
36-Pin VTLA
AVDD
AVSS
PWM1L/RA3
RMW1H/RA4
34
AN0/RA0
AN1/RA1
35
MCLR
AN2/RA2
36
33
32
31
30
29
28
27
PWM2L/RP14(1)/CN14/RB14
AN4/RP9(1)/CN9/RB9
1
26
PWM2H/RP13(1)/CN13/RB13
AN5/RP10(1)/CN10/RB10
2
25
TCK/RP12(1)/CN12/RB12
NC
3
24
TMS/RP11(1)/CN11/RB11
NC
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/RP1(1)/CN1/RB1
7
20
N/C
OSCO/CLKO/RP2 /CN2/RB2
8
19
PGEC1/SDA1/RP7(1)/CN7/RB7
NC
9
12
13
14
15
16 17
18
VSS
VDD
PGED3/RP8(1)/CN8/RB8
PGEC3/RP15(1)/CN15/RB15
TDO/RP5(1)/CN5/RB5
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
11
VDD
10
PGEC2/RP4(1)/CN4/RB4
dsPIC33FJ06GS102A
PGED2/INT0/RP3(1)/CN3/RB3
(1)
Note
AN3/RP0(1)/CN0/RB0
= Pins are up to 5V tolerant
1:
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2:
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2011-2012 Microchip Technology Inc.
DS75018C-page 7
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
36-Pin VTLA
Note 1:
2:
RMW1H/RA4
33
PWM1L/RA3
AN0/CMP1A/RA0
34
AVSS
AN1/CMP1B/RA1
35
MCLR
AN2/CMP1C/CMP2A/RA2
36
AVDD
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
= Pins are up to 5V tolerant
32
31
30
29
28
27
PWM2L/RP14(1)/CN14/RB14
AN4/CMP2C/RP9(1)/CN9/RB9
1
26
PWM2H/RP13(1)/CN13/RB13
AN5/CMP2D/RP10(1)/CN10/RB10
2
25
TCK/RP12(1)/CN12/RB12
NC
3
24
TMS/RP11(1)/CN11/RB11
NC
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/RP1(1)/CN1/RB1
7
20
N/C
OSCO/CLKO/RP2(1)/CN2/RB2
8
19
PGEC1/SDA1/RP7(1)/CN7/RB7
NC
9
VSS
VDD
15
16 17
18
PGED1/TDI/SCL1/RP6(1)/CN6/RB6
PGEC2/EXTREF/RP4(1)/CN4/RB4
14
TDO/RP5(1)/CN5/RB5
13
PGEC3/RP15(1)/CN15/RB15
12
VDD
11
PGED3/RP8(1)/CN8/RB8
10
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
dsPIC33FJ06GS202A
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
DS75018C-page 8
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Pin Diagrams (Continued)
36-Pin VTLA
AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0
AN2/CMP1C/CMP2A/RA2
AN1/CMP1B/RA1
AN0/CMP1A/RA0
MCLR
AVDD
AVSS
PWM1L/RA3
RMW1H/RA4
= Pins are up to 5V tolerant
36
35
34
33
32
31 30
29
28
27
PWM2L/RP14(1)/CN14/RB14
1
26
PWM2H/RP13(1)/CN13/RB13
AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10
2
25
TCK/RP12(1)/CN12/RB12
NC
3
24
TMS/RP11(1)/CN11/RB11
NC
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/AN6/ISRC2/RP1(1)/CN1/RB1
7
20
N/C
OSCO/CLKO/AN7/ISRC1/RP2 /CN2/RB2
8
19
PGEC1/SDA1/RP7(1)/CN7/RB7
NC
9
Note 1:
2:
11
12
13
14
15
16
17
18
VSS
VDD
VDD
PGED3/RP8(1)/CN8/RB8
PGEC3/RP15(1)/CN15/RB15
TDO/RP5(1)/CN5/RB5
(1)
PGED1/TDI/SCL1/RP6 /CN6/RB6
10
PGEC2/EXTREF/RP4(1)/CN4/RB4
(1)
dsPIC33FJ09GS302
PGED2/DACOUT/INT0/RP3(1)/CN3/RB3
AN4/ISRC4/CMP2C/RP9(1)/CN9/RB9
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2011-2012 Microchip Technology Inc.
DS75018C-page 9
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers .......................................................................................... 17
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization ................................................................................................................................................................. 37
5.0 Flash Program Memory .............................................................................................................................................................. 75
6.0 Resets ....................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 87
8.0 Oscillator Configuration ......................................................................................................................................................... 123
9.0 Power-Saving Features............................................................................................................................................................ 137
10.0 I/O Ports ................................................................................................................................................................................... 145
11.0 Timer1 ...................................................................................................................................................................................... 173
12.0 Timer2 Features ....................................................................................................................................................................... 175
13.0 Input Capture............................................................................................................................................................................ 177
14.0 Output Compare....................................................................................................................................................................... 179
15.0 High-Speed PWM..................................................................................................................................................................... 183
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 205
17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 211
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 219
19.0 High-Speed 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................. 225
20.0 High-Speed Analog Comparator .............................................................................................................................................. 243
21.0 Constant Current Source.......................................................................................................................................................... 249
22.0 Special Features ...................................................................................................................................................................... 251
23.0 Instruction Set Summary .......................................................................................................................................................... 259
24.0 Development Support............................................................................................................................................................... 267
25.0 Electrical Characteristics .......................................................................................................................................................... 271
26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 315
27.0 Packaging Information.............................................................................................................................................................. 319
Appendix A: Revision History............................................................................................................................................................. 339
Index ................................................................................................................................................................................................. 341
DS75018C-page 10
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2011-2012 Microchip Technology Inc.
DS75018C-page 11
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered the primary reference for the operation of a
particular module or device feature.
Note:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
To access the documents listed below,
visit
the
Microchip
web
site
(www.microchip.com).
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory” (DS70202)
Section 4. “Program Memory” (DS70203)
Section 5. “Flash Programming” (DS70191)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
Section 24. “Programming and Diagnostics” (DS70207)
Section 25. “Device Configuration” (DS70194)
Section 41. “Interrupts (Part IV)” (DS70300)
Section 42. “Oscillator (Part IV)” (DS70307)
Section 43. “High-Speed PWM” (DS70323)
Section 44. “High-Speed 10-Bit ADC” (DS70321)
Section 45. “High-Speed Analog Comparator” (DS70296)
DS75018C-page 12
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features of
the dsPIC33FJ06GS001/101A/102A/202A
and dsPIC33FJ09GS302 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest “dsPIC33F/PIC24H Family
Reference Manual” sections.
The dsPIC33FJ06GS001/101A/102A/202A and
dsPIC33FJ09GS302 devices contain extensive
Digital Signal Processor (DSP) functionality with a
high-performance, 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the devices. Table 1-1 lists the
functions of the various pins shown in the pinout
diagrams.
This document contains device-specific information for
the following dsPIC33F Digital Signal Controller (DSC)
devices:
•
•
•
•
•
dsPIC33FJ06GS001
dsPIC33FJ06GS101A
dsPIC33FJ06GS102A
dsPIC33FJ06GS202A
dsPIC33FJ09GS302
2011-2012 Microchip Technology Inc.
DS75018C-page 13
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 1-1:
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
8
PORTA
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
PORTB
16
23
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program
Memory
EA MUX
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Power-up
Timer
Instruction Reg
Literal Data
Instruction
Decode and
Control
Timing
OSC2/CLKO
OSC1/CLKI Generation
16
16
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
FRC/LPRC
Oscillators
16-Bit ALU
Watchdog
Timer
Voltage
Regulator
VCAP
Note:
16
Brown-out
Reset
VDD, VSS
MCLR
Timer1,2
Constant
Current
Source
UART1
ADC1
OC1
PWM
3x2
Analog
Comparator 1, 2
Reference
Clock
IC1
CNx
I2C1
SPI1
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
DS75018C-page 14
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
Capable
AN0-AN7
I
Analog
No
Analog input channels.
CLKI
I
ST/CMOS
No
CLKO
O
—
No
External clock source input. Always associated with OSC1 pin
function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes. Always associated with OSC2 pin function.
OSC1
I
ST/CMOS
No
OSC2
I/O
—
No
CN0-CN15
I
ST
No
Change notification inputs. Can be software programmed for
internal weak pull-ups on all inputs.
IC1
I
ST
Yes
Capture Input 1.
OCFA
OC1
I
O
ST
—
Yes
Yes
Compare Fault A input (for Compare Channel 1).
Compare Output 1.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
RA0-RA4
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15(1)
I/O
ST
No
PORTB is a bidirectional I/O port.
RP0-RP15(1)
Pin Name
Description
Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC
modes.
I/O
ST
No
Remappable I/O pins.
T1CK
T2CK
I
I
ST
ST
Yes
Yes
Timer1 external clock input.
Timer2 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
I/O
I/O
ST
ST
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
TTL
TTL
TTL
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
I = Input
ST = Schmitt Trigger input with CMOS levels
P = Power
O = Output
TTL = Transistor-Transistor Logic
PPS = Peripheral Pin Select
— = Does not apply
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.
2011-2012 Microchip Technology Inc.
DS75018C-page 15
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
PPS
Capable
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No
No
No
No
No
No
No
No
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A.
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
DACOUT
O
—
No
DAC output voltage.
ACMP1-ACMP2
O
—
Yes
DAC trigger to PWM module.
ISRC1(2)
ISRC2(2)
ISRC3(2)
ISRC4(2)
O
O
O
O
—
—
—
—
No
No
No
No
Constant Current Source Output 1.
Constant Current Source Output 2.
Constant Current Source Output 3.
Constant Current Source Output 4.
EXTREF
I
Analog
No
External voltage reference input for the reference DACs.
REFCLKO
O
—
Yes
REFCLKO output signal is a postscaled derivative of the system
clock.
Pin Name
Description
FLT1-FLT8
I
ST
Yes
Fault inputs to PWM module.
SYNCI1-SYNCI2
SYNCO1
PWM1L
PWM1H
PWM2L
PWM2H
PWM4L
PWM4H
I
O
O
O
O
O
O
O
ST
—
—
—
—
—
—
—
Yes
Yes
No
No
No
No
Yes
Yes
External synchronization signal to PWM master time base.
PWM master time base for external device synchronization.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM4 low output.
PWM4 high output.
PGED1
PGEC1
I/O
I
ST
ST
No
No
PGED2
PGEC2
I/O
I
ST
ST
No
No
PGED3(1)
PGEC3(1)
I/O
I
ST
ST
No
No
Data I/O pin for programming/debugging Communication Channel 1.
Clock input pin for programming/debugging Communication
Channel 1.
Data I/O pin for programming/debugging Communication Channel 2.
Clock input pin for programming/debugging Communication
Channel 2.
Data I/O pin for programming/debugging Communication Channel 3.
Clock input pin for programming/debugging Communication
Channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected
at all times. AVDD is connected to VDD on 18 and 28-pin devices.
AVSS
P
P
No
Ground reference for analog modules. AVSS is connected to VSS
on 18 and 28-pin devices.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
I = Input
ST = Schmitt Trigger input with CMOS levels
P = Power
O = Output
TTL = Transistor-Transistor Logic
PPS = Peripheral Pin Select
— = Does not apply
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.
DS75018C-page 16
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ06GS001/101A/
102A/202A and dsPIC33FJ09GS302 family of 16-bit
Digital Signal Controllers (DSCs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins, regardless if ADC module
is not used
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP™ Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2011-2012 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible;
for example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
DS75018C-page 17
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
R
R1
VSS
VCAP
VDD
10 µF
Tantalum
VDD
MCLR
C
VDD
0.1 µF
Ceramic
VSS
VSS
AVSS
VDD
AVDD
0.1 µF
Ceramic
VDD
0.1 µF
Ceramic
0.1 µF
Ceramic
1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
CNV
------------f = F
2
1 f = --------------------- 2 LC
(i.e., ADC conversion rate/2)
2
1
L = ----------------------
2f C
2.2.1
A low-ESR ( 5.5V; characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit; characterized but not tested.
DS75018C-page 278
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-9:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
IICL
Characteristic
IICT
3:
4:
5:
6:
7:
8:
9:
Units
Conditions
0
—
-5(5,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP and RB5
0
—
+5(6,7,8)
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, RB5 and digital 5V
tolerant designated pins
-20(9)
—
+20(9)
mA
Absolute instantaneous
sum of all ± input
injection currents from
all I/O pins
( | IICL + | IICH | )
IICT
Total Input Injection Current
(sum of all I/O and control pins)
Note 1:
2:
Max.
Input High Injection Current
DI60b
DI60c
Typ.(1)
Input Low Injection Current
DI60a
IICH
Min.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the list of 5V tolerant I/O pins.
VIL source < (VSS – 0.3); characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V; characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit; characterized but not tested.
2011-2012 Microchip Technology Inc.
DS75018C-page 279
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
DO10
DO20
VOL
VOH
DO20A VOH1
Note 1:
Characteristic
Min.
Typ.
Max.
Units
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15
—
—
0.4
V
IOL 6 mA, VDD = 3.3V(1)
Output Low Voltage
I/O Pins:
16x Sink Driver Pins – RA3, RA4,
RB3, RB4, RB11-RB14
—
—
0.4
V
IOL 18 mA, VDD = 3.3V(1)
Output High Voltage
I/O Pins:
4x Source Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15
2.4
—
—
V
IOH -6 mA, VDD = 3.3V(1)
Output High Voltage
I/O Pins:
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
2.4
—
—
V
IOH -18 mA, VDD = 3.3V(1)
Output High Voltage
I/O Pins:
4x Source Driver Pins – RA0-RA2,
RB0-RB2, RB5-RB10, RB15
1.5
—
—
V
IOH -12 mA, VDD = 3.3V(1)
2.0
—
—
IOH -11 mA, VDD = 3.3V(1)
3.0
—
—
IOH -3 mA, VDD = 3.3V(1)
Output High Voltage
I/O Pins:
16x Source Driver Pins – RA3,
RA4, RB3, RB4, RB11-RB14
1.5
—
—
2.0
—
—
IOH -25 mA, VDD = 3.3V(1)
3.0
—
—
IOH -8 mA, VDD = 3.3V(1)
V
Conditions
IOH -30 mA, VDD = 3.3V(1)
These parameters are characterized, but not tested.
TABLE 25-11: ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Param.
Symbol
Standard Operating Conditions: 3.0V to 3.6V(3)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
BOR Event on VDD Transition
High-to-Low
BOR Event is Tied to VDD Core
Voltage Decrease
Min.(1)
Typ.
Max.
Units
2.55
—
2.96
V
Conditions
(See Note 2)
BO10
VBOR
Note 1:
2:
3:
These parameters are for design guidance only and are not tested in manufacturing.
The device will operate as normal until the VDDMIN threshold is reached.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
DS75018C-page 280
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
10,000
—
—
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132B
VPEW
VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated, -40C to +125C
D135
IDDP
Supply Current during
Programming
—
10
—
mA
D137a
TPE
Page Erase Time
20.1
—
26.5
ms
TPE = 168517 FRC cycles,
TA = +85°C(2)
D137b
TPE
Page Erase Time
19.5
—
27.3
ms
TPE = 168517 FRC cycles,
TA = +125°C(2)
D138a
TWW
Word Write Cycle Time
42.3
—
55.9
µs
TWW = 355 FRC cycles,
TA = +85°C(2)
D138b
TWW
Word Write Cycle Time
41.1
—
57.6
µs
TWW = 355 FRC cycles,
TA = +125°C(2)
Note 1:
2:
E/W -40C to +125C
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Other conditions: FRC = 7.37 MHz, TUN = ‘b011111 (for Minimum), TUN = ‘b100000 (for
Maximum). This parameter depends on the FRC accuracy (see Table 25-20) and the value of the FRC
Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.
TABLE 25-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions:
Param.
Symbol
CEFC
Note 1:
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics
External Filter Capacitor
Value(1)
Min.
Typ.
Max.
Units
4.7
10
—
F
Comments
Capacitor must be low
series resistance
(< 0.5 Ohms)
Typical VCAP voltage = 2.5 volts when VDD VDDMIN.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
25.2
AC Characteristics and Timing Parameters
This section defines dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 AC characteristics and timing
parameters.
TABLE 25-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Table 25-1.
AC CHARACTERISTICS
FIGURE 25-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 25-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param. Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
DO50
COSCO
OSC2 Pin
—
—
15
pF
In XT and HS modes when external
clock is used to drive OSC1
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCL1, SDA1
—
—
400
pF
In I2C™ mode
DS75018C-page 282
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
OS30
OS30
Q4
OSC1
OS20
OS31
OS31
OS25
CLKO
OS41
OS40
TABLE 25-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
OS10
FIN
Min.
Typ.(1)
Max.
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz
EC
Oscillator Crystal Frequency
3.0
10
—
—
10
32
MHz
MHz
XT
HS
Characteristic
Conditions
OS20
TOSC
TOSC = 1/FOSC
12.5
—
DC
ns
OS25
TCY
Instruction Cycle Time(2)
25
—
DC
ns
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
—
0.625 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
5.2
—
ns
—
5.2
—
ns
14
16
18
mA/V
Time(3)
OS41
TckF
CLKO Fall
OS42
GM
External Oscillator
Transconductance(4)
Note 1:
2:
3:
4:
VDD = 3.3V
TA = +25ºC
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
mS
-3
0.5
3
%
OS53
DCLK
Note 1:
2:
(2)
CLKO Stability (Jitter)
Conditions
ECPLL, XTPLL modes
Measured over 100 ms
period
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases
or communication clocks use this formula:
D CLK
Peripheral Clock Jitter = ----------------------------------------------------------------------F OSC
------------------------------------------------------------
Peripheral Bit Rate Clock
For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCK) is 2 MHz.
D CLK
3%
3%
SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75%
4
16
MHz-
32
------------------ 2 MHz
TABLE 25-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
OS56
FHPOUT
On-Chip 16x PLL CCO
Frequency
112
118
120
MHz
OS57
FHPIN
On-Chip 16x PLL Phase
Detector Input Frequency
7.0
7.37
7.5
MHz
OS58
TSU
Frequency Generator Lock
Time
—
—
10
µs
Note 1:
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
DS75018C-page 284
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz
(1)
F20a
FRC
-2
—
+2
%
-40°C TA +85°C
VDD = 3.0-3.6V
F20b
FRC
-5
—
+5
%
-40°C TA +125°C
VDD = 3.0-3.6V
Note 1:
Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 25-20: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
LPRC
-20
—
+20
%
-40°C TA +85°C
VDD = 3.0-3.6V
F21b
LPRC
-70
—
+70
%
-40°C TA +125°C
VDD = 3.0-3.6V
Note 1:
The change of LPRC frequency as VDD changes.
2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
DO31
DO32
Symbol
TIOR
TIOF
Min.
Typ.(1)
Max.
Units
I/O Pins: 4x Sink Driver Pins
RA0-RA2, RB0-RB2, RB5-RB10,
RB15
—
10
25
ns
I/O Pins: 16x Sink Driver Pins
RA3, RA4, RB3, RB4, RB11-RB14
—
6
15
ns
I/O Pins: 4x Sink Driver Pins
RA0-RA2, RB0-RB2, RB5-RB10,
RB15
—
10
25
ns
I/O Pins: 16x Sink Driver Pins
RA3, RA4, RB3, RB4, RB11-RB14
—
6
15
ns
Characteristic
DI35
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TCY
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS75018C-page 286
Conditions
Refer to Figure 25-1
for test conditions
Refer to Figure 25-1
for test conditions
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-4:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
PWRT
Time-out
SY11
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.(2)
Max.
Units
Conditions
SY10
TMCL
MCLR Pulse Width (low)
2
—
—
s
-40°C to +125°C
SY11
TPWRT
Power-up Timer Period
—
64
—
ms
-40°C to +125°C
-40°C to +125°C
SY12
TPOR
Power-on Reset Delay
SY13
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
SY30
TOST
Oscillator Start-up Time
Note 1:
2:
3
10
30
s
0.68
0.72
1.2
s
—
1024 TOSC
—
—
TOSC = OSC1 period
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2011-2012 Microchip Technology Inc.
DS75018C-page 287
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-5:
TIMER1 AND TIMER2 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristic
Min.
Typ.
Max.
Units
Synchronous,
no prescaler
TCY + 20
—
—
ns
Synchronous,
with prescaler
(TCY + 20)/N
—
—
ns
Asynchronous
20
—
—
ns
Synchronous,
no prescaler
TCY + 20
—
—
ns
Synchronous,
with prescaler
(TCY + 20)/N
—
—
ns
Asynchronous
20
—
—
ns
2 TCY + 40
—
—
ns
Greater of:
40 ns or
(2 TCY + 40)/N
—
—
—
Asynchronous
40
—
—
ns
T1CK Oscillator Input
Frequency Range
(oscillator enabled by setting
bit, TCS (T1CON))
DC
—
50
kHz
0.75 TCY + 40
—
1.75 TCY + 40
—
TxCK High
Time
TxCK Low
Time
TxCK Input Synchronous,
Period
no prescaler
Synchronous,
with prescaler
OS60
Ft1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
Conditions
Must also meet
Parameter TA15,
N = prescale
value
(1, 8, 64, 256)
Must also meet
Parameter TA15,
N = prescale
value
(1, 8, 64, 256)
N = prescale
value
(1, 8, 64, 256)
Timer1 is a Type A.
DS75018C-page 288
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
TB10
TTXH
TxCK High Time
Synchronous
Greater of:
20 ns or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15
N = prescale
value (1, 8, 64, 256)
TB11
TTXL
TxCK Low Time
Synchronous
Greater of:
20 ns or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15
N = prescale
value (1, 8, 64, 256)
TB15
TTXP
TxCK Input Period Synchronous,
no prescaler
TCY + 40
—
—
ns
N = prescale
value (1, 8, 64, 256)
—
1.5 TCY
—
Synchronous,
with prescaler
TB20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
2011-2012 Microchip Technology Inc.
Greater of:
20 ns or
(TCY + 40)/N
0.5 TCY
DS75018C-page 289
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-6:
INPUT CAPTURE (CAP1) TIMING CHARACTERISTICS
IC1
IC10
IC11
IC15
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Characteristic(1)
Param. Symbol
IC10
TccL
IC1 Input Low Time No prescaler
IC11
TccH
IC1 Input High Time No prescaler
IC15
TccP
IC1 Input Period
Min.
Max.
Units
0.5 TCY + 20
—
ns
With prescaler
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(TCY + 40)/N
—
ns
With prescaler
Note 1:
Conditions
N = prescale value
(1, 4, 16)
These parameters are characterized but not tested in manufacturing.
FIGURE 25-7:
OUTPUT COMPARE MODULE (OC1) TIMING CHARACTERISTICS
OC1
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
Conditions
OC10
TccF
OC1 Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OC1 Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
DS75018C-page 290
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-8:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
Active
OC1
Tri-State
TABLE 25-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ.
Max.
Units
OC15
TFD
Fault Input to PWM I/O
Change
—
—
TCY + 20
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
2011-2012 Microchip Technology Inc.
Conditions
DS75018C-page 291
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-9:
HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTx
MP20
PWMx
FIGURE 25-10:
HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-28: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
MP10
TFPWM
PWM Output Fall Time
—
2.5
—
ns
MP11
TRPWM
PWM Output Rise Time
—
2.5
—
ns
TFD
Fault Input to PWM
I/O Change
—
—
15
ns
TFH
Minimum PWM Fault Pulse
Width
8
—
—
ns
DTC = 10
MP31
TPDLY
Tap Delay
1.04
—
—
ns
ACLK = 120 MHz
MP32
ACLK
PWM Input Clock
—
—
120
MHz
MP20
MP30
Note 1:
2:
3:
See Note 2, Note 3
These parameters are characterized but not tested in manufacturing.
This parameter is a maximum allowed input clock for the PWM module.
The maximum value for this parameter applies to dsPIC33FJ06GS101A/102A/202A/302 devices only.
DS75018C-page 292
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 25-30
—
—
0,1
0,1
0,1
9 MHz
—
Table 25-31
—
1
0,1
1
9 MHz
—
Table 25-32
—
0
0,1
1
15 MHz
—
—
Table 25-33
1
0
0
11 MHz
—
—
Table 25-34
1
1
0
15 MHz
—
—
Table 25-35
0
1
0
11 MHz
—
—
Table 25-36
0
0
0
FIGURE 25-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 293
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
LSb
SP30, SP31
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS75018C-page 294
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP40
SDIx
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
SP20
TscP
TscF
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
9
—
MHz
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
2011-2012 Microchip Technology Inc.
DS75018C-page 295
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SP30, SP31
SDIx
MSb In
LSb
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40ºC to +125ºC and
see Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
TscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
DS75018C-page 296
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-15:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 297
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
DS75018C-page 298
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-16:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 299
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS75018C-page 300
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-17:
SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 301
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
DS75018C-page 302
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 303
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter
DO32 and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter
DO31 and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS75018C-page 304
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-19:
I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCL1
IM31
IM34
IM30
IM33
SDA1
Start
Condition
Stop
Condition
Note: Refer to Figure 25-1 for load conditions.
FIGURE 25-20:
I2C1 BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCL1
IM11
IM26
IM10
IM25
IM33
SDA1
In
IM40
IM40
IM45
SDA1
Out
Note: Refer to Figure 25-1 for load conditions.
2011-2012 Microchip Technology Inc.
DS75018C-page 305
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-37: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Min.(1)
Max.
Units
TLO:SCL Clock Low Time 100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
(2)
TCY/2 (BRG + 1)
—
s
Clock High Time 100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TCY/2 (BRG + 1)
—
s
—
300
ns
20 + 0.1 CB
300
ns
Param. Symbol
IM10
Characteristic
1 MHz mode
IM11
THI:SCL
IM20
TF:SCL
IM21
TR:SCL
IM25
SDA1 and SCL1 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode(2)
—
100
ns
SDA1 and SCL1 100 kHz mode
Rise Time
400 kHz mode
—
1000
ns
TSU:DAT Data Input
Setup Time
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
mode(2)
40
—
ns
100 kHz mode
0
—
s
1 MHz
IM26
THD:DAT Data Input
Hold Time
IM30
TSU:STA
IM31
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
IM33
TSU:STO Stop Condition
Setup Time
IM34
THD:STO Stop Condition
Hold Time
IM40
TAA:SCL
Output Valid
From Clock
400 kHz mode
0
0.9
s
1 MHz mode(2)
0.2
—
s
100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TCY/2 (BRG + 1)
—
s
100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TCY/2 (BRG + 1)
—
s
100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
100 kHz mode
TCY/2 (BRG + 1)
—
ns
400 kHz mode
TCY/2 (BRG + 1)
—
ns
1 MHz mode(2)
TCY/2 (BRG + 1)
—
ns
100 kHz mode
—
3500
ns
400 kHz mode
—
1000
ns
mode(2)
—
400
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(2)
0.5
—
s
1 MHz
IM45
TBF:SDA Bus Free Time
IM50
CB
Bus Capacitive Loading
—
400
pF
IM51
TPGD
Pulse Gobbler Delay
65
390
ns
Note 1:
2:
3:
Conditions
CB is specified to be
from 10 pF to 400 pF
CB is specified to be
from 10 pF to 400 pF
Only relevant for
Repeated Start
condition
After this period the
first clock pulse is
generated
Time the bus must be
free before a new
transmission can start
See Note 3
I2
BRG is the value of the C™ Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit
(I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”.
Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
Typical value for this parameter is 130 ns.
DS75018C-page 306
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 25-21:
I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCL1
IS34
IS31
IS30
IS33
SDA1
Start
Condition
FIGURE 25-22:
Stop
Condition
I2C1 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCL1
IS30
IS26
IS31
IS25
IS33
SDA1
In
IS40
IS40
IS45
SDA1
Out
2011-2012 Microchip Technology Inc.
DS75018C-page 307
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
TABLE 25-38: I2C1 BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
IS10
IS11
IS20
IS21
IS25
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
Characteristic
Clock Low Time
Clock High Time
SDA1 and SCL1
Fall Time
SDA1 and SCL1
Rise Time
Data Input
Setup Time
Min.
Max.
Units
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(2)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
mode(2)
1 MHz
IS26
IS30
IS31
IS33
IS34
IS40
THD:DAT Data Input
Hold Time
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO
Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
TAA:SCL
Output Valid
From Clock
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
1 MHz mode(2)
0
0.3
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(2)
0.25
—
s
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
1 MHz mode(2)
0.25
—
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(2)
0.6
—
s
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(2)
250
100 kHz mode
0
3500
ns
400 kHz mode
0
1000
ns
1 MHz
IS45
IS50
Note 1:
TBF:SDA Bus Free Time
CB
mode(2)
CB is specified to be from
10 pF to 400 pF
CB is specified to be from
10 pF to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
ns
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(2)
0.5
—
s
—
400
pF
Bus Capacitive Loading
Conditions
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).
DS75018C-page 308
2011-2012 Microchip Technology Inc.
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
=
TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V and 3.6V
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS(2)
Param.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
—
—
—
—
AVDD is internally connected
to VDD on 18-pin and 28-pin
devices. See parameters
(DC10) in Table 25-4.
AD02
AVSS
Module VSS Supply
—
—
—
—
AVSS is internally connected to
VSS on 18-pin and 28-pin
devices
AD10
VINH-VINL Full-Scale Input Span
VSS
—
VDD
V
AD11
VIN
AVSS
—
AVDD
V
AD12
IAD
Analog Input
AD13
Absolute Input Voltage
—
Operating Current
—
8
—
mA
Leakage Current
—
±0.6
—
A
VINL = AVSS = 0V,
AVDD = 3.3V,
Source Impedance = 100
RIN
Recommended Impedance
—
—
100
of Analog Voltage Source
DC Accuracy @ 1.5 Msps for 18 and 28-Pin Devices
AD20a
Nr
Resolution
AD21a
INL
Integral Nonlinearity
-0.5
-0.3/+0.5
+1.2
LSb
See Note 3
AD17
10 data bits
AD22a
DNL
Differential Nonlinearity
-0.9
±0.6
+0.9
LSb
See Note 3
AD23a
GERR
Gain Error
—
10
20
LSb
See Note 3
AD24a
EOFF
Offset Error
—
10
20
LSb
See Note 3
—
—
—
—
Guaranteed
AD25a
—
Monotonicity
(1)
DC Accuracy @ 2.0 Msps for 18 and 28-Pin Devices
AD20b
Nr
Resolution
AD21b
INL
Integral Nonlinearity
AD22b
DNL
Differential Nonlinearity
AD23b
GERR
AD24b
EOFF
AD25b
—
10 data bits
-1
±1.5
+2.8
LSb
-1.5
±2
+2.8
LSb
Gain Error
—
10
20
LSb
Offset Error
—
10
20
LSb
Monotonicity(1)
—
—
—
—
Guaranteed
DC Accuracy @ 2.0 Msps for 20 and 36-Pin Devices
AD20c
Nr
Resolution
10 data bits
AD21c
INL
Integral Nonlinearity
> -2
±0.5
-1
±0.5
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