DSPIC33FJ128GP802-E/SO

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 16-bit Digital Signal Controllers (up to 128 KB Flash and 16K SRAM) with Advanced Analog Operating Conditions System Peripherals • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS • 16-bit dual channel 100 ksps Audio DAC • Cyclic Redundancy Check (CRC) module • Up to five 16-bit and up to two 32-bit Timers/ Counters • Up to four Input Capture (IC) modules • Up to four Output Compare (OC) modules • Real-Time Clock and Calendar (RTCC) module Clock Management • • • • • • 2% internal oscillator Programmable PLL and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer Low-power management modes Fast wake-up and start-up Core Performance • Up to 40 MIPS 16-bit dsPIC33F CPU • Single-cycle MUL plus hardware divide Advanced Analog Features • 10/12-bit ADC with 1.1Msps/500 ksps rate: - Up to 13 ADC input channels and four S&H - Flexible/Independent trigger sources • 150 ns Comparators: - Up to two Analog Comparator modules - 4-bit DAC with two ranges for Analog Comparators Input/Output • • • • • Communication Interfaces • Parallel Master Port (PMP) • Two UART modules (10 Mbps) - Supports LIN 2.0 protocols - RS-232, RS-485, and IrDA® support • Two 4-wire SPI modules (15 Mbps) • Enhanced CAN (ECAN) module (1 Mbaud) with 2.0B support • I2C module (100K, 400K and 1Mbaud) with SMbus support • Data Converter Interface (DCI) module with I2S codec support Direct Memory Access (DMA) • 8-channel DMA with no CPU stalls or overhead • UART, SPI, ADC, ECAN, IC, OC, INT0 Qualification and Class B Support Software remappable pin functions 5V-tolerant pins Selectable open drain and internal pull-ups Up to 5 mA overvoltage clamp current/pin Multiple external interrupts • AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) • Class B Safety Library, IEC 60730, VDE certified Debugger Development Support • In-circuit and in-application programming • Two program breakpoints • Trace and run-time watch Packages Type SPDIP SOIC Pin Count 28 28 I/O Pins 21 21 Contact Lead/Pitch .100” 1.27 Dimensions .285x.135x1.365” 7.50x2.05x17.9 Note: All dimensions are in millimeters (mm) unless specified. © 2007-2012 Microchip Technology Inc. QFN-S QFN TQFP 28 21 0.65 6x6x0.9 44 35 0.65 8x8x0.9 44 35 0.80 10x10x1 DS70292G-page 1 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes, and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 CONTROLLER FAMILIES Program Flash Memory (Kbyte) RAM (Kbyte)(1) Remappable Pins 16-bit Timer(2) Input Capture Output Compare Standard PWM Data Converter Interface UART SPI ECAN™ External Interrupts(3) RTCC I2C™ CRC Generator 10-bit/12-bit ADC (Channels) 16-bit Audio DAC (Pins) Analog Comparator (2 Channels/Voltage Regulator) I/O Pins Packages dsPIC33FJ128GP804 44 128 16 26 5 4 4 1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN TQFP dsPIC33FJ128GP802 28 128 16 16 5 4 4 1 2 2 1 3 1 1 1 10 4 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ128GP204 44 128 8 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ128GP202 28 128 8 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ64GP804 44 64 16 26 5 4 4 1 2 2 1 3 1 1 1 13 6 1/1 11 35 QFN TQFP dsPIC33FJ64GP802 28 64 16 16 5 4 4 1 2 2 1 3 1 1 1 10 4 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ64GP204 44 64 8 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ64GP202 28 64 8 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 SPDIP SOIC QFN-S dsPIC33FJ32GP304 44 32 4 26 5 4 4 1 2 2 0 3 1 1 1 13 0 1/1 11 35 QFN TQFP dsPIC33FJ32GP302 28 32 4 16 5 4 4 1 2 2 0 3 1 1 1 10 0 1/0 2 21 Note 1: 2: 3: 8-bit Parallel Master Port (Address Lines) Device Pins Remappable Peripheral SPDIP SOIC QFN-S RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32GP302/304, which include 1 Kbyte of DMA RAM. Only four out of five timers are remappable. Only two out of three interrupts are remappable. DS70292G-page 2 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant 1 28 AVDD 2 27 AVSS AN1/VREF-/CN3/RA1 3 26 AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 25 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 24 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 23 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 4 PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1 5 (1) AN4/C1IN-/RP2 /CN6/RB2 (1) 6 AN5/C1IN+/RP3 /CN7/RB3 7 VSS 8 OSC1/CLKI/CN30/RA2 9 dsPIC33FJ64GP802 dsPIC33FJ128GP802 MCLR AN0/VREF+/CN2/RA0 22 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 21 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 20 VCAP 19 VSS 18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 OSC2/CLKO/CN29/PMA0/RA3 10 SOSCI/RP4(1)/CN1/PMBE/RB4 11 SOSCO/T1CK/CN0/PMA1/RA4 12 VDD 13 16 INT0/RP7(1)/CN23/PMD5/RB7 PGED3/ASDA1/RP5 /CN27/PMD7/RB5 14 15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 (1) 28-Pin SPDIP, SOIC = Pins are up to 5V tolerant 1 28 AVDD 2 27 AVSS AN1/VREF-/CN3/RA1 3 26 AN9/RP15(1)/CN11/PMCS1/RB15 25 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 (1) PGED1/AN2/C2IN-/RP0 /CN4/RB0 (1) PGEC1/ AN3/C2IN+/RP1 /CN5/RB1 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 4 5 6 7 VSS 8 OSC1/CLKI/CN30/RA2 9 AN11/RP13(1)/CN13/PMRD/RB13 23 AN12/RP12(1)/CN14/PMD0/RB12 22 21 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 VCAP 19 VSS 18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 12 17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 13 16 INT0/RP7(1)/CN23/PMD5/RB7 14 15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 10 SOSCI/RP4(1)/CN1/PMBE/RB4 11 SOSCO/T1CK/CN0/PMA1/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 1: 24 20 OSC2/CLKO/CN29/PMA0/RA3 Note dsPIC33FJ32GP302 dsPIC33FJ64GP202 dsPIC33FJ128GP202 MCLR AN0/VREF+/CN2/RA0 The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. © 2007-2012 Microchip Technology Inc. DS70292G-page 3 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 24 23 22 28 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 (1) PGEC1/AN3/C2IN+/RP1 /CN5/RB1 AN4/C1IN-/RP2(1)/CN6/RB2 1 21 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 2 20 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 5 17 VCAP OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 14 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 8 SOSCI/RP4(1)/CN1/PMBE/RB4 SOSCO/T1CK/CN0/PMA1/RA4 VDD 12 13 VSS 10 11 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 9 3 dsPIC33FJ64GP802 19 4 dsPIC33FJ128GP802 18 AN5/C1IN+/RP3(1)/CN7/RB3 Note 27 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR 26 25 = Pins are up to 5V tolerant 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70292G-page 4 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 28-Pin QFN-S(2) AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 24 23 22 AVDD 26 25 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR 28 27 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 = Pins are up to 5V tolerant PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 1 21 AN11/RP13(1)/CN13/PMRD/RB13 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 2 20 AN12/RP12(1)/CN14/PMD0/RB12 AN4/C1IN-/RP2(1)/CN6/RB2 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 VSS 5 dsPIC33FJ128GP202 17 VCAP OSC1/CLKI/CN30/RA2 6 16 VSS OSC2/CLKO/CN29/PMA0/RA3 7 15 TDO/SDA1/RP9(1)/CN21/PMD3/RB9 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 SOSCO/T1CK/CN0/PMA1/RA4 VDD 8 SOSCI/RP4(1)/CN1/PMBE/RB4 Note 14 4 dsPIC33FJ64GP202 18 12 13 AN5/C1IN+/RP3 /CN7/RB3 10 11 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 (1) 9 3 dsPIC33FJ32GP302 19 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2012 Microchip Technology Inc. DS70292G-page 5 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant (1) AN5/C1IN+/RP3 /CN7/RB3 AN6/DAC1RM/RP16(1)/CN8/RC0 AN7/DAC1LM/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 11 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 24 10 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 25 9 26 8 23 27 VDD 28 VSS 29 22 21 20 19 18 17 16 15 14 13 12 AN4/C1IN-/RP2(1)/CN6/RB2 dsPIC33FJ64GP804 dsPIC33FJ128GP804 7 VCAP 6 VSS 5 30 4 31 3 TDO/PMA8/RA8 32 2 33 1 RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 RP20(1)/CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 34 35 36 37 38 39 40 41 42 43 44 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4(1)/CN1/RB4 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/RP10(1)/CN16/PMD2/RB10 Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70292G-page 6 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) AN4/C1IN-/RP2(1)/CN6/RB2 (1) AN5/C1IN+/RP3 /CN7/RB3 23 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant 11 AN11/RP13(1)/CN13/PMRD/RB13 10 AN12/RP12(1)/CN14/PMD0/RB12 25 9 PGEC2/RP11(1)/CN15/PMD1/RB11 26 8 PGED2/RP10(1)/CN16/PMD2/RB10 24 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 27 VDD 28 VSS 29 dsPIC33FJ32GP304 dsPIC33FJ64GP204 dsPIC33FJ128GP204 7 VCAP 6 VSS 5 RP25(1)/CN19/PMA6/RC9 30 4 RP24(1)/CN20/PMA5/RC8 31 3 RP23(1)/CN17/PMA0/RC7 TDO/PMA8/RA8 32 2 RP22(1)/CN18/PMA1/RC6 33 1 SDA1/RP9(1)/CN21/PMD3/RB9 (1) SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 RP20(1)/CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD (1) PGED3/ASDA1/RP5 /CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 SOSCI/RP4 /CN1/RB4 34 35 36 37 38 39 40 41 42 43 44 OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2012 Microchip Technology Inc. DS70292G-page 7 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin TQFP 11 10 9 8 dsPIC33FJ64GP804 7 6 dsPIC33FJ128GP804 5 4 3 2 1 AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13 AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 VCAP VSS RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 34 35 36 37 38 39 40 41 42 43 44 23 24 25 26 27 28 29 30 31 32 33 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 (1) RP20 /CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 AN6/DAC1RM/RP16(1)/CN8/RC0 AN7/DAC1LM/RP17/(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15 AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant Note 1: DS70292G-page 8 The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin TQFP AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 VCAP VSS RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 34 35 36 37 38 39 40 41 42 43 44 11 23 10 24 25 9 8 26 27 dsPIC33FJ32GP304 7 28 dsPIC33FJ64GP204 6 5 29 dsPIC33FJ128GP204 4 30 3 31 2 32 1 33 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 (1) RP20 /CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD (1) PGED3/ASDA1/RP5 /CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 = Pins are up to 5V tolerant Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. © 2007-2012 Microchip Technology Inc. DS70292G-page 9 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Table of Contents dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Product Families............................................. 2 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 19 3.0 CPU............................................................................................................................................................................................ 23 4.0 Memory Organization ................................................................................................................................................................. 35 5.0 Flash Program Memory .............................................................................................................................................................. 71 6.0 Resets ....................................................................................................................................................................................... 77 7.0 Interrupt Controller ..................................................................................................................................................................... 87 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 129 9.0 Oscillator Configuration ............................................................................................................................................................ 141 10.0 Power-Saving Features............................................................................................................................................................ 153 11.0 I/O Ports ................................................................................................................................................................................... 159 12.0 Timer1 ...................................................................................................................................................................................... 189 13.0 Timer2/3 and Timer4/5 Feature ............................................................................................................................................... 193 14.0 Input Capture............................................................................................................................................................................ 199 15.0 Output Compare....................................................................................................................................................................... 203 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 207 17.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 213 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 221 19.0 Enhanced CAN (ECAN™) Module ........................................................................................................................................... 227 20.0 Data Converter Interface (DCI) Module.................................................................................................................................... 255 21.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 263 22.0 Audio Digital-to-Analog Converter (DAC) ................................................................................................................................. 277 23.0 Comparator Module.................................................................................................................................................................. 283 24.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 289 25.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 301 26.0 Parallel Master Port (PMP)....................................................................................................................................................... 307 27.0 Special Features ...................................................................................................................................................................... 315 28.0 Instruction Set Summary .......................................................................................................................................................... 325 29.0 Development Support............................................................................................................................................................... 333 30.0 Electrical Characteristics .......................................................................................................................................................... 337 31.0 High Temperature Electrical Characteristics ............................................................................................................................ 391 32.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 403 33.0 Packaging Information.............................................................................................................................................................. 407 Appendix A: Revision History............................................................................................................................................................. 417 Index .................................................................................................................................................................................................. 427 The Microchip Web Site ..................................................................................................................................................................... 431 Customer Change Notification Service .............................................................................................................................................. 431 Customer Support .............................................................................................................................................................................. 431 Reader Response .............................................................................................................................................................................. 432 Product Identification System............................................................................................................................................................. 433 DS70292G-page 10 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007-2012 Microchip Technology Inc. DS70292G-page 11 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ64GP804 product page of the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • • • • • • • • • • • • • • • • • • • • • • • • • • Section 1. “Introduction” (DS70197) Section 2. “CPU” (DS70204) Section 3. “Data Memory” (DS70202) Section 4. “Program Memory” (DS70203) Section 5. “Flash Programming” (DS70191) Section 8. “Reset” (DS70192) Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) Section 11. “Timers” (DS70205) Section 12. “Input Capture” (DS70198) Section 13. “Output Compare” (DS70209) Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) Section 17. “UART” (DS70188) Section 18. “Serial Peripheral Interface (SPI)” (DS70206) Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) Section 23. “CodeGuard™ Security” (DS70199) Section 24. “Programming and Diagnostics” (DS70207) Section 25. “Device Configuration” (DS70194) Section 30. “I/O Ports with Peripheral Pin Select (PPS)” (DS70190) Section 32. “Interrupts (Part III)” (DS70214) Section 33. “Audio Digital-to-Analog Converter (DAC)” (DS70211) Section 34. “Comparator” (DS70212) Section 35. “Parallel Master Port (PMP)” (DS70299) Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298) Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301) Section 38. “Direct Memory Access (DMA) (Part III)” (DS70215) Section 39. “Oscillator (Part III)” (DS70216) DS70292G-page 12 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. This document contains device specific information for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Digital Signal Controller (DSC) Devices. The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. © 2007-2012 Microchip Technology Inc. DS70292G-page 13 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 1-1: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch DMA RAM 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic PORTB 16 DMA 23 16 Controller 16 Address Generator Units Address Latch Remappable Program Memory Pins EA MUX Data Latch ROM Latch 24 Control Signals to Various Blocks FRC/LPRC Oscillators Divide Support 16 x 16 W Register Array 16 Power-on Reset 16-bit ALU Watchdog Timer 16 Brown-out Reset Voltage Regulator Note: 16 Oscillator Start-up Timer Precision Band Gap Reference VCAP 16 DSP Engine Power-up Timer Timing Generation Instruction Reg Literal Data 16 Instruction Decode and Control OSC2/CLKO OSC1/CLKI PORTC VDD, VSS MCLR PMP/ EPSP Comparator 2 Ch. ECAN1 Timers 1-5 UART1, 2 ADC1 OC/ PWM1-4 RTCC DAC1 SPI1, 2 IC1, 2, 7, 8 CNx I2C1 DCI Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70292G-page 14 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type AN0-AN12 I Analog CLKI I ST/CMOS No CLKO O — No OSC1 I ST/CMOS No OSC2 I/O — No SOSCI SOSCO I O ST/CMOS — No No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. CN0-CN30 I ST No No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 IC7-IC8 I I ST ST Yes Yes Capture inputs 1/2. Capture inputs 7/8. OCFA OC1-OC4 I O ST — Yes Yes Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare outputs 1 through 4. INT0 INT1 INT2 I I I ST ST ST No Yes Yes External interrupt 0. External interrupt 1. External interrupt 2. RA0-RA4 RA7-RA10 I/O I/O ST ST No No PORTA is a bidirectional I/O port. PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC9 I/O ST No PORTC is a bidirectional I/O port. T1CK T2CK T3CK T4CK T5CK I I I I I ST ST ST ST ST No Yes Yes Yes Yes Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. U1CTS U1RTS U1RX U1TX I O I O ST — ST — Yes Yes Yes Yes UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. U2CTS U2RTS U2RX U2TX I O I O ST — ST — Yes Yes Yes Yes UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCK2 SDI2 SDO2 SS2 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Pin Name PPS Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer © 2007-2012 Microchip Technology Inc. Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select DS70292G-page 15 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS SCL1 SDA1 ASCL1 ASDA1 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. TMS TCK TDI TDO I I I O ST ST ST — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. C1RX C1TX I O ST — Yes Yes ECAN1 bus receive pin. ECAN1 bus transmit pin. Pin Name Description RTCC O — No Real-Time Clock Alarm Output. CVREF O ANA No Comparator Voltage Reference Output. C1INC1IN+ C1OUT I I O ANA ANA — No No Yes Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. C2INC2IN+ C2OUT I I O ANA ANA — No No Yes Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. PMA0 I/O TTL/ST No PMA1 I/O TTL/ST No PMA2 -PMPA10 PMBE PMCS1 PMD0-PMPD7 O O O I/O — — — TTL/ST No No No No PMRD PMWR O O — — No No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master Modes). Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe. Parallel Master Port Data (Demultiplexed Master mode) or Address/ Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. DAC1RN DAC1RP DAC1RM O O O — — — No No No DAC1 Right Channel Negative Output. DAC1 Right Channel Positive Output. DAC1 Right Channel Middle Point Value (typically 1.65V). DAC1LN DAC1LP DAC1LM O O O — — — No No No DAC1 Left Channel Negative Output. DAC1 Left Channel Positive Output. DAC1 Left Channel Middle Point Value (typically 1.65V). COFS I/O ST Yes Data Converter Interface frame synchronization pin. CSCK I/O ST Yes Data Converter Interface serial clock input/output pin. CSDI I ST Yes Data Converter Interface serial data input pin CSDO O — Yes Data Converter Interface serial data output pin. PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST No No No No No No Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer DS70292G-page 16 Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS AVSS P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. Vss P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Pin Name Description Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer © 2007-2012 Microchip Technology Inc. Analog = Analog input P = Power O = Output I = Input PPS = Peripheral Pin Select DS70292G-page 17 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 18 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP (see Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2007-2012 Microchip Technology Inc. DS70292G-page 19 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD • Device Reset • Device programming and debugging C dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1Ω and the inductor capacity greater than 10 mA. Where: CNV ------------f = F 2 1 f = ----------------------( 2π LC ) Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: MCLR 0.1 µF Ceramic The placement of this capacitor should be close to the VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 27.2 “On-Chip Voltage Regulator” for details. (i.e., ADC conversion rate/2) During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: VDD 2 1 L = ⎛⎝ ---------------------⎞⎠ ( 2πf C ) 2.2.1 R(1) TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. 2.3 EXAMPLE OF MCLR PIN CONNECTIONS CPU Logic Filter Capacitor Connection (VCAP) JP R1(2) MCLR dsPIC33F C Note 1: R ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, preferably surface mount connected within one-eights inch of the VCAP pin connected to ground. The type can be ceramic or tantalum. Refer to Section 30.0 “Electrical Characteristics” for additional information. DS70292G-page 20 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 2.5 ICSP Pins 2.6 The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. Recommendations for crystals and ceramic resonators are provided in Table 2-1 and Table 2-2, respectively. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. • “Using MPLAB® ICD 3 In-Circuit Debugger” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™” (poster) DS51749 Main Oscillator 13 Guard Ring 14 15 Guard Trace 16 17 Secondary Oscillator 18 19 20 TABLE 2-1: CRYSTAL RECOMMENDATIONS Part Number Vendor Freq. Load Cap. ECS-40-20-4DN ECS Inc. 4 MHz 20 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-80-18-4DN ECS Inc. 8 MHz 18 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-100-18-4-DN ECS Inc. 10 MHz 18 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-200-20-4DN ECS Inc. 20 MHz 20 pF HC49/US ±30 ppm TH -40°C to +85°C ECS-40-20-5G3XDS-TR ECS Inc. 4 MHz 20 pF HC49/US ±30 ppm SM -40°C to +125°C ECS-80-20-5G3XDS-TR ECS Inc. 8 MHz 20 pF HC49/US ±30 ppm SM -40°C to +125°C ECS-100-20-5G3XDS-TR ECS Inc. 10 MHz 20 pF HC49/US ±30 ppm SM -40°C to +125°C ECS-200-20-5G3XDS-TR ECS Inc. 20 MHz 20 pF HC49/US ±30 ppm SM -40°C to 125°C NX3225SA 20MHZ AT-W 20 MHz 8 pF 3.2 mm x 2.5 mm ±50 ppm SM -40°C to 125°C Legend: NDK TH = Through Hole © 2007-2012 Microchip Technology Inc. Package Case Frequency Mounting Tolerance Type Operating Temperature SM = Surface Mount DS70292G-page 21 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 2-2: Part Number RESONATOR RECOMMENDATIONS Vendor Freq. Load Cap. FCR4.0M5T TDK Corp. 4 MHz N/A FCR8.0M5 TDK Corp. 8 MHz HWZT-10.00MD TDK Corp. 10 MHz HWZT-20.00MD TDK Corp. 20 MHz Legend: 2.7 Package Case Frequency Tolerance Mounting Type Operating Temperature Radial ±0.5% TH -40°C to +85°C N/A Radial ±0.5% TH -40°C to +85°C N/A Radial ±0.5% TH -40°C to +85°C N/A Radial ±0.5% TH -40°C to +85°C TH = Through Hole Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤8 MHz for start-up with the PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor between VSS and the unused pin. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the analog-to-digital input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the analog-to-digital pins that are initialized by MPLAB ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. DS70292G-page 22 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 3.1 Overview The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any time. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. There are two classes of instruction in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and © 2007-2012 Microchip Technology Inc. a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the dsPIC33FJ32GP302/ 304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 is shown in Figure 3-2. 3.2 Data Addressing Overview The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data-space mapping feature lets any instruction access program space as if it were data space. 3.3 DSP Engine Overview The DSP engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal realtime performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. DS70292G-page 23 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.4 Special MCU Features The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 8 16 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 16 DMA RAM 16 DMA Controller Address Generator Units Address Latch 16 Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg 16 Literal Data Instruction Decode and Control 16 16 Control Signals to Various Blocks DSP Engine Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70292G-page 24 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 3-2: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/ X04 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand Registers W5 W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer Stack Pointer Limit Register SPLIM AD39 AD15 AD31 AD0 ACCA DSP Accumulators ACCB PC22 PC0 Program Counter 0 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address DOEND DO Loop End Address 22 15 0 Core Configuration Register CORCON OA OB SA SB OAB SAB DA SRH © 2007-2012 Microchip Technology Inc. DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRL DS70292G-page 25 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.5 CPU Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 3.5.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 KEY RESOURCES • • • • • • Section 2. “CPU” (DS70204) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 26 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.6 CPU Control Registers REGISTER 3-1: R-0 OA SR: CPU STATUS REGISTER R-0 R/C-0 R/C-0 OB (1) (1) SA SB R-0 OAB R/C-0 (4) SAB R -0 R/W-0 DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) IPL(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator (Sticky) Status bit(4) 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred Note 1: 2: 3: 4: This bit can be read or cleared (not set). The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. The IPL Status bits are read only when the NSTDIS bit (INTCON1) = 1. This bit can be read or cleared (not set). Clearing this bit clears SA and SB. © 2007-2012 Microchip Technology Inc. DS70292G-page 27 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: 3: 4: This bit can be read or cleared (not set). The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. The IPL Status bits are read only when the NSTDIS bit (INTCON1) = 1. This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70292G-page 28 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 001 = 1 DO loop active 000 = 0 DO loops active SATA: ACCA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: ACCB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops This bit is always read as ‘0’. The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. © 2007-2012 Microchip Technology Inc. DS70292G-page 29 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.7 Arithmetic Logic Unit (ALU) 3.8 DSP Engine The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/ subtracter (with two target accumulators, round and saturation logic). The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG. Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. • • • • • • The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 3.7.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 3.7.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (e.g., ED, EDAC). The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below: Fractional or integer DSP multiply (IF) Signed or unsigned DSP multiply (US) Conventional or convergent rounding (RND) Automatic saturation on/off for ACCA (SATA) Automatic saturation on/off for ACCB (SATB) Automatic saturation on/off for writes to data memory (SATDW) • Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. TABLE 3-1: Instruction DSP INSTRUCTIONS SUMMARY Algebraic Operation CLR A=0 ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC A = (x – y)2 A = A + (x – y)2 A = A + (x • y) A = A + x2 No change in A A=x•y A=x2 A=–x•y A=A–x•y ACC Write Back Yes No No Yes No Yes No No No Yes The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70292G-page 30 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2007-2012 Microchip Technology Inc. DS70292G-page 31 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.8.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1. • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0. • For a 32-bit integer, the data range is 2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF). When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to (1 – 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0 and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations. The MUL instruction can be directed to use byte or word-sized operands. Byte operands direct a 16-bit result, and word operands direct a 32-bit result to the specified registers in the W array. 3.8.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/ subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its preaccumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. 3.8.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented). • In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. DS70292G-page 32 The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. • Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT (CORCON) and ACCSAT (CORCON) mode control bits to determine when and to what value to saturate. Six STATUS register bits support saturation and overflow: • OA: ACCA overflowed into guard bits • OB: ACCB overflowed into guard bits • SA: ACCA saturated (bit 31 overflow and saturation) or ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation) • SB: ACCB saturated (bit 31 overflow and saturation) or ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation) • OAB: Logical OR of OA and OB • SAB: Logical OR of SA and SB The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct the system gain. The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and is saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, the SA and SB bits generate an arithmetic warning trap when saturation is disabled. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators. The device supports three Saturation and Overflow modes: • Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). • Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set. • Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed, and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. 3.8.3 ACCUMULATOR ‘WRITE BACK’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: 3.8.3.1 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). • If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. • If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined: • If it is ‘1’, ACCxH is incremented. • If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.8.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator writeback operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. • W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. • [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). © 2007-2012 Microchip Technology Inc. DS70292G-page 33 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 3.8.3.2 Data Space Write Saturation 3.8.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. • For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. The Most Significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70292G-page 34 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.0 MEMORY ORGANIZATION Note: 4.1 This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70203) of the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. User Memory Space FIGURE 4-1: Program Address Space The program address memory space of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.8 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices is shown in Figure 4-1. PROGRAM MEMORY MAP FOR dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, AND dsPIC33FJ128GPX02/X04 DEVICES dsPIC33FJ32GP302/304 dsPIC33FJ64GPX02/X04 dsPIC33FJ128GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved GOTO Instruction Reset Address Interrupt Vector Table Reserved GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table Alternate Vector Table Alternate Vector Table User Program Flash Memory (11264 instructions) User Program Flash Memory (22016 instructions) User Program Flash Memory (44032 instructions) 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x0057FE 0x005800 0x00ABFE 0x00AC00 Unimplemented (Read ‘0’s) Unimplemented 0x0157FE 0x015800 (Read ‘0’s) Unimplemented (Read ‘0’s) Configuration Memory Space 0x7FFFFE 0x800000 Reserved Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) Reserved Reserved Reserved 0xF7FFFE 0xF80000 0xF80017 0xF80018 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE Note: Memory areas are not shown to scale. © 2007-2012 Microchip Technology Inc. DS70292G-page 35 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. FIGURE 4-2: msw Address least significant word most significant word 16 8 PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) DS70292G-page 36 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. PROGRAM MEMORY ORGANIZATION 23 0x000001 0x000003 0x000005 0x000007 INTERRUPT AND TRAP VECTORS Instruction Width © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2 Data Address Space The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-4. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 4.8.3 “Reading Data from Program Memory Using Program Space Visibility”). dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement up to 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte is returned. 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results in a value of Ws + 1 for byte operations and Ws + 2 for word operations. A data byte read, reads the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007-2012 Microchip Technology Inc. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.3 SFR SPACE The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. Note: 4.2.4 The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer. DS70292G-page 37 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32GP302/304 DEVICES WITH 4 KB RAM MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0000 SFR Space 0x07FF 0x0801 0x07FE 0x0800 X Data RAM (X) 0x0FFE 0x1000 0x0FFF 0x1001 4 Kbyte SRAM Space Y Data RAM (Y) 0x13FE 0x1400 0x13FF 0x1401 0x17FF 0x1801 DMA RAM 0x8001 Optionally Mapped into Program Memory 0x17FE 0x1800 0x8000 X Data Unimplemented (X) 0xFFFF DS70292G-page 38 6 Kbyte Near Data Space 0xFFFE © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ128GP202/204 AND dsPIC33FJ64GP202/ 204 DEVICES WITH 8 KB RAM MSB Address MSB 2 Kbyte SFR Space LSB Address 16 bits LSB 0x0000 0x0001 SFR Space 0x07FE 0x0800 0x07FF 0x0801 8 Kbyte Near Data Space X Data RAM (X) 8 Kbyte SRAM Space 0x17FF 0x1801 0x1FFF 0x2001 0x27FF 0x2801 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 DMA RAM 0x8001 0x27FE 0x2800 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF © 2007-2012 Microchip Technology Inc. 0xFFFE DS70292G-page 39 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/ 804 DEVICES WITH 16 KB RAM MSB Address 16 bits MSB 2 Kbyte SFR Space LSB Address LSB 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x07FE 0x0800 X Data RAM (X) 16 Kbyte SRAM Space 0x1FFF 0x1FFE 0x27FF 0x2801 0x27FE 0x2800 0x3FFF 0x4001 0x47FF 0x4801 8 Kbyte Near Data Space Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x8001 0x47FE 0x4800 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70292G-page 40 0xFFFE © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. 4.2.6 DMA RAM Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 device contains up to 2 Kbytes of dual ported DMA RAM located at the end of Y data space, and is part of Y data space. Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: 4.3 DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. Memory Resources Many useful resources related to Memory Organization are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. 4.3.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 KEY RESOURCES • • • • • • Section 2. “Program Memory” (DS70203) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 41 Special Function Register Maps TABLE 4-1: CPU CORE REGISTERS MAP © 2007-2012 Microchip Technology Inc. SFR Name SFR Addr WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 WREG14 001C Working Register 14 0000 WREG15 001E Working Register 15 0800 SPLIM 0020 Stack Pointer Limit Register xxxx ACCAL 0022 ACCAL xxxx ACCAH 0024 ACCAH ACCAU 0026 ACCBL 0028 ACCBL ACCBH 002A ACCBH ACCBU 002C PCL 002E PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 Repeat Loop Counter Register xxxx DCOUNT 0038 DCOUNT xxxx Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACCAU xxxx xxxx xxxx ACCB ACCBU xxxx Program Counter Low Word Register 003A DOSTARTH 003C DOENDL 003E DOENDH 0040 — — — — — — — — SR 0042 OA OB SA SB OAB SAB DA DC CORCON 0044 — — — US EDT xxxx DOSTARTL — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — SATB xxxx 0 xxxx 00xx DOENDH IPL SATA 0 DOSTARTH DOENDL DL All Resets xxxx ACCA DOSTARTL Legend: Bit 7 SATDW 00xx RA N OV Z C 0000 ACCSAT IPL3 PSV RND IF 0020 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 42 4.4 CPU CORE REGISTERS MAP (CONTINUED) SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 SFR Name Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 BWM Bit 6 Bit 5 YWM XS Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0 xxxx XWM 0000 XMODEND 004A XE 1 xxxx YMODSRT 004C YS 0 xxxx 1 xxxx YMODEND 004E XBREV 0050 BREN DISICNT 0052 — Legend: YE XB — Disable Interrupts Counter Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. xxxx xxxx DS70292G-page 43 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-1: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 CNEN1 0060 CN15IE CN14IE CN13IE — CN30IE CN29IE CNEN2 0062 CNPU1 0068 CNPU2 006A Legend: Bit 11 Bit 10 Bit 9 CN12IE CN11IE — — — CN7IE — CN27IE — — CN24IE CN23IE — — — CN7PUE CN6PUE — — CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — CN30PUE CN29PUE — CN27PUE Bit 8 Bit 7 Bit 6 Bit 0 All Resets CN1IE CN0IE 0000 — CN16IE 0000 CN2PUE CN1PUE CN0PUE 0000 — — CN16PUE 0000 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CN6IE CN5IE CN4IE CN3IE CN2IE CN22IE CN21IE — — — CN5PUE CN4PUE CN3PUE — — CN24PUE CN23PUE CN22PUE CN21PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 CNPU1 0068 CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 CNPU2 006A Legend: CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All Resets © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 44 TABLE 4-2: INTERRUPT CONTROLLER REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI Bit 13 Bit 12 Bit 11 OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 OVATE OVBTE COVTE — — — — — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — 0000 INT1EP INT0EP 0000 IC1IF INT0IF 0000 MI2C1IF SI2C1IF 0000 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — — — — — INT2EP All Resets IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF IC8IF IC7IF — INT1IF CNIF CMIF IFS2 0088 — DMA4IF PMPIF — — — — — — — — DMA3IF C1IF(1) C1RXIF(1) SPI2IF SPI2EIF 0000 IFS3 008A — RTCIF DMA5IF DCIIF DCIEIF — — — — — — — — — — — 0000 IFS4 008C DAC1LIF(2) DAC1RIF(2) — — — — — — — C1TXIF(1) DMA7IF DMA6IF CRCIF U2EIF U1EIF — 0000 IEC0 0094 — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE IC8IE IC7IE — INT1IE CNIE CMIE IEC2 0098 — DMA4IE PMPIE — — — — — — — — DMA3IE C1IE(1) C1RXIE(1) SPI2IE SPI2EIE 0000 IEC3 009A — RTCIE DMA5IE DCIIE DCIEIE — — — — — — — — — — — 0000 IEC4 009C DAC1LIE(2) DAC1RIE(2) — — — — — — — C1TXIE(1) DMA7IE DMA6IE CRCIE U2EIE U1EIE — IPC0 00A4 — IPC1 00A6 IPC2 00A8 IPC3 00AA — IPC4 00AC — IPC5 00AE IPC6 DMA1IE T1IP — OC1IP — — T2IP — U1RXIP — OC2IP — SPI1IP — CNIP — 00B0 IPC7 MI2C1IE SI2C1IE 0000 0000 IC1IP — INT0IP 4444 — IC2IP — DMA0IP 4444 — SPI1EIP — T3IP 4444 DMA1IP — AD1IP — U1TXIP 0444 — CMIP — MI2C1IP — SI2C1IP 4444 IC8IP — IC7IP — — INT1IP 4404 — T4IP — OC4IP — OC3IP — DMA2IP 4444 00B2 — U2TXIP — U2RXIP — INT2IP — T5IP 4444 IPC8 00B4 — C1IP(1) — C1RXIP(1) — SPI2IP — SPI2EIP 4444 IPC9 00B6 — — — — — — DMA3IP IPC11 00BA — — — — — IPC14 00C0 — IPC15 00C2 — IPC16 00C4 — IPC17 00C6 — IPC19 00CA — INTTREG 00E0 — — — — DCIEIP — — — — CRCIP — — — DAC1LIP(2) — — — — — — DMA4IP — — — — — — — U2EIP — C1TXIP(1) DAC1RIP(2) — — ILR> — — — — PMPIP — — — — — — — — — — — — U1EIP — — DMA7IP — — DS70292G-page 45 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Interrupts disabled on devices without ECAN™ modules. Interrupts disabled on devices without Audio DAC modules. — — — 0004 — DMA5IP Note 1: 2: — — RTCIP — — — VECNUM DCIIP — — — 4000 0444 — DMA6IP — 0440 4440 0444 — 4400 4444 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-4: SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 Timer2 Register 0000 TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register 0000 PR2 010C Period Register 2 FFFF PR3 010E Period Register 3 T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS T32 — TCS — 0000 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS — — TCS — 0000 TMR4 0114 Timer4 Register 0000 TMR5HLD 0116 Timer5 Holding Register (for 32-bit timer operations only) xxxx TMR5 0118 Timer5 Register 0000 PR4 011A Period Register 4 FFFF PR5 011C Period Register 5 T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS T32 — TCS — 0000 T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS — — TCS — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM TABLE 4-6: SFR Name SFR Addr TON — TSIDL — — — — — — 0000 FFFF TGATE TCKPS — TSYNC TCS — 0000 FFFF FFFF INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 © 2007-2012 Microchip Technology Inc. IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC7BUF 0158 IC7CON 015A IC8BUF 015C IC8CON 015E Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 6 Bit 5 Input 1 Capture Register — ICTMR xxxx Input 2 Capture Register — — ICSIDL — — — — — ICTMR xxxx Input 7 Capture Register — — ICSIDL — — — — — ICTMR — ICSIDL — — — — — ICTMR 0000 xxxx Input 8Capture Register — 0000 0000 xxxx 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 46 TABLE 4-5: SFR Name OUTPUT COMPARE REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 OC1RS 0180 Output Compare 1 Secondary Register OC1R 0182 Output Compare 1 Register OC1CON 0184 OC2RS 0186 Output Compare 2 Secondary Register OC2R 0188 Output Compare 2 Register OC2CON 018A OC3RS 018C Output Compare 3 Secondary Register OC3R 018E Output Compare 3 Register OC3CON 0190 OC4RS 0192 Output Compare 4 Secondary Register OC4R 0194 Output Compare 4 Register OC4CON 0196 Legend: — — — — — — — — OCSIDL OCSIDL OCSIDL OCSIDL — — — — — — — — — — — — — — — — — — — — — Bit 2 Bit 1 Bit 0 All Resets xxxx — OCFLT OCTSEL OCM 0000 xxxx — OCFLT OCTSEL OCM 0000 xxxx xxxx — — Bit 3 xxxx — — Bit 4 xxxx — — Bit 5 — OCFLT OCTSEL OCM 0000 xxxx xxxx — — OCFLT OCTSEL OCM 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-8: I2C1 REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — Receive Register 0000 I2C1TRN 0202 — — — — — — — — Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 I2C1ADD 020A — — — — — — Address Register 0000 I2C1MSK 020C — — — — — — Address Mask Register 0000 SFR Name Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Baud Rate Generator Register All Resets 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-9: SFR Name Bit 7 SFR Addr UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK DS70292G-page 47 Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U1TXREG 0224 — — — — — — — UTX8 UART Transmit Register xxxx U1RXREG 0226 — — — — — — — URX8 UART Received Register 0000 U1BRG 0228 Legend: URXISEL Baud Rate Generator Prescaler x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PDSEL Bit 0 FERR OERR 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-7: SFR Name SFR Addr UART2 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U2TXREG 0234 — — — — — — — UTX8 UART Transmit Register xxxx U2RXREG 0236 — — — — — — — URX8 UART Receive Register 0000 U2BRG 0238 Legend: Bit 14 Bit 13 SPI1STAT 0240 SPIEN — SPISIDL — — — — SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — SPI1BUF 0248 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — CKE SSEN SPIROV — — CKP MSTEN — — — Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPITBF SPIRBF 0000 SPRE — — PPRE — FRMDLY — SPI1 Transmit and Receive Buffer Register 0000 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: SPI2 REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 SPI2STAT 0260 SPIEN — SPISIDL — — — — SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — SPI2BUF 0268 Legend: 0000 SPI1 REGISTER MAP Bit 15 SFR Name OERR Baud Rate Generator Prescaler SFR Addr Legend: FERR x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-11: SFR Name URXISEL PDSEL Bit 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — CKE SSEN SPIROV — — CKP MSTEN — — — SPI2 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPITBF SPIRBF 0000 SPRE — — PPRE — FRMDLY — 0000 0000 0000 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 48 TABLE 4-10: File Name Addr ADC1BUF0 0300 AD1CON1 0320 AD1CON2 0322 AD1CON3 0324 AD1CHS123 AD1CHS0 ADC1 REGISTER MAP FOR dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 AND dsPIC33FJ32GP302 Bit 15 Bit 14 ADON — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — AD12B FORM — CSCNA CHPS VCFG — — — 0326 — — — 0328 CH0NB — — AD1PCFGL 032C — — — PCFG12 PCFG9 AD1CSSL 0330 — — — CSS12 CSS11 CSS10 CSS9 AD1CON4 0332 — — — — — — — Addr ADC1BUF0 0300 AD1CON1 0320 AD1CON2 0322 AD1CON3 0324 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — SIMSAM ASAM SAMP DONE BUFS BUFM ALTS — — — SMPI ADCS CH123NB CH123SB PCFG11 PCFG10 — 0000 0000 0000 — — — CH0NA — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 — — — — — — CH0SB All Resets xxxx SSRC SAMC — CH123NA CH123SA CH0SA 0000 0000 0000 0000 0000 DMABL AD1CHS123 AD1CHS0 ADC1 REGISTER MAP FOR dsPIC33FJ64GP204/804, dsPIC33FJ128GP204/804 AND dsPIC33FJ32GP304 Bit 15 Bit 14 ADON — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 — AD12B FORM — CSCNA CHPS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — SIMSAM ASAM SAMP DONE BUFM ALTS ADC Data Buffer 0 ADSIDL ADDMABM VCFG — ADRC — — 0326 — — — 0328 CH0NB — — AD1PCFGL 032C — — — PCFG12 PCFG9 AD1CSSL 0330 — — — CSS12 CSS11 CSS10 CSS9 AD1CON4 0332 — — — — — — — Legend: Bit 6 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-14: File Name Bit 7 ADC Data Buffer 0 ADSIDL ADDMABM ADRC Legend: Bit 8 xxxx SSRC BUFS — SMPI SAMC — — ADCS CH123NB CH123SB PCFG11 PCFG10 — 0000 0000 0000 — — — CH0NA — — PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 — — — — — — Bit 3 CH0SB All Resets — CH123NA CH123SA CH0SA 0000 0000 0000 0000 0000 DMABL x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-15: DAC1 REGISTER MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804 SFR Name SFR Addr Bit 15 Bit 14 DAC1CON 03F0 DACEN — DACSIDL AMPON — — — FORM — DAC1STAT 03F2 LOEN — LMVOEN — LITYPE LFULL LEMPTY ROEN Bit 13 Bit 12 — Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — RMVOEN — Bit 2 Bit 1 Bit 0 All Resets RITYPE RFULL REMPTY 0000 DACFDIV — 0000 DS70292G-page 49 DAC1DFLT 03F4 DAC1DFLT 0000 DAC1RDAT 03F6 DAC1RDAT 0000 DAC1LDAT 03F8 DAC1LDAT 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-13: File Name Addr DMA0CON DMA0REQ DMA0STA 0384 DMA REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 0380 CHEN SIZE DIR HALF NULLW — — — — — 0382 FORCE — — — — — — — — Bit 5 Bit 4 AMODE Bit 3 Bit 2 — — Bit 1 Bit 0 MODE IRQSEL All Resets 0000 0000 STA 0000 0000 DMA0STB 0386 STB DMA0PAD 0388 PAD DMA0CNT 038A — — — — — — DMA1CON 038C CHEN SIZE DIR HALF NULLW — — — DMA1REQ 038E FORCE — — — — — — — DMA1STA 0390 0000 CNT — — AMODE — 0000 — — MODE IRQSEL 0000 0000 STA 0000 0000 DMA1STB 0392 STB DMA1PAD 0394 PAD DMA1CNT 0396 — — — — — — DMA2CON 0398 CHEN SIZE DIR HALF NULLW — — — DMA2REQ 039A FORCE — — — — — — — DMA2STA 039C 0000 CNT — — AMODE — 0000 — — MODE IRQSEL 0000 0000 STA 0000 0000 DMA2STB 039E STB DMA2PAD 03A0 PAD DMA2CNT 03A2 — — — — — — DMA3CON 03A4 CHEN SIZE DIR HALF NULLW — — — DMA3REQ 03A6 FORCE — — — — — — — DMA3STA 03A8 0000 CNT — — AMODE — 0000 — — MODE IRQSEL 0000 0000 STA 0000 0000 © 2007-2012 Microchip Technology Inc. DMA3STB 03AA STB DMA3PAD 03AC PAD DMA3CNT 03AE — — — — — — DMA4CON 03B0 CHEN SIZE DIR HALF NULLW — — — DMA4REQ 03B2 FORCE — — — — — — — DMA4STA 03B4 0000 CNT — — AMODE — 0000 — — MODE IRQSEL 0000 0000 STA 0000 0000 DMA4STB 03B6 STB DMA4PAD 03B8 PAD DMA4CNT 03BA — — — — — — DMA5CON 03BC CHEN SIZE DIR HALF NULLW — — — DMA5REQ 03BE FORCE — — — — — — — DMA5STA 03C0 STA 0000 DMA5STB 03C2 STB 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0000 CNT — — — AMODE 0000 — IRQSEL — MODE 0000 0000 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 50 TABLE 4-16: File Name Addr DMA5PAD 03C4 DMA5CNT DMA6CON DMA REGISTER MAP (CONTINUED) Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 03C6 — — — — — — 03C8 CHEN SIZE DIR HALF NULLW — — — DMA6REQ 03CA FORCE — — — — — — — DMA6STA 03CC STA 0000 DMA6STB 03CE STB 0000 DMA6PAD 03D0 PAD DMA6CNT 03D2 PAD — — — — — — 0000 CNT — — AMODE — 0000 — — MODE IRQSEL 0000 0000 0000 CNT 0000 DMA7CON 03D4 CHEN SIZE DIR HALF NULLW — — — — DMA7REQ 03D6 FORCE — — — — — — — — DMA7STA 03D8 STA 0000 DMA7STB 03DA STB 0000 DMA7PAD 03DC PAD DMA7CNT 03DE DMACS0 03E0 DMACS1 03E2 DSADR 03E4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — — — — — — LSTCH AMODE — — MODE IRQSEL 0000 0000 0000 — CNT PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 — — 0000 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0000 DSADR 0000 DS70292G-page 51 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-16: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1CTRL1 0400 — — CSIDL ABAT — C1CTRL2 0402 — — — — — — — — — — Bit 10 Bit 9 Bit 8 Bit 7 — — — — — REQOP — Bit 6 Bit 5 OPMODE — — — — — — — Bit 4 Bit 3 — CANCAP Bit 2 Bit 1 Bit 0 — — WIN DNCNT All Resets 0480 0000 C1VEC 0404 C1FCTRL 0406 C1FIFO 0408 — — C1INTF 040A — — TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF 0000 C1INTE 040C — — — — — — — — IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE 0000 C1EC 040E C1CFG1 0410 DMABS FILHIT — — FBP ICODE — — — — C1CFG2 0412 — WAKFIL — — — C1FEN1 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 0000 FSA FNRB TERRCNT — 0000 0000 RERRCNT — — — SEG2PH FLTEN10 FLTEN9 SJW SEG2PHTS SAM FLTEN7 FLTEN6 FLTEN8 0000 BRP SEG1PH FLTEN5 FLTEN4 0000 PRSEG FLTEN3 FLTEN2 FLTEN1 0000 FLTEN0 FFFF C1FMSKSEL1 0418 F7MSK F6MSK F5MSK F4MSK F3MSK F2MSK F1MSK F0MSK 0000 C1FMSKSEL2 041A F15MSK F14MSK F13MSK F12MSK F11MSK F10MSK F9MSK F8MSK 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: File Name Addr ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 0400041E Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 See definition when WIN = x C1RXFUL1 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 C1RXFUL2 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 RXFUL9 RXFUL8 0000 C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 0000 C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 RXOVF8 RXFUL7 RXOVF7 RXFUL6 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000 © 2007-2012 Microchip Technology Inc. C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI TXEN0 TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI 0000 C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI TXEN2 TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI 0000 C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI TXEN4 TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI 0000 C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI TXEN6 TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI 0000 C1RXD 0440 Received Data Word xxxx C1TXD 0442 Transmit Data Word xxxx Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 52 TABLE 4-17: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0400041E Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x DS70292G-page 53 C1BUFPNT1 0420 F3BP F2BP F1BP F0BP 0000 C1BUFPNT2 0422 F7BP F6BP F5BP F4BP 0000 C1BUFPNT3 0424 F11BP F10BP F9BP F8BP 0000 C1BUFPNT4 0426 F15BP F14BP F13BP F12BP 0000 C1RXM0SID 0430 SID — EID xxxx C1RXM0EID 0432 EID C1RXM1SID 0434 SID — EID xxxx C1RXM1EID 0436 EID C1RXM2SID 0438 SID — EID xxxx C1RXM2EID 043A EID C1RXF0SID 0440 SID — EID xxxx C1RXF0EID 0442 EID C1RXF1SID 0444 SID — EID xxxx C1RXF1EID 0446 EID C1RXF2SID 0448 SID — EID xxxx C1RXF2EID 044A EID C1RXF3SID 044C SID — EID xxxx C1RXF3EID 044E EID C1RXF4SID 0450 SID — EID xxxx C1RXF4EID 0452 EID C1RXF5SID 0454 SID — EID xxxx C1RXF5EID 0456 EID C1RXF6SID 0458 SID — EID xxxx C1RXF6EID 045A EID C1RXF7SID 045C SID — EID xxxx C1RXF7EID 045E EID C1RXF8SID 0460 SID — EID xxxx C1RXF8EID 0462 EID C1RXF9SID 0464 SID — EID xxxx C1RXF9EID 0466 EID C1RXF10SID 0468 SID — EID xxxx — EID xxxx C1RXF10EID 046A EID C1RXF11SID 046C SID Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. SID — MIDE EID SID — SID — SID — SID — SID — SID — SID — SID — SID — SID — SID — SID — SID — SID — MIDE xxxx EID MIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx EID EXIDE xxxx dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-19: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) (CONTINUED) Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 C1RXF11EID 046E EID C1RXF12SID 0470 SID C1RXF12EID 0472 EID C1RXF13SID 0474 SID C1RXF13EID 0476 EID C1RXF14SID 0478 SID C1RXF14EID 047A EID C1RXF15SID 047C SID 047E EID C1RXF15EID Legend: Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EID SID — xxxx EXIDE — EID xxxx — EID xxxx — EID xxxx — EID xxxx EID SID — SID — SID — All Resets xxxx EXIDE EID xxxx EXIDE EID xxxx EXIDE EID xxxx x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-20: SFR Name Bit 10 DCI REGISTER MAP Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 COFSD UNFM CSDOM DJST — — — DCICON1 0280 DCIEN — DCISIDL — DLOOP CSCKD CSCKE DCICON2 0282 — — — — BLEN1 BLEN0 — DCICON3 0284 — — — — DCISTAT 0286 — — — — COFSG — Bit 1 COFSM1 Bit 0 COFSM0 0000 0000 0000 0000 WS 0000 0000 0000 0000 BCG SLOT3 SLOT2 SLOT1 SLOT0 — — — Reset State 0000 0000 0000 0000 — ROV RFUL TUNF TMPTY 0000 0000 0000 0000 © 2007-2012 Microchip Technology Inc. TSCON 0288 TSE15 TSE14 TSE13 TSE12 TSE11 TSE10 TSE9 TSE8 TSE7 TSE6 TSE5 TSE4 TSE3 TSE2 TSE1 TSE0 0000 0000 0000 0000 RSCON 028C RSE15 RSE14 RSE13 RSE12 RSE11 RSE10 RSE9 RSE8 RSE7 RSE6 RSE5 RSE4 RSE3 RSE2 RSE1 RSE0 0000 0000 0000 0000 RXBUF0 0290 Receive Buffer 0 Data Register 0000 0000 0000 0000 RXBUF1 0292 Receive Buffer 1 Data Register 0000 0000 0000 0000 RXBUF2 0294 Receive Buffer 2 Data Register 0000 0000 0000 0000 RXBUF3 0296 Receive Buffer 3 Data Register 0000 0000 0000 0000 TXBUF0 0298 Transmit Buffer 0 Data Register 0000 0000 0000 0000 TXBUF1 029A Transmit Buffer 1 Data Register 0000 0000 0000 0000 TXBUF2 029C Transmit Buffer 2 Data Register 0000 0000 0000 0000 TXBUF3 029E Transmit Buffer 3 Data Register 0000 0000 0000 0000 Legend: — = unimplemented, read as ‘0’. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 54 TABLE 4-19: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 RPINR0 0680 — — — RPINR1 0682 — — — RPINR3 0686 — — — RPINR4 0688 — — RPINR7 068E — RPINR10 0694 — RPINR11 0696 RPINR18 Bit 12 Bit 11 — — Bit 10 Bit 9 Bit 8 — — Bit 2 Bit 1 Bit 0 All Resets — — — 1F00 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — — — — INT2R 001F T3CKR — — — T2CKR 1F1F — T5CKR — — — T4CKR 1F1F — — IC2R — — — IC1R 1F1F — — IC8R — — — IC7R 1F1F — — — — — — OCFAR 001F 06A4 — — — U1CTSR — — — U1RXR 1F1F RPINR19 06A6 — — — U2CTSR — — — U2RXR 1F1F RPINR20 06A8 — — — SCK1R — — — SDI1R 1F1F RPINR21 06AA — — — — — — SS1R 001F RPINR22 06AC — — — — — — SDI2R 1F1F RPINR23 06AE — — — — — — SS2R 001F RPINR24 06B0 — — — RPINR25 06B2 — — RPINR26(1) 06B4 — — Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is present only for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804 INT1R — — — — — — — — — — — SCK2R — — — — — — — — — — — — — — CSDIR 1F1F — — — — — — COFSR 001F — — — — — — C1RXR 001F CSCKR DS70292G-page 55 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-21: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 File Name Addr Bit 15 Bit 14 Bit 13 RPOR0 06C0 — — — RPOR1 06C2 — — RPOR2 06C4 — — RPOR3 06C6 — RPOR4 06C8 RPOR5 06CA RPOR6 06CC RPOR7 Legend: Bit 11 Bit 10 Bit 9 Bit 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 7 Bit 6 Bit 5 RP1R — — — RP0R 0000 — RP3R — — — RP2R 0000 — RP5R — — — RP4R 0000 — — RP7R — — — RP6R 0000 — — — RP9R — — — RP8R 0000 — — — RP11R — — — RP10R 0000 — — — RP13R — — — RP12R 0000 06CE — — — RP15R — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — RP14R 0000 TABLE 4-23: Bit 12 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 File Name Addr Bit 15 Bit 14 Bit 13 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — RPOR3 06C6 — — RPOR4 06C8 — RPOR5 06CA RPOR6 Bit 11 Bit 10 Bit 9 Bit 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets © 2007-2012 Microchip Technology Inc. Bit 7 Bit 6 Bit 5 RP1R — — — RP0R 0000 RP3R — — — RP2R 0000 — RP5R — — — RP4R 0000 — RP7R — — — RP6R 0000 — — RP9R — — — RP8R 0000 — — — RP11R — — — RP10R 0000 06CC — — — RP13R — — — RP12R 0000 RPOR7 06CE — — — RP15R — — — RP14R 0000 RPOR8 06D0 — — — RP17R — — — RP16R 0000 RPOR9 06D2 — — — RP19R — — — RP18R 0000 RPOR10 06D4 — — — RP21R — — — RP20R 0000 RPOR11 06D6 — — — RP23R — — — RP22R 0000 RPOR12 — — — RP25R — 06D8 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — RP24R 0000 Legend: Bit 12 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 56 TABLE 4-22: File Name PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 Addr Bit 15 Bit 14 Bit 13 PMCON 0600 PMPEN — PSIDL PMMODE 0602 BUSY PMADDR PMDOUT1 0604 ADDR15 IRQM Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADRMUX PTBEEN PTWREN PTRDEN INCM MODE16 MODE CS1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000 WAITB WAITM WAITE ADDR 0000 0000 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) PMAEN 060C — PTEN14 — — — — — — — — — — — — PMSTAT 060E IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E Legend: Bit 15 Bit 14 Bit 13 PMCON 0600 PMPEN — PSIDL PMMODE 0602 BUSY PMDOUT1 0000 OB0E 008F PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Addr PMADDR OB1E — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-25: File Name 0000 PTEN 0604 ADDR15 IRQM Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADRMUX PTBEEN PTWREN PTRDEN INCM MODE16 MODE CS1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets CSF1 CSF0 ALP — CS1P BEP WRSP RDSP 0000 WAITB WAITM WAITE ADDR 0000 0000 Parallel Port Data Out Register 1 (Buffers 0 and 1) 0000 PMDOUT2 0606 Parallel Port Data Out Register 2 (Buffers 2 and 3) 0000 PMDIN1 0608 Parallel Port Data In Register 1 (Buffers 0 and 1) 0000 PMPDIN2 060A Parallel Port Data In Register 2 (Buffers 2 and 3) 0000 PMAEN 060C — PTEN14 — — — PMSTAT 060E IBF IBOV — — IB3F Legend: PTEN IB2F — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. IB1F IB0F OBE OBUF — 0000 — OB3E OB2E OB1E OB0E 008F DS70292G-page 57 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-24: File Name Addr REAL-TIME CLOCK AND CALENDAR REGISTER MAP Bit 15 Bit 14 ALRMEN CHIME ALRMVAL 0620 ALCFGRPT 0622 RTCVAL 0624 RCFGCAL 0626 RTCEN — PADCFG1 02FC — — Legend: Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Alarm Value Register Window based on APTR AMASK xxxx ALRMPTR ARPT 0000 RTCC Value Register Window based on RTCPTR RTCWREN RTCSYNC HALFSEC — — RTCOE — xxxx RTCPTR — — CAL — — All Resets — — — — 0000 — RTSECSEL PMPTTL 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-27: File Name Bit 13 CRC REGISTER MAP Bit 15 Bit 14 Bit 13 CRCCON 0640 — — CSIDL CRCXOR 0642 X 0000 CRCDAT 0644 CRC Data Input Register 0000 CRCWDAT 0646 CRC Result Register 0000 Legend: Bit 11 Bit 10 Bit 9 Bit 8 VWORD Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CMCON 0630 CMIDL — C2EVT C1EVT C2EN C1EN C2OUTEN C1OUTEN CVRCON 0632 — — — — — — — — Bit 5 Bit 4 CRCFUL CRCMPT — CRCGO Bit 3 Bit 2 Bit 1 Bit 0 PLEN 0000 Bit 7 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets C2INV C1INV C2NEG C2POS C1NEG C1POS 0000 CVRR CVRSS Bit 6 Bit 5 C2OUT C1OUT CVREN CVROE CVR 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2007-2012 Microchip Technology Inc. TABLE 4-29: File Name Bit 6 DUAL COMPARATOR REGISTER MAP Addr Legend: Bit 7 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-28: File Name Bit 12 All Resets Addr Addr PORTA REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — — — — — — — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 58 TABLE 4-26: File Name Addr PORTA REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 079F PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-31: PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx ODCB 02CE — — — — ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 — — — — — 0000 File Name Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-32: PORTC REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx ODCC 02D6 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. File Name DS70292G-page 59 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 4-30: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) OSCCON 0742 — CLKLOCK IOLOCK LOCK — CF — LPOSCEN OSWEN 0300(2) CLKDIV 0744 ROI PLLFBD 0746 — — OSCTUN 0748 — — — ACLKCON 074A — — SELACLK Legend: Note 1: 2: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 4-34: File Name Addr COSC — DOZE — NOSC DOZEN FRCDIV — — — — — — AOSCMD PLLPOST — — PLLPRE 3040 PLLDIV — — APSTSCLR — — ASRCSEL — 0030 TUN — — — — Bit 3 Bit 2 0000 — — 0000 Bit 1 Bit 0 All Resets SECURITY REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 SSRAM 0752 — — — — — — — — — — — — — IW_ SSR IR_SSR RL_SSR 0000 Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not present in devices with 4K RAM and 32K Flash memory. Bit 2 Bit 1 TABLE 4-35: File Name NVM REGISTER MAP Addr Bit 15 Bit 14 Bit 13 NVMCON 0760 WR WREN WRERR — — — NVMKEY 0766 — — — — — — © 2007-2012 Microchip Technology Inc. Legend: Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — — — ERASE — — — Bit 4 Bit 3 — Bit 0 NVMOP All Resets 0000 NVMKEY 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-36: PMD REGISTER MAP File Name Addr PMD1 0770 PMD2 0772 PMD3 0774 — Legend: Bit 12 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 T5MD T4MD T3MD T2MD T1MD IC8MD IC7MD — — — — — — — All Resets C1MD AD1MD 0000 OC2MD OC1MD 0000 — 0000 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — DCIMD I2C1MD U2MD U1MD SPI2MD SPI1MD — — IC2MD IC1MD — — — — OC4MD OC3MD CMPMD RTCCMD PMPMD CRCMD DAC1MD — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 2 Bit 0 Bit 9 Bit 1 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 60 TABLE 4-33: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.4.1 SOFTWARE STACK 4.4.2 In addition to its use as a working register, the W15 register in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6. For a PC push during any CALL instruction, the MSb of the PC is zeroextended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap does not occur. The stack error trap occurs on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 4-6: Stack Grows Toward Higher Address 0x0000 CALL STACK FRAME 15 W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007-2012 Microchip Technology Inc. The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 4-1 for an overview of the BSRAM and SSRAM SFRs. 4.5 Instruction Addressing Modes The addressing modes shown in Table 4-37 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.5.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.5.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where: Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: 0 PC 000000000 PC DATA RAM PROTECTION FEATURE • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. DS70292G-page 61 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 4-37: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset 4.5.3 The sum of Wn and a literal forms the EA. MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). In summary, the following addressing modes are supported by move and accumulator instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. DS70292G-page 62 4.5.4 MAC INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by the MAC class of instructions: • • • • • Register Indirect Register Indirect Post-Modified by 2 Register Indirect Post-Modified by 4 Register Indirect Post-Modified by 6 Register Indirect with Register Offset (Indexed) 4.5.5 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6 Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can be configured to operate in only one direction as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). 4.6.1 The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.6.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that operate with Modulo Addressing: • If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled. • If YWM = 15, Y AGU Modulo Addressing is disabled. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON. START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1). Note: Y space Modulo Addressing EA calculations assume word-sized data (LSb of every EA is always clear). FIGURE 4-7: MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 0x1163 MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;fill the 50 buffer locations ;fill the next location ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2007-2012 Microchip Technology Inc. DS70292G-page 63 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.6.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers It is important to realize that the address boundaries check for addresses less than or greater than the upper (for incrementing buffers) and lower (for decrementing buffers) boundary addresses (not just equal to). Address changes can, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.7 The modulo corrected effective address is written back to the register only when PreModify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7 + W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged. Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.7.1 XB is the Bit-Reversed Address modifier, or ‘pivot point,’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word-sized data (LSb of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or PostIncrement Addressing and word-sized data writes. It does not function for any other addressing mode or for byte-sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word-sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing assumes priority when active for the X WAGU and X WAGU, Modulo Addressing is disabled. However, Modulo Addressing continues to function in the X RAGU. If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV), a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: • BWM bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing) • The BREN bit is set in the XBREV register • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros. DS70292G-page 64 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point TABLE 4-38: XB = 0x0008 for a 16-Word Bit-Reversed Buffer BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 © 2007-2012 Microchip Technology Inc. DS70292G-page 65 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.8 Interfacing Program and Data Memory Spaces 4.8.1 Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 architecture uses a 24 bit wide program space and a 16 bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). Aside from normal execution, the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 architecture provides two methods by which program space can be accessed during operation: For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-39: Table 4-39 and Figure 4-9 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word. PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User Program Space Address Program Space Visibility (Block Remap/Read) 0xx xxxx xxxx TBLPAG 0xxx xxxx User PC 0 Configuration Note 1: ADDRESSING PROGRAM SPACE 0 xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx TBLPAG Data EA 1xxx xxxx xxxx xxxx xxxx xxxx 0 PSVPAG 0 xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. DS70292G-page 66 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 1 EA 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2007-2012 Microchip Technology Inc. DS70292G-page 67 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.8.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bitwide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D). FIGURE 4-10: - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. The ‘phantom’ byte (D), is always ‘0’. - In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user application and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 0x020000 0x030000 00000000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W 0x800000 DS70292G-page 68 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 4.8.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 0x8000 and higher maps directly into a corresponding program memory address (see Figure 4-11), only the lower 16 bits of the FIGURE 4-11: 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop allows the instruction using PSV to access data, to execute in a single cycle. PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 Data Space 0 0x000000 0x0000 Data EA 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... 0x8000 PSV Area 0x800000 © 2007-2012 Microchip Technology Inc. ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. DS70292G-page 69 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 70 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.0 FLASH PROGRAM MEMORY programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Programming” (DS70191) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 5.1 The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows any of the following devices, dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04, to be serially programmed while in the end application circuit. This is done with two lines for programming clock and FIGURE 5-1: Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter Program Counter 0 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits User/Configuration Space Select © 2007-2012 Microchip Technology Inc. 16 bits 24-bit EA Byte Select DS70292G-page 71 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.2 RTSP Operation The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 30-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. 5.3 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 30-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). Use the formula in Equation 5-1 to calculate the minimum and maximum values for the Row Write Time, Page Erase Time and Word Write Cycle Time parameters (see Table 30-12). EQUATION 5-1: EQUATION 5-2: 11064 Cycles T RW = ------------------------------------------------------------------------------------------------ = 1.435ms 7.37 MHz × ( 1 + 0.05 ) × ( 1 – 0.00375 ) The maximum row write time is equal to Equation 5-3. EQUATION 5-3: Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register 5-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. 5.5 Flash Resources Many useful resources related to Flash memory are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: T --------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy )% × ( FRC Tuning )% 5.5.1 DS70292G-page 72 MAXIMUM ROW WRITE TIME 11064 Cycles T RW = ------------------------------------------------------------------------------------------------ = 1.586ms 7.37 MHz × ( 1 – 0.05 ) × ( 1 – 0.00375 ) PROGRAMMING TIME For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. MINIMUM ROW WRITE TIME In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 KEY RESOURCES • • • • • • Section 5. “Flash Programming” (DS70191) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.6 Flash Control Registers REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — R/W-0(1) U-0 R/W-0(1) R/W-0(1) R/W-0(1) (2) — NVMOP bit 7 bit 0 Legend: SO = Settable only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1110 = Reserved 1101 = Erase General Segment 1100 = Erase Secure Segment 1011 = Reserved 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1110 = Reserved 1101 = No operation 1100 = No operation 1011 = Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: 2: These bits can only be reset on POR. All other combinations of NVMOP are unimplemented. © 2007-2012 Microchip Technology Inc. DS70292G-page 73 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY: Key Register (write-only) bits DS70292G-page 74 x = Bit is unknown © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 5.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 5-1: For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP 6. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR © 2007-2012 Microchip Technology Inc. ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority C2 VIN1 = C2 VIN+ < C2 VIN- Note 1: 2: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. © 2007-2012 Microchip Technology Inc. DS70292G-page 285 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED) bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted bit 3 C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 23-1 for the comparator modes. bit 2 C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 23-1 for the comparator modes. bit 1 C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 23-1 for the comparator modes. bit 0 C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 23-1 for the comparator modes. Note 1: 2: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. DS70292G-page 286 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 23.3 Comparator Voltage Reference 23.3.1 The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). CONFIGURING THE COMPARATOR VOLTAGE REFERENCE The settling time of the comparator voltage reference must be considered when changing the CVREF output. The voltage reference module is controlled through the CVRCON register (Register 23-2). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. VREF+ AVDD COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVRSRC CVRCON CVR3 CVR2 CVR1 CVR0 FIGURE 23-2: 8R CVRSS = 0 R CVREN CVREFIN R R 16-to-1 MUX R 16 Steps R CVREF CVROE (CVRCON) R R CVRR VREFAVSS 8R CVRSS = 1 CVRSS = 0 © 2007-2012 Microchip Technology Inc. DS70292G-page 287 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 23-2: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS R/W-0 R/W-0 R/W-0 R/W-0 CVR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS bit 3-0 CVR: Comparator VREF Value Selection 0 ≤CVR ≤15 bits When CVRR = 1: CVREF = (CVR/ 24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC)+ (CVR/32) • (CVRSRC) DS70292G-page 288 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.0 REAL-TIME CLOCK AND CALENDAR (RTCC) • Time: hours, minutes, and seconds • 24-hour format (military time) • Calendar: weekday, date, month and year Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). • Alarm configurable • Year range: 2000 to 2099 • Leap year correction • BCD format for compact firmware • Optimized for low-power operation • User calibration with auto-adjust • Calibration range: ±2.64 seconds error per month • Requirements: External 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The RTCC module is intended for applications where accurate time must be maintained for extended periods of time with minimum to no intervention from the CPU. The RTCC module is optimized for low-power usage to provide extended battery lifetime while keeping track of time. This chapter discusses the Real-Time Clock and Calendar (RTCC) module, available on dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices, and its operation. The following are some of the key features of this module: FIGURE 24-1: The RTCC module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. The hours are available in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user. RTCC BLOCK DIAGRAM RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator CPU Clock Domain RCFGCAL RTCC Prescalers ALCFGRPT 0.5s RTCVAL RTCC Timer Alarm Event Comparator Compare Registers with Masks ALRMVAL Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE © 2007-2012 Microchip Technology Inc. DS70292G-page 289 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 24.1.1 By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. TABLE 24-2: REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL) to select the desired timer register pair (see Table 24-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. TABLE 24-1: RTCVAL REGISTER MAPPING ALRMPTR RTCVAL RTCVAL 00 MINUTES SECONDS 01 WEEKDAY HOURS 10 MONTH DAY 11 — YEAR ALRMMIN 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 — — 24.1.2 This only applies to read operations and not write operations. WRITE LOCK To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 24-1. SETTING THE RTCWREN BIT #NVMKEY, W1 #0x55, W2 #0xAA, W3 W2, [W1] W3, [W1] RCFGCAL, #13 DS70292G-page 290 ALRMSEC In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL) must be set (refer to Example 24-1). Note: MOV MOV MOV MOV MOV BSET ALRMVAL ALRMVAL 00 Note: The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT) to select the desired Alarm register pair (see Table 24-2). EXAMPLE 24-1: Alarm Value Register Window Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR being decremented. RTCC Value Register Window RTCPTR ALRMVAL REGISTER MAPPING ;move the address of NVMKEY into W1 ;start 55/AA sequence ;set the RTCWREN bit © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.2 RTCC Resources Many useful resources related to RTCC are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 24.2.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 KEY RESOURCES • Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 291 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 24.3 RTCC Registers REGISTER 24-1: R/W-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) U-0 (2) RTCEN — R/W-0 RTCWREN R-0 RTCSYNC R-0 R/W-0 (3) HALFSEC R/W-0 RTCOE R/W-0 RTCPTR bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled bit 9-8 RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. DS70292G-page 292 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-1: bit 7-0 Note 1: 2: 3: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL: RTC Drift Calibration bits 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. © 2007-2012 Microchip Technology Inc. DS70292G-page 293 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE bit (RCFGCAL) needs to be set. DS70292G-page 294 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 ALRMEN CHIME R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMASK R/W-0 ALRMPTR bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 0x00 and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 0x00 to 0xFF 0 = Chime is disabled; ARPT bits stop once they reach 0x00 bit 13-10 AMASK: Alarm Mask Configuration bits 11xx = Reserved – do not use 101x = Reserved – do not use 1001 = Once a year (except when configured for February 29th, once every 4 years) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every 10 minutes 0011 = Every minute 0010 = Every 10 seconds 0001 = Every second 0000 = Every half second bit 9-8 ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC bit 7-0 ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times • • • 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to 0xFF unless CHIME = 1. © 2007-2012 Microchip Technology Inc. DS70292G-page 295 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-4: RTCVAL (WHEN RTCPTR = 11): YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN R/W-x R/W-x YRONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9 bit 3-0 YRONE: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9 Note 1: A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 24-5: RTCVAL (WHEN RTCPTR = 10): MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R-x — — — MTHTEN0 R-x R-x R-x R-x MTHONE bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x DAYTEN R/W-x R/W-x R/W-x DAYONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 bit 11-8 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 bit 3-0 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. DS70292G-page 296 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-6: RTCVAL (WHEN RTCPTR = 01): WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x WDAY bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x HRTEN R/W-x R/W-x R/W-x HRONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 bit 3-0 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 24-7: U-0 RTCVAL (WHEN RTCPTR = 00): MINUTES AND SECONDS VALUE REGISTER R/W-x — R/W-x R/W-x R/W-x MINTEN R/W-x R/W-x R/W-x MINONE bit 15 bit 8 U-0 R/W-x — R/W-x R/W-x R/W-x SECTEN R/W-x R/W-x R/W-x SECONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 bit 11-8 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 bit 3-0 SECONE: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 © 2007-2012 Microchip Technology Inc. DS70292G-page 297 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-8: ALRMVAL (WHEN ALRMPTR = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x — — — MTHTEN0 R/W-x R/W-x R/W-x R/W-x MTHONE bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x R/W-x DAYTEN R/W-x R/W-x DAYONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 bit 11-8 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 bit 3-0 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 24-9: ALRMVAL (WHEN ALRMPTR = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 — — R/W-x R/W-x R/W-x HRTEN R/W-x R/W-x R/W-x HRONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 bit 3-0 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. DS70292G-page 298 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 24-10: ALRMVAL (WHEN ALRMPTR = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x — R/W-x R/W-x R/W-x MINTEN R/W-x R/W-x R/W-x MINONE bit 15 bit 8 U-0 R/W-x — R/W-x R/W-x R/W-x SECTEN R/W-x R/W-x R/W-x SECONE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 bit 11-8 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 bit 3-0 SECONE: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 © 2007-2012 Microchip Technology Inc. DS70292G-page 299 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 300 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR 25.1 The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR bits (X) and the CRCCON bits (PLEN), respectively. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). EQUATION 25-1: x 16 CRC EQUATION +x 12 5 +x +1 To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 25-1. TABLE 25-1: 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. EXAMPLE CRC SETUP Bit Name Bit Value PLEN 1111 X 000100000010000 For the value of X, the 12th bit and the 5th bit are set to ‘1’, as required by the CRC equation. The 0th bit required by the CRC equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X bits do not have the 0th bit or the 16th bit. The programmable CRC generator offers the following features: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO FIGURE 25-1: Overview The topology of a standard CRC generator is shown in Figure 25-2. CRC SHIFTER DETAILS PLEN 0 1 2 15 CRC Shift Register Hold XOR DOUT OUT IN BIT 0 X1 0 1 p_clk Hold OUT IN BIT 1 p_clk X2 0 1 Hold OUT IN BIT 2 X3 X15 0 0 1 1 p_clk Hold OUT IN BIT 15 p_clk CRC Read Bus CRC Write Bus © 2007-2012 Microchip Technology Inc. DS70292G-page 301 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 FIGURE 25-2: XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 p_clk p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus 25.2 25.2.1 User Interface DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN) > 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = ‘bxx Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of VWORD (VWORD) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. DS70292G-page 302 To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter allowed to run until the CRCMPT bit is set. Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 25.2.2 “Interrupt Operation”). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. 25.2.2 INTERRUPT OPERATION When the VWORD bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. 25.3 25.3.1 Operation in Power-Saving Modes SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 25.3.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.4 Programmable CRC Resources Many useful resources related to Programmable CRC are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 25.4.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 KEY RESOURCES • Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools © 2007-2012 Microchip Technology Inc. DS70292G-page 303 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 25.5 Programmable CRC Registers REGISTER 25-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 — — CSIDL R-0 R-0 R-0 R-0 R-0 VWORD bit 15 bit 8 R-0 R-1 U-0 R/W-0 CRCFUL CRCMPT — CRCGO R/W-0 R/W-0 R/W-0 R/W-0 PLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN is greater than 7, or 16 when PLEN is less than or equal to 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as ‘0’ bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = Turn off CRC serial shifter after FIFO is empty bit 3-0 PLEN: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. DS70292G-page 304 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 25-2: R/W-0 CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X U-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’ © 2007-2012 Microchip Technology Inc. x = Bit is unknown DS70292G-page 305 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 306 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Parallel Master Port (PMP)” (DS70299) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Parallel Master Port (PMP) module is a parallel 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory FIGURE 26-1: devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. Key features of the PMP module include: • Fully multiplexed address/data mode • Demultiplexed or partially multiplexed address/ data mode: - Up to 11 address lines with single chip select - Up to 12 address lines without chip select • One Chip Select Line • Programmable Strobe Options - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels PMP MODULE OVERVIEW Address Bus Data Bus dsPIC33F Parallel Master Port PMA PMALL PMA PMALH Control Lines Up to 11-bit Address EEPROM PMA(1) PMA PMCS1 PMBE PMRD PMRD/PMWR PMWR PMENB Microcontroller PMD PMA PMA LCD FIFO Buffer 8-bit Data Note 1: 28-pin devices do not have PMA. © 2007-2012 Microchip Technology Inc. DS70292G-page 307 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.1 PMP Resources Many useful resources related to PMP are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 26.1.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en532311 KEY RESOURCES • Section 35. “Parallel Master Port (PMP)” (DS70299) • Code Samples • Application Notes • Software Libraries • Webinars • All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70292G-page 308 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 26.2 PMP Control Registers REGISTER 26-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) U-0 R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP — CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins, upper 3 bits are multiplexed on PMA 00 = Address and data appear on separate pins bit 10 PTBEEN: Byte Enable Port Enable bit (16-bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip select 0x = PMCS1 functions as address bit 14 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 Unimplemented: Read as ‘0’ bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2007-2012 Microchip Technology Inc. DS70292G-page 309 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS70292G-page 310 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-2: R-0 PMMODE: PARALLEL PORT MODE REGISTER R/W-0 BUSY R/W-0 IRQM R/W-0 R/W-0 INCM R/W-0 R/W-0 MODE16 R/W-0 MODE bit 15 bit 8 R/W-0 R/W-0 R/W-0 WAITB(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITE(1) WAITM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy bit 14-13 IRQM: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 12-11 INCM: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR by 1 every read/write cycle 01 = Increment ADDR by 1 every read/write cycle 00 = No increment or decrement of address bit 10 MODE16: 8-bit/16-bit Mode bit 1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer bit 9-8 MODE: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA and PMD) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA and PMD) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD and PMA) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD) bit 7-6 WAITB: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY • • • 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) bit 1-0 WAITE: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. © 2007-2012 Microchip Technology Inc. DS70292G-page 311 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-3: PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 R/W-0 ADDR15 CS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADDR15: Parallel Port Destination Address bits bit 14 CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive bit 13-0 ADDR13:ADDR0: Parallel Port Destination Address bits REGISTER 26-4: x = Bit is unknown PMAEN: PARALLEL PORT ENABLE REGISTER U-0 R/W-0 U-0 U-0 U-0 — PTEN14 — — — R/W-0 R/W-0 R/W-0 PTEN(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN(1) R/W-0 PTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PTEN14: PMCS1 Strobe Enable bit 1 = PMA14 functions as either PMA bit or PMCS1 0 = PMA14 pin functions as port I/O bit 13-11 Unimplemented: Read as ‘0’ bit 10-2 PTEN: PMP Address Port Enable bits(1) 1 = PMA function as PMP address lines 0 = PMA function as port I/O bit 1-0 PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Note 1: Devices with 28 pins do not have PMA. DS70292G-page 312 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Set bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted © 2007-2012 Microchip Technology Inc. DS70292G-page 313 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 26-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE bit (RCFGCAL) needs to be set. DS70292G-page 314 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.0 SPECIAL FEATURES 27.1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Configuration Bits The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices provide nonvolatile memory implementation for device configuration bits. Refer to Section 25. “Device Configuration” (DS70194), in the “dsPIC33F/PIC24H Family Reference Manual” for more information on this implementation. The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. The individual Configuration bit descriptions for the Configuration registers are shown in Table 27-2. Note that address 0xF80000 is beyond the user program memory space. It belongs to the configuration memory space (0x800000-0xFFFFFF), which can only be accessed using table reads and table writes. The Device Configuration register map is shown in Table 27-1. Flexible configuration Watchdog Timer (WDT) Code Protection and CodeGuard™ Security JTAG Boundary Scan Interface In-Circuit Serial Programming™ (ICSP™) In-Circuit emulation TABLE 27-1: Address DEVICE CONFIGURATION REGISTER MAP Name 0xF80000 FBS 0xF80002 FSS(1) 0xF80004 FGS 0xF80006 FOSCSEL Bit 7 Bit 6 Bit 5 Bit 4 RBS — — RSS — — — — — — IESO — — Bit 3 — 0xF8000A FWDT FWDTEN WINDIS — WDTPRE 0xF8000E FICD Reserved(3) JTAGEN GWRP FNOSC — OSCIOFNC POSCMD WDTPOST ALTI2C — — — 0xF80010 FUID0 User Unit ID Byte 0 0xF80012 FUID1 User Unit ID Byte 1 0xF80014 FUID2 User Unit ID Byte 2 0xF80016 FUID3 User Unit ID Byte 3 Legend: Note 1: 2: 3: SWRP GSS — IOL1WAY Bit 0 BWRP SSS — FCKSM Reserved(2) Bit 1 BSS 0xF80008 FOSC 0xF8000C FPOR Bit 2 FPWRT — ICS — = unimplemented bit, read as ‘0’. This Configuration register is not available and reads as 0xFF on dsPIC33FJ32GP302/304 devices. These bits are reserved and always read as ‘1’. These bits are reserved for use by development tools and must be programmed as ‘1’. © 2007-2012 Microchip Technology Inc. DS70292G-page 315 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection 1 = Boot segment can be written 0 = Boot segment is write-protected BSS FBS Immediate Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security; boot program Flash segment ends at 0x0007FE Boot space is 4K Instruction Words (except interrupt vectors) 101 = Standard security; boot program Flash segment, ends at 0x001FFE 001 = High security; boot program Flash segment ends at 0x001FFE Boot space is 8K Instruction Words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x003FFE 000 = High security; boot program Flash segment ends at 0x003FFE RBS(1) FBS Immediate Boot Segment RAM Code Protection Size 11 = No Boot RAM defined 10 = Boot RAM is 128 bytes 01 = Boot RAM is 256 bytes 00 = Boot RAM is 1024 bytes SWRP(1) FSS(1) Immediate Secure Segment Program Flash Write-Protect bit 1 = Secure Segment can bet written 0 = Secure Segment is write-protected SSS(1) FSS(1) Immediate Secure Segment Program Flash Code Protection Size (Secure segment is not implemented on 32K devices) X11 = No Secure program flash segment Secure space is 4K IW less BS 110 = Standard security; secure program flash segment starts at End of BS, ends at 0x001FFE 010 = High security; secure program flash segment starts at End of BS, ends at 0x001FFE Secure space is 8K IW less BS 101 = Standard security; secure program flash segment starts at End of BS, ends at 0x003FFE 001 = High security; secure program flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 100 = Standard security; secure program flash segment starts at End of BS, ends at 007FFEh 000 = High security; secure program flash segment starts at End of BS, ends at 0x007FFE Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. DS70292G-page 316 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description RSS(1) FSS(1) Immediate Secure Segment RAM Code Protection 11 = No Secure RAM defined 10 = Secure RAM is 256 Bytes less BS RAM 01 = Secure RAM is 2048 Bytes less BS RAM 00 = Secure RAM is 4096 Bytes less BS RAM GSS FGS Immediate General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security 0x = High security GWRP FGS Immediate General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO FOSCSEL Immediate Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source FNOSC FOSCSEL If clock switch is enabled, RTSP effect is on any device Reset; otherwise, Immediate FCKSM FOSC Immediate Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled IOL1WAY FOSC Immediate Peripheral pin select configuration 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSCIOFNC FOSC Immediate OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin POSCMD FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register has no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) WINDIS FWDT Immediate Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. © 2007-2012 Microchip Technology Inc. DS70292G-page 317 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register RTSP Effect Description WDTPRE FWDT Immediate Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST FWDT Immediate Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT FPOR Immediate Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled ALTI2C FPOR Immediate Alternate I2C™ pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/ASCL1 pins JTAGEN FICD Immediate JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS FICD Immediate ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. DS70292G-page 318 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.2 On-Chip Voltage Regulator 27.3 BOR: Brown-out Reset All of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage VCAP. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 Ohms) capacitor (such as tantalum or ceramic) must be connected to the VCAP pin (Figure 27-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 30-13 located in Section 30.1 “DC Characteristics”. A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC and POSCMD). Note: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. On a POR, it takes approximately 20 μs for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. FIGURE 27-1: If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON) is ‘1’. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case is TFSCM. The BOR Status bit (RCON) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1,2,3) 3.3V dsPIC33F VDD VCAP CEFC 10 µF Tantalum VSS Note 1: These are typical operating voltages. Refer to Table 30-13, located in Section 30.1 “DC Characteristics” for the full operating ranges of VDD and VCAP. 2: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. 3: Typical VCAP pin voltage = 2.5V when VDD ≥ VDDMIN. © 2007-2012 Microchip Technology Inc. DS70292G-page 319 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.4 Watchdog Timer (WDT) 27.4.2 For dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 27.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST Configuration bits (FWDT), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any form of device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution Note: SLEEP AND IDLE MODES If the WDT is enabled, it continues to run during Sleep or Idle modes. When the WDT time-out occurs, the device wakes the device and code execution continues from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) needs to be cleared in software after the device wakes up. 27.4.3 ENABLING WDT The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. Note: If the WINDIS bit (FWDT) is cleared, the CLRWDT instruction should be executed by the application software only during the last 1/4 of the WDT period. This CLRWDT window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. The WDT flag, WDTO bit (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. FIGURE 27-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE SWDTEN FWDTEN WDTPOST RS Prescaler (divide by N1) LPRC Clock WDT Wake-up 1 RS Postscaler (divide by N2) 0 WINDIS WDT Reset WDT Window Select CLRWDT Instruction DS70292G-page 320 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 27.5 JTAG Interface dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface is provided in future revisions of the document. Note: 27.6 Refer to Section 24. “Programming and Diagnostics” (DS70207) of the “dsPIC33F/PIC24H Family Reference Manual” for further information on usage, configuration and operation of the JTAG interface. In-Circuit Serial Programming™ (ICSP)™ The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/ X04, and dsPIC33FJ128GPX02/X04 devices can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for details about In-Circuit Serial Programming (ICSP). 27.8 Code Protection and CodeGuard™ Security The dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 devices offer advanced implementation of CodeGuard Security that supports BS, SS and GS while, the dsPIC33FJ32GP302/304 devices offer the intermediate level of CodeGuard Security that supports only BS and GS. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. When coupled with software encryption libraries, CodeGuard Security can be used to securely update Flash even when multiple IPs reside on the single chip. The code protection features vary depending on the actual dsPIC33F implemented. The following sections provide an overview of these features. Secure segment and RAM protection is implemented on the dsPIC33FJ64GPX02/X04 and dsPIC33FJ128GPX02/X04 devices. The dsPIC33FJ32GP302/304 devices do not support secure segment and RAM protection. Note: Refer to Section 23. “CodeGuard™ Security” (DS70199) of the “dsPIC33F/ PIC24H Family Reference Manual” for further information on usage, configuration and operation of CodeGuard Security. Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 27.7 In-Circuit Debugger When MPLAB® ICD 3 is selected as a debugger, the incircuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGC, PGD and the PGECx and PGEDx pin pairs. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 321 CODE FLASH SECURITY SEGMENT SIZES FOR 32 KB DEVICES CONFIG BITS BSS = x11 0K VS = 256 IW SSS = x11 0K GS = 11008 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS = x10 1K VS = 256 IW BS = 768 IW GS = 10240 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS = x01 4K VS = 256 IW BS = 3840 IW GS = 7168 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS = x00 8K VS = 256 IW BS = 7936 IW GS = 3072 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 322 TABLE 27-3: CODE FLASH SECURITY SEGMENT SIZES FOR 64 KB DEVICES CONFIG BITS BSS = x11 0K VS = 256 IW SSS = x11 0K GS = 21760 IW VS = 256 IW SSS = x10 SS = 3840 IW 4K GS = 17920 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh BSS = x10 1K VS = 256 IW BS = 768 IW GS = 20992 IW 0x0157FEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 768 IW SS = 3072 IW GS = 17920 IW SSS = x01 SS = 7936 IW 8K GS = 13824 IW VS = 256 IW DS70292G-page 323 SSS = x00 16K SS = 16128 IW GS = 5632 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 3840 IW GS = 17920 IW VS = 256 IW BS = 768 IW SS = 7168 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh BSS = x00 8K VS = 256 IW BS = 7936 IW GS = 13824 IW VS = 256 IW BS = 3840 IW GS = 17920 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 7936 IW GS = 13824 IW 0x0157FEh VS = 256 IW BS = 3840 IW SS = 4096 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh BSS = x01 4K 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 7936 IW GS = 13824 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x0157FEh 0x0157FEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 768 IW SS = 15360 IW GS = 5632 IW 0x0157FEh VS = 256 IW BS = 3840 IW SS = 12288 IW GS = 5632 IW 0x0157FEh VS = 256 IW BS = 7936 IW SS = 8192 IW GS = 5632 IW 0x0157FEh dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. TABLE 27-4: CODE FLASH SECURITY SEGMENT SIZES FOR 128 KB DEVICES CONFIG BITS BSS = x11 0K VS = 256 IW SSS = x11 0K GS = 43776 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h BSS = x10 1K VS = 256 IW BS = 768 IW GS = 43008 IW SSS = x10 SS = 3840 IW 4K GS = 39936 IW VS = 256 IW SSS = x01 SS = 7936 IW 8K © 2007-2012 Microchip Technology Inc. GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh VS = 256 IW BS = 768 IW SS = 3072 IW GS = 39936 IW SSS = x00 16K SS = 16128 IW GS = 27648 IW BS = 3840 IW GS = 39936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h VS = 256 IW BS = 3840 IW GS = 39936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x0157FEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h VS = 256 IW BS = 768 IW SS = 7168 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 3840 IW SS = 4096 IW GS = 35840 IW BS = 768 IW SS = 15360 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW VS = 256 IW BS = 3840 IW SS = 12288 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW 0x0157FEh 0x0157FEh VS = 256 IW BSS = x00 8K 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW VS = 256 IW 0x0157FEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h BSS = x01 4K 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW SS = 8192 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 324 TABLE 27-5: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest reference manual sections. The dsPIC33F instruction set is identical to that of the dsPIC30F. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: • • • • • Word or byte-oriented operations Bit-oriented operations Literal operations DSP operations Control operations Table 28-1 shows the general symbols used in describing the instructions. The dsPIC33F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) The literal instructions that involve data movement can use some of the following operands: • A literal value to be loaded into a W register or file register (specified by ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The MAC class of DSP instructions can use some of the following operands: • The accumulator (A or B) to be used (required operand) • The W registers to be used as the two operands • The X and Y address space prefetch operations • The X and Y address space prefetch destinations • The accumulator write back destination The other DSP instructions do not involve any multiplication and can include: • The accumulator to be used (required) • The source or destination operand (designated as Wso or Wdo, respectively) with or without an address modifier • The amount of shift specified by a W register ‘Wn’ or a literal value The control instructions can use some of the following operands: • A program memory address • The mode of the table read and table write instructions • The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007-2012 Microchip Technology Inc. DS70292G-page 325 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Most instructions are a single word. Certain doubleword instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it executes as a NOP. The double-word instructions execute in two instruction cycles. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA TABLE 28-1: (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). SYMBOLS USED IN OPCODE DESCRIPTIONS Field #text Description Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” {} Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) Acc One of two accumulators {A, B} AWB Accumulator write back destination address register ∈ {W13, [W13]+ = 2} bit4 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address ∈ {0x0000...0x1FFF} lit1 1-bit unsigned literal ∈ {0,1} lit4 4-bit unsigned literal ∈ {0...15} lit5 5-bit unsigned literal ∈ {0...31} lit8 8-bit unsigned literal ∈ {0...255} lit10 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal ∈ {0...16384} lit16 16-bit unsigned literal ∈ {0...65535} lit23 23-bit unsigned literal ∈ {0...8388608}; LSb must be ‘0’ None Field does not require an entry, can be blank OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate PC Program Counter Slit10 10-bit signed literal ∈ {-512...511} Slit16 16-bit signed literal ∈ {-32768...32767} Slit6 6-bit signed literal ∈ {-16...16} Wb Base W register ∈ {W0...W15} Wd Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) DS70292G-page 326 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 working registers ∈ {W0...W15} Wnd One of 16 destination working registers ∈ {W0...W15} Wns One of 16 source working registers ∈ {W0...W15} WREG W0 (working register used in file register instructions) Ws Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } Wx X data space prefetch address register for DSP instructions ∈ {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2, [W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2, [W9 + W12], none} Wxd X data space prefetch destination register for DSP instructions ∈ {W4...W7} Wy Y data space prefetch address register for DSP instructions ∈ {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2, [W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2, [W11 + W12], none} Wyd Y data space prefetch destination register for DSP instructions ∈ {W4...W7} © 2007-2012 Microchip Technology Inc. DS70292G-page 327 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z OA,OB,SA,SB ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z AND f f = f .AND. WREG 1 1 N,Z AND f,WREG WREG = f .AND. WREG 1 1 N,Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z f,#bit4 Bit Clear f 1 1 None None 5 BCLR BCLR BCLR Ws,#bit4 Bit Clear Ws 1 1 6 BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if greater than or equal 1 1 (2) None BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2) None BRA GT,Expr Branch if greater than 1 1 (2) None BRA GTU,Expr Branch if unsigned greater than 1 1 (2) None BRA LE,Expr Branch if less than or equal 1 1 (2) None BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2) None BRA LT,Expr Branch if less than 1 1 (2) None BRA LTU,Expr Branch if unsigned less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OA,Expr Branch if Accumulator A overflow 1 1 (2) None BRA OB,Expr Branch if Accumulator B overflow 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None 7 8 9 BSET BSW BTG BRA SA,Expr Branch if Accumulator A saturated 1 1 (2) None BRA SB,Expr Branch if Accumulator B saturated 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws 1 1 None BSW.Z Ws,Wb Write Z bit to Ws 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None DS70292G-page 328 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z 14 CALL CALL lit23 Call subroutine 2 2 None CALL Wn Call indirect subroutine 1 2 None 15 CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB 16 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep 17 COM COM f f=f 1 1 N,Z COM f,WREG WREG = f 1 1 N,Z COM Ws,Wd Wd = Ws 1 1 N,Z CP f Compare f with WREG 1 1 C,DC,N,OV,Z CP Wb,#lit5 Compare Wb with lit5 1 1 C,DC,N,OV,Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C,DC,N,OV,Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb – Ws – C) 1 1 C,DC,N,OV,Z 18 19 20 CP CP0 CPB 21 CPSEQ CPSEQ Wb, Wn Compare Wb with Wn, skip if = 1 1 (2 or 3) None 22 CPSGT CPSGT Wb, Wn Compare Wb with Wn, skip if > 1 1 (2 or 3) None 23 CPSLT CPSLT Wb, Wn Compare Wb with Wn, skip if < 1 1 (2 or 3) None 24 CPSNE CPSNE Wb, Wn Compare Wb with Wn, skip if ≠ 1 1 (2 or 3) None 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z DEC2 f f=f–2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None 27 28 DEC2 DISI © 2007-2012 Microchip Technology Inc. DS70292G-page 329 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV None 30 DIVF DIVF 31 DO DO #lit14,Expr Do code to PC + Expr, lit14 + 1 times 2 2 DO Wn,Expr Do code to PC + Expr, (Wn) + 1 times 2 2 None Wm,Wn 32 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB, SA,SB,SAB 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB, SA,SB,SAB 34 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None 35 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C 36 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C 37 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C 38 GOTO GOTO Expr Go to address 2 2 None GOTO Wn Go to indirect 1 2 None INC f f=f+1 1 1 C,DC,N,OV,Z INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z C,DC,N,OV,Z 39 40 41 INC INC2 IOR INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C,DC,N,OV,Z INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z C,DC,N,OV,Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N,Z IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z OA,OB,OAB, SA,SB,SAB 42 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 43 LNK LNK #lit14 Link Frame Pointer 1 1 None 44 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd , AWB Multiply and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB, SA,SB,SAB MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 None 45 46 47 MAC MOV MOVSAC MOV f,WREG Move f to WREG 1 1 N,Z MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f None Move WREG to f 1 1 MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None Prefetch and store accumulator 1 1 None MOVSAC DS70292G-page 330 Acc,Wx,Wxd,Wy,Wyd,AWB © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None 50 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd , AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 51 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG Acc Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB C,DC,N,OV,Z 52 53 54 NEG NOP POP NEG f f=f+1 1 1 NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z NOP No Operation 1 1 None NOPR No Operation 1 1 None POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) 1 2 None Pop Shadow Registers 1 1 All f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack (TOS) 1 2 None POP.S 55 PUSH PUSH Push Shadow Registers 1 1 None Go into Sleep or Idle mode 1 1 WDTO,Sleep Expr Relative Call 1 2 None Wn Computed Call 1 2 None REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None PUSH.S 56 PWRSAV PWRSAV 57 RCALL RCALL RCALL 58 REPEAT #lit1 59 RESET RESET Software device Reset 1 1 None 60 RETFIE RETFIE Return from interrupt 1 3 (2) None 61 RETLW RETLW Return with literal in Wn 1 3 (2) None 62 RETURN RETURN Return from Subroutine 1 3 (2) None 63 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z RLNC f f = Rotate Left (No Carry) f 1 1 N,Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z RRC f f = Rotate Right through Carry f 1 1 C,N,Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z 64 65 RLNC RRC #lit10,Wn © 2007-2012 Microchip Technology Inc. DS70292G-page 331 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 28-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z None 68 SE SE 69 SETM SETM f f = 0xFFFF 1 1 SETM WREG WREG = 0xFFFF 1 1 None SETM Ws Ws = 0xFFFF 1 1 None SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB, SA,SB,SAB SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB, SA,SB,SAB SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z SUB Acc Subtract Accumulators 1 1 OA,OB,OAB, SA,SB,SAB SUB f f = f – WREG 1 1 C,DC,N,OV,Z SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z 70 71 72 73 74 75 76 SFTAC SL SUB SUBB SUBR SUBBR SWAP SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z SUBR f f = WREG – f 1 1 C,DC,N,OV,Z SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z C,DC,N,OV,Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z C,DC,N,OV,Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 SWAP.b Wn Wn = nibble swap Wn 1 1 None SWAP Wn Wn = byte swap Wn 1 1 None 77 TBLRDH TBLRDH Ws,Wd Read Prog to Wd 1 2 None 78 TBLRDL TBLRDL Ws,Wd Read Prog to Wd 1 2 None 79 TBLWTH TBLWTH Ws,Wd Write Ws to Prog 1 2 None 80 TBLWTL TBLWTL Ws,Wd Write Ws to Prog 1 2 None 81 ULNK ULNK Unlink Frame Pointer 1 1 None 82 XOR XOR f f = f .XOR. WREG 1 1 N,Z XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N 83 ZE DS70292G-page 332 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.0 DEVELOPMENT SUPPORT ® ® The PIC microcontrollers and dsPIC digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 29.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2007-2012 Microchip Technology Inc. DS70292G-page 333 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 29.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 29.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 29.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 29.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process DS70292G-page 334 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 29.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2007-2012 Microchip Technology Inc. 29.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 29.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP)™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. DS70292G-page 335 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 29.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 29.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 29.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70292G-page 336 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 electrical characteristics. Additional information is provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(4) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(4) ...................................................... -0.3V to 3.6V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2) ...........................................................................................................................250 mA Maximum current sourced/sunk by any 2x I/O pin(3) ................................................................................................8 mA Maximum current sourced/sunk by any 4x I/O pin(3) ..............................................................................................15 mA Maximum current sourced/sunk by any 8x I/O pin(3) ..............................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(2) ...............................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx and PGEDx pins, which are able to sink/source 12 mA. 4: See the “Pin Diagrams” section for 5V tolerant pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 337 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.1 DC Characteristics TABLE 30-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temp Range (in °C) dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. Refer to parameter BO10 in Table 30-11 for the minimum and maximum BOR values. TABLE 30-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +125 °C Industrial Temperature Devices Extended Temperature Devices Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD – Σ IOH) PD PINT + PI/O W PDMAX (TJ – TA)/θJA W I/O Pin Power Dissipation: I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Package Thermal Resistance, 44-pin QFN Package Thermal Resistance, 44-pin TFQP Package Thermal Resistance, 28-pin SPDIP Package Thermal Resistance, 28-pin SOIC Package Thermal Resistance, 28-pin QFN-S Note 1: Symbol Typ Max Unit Note θJA θJA θJA θJA θJA 30 — °C/W 1 40 — °C/W 1 45 — °C/W 1 50 — °C/W 1 30 — °C/W 1 Junction to ambient thermal resistance, Theta-JA (θ JA) numbers are achieved by package simulations. DS70292G-page 338 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 Supply Voltage VDD — 3.0 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.8 — — V — DC16 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — — VSS V — DC17 SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.03 — — Note 1: 2: Industrial and Extended V/ms 0-3.0V in 0.1s Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. This is the limit to which VDD can be lowered without losing RAM data. © 2007-2012 Microchip Technology Inc. DS70292G-page 339 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No.(3) Typical(2) Max Units Conditions Operating Current (IDD)(1) DC20d 18 21 mA -40°C DC20a 18 22 mA +25°C DC20b 18 22 mA +85°C DC20c 18 25 mA +125°C DC21d 30 35 mA -40°C DC21a 30 34 mA +25°C DC21b 30 34 mA +85°C DC21c 30 36 mA +125°C DC22d 34 42 mA -40°C DC22a 34 41 mA +25°C DC22b 34 42 mA +85°C DC22c 35 44 mA +125°C DC23d 49 58 mA -40°C DC23a 49 57 mA +25°C DC23b 49 57 mA +85°C DC23c 49 60 mA +125°C DC24d 63 75 mA -40°C DC24a 63 74 mA +25°C DC24b 63 74 mA +85°C 63 76 mA +125°C DC24c Note 1: 2: 3: 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: • Oscillator is configured in EC mode, no PLL until 10 MIPS, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • CPU, SRAM, program memory and data memory are operational • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero) • CPU executing while(1) statement • JTAG is disabled Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. These parameters are characterized but not tested in manufacturing. DS70292G-page 340 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No.(3) Typical(2) Max Units Conditions Idle Current (IIDLE): Core OFF Clock ON Base Current(1) DC40d 8 10 mA -40°C DC40a 8 10 mA +25°C DC40b 9 10 mA +85°C DC40c 10 13 mA +125°C DC41d 13 15 mA -40°C DC41a 13 15 mA +25°C DC41b 13 16 mA +85°C DC41c 13 19 mA +125°C DC42d 15 18 mA -40°C DC42a 16 18 mA +25°C DC42b 16 19 mA +85°C DC42c 17 22 mA +125°C DC43a 23 27 mA +25°C DC43d 23 26 mA -40°C DC43b 24 28 mA +85°C DC43c 25 31 mA +125°C DC44d 31 42 mA -40°C DC44a 31 36 mA +25°C DC44b 32 39 mA +85°C 34 43 mA +125°C DC44c Note 1: 2: 3: 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS Base IIDLE current is measured as follows: • CPU core is off (i.e., Idle mode), oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • External Secondary Oscillator disabled (i.e., SOSCO and SOSCI pins configured as digital I/O inputs) • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled • No peripheral modules are operating; however, every peripheral is being clocked (defined PMDx bits are set to zero) • JTAG is disabled Data in “Typ” column is at 3.3V, +25ºC unless otherwise stated. These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 341 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No.(3) Typical(2) Max Units Conditions 68 μA -40°C Power-Down Current (IPD)(1) DC60d 24 DC60a 28 87 μA +25°C DC60b 124 292 μA +85°C DC60c 350 1000 μA +125°C DC61d 8 13 μA -40°C DC61a 10 15 μA +25°C DC61b 12 20 μA +85°C 13 25 μA +125°C DC61c Note 1: 2: 3: 4: 5: 3.3V Base Power-Down Current(3,4) 3.3V Watchdog Timer Current: ΔIWDT(3,5) IPD (Sleep) current is measured as follows: • CPU core is off (i.e., Sleep mode), oscillator is configured in EC mode and external clock active, OSC1 is driven with external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required) • CLKO is configured as an I/O input pin in the Configuration word • All I/O pins are configured as inputs and pulled to VSS • MCLR = VDD, WDT and FSCM are disabled, all peripheral modules are disabled (PMDx bits are all ‘1’s) • RTCC is disabled • JTAG is disabled Data in the “Typ” column is at 3.3V, +25ºC unless otherwise stated. The Watchdog Timer Current is the additional current consumed when the WDT module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. These parameters are characterized, but are not tested in manufacturing. DS70292G-page 342 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Doze Ratio Units 50 1:2 mA 30 1:64 mA Parameter No. Typical(1) Max DC73a 20 DC73f 17 DC73g 17 30 1:128 mA DC70a 20 50 1:2 mA DC70f 17 30 1:64 mA DC70g 17 30 1:128 mA DC71a 20 50 1:2 mA DC71f 17 30 1:64 mA DC71g 17 30 1:128 mA DC72a 21 50 1:2 mA DC72f 18 30 1:64 mA DC72g 18 30 1:128 mA Note 1: Conditions -40°C 3.3V 40 MIPS +25°C 3.3V 40 MIPS +85°C 3.3V 40 MIPS +125°C 3.3V 40 MIPS Data in the Typical column is at 3.3V, 25°C unless otherwise stated. © 2007-2012 Microchip Technology Inc. DS70292G-page 343 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL DI10 DI11 DI15 DI16 DI18 DI19 DI20 DI21 DI28 DI29 DI30 Note Characteristic Input Low Voltage I/O pins PMP pins Min Typ(1) Max Units VSS VSS — — — 0.2 VDD 0.15 VDD V V Conditions PMPTTL = 1 MCLR VSS V 0.2 VDD — 0.2 VDD V I/O Pins with OSC1 or SOSCI VSS — 0.3 VDD V SMBus disabled I/O Pins with SDAx, SCLx VSS I/O Pins with SDAx, SCLx VSS — 0.8 VDD V SMBus enabled Input High Voltage VIH VDD — V 0.7 VDD I/O Pins Not 5V Tolerant(4) — V I/O Pins 5V Tolerant(4) 0.7 VDD 5.5 — V I/O Pins Not 5V Tolerant with 0.24 VDD + 0.8 VDD PMP(4) I/O Pins 5V Tolerant with — 5.5 V 0.24 VDD + 0.8 PMP(4) — 5.5 V SMBus disabled SDAx, SCLx 0.7 VDD SDAx, SCLx 2.1 — 5.5 V SMBus enabled CNx Pull-up Current ICNPU 50 250 400 μA VDD = 3.3V, VPIN = VSS 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 4: See the “Pin Diagrams” section for the 5V tolerant I/O pins. 5: VIL source < (VSS – 0.3). Characterized but not tested. 6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. 7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. 8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. 9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70292G-page 344 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Min Typ(1) Max Units Conditions — — ±2 μA I/O Pins Not 5V Tolerant(4) (Excluding AN9 through AN12) I/O Pins Not 5V Tolerant(4) — — ±1 μA — — ±2 μA — — ±3.5 μA DI51c I/O Pins Not 5V Tolerant(4) (Excluding AN9 through AN12) I/O Pins Not 5V Tolerant(4) — — ±8 μA DI51d AN9 through AN12 — — ±11 μA DI51e AN9 through AN12 — — ±13 μA VSS ≤VPIN ≤VDD, Pin at high-impedance VSS ≤VPIN ≤VDD, Pin at high-impedance, 40°C ≤ TA ≤+85°C Shared with external reference pins, 40°C ≤ TA ≤+85°C VSS ≤VPIN ≤VDD, Pin at high-impedance, -40°C ≤TA ≤+125°C Analog pins shared with external reference pins, -40°C ≤TA ≤+125°C VSS ≤VPIN ≤VDD, Pin at high-impedance, -40°C ≤TA ≤+85°C VSS ≤VPIN ≤VDD, Pin at high-impedance, -40°C ≤TA ≤+125°C DI55 DI56 MCLR OSC1 — — — — ±2 ±2 μA μA IIL DI50 DI51 DI51a DI51b Note 1: 2: 3: 4: 5: 6: 7: 8: 9: Characteristic Input Leakage Current(2,3) I/O pins 5V Tolerant(4) VSS ≤VPIN ≤VDD VSS ≤VPIN ≤VDD, XT and HS modes Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. Negative current is defined as current sourced by the pin. See the “Pin Diagrams” section for the 5V tolerant I/O pins. VIL source < (VSS – 0.3). Characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. © 2007-2012 Microchip Technology Inc. DS70292G-page 345 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. IICL Characteristic ∑IICT Note 1: 2: 3: 4: 5: 6: 7: 8: 9: Max Units Conditions 0 — -5(5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, and RB14 0 — +5(6,7,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB14, and digital 5V-tolerant designated pins -20(9) — +20(9) mA Absolute instantaneous sum of all ± input injection currents from all I/O pins ( | IICL + | IICH | ) ≤∑IICT Input High Injection Current DI60b DI60c Typ(1) Input Low Injection Current DI60a IICH Min Total Input Injection Current (sum of all I/O and control pins) Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. Negative current is defined as current sourced by the pin. See the “Pin Diagrams” section for the 5V tolerant I/O pins. VIL source < (VSS – 0.3). Characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70292G-page 346 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 2x Sink Driver Pins - RA2, RA7RA10, RB10, RB11, RB7, RB4, RC3-RC9 — — 0.4 V IOL ≤3 mA, VDD = 3.3V See Note 1 Output Low Voltage I/O Pins: 4x Sink Driver Pins - RA0, RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 — — 0.4 V IOL ≤6 mA, VDD = 3.3V See Note 1 Output Low Voltage I/O Pins: 8x Sink Driver Pins - RA3, RA4 — — 0.4 V IOL ≤10 mA, VDD = 3.3V See Note 1 Output High Voltage I/O Pins: 2x Source Driver Pins - RA2, RA7-RA10, RB4, RB7, RB10, RB11, RC3-RC9 2.4 — — V IOH ≥ -3 mA, VDD = 3.3V See Note 1 Output High Voltage I/O Pins: 4x Source Driver Pins - RA0, RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 2.4 — — V IOH ≥ -6 mA, VDD = 3.3V See Note 1 Output High Voltage I/O Pins: 8x Source Driver Pins - RA4, RA3 2.4 — — V IOH ≥ -10 mA, VDD = 3.3V See Note 1 1.5 — — 2.0 — — 3.0 — — IOH ≥ -2 mA, VDD = 3.3V See Note 1 1.5 — — IOH ≥ -12 mA, VDD = 3.3V See Note 1 2.0 — — 3.0 — — IOH ≥ -3 mA, VDD = 3.3V See Note 1 1.5 — — IOH ≥ -16 mA, VDD = 3.3V See Note 1 2.0 — — 3.0 — — Output High Voltage I/O Pins: 2x Source Driver Pins - RA2, RA7-RA10, RB4, RB7, RB10, RB11, RC3-RC9 DO20A VOH1 Output High Voltage 4x Source Driver Pins - RA0, RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 Output High Voltage I/O Pins: 8x Source Driver Pins - RA3, RA4 Note 1: IOH ≥ -6 mA, VDD = 3.3V See Note 1 V V V IOH ≥ -5 mA, VDD = 3.3V See Note 1 IOH ≥ -11 mA, VDD = 3.3V See Note 1 IOH ≥ -12 mA, VDD = 3.3V See Note 1 IOH ≥ -4 mA, VDD = 3.3V See Note 1 Parameters are characterized, but not tested. © 2007-2012 Microchip Technology Inc. DS70292G-page 347 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-11: ELECTRICAL CHARACTERISTICS: BOR Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param No. Characteristic Min(1) Typ Max(1) Units Conditions BOR Event on VDD transition high-to-low 2.40 — 2.55 V VDD Symbol BO10 VBOR Note 1: Parameters are for design guidance only and are not tested in manufacturing. TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units E/W -40° C to +125° C V VMIN = Minimum operating voltage V VMIN = Minimum operating voltage Year Provided no other specifications are violated mA D130a D131 EP VPR Program Flash Memory Cell Endurance VDD for Read 10,000 VMIN — — — 3.6 D132B VPEW VDD for Self-Timed Write VMIN — 3.6 D134 TRETD Characteristic Retention 20 — — D135 IDDP — 10 — D136a TRW Supply Current during Programming Row Write Time 1.32 — 1.74 ms D136b TRW Row Write Time 1.28 — 1.79 ms D137a TPE Page Erase Time 20.1 — 26.5 ms D137b TPE Page Erase Time 19.5 — 27.3 ms D138a TWW Word Write Cycle Time 42.3 — 55.9 µs D138b TWW Word Write Cycle Time 41.1 — 57.6 µs Note 1: 2: Conditions TRW = 11064 FRC cycles, TA = +85°C, See Note 2 TRW = 11064 FRC cycles, TA = +125°C, See Note 2 TPE = 168517 FRC cycles, TA = +85°C, See Note 2 TPE = 168517 FRC cycles, TA = +125°C, See Note 2 TWW = 355 FRC cycles, TA = +85°C, See Note 2 TWW = 355 FRC cycles, TA = +125°C, See Note 2 Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Other conditions: FRC = 7.37 MHz, TUN = b'011111 (for Min), TUN = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table 30-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see Section 5.3 “Programming Operations”. TABLE 30-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param No. — Note 1: Symbol Characteristics Min Typ External Filter Capacitor 4.7 10 Value(1) Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN. CEFC DS70292G-page 348 Max Units Comments — μF Capacitor must be low series resistance (< 5 Ohms) © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 30.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 AC characteristics and timing parameters. TABLE 30-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table 30-1. AC CHARACTERISTICS FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 15 pF for OSC2 output VSS TABLE 30-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 Characteristic Min Typ Max Units Conditions 15 pF In XT and HS modes when external clock is used to drive OSC1 COSCO OSC2/SOSCO pin — — DO56 CIO All I/O pins and OSC2 — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode © 2007-2012 Microchip Technology Inc. DS70292G-page 349 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 30-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. OS10 Symbol FIN OS20 TOSC Characteristic Min Typ(1) Max Units External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) DC — 40 MHz EC Oscillator Crystal Frequency 3.5 10 — 3.5 — — — — 10 40 33 10 MHz MHz kHz MHz XT HS SOSC AUX_OSC_FIN TOSC = 1/FOSC 12.5 — DC ns — Time(2) Conditions OS25 TCY Instruction Cycle 25 — DC ns OS30 TosL, TosH External Clock in (OSC1) High or Low Time 0.375 x TOSC — 0.625 x TOSC ns EC OS31 TosR, TosF External Clock in (OSC1) Rise or Fall Time — — 20 ns EC OS40 TckR CLKO Rise Time(3) — 5.2 — ns — OS41 TckF CLKO Fall Time(3) — 5.2 — ns — OS42 GM External Oscillator Transconductance(4) 14 16 18 mA/V Note 1: 2: 3: 4: — VDD = 3.3V TA = +25ºC Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. DS70292G-page 350 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol OS50 FPLLI OS51 FSYS OS52 OS53 TLOCK DCLK Characteristic PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter)(2) Min Typ(1) Max Units 0.8 — 8 MHz ECPLL, HSPLL, XTPLL modes 100 — 200 MHz — 0.9 -3 1.5 0.5 3.1 3 mS % Conditions — Measured over 100 ms period Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula: Note 1: 2: D CLK Peripheral Clock Jitter = ----------------------------------------------------------------------F OSC ⎛ ------------------------------------------------------------⎞ ⎝ Peripheral Bit Rate Clock⎠ For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz. D CLK 3% 3% SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75% 4 16 32 MHz ⎛ --------------------⎞ ⎝ 2 MHz ⎠ TABLE 30-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ 7.3728 MHz(1) F20a FRC -2 — +2 % -40°C ≤ TA ≤ +85°C F20b FRC -5 — +5 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V Note 1: VDD = 3.0-3.6V Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 30-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions LPRC @ 32.768 kHz(1) F21a LPRC -20 ±6 +20 % -40°C ≤ TA ≤ +85°C F21b LPRC -30 — +30 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V Note 1: VDD = 3.0-3.6V Change of LPRC frequency as VDD changes. © 2007-2012 Microchip Technology Inc. DS70292G-page 351 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value Note: Refer to Figure 30-1 for load conditions. DO31 DO32 TABLE 30-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ(1) Max Units Conditions DO31 TIOR Port Output Rise Time — 10 25 ns — DO32 TIOF Port Output Fall Time — 10 25 ns — DI35 TINP INTx Pin High or Low Time (input) 20 — — ns — DI40 TRBP CNx High or Low Time (input) 2 — — TCY — Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS70292G-page 352 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out OSC Time-out SY11 SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay © 2007-2012 Microchip Technology Inc. Note: Refer to Figure 30-1 for load conditions. DS70292G-page 353 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ(2) Max Units Conditions SY10 TMCL MCLR Pulse Width (low) 2 — — μs -40°C to +85°C SY11 TPWRT Power-up Timer Period — 2 4 8 16 32 64 128 — ms -40°C to +85°C User programmable SY12 TPOR Power-on Reset Delay 3 10 30 μs -40°C to +85°C SY13 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset 0.68 0.72 1.2 μs SY20 TWDT1 Watchdog Timer Time-out Period — — — — See Section 27.4 “Watchdog Timer (WDT)” and LPRC specification F21 (Table 30-19) SY30 TOST Oscillator Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period SY35 TFSCM Fail-Safe Clock Monitor Delay — 500 900 μs -40°C to +85°C Note 1: 2: — These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS70292G-page 354 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-5: TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 30-1 for load conditions. TABLE 30-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. TA10 TA11 TA15 Symbol TTXH TTXL TTXP Characteristic TxCK High Time TxCK Low Time TxCK Input Period Min Typ Max Units Conditions Synchronous, no prescaler TCY + 20 — — ns Synchronous, with prescaler (TCY + 20)/N — — ns Must also meet parameter TA15. N = prescale value (1, 8, 64, 256) Asynchronous 20 — — ns Synchronous, no prescaler (TCY + 20) — — ns Synchronous, with prescaler (TCY + 20)/N — — ns Asynchronous 20 — — ns Synchronous, no prescaler 2 TCY + 40 — — ns Synchronous, with prescaler Greater of: 40 ns or (2 TCY + 40)/ N — — — Asynchronous 40 — — ns — DC — 50 kHz — 0.75 TCY + 40 — 1.75 TCY + 40 — — OS60 Ft1 TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Note 1: Must also meet parameter TA15. N = prescale value (1, 8, 64, 256) SOSCI/T1CK Oscillator Input frequency Range (oscillator enabled by setting bit TCS (T1CON)) — N = prescale value (1, 8, 64, 256) Timer1 is a Type A. © 2007-2012 Microchip Technology Inc. DS70292G-page 355 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-23: TIMER2 AND TIMER 4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ Max Units Conditions TB10 TtxH TxCK High Synchronous mode Time Greater of: 20 or (TCY + 20)/N — — ns Must also meet parameter TB15 N = prescale value (1, 8, 64, 256) TB11 TtxL TxCK Low Synchronous Time mode Greater of: 20 or (TCY + 20)/N — — ns Must also meet parameter TB15 N = prescale value (1, 8, 64, 256) TB15 TtxP TxCK Input Period Greater of: 40 or (2 TCY + 40)/N — — ns N = prescale value (1, 8, 64, 256) TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 Clock Edge to Timer Increment — 1.75 TCY + 40 ns Note 1: Synchronous mode — These parameters are characterized, but are not tested in manufacturing. TABLE 30-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ Max Units Conditions TC10 TtxH TxCK High Time Synchronous TCY + 20 — — ns Must also meet parameter TC15 TC11 TtxL TxCK Low Time Synchronous TCY + 20 — — ns Must also meet parameter TC15 TC15 TtxP TxCK Input Period Synchronous, with prescaler 2 TCY + 40 — — ns N = prescale value (1, 8, 64, 256) TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment 0.75 TCY + 40 — 1.75 TCY + 40 ns Note 1: — These parameters are characterized, but are not tested in manufacturing. DS70292G-page 356 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 30-1 for load conditions. TABLE 30-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol IC10 TccL Characteristic(1) ICx Input Low Time No Prescaler Min Max Units Conditions 0.5 TCY + 20 — ns — 10 — ns 0.5 TCY + 20 — ns 10 — ns (TCY + 40)/N — ns With Prescaler IC11 TccH ICx Input High Time No Prescaler With Prescaler IC15 Note 1: TccP ICx Input Period — N = prescale value (1, 4, 16) These parameters are characterized but not tested in manufacturing. FIGURE 30-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC10 OC11 Note: Refer to Figure 30-1 for load conditions. TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions OC10 TccF OCx Output Fall Time — — — ns See parameter D032 OC11 TccR OCx Output Rise Time — — — ns See parameter D031 Note 1: These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 357 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 Active OCx Tri-state TABLE 30-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ Max Units Conditions OC15 TFD Fault Input to PWM I/O Change — — TCY + 20 ns — OC20 TFLT Fault Input Pulse-Width TCY + 20 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. DS70292G-page 358 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-28: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Maximum Data Rate Master Transmit Only (Half-Duplex) 15 MHz Table 30-29 9 MHz — 9 MHz — 15 MHz — Master Transmit/Receive (Full-Duplex) Slave Transmit/Receive (Full-Duplex) CKE — — Table 30-30 — Table 30-31 — CKP SMP 0,1 0,1 0,1 1 0,1 1 — 0 0,1 1 Table 30-32 1 0 0 11 MHz — — Table 30-33 1 1 0 15 MHz — — Table 30-34 0 1 0 11 MHz — — Table 30-35 0 0 0 FIGURE 30-9: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 LSb SP30, SP31 Note: Refer to Figure 30-1 for load conditions. FIGURE 30-10: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 359 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-29: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 SP10 TscP Maximum SCK Frequency — — 15 MHz SP20 TscF SCKx Output Fall Time — — — ns See parameter DO32 and Note 4 SP21 TscR SCKx Output Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — 6 20 ns — SP36 TdiV2scH, TdiV2scL SDOx Data Output Setup to First SCKx Edge 30 — — ns — Note 1: 2: 3: 4: These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70292G-page 360 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-11: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-30: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 SP10 SP20 TscP TscF Maximum SCK Frequency SCKx Output Fall Time — — — — 9 — MHz ns SP21 TscR SCKx Output Rise Time — — — ns SP30 TdoF SDOx Data Output Fall Time — — — ns SP31 TdoR SDOx Data Output Rise Time — — — ns SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge TdoV2sc, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. SP36 SP40 SP41 Note 1: 2: 3: 4: © 2007-2012 Microchip Technology Inc. See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — DS70292G-page 361 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-12: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP30, SP31 SDIx MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 30-1 for load conditions. TABLE 30-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions -40ºC to +125ºC and see Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — SP10 TscP Maximum SCK Frequency — — 9 MHz SP20 TscF SCKx Output Fall Time — — — ns SP21 TscR SCKx Output Rise Time — — — ns SP30 TdoF SDOx Data Output Fall Time — — — ns SP31 TdoR SDOx Data Output Rise Time — — — ns SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. SP36 SP40 SP41 Note 1: 2: 3: 4: DS70292G-page 362 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-13: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 363 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-32: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 SP70 SP72 TscP TscF Maximum SCK Input Frequency SCKx Input Fall Time — — — — 15 — MHz ns SP73 TscR SCKx Input Rise Time — — — ns SP30 TdoF SDOx Data Output Fall Time — — — ns SP31 TdoR SDOx Data Output Rise Time — — — ns SP35 TscH2doV, TscL2doV TdoV2scH, TdoV2scL TdiV2scH, TdiV2scL SDOx Data Output Valid after SCKx Edge SDOx Data Output Setup to First SCKx Edge Setup Time of SDIx Data Input to SCKx Edge — 6 20 ns See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — 30 — — ns — 30 — — ns — SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns — SP50 TssL2scH, TssL2scL SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — SP51 TssH2doZ SSx ↑ to SDOx Output High-Impedance(4) 10 — 50 ns — SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 SP60 TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specification. Assumes 50 pF load on all SPIx pins. SP36 SP40 Note 1: 2: 3: 4: DS70292G-page 364 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-14: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDI SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 365 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 SP70 TscP Maximum SCK Input Frequency — — 11 MHz SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns — SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns — SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns — SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns — SP50 TssL2scH, TssL2scL SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — SP51 TssH2doZ SSx ↑ to SDOx Output High-Impedance(4) 10 — 50 ns — SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 SP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 50 ns — Note 1: 2: 3: 4: These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70292G-page 366 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-15: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 367 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 SP70 TscP Maximum SCK Input Frequency — — 15 MHz SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns — SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns — SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns — SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns — SP50 TssL2scH, TssL2scL SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — SP51 TssH2doZ SSx ↑ to SDOx Output High-Impedance(4) 10 — 50 ns — SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 Note 1: 2: 3: 4: These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70292G-page 368 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 369 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions See Note 3 SP70 TscP Maximum SCK Input Frequency — — 11 MHz SP72 TscF SCKx Input Fall Time — — — ns See parameter DO32 and Note 4 SP73 TscR SCKx Input Rise Time — — — ns See parameter DO31 and Note 4 SP30 TdoF SDOx Data Output Fall Time — — — ns See parameter DO32 and Note 4 SP31 TdoR SDOx Data Output Rise Time — — — ns See parameter DO31 and Note 4 SP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 6 20 ns — SP36 TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge 30 — — ns — SP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 30 — — ns — SP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 30 — — ns — SP50 TssL2scH, TssL2scL SSx ↓ to SCKx ↑ or SCKx Input 120 — — ns — SP51 TssH2doZ SSx ↑ to SDOx Output High-Impedance(4) 10 — 50 ns — SP52 TscH2ssH SSx after SCKx Edge TscL2ssH 1.5 TCY + 40 — — ns See Note 4 Note 1: 2: 3: 4: These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70292G-page 370 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-17: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 30-1 for load conditions. FIGURE 30-18: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 371 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-36: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No. IM10 IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 IM40 IM45 IM50 Characteristic TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode(2) THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(2) TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode(2) TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(2) TSU:DAT Data Input 100 kHz mode Setup Time 400 kHz mode 1 MHz mode(2) THD:DAT Data Input 100 kHz mode Hold Time 400 kHz mode 1 MHz mode(2) TSU:STA Start Condition 100 kHz mode Setup Time 400 kHz mode 1 MHz mode(2) THD:STA Start Condition 100 kHz mode Hold Time 400 kHz mode 1 MHz mode(2) TSU:STO Stop Condition 100 kHz mode Setup Time 400 kHz mode 1 MHz mode(2) THD:STO Stop Condition 100 kHz mode Hold Time 400 kHz mode 1 MHz mode(2) TAA:SCL Output Valid 100 kHz mode From Clock 400 kHz mode 1 MHz mode(2) TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode(2) CB Bus Capacitive Loading Min(1) Max Units TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) — 20 + 0.1 CB — — 20 + 0.1 CB — 250 100 40 0 0 0.2 TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) TCY/2 (BRG + 1) — — — 4.7 1.3 0.5 — — — — — — — 300 300 100 1000 300 300 — — — — 0.9 — — — — — — — — — — — — — 3500 1000 400 — — — 400 μs μs μs μs μs μs ns ns ns ns ns ns ns ns ns μs μs μs μs μs μs μs μs μs μs μs μs ns ns ns ns ns ns μs μs μs pF Conditions — — — — — — CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period the first clock pulse is generated — — — — — Time the bus must be free before a new transmission can start — IM51 TPGD Pulse Gobbler Delay 65 390 ns See Note 3 2 Note 1: BRG is the value of the I C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual chapters. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. DS70292G-page 372 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 30-20: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out © 2007-2012 Microchip Technology Inc. DS70292G-page 373 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-37: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param. Symbol IS10 IS11 IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 TLO:SCL Clock Low Time THI:SCL TF:SCL TR:SCL IS45 IS50 Note 1: Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time TSU:DAT Data Input Setup Time THD:DAT Data Input Hold Time TSU:STA Start Condition Setup Time THD:STA Start Condition Hold Time TSU:STO Stop Condition Setup Time THD:ST O IS40 Characteristic Stop Condition Hold Time TAA:SCL Output Valid From Clock TBF:SDA Bus Free Time CB Min Max Units 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — μs 100 kHz mode — 300 ns ns 400 kHz mode 20 + 0.1 CB 300 1 MHz mode(1) — 100 ns 100 kHz mode — 1000 ns 400 kHz mode ns 20 + 0.1 CB 300 1 MHz mode(1) — 300 ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns 100 kHz mode 0 — μs 400 kHz mode 0 0.9 μs 1 MHz mode(1) 0 0.3 μs 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.25 — μs 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.25 — μs 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs 1 MHz mode(1) 0.6 — μs 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1 MHz mode(1) 250 100 kHz mode 0 3500 ns 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns — — CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period, the first clock pulse is generated — — ns 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs 1 MHz mode(1) 0.5 — μs — 400 pF Bus Capacitive Loading Conditions — Time the bus must be free before a new transmission can start — Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS70292G-page 374 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-21: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS CSCK (SCKE = 0) CS11 CS10 CS21 CS20 CS20 CS21 CSCK (SCKE = 1) COFS CS55 CS56 CS35 CS51 CSDO 70 CS50 High-Z LSb MSb CS30 CSDI MSb In High-Z CS31 LSb In CS40 CS41 Note: Refer to Figure 30-1 for load conditions. © 2007-2012 Microchip Technology Inc. DS70292G-page 375 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-38: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. CS10 Symbol TCSCKL Characteristic(1) Min Typ(2) Max Units Conditions TCY/2 + 20 — — ns — 30 — — ns — TCY/2 + 20 — — ns — CSCK Output High Time(3) (CSCK pin is an output) 30 — — ns — CSCK Input Low Time (CSCK pin is an input) CSCK Output Low Time(3) (CSCK pin is an output) CS11 TCSCKH CSCK Input High Time (CSCK pin is an input) CS20 TCSCKF CSCK Output Fall Time(4) (CSCK pin is an output) — 10 25 ns — CS21 TCSCKR CSCK Output Rise Time(4) (CSCK pin is an output) — 10 25 ns — CS30 TCSDOF CSDO Data Output Fall Time(4) — 10 25 ns — — 10 25 ns — Time(4) CS31 TCSDOR CSDO Data Output Rise CS35 TDV Clock Edge to CSDO Data Valid — — 10 ns — CS36 TDIV Clock Edge to CSDO Tri-Stated 10 — 20 ns — CS40 TCSDI Setup Time of CSDI Data Input to CSCK Edge (CSCK pin is input or output) 20 — — ns — CS41 THCSDI Hold Time of CSDI Data Input to CSCK Edge (CSCK pin is input or output) 20 — — ns — CS50 TCOFSF COFS Fall Time (COFS pin is output) — 10 25 ns See Note 1 CS51 TCOFSR COFS Rise Time (COFS pin is output) — 10 25 ns See Note 1 CS55 TSCOFS Setup Time of COFS Data Input to CSCK Edge (COFS pin is input) 20 — — ns — CS56 THCOFS Hold Time of COFS Data Input to CSCK Edge (COFS pin is input) 20 — — ns — Note 1: 2: 3: 4: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all DCI pins. DS70292G-page 376 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-22: DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS BIT_CLK (CSCK) CS61 CS60 CS62 CS21 CS20 CS71 CS70 CS72 SYNC (COFS) CS76 CS75 CS80 SDOx (CSDO) LSb MSb LSb CS76 SDIx (CSDI) CS75 MSb In CS65 CS66 © 2007-2012 Microchip Technology Inc. DS70292G-page 377 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-39: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. CS60 Symbol Characteristic(1,2) Min Typ(3) Max Units Conditions — TBCLKL BIT_CLK Low Time 36 40.7 45 ns CS61 TBCLKH BIT_CLK High Time 36 40.7 45 ns CS62 TBCLK BIT_CLK Period — 81.4 — ns CS65 TSACL Input Setup Time to Falling Edge of BIT_CLK — — 10 ns — CS66 THACL Input Hold Time from Falling Edge of BIT_CLK — — 10 ns — CS70 TSYNCLO SYNC Data Output Low Time — 19.5 — μs See Note 1 CS71 TSYNCHI SYNC Data Output High Time — 1.3 — μs See Note 1 CS72 TSYNC SYNC Data Output Period — 20.8 — μs See Note 1 — Bit clock is input CS75 TRACL Rise Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS76 TFACL Fall Time, SYNC, SDATA_OUT — — 30 ns CLOAD = 50 pF, VDD = 3V CS80 TOVDACL Output Valid Delay from Rising Edge of BIT_CLK — — 15 ns — Note 1: 2: 3: These parameters are characterized but not tested in manufacturing. These values assume BIT_CLK frequency is 12.288 MHz. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70292G-page 378 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-23: CiTx Pin (output) ECAN™ MODULE I/O TIMING CHARACTERISTICS New Value Old Value CA10 CA11 CiRx Pin (input) CA20 TABLE 30-40: ECAN™ MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions — — — ns See parameter D032 — — ns See parameter D031 ns — CA10 TioF Port Output Fall Time CA11 TioR Port Output Rise Time — CA20 Tcwf Pulse-Width to Trigger CAN Wake-up Filter 120 Note 1: 2: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2007-2012 Microchip Technology Inc. DS70292G-page 379 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-41: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min. Typ Max. Units Lesser of VDD + 0.3 or 3.6 V VSS + 0.3 V Conditions Device Supply AD01 AVDD Module VDD Supply AD02 AVSS Module VSS Supply AD05 VREFH Reference Voltage High Greater of VDD – 0.3 or 3.0 — VSS – 0.3 — — — Reference Inputs AD05a AD06 VREFL Reference Voltage Low AD06a AVSS + 2.5 — AVDD V 3.0 — 3.6 V AVSS — AVDD – 2.5 V 0 — 0 V VREFH = AVDD VREFL = AVSS = 0 2.5 — 3.6 V VREF = VREFH - VREFL VREFH = AVDD VREFL = AVSS = 0 AD07 VREF Absolute Reference Voltage AD08 IREF Current Drain — — 10 μA ADC off AD09 IAD Operating Current — 7.0 9.0 mA — 2.7 3.2 mA ADC operating in 10-bit mode, see Note 1 ADC operating in 12-bit mode, see Note 1 Analog Input AD12 VINH Input Voltage Range VINH VINL — VREFH V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input AD13 VINL Input Voltage Range VINL VREFL — AVSS + 1V V This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input AD17 RIN Recommended Impedance of Analog Voltage Source — — — — 200 200 Ω Ω 10-bit ADC 12-bit ADC Note 1: These parameters are not characterized or tested in manufacturing. DS70292G-page 380 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-42: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREFAD20a Nr Resolution(1) AD21a INL Integral Nonlinearity AD22a DNL Differential Nonlinearity AD23a GERR AD24a EOFF AD25a — 12 data bits bits -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V > -1 — -1 — |0| can affect the ADC results by approximately 4 to 6 counts (i.e., VIH source > (VDD + 0.3V) or VIL source < (VSS – 0.3V). © 2007-2012 Microchip Technology Inc. DS70292G-page 381 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-43: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREFAD20b Nr Resolution(1) 10 data bits bits — AD21b INL Integral Nonlinearity -1.5 — +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V AD22b DNL Differential Nonlinearity > -1 — -1 — | 0 | can affect the ADC results by approximately 4-6 counts. DS70292G-page 382 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-24: ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”. 3 – Software clears AD1CON. SAMP to start conversion. 6 – Convert bit 10. 4 – Sampling ends, conversion sequence starts. 9 – One TAD for end of conversion. © 2007-2012 Microchip Technology Inc. 7 – Convert bit 1. 8 – Convert bit 0. DS70292G-page 383 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-44: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ(2) Max. Units Conditions Clock Parameters(1) AD50 TAD ADC Clock Period AD51 tRC ADC Internal RC Oscillator Period 117.6 — — ns — — 250 — ns — Conversion Rate AD55 tCONV Conversion Time — 14 TAD ns — AD56 FCNV Throughput Rate — — 500 ksps — AD57 TSAMP Sample Time 3 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample Trigger(2) 2 TAD — 3 TAD — Auto convert trigger not selected AD61 tPSS Sample Start from Setting Sample (SAMP) bit(2) 2 TAD — 3 TAD — — AD62 tCSS Conversion Completion to Sample Start (ASAM = 1)(2) — 0.5 TAD — — — AD63 tDPU Time to Stabilize Analog Stage from ADC Off to ADC On(2,3) — — 20 μs — Note 1: 2: 3: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. These parameters are characterized but not tested in manufacturing. The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is turned on ADON bit (AD1CON1) = ‘1’. During this time, the ADC result is indeterminate. DS70292G-page 384 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-25: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Execution Set SAMP Clear SAMP SAMP AD61 AD60 AD55 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 8 1 – Software sets AD1CON. SAMP to start sampling. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”. 3 – Software clears AD1CON. SAMP to start conversion. 4 – Sampling ends, conversion sequence starts. 5 – Convert bit 9. 6 – Convert bit 8. 7 – Convert bit 0. 8 – One TAD for end of conversion. FIGURE 30-26: ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001) AD50 ADCLK Instruction Set ADON Execution SAMP TSAMP AD55 TSAMP AD55 AD55 AD1IF DONE 1 2 3 4 5 6 7 3 4 5 6 8 1 – Software sets AD1CON. ADON to start AD operation. 5 – Convert bit 0. 2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) in the “dsPIC33F/PIC24H Family Reference Manual'. 3 – Convert bit 9. 6 – One TAD for end of conversion. 7 – Begin conversion of next channel. 8 – Sample for time specified by SAMC. 4 – Convert bit 8. © 2007-2012 Microchip Technology Inc. DS70292G-page 385 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-45: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤T A ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Typ(2) Min. Max. Units Conditions Clock Parameters(1) AD50 TAD ADC Clock Period AD51 tRC ADC Internal RC Oscillator Period 76 — — ns — — 250 — ns — Conversion Rate AD55 tCONV Conversion Time — 12 TAD — — — AD56 FCNV Throughput Rate — — 1.1 Msps — AD57 TSAMP Sample Time 2 TAD — — — — Timing Parameters AD60 tPCS Conversion Start from Sample Trigger(2) 2 TAD — 3 TAD — AD61 tPSS Sample Start from Setting Sample (SAMP) bit(2) 2 TAD — 3 TAD — — AD62 tCSS Conversion Completion to Sample Start (ASAM = 1)(2) — 0.5 TAD — — — AD63 tDPU Time to Stabilize Analog Stage from ADC Off to ADC On(2,3) — — 20 μs — Note 1: 2: 3: Auto-Convert Trigger not selected Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity performance, especially at elevated temperatures. These parameters are characterized but not tested in manufacturing. The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is turned on ADON bit (AD1CON1) = 1. During this time, the ADC result is indeterminate. TABLE 30-46: AUDIO DAC MODULE SPECIFICATIONS AC/DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended Param No. Min. Symbol Characteristic Typ Max. Units Conditions Clock Parameters DA01 VOD+ Positive Output Differential Voltage 1 1.15 2 V VOD+ = VDACH – VDACL See Note 1, 2 DA02 VOD- Negative Output Differential Voltage -2 -1.15 -1 V VOD- = VDACL – VDACH See Note 1, 2 DA03 VRES Resolution — 16 — bits DA04 GERR Gain Error — 3.1 — % — DA08 FDAC Clock frequency — — 25.6 MHz — DA09 FSAMP Sample Rate 0 — 100 kHz DA10 FINPUT Input data frequency 0 — 45 kHz 1024 — — Clks Time before first sample — 61 DA11 TINIT Initialization period DA12 SNR Signal-to-Noise Ratio Note 1: 2: dB — — Sampling frequency = 100 kHz Sampling frequency = 96 kHz Measured VDACH and VDACL output with respect to VSS, with 15 µA load and FORM bit (DACXCON) = 0. This parameter is tested at -40°C ≤TA ≤85°C only. DS70292G-page 386 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 30-47: COMPARATOR TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions 300 TRESP Response Time(1,2) — 150 400 ns — 301 TMC2OV Comparator Mode Change to Output Valid(1) — — 10 μs — Note 1: 2: Parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD. TABLE 30-48: COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param No. Symbol D300 VIOFF D301 D302 Note 1: Characteristic Min. Typ Max. Units Input Offset Voltage(1) — VICM Input Common Mode Voltage(1) 0 CMRR Common Mode Rejection Ratio (1) -54 Conditions ±10 — mV — — AVDD-1.5V V — — — dB — Parameters are characterized but not tested. TABLE 30-49: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. VR310 Note 1: Symbol TSET Characteristic Settling Time(1) Min. Typ Max. Units Conditions — — 10 μs — Settling time measured while CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’. TABLE 30-50: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions CVRSRC/24 — CVRSRC/32 LSb — VRD310 CVRES Resolution VRD311 CVRAA Absolute Accuracy — — 0.5 LSb — VRD312 CVRUR Unit Resistor Value (R) — 2k — Ω — © 2007-2012 Microchip Technology Inc. DS70292G-page 387 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-27: PARALLEL SLAVE PORT TIMING DIAGRAM CS RD WR PS4 PMD PS1 PS3 PS2 TABLE 30-51: PARALLEL SLAVE PORT TIME SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions PS1 TdtV2wrH Data in Valid before WR or CS Inactive (setup time) 20 — — ns — PS2 TwrH2dtI WR or CS Inactive to Data-In Invalid (hold time) 20 — — ns — PS3 TrdL2dtV RD and CS to Active Data-Out Valid — — 80 ns — PS4 TrdH2dtI RD Active or CS Inactive to Data-Out Invalid 10 — 30 ns — DS70292G-page 388 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-28: PARALLEL MASTER PORT READ TIMING DIAGRAM P1 P2 P3 P4 P1 P2 P3 P4 P1 P2 System Clock PMA Address PMD Data Address PM6 PM2 PM7 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS1 TABLE 30-52: PARALLEL MASTER PORT READ TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min. Typ Max. Units Conditions PM1 PMALL/PMALH Pulse-Width — 0.5 TCY — ns — PM2 Address Out Valid to PMALL/PMALH Invalid (address setup time) — 0.75 TCY — ns — PM3 PMALL/PMALH Invalid to Address Out Invalid (address hold time) — 0.25 TCY — ns — PM5 PMRD Pulse-Width — 0.5 TCY — ns — PM6 PMRD or PMENB Active to Data In Valid (data setup time) 150 — — ns — PM7 PMRD or PMENB Inactive to Data In Invalid (data hold time) — — 5 ns — © 2007-2012 Microchip Technology Inc. DS70292G-page 389 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 30-29: PARALLEL MASTER PORT WRITE TIMING DIAGRAM P1 P2 P3 P4 P2 P1 P3 P4 P1 P2 System Clock PMA Address Address PMD Data Data PM12 PM13 PMRD PMWR PM11 PMALL/PMALH PM16 PMCS1 TABLE 30-53: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min. Typ Max. Units Conditions PM11 PMWR Pulse-Width — 0.5 TCY — ns — PM12 Data Out Valid before PMWR or PMENB goes Inactive (data setup time) — — — ns — PM13 PMWR or PMEMB Invalid to Data Out Invalid (data hold time) — — — ns — PM16 PMCSx Pulse-Width TCY - 5 — — ns — TABLE 30-54: DMA READ/WRITE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DM1 Characteristic DMA Read/Write Cycle Time DS70292G-page 390 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended Min. Typ Max. Units Conditions — — 1 TCY ns — © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/ X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section 30.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in Section 30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10. Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 high temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias(4) .........................................................................................................-40°C to +150°C Storage temperature .............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(5) .................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(5) ....................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(5) .................................................... -0.3V to 5.6V Maximum current out of VSS pin .............................................................................................................................60 mA Maximum current into VDD pin(2) .............................................................................................................................60 mA Maximum junction temperature............................................................................................................................. +155°C Maximum current sourced/sunk by any 2x I/O pin(3) ................................................................................................2 mA Maximum current sourced/sunk by any 4x I/O pin(3) ................................................................................................4 mA Maximum current sourced/sunk by any 8x I/O pin(3) ................................................................................................8 mA Maximum current sunk by all ports combined ........................................................................................................70 mA Maximum current sourced by all ports combined(2) ................................................................................................70 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2). 3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+, VREF-, SCLx, SDAx, PGCx, and PGDx pins. 4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. 5: Refer to the “Pin Diagrams” section for 5V tolerant pins. © 2007-2012 Microchip Technology Inc. DS70292G-page 391 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.1 High Temperature DC Characteristics TABLE 31-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temperature Range (in °C) dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 — 3.0V to 3.6V(1) -40°C to +150°C 20 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. TABLE 31-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +155 °C Operating Ambient Temperature Range TA -40 — +150 °C High Temperature Devices Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD - Σ IOH) PD PINT + PI/O W PDMAX (TJ - TA)/θJA W I/O Pin Power Dissipation: I/O = Σ ({VDD - VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature DC CHARACTERISTICS Parameter No. Symbol Characteristic Min Typ Max Units 3.0 3.3 3.6 V Conditions Operating Voltage HDC10 Supply Voltage VDD Note 1: — -40°C to +150°C Device is functional at VBORMIN < VDD < VDDMIN. Analog modules such as the ADC will have degraded performance. Device functionality is tested but not characterized. DS70292G-page 392 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Power-Down Current (IPD) HDC60e 250 2000 μA +150°C 3.3V Base Power-Down Current(1,3) HDC61c 3 5 μA +150°C 3.3V Watchdog Timer Current: ΔIWDT(2,4) Note 1: 2: 3: 4: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON) = 1. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. These parameters are characterized, but are not tested in manufacturing. TABLE 31-5: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150ºC for High Temperature DC CHARACTERISTICS Parameter No. Doze Ratio Units 45 1:2 mA 25 1:64 mA 25 1:128 mA Typical(1) Max HDC72a 39 HDC72f 18 18 HDC72g Note 1: Conditions +150°C 3.3V 20 MIPS Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 393 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 2x Sink Driver Pins - RA2, RA7RA10, RB10, RB11, RB7, RB4, RC3-RC9 — — 0.4 V IOL ≤1.8 mA, VDD = 3.3V See Note 1 Output Low Voltage I/O Pins: 4x Sink Driver Pins - RA0, RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 — — 0.4 V IOL ≤3.6 mA, VDD = 3.3V See Note 1 Output Low Voltage I/O Pins: 8x Sink Driver Pins - RA3, RA4 — — 0.4 V IOL ≤6 mA, VDD = 3.3V See Note 1 Output High Voltage I/O Pins: 2x Source Driver Pins - RA2, RA7-RA10, RB4, RB7, RB10, RB11, RC3-RC9 2.4 — — V IOL ≥ -1.8 mA, VDD = 3.3V See Note 1 Output High Voltage I/O Pins: 4x Source Driver Pins - RA0, RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 2.4 — — V IOL ≥ -3 mA, VDD = 3.3V See Note 1 Output High Voltage I/O Pins: 8x Source Driver Pins - RA4, RA3 2.4 — — V IOL ≥ -6 mA, VDD = 3.3V See Note 1 1.5 — — 2.0 — — 3.0 — — IOH ≥ -1.4 mA, VDD = 3.3V See Note 1 1.5 — — IOH ≥ -3.9 mA, VDD = 3.3V See Note 1 2.0 — — 3.0 — — IOH ≥ -2 mA, VDD = 3.3V See Note 1 1.5 — — IOH ≥ -7.5 mA, VDD = 3.3V See Note 1 2.0 — — 3.0 — — Output High Voltage I/O Pins: 2x Source Driver Pins - RA2, RA7-RA10, RB4, RB7, RB10, RB11, RC3-RC9 DO20A VOH1 Output High Voltage 4x Source Driver Pins - RA0, RA1, RB0-RB3, RB5, RB6, RB8, RB9, RB12-RB15, RC0-RC2 Output High Voltage I/O Pins: 8x Source Driver Pins - RA3, RA4 Note 1: IOH ≥ -1.9 mA, VDD = 3.3V See Note 1 V V V IOH ≥ -1.85 mA, VDD = 3.3V See Note 1 IOH ≥ -3.7 mA, VDD = 3.3V See Note 1 IOH ≥ -6.8 mA, VDD = 3.3V See Note 1 IOH ≥ -3 mA, VDD = 3.3V See Note 1 Parameters are characterized, but not tested. DS70292G-page 394 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-7: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Min Typ Max Units Conditions 10,000 — — E/W -40° C to +150ºC(2) 20 — — Year 1000 E/W cycles or less and no other specifications are violated Program Flash Memory HD130 EP Cell Endurance HD134 TRETD Characteristic Retention Note 1: 2: These parameters are assured by design, but are not characterized or tested in manufacturing. Programming of the Flash memory is allowed up to 150°C. © 2007-2012 Microchip Technology Inc. DS70292G-page 395 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 31.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 AC characteristics and timing parameters for high temperature devices. However, all AC timing specifications in this section are the same as those in Section 30.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature. For example, parameter OS53 in Section 30.2 “AC Characteristics and Timing Parameters” is the Industrial and Extended temperature equivalent of HOS53. TABLE 31-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 31-1: Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Operating voltage VDD range as described in Table 31-1. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2 VDD/2 CL Pin RL VSS CL Pin RL = 464Ω CL = 50 pF for all pins except OSC2 15 pF for OSC2 output VSS TABLE 31-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic CLKO Stability (Jitter)(1) Min Typ Max Units -5 0.5 5 % HOS53 DCLK Note 1: These parameters are characterized, but are not tested in manufacturing. DS70292G-page 396 Conditions Measured over 100 ms period © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 10 25 ns — HSP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 28 — — ns — HSP41 TscH2diL, TscL2diL 35 — — ns — Note 1: These parameters are characterized but not tested in manufacturing. Hold Time of SDIx Data Input to SCKx Edge TABLE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — 10 25 ns — HSP36 TdoV2sc, TdoV2scL 35 — — ns — HSP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 28 — — ns — HSP41 TscH2diL, TscL2diL 35 — — ns — Note 1: SDOx Data Output Setup to First SCKx Edge Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized but not tested in manufacturing. © 2007-2012 Microchip Technology Inc. DS70292G-page 397 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, TscL2doV SDOx Data Output Valid after SCKx Edge — — 35 ns — HSP40 TdiV2scH, TdiV2scL Setup Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP51 TssH2doZ SSx ↑ to SDOx Output High-Impedance 15 — 55 ns Note 1: 2: See Note 2 These parameters are characterized but not tested in manufacturing. Assumes 50 pF load on all SPIx pins. TABLE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Characteristic(1) Min Typ Max Units Conditions HSP35 TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge — — 35 ns — HSP40 TdiV2scH, Setup Time of SDIx Data Input TdiV2scL to SCKx Edge 25 — — ns — HSP41 TscH2diL, TscL2diL Hold Time of SDIx Data Input to SCKx Edge 25 — — ns — HSP51 TssH2doZ SSx ↑ to SDOX Output High-Impedance 15 — 55 ns HSP60 TssL2doV SDOx Data Output Valid after SSx Edge — — 55 ns Note 1: 2: These parameters are characterized but not tested in manufacturing. Assumes 50 pF load on all SPIx pins. DS70292G-page 398 See Note 2 — © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-14: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+150°C for High Temperature Characteristic Min Typ Max Units 600 50 μA μA Conditions Reference Inputs HAD08 Note 1: 2: IREF Current Drain — — 250 — ADC operating, See Note 1 ADC off, See Note 1 These parameters are not characterized or tested in manufacturing. These parameters are characterized, but are not tested in manufacturing. TABLE 31-15: ADC MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20a Nr Resolution(3) HAD21a INL Integral Nonlinearity HAD22a DNL Differential Nonlinearity HAD23a GERR HAD24a EOFF 12 data bits bits — -2 — +2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V > -1 — -1 — | 0 | can affect the ADC results by approximately 4-6 counts. Input Signal Bandwidth © 2007-2012 Microchip Technology Inc. — — 200 kHz — DS70292G-page 399 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-16: ADC MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-(1) HAD20b Nr Resolution(3) HAD21b INL Integral Nonlinearity HAD22b DNL Differential Nonlinearity HAD23b GERR HAD24b EOFF 10 data bits bits — -3 — 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.6V > -1 — -1 — | 0 | can affect the ADC results by approximately 4-6 counts. DS70292G-page 400 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 TABLE 31-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions — — ns — — 400 Ksps — Clock Parameters HAD50 TAD ADC Clock Period(1) HAD56 FCNV Throughput Rate(1) 147 Conversion Rate Note 1: — These parameters are characterized but not tested in manufacturing. TABLE 31-18: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤TA ≤+150°C for High Temperature Param No. Symbol Characteristic Min Typ Max Units Conditions — ns — 800 Ksps — Clock Parameters HAD50 TAD ADC Clock Period(1) HAD56 FCNV Throughput Rate(1) Note 1: These parameters are characterized but not tested in manufacturing. 104 — Conversion Rate © 2007-2012 Microchip Technology Inc. — — DS70292G-page 401 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 NOTES: DS70292G-page 402 © 2007-2012 Microchip Technology Inc. DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 32-1: VOH – 2x DRIVER PINS -0.040 -0.016 -0.035 3.6V IOH (A) -0.012 -0.010 3V -0.008 -0.006 3.3V -0.025 3V -0.020 -0.015 -0.004 -0.010 -0.002 -0.005 0.000 0.00 3.6V -0.030 3.3V IOH (A) -0.014 VOH – 8x DRIVER PINS FIGURE 32-3: 0.50 1.00 1.50 2.00 2.50 3.00 3.50 0.000 0.00 4.00 1.00 2.00 VOH (V) FIGURE 32-2: VOH – 4x DRIVER PINS FIGURE 32-4: 3.6V -0.070 IOH (A) IOH (A) 3V -0.015 -0.010 DS70292G-page 403 3.00 4.00 VOH – 16x DRIVER PINS 3.6V -0.060 3.3V -0.020 3.3V -0.050 3V -0.040 -0.030 -0.020 -0.005 0.000 0.00 4.00 -0.080 -0.030 -0.025 3.00 VOH (V) -0.010 0.50 1.00 1.50 2.00 VOH (V) 2.50 3.00 3.50 4.00 0.000 0.00 1.00 2.00 VOH (V) dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. 32.0 FIGURE 32-7: VOL – 2x DRIVER PINS 0.060 0.020 0.018 3.6V 0.016 3.6V 0.050 3.3V 3.3V 0.014 0.040 3V 0.012 IOL (A) IOL (A) VOL – 8x DRIVER PINS 0.010 0.008 3V 0.030 0.020 0.006 0.004 0.010 0.002 0.000 0.00 1.00 2.00 3.00 0.000 0.00 4.00 1.00 FIGURE 32-6: VOL – 4x DRIVER PINS FIGURE 32-8: 3.00 4.00 VOL – 16x DRIVER PINS 0.120 0.040 0.035 3.6V 0.030 3.6V 0.100 3.3V 0.025 3.3V 0.080 3V IOL (A) © 2007-2012 Microchip Technology Inc. IOL (A) 2.00 VOL (V) VOL (V) 0.020 0.015 3V 0.060 0.040 0.010 0.020 0.005 0.000 0.00 1.00 2.00 VOL (V) 3.00 4.00 0.000 0.00 1.00 2.00 VOL (V) 3.00 4.00 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 404 FIGURE 32-5: TYPICAL IPD CURRENT @ VDD = 3.3V, +85ºC FIGURE 32-11: TYPICAL IDOZE CURRENT @ VDD = 3.3V, +85ºC 80.00 1200 70.00 1000 IDOZE Current (mA) 60.00 IPD (uA) 800 600 400 50.00 40.00 30.00 20.00 200 10.00 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0.00 90 100 110 120 1:1 2:1 Temperature (Celsius) FIGURE 32-10: 64:1 128:1 Doze Ratio TYPICAL IDD CURRENT @ VDD = 3.3V, +85ºC FIGURE 32-12: 60 TYPICAL IIDLE CURRENT @ VDD = 3.3V, +85ºC 35 30 PMD = 0, with PLL 50 IDD (mA) IIDLE Current (mA) 25 40 PMD = 1, with PLL 30 20 20 15 10 PMD = 0, no PLL DS70292G-page 405 PMD = 1, no PLL 10 5 0 0 0 5 10 15 20 25 MIPS 30 35 40 45 10 20 30 MIPS 40 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 © 2007-2012 Microchip Technology Inc. FIGURE 32-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 32-14: 35 LPRC Frequency (kHz) FRC Frequency (kHz) 7500 TYPICAL LPRC FREQUENCY @ VDD = 3.3V 7400 7300 30 25 7200 -40 -30 -20 -10 0 10 20 30 40 50 60 Temperature (Celsius) 70 80 90 100 110 120 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (Celsius) © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292G-page 406 FIGURE 32-13: dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 33.0 PACKAGING INFORMATION 28-Lead SPDIP Example dsPIC33FJ32GP 302-E/SP e3 0730235 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN-S Example XXXXXXXX XXXXXXXX YYWWNNN 33FJ32GP 302E/MM e3 0730235 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC 33FJ32GP304 -I/PT e3 0730235 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN e3 * Note: dsPIC 33FJ32GP304 -E/ML e3 0730235 Example 44-Lead TQFP Legend: XX...X Y YY WW NNN dsPIC33FJ32GP 302-E/SO e3 0730235 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. If the full Microchip part number cannot be marked on one line, it is carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007-2012 Microchip Technology Inc. DS70292G-page 407 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 33.1 Package Details 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .050 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B DS70292G-page 408 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2007-2012 Microchip Technology Inc. DS70292G-page 409 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70292G-page 410 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2007-2012 Microchip Technology Inc. DS70292G-page 411 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S] with 0.40 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E2 E b 2 2 1 1 K N N L NOTE 1 TOP VIEW BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 3.65 3.70 4.70 b 0.23 0.38 0.43 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 6.00 BSC 3.65 3.70 4.70 6.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-124B DS70292G-page 412 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH00±[[PP%RG\>4)16@ ZLWKPP&RQWDFW/HQJWK 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ © 2007-2012 Microchip Technology Inc. DS70292G-page 413 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 6.30 6.45 6.80 b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 8.00 BSC 6.30 6.45 6.80 8.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 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