dsPIC33FJ12GP201/202
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
© 2007-2011 Microchip Technology Inc.
DS70264E
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-358-6
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70264E-page 2
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
High-Performance, 16-Bit Digital Signal Controllers
Operating Range:
Digital I/O:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
•
•
•
•
•
High-Performance DSC CPU:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Modified Harvard architecture
C compiler optimized instruction set
16 bit wide data path
24 bit wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
83 base instructions, mostly one word/one cycle
Sixteen 16-bit general purpose registers
Two 40-bit accumulators with rounding and
saturation options
Flexible and powerful addressing modes:
- Indirect
- Modulo
- Bit-Reversed
Software stack
16 x 16 fractional/integer multiply operations
32/16 and 16/16 divide operations
Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
Up to ±16-bit shifts for up to 40-bit data
Interrupt Controller:
•
•
•
•
•
5-cycle latency
Up to 21 available interrupt sources
Up to three external interrupts
Seven programmable priority levels
Four processor exceptions
On-Chip Flash and SRAM:
• Flash program memory (12 Kbytes)
• Data SRAM (1024 bytes)
• Boot and General Security for Program Flash
© 2007-2011 Microchip Technology Inc.
Peripheral Pin Select Functionality
Up to 21 programmable digital I/O pins
Wake-up/interrupt-on-change for up to 21 pins
Output pins can drive from 3.0V to 3.6V
Up to 5V output with open drain configurations on
5V tolerant pins
• 4 mA sink on all I/O pins
System Management:
• Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low-jitter PLL
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare:
• Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to four channels):
- Capture on up, down, or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
• Output Compare (up to two channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM Mode
DS70264E-page 3
dsPIC33FJ12GP201/202
Communication Modules:
Analog-to-Digital Converters (ADCs):
• 4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• I2C™:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
• UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4 character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to 10 input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
DS70264E-page 4
CMOS Flash Technology:
•
•
•
•
•
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial and extended temperature
Low power consumption
Packaging:
• 18-pin PDIP/SOIC
• 28-pin SPDIP/SOIC/SSOP/QFN
Note:
See Table 1 for the exact peripheral
features per device.
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
dsPIC33FJ12GP201/202 Product Families
The device names, pin counts, memory sizes, and
peripheral availability of each family are listed below,
followed by their pinout diagrams.
dsPIC33FJ12GP201/202 CONTROLLER FAMILIES
Remappable
Pins
16-bit Timer
Input Capture
Output Compare
Std. PWM
UART
External Interrupts(2)
SPI
I2C™
I/O Pins (Max)
18
12
1
8
3(1)
4
2
1
3
1
1 ADC,
6 ch
1
13
PDIP
SOIC
dsPIC33FJ12GP202
28
12
1
16
3(1)
4
2
1
3
1
1 ADC,
10 ch
1
21
SPDIP
SOIC
SSOP
QFN
Note 1:
2:
Packages
RAM
(Kbyte)
dsPIC33FJ12GP201
10-Bit/12-Bit ADC
Device
Program Flash Memory
(Kbyte)
Remappable Peripherals
Pins
TABLE 1:
Only two out of three timers are remappable.
Only two out of three interrupts are remappable.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 5
dsPIC33FJ12GP201/202
Pin Diagrams
18-PIN PDIP, SOIC
= Pins are up to 5V tolerant
1
18
VDD
2
17
VSS
PGEC2/AN1/VREF-/CN3/RA1
3
16
AN6/RP15(1)/CN11/RB15
PGED1/AN2/RP0(1)/CN4/RB0
4
PGEC1/AN3/RP1(1)/CN5/RB1
5
OSC1/CLKI/CN30/RA2
6
OSC2/CLKO/CN29/RA3
7
PGED3/SOSCI/RP4(1)/CN1/RB4
8
PGEC3/SOSCO/T1CK/CN0/RA4
9
dsPIC33FJ12GP201
MCLR
PGED2/AN0/VREF+/CN2/RA0
15
AN7/RP14(1)/CN12/RB14
14
VCAP
13
VSS
12
SDA1/RP9(1)/CN21/RB9
11
SCL1/RP8(1)/CN22/RB8
10
INT0/RP7(1)/CN23/RB7
= Pins are up to 5V tolerant
28-PIN SPDIP, SOIC, SSOP
MCLR
1
28
AVDD
2
27
PGEC2/AN1/VREF-/CN3/RA1
3
26
AN6/RP15(1)/CN11/RB15
(1)
4
25
AN7/RP14(1)/CN12/RB14
(1)
5
24
AN8/RP13(1)/CN13/RB13
(1)
AN4/RP2 /CN6/RB2
6
23
AN9/RP12(1)/CN14/RB12
AN5/RP3(1)/CN7/RB3
7
22
TMS/RP11(1)/CN15/RB11
Vss
8
21
TDI/RP10(1)/CN16/RB10
OSC1/CLKI/CN30/RA2
9
20
VCAP
PGED1/AN2/RP0 /CN4/RB0
PGEC1/AN3/RP1 /CN5/RB1
dsPIC33FJ12GP202
PGED2/AN0/VREF+/CN2/RA0
AV ss
OSC2/CLKO/CN29/RA3
10
19
Vss
PGED3/SOSC/RP4(1)/CN1/RB4
11
18
TDO/SDA1/RP9(1)/CN21/RB9
PGEC3/SOSCO/T1CK/CN0/RA4
12
17
TCK/SCL1/RP8(1)/CN22/RB8
VDD
13
16
INT0/RP7(1)/CN23/RB7
ASDA1/RP5(1)/CN27/RB5
14
15
ASCL1/RP6(1)/CN24/RB6
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
DS70264E-page 6
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
Pin Diagrams (Continued)
28-Pin QFN(2)
MCLR
AVDD
AVSS
AN6/RP15(1)/CN11/RB15
AN7/RP14(1)/CN12/RB14
28
PGED2/AN0/VREF+/CN2/RA0
PGEC2/AN1/VREF-/CN3/RA1
= Pins are up to 5V tolerant
27
26
25
24
23
22
PGED1/AN2/RP0(1)/CN4/RB0
1
21
AN8/RP13(1)/CN13/RB13
PGEC1/AN3/RP1(1)/CN5/RB1
2
20
AN9/RP12(1)/CN14/RB12
AN4/RP2(1)/CN6/RB2
3
19
TMS/RP11(1)/CN15/RB11
AN5/RP3(1)/CN7/RB3
4
18
TDI/RP10(1)/CN16/RB10
VSS
5
17
VCAP
OSC1/CLKI/CN30/RA2
6
16
VSS
OSC2/CLKO/CN29/RA3
7
15
TDO/SDA1/RP9(1)/CN21/RB9
11
12
13
14
ASDA1/RP5 /CN27/RB5
(1)
ASCL1/RP6 /CN24/RB6
INT0/RP7(1)/CN23/RB7
TCK/SCL1/RP8(1)/CN22/RB8
10
(1)
9
VDD
PGED3/SOSCI/RP4(1)/CN1/RB4
8
PGEC3/SOSCO/T1CK/CN0/RA4
dsPIC33FJ12GP202
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 7
dsPIC33FJ12GP201/202
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 15
3.0 CPU............................................................................................................................................................................................ 19
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory .............................................................................................................................................................. 55
6.0 Resets ....................................................................................................................................................................................... 61
7.0 Interrupt Controller ..................................................................................................................................................................... 69
8.0 Oscillator Configuration .............................................................................................................................................................. 97
9.0 Power-Saving Features............................................................................................................................................................ 107
10.0 I/O Ports ................................................................................................................................................................................... 111
11.0 Timer1 ...................................................................................................................................................................................... 129
12.0 Timer2/3 Feature...................................................................................................................................................................... 131
13.0 Input Capture............................................................................................................................................................................ 137
14.0 Output Compare....................................................................................................................................................................... 139
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 143
16.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 149
17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 157
18.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 163
19.0 Special Features ...................................................................................................................................................................... 175
20.0 Instruction Set Summary .......................................................................................................................................................... 181
21.0 Development Support............................................................................................................................................................... 189
22.0 Electrical Characteristics .......................................................................................................................................................... 193
23.0 Packaging Information.............................................................................................................................................................. 237
Appendix A: Revision History............................................................................................................................................................. 245
Index ................................................................................................................................................................................................. 253
The Microchip Web Site ..................................................................................................................................................................... 257
Customer Change Notification Service .............................................................................................................................................. 257
Customer Support .............................................................................................................................................................................. 257
Reader Response .............................................................................................................................................................................. 258
Product Identification System............................................................................................................................................................. 259
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70264E-page 8
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12GP201/202 devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This document contains device specific information for
the dsPIC33FJ12GP201/202 Digital Signal Controller
(DSC) devices. The dsPIC33F devices contain
extensive Digital Signal Processor (DSP) functionality
with a high-performance, 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a general block diagram of the
core
and
peripheral
modules
in
the
dsPIC33FJ12GP201/202 family of devices. Table 1-1
lists the functions of the various pins shown in the
pinout diagrams.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 9
dsPIC33FJ12GP201/202
FIGURE 1-1:
dsPIC33FJ12GP201/202 BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
8
PORTA
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
PORTB
16
23
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP
16
DSP Engine
Power-up
Timer
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
VDD, VSS
Timers
1-3
IC1,2,7,8
Note:
Literal Data
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
16
16
MCLR
UART1
ADC1
OC/
PWM1-2
CNx
I2C1
SPI1
Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features
on each device.
DS70264E-page 10
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
Description
AN0-AN9
I
Analog
No
Analog input channels.
CLKI
CLKO
I
O
ST/CMOS
—
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
ST/CMOS
No
OSC2
I/O
—
No
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/CMOS
—
No
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
CN0-CN7
CN11-CN15
CN21-CN24
CN27
CN29-CN30
I
ST
No
No
No
No
No
Change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
IC1-IC2
IC7-IC8
I
ST
Yes
Yes
Capture inputs 1/2
Capture inputs 7/8
OCFA
OC1-OC2
I
O
ST
—
Yes
Yes
Compare Fault A input (for Compare Channels 1 and 2).
Compare outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No
Yes
Yes
External interrupt 0.
External interrupt 1.
External interrupt 2.
RA0-RA4
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
No
PORTB is a bidirectional I/O port.
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
No
Yes
Yes
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
© 2007-2011 Microchip Technology Inc.
Analog = Analog input
O = Output
P = Power
I = Input
DS70264E-page 11
dsPIC33FJ12GP201/202
TABLE 1-1:
Pin Name
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
PPS
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
—
No
CPU logic filter capacitor connection.
Description
VCAP
P
VSS
P
—
No
Ground reference for logic and I/O pins.
VREF+
I
Analog
No
Analog voltage reference (high) input.
VREF-
I
Analog
No
Analog voltage reference (low) input.
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all times.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVSS
P
P
No
Ground reference for analog modules.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
DS70264E-page 12
Analog = Analog input
O = Output
P = Power
I = Input
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
1.1
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the dsPIC33FJ12GP202 product page of
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory” (DS70202)
Section 4. “Program Memory” (DS70202)
Section 5. “Flash Programming” (DS70191)
Section 6. “Interrupts” (DS70184)
Section 7. “Oscillator” (DS70186)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer and Power-saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 14. “Motor Control PWM” (DS70187)
Section 15. “Quadrature Encoder Interface (QEI)” (DS70208)
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
© 2007-2011 Microchip Technology Inc.
DS70264E-page 13
dsPIC33FJ12GP201/202
NOTES:
DS70264E-page 14
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12GP201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the
Microchip
web
site
(www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ12GP201/202
family of 16-bit Digital Signal Controllers (DSC)
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Additionally, the following pins may be required:
• VREF+/VREF- pins are used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 15
dsPIC33FJ12GP201/202
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
R
R1
MCLR
C
dsPIC33F
VSS
10 Ω
2.2.1
VDD
0.1 µF
Ceramic
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
VSS
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
• Device Reset
• Device Programming and Debugging.
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
VSS
VCAP
VDD
10 µF
Tantalum
VDD
2.4
0.1 µF
Ceramic
0.1 µF
Ceramic
TANK CAPACITORS
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 22.0
“Electrical
Characteristics”
for
additional
information.
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R
R1
JP
MCLR
dsPIC33F
C
Note 1:
R ≤ 10 kΩ is recommended. A suggested
starting value is 10 kΩ. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 19.2
“On-Chip Voltage Regulator” for details.
DS70264E-page 16
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and timing requirements information in the respective device
Flash programming specification for information on
capacitive loading limits and pin input voltage high (VIH)
and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB® ICD 3, or MPLAB® REAL
ICE™.
For more information on ICD 2, ICD 3, and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB® ICD 2 In-Circuit Debugger User's
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User's Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
© 2007-2011 Microchip Technology Inc.
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
DS70264E-page 17
dsPIC33FJ12GP201/202
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor between VSS
and unused pins and drive the output to logic low.
When the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV, and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE
in-circuit emulator is selected as a debugger, it
automatically initializes all of the A/D input pins (ANx)
as “digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, MPLAB ICD 3, or
MPLAB REAL ICE in-circuit emulator, must not be
cleared by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE In-Circuit Emulator is used as a programmer, the
user application firmware must correctly configure the
AD1PCFGL register. Automatic initialization of this
register is only done during debugger operation.
Failure to correctly configure the register(s) will result in
all A/D pins being recognized as analog input pins,
resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
DS70264E-page 18
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
3.0
CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12GP201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS70204) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJ12GP201/202 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M by 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with
the exception of instructions that change the program
flow, the double-word move (MOV.D) instruction and
the table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The dsPIC33FJ12GP201/202 devices have sixteen,
16-bit working registers in the programmer’s model.
Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
The dsPIC33FJ12GP201/202 instruction set has two
classes of instructions: MCU and DSP. These two
instruction classes are seamlessly integrated into a
single CPU. The instruction set includes many
addressing modes and is designed for optimum C
compiler
efficiency.
For
most
instructions,
dsPIC33FJ12GP201/202 devices are capable of
executing a data (or program data) memory read, a
working register (data) read, a data memory write and
a program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1. The
programmer’s model for the dsPIC33FJ12GP201/202
is shown in Figure 3-2.
© 2007-2011 Microchip Technology Inc.
3.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC instruction and other associated instructions
can concurrently fetch two data operands from memory
while multiplying two W registers and accumulating and
optionally saturating the result in the same cycle. This
instruction functionality requires that the RAM data
space be split for these instructions and linear for all
others. Data space partitioning is achieved in a
transparent and flexible manner through dedicating
certain working registers to each address space.
3.3
Special MCU Features
The dsPIC33FJ12GP201/202 features a 17-bit by
17-bit single-cycle multiplier that is shared by both the
MCU ALU and DSP engine. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special
operations, such as (-1.0) x (-1.0).
DS70264E-page 19
dsPIC33FJ12GP201/202
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
The dsPIC33FJ12GP201/202 supports 16/16 and
32/16 divide operations, both fractional and integer. All
divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
FIGURE 3-1:
dsPIC33FJ12GP201/202 CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
16
16
16
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction Reg
16
Literal Data
Instruction
Decode &
Control
16
Control Signals
to Various Blocks
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
To Peripheral Modules
DS70264E-page 20
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
FIGURE 3-2:
dsPIC33FJ12GP201/202 PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
ACCA
DSP
Accumulators
ACCB
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
© 2007-2011 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70264E-page 21
dsPIC33FJ12GP201/202
3.4
CPU Control Registers
CPU control registers include:
• CPU Status Register (Register 3-1)
• Core Control Register (Register 3-2)
REGISTER 3-1:
R-0
OA
SR: CPU STATUS REGISTER
R-0
R/C-0
R/C-0
OB
(1)
(1)
SA
SB
R-0
R/C-0
R -0
R/W-0
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(2)
R/W-0(3)
R/W-0(3)
IPL(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
This bit can be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
Note 1:
2:
3:
This bit can be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
DS70264E-page 22
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the MSb of the result occurred
0 = No carry-out from the MSb of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
© 2007-2011 Microchip Technology Inc.
DS70264E-page 23
dsPIC33FJ12GP201/202
REGISTER 3-2:
U-0
—
bit 15
U-0
—
R/W-0
SATB
Legend:
R = Readable bit
0’ = Bit is cleared
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
U-0
—
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
DL
R-0
bit 8
R/W-0
SATA
bit 7
bit 15-13
bit 12
CORCON: CORE CONTROL REGISTER
R/W-1
SATDW
R/W-0
ACCSAT
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
001 = 1 DO loop active
000 = 0 DO loops active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply operations
0 = Fractional mode enabled for DSP multiply operations
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.
DS70264E-page 24
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
3.5
Arithmetic Logic Unit (ALU)
The dsPIC33FJ12GP201/202 ALU is 16 bits wide and
is capable of addition, subtraction, bit shifts and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending
on the operation, the ALU can affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV) and
Digit Carry (DC) Status bits in the SR register. The C
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The dsPIC33FJ12GP201/202 CPU incorporates hardware support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit-divisor division.
Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR
bits affected by each instruction.
3.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed-sign
operation in several MCU multiplication modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
•
•
•
•
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
3.6
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The dsPIC33FJ12GP201/202 is a single-cycle instruction flow architecture; therefore, concurrent operation of
the DSP engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
can be used concurrently by the same instruction
(e.g., ED, EDAC).
The DSP engine can also perform accumulator-to-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
•
•
•
•
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for ACCA (SATA),
ACCB (SATB) and writes to data memory
(SATDW)
• Accumulator Saturation mode selection (ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
Instruction
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
A=0
Yes
No
No
Yes
No
Yes
No
No
No
Yes
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
No change in A
A=x*y
A=x2
A=–x*y
A=A–x*y
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m+1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 25
dsPIC33FJ12GP201/202
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
Zero Backfill
16
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS70264E-page 26
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit.
• The range of an N-bit 2’s complement integer is
-2N-1 to 2N-1 – 1
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including ‘0’
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF)
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte- or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit
adder/subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
© 2007-2011 Microchip Technology Inc.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented)
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously,
and
the
SAT
(CORCON) and ACCSAT (CORCON) mode
control bits to determine when, and to what value, to
saturate.
Six STATUS register bits have been provided to
support saturation and overflow:
• OA:
• OB:
• SA:
ACCA overflowed into guard bits
ACCB overflowed into guard bits
ACCA saturated (bit 31 overflow and
saturation)
or
• SB:
ACCA overflowed into guard bits and
saturated (bit 39 overflow and saturation)
ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when OA and OB are set and
the corresponding Overflow Trap Flag Enable bits
(OVATE, OVBTE) in the INTCON1 register are set
(refer to Section 7.0 “Interrupt Controller”). This
allows the user application to take immediate action; for
example, to correct system gain.
DS70264E-page 27
dsPIC33FJ12GP201/202
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow, and therefore, indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 register is set, the SA and SB bits will
generate an arithmetic warning trap when saturation is
disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programs can check one bit in the
STATUS register to determine whether either accumulator has overflowed, or one bit to determine whether
either accumulator has saturated. This is useful for
complex number arithmetic, which typically uses both
accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
value (0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user application. This condition is
referred to as ‘super saturation’ and provides
protection against erroneous data or unexpected
algorithm problems (such as gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
3.6.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator which is not targeted by the
instruction into data space memory. The write is
DS70264E-page 28
performed across the X bus into combined X and Y
address space. The following addressing modes are
supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
3.6.2.3
Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least
significant word (lsw) is simply discarded.
Conventional rounding will zero-extend bit 15 of the
accumulator and will add it to the ACCxH word (bits 16
through 31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged
A consequence of this algorithm is that over a succession of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the LSb (bit 16 of
the accumulator) of ACCxH is examined.
• If it is ‘1’, ACCxH is incremented
• If it is ‘0’, ACCxH is not modified. Assuming that
bit 16 is effectively random in nature, this scheme
removes any rounding bias that may accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 3.6.2.4 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator
write-back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
3.6.2.4
Data Space Write Saturation
3.6.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
• For input data greater than 0x007FFF, data written to memory is forced to the maximum positive
1.15 value, 0x7FFF
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The MSb of the source (bit 39) is used to determine the
sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 29
dsPIC33FJ12GP201/202
NOTES:
DS70264E-page 30
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
4.0
Note:
MEMORY ORGANIZATION
4.1
The program address memory space of the
dsPIC33FJ12GP201/202 devices is 4M instructions.
The space is addressable by a 24-bit value derived
either from the 23-bit PC during program execution, or
from table operation or data space remapping as
described in Section 4.6 “Interfacing Program and
Data Memory Spaces”.
This data sheet summarizes the features
of the dsPIC33FJ12GP201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Program
Memory”
(DS70202)
of
the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
The dsPIC33FJ12GP201/202 architecture features
separate program and data memory spaces and
buses. This architecture also allows the direct access
of program memory from the data space during code
execution.
FIGURE 4-1:
Program Address Space
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory map for the dsPIC33FJ12GP201/202
family of devices is shown in Figure 4-1.
PROGRAM MEMORY FOR dsPIC33FJ12GP201/202 DEVICES
User Memory Space
dsPIC33FJ12GP201/202
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(4K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x001FFE
0x002000
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Configuration Memory Space
Reserved
Device Configuration
Registers
Reserved
DEVID (2)
© 2007-2011 Microchip Technology Inc.
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
DS70264E-page 31
dsPIC33FJ12GP201/202
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.2
The dsPIC33FJ12GP201/202 CPU has a separate
16-bit-wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. The data
memory map is shown in Figure 4-3.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
All Effective Addresses (EAs) in the data memory
space are 16 bits wide and point to bytes within the
data space. This arrangement gives a data space
address range of 64 Kbytes or 32K words. The lower
half of the data memory space (that is, when
EA = 0) is used for implemented memory
addresses, while the upper half (EA = 1) is
reserved for the Program Space Visibility area (see
Section 4.6.3 “Reading Data From Program Memory Using Program Space Visibility”).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
4.1.2
Microchip dsPIC33FJ12GP201/202 devices implement
up to 1 Kbyte of data memory. Should an EA point to a
location outside of this area, an all-zero word or byte
will be returned.
INTERRUPT AND TRAP VECTORS
All dsPIC33FJ12GP201/202 devices reserve the
addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user application at 0x000000, with the actual
address for the start of code at 0x000002.
4.2.1
msw
Address
PROGRAM MEMORY ORGANIZATION
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS70264E-page 32
least significant word (lsw)
most significant word (msw)
23
0x000001
0x000003
0x000005
0x000007
DATA SPACE WIDTH
The data memory space is organized in byte addressable, 16-bit-wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
dsPIC33FJ12GP201/202 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt
vector tables is provided in Section 7.1 “Interrupt
Vector Table”.
FIGURE 4-2:
Data Address Space
Instruction Width
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the dsPIC33FJ12GP201/202 instruction set
supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing
mode [Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel byte-wide
entities with shared (word) address decoding, but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches
the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the instruction
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then executed, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
4.2.3
SFR SPACE
The first 2 Kbytes of the near data space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ12GP201/202 core and peripheral modules
for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 4-1
through Table 4-21.
Note:
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV class of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an address pointer.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternately, for 16-bit unsigned data, user
applications can clear the MSB of any W register by
executing a zero-extend (ZE) instruction on the
appropriate address.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 33
dsPIC33FJ12GP201/202
FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJ12GP201/202 DEVICES WITH 1 KB RAM
MSB
Address
2 Kbyte
SFR Space
1 Kbyte
SRAM Space
16 bits
MSb
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x09FF
0x0A01
X Data RAM (X)
Y Data RAM (Y)
0x0BFF
0x0C01
0x09FE
0x0A00
8 Kbyte
Near Data Space
0x0BFE
0x0C00
0x1FFFF
0x2000
0x8001
0x8000
X Data
Unimplemented (X)
0xFFFF
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
fast Fourier transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
DS70264E-page 34
0x07FE
0x0800
0x1FFF
0x2001
Optionally
Mapped
into Program
Memory
4.2.5
LSB
Address
0xFFFE
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to
provide two concurrent data read paths.
Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing
mode restrictions. Bit-Reversed Addressing mode is
only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
© 2007-2011 Microchip Technology Inc.
© 2007-2011 Microchip Technology Inc.
TABLE 4-1:
SFR Name
CPU CORE REGISTERS MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
Accumulator A Low Word Register
0000
ACCAH
0024
Accumulator A High Word Register
0000
ACCAU
0026
Accumulator A Upper Word Register
0000
ACCBL
0028
Accumulator B Low Word Register
0000
ACCBH
002A
Accumulator B High Word Register
0000
ACCBU
002C
Accumulator B Upper Word Register
0000
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
Program Counter High Byte Register
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Page Address Pointer Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Memory Visibility Page Address Pointer Register
0000
RCOUNT
0036
Repeat Loop Counter Register
xxxx
DCOUNT
0038
DCOUNT
xxxx
DS70264E-page 35
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
0000
DOSTARTL
—
—
—
—
—
—
—
—
—
—
0
xxxx
0
xxxx
DOSTARTH
00xx
DOENDL
DOENDH
0040
—
—
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
IPL0
RA
N
OV
Z
C
CORCON
0044
—
—
—
US
EDT
SATA
SATB
SATDW
ACCSAT
IPL3
PSV
RND
IF
MODCON
0046
XMODEN
YMODEN
—
—
Legend:
DL
BWM
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DOENDH
YWM
00xx
XWM
0000
0020
0000
dsPIC33FJ12GP201/202
WREG0
CPU CORE REGISTERS MAP (CONTINUED)
SFR
Addr
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
XMODSRT
0048
XS
0
xxxx
XMODEND
004A
XE
1
xxxx
YMODSRT
004C
YS
0
xxxx
YMODEND
004E
YE
1
xxxx
XBREV
0050
BREN
DISICNT
0052
—
Legend:
—
xxxx
Disable Interrupts Counter Register
xxxx
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP202
SFR
Name
SFR
Addr
Bit 15
Bit 14
CNEN1
0060
CN15IE
CNEN2
0062
—
CNPU1
0068
CNPU2
006A
Legend:
XB
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
CN14IE
CN13IE
CN30IE
CN29IE
CN12IE
CN11IE
—-
—
—
CN7IE
—
CN27IE
—
—
CN24IE
CN23IE
—
—
—
CN7PUE
CN6PUE
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
—
CN30PUE CN29PUE
—
CN27PUE
—
—
Bit 8
Bit 7
Bit 6
Bit 0
All
Resets
CN1IE
CN0IE
0000
—
CN16IE
0000
CN1PUE
CN0PUE
0000
CN16PUE
0000
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN22IE
CN21IE
—
—
—
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN24PUE CN23PUE CN22PUE CN21PUE
—
—
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP201
© 2007-2011 Microchip Technology Inc.
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
—
—
—
CN12IE
CN11IE
—
—
—
—
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CNEN2
0062
—
CN30IE
CN29IE
—
—
—
—
—
CN23IE
CN22IE
CN21IE
—
—
—
—
—
0000
CNPU1
0068
—
—
—
—
—
—
—
—
CN5PUE
CNPU2
006A
—
—
—
—
Legend:
CN30PUE CN29PUE
CN12PUE CN11PUE
—
—
CN23PUE CN22PUE CN21PUE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
—
—
—
—
—
0000
0000
dsPIC33FJ12GP201/202
DS70264E-page 36
TABLE 4-1:
© 2007-2011 Microchip Technology Inc.
TABLE 4-4:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr
INTCON1
0080
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE
INTCON2
0082
ALTIVT
DISI
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
—
—
Bit 10
—
Bit 9
Bit 8
OVBTE
COVTE
—
—
Bit 7
Bit 6
SFTACERR DIV0ERR
Bit 5
—
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
MATHERR ADDRERR STKERR
—
—
INT2EP
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
IFS0
0084
—
—
AD1IF
U1TXIF
U1RXIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
—
—
INT2IF
—
—
—
—
—
IC8IF
IC7IF
—
INT1IF
CNIF
—
MI2C1IF
SI2C1IF
0000
IFS4
008C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U1EIF
—
0000
IEC0
0094
—
—
AD1IE
U1TXIE
U1RXIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
—
—
INT2IE
—
—
—
—
—
IC8IE
IC7IE
—
INT1IE
CNIE
—
IEC4
009C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IPC0
00A4
—
IPC1
00A6
IPC2
00A8
IPC3
00AA
—
—
—
—
—
IPC4
00AC
—
CNIP
—
—
—
—
IPC5
00AE
—
IC8IP
—
IPC7
00B2
—
—
—
—
—
—
—
—
—
INT2IP
—
—
—
—
IPC16
00C4
—
—
—
—
—
—
—
—
—
U1EIP
—
—
—
—
INTTREG
00E0
—
—
—
—
—
—
T2IP
—
U1RXIP
—
—
—
SPI1IE SPI1EIE
OC1IP
—
—
OC2IP
—
SPI1IP
IC7IP
ILR>
IC1IP
—
—
IC2IP
—
—
SPI1EIP
—
—
AD1IP
—
MI2C1IP
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
MI2C1IE SI2C1IE
U1EIE
—
INT0IP
—
—
0000
0000
4444
—
4440
T3IP
4444
—
U1TXIP
0044
—
SI2C1IP
4044
—
INT1IP
VECNUM
4404
0040
0040
0000
DS70264E-page 37
dsPIC33FJ12GP201/202
Legend:
T1IP
SPI1IF SPI1EIF
SFR Name
TIMER REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
0000
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
Bit 4
Bit 3
Legend:
TSIDL
—
—
—
—
—
—
FFFF
TGATE
SFR Name
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
—
TSYNC
TCS
—
0000
FFFF
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Input 1 Capture Register
—
xxxx
ICTMR
0000
Input 2 Capture Register
—
—
ICSIDL
—
—
—
—
—
xxxx
ICTMR
0000
Input 7 Capture Register
—
—
ICSIDL
—
—
—
—
—
xxxx
ICTMR
0000
Input 8Capture Register
—
—
ICSIDL
—
—
—
—
—
xxxx
ICTMR
0000
© 2007-2011 Microchip Technology Inc.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
Legend:
TCKPS
INPUT CAPTURE REGISTER MAP
SFR
Addr
SFR Name
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
Legend:
TON
0000
—
—
—
—
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 5
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
—
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
—
OCFLT
OCTSEL
OCM
0000
dsPIC33FJ12GP201/202
DS70264E-page 38
TABLE 4-5:
© 2007-2011 Microchip Technology Inc.
TABLE 4-8:
I2C1 REGISTER MAP
SFR Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
Address Mask Register
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
SFR Name
SFR
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
0220
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U1STA
0222
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U1TXREG
0224
—
—
—
—
—
—
—
UART Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
UART Receive Register
0000
U1BRG
0228
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10:
SFR
Name
FERR
OERR
Baud Rate Generator Prescaler
0000
SPI1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
SPI1 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
0000
0000
0000
DS70264E-page 39
dsPIC33FJ12GP201/202
U1MODE
URXISEL
PDSEL
Bit 0
PERIPHERAL PIN SELECT INPUT REGISTER MAP
File
Name
Addr
Bit 15
Bit 14
Bit 13
RPINR0
0680
—
—
—
RPINR1
0682
—
—
—
RPINR3
0686
—
—
—
RPINR7
068E
—
—
—
RPINR10
0694
—
—
—
RPINR11
0696
—
—
—
RPINR18
06A4
—
—
—
RPINR20
06A8
—
—
—
RPINR21
06AA
—
—
—
Legend:
Bit 11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
—
1F00
—
—
—
INT2R
001F
T3CKR
—
—
—
T2CKR
1F1F
IC2R
—
—
—
IC1R
1F1F
IC8R
—
—
—
IC7R
1F1F
—
—
—
OCFAR
001F
U1CTSR
—
—
—
U1RXR
1F1F
SCK1R
—
—
—
SDI1R
1F1F
—
—
—
SS1R
001F
Bit 10
Bit 9
Bit 8
INT1R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
File
Name
Bit 12
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12GP202
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RPOR0
06C0
—
—
—
RP1R
—
—
—
RP0R
0000
RPOR1
06C2
—
—
—
RP3R
—
—
—
RP2R
0000
RPOR2
06C4
—
—
—
RP5R
—
—
—
RP4R
0000
RPOR3
06C6
—
—
—
RP7R
—
—
—
RP6R
0000
RPOR4
06C8
—
—
—
RP9R
—
—
—
RP8R
0000
RPOR5
06CA
—
—
—
RP11R
—
—
—
RP10R
0000
RPOR6
06CC
—
—
—
RP13R
—
—
—
RP12R
0000
RPOR7
06CE
—
—
—
RP15R
—
—
—
RP14R
0000
© 2007-2011 Microchip Technology Inc.
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13:
File Name
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ12GP201
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
—
—
—
RPOR2
06C4
—
—
—
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
—
—
RP1R
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 7
Bit 6
Bit 5
—
—
—
RP0R
0000
—
—
—
RP4R
0000
RPOR3
06C6
—
—
—
RP7R
—
—
—
RPOR4
06C8
—
—
—
RP9R
—
—
—
RP8R
0000
RPOR7
Legend:
06CE
—
—
—
RP15R
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
RP14R
0000
—
—
—
—
—
0000
dsPIC33FJ12GP201/202
DS70264E-page 40
TABLE 4-11:
© 2007-2011 Microchip Technology Inc.
TABLE 4-14:
ADC1 REGISTER MAP FOR dsPIC33FJ12GP201
Bit 15
ADC1BUF0
0300
ADC Data Buffer 0
xxxx
ADC1BUF1
0302
ADC Data Buffer 1
xxxx
ADC1BUF2
0304
ADC Data Buffer 2
xxxx
ADC1BUF3
0306
ADC Data Buffer 3
xxxx
ADC1BUF4
0308
ADC Data Buffer 4
xxxx
ADC1BUF5
030A
ADC Data Buffer 5
xxxx
ADC1BUF6
030C
ADC Data Buffer 6
xxxx
ADC1BUF7
030E
ADC Data Buffer 7
xxxx
ADC1BUF8
0310
ADC Data Buffer 8
xxxx
ADC1BUF9
0312
ADC Data Buffer 9
xxxx
ADC1BUFA
0314
ADC Data Buffer 10
xxxx
ADC1BUFB
0316
ADC Data Buffer 11
xxxx
ADC1BUFC
0318
ADC Data Buffer 12
xxxx
ADC1BUFD
031A
ADC Data Buffer 13
xxxx
ADC1BUFE
031C
ADC Data Buffer 14
xxxx
ADC1BUFF
031E
ADC Data Buffer 15
AD1CON1
0320
AD1CON2
0322
AD1CON3
0324
AD1CHS123
AD1CHS0
—
Bit 13
ADSIDL
VCFG
Bit 12
Bit 11
Bit 10
Bit 9
—
—
AD12B
FORM
—
—
CSCNA
CHPS
ADRC
—
—
0326
—
—
—
0328
CH0NB
—
—
AD1PCFGL
032C
—
—
—
—
—
—
—
AD1CSSL
0330
—
—
—
—
—
—
—
Legend:
Bit 8
Bit 7
Bit 6
Bit 5
—
—
—
Bit 2
SIMSAM
ASAM
SMPI
SAMC
—
Bit 3
Bit 1
Bit 0
xxxx
SSRC
BUFS
Bit 4
SAMP
DONE
BUFM
ALTS
ADCS
CH123NB
CH123SB
—
—
—
—
—
—
PCFG7
PCFG6
—
—
PCFG3
PCFG2
PCFG1
PCFG0
0000
—
CSS7
CSS6
—
—
CSS3
CSS2
CSS1
CSS0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
0000
CH0NA
CH0SB
—
0000
CH123NA
CH123SA
CH0SA
0000
0000
DS70264E-page 41
dsPIC33FJ12GP201/202
Addr
ADON
Bit 14
All
Resets
File Name
ADC1 REGISTER MAP FOR dsPIC33FJ12GP202
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
File Name
Addr
ADC1BUF0
0300
ADC Data Buffer 0
xxxx
ADC1BUF1
0302
ADC Data Buffer 1
xxxx
ADC1BUF2
0304
ADC Data Buffer 2
xxxx
ADC1BUF3
0306
ADC Data Buffer 3
xxxx
ADC1BUF4
0308
ADC Data Buffer 4
xxxx
ADC1BUF5
030A
ADC Data Buffer 5
xxxx
ADC1BUF6
030C
ADC Data Buffer 6
xxxx
ADC1BUF7
030E
ADC Data Buffer 7
xxxx
ADC1BUF8
0310
ADC Data Buffer 8
xxxx
ADC1BUF9
0312
ADC Data Buffer 9
xxxx
ADC1BUFA
0314
ADC Data Buffer 10
xxxx
ADC1BUFB
0316
ADC Data Buffer 11
xxxx
ADC1BUFC
0318
ADC Data Buffer 12
xxxx
© 2007-2011 Microchip Technology Inc.
ADC1BUFD
031A
ADC Data Buffer 13
xxxx
ADC1BUFE
031C
ADC Data Buffer 14
xxxx
ADC1BUFF
031E
AD1CON1
0320
AD1CON2
0322
AD1CON3
0324
ADRC
—
—
AD1CHS123
0326
—
—
—
AD1CHS0
0328
CH0NB
—
—
AD1PCFGL
032C
—
—
0330
—
—
AD1CSSL
Legend:
ADC Data Buffer 15
ADON
—
ADSIDL
xxxx
—
—
AD12B
FORM
—
—
CSCNA
CHPS
—
—
CH0NA
—
—
—
—
—
—
PCFG9
PCFG8
PCFG7
PCFG6
—
—
—
—
CSS9
CSS8
CSS7
CSS6
VCFG
SSRC
BUFS
—
—
—
—
SIMSAM
ASAM
SMPI
SAMC
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
ADCS
CH123NB
CH123SB
CH0SB
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
—
—
CH123NA
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
CH0SA
0000
dsPIC33FJ12GP201/202
DS70264E-page 42
TABLE 4-15:
© 2007-2011 Microchip Technology Inc.
TABLE 4-16:
PORTA REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
02C0
—
—
—
—
—
—
—
—
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
001F
PORTA
02C2
—
—
—
—
—
—
—
—
—
—
—
RA4
RA3
RA2
RA1
RA0
xxxx
LATA
02C4
—
—
—
—
—
—
—
—
—
—
—
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
ODCA
02C6
—
—
—
—
—
—
—
—
—
—
—
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name
TABLE 4-17:
PORTB REGISTER MAP FOR dsPIC33FJ12GP202
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C8
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02CA
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CC
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
ODCB
02CE
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File Name
File Name
Addr
PORTB REGISTER MAP FOR dsPIC33FJ12GP201
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C8
—
—
—
—
TRISB9
TRISB8
TRISB7
—
—
TRISB4
—
—
TRISB1
TRISB0
C393
PORTB
02CA
RB15
RB14
—
—
—
—
RB9
RB8
RB7
—
—
RB4
—
—
RB1
RB0
xxxx
LATB
02CC
LATB15
LATB14
—
—
—
—
LATB9
LATB8
LATB7
—
—
LATB4
—
—
LATB1
LATB0
xxxx
ODCB
02CE
ODCB15
ODCB14
—
—
—
—
ODCB9
ODCB8
ODCB7
—
—
ODCB4
—
—
ODCB1
ODCB0
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19:
TRISB15 TRISB14
SYSTEM CONTROL REGISTER MAP
DS70264E-page 43
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
0740
TRAPR
IOPUWR
—
—
—
—
CM
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
OSCCON
0742
—
—
CF
—
LPOSCEN
OSWEN
0300(2)
CLKDIV
0744
ROI
PLLFBD
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
Legend:
Note 1:
2:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on the type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by the type of Reset.
COSC
—
DOZE
DOZEN
NOSC
CLKLOCK IOLOCK
LOCK
FRCDIV
PLLPOST
—
PLLPRE
PLLDIV
—
—
—
3040
0030
TUN
0000
dsPIC33FJ12GP201/202
TABLE 4-18:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
0766
—
—
—
—
—
—
—
—
NVMKEY
Legend:
Note 1:
Bit 2
Bit 1
Bit 0
All
Resets
0000(1)
NVMOP
NVMKEY
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-21:
File Name
Bit 3
Addr
PMD REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
—
—
T3MD
T2MD
T1MD
—
—
—
I2C1MD
—
U1MD
—
SPI1MD
—
—
AD1MD
0000
PMD2
0772
IC8MD
IC7MD
—
—
—
—
IC2MD
IC1MD
—
—
—
—
—
—
OC2MD
OC1MD
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ12GP201/202
DS70264E-page 44
TABLE 4-20:
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
4.2.6
4.2.7
SOFTWARE STACK
In addition to its use as a working register, the W15
register in the dsPIC33FJ12GP201/202 devices is also
used as a software Stack Pointer. The Stack Pointer
always points to the first available free word and grows
from lower to higher addresses. It pre-decrements for
stack pops and post-increments for stack pushes, as
shown in Figure 4-4. For a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSB
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM is forced to ‘0’
because all stack operations must be word-aligned.
When an EA is generated using W15 as a source or
destination pointer, the resulting address is compared
with the value in SPLIM. If the contents of the Stack
Pointer (W15) and the SPLIM register are equal and a
push operation is performed, a stack error trap will not
occur. However, the stack error trap will occur on a subsequent push operation. For example, to cause a stack
error trap when the stack grows beyond address
0x0C00 in RAM, initialize the SPLIM with the value
0x0BFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the SFR space.
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code, when it is enabled. SSRAM
(Secure RAM segment for RAM) is accessible only
from the Secure Segment Flash code, when it is
enabled. See Table 4-1 for an overview of the BSRAM
and SSRAM SFRs.
4.3
Instruction Addressing Modes
The addressing modes shown in Table 4-22 form the
basis of the addressing modes that are optimized to
support the specific features of individual instructions.
The addressing modes provided in the MAC class of
instructions differ from those provided in the other
instruction types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
MCU INSTRUCTIONS
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
The three-operand MCU instructions are of the form:
FIGURE 4-4:
where:
Stack Grows Toward
Higher Address
0x0000
15
CALL STACK FRAME
Operand 1 is always a working register (that is, the
addressing mode can only be register direct), which is
referred to as Wb.
0
PC
000000000 PC
Operand 3 = Operand 1 Operand 2
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
Operand 2 can be a W register, fetched from data
memory, or a 5-bit literal. The result location can be
either a W register or a data memory location. The following addressing modes are supported by MCU
instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
© 2007-2011 Microchip Technology Inc.
Not all instructions support all the
addressing
modes
given
above.
Individual instructions can support different subsets of these addressing modes.
DS70264E-page 45
dsPIC33FJ12GP201/202
TABLE 4-22:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the Effective Address (EA.)
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
4.3.3
The sum of Wn and a literal forms the EA.
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU instructions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
4.3.4
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC, and MSC), also
referred to as MAC instructions, use a simplified set of
addressing modes to allow the user application to
effectively manipulate the data pointers through register
indirect tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
DS70264E-page 46
MAC INSTRUCTIONS
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.3.5
OTHER INSTRUCTIONS
In addition to the addressing modes outlined previously, some instructions use literal constants of various
sizes. For example, BRA (branch) instructions use
16-bit signed literals to specify the branch destination
directly, whereas the DISI instruction uses a 14-bit
unsigned literal field. In some instructions, such as ADD
Acc, the source of an operand or result is implied by
the opcode itself. Certain operations, such as NOP, do
not have any operands.
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
4.4
Modulo Addressing
Note:
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be configured to operate in only one direction, as there are
certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers), based upon the direction of the circular buffer.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
4.4.1
START AND END ADDRESS
The Modulo Addressing scheme requires that a starting
and ending address be specified and loaded into the
16-bit Modulo Buffer Address registers: XMODSRT,
XMODEND, YMODSRT and YMODEND (see
Table 4-1).
FIGURE 4-5:
Y space Modulo Addressing EA calculations assume word-sized data (LSB of
every EA is always clear).
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that will
operate with Modulo Addressing:
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled
• If YWM = 15, Y AGU Modulo Addressing is
disabled
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM), to
which Modulo Addressing is to be applied, is stored in
MODCON. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON.
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
MOV
#0x0000, W0
;W0 holds buffer fill value
MOV
#0x1110, W1
;point W1 to buffer
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations
;fill the next location
;increment the fill value
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
© 2007-2011 Microchip Technology Inc.
DS70264E-page 47
dsPIC33FJ12GP201/202
4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the EA
calculation associated with any W register.
Address boundaries check for addresses equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
It is important to realize that the address boundaries
also check for addresses less than or greater than
these addresses. Address changes can, therefore,
jump beyond boundaries and still be adjusted correctly.
Note:
4.5
The modulo corrected effective address is
written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the effective
address. When an address offset (such as
[W7+W2]) is used, Modulo Address correction is performed, but the contents of
the register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
XB is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume
word-sized data (LSB of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or
Post-Increment Addressing, and word-sized data
writes. It will not function for any other addressing
mode or for byte-sized data, and normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB), and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority when active for the X WAGU, and X
WAGU Modulo Addressing will be disabled. However, Modulo Addressing will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
DS70264E-page 48
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
FIGURE 4-6:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2
b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word, Bit-Reversed Buffer
TABLE 4-23:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
© 2007-2011 Microchip Technology Inc.
DS70264E-page 49
dsPIC33FJ12GP201/202
4.6
4.6.1
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The dsPIC33FJ12GP201/202 architecture uses a
24-bit-wide program space and a 16-bit-wide data
space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the MSb of TBLPAG is used to determine if
the operation occurs in the user memory (TBLPAG
= 0) or the configuration memory (TBLPAG = 1).
Aside from normal execution, the Microchip
dsPIC33FJ12GP201/202 architecture provides two
methods by which program space can be accessed
during operation:
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
• Using table instructions to access individual
bytes, or words, anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for lookups
from a large table of static data. The application can
only access the lsw of the program word.
TABLE 4-24:
Table 4-24 and Figure 4-7 show how the program EA is
created for table operations and remapping accesses
from the data EA.
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
Program Space Address
Program Space Visibility
(Block Remap/Read)
0xx
xxxx
xxxx
TBLPAG
0xxx xxxx
User
PC
0
Configuration
Note 1:
ADDRESSING PROGRAM SPACE
0
xxxx
xxxx xxx0
Data EA
xxxx xxxx xxxx xxxx
TBLPAG
Data EA
1xxx xxxx
xxxx xxxx xxxx xxxx
0
PSVPAG
0
xxxx xxxx
Data EA(1)
xxx xxxx xxxx xxxx
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG.
DS70264E-page 50
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
FIGURE 4-7:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
0
EA
1
0
PSVPAG
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ to maintain word alignment of
data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 51
dsPIC33FJ12GP201/202
4.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two
16-bit-wide word address spaces, residing side by side,
each with the same address range. TBLRDL and
TBLWTL access the space that contains the least
significant data word. TBLRDH and TBLWTH access the
space that contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
• TBLRDL (Table Read Low): In Word mode, this
instruction maps the lower word of the program
space location (P) to a data address
(D).
FIGURE 4-8:
In Byte mode, either the upper or lower byte of the
lower program word is mapped to the lower byte of
a data address. The upper byte is selected when
Byte Select is ‘1’; the lower byte is selected when
it is ‘0’.
• TBLRDH (Table Read High): In Word mode, this
instruction maps the entire upper word of a program
address (P) to a data address. Note that
D, the ‘phantom byte’, will always be ‘0’.
In Byte mode, this instruction maps the upper or
lower byte of the program word to D of the
data address, as in the TBLRDL instruction. Note
that the data will always be ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page
is located in the user memory space. When
TBLPAG = 1, the page is located in configuration
space.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
0x020000
0x030000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
0x800000
DS70264E-page 52
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
4.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored constant data from the data space without the need to use
special instructions (such as TBLRDL or TBLRDH).
Program space access through the data space occurs
if the MSb of the data space EA is ‘1’ and program
space visibility is enabled by setting the PSV bit in the
Core Control register (CORCON). The location of
the program memory space to be mapped into the data
space is determined by the Program Space Visibility
Page register (PSVPAG). This 8-bit register defines
any one of 256 possible pages of 16K words in
program space. In effect, PSVPAG functions as the
upper 8 bits of the program memory address, with the
15 bits of the EA functioning as the lower bits. By
incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Although each data space address 0x8000 and higher
maps directly into a corresponding program memory
address (see Figure 4-9), only the lower 16 bits of the
FIGURE 4-9:
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
PSV access is temporarily disabled during
table reads/writes.
Note:
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to access data to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
0x000000
0x0000
Data EA
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
0x800000
© 2007-2011 Microchip Technology Inc.
...while the lower 15 bits
of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
DS70264E-page 53
dsPIC33FJ12GP201/202
NOTES:
DS70264E-page 54
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
5.0
unprogrammed devices and then program the digital
signal controller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the dsPIC33FJ12GP201/202 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash Programming”
(DS70191)
of
the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536
bytes).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
The dsPIC33FJ12GP201/202 devices contain internal
Flash program memory for storing and executing application code. The memory is readable, writable, and
erasable during normal operation over the entire VDD
range.
Flash memory can be programmed in two ways:
Regardless of the method used, all programming of
Flash memory is done with the table-read and tablewrite instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to bits of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJ12GP201/202 device to be
serially programmed while in the end application circuit.
This is done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows users to manufacture boards with
FIGURE 5-1:
Table Instructions and Flash
Programming
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
User/Configuration
Space Select
© 2007-2011 Microchip Technology Inc.
16 bits
24-bit EA
Byte
Select
DS70264E-page 55
dsPIC33FJ12GP201/202
5.2
RTSP Operation
The dsPIC33FJ12GP201/202 Flash program memory
array is organized into rows of 64 instructions or 192
bytes. RTSP allows the user application to erase a
page of memory, which consists of eight rows (512
instructions), and to program one row or one word. The
8-row erase pages and single row write rows are edgealigned from the beginning of program memory, on
boundaries of 1536 bytes and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, and then perform a series of TBLWT
instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions
are required to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 22-18) and the value of the FRC Oscillator
Tuning register (see Register 8-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see Table 22-12).
EQUATION 5-1:
PROGRAMMING TIME
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN bits (see
Register 8-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2:
MINIMUM ROW WRITE
TIME
11064 Cycles
T RW = ------------------------------------------------------------------------------------------------ = 1.435ms
7.37 MHz × ( 1 + 0.05 ) × ( 1 – 0.00375 )
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
MAXIMUM ROW WRITE
TIME
11064 Cycles
T RW = ------------------------------------------------------------------------------------------------ = 1.586ms
7.37 MHz × ( 1 – 0.05 ) × ( 1 – 0.00375 )
Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the
operation is finished.
5.4
Control Registers
Two SFRs are used to read and write the program
Flash memory:
• NVMCON: Flash Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed, and the start of the programming cycle.
NVMKEY (Register 5-2) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register.
Refer to Section 5.3 “Programming Operations” for
further details.
T
--------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy )% × ( FRC Tuning )%
DS70264E-page 56
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
U-0
bit 8
R/W-0(1)
—
U-0
ERASE
—
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
(2)
—
NVMOP
bit 7
bit 0
SO = Settable only bit
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware when operation is complete.
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP on the next WR command
0 = Perform the program operation specified by NVMOP on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP: NVM Operation Select bits(2)
If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erase General Segment
1100 = Erase Secure Segment
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
Note 1:
2:
These bits can only be Reset on POR.
All other combinations of NVMOP are unimplemented.
© 2007-2011 Microchip Technology Inc.
DS70264E-page 57
dsPIC33FJ12GP201/202
REGISTER 5-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY
bit 7
bit 0
Legend:
SO = Settable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
NVMKEY: Key Register (write-only) bits
DS70264E-page 58
x = Bit is unknown
© 2007-2011 Microchip Technology Inc.
dsPIC33FJ12GP201/202
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
Programmers can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a) Set the NVMOP bits (NVMCON) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON) and WREN
(NVMCON) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 5-3.
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash memory is done, the WR bit is cleared
automatically.
Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
© 2007-2011 Microchip Technology Inc.
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority
