dsPIC33FJ16(GP/MC)101/102 AND
dsPIC33FJ32(GP/MC)101/102/104
16-Bit Digital Signal Controllers
(up to 32-Kbyte Flash and 2-Kbyte SRAM)
Operating Conditions
Advanced Analog Features
• 3.0V to 3.6V, -40°C to +125°C, DC to 16 MIPS
• ADC module:
- 10-bit, 1.1 Msps with four S&H
- Four analog inputs on 18-pin devices and up to
14 analog inputs on 44-pin devices
• Flexible and Independent ADC Trigger Sources
• Three Comparator modules
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
• 3.0V to 3.6V, -40°C to +150°C, DC to 5 MIPS
Core: 16-Bit dsPIC33F CPU
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Clock Management
•
•
•
•
•
±0.25% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
1 mA/MHz Dynamic Current (typical)
30 µA IPD Current (typical)
PWM
•
•
•
•
Up to Three PWM Pairs
Two Dead-Time Generators
31.25 ns PWM Resolution
PWM Support for:
- Inverters, PFC, UPS
- BLDC, PMSM, ACIM, SRM
• Class B-Compliant Fault Inputs
• Possibility of ADC Synchronization with PWM Signal
Timers/Output Compare/Input Capture
• Up to Five General Purpose Timers:
- One 16-bit and up to two 32-bit timers/counters
• Two Output Compare modules
• Three Input Capture modules
• Peripheral Pin Select (PPS) to allow Function Remap
Communication Interfaces
• UART module (4 Mbps):
- With support for LIN/J2602 Protocols and IrDA®
• 4-Wire SPI module (8 MHz maximum speed):
- Remappable pins in 32-Kbyte Flash devices
• I2C™ module (400 kHz)
Input/Output
• Sink/Source 10 mA or 6 mA, Pin-Specific for Standard
VOH/VOL, up to 16 mA or 12 mA for Non-Standard VOH1
• 5V Tolerant Pins
• Up to 20 Selectable Open-Drain and Pull-ups
• Three External Interrupts (two are remappable)
Qualification and Class B Support
• AEC-Q100 REV G (Grade 0 -40°C to +150°C)
• Class B Safety Library, IEC 60730, UDE Certified
Debugger Development Support
• In-Circuit and In-Application Programming
• Up to Three Complex Data Breakpoints
• Trace and Run-Time Watch
2011-2014 Microchip Technology Inc.
DS70000652F-page 1
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
dsPIC33FJ16(GP/MC)101/102 AND
dsPIC33FJ32(GP/MC)101/102/104
PRODUCT FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in
Table 1. The following pages show their pinout
diagrams.
dsPIC33FJ16(GP/MC)101/102 DEVICE FEATURES
Remappable Pins
16-bit Timer(1,2)
Input Capture
Output Compare
UART
External Interrupts(3)
SPI
Motor Control PWM
PWM Faults
RTCC
I2C™
Comparators
CTMU
I/O Pins
16
1
8
3
3
2
1
3
1
—
—
1 ADC,
4-ch
Y
1
3
Y
13 PDIP,
SOIC
20
16
1
8
3
3
2
1
3
1
—
—
1 ADC,
4-ch
Y
1
3
Y
15 SSOP
28
16
1
16
3
3
2
1
3
1
—
—
1 ADC,
6-ch
Y
1
3
Y
21 SPDIP,
SOIC,
SSOP,
QFN
36
16
1
16
3
3
2
1
3
1
—
—
1 ADC,
6-ch
Y
1
3
Y
21 VTLA
dsPIC33FJ16MC101
20
16
1
10
3
3
2
1
3
1
6-ch
1
1 ADC,
4-ch
Y
1
3
Y
15 PDIP,
SOIC,
SSOP
dsPIC33FJ16MC102
28
16
1
16
3
3
2
1
3
1
6-ch
2
1 ADC,
6-ch
Y
1
3
Y
21 SPDIP,
SOIC,
SSOP,
QFN
36
16
1
16
3
3
2
1
3
1
6-ch
2
1 ADC,
6-ch
Y
1
3
Y
21 VTLA
dsPIC33FJ16GP101
dsPIC33FJ16GP102
Note 1:
2:
3:
Packages
RAM (Kbytes)
18
Device
10-Bit, 1.1 Msps ADC
Program Flash (Kbyte)
Remappable Peripherals
Pins
TABLE 1:
Two out of three timers are remappable.
One pair can be combined to create one 32-bit timer.
Two out of three interrupts are remappable.
DS70000652F-page 2
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
dsPIC33FJ32(GP/MC)101/102/104 DEVICE FEATURES
Remappable Pins
16-bit Timer(1,2)
Input Capture
Output Compare
UART
External Interrupts(3)
SPI
Motor Control PWM
PWM Faults
RTCC
I2C™
Comparators
CTMU
I/O Pins
32
2
8
5
3
2
1
3
1
—
—
1 ADC,
6-ch
Y
1
3
Y
13 PDIP,
SOIC
20
32
2
8
5
3
2
1
3
1
—
—
1 ADC,
6-ch
Y
1
3
Y
15 SSOP
28
32
2
16
5
3
2
1
3
1
—
—
1 ADC,
8-ch
Y
1
3
Y
21 SPDIP,
SOIC,
SSOP,
QFN
36
32
2
16
5
3
2
1
3
1
—
—
1 ADC,
8-ch
Y
1
3
Y
21 VTLA
dsPIC33FJ32GP104
44
32
2
26
5
3
2
1
3
1
—
—
1 ADC,
14-ch
Y
1
3
Y
35 TQFP,
QFN,
VTLA
dsPIC33FJ32MC101
20
32
2
10
5
3
2
1
3
1
6-ch
1
1 ADC,
6-ch
Y
1
3
Y
15 PDIP,
SOIC,
SSOP
dsPIC33FJ32MC102
28
32
2
16
5
3
2
1
3
1
6-ch
2
1 ADC,
8-ch
Y
1
3
Y
21 SPDIP,
SOIC,
SSOP,
QFN
36
32
2
16
5
3
2
1
3
1
6-ch
2
1 ADC,
8-ch
Y
1
3
Y
21 VTLA
44
32
2
26
5
3
2
1
3
1
6-ch
2
1 ADC,
14-ch
Y
1
3
Y
35 TQFP,
QFN,
VTLA
dsPIC33FJ32GP101
dsPIC33FJ32GP102
dsPIC33FJ32MC104
Note 1:
2:
3:
Packages
RAM (Kbytes)
18
Device
10-Bit, 1.1 Msps ADC
Program Flash (Kbyte)
Remappable Peripherals
Pins
TABLE 2:
Four out of five timers are remappable.
Two pairs can be combined to have up to two 32-bit timers.
Two out of three interrupts are remappable.
2011-2014 Microchip Technology Inc.
DS70000652F-page 3
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams
= Pins are up to 5V tolerant
18-Pin PDIP/SOIC
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
Note 1:
1
2
3
4
5
6
7
8
9
dsPIC33FJ32GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
dsPIC33FJ16GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
18
17
16
15
14
13
12
11
10
18
17
16
15
14
13
12
11
10
VDD
VSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VCAP
VSS
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
VDD
VSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VCAP
VSS
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
DS70000652F-page 4
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
20-Pin SSOP
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
Note 1:
1
2
3
4
5
6
7
8
9
10
dsPIC33FJ32GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
dsPIC33FJ16GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VDD
VCAP
VSS
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VDD
VCAP
VSS
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2011-2014 Microchip Technology Inc.
DS70000652F-page 5
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
28-Pin SPDIP/SOIC/SSOP
Note 1:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ32GP102
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
VDD
ASDA1/RP5(1)/CN27/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ16GP102
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
VDD
ASDA1/RP5(1)/CN27/RB5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP11(1)/CN15/RB11
RP10(1)/CN16/RB10
VCAP
VSS
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
RP11(1)/CN15/RB11
RP10(1)/CN16/RB10
VCAP
VSS
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
DS70000652F-page 6
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
20-Pin PDIP/SOIC/SSOP
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
Note 1:
2:
1
2
3
4
5
6
7
8
9
10
dsPIC33FJ32MC101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
1
2
3
4
5
6
7
8
9
10
dsPIC33FJ16MC101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
VDD
VSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
VCAP
SDA1/SDI1/PWM1L3/RP9(1)/CN21/RB9
SCL1/SDO1/PWM1H3/RP8(1)/CN22/RB8
FLTA1(2)/SCK1/INT0/RP7(1)/CN23/RB7
VDD
VSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
VCAP
SDA1/PWM1L3/RP9(1)/CN21/RB9
SCL1/PWM1H3/RP8(1)/CN22/RB8
FLTA1(2)/INT0/RP7(1)/CN23/RB7
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
2011-2014 Microchip Technology Inc.
DS70000652F-page 7
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
28-Pin SPDIP/SOIC/SSOP
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
VDD
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note 1:
2:
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1L3/RP11(1)/CN15/RB11
PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
SDA1/SDI1/RP9(1)/CN21/RB9
SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
dsPIC33FJ32MC102
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ16MC102
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
VDD
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
PWM1L3/RP11(1)/CN15/RB11
PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
SDA1/RP9(1)/CN21/RB9
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
DS70000652F-page 8
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
28-Pin QFN(2)
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
AVSS
MCLR
AVDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
21
RP13(1)/CN13/RB13
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
2
20
RP12(1)/CN14/RB12
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
3
19
RP11(1)/CN15/RB11
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4 dsPIC33FJ16GP102 18
RP10(1)/CN16/RB10
VSS
5
17
VCAP
OSCI/CLKI/CN30/RA2
6
16
VSS
OSCO/CLKO/CN29/RA3
7
15
SDA1/SDI1/RP9(1)/CN21/RB9
Note 1:
2:
SCL1/SDO1/RP8(1)/CN22/RB8
ASCL1/RP6(1)/CN24/RB6
SCK1/INT0/RP7(1)/CN23/RB7
ASDA1/RP5(1)/CN27/RB5
9 10 11 12 13 14
VDD
8
PGED3/SOSCI/RP4(1)/CN1/RB4
1
PGEC3/SOSCO/T1CK/CN0/RA4
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2014 Microchip Technology Inc.
DS70000652F-page 9
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
28-Pin QFN(2)
RTCC/RP14(1)/CN12/RB14
RP15(1)/CN11/RB15
AVSS
MCLR
AVDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
1
21
RP13(1)/CN13/RB13
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
2
20
RP12(1)/CN14/RB12
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
3
19
RP11(1)/CN15/RB11
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4 dsPIC33FJ32GP102 18
RP10(1)/CN16/RB10
VSS
Note 1:
2:
VCAP
6
16
VSS
OSCO/CLKO/CN29/RA3
7
15
SDA1/RP9(1)/CN21/RB9
SCL1/RP8 /CN22/RB8
(1)
INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
ASDA1/RP5(1)/CN27/RB5
9 10 11 12 13 14
VDD
8
PGEC3/SOSCOAN10//T1CK/CN0/RA4
17
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
5
OSCI/CLKI/CN30/RA2
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
DS70000652F-page 10
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
28-Pin QFN(2)
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
AVSS
MCLR
AVDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
(1)
1
21
(1)
2
20
PGED1/AN2/C2INA/C1INC/RP0 /CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
3
19
4 dsPIC33FJ16MC102 18
VSS
5
17
VCAP
OSCI/CLKI/CN30/RA2
6
16
VSS
OSCO/CLKO/CN29/RA3
7
15
SDA1/SDI1/RP9(1)/CN21/RB9
PWM1H3/RP10(1)/CN16/RB10
SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
9 10 11 12 13 14
VDD
PGED3/SOSCI/RP4(1)/CN1/RB4
8
PGEC3/SOSCO/T1CK/CN0/RA4
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
3:
PWM1H2/RP12(1)/CN14/RB12
PWM1L3/RP11(1)/CN15/RB11
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
Note 1:
2:
PWM1L2/RP13(1)/CN13/RB13
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
2011-2014 Microchip Technology Inc.
DS70000652F-page 11
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
28-Pin QFN(2)
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
AVSS
MCLR
AVDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
(1)
1
21
PWM1L2/RP13(1)/CN13/RB13
(1)
2
20
PWM1H2/RP12(1)/CN14/RB12
PGED1/AN2/C2INA/C1INC/RP0 /CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
3
19
4 dsPIC33FJ32MC102 18
PWM1L3/RP11(1)/CN15/RB11
VSS
5
17
VCAP
OSCI/CLKI/CN30/RA2
6
16
VSS
OSCO/CLKO/CN29/RA3
7
15
SDA1/RP9(1)/CN21/RB9
Note 1:
2:
3:
PWM1H3/RP10(1)/CN16/RB10
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
9 10 11 12 13 14
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
8
VDD
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM
Faults” for more information on the PWM Faults.
DS70000652F-page 12
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
36-Pin VTLA(2)
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
N/C
N/C
MCLR
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
= Pins are up to 5V tolerant
36
35
34
33
32
31
30
29
28
27
RP13(1)/CN13/RB13
1
26
RP12(1)/CN14/RB12
(1)
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
2
25
RP11(1)/CN15/RB11
(1)/CN6/RB2
3
24
RP10(1)/CN16/RB10
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/CN30/RA2
7
20
N/C
OSCO/CLKO/CN29/RA3
8
19
SDA1/SDI1/RP9(1)/CN21/RB9
PGED3/SOSCI/RP4(1)/CN1/RB4
9
Note 1:
2:
18
SCL1/SDO1/RP8 /CN22/RB8
16 17
(1)
VDD
15
SCK1/INT0/RP7(1)/CN23/RB7
N/C (Vss)
14
ASCL1/RP6 /CN24/RB6
13
(1)
12
N/C (VDD)
11
ASDA1/RP5(1)/CN27/RB5
10
N/C
dsPIC33FJ16GP102
PGEC3/SOSCO/T1CK/CN0/RA4
AN4/C3INC/C2INC/RP2
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2014 Microchip Technology Inc.
DS70000652F-page 13
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
36-Pin VTLA(2)
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
N/C
N/C
MCLR
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
= Pins are up to 5V tolerant
36
35
34 33
32
31
30
29
28
27
RP13(1)/CN13/RB13
1
26
RP12(1)/CN14/RB12
(1)
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
2
25
RP11(1)/CN15/RB11
(1)/CN6/RB2
3
24
RP10(1)/CN16/RB10
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/CN30/RA2
7
20
N/C
OSCO/CLKO/CN29/RA3
8
19
SDA1/RP9(1)/CN21/RB9
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
9
Note 1:
2:
15
N/C (Vss)
VDD
N/C (VDD)
ASDA1/RP5(1)/CN27/RB5
16 17
18
SCL1/RP8 /CN22/RB8
14
(1)
13
INT0/RP7(1)/CN23/RB7
12
ASCL1/RP6 /CN24/RB6
11
(1)
10
N/C
dsPIC33FJ32GP102
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
AN4/C3INC/C2INC/RP2
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
DS70000652F-page 14
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
36-Pin VTLA(2)
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
N/C
N/C
MCLR
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
= Pins are up to 5V tolerant
36
35
34
33
32
31
30
29
28
27
PWM1L2/RP13(1)/CN13/RB13
1
26
PWM1H2/RP12(1)/CN14/RB12
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
2
25
PWM1L3/RP11(1)/CN15/RB11
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
3
24
PWM1H3/RP10(1)/CN16/RB10
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/CN30/RA2
7
20
N/C
OSCO/CLKO/CN29/RA3
8
19
SDA1/SDI1/RP9(1)/CN21/RB9
PGED3/SOSCI/RP4(1)/CN1/RB4
9
Note 1:
2:
3:
18
SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
N/C (VDD)
16 17
/ASCL1/RP6 /CN24/RB6
VDD
15
(1)
14
FLTA1(3)
13
FLTB1 /ASDA1/RP5 /CN27/RB5
12
(1)
11
(3)
10
N/C (Vss)
dsPIC33FJ16MC102
N/C
(1)
PGEC3/SOSCO/T1CK/CN0/RA4
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
2011-2014 Microchip Technology Inc.
DS70000652F-page 15
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
36-Pin VTLA(2)
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
N/C
N/C
MCLR
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
= Pins are up to 5V tolerant
36
35
34
33
32
31
30
29
28 27
PWM1L2/RP13(1)/CN13/RB13
1
26
PWM1H2/RP12(1)/CN14/RB12
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
2
25
PWM1L3/RP11(1)/CN15/RB11
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
3
24
PWM1H3/RP10(1)/CN16/RB10
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/CN30/RA2
7
20
N/C
OSCO/CLKO/CN29/RA3
8
19
SDA1/RP9(1)/CN21/RB9
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
9
Note 1:
2:
3:
11
12
13
14
15
16 17
18
VDD
N/C (VDD)
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
SCL1/RP8(1)/CN22/RB8
INT0/RP7(1)/CN23/RB7
10
N/C (Vss)
dsPIC33FJ32MC102
N/C
(1)
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
DS70000652F-page 16
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
RA9
AN11/RP19(1)/CN28/RC3
AN12/RP20(1)/CN25/RC4
AN15/RP21(1)/CN26/RC5
VSS
VDD
ASDA1/RP5(1)/CN27/RB5
ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
44-Pin TQFP
44 43 42 41 40 39 38 37 36 35 34
SDA1/RP9(1)/CN21/RB9
1
33
PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4
RP22(1)/CN18/RC6
2
32
RA8
RP23(1)/CN17/RC7
3
31
OSC2/CLK0/CN29/RA3
RP24(1)/CN20/RC8
4
30
OSC1/CLKI/CN30/RA2
RP25(1)/CN19/RC9
5
29
VSS
dsPIC33FJ32GP104
VSS
6
28
VDD
VCAP
7
27
AN8/RP18(1)/CN10/RC2
RP10/CN16/RB10
8
26
AN7/RP17(1)/CN9/RC1
RP11(1)/CN15/RB11
9
25
AN6/RP16(1)/CN8/RC0
RP12(1)/CN14/RB12
10
24
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
RP13(1)/CN13/RB13
11
23
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
Note 1:
/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
PGED1/AN2/C2INA/C1INC/RP0(1)
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
MCLR
AVSS
AVDD
RP15(1)/CN11/RB15
RA7
RTCC/RP14(1)/CN12/RB14
RA10
12 13 14 15 16 17 18 19 20 21 22
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
2011-2014 Microchip Technology Inc.
DS70000652F-page 17
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
44-Pin TQFP
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
RA9
AN11/RP19(1)/CN28/RC3
AN12/RP20(1)/CN25/RC4
AN15/RP21(1)/CN26/RC5
VSS
VDD
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
= Pins are up to 5V tolerant
44 43 42 41 40 39 38 37 36 35 34
SDA1/RP9(1)/CN21/RB9
1
33
PEGED3/SOSCI/AN9/RP4(1)/CN1/RB4
RP22(1)/CN18/RC6
2
32
RA8
RP23(1)/CN17/RC7
3
31
OSC2/CLK0/CN29/RA3
RP24(1)/CN20/RC8
4
30
OSC1/CLKI/CN30/RA2
RP25(1)/CN19/RC9
5
29
VSS
dsPIC33FJ32MC104
VSS
6
28
VDD
VCAP
7
27
AN8/RP18(1)/CN10/RC2
PWM1H3/RP10(1)/CN16/RB10
8
26
AN7/RP17(1)/CN9/RC1
(1)/CN15/RB11
9
25
AN6/RP16(1)/CN8/RC0
10
24
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
11
23
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PWM1L3/RP11
PWM1H2/RP12(1)/CN14/RB12
(1)
PWM1L2/RP13 /CN13/RB13
Note 1:
2:
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
MCLR
AVSS
AVDD
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
RA7
RA10
12 13 14 15 16 17 18 19 20 21 22
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
DS70000652F-page 18
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
44-Pin QFN(2)
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
RA9
AN11/RP19(1)/CN28/RC3
AN12/RP20(1)/CN25/RC4
AN15/RP21(1)/CN26/RC5
VSS
VDD
ASDA1/RP5(1)/CN27/RB5
ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
= Pins are up to 5V tolerant
44 43 42 41 40 39 38 37 36 35 34
SDA1/RP9(1)/CN21/RB9
1
33
(1)
RP22 /CN18/RC6
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
2
32
RA8
RP23(1)/CN17/RC7
3
31
OSC2/CLKO/CN29/RA3
RP24(1)/CN20/RC8
4
30
OSC1/CLKI/CN30/RA2
RP25(1)/CN19/RC9
5
29
VSS
dsPIC33FJ32GP104
VSS
6
28
VDD
VCAP
7
27
AN8/RP18(1)/CN10/RC2
RP10(1)/CN16/RB10
8
26
AN7/RP17(1)/CN9/RC1
RP11(1)/CN15/RB11
9
25
AN6/RP16(1)/CN8/RC0
RP12 /CN14/RB12
10
24
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
RP13(1)/CN13/RB13
11
23
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
(1)
Note 1:
2:
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
(1)
PGED1/AN2/C2INA/C1INC/RP0 /CN4/RB0
(1)
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
AVDD
MCLR
AVSS
RP15 /CN11/RB15
(1)
RTCC/RP14(1)/CN12/RB14
RA7
RA10
12 13 14 15 16 17 18 19 20 21 22
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2014 Microchip Technology Inc.
DS70000652F-page 19
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
44-Pin QFN(2)
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
RA9
AN11/RP19(1)/CN28/RC3
AN12/RP20(1)/CN25/RC4
AN15/RP21(1)/CN26/RC5
VSS
VDD
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
INT0/RP7(1)/CN23/RB7
SCL1/RP8(1)/CN22/RB8
= Pins are up to 5V tolerant
44 43 42 41 40 39 38 37 36 35 34
SDA1/RP9(1)/CN21/RB9
1
33
RP22(1)/CN18/RC6
2
32
RA8
RP23(1)/CN17/RC7
3
31
OSC2/CLKO/CN29/RA3
RP24(1)/CN20/RC8
4
30
OSC1/CLKI/CN30/RA2
RP25(1)/CN19/RC9
5
29
VSS
VSS
6
28
VDD
dsPIC33FJ32MC104
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
VCAP
7
27
AN8/RP18(1)/CN10/RC2
PWM1H3/RP10(1)/CN16/RB10
8
26
AN7/RP17(1)/CN9/RC1
PWM1L3/RP11(1)/CN15/RB11
9
25
AN6/RP16(1)/CN8/RC0
PWM1H2/RP12(1)/CN14/RB12
10
24
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
11
23
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
(1)
PWM1L2/RP13 /CN13/RB13
Note 1:
2:
3:
PGED1/AN2/C2INA/C1INC/RP0 /CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
(1)
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
MCLR
AVSS
AVDD
PWM1L1/RP15(1)/CN11/RB15
RA7
PWM1H1/RTCC/RP14(1)/CN12/RB14
RA10
12 13 14 15 16 17 18 19 20 21 22
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
DS70000652F-page 20
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
44-Pin TLA(2)
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
AN11/RP19(1)/CN28/RC3
AN12/RP20(1)/CN25/RC4
AN15/RP21(1)/CN26/RC5
32
RA8
RP22 /CN18/RC6
2
31
OSC2/CLKO/CN29/RA3
RP23(1)/CN17/RC7
3
30
OSC1/CLKI/CN30/RA2
RP24 /CN20/RC8
4
29
VSS
RP25(1)/CN19/RC9
5
28
VDD
VSS
6
27
AN8/RP18(1)/CN10/RC2
VCAP
7
26
AN7/RP17(1)/CN9/RC1
RP10 /CN16/RB10
8
25
AN6/RP16(1)/CN8/RC0
RP11(1)/CN15/RB11
(1)
(1)
RA9
1
(1)
VDD
43 42 41 40 39 38 37 36 35 34 33
VSS
INT0/RP7(1)/CN23/RB7
ASDA1/RP5(1)/CN27/RB5
SCL1/RP8(1)/CN22/RB8
44
SDA1/RP9(1)/CN21/RB9
dsPIC33FJ32GP104
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
RP15
RA10
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
11 12 13 14 15 16 17 18 19 20 21 22
RP13 /CN13/RB13
MCLR
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AVDD
23
AVSS
10
(1)
(1)/CN11/RB15
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
RTCC/RP14(1)/CN12/RB14
24
RA7
9
(1)
RP12 /CN14/RB12
Note 1:
2:
ASCL1/RP6(1)/CN24/RB6
= Pins are up to 5V tolerant
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
2011-2014 Microchip Technology Inc.
DS70000652F-page 21
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Pin Diagrams (Continued)
44-Pin TLA(2)
SDA1/RP9(1)
PGEC3/SOSCO/AN10/T1CK/CN0/RA4
AN11/RP19(1)/CN28/RC3
AN12/RP20(1)/CN25/RC4
AN15/RP21(1)/CN26/RC5
RA9
43 42 41 40 39 38 37 36 35 34 33
VSS
44
VDD
INT0/RP7(1)/CN23/RB7
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
SCL1/RP8(1)/CN22/RB8
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
= Pins are up to 5V tolerant
PGED3/SOSCI/AN9/RP4(1)/CN1/RB4
1
32
RA8
2
31
OSC2/CLKO/CN29/RA3
RP23(1)/CN17/RC7
3
30
OSC1/CLKI/CN30/RA2
RP24(1)/CN20/RC8
4
29
VSS
RP25(1)/CN19/RC9
5
28
VDD
VSS
6
27
AN8/RP18(1)/CN10/RC2
VCAP
7
26
AN7/RP17(1)/CN9/RC1
PWM1H3/RP10(1)/CN16/RB10
8
25
AN6/RP16(1)/CN8/RC0
PWM1L3/RP11(1)/CN15/RB11
9
24
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
PWM1H2/RP12(1)/CN14/RB12
10
23
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
PWM1L2/RP13(1)/CN13/RB13
11 12 13 14 15 16 17 18 19 20 21 22
Note 1:
2:
3:
(1)
PGED1/AN2/C2INA/C1INC/RP0(1)/CN4/RB0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
MCLR
AVSS
AVDD
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14 /CN12/RB14
RA7
(1)
RA10
dsPIC33FJ32MC104
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
/CN21/RB9
RP22(1)/CN18/RC6
The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals.
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected
to VSS externally.
The PWM Fault pins are enabled and asserted during any Reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM Faults.
DS70000652F-page 22
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 27
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 33
3.0 CPU............................................................................................................................................................................................ 37
4.0 Memory Organization ................................................................................................................................................................. 49
5.0 Flash Program Memory.............................................................................................................................................................. 83
6.0 Resets ....................................................................................................................................................................................... 87
7.0 Interrupt Controller ..................................................................................................................................................................... 95
8.0 Oscillator Configuration ............................................................................................................................................................ 125
9.0 Power-Saving Features............................................................................................................................................................ 133
10.0 I/O Ports ................................................................................................................................................................................... 139
11.0 Timer1 ...................................................................................................................................................................................... 165
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................. 167
13.0 Input Capture............................................................................................................................................................................ 175
14.0 Output Compare....................................................................................................................................................................... 177
15.0 Motor Control PWM Module ..................................................................................................................................................... 181
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 197
17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 203
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 211
19.0 10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 217
20.0 Comparator Module.................................................................................................................................................................. 231
21.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 243
22.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 255
23.0 Special Features ...................................................................................................................................................................... 261
24.0 Instruction Set Summary .......................................................................................................................................................... 269
25.0 Development Support............................................................................................................................................................... 277
26.0 Electrical Characteristics .......................................................................................................................................................... 281
27.0 High-Temperature Electrical Characteristics............................................................................................................................ 339
28.0 Packaging Information.............................................................................................................................................................. 343
Appendix A: Revision History............................................................................................................................................................. 373
Index ................................................................................................................................................................................................. 381
The Microchip Web Site ..................................................................................................................................................................... 387
Customer Change Notification Service .............................................................................................................................................. 387
Customer Support .............................................................................................................................................................................. 387
Product Identification System ............................................................................................................................................................ 389
2011-2014 Microchip Technology Inc.
DS70000652F-page 23
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70000652F-page 24
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family Reference Manual”. These documents should be
considered as the primary reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section
of the dsPIC33FJ16MC102 product
page of the Microchip Web site
(www.microchip.com).
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“CPU” (DS70204)
“Data Memory” (DS70202)
“Program Memory” (DS70203)
“Flash Programming” (DS70191)
“Reset” (DS70192)
“Watchdog Timer and Power-Saving Modes” (DS70196)
“Timers” (DS70205)
“Input Capture” (DS70198)
“Output Compare” (DS70209)
“Motor Control PWM” (DS70187)
“Analog-to-Digital Converter (ADC)” (DS70183)
“UART” (DS70188)
“Serial Peripheral Interface (SPI)” (DS70206)
“Inter-Integrated Circuit™ (I2C™)” (DS70195)
“CodeGuard Security” (DS70199)
“Programming and Diagnostics” (DS70207)
“Device Configuration” (DS70194)
“I/O Ports with Peripheral Pin Select (PPS)” (DS70190)
“Real-Time Clock and Calendar (RTCC)” (DS70301)
“Introduction (Part VI)” (DS70655)
“Oscillator (Part VI)” (DS70644)
“Interrupts (Part VI)” (DS70633)
“Comparator with Blanking” (DS70647)
“Charge Time Measurement Unit (CTMU)” (DS70635)
2011-2014 Microchip Technology Inc.
DS70000652F-page 25
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
NOTES:
DS70000652F-page 26
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the latest family reference
sections of the “dsPIC33/PIC24 Family
Reference Manual”, which are available
from
the
Microchip
web
site
(www.microchip.com).
2011-2014 Microchip Technology Inc.
This data sheet contains device-specific information for
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 Digital Signal Controller (DSC)
devices. These devices contain extensive Digital Signal
Processor (DSP) functionality with a high-performance,
16-bit microcontroller (MCU) architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
family of devices. Table 1-1 lists the functions of the
various pins shown in the pinout diagrams.
DS70000652F-page 27
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 1-1:
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104 BLOCK
DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
16
16
8
16
16
Data Latch
Data Latch
PCU PCH PCL
Program Counter
X RAM
Y RAM
Loop
Control
Logic
Address
Latch
Address
Latch
23
23
Stack
Control
Logic
23
PORTB
16
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program Memory
EA MUX
ROM Latch
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
CTMU
Note:
16
DSP Engine
16 x 16
W Register Array
Power-up
Timer
Divide Support
16
Oscillator
Start-up Timer
Power-on
Reset
Precision
Band Gap
Reference
Watchdog
Timer
Voltage
Regulator
Brown-out
Reset
VCAP
Literal Data
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
16
16
VDD, VSS
16-Bit ALU
16
MCLR
External
Interrupts
1-3
Timers
1-5
UART1
ADC1
OC/
PWM1-2
RTCC
Comparators
1-3
SPI1
IC1-IC3
CNx
I2C1
PWM
6-ch
Not all pins or features are implemented on all device pinout configurations. See the “Pin Diagrams” section for the specific pins
and features present on each device.
DS70000652F-page 28
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
AN0-AN12,
AN15(5)
I
Analog
No
Analog input channels.
CLKI
CLKO
I
O
ST/CMOS
—
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
OSC1
I
ST/CMOS
—
No
OSC2
I/O
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/CMOS
—
No
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
CN0-CN30(5)
I
ST
No
Change Notification inputs. Can be software programmable for internal weak
pull-ups on all inputs.
Pin Name
No
Description
IC1-IC3
I
ST
Yes Capture Inputs 1/2/3.
OCFA
OC1-OC2
I
O
ST
—
Yes Compare Fault A input (for Compare Channels 1 and 2).
Yes Compare Outputs 1/2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No External Interrupt 0.
Yes External Interrupt 1.
Yes External Interrupt 2.
RA0-RA4,
RA7-RA10(5)
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15(5)
I/O
ST
No
PORTB is a bidirectional I/O port.
RC0-RC9(5)
I/O
ST
No
PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK(6)
T5CK(6)
I
I
I
I
I
ST
ST
ST
ST
ST
No
Yes
Yes
Yes
Yes
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 Clear-to-Send.
UART1 Ready-to-Send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Yes Synchronous serial clock input/output for SPI1.
Yes SPI1 data in.
Yes SPI1 data out.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin in dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: These pins are available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.
2011-2014 Microchip Technology Inc.
DS70000652F-page 29
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
PPS
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
FLTA1(1,2,4)
FLTB1(3,4)
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
I
I
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
No
No
No
No
No
No
No
No
PWM1 Fault A input.
PWM1 Fault B input.
PWM1 Low Output 1.
PWM1 High Output 1.
PWM1 Low Output 2.
PWM1 High Output 2.
PWM1 Low Output 3.
PWM1 High Output 3.
RTCC
O
Digital
No
RTCC Alarm output.
CTPLS
CTED1
CTED2
O
I
I
Digital
Digital
Digital
Yes CTMU pulse output.
No CTMU External Edge Input 1.
No CTMU External Edge Input 2.
CVREFIN
CVREFOUT
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
C3INA
C3INB
C3INC
C3IND
C3OUT
I
O
I
I
I
I
O
I
I
I
I
O
I
I
I
I
O
Analog
Analog
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
No
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
Comparator Voltage Positive Reference Input.
Comparator Voltage Positive Reference Output.
Comparator 1 Positive Input A.
Comparator 1 Negative Input B.
Comparator 1 Negative Input C.
Comparator 1 Negative Input D.
Comparator 1 Output.
Comparator 2 Positive Input A.
Comparator 2 Negative Input B.
Comparator 2 Negative Input C.
Comparator 2 Negative Input D.
Comparator 2 Output.
Comparator 3 Positive Input A.
Comparator 3 Negative Input B.
Comparator 3 Negative Input C.
Comparator 3 Negative Input D.
Comparator 3 Output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the device.
Pin Name
Description
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin in dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: These pins are available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.
DS70000652F-page 30
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
PPS
Description
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all times.
AVDD is connected to VDD in the 18-pin dsPIC33FJXXGP101 and 20-pin
dsPIC33FJXXMC101 devices. In all other devices, AVDD is separated from
VDD.
AVSS
P
P
No
Ground reference for analog modules. AVSS is connected to VSS in the
18-pin dsPIC33FJXXGP101 and 20-pin dsPIC33FJXXMC101 devices. In all
other devices, AVSS is separated from VSS.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Pin Name
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin in dsPIC33FJXXMC101 (20-pin) devices.
2: The FLTA1 pin and the PWM1Lx/PWM1Hx pins are available in dsPIC(16/32)MC10X devices only.
3: The FLTB1 pin is available in dsPIC(16/32)MC102/104 devices only.
4: The PWM Fault pins are enabled during any Reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM Faults.
5: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
6: These pins are available in dsPIC33FJ32(GP/MC)104 (44-pin) devices only.
2011-2014 Microchip Technology Inc.
DS70000652F-page 31
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
NOTES:
DS70000652F-page 32
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To complement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest “dsPIC33/PIC24 Family
Reference Manual” sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 family of 16-bit
Digital Signal Controllers (DSCs) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins, if present on the device
(regardless if ADC module is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2011-2014 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10V-20V. This capacitor
should be a low-ESR and have resonance
frequency in the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
DS70000652F-page 33
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
VDD
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 23.2
“On-Chip Voltage Regulator” for details.
R1
VSS
VDD
VCAP
2.4
R
The MCLR
functions:
MCLR
dsPIC33F
VSS
VSS
VDD
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note
1:
pin
provides
two
specific
device
• Device Reset
• Device programming and debugging
C
0.1 µF
Ceramic
Master Clear (MCLR) Pin
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------- (i.e., ADC conversion rate/2)
2
1
f = ---------------------- 2 LC
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
2
1
L = ----------------------
2f C
R(1)
R1(2)
MCLR
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
JP
dsPIC33F
C
Note 1:
R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR
pin VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 26.0
“Electrical Characteristics” for additional information.
DS70000652F-page 34
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternately, refer to the AC/DC characteristics and
timing requirements information in the “dsPIC33F
Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70659) for information on
capacitive loading limits and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) (DS51765)
• “MPLAB® ICD 3 Design Advisory” (DS51764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS51616)
• “Using MPLAB® REAL ICE™” (poster) (DS51749)
2011-2014 Microchip Technology Inc.
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
DS70000652F-page 35
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz <
FIN < 8 MHz (for ECPLL mode) to comply with device
PLL start-up conditions. HSPLL mode is not supported.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. The fixed PLL settings of 4x after a
POR with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the application firmware
can enable the PLL and then perform a clock switch to
the Oscillator + PLL clock source. Note that clock
switching must be enabled in the device Configuration
Word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If your application needs to use certain
Analog-to-Digital pins as analog input pins during the
debug session, the user application must clear the
corresponding bits in the AD1PCFGL register during
initialization of the ADC module.
When MPLAB ICD 3 or MPLAB REAL ICE in-circuit
emulator is used as a programmer, the user application
firmware must correctly configure the AD1PCFGL
register. Automatic initialization of this register is only
done during debugger operation. Failure to correctly
configure the register(s) will result in all
Analog-to-Digital pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor between VSS
and unused pins.
If MPLAB ICD 3 or MPLAB REAL ICE in-circuit
emulator is selected as a debugger, it automatically
initializes all of the Analog-to-Digital input pins (ANx) as
“digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the
Analog-to-Digital pins that are initialized by MPLAB
ICD 3 or MPLAB REAL ICE in-circuit emulator, must
not be cleared by the user application firmware;
otherwise, communication errors will result between
the debugger and the device.
DS70000652F-page 36
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.0
CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “CPU” (DS70204) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 devices have sixteen, 16-bit Working registers in the programmer’s
model. Each of the Working registers can serve as a
data, address, or address offset register. The 16th
Working register (W15) operates as a Software Stack
Pointer (SSP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices: MCU and DSP. These two
instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing
modes and is designed for optimum C compiler efficiency. For most instructions, dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
devices are capable of executing a data (or program
data) memory read, a Working register (data) read, a
data memory write and a program (instruction) memory
read per instruction cycle. As a result, three parameter
instructions can be supported, allowing A + B = C
operations to be executed in a single cycle.
2011-2014 Microchip Technology Inc.
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
is shown in Figure 3-2.
3.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been
designed for optimal real-time performance. The MAC
instruction and other associated instructions can concurrently fetch two data operands from memory, while
multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be
split for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain Working
registers to each address space.
DS70000652F-page 37
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.3
Special MCU Features
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 supports 16/16
and 32/16 divide operations, both fractional and
integer. All divide instructions are iterative operations.
They must be executed within a REPEAT loop, resulting
in a total execution time of 19 instruction cycles. The
divide operation can be interrupted during any of those
19 cycles without loss of data.
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 features a 17-bit
by 17-bit, single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
23
16
16
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction Reg
16
Literal Data
Instruction
Decode and
Control
16
Control Signals
to Various Blocks
16
DSP Engine
16 x 16
W Register Array
Divide Support
16
16-Bit ALU
16
To Peripheral Modules
DS70000652F-page 38
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 3-2:
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
DSP
Accumulators
AD15
AD31
AD0
ACCA
ACCB
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
2011-2014 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70000652F-page 39
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.4
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
R/C-0
R/C-0
R-0
R/C-0
R-0
R/W-0
OB
SA(1)
SB(1)
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
IPL2
R/W-0(3)
R/W-0(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL1(2)
IPL0(2)
RA
N
OV
Z
C
(2)
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9
DA: DO Loop Active bit
1 = DO loop is in progress
0 = DO loop is not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when NSTDIS = 1 (INTCON1).
DS70000652F-page 40
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when NSTDIS = 1 (INTCON1).
2011-2014 Microchip Technology Inc.
DS70000652F-page 41
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
R/W-0
SATA
bit 7
R/W-0
SATB
bit 11
bit 10-8
R/W-0
US
R/W-0
EDT(1)
R-0
DL2
R-0
DL1
R-0
DL0
bit 8
Legend:
R = Readable bit
0’ = Bit is cleared
bit 15-13
bit 12
U-0
—
R/W-1
SATDW
R/W-0
ACCSAT
C = Clearable bit
W = Writable bit
‘x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at the end of current loop iteration
0 = No effect
DL: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
001 = 1 DO loop is active
000 = 0 DO loops are active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply operations
0 = Fractional mode is enabled for DSP multiply operations
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level.
DS70000652F-page 42
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.5
Arithmetic Logic Unit (ALU)
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 ALU is 16 bits
wide, and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are 2’s complement in nature.
Depending on the operation, the ALU can affect the
values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR
register. The C and DC Status bits operate as Borrow
and Digit Borrow bits, respectively, for subtraction
operations.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
3.6
DSP Engine
The DSP engine consists of a high-speed,
17-bit x 17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumulatorto-accumulator operations that require no additional
data. These instructions are ADD, SUB and NEG.
Refer to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 CPU incorporates
hardware support for both multiplication and division.
This includes a dedicated hardware multiplier and
support hardware for 16-bit-divisor division.
•
•
•
•
•
•
3.5.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
•
•
•
•
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
2011-2014 Microchip Technology Inc.
Fractional or Integer DSP Multiply (IF)
Signed or Unsigned DSP Multiply (US)
Conventional or Convergent Rounding (RND)
Automatic Saturation On/Off for ACCA (SATA)
Automatic Saturation On/Off for ACCB (SATB)
Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
• Accumulator Saturation mode Selection (ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
CLR
A=0
Yes
ED
A = (x – y)2
Instruction
No
EDAC
A = A + (x –
y)2
No
MAC
A = A + (x * y)
Yes
MAC
A = A + x2
No
No change in A
Yes
MPY
A=x*y
No
MPY
A=x2
No
MOVSAC
MPY.N
MSC
A=–x*y
No
A=A–x*y
Yes
DS70000652F-page 43
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-Bit Accumulator A
40-Bit Accumulator B
Carry/Borrow Out
Saturate
Carry/Borrow In
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-Bit
Multiplier/Scaler
16
16
To/From W Array
DS70000652F-page 44
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an
N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a sign
bit and the radix point is implied to lie just after the sign bit
(QX format). The range of an N-bit 2’s complement
fraction with this implied radix point is -1.0 to (1 – 21-N).
For a 16-bit fraction, the Q15 data range is -1.0 (0x8000)
to 0.999969482 (0x7FFF) including 0 and has a precision
of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply
operation generates a 1.31 product that has a precision
of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It
can select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
2011-2014 Microchip Technology Inc.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS Register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that controls
accumulator data saturation, if selected. It uses the result
of the adder, the Overflow Status bits described
previously, and the SAT (CORCON) and
ACCSAT (CORCON) mode control bits to determine
when and to what value, to saturate.
Six STATUS Register bits support saturation and
overflow:
• OA:
• OB:
• SA:
ACCA overflowed into guard bits
ACCB overflowed into guard bits
ACCA saturated (bit 31 overflow and
saturation)
or
• SB:
ACCA overflowed into guard bits and
saturated (bit 39 overflow and saturation)
ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when OA and OB are set and
the corresponding Overflow Trap Flag Enable bits
(OVATE, OVBTE) in the INTCON1 register are set
(refer to Section 7.0 “Interrupt Controller”). This
allows the user application to take immediate action; for
example, to correct system gain.
DS70000652F-page 45
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow, and therefore, indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 register is set, the SA and SB bits will
generate an arithmetic warning trap when saturation is
disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programmers can check one bit in
the STATUS Register to determine whether either
accumulator has overflowed, or one bit to determine
whether either accumulator has saturated. This is
useful for complex number arithmetic, which typically
uses both accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive
9.31 value (0x7FFFFFFFFF) or maximally negative
9.31 value (0x8000000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides
protection against erroneous data or unexpected
algorithm problems (such as gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
DS70000652F-page 46
3.6.3
ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator which is not targeted by the instruction into data space memory. The write is performed
across the X bus into combined X and Y address
space. The following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
• [W13]+ = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
3.6.3.1
Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit,
1.15 data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word (lsw) is simply discarded.
Conventional rounding will zero-extend bit 15 of the
accumulator and will add it to the ACCxH word (bits 16
through 31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a succession of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (LSb), bit 16 of the accumulator, of
ACCxH is examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 3.6.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator writeback operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
3.6.3.2
Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit,
1.15 fractional value from the round logic block as its
input, together with overflow status from the original
source (accumulator) and the 16-bit round adder.
These inputs are combined and used to select the
appropriate 1.15 fractional value as output to write to
data space memory.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The MSb of the source (bit 39) is used to determine the
sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
3.6.4
BARREL SHIFTER
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts, in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between Bit Positions 16
and 31 for right shifts, and between Bit Positions 0 and
16 for left shifts.
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative
1.15 value, 0x8000.
2011-2014 Microchip Technology Inc.
DS70000652F-page 47
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
NOTES:
DS70000652F-page 48
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.0
MEMORY ORGANIZATION
Note:
4.1
This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “Data Memory” (DS70202)
and “Program Memory” (DS70203) in
the “dsPIC33/PIC24 Family Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
The device architecture features separate program and
data memory spaces and buses. This architecture also
allows the direct access of program memory from the
data space during code execution.
FIGURE 4-1:
Program Address Space
The program address memory space of the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices is 4M instructions. The space
is addressable by a 24-bit value derived either from the
23-bit Program Counter (PC) during program execution,
or from table operation or data space remapping as
described in Section 4.6 “Interfacing Program and
Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps for the dsPIC33FJ16(GP/MC)101/
102 and dsPIC33FJ32(GP/MC)101/102/104 family of
devices are shown in Figure 4-1 and Figure 4-2.
PROGRAM MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES
User Memory Space
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(5.6K instructions)
Flash Configuration
Words(1)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x002BFA
0x002BFC
0x002BFE
0x002COO
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Configuration Memory Space
Reserved
Device Configuration
Shadow Registers
Reserved
DEVID (2)
Note 1:
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
On Reset, these bits are automatically copied into the device Configuration Shadow registers.
2011-2014 Microchip Technology Inc.
DS70000652F-page 49
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 4-2:
PROGRAM MEMORY MAP FOR dsPIC33FJ32(GP/MC)101/102/104 DEVICES
User Memory Space
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(11.2K instructions)
Flash Configuration
Words(1)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x0057FA
0x0057FC
0x0057FE
0x005800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Configuration Memory Space
Reserved
Device Configuration
Shadow Registers
Reserved
DEVID (2)
Note 1:
0xF7FFFE
0xF80000
0xF80020
0xF80022
0xFEFFFE
0xFF0000
0xFFFFFE
On Reset, these bits are automatically copied into the device Configuration Shadow registers.
DS70000652F-page 50
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTO instruction is programmed
by the user application at 0x000000, with the actual
address for the start of code at 0x000002.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-3).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-3:
msw
Address
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices also have two Interrupt Vector Tables (IVTs), located from 0x000004 to 0x0000FF
and 0x000100 to 0x0001FF. These vector tables allow
each of the device interrupt sources to be handled by
separate Interrupt Service Routines (ISRs). A more
detailed discussion of the Interrupt Vector Tables is
provided in Section 7.1 “Interrupt Vector Table”.
PROGRAM MEMORY ORGANIZATION
least significant word (lsw)
most significant word (msw)
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
16
8
2011-2014 Microchip Technology Inc.
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
PC Address
(lsw Address)
Instruction Width
DS70000652F-page 51
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.2
Data Address Space
The
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 family CPU has a
separate 16-bit-wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
Microchip
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 devices implement
up to 2 Kbytes of data memory. Should an EA point to
a location outside of this area, an all-zero word or byte
will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byteaddressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the error
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then executed, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternately, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 family core and peripheral modules
for controlling the operation of the device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note:
®
To maintain backward compatibility with PIC MCU
devices and improve data space memory usage
efficiency, the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 family instruction
set supports both word and byte operations. As a
consequence of byte accessibility, all Effective Address
calculations are internally scaled to step through wordaligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
DS70000652F-page 52
SFR SPACE
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8-Kbyte area, between 0x0000 and 0x1FFF, is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
the MOV class of instructions, which support Memory
Direct Addressing mode with a 16-bit address field or
by using Indirect Addressing mode with a Working
register as an Address Pointer.
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 4-4:
DATA MEMORY MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES WITH
1-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
1-Kbyte
SRAM Space
LSB
Address
16 Bits
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x07FE
0x0800
X Data RAM (X)
0x09FF
0x0A01
0x09FE
0x0A00
Y Data RAM (Y)
0x0BFF
0x0C01
0x0BFE
0x0C00
0x1FFF
0x2001
0x1FFE
0x8001
0x8000
8-Kbyte
Near Data
Space
0x2000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
2011-2014 Microchip Technology Inc.
0xFFFE
DS70000652F-page 53
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 4-5:
DATA MEMORY MAP FOR dsPIC33FJ32(GP/MC)101/102/104 DEVICES WITH
2-KBYTE RAM
MSB
Address
MSb
2 Kbyte
SFR Space
2 Kbyte
SRAM Space
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x0BFF
0x0C01
0x07FE
0x0800
X Data RAM (X)
Y Data RAM (Y)
0x0BFE
0x0C00
0x0FFF
0x1001
0x0FFE
0x1000
0x1FFF
0x2001
0x1FFE
0x8001
0x8000
8 Kbyte
Near Data
Space
0x2000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70000652F-page 54
LSB
Address
16 Bits
0xFFFE
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
2011-2014 Microchip Technology Inc.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, although the
implemented memory locations vary by device.
DS70000652F-page 55
SFR Name
CPU CORE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
WREG0
0000
Working Register 0
xxxx
WREG1
0002
Working Register 1
xxxx
WREG2
0004
Working Register 2
xxxx
WREG3
0006
Working Register 3
xxxx
WREG4
0008
Working Register 4
xxxx
WREG5
000A
Working Register 5
xxxx
WREG6
000C
Working Register 6
xxxx
WREG7
000E
Working Register 7
xxxx
WREG8
0010
Working Register 8
xxxx
WREG9
0012
Working Register 9
xxxx
WREG10
0014
Working Register 10
xxxx
WREG11
0016
Working Register 11
xxxx
WREG12
0018
Working Register 12
xxxx
WREG13
001A
Working Register 13
xxxx
WREG14
001C
Working Register 14
xxxx
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
Accumulator A Low Word Register
xxxx
ACCAH
0024
Accumulator A High Word Register
xxxx
ACCAU
0026
Accumulator A Upper Word Register
xxxx
ACCBL
0028
Accumulator B Low Word Register
xxxx
ACCBH
002A
Accumulator B High Word Register
xxxx
xxxx
2011-2014 Microchip Technology Inc.
ACCBU
002C
Accumulator B Upper Word Register
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
Program Counter High Byte Register
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Page Address Pointer Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Memory Visibility Page Address Pointer Register
RCOUNT
0036
0000
0000
Repeat Loop Counter Register
xxxx
DCOUNT
0038
DOSTARTL
003A
DCOUNT
DOSTARTH
003C
DOENDL
003E
DOENDH
0040
—
—
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
xxxx
DOSTARTL
—
—
—
—
—
—
—
—
—
—
xxxx
0
xxxx
DOSTARTH
00xx
DOENDL
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0
DOENDH
IPL0
RA
N
OV
00xx
Z
C
0000
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 56
TABLE 4-1:
SFR Name
CPU CORE REGISTER MAP (CONTINUED)
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CORCON
0044
—
—
—
US
EDT
DL2
DL1
DL0
SATA
SATB
SATDW
ACCSAT
IPL3
PSV
RND
IF
0020
MODCON
0046
XMODEN
YMODEN
—
—
BWM3
BWM2
BWM1
BWM0
YWM3
YWM2
YWM1
YWM0
XWM3
XWM2
XWM1
XWM0
0000
XMODSRT
0048
XS
0
xxxx
XMODEND
004A
XE
1
xxxx
YMODSRT
004C
YS
0
xxxx
YMODEND
004E
YE
1
xxxx
XBREV
0050
BREN
DISICNT
0052
—
XB
—
Disable Interrupts Counter Register
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
0000
DS70000652F-page 57
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2011-2014 Microchip Technology Inc.
TABLE 4-1:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES
SFR
Name
SFR
Addr
Bit 15
CNEN1
0060
—
CNEN2
0062
—
CNPU1
0068
—
—
—
CNPU2
006A
—
Bit 14
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CN22IE
CN21IE
—
—
—
—
—
0000
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
—
—
—
—
—
0000
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
—
—
CN12IE
CN11IE
—
—
—
—
CN30IE
CN29IE
—
—
—
—
—
CN23IE
—
—
—
—
—
—
—
—
CN30PUE CN29PUE
CN12PUE CN11PUE
—
—
Bit 7
Bit 5
Bit 13
Bit 6
CN23PUE CN22PUE CN21PUE
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXMC101 DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
—
CN14IE
CN13IE
CN12IE
CN11IE
—
—
—
—
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CNEN2
0062
—
CN30IE
CN29IE
—
—
—
—
—
CN23IE
CN22IE
CN21IE
—
—
—
—
—
0000
CNPU1
0068
—
CN14PUE CN13PUE CN12PUE CN11PUE
—
—
—
—
—
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CNPU2
006A
—
CN30PUE CN29PUE
—
—
—
—
—
—
—
—
0000
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
—
—
Bit 7
Bit 6
CN23PUE CN22PUE CN21PUE
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
CNEN1
0060
CN15IE
CN14IE
CN13IE
CNEN2
0062
—
CN30IE
CN29IE
CNPU1
0068
CNPU2
006A
Bit 11
Bit 10
Bit 9
CN12IE
CN11IE
—
—
—
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
—
CN27IE
—
—
CN24IE
CN23IE
CN22IE
CN21IE
—
—
—
—
CN16IE
0000
—
—
—
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
—
—
—
—
—
—
CN16PUE
0000
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
—
CN30PUE CN29PUE
—
CN27PUE
Bit 8
Bit 7
Bit 6
CN24PUE CN23PUE CN22PUE CN21PUE
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2014 Microchip Technology Inc.
TABLE 4-5:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
CNEN1
0060
CN15IE
CN13IE
CN13IE
CNEN2
0062
—
CN30IE
CN29IE
CNPU1
0068
CNPU2
006A
Bit 11
Bit 10
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CN28IE
CN27IE
CN26IE
CN25IE
CN24IE
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
0000
CN15PUE CN13PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 58
TABLE 4-2:
SFR
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
INTCON1 0080
NSTDIS
OVAERR
OVBERR
INTCON2 0082
ALTIVT
DISI
—
—
—
—
COVAERR COVBERR OVATE
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
OVBTE
COVTE
SFTACERR
DIV0ERR
—
—
—
—
—
—
—
—
MATHERR ADDRERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 2
Bit 1
STKERR
INT2EP
IFS0
0084
—
—
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
—
—
INT2IF
T5IF(2)
T4IF(2)
—
—
—
—
—
—
INT1IF
CNIF
CMIF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
—
IC3IF
—
—
—
—
—
0000
IFS3
008A FLTA1IF(1)
RTCIF
—
—
—
—
PWM1IF(1)
—
—
—
—
—
—
—
—
—
0000
IFS4
008C
—
—
CTMUIF
—
—
—
—
—
—
—
—
—
—
—
U1EIF
FLTB1IF(3)
0000
IEC0
0094
—
—
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
—
—
INT2IE
T5IE(2)
T4IE(2)
—
—
—
—
—
—
INT1IE
CNIE
CMIE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
—
IC3IE
—
—
—
—
—
0000
IEC3
009A FLTA1IE(1)
RTCIE
—
—
—
—
PWM1IE(1)
—
—
—
—
—
—
—
—
—
0000
IEC4
009C
—
—
CTMUIE
—
—
—
—
—
—
—
—
—
—
—
U1EIE
FLTB1IE(3)
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
AD1IP2
AD1IP1
AD1IP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
CMIP2
CMIP1
CMIP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2(2)
T4IP1(2)
T4IP0(2)
—
—
—
—
—
—
—
—
—
—
—
—
4000
IPC7
00B2
—
—
—
—
—
—
—
—
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2(2)
T5IP1(2)
T5IP0(2)
0044
IPC9
00B6
—
—
—
—
—
—
—
—
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0040
IPC14
00C0
—
—
—
—
—
—
—
—
—
—
—
—
—
0040
IPC15
00C2
—
—
RTCIP2
RTCIP1
RTCIP0
—
—
—
—
—
—
—
—
4400
IPC16
00C4
—
—
—
—
—
—
—
—
—
U1EIP2
U1EIP1
U1EIP0
—
IPC19
00CA
—
—
—
—
—
—
—
—
—
CTMUIP2
CTMUIP1
CTMUIP0
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6
VECNUM5
VECNUM4 VECNUM3 VECNUM2
DS70000652F-page 59
Legend:
Note 1:
2:
3:
FLTA1IP2(1) FLTA1IP1(1) FLTA1IP0(1)
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are available in dsPIC33FJXXMC10X devices only.
These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
These bits are available in dsPIC33FJ(16/32)MC102/104 devices only.
PWM1IP2(1) PWM1IP1(1) PWM1IP0(1)
INT0IP2:0>
4444
FLTB1IP2(3) FLTB1IP1(3) FLTB1IP0(3) 0040
—
—
—
VECNUM1 VECNUM0
0040
0000
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2011-2014 Microchip Technology Inc.
TABLE 4-6:
SFR
Name
SFR
Addr
TIMERS REGISTER MAP FOR dsPIC33FJ16(GP/MC)10X DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
—
TMR3HLD 0108
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
FFFF
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
Timer2 Register
0000
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FFFF
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
SFR
Name
SFR
Addr
TIMERS REGISTER MAP FOR DSPIC33FJ32(GP/MC)10X DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
—
TMR3HLD 0108
—
—
—
0000
FFFF
TGATE
TCKPS1
TCKPS0
—
TSYNC
TCS
—
0000
Timer2 Register
0000
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
2011-2014 Microchip Technology Inc.
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
TMR4
0114
TMR5HLD 0116
FFFF
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Timer4 Register
0000
Timer5 Holding Register (for 32-bit operations only)
xxxx
TMR5
0118
Timer5 Register
0000
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1
TCKPS0
—
—
TCS
—
0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
FFFF
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 60
TABLE 4-7:
SFR Name
INPUT CAPTURE REGISTER MAP
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
Input Capture 1 Register
—
ICTMR
xxxx
Input Capture 2 Register
—
ICTMR
xxxx
Input Capture 3 Register
—
—
ICSIDL
—
—
—
—
—
ICTMR
0000
xxxx
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
Bit 1
Bit 0
All
Resets
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10:
SFR Name
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
OC1RS
0180
Output Compare 1 Secondary Register
xxxx
OC1R
0182
Output Compare 1 Register
xxxx
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
xxxx
OC2R
0188
Output Compare 2 Register
xxxx
OC2CON
018A
—
—
—
—
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
—
OCFLT
OCTSEL
OCTSEL
OCM2
OCM2
OCM1
OCM1
OCM0
OCM0
0000
0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11:
SFR Name
SFR
Addr.
6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJXXMC10X DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
PTSIDL
—
—
—
—
Bit 8
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
P1TCON
01C0
PTEN
P1TMR
01C2
PTDIR
PWM1 Timer Count Value Register
PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 0000 0000
0000 0000 0000 0000
P1TPER
01C4
—
PWM1 Time Base Period Register
0111 1111 1111 1111
P1SECMP
01C6 SEVTDIR
PWM1 Special Event Compare Register
PWM1CON1 01C8
—
—
—
—
—
PMOD3
PMOD2
PMOD1
PWM1CON2 01CA
—
—
—
—
DTB5
DTB4
DTB3
DTB2
DTB1
DTB0
—
—
—
—
—
—
—
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0
0000 0000 0000 0000
—
PEN3H
PEN2H
PEN1H
—
PEN3L
PEN2L
PEN1L
0000 0000 0000 0000
—
—
—
—
—
IUE
OSYNC
UDIS
0000 0000 0000 0000
DTA5
DTA4
DTA3
DTA2
DTA1
DTA0
0000 0000 0000 0000
—
DTS3A
DTS3I
DTS2A
DTS2I
DTS1A
DTS1I
0000 0000 0000 0000
DS70000652F-page 61
P1DTCON1
01CC DTBPS1 DTBPS0
DTAPS1 DTAPS0
P1DTCON2
01CE
—
—
P1FLTACON 01D0
—
—
FAOV3H FAOV3L
FAOV2H
FAOV2L
FAOV1H
FAOV1L
FLTAM
—
—
—
—
FAEN3
FAEN2
FAEN1
0000 0000 0000 0111
P1FLTBCON 01D2
—
—
FBOV3H FBOV3L
FBOV2H
FBOV2L
FBOV1H
FBOV1L
FLTBM
—
—
—
—
FBEN3
FBEN2
FBEN1
0000 0000 0000 0111
P1OVDCON 01D4
—
—
POVD3H POVD3L POVD2H
POVD2L
POVD1H
POVD1L
—
—
POUT3H POUT3L POUT2H
POUT2L POUT1H POUT1L 0011 1111 0000 0000
P1DC1
01D6
PWM1 Duty Cycle 1 Register
0000 0000 0000 0000
P1DC2
01D8
PWM1 Duty Cycle 2 Register
0000 0000 0000 0000
P1DC3
01DA
PWM1 Duty Cycle 3 Register
0000 0000 0000 0000
PWM1KEY
01DE
PWMKEY
0000 0000 0000 0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2011-2014 Microchip Technology Inc.
TABLE 4-9:
I2C1 REGISTER MAP
All
Resets
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
I2C1ADD
020A
—
—
—
—
—
—
I2C1 Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
I2C1 Address Mask Register
0000
SFR Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
0000
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
D_A
P
S
R_W
RBF
TBF
1000
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13:
SFR Name
SFR
Addr
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
—
UTXBRK
UTXEN
UTXBF
TRMT
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
U1TXREG
0224
—
—
—
—
—
—
—
U1RXREG
0226
—
—
—
—
—
—
—
U1BRG
0228
UTXINV UTXISEL0
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
URXISEL1 URXISEL0
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
0110
UART1 Transmit Register
xxxx
UART1 Receive Register
0000
Baud Rate Generator Prescaler
0000
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
SFR Name
SPI1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
2011-2014 Microchip Technology Inc.
Bit 2
Bit 1
Bit 0
All
Resets
0000
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
—
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
—
—
—
—
—
FRMDLY
—
0000
SPI1BUF
0248
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI1 Transmit and Receive Buffer Register
0000
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 62
TABLE 4-12:
ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)101 DEVICES
All
Resets
File Name
SFR
Addr
ADC1BUF0
0300
ADC1 Data Buffer 0
xxxx
ADC1BUF1
0302
ADC1 Data Buffer 1
xxxx
ADC1BUF2
0304
ADC1 Data Buffer 2
xxxx
ADC1BUF3
0306
ADC1 Data Buffer 3
xxxx
ADC1BUF4
0308
ADC1 Data Buffer 4
xxxx
ADC1BUF5
030A
ADC1 Data Buffer 5
xxxx
ADC1BUF6
030C
ADC1 Data Buffer 6
xxxx
ADC1BUF7
030E
ADC1 Data Buffer 7
xxxx
ADC1BUF8
0310
ADC1 Data Buffer 8
xxxx
ADC1BUF9
0312
ADC1 Data Buffer 9
xxxx
ADC1BUFA
0314
ADC1 Data Buffer 10
xxxx
ADC1BUFB
0316
ADC1 Data Buffer 11
xxxx
ADC1BUFC
0318
ADC1 Data Buffer 12
xxxx
ADC1BUFD
031A
ADC1 Data Buffer 13
xxxx
ADC1BUFE
031C
ADC1 Data Buffer 14
xxxx
ADC1BUFF
031E
ADC1 Data Buffer 15
AD1CON1
0320
ADON
—
ADSIDL
AD1CON2
0322
VCFG2
VCFG1
VCFG0
AD1CON3
0324
ADRC
—
—
Bit 15
Bit 14
Bit 13
Bit 12
—
Bit 11
Bit 10
Bit 9
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
xxxx
—
—
CSCNA
CHPS1
CHPS0
BUFS
—
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
0000
0326
—
—
—
—
—
0328
CH0NB
—
—
CH0SB4
CH0SB3
AD1PCFGL
032C
—
—
—
—
—
AD1CSSL
0330
—
—
—
—
—
SSRC2
Bit 6
—
AD1CHS123
FORM0
Bit 7
—
AD1CHS0
FORM1
Bit 8
CH123NB1 CH123NB0 CH123SB
SSRC1
SSRC0
—
SIMSAM
ASAM
SAMP
0000
—
—
—
—
—
CH0SB0
CH0NA
—
—
CH0SA4
CH0SA3
PCFG(1)
—
—
—
—
—
PCFG
0000
CSS(1)
—
—
—
—
—
CSS
0000
CH0SB2
CH0SB1
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The PCFG and CSS bits are available in dsPIC33FJ32(GP/MC)101/102 devices only.
CH123NA1 CH123NA0
DONE
CH0SA2
CH0SA1
CH123SA
0000
CH0SA0
0000
DS70000652F-page 63
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2011-2014 Microchip Technology Inc.
TABLE 4-15:
ADC1 REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES
File Name
SFR
Addr
ADC1BUF0
0300
ADC1 Data Buffer 0
xxxx
ADC1BUF1
0302
ADC1 Data Buffer 1
xxxx
ADC1BUF2
0304
ADC1 Data Buffer 2
xxxx
ADC1BUF3
0306
ADC1 Data Buffer 3
xxxx
ADC1BUF4
0308
ADC1 Data Buffer 4
xxxx
ADC1BUF5
030A
ADC1 Data Buffer 5
xxxx
ADC1BUF6
030C
ADC1 Data Buffer 6
xxxx
ADC1BUF7
030E
ADC1 Data Buffer 7
xxxx
ADC1BUF8
0310
ADC1 Data Buffer 8
xxxx
ADC1BUF9
0312
ADC1 Data Buffer 9
xxxx
ADC1BUFA
0314
ADC1 Data Buffer 10
xxxx
ADC1BUFB
0316
ADC1 Data Buffer 11
xxxx
ADC1BUFC
0318
ADC1 Data Buffer 12
xxxx
ADC1BUFD
031A
ADC1 Data Buffer 13
xxxx
ADC1BUFE
031C
ADC1 Data Buffer 14
xxxx
ADC1BUFF
031E
ADC1 Data Buffer 15
AD1CON1
0320
ADON
—
ADSIDL
AD1CON2
0322
VCFG2
VCFG1
VCFG0
AD1CON3
0324
ADRC
—
—
Bit 15
Bit 14
Bit 13
Bit 12
—
Bit 11
Bit 10
Bit 9
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
—
—
CSCNA
CHPS1
CHPS0
BUFS
—
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
0000
—
—
0326
—
—
—
—
—
0328
CH0NB
—
—
CH0SB4
CH0SB3
AD1PCFGL
032C
—
—
—
—
—
AD1CSSL
0330
—
—
—
—
—
CH123NB1 CH123NB0 CH123SB
SSRC2
Bit 6
—
AD1CHS0
FORM0
Bit 7
—
AD1CHS123
FORM1
Bit 8
SSRC1
SSRC0
—
SIMSAM
ASAM
SAMP
DONE
—
—
—
CH0SB0
CH0NA
—
—
PCFG(1)
—
—
—
PCFG
0000
CSS(1)
—
—
—
CSS
0000
CH0SB2
CH0SB1
2011-2014 Microchip Technology Inc.
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The PCFG and CSS bits are available in dsPIC33FJ32(GP/MC)101/102 devices only.
CH123NA1 CH123NA0 CH123SA
0000
CH0SA4 CH0SA3
CH0SA2
CH0SA1
CH0SA0
0000
0000
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 64
TABLE 4-16:
ADC1 REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
File Name
SFR
Addr
ADC1BUF0
0300
ADC1 Data Buffer 0
xxxx
ADC1BUF1
0302
ADC1 Data Buffer 1
xxxx
ADC1BUF2
0304
ADC1 Data Buffer 2
xxxx
ADC1BUF3
0306
ADC1 Data Buffer 3
xxxx
ADC1BUF4
0308
ADC1 Data Buffer 4
xxxx
ADC1BUF5
030A
ADC1 Data Buffer 5
xxxx
ADC1BUF6
030C
ADC1 Data Buffer 6
xxxx
ADC1BUF7
030E
ADC1 Data Buffer 7
xxxx
ADC1BUF8
0310
ADC1 Data Buffer 8
xxxx
ADC1BUF9
0312
ADC1 Data Buffer 9
xxxx
ADC1BUFA
0314
ADC1 Data Buffer 10
xxxx
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADC1BUFB
0316
ADC1 Data Buffer 11
xxxx
ADC1BUFC
0318
ADC1 Data Buffer 12
xxxx
ADC1BUFD
031A
ADC1 Data Buffer 13
xxxx
ADC1BUFE
031C
ADC1 Data Buffer 14
xxxx
ADC1BUFF
031E
ADC1 Data Buffer 15
AD1CON1
0320
ADON
—
ADSIDL
—
—
—
FORM1
FORM0
SSRC2
SSRC1
SSRC0
—
SIMSAM
ASAM
SAMP
DONE
0000
AD1CON2
0322
VCFG2
VCFG1
VCFG0
—
—
CSCNA
CHPS1
CHPS0
BUFS
—
SMPI3
SMPI2
SMPI1
SMPI0
BUFM
ALTS
0000
AD1CON3
0324
ADRC
—
—
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
—
—
—
—
—
—
—
—
—
—
—
—
CH0SA4
CH0SA3
AD1CHS123 0326
CH123NB1 CH123NB0 CH123SB
xxxx
CH123NA1 CH123NA0
ADCS0
0000
CH123SA
0000
CH0SA0
0000
AD1CHS0
0328
CH0NB
—
—
AD1PCFGL
032C PCFG15
—
—
PCFG(1)
0000
AD1CSSL
0330
—
—
CSS12:0>(1)
0000
CSS15
CH0SB4 CH0SB3
CH0SB2
CH0SB1
CH0SB0
CH0NA
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The PCFG and CSS bits are available in dsPIC33FJ32(GP/MC)104 devices only.
CH0SA2
CH0SA1
DS70000652F-page 65
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2011-2014 Microchip Technology Inc.
TABLE 4-17:
File Name
SFR
Addr
CTMUCON1 033A
CTMU REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CTMUEN
—
CTMUSIDL
TGEN
EDGEN
EDGSEQEN
IDISSEN
CTTRIG
—
—
—
—
—
—
—
—
0000
CTMUCON2 033C EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0
—
—
0000
CTMUICON 033E
—
—
0000
Legend:
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
—
—
—
—
—
—
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19:
File Name
SFR
Addr
ALRMVAL
0620
ALCFGRPT
0622
RTCVAL
0624
RCFGCAL
0626
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
RTCEN
—
RTCWREN RTCSYNC HALFSEC
RTCOE
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
0000
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
0000
Alarm Value Register Window based on ALRMPTR
ALRMPTR1 ALRMPTR0
ARPT7
ARPT6
xxxx
RTCC Value Register Window based on RTCPTR
RTCPTR1
RTCPTR0
CAL7
CAL6
xxxx
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20:
PAD CONFIGURATION REGISTER MAP
File Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PADCFG1
02FC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RTSECSEL
—
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 66
TABLE 4-18:
File Name
SFR
Addr
COMPARATOR REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CMSTAT
0650 CMSIDL
—
—
—
—
C3EVT
C2EVT
C1EVT
—
—
—
—
—
C3OUT
C2OUT
C1OUT
0000
CVRCON
0652
—
—
—
—
—
VREFSEL
BGSEL1
BGSEL0
CVREN
CVROE
CVRR
—
CVR3
CVR2
CVR1
CVR0
0000
CM1CON
0654
CON
COE
CPOL
—
—
—
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
CM1MSKSRC 0656
—
—
—
—
CM1MSKCON 0658
OCEN OCNEN
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
HLMS
—
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
CM1FLTR
065A
—
—
—
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
CM2CON
065C
CON
COE
CPOL
—
—
—
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
CM2MSKSRC 065E
—
—
—
—
CM2MSKCON 0660
HLMS
—
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
CM2FLTR
0662
—
—
—
—
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
CM3CON
0664
CON
COE
CPOL
—
—
—
CEVT
COUT
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
0000
CM3MSKSRC 0666
—
—
—
—
CM3MSKCON 0668
HLMS
—
—
—
CM3FLTR
066A
OCEN OCNEN
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
OCEN OCNEN
—
SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0 0000
OBEN
OBNEN
OAEN
OANEN
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
0000
—
—
—
—
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
0000
—
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-22:
File
Name
PERIPHERAL PIN SELECT INPUT REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
—
—
—
—
—
DS70000652F-page 67
RPINR0
0680
—
—
—
RPINR1
0682
—
—
—
RPINR3
0686
—
—
—
T3CKR
—
—
RPINR4
0688
—
—
—
T5CKR(1)
—
—
RPINR7
068E
—
—
—
IC2R
—
RPINR8
0690
—
—
—
—
—
—
—
—
RPINR11
0696
—
—
—
—
—
—
—
—
RPINR18
06A4
—
—
—
RPINR20
06A8
—
—
—
RPINR21
06AA
—
—
—
INT1R
—
—
—
Bit 2
Bit 1
Bit 0
—
—
—
All
Resets
1F00
INT2R
001F
—
T2CKR
1F1F
—
T4CKR(1)
1F1F
—
—
IC1R
1F1F
—
—
—
IC3R
001F
—
—
—
OCFAR
001F
U1CTSR
—
—
—
U1RXR
1F1F
SCK1R(1)
—
—
—
SDI1R(1)
1F1F
—
—
—
SS1R
001F
—
—
—
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These bits are available in dsPIC33FJ32(GP/MC)10X devices only.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
2011-2014 Microchip Technology Inc.
TABLE 4-21:
File
Name
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXGP101 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
—
—
RP1R
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 7
Bit 6
Bit 5
—
—
—
RP0R
0000
—
—
—
RP4R
0000
RPOR0
06C0
—
—
—
RPOR2
06C4
—
—
—
RPOR3
06C6
—
—
—
RP7R
—
—
—
RPOR4
06C8
—
—
—
RP9R
—
—
—
RP8R
0000
RPOR7
06CE
—
—
—
RP15R
—
—
—
RP14R
0000
—
—
—
—
—
—
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24:
File
Name
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXXMC101 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
—
—
—
RPOR2
06C4
—
—
—
RPOR3
06C6
—
—
—
RPOR4
06C8
—
—
RPOR6
06CC
—
—
RPOR7
06CE
—
—
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
—
—
—
—
—
RP0R
—
—
—
RP4R
RP7R
—
—
—
—
RP9R
—
—
—
RP8R
0000
—
RP13R
—
—
—
RP12R
0000
—
RP15R
—
—
—
RP14R
0000
RP1R
—
Bit 4
—
Bit 3
—
Bit 2
—
Bit 1
Bit 0
All
Resets
Bit 7
0000
0000
—
—
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25:
File
Name
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJXX(GP/MC)102 DEVICES
2011-2014 Microchip Technology Inc.
SFR
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
—
—
—
RPOR1
06C2
—
—
—
RPOR2
06C4
—
—
RPOR3
06C6
—
RPOR4
06C8
RPOR5
Bit 12
Bit 11
Bit 10
Bit 8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 7
Bit 6
Bit 5
RP1R
—
—
—
RP0R
0000
RP3R
—
—
—
RP2R
0000
—
RP5R
—
—
—
RP4R
0000
—
—
RP7R
—
—
—
RP6R
0000
—
—
—
RP9R
—
—
—
RP8R
0000
06CA
—
—
—
RP11R
—
—
—
RP10R
0000
RPOR6
06CC
—
—
—
RP13R
—
—
—
RP12R
0000
RPOR7
06CE
—
—
—
RP15R
—
—
—
RP14R
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 9
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 68
TABLE 4-23:
File
Name
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32(GP/MC)104 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
—
—
—
RPOR1
06C2
—
—
—
RPOR2
06C4
—
—
RPOR3
06C6
—
—
RPOR4
06C8
—
RPOR5
06CA
RPOR6
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 7
Bit 6
Bit 5
RP1R
—
—
—
RP0R
0000
RP3R
—
—
—
RP2R
0000
—
RP5R
—
—
—
RP4R
0000
—
RP7R
—
—
—
RP6R
0000
—
—
RP9R
—
—
—
RP8R
0000
—
—
—
RP11R
—
—
—
RP10R
0000
06CC
—
—
—
RP13R
—
—
—
RP12R
0000
RPOR7
06CE
—
—
—
RP15R
—
—
—
RP14R
0000
RPOR8
06D0
—
—
—
RP17R
—
—
—
RP16R
0000
RPOR9
06D2
—
—
—
RP19R
—
—
—
RP18R
0000
RPOR10
06D4
—
—
—
RP21R
—
—
—
RP20R
0000
RPOR11
06D6
—
—
—
RP23R
—
—
—
RP22R
0000
RPOR12
06D8
—
—
—
RP25R
—
—
—
RP24R
0000
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-27:
File
Name
PORTA REGISTER MAP FOR dsPIC33FJ16(GP/MC)101/102 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
02C0
—
—
—
—
—
—
—
—
—
—
—
TRISA
001F
PORTA
02C2
—
—
—
—
—
—
—
—
—
—
—
RA VIN-
DS70000652F-page 234
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-2:
CMxCON: COMPARATOR x CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
CON
COE
CPOL
—
—
—
CEVT
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
EVPOL1
EVPOL0
—
CREF
—
—
CCH1
CCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CON: Comparator x Enable bit
1 = Comparator x is enabled
0 = Comparator x is disabled
bit 14
COE: Comparator x Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13
CPOL: Comparator x Output Polarity Select bit
1 = Comparator x output is inverted
0 = Comparator x output is not inverted
bit 12-10
Unimplemented: Read as ‘0’
bit 9
CEVT: Comparator x Event bit
1 = Comparator x event according to EVPOL settings occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator x event did not occur
bit 8
COUT: Comparator x Output bit
When CPOL = 0 (non-inverted polarity):
1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1 (inverted polarity):
1 = VIN+ < VIN0 = VIN+ > VIN-
bit 7-6
EVPOL: Trigger/Event/Interrupt Polarity Select bits
11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt is generated only on high-to-low transition of the polarity selected
comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt is generated only on low-to-high transition of the polarity selected
comparator output (while CEVT = 0)
If CPOL = 1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL = 0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5
Unimplemented: Read as ‘0’
2011-2014 Microchip Technology Inc.
DS70000652F-page 235
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-2:
CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
bit 4
CREF: Comparator x Reference Select bit (VIN+ input)
1 = VIN+ input connects to internal CVREFIN voltage
0 = VIN+ input connects to CxINA pin
bit 3-2
Unimplemented: Read as ‘0’
bit 1-0
CCH: Comparator x Channel Select bits
11 = VIN- input of comparator connects to INTREF
10 = VIN- input of comparator connects to CXIND pin
01 = VIN- input of comparator connects to CXINC pin
00 = VIN- input of comparator connects to CXINB pin
DS70000652F-page 236
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT REGISTER
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
RW-0
—
—
—
—
SELSRCC3
SELSRCC2
SELSRCC1
SELSRCC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SELSRCB3
SELSRCB2
SELSRCB1
SELSRCB0
SELSRCA3
SELSRCA2
SELSRCA1
SELSRCA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
SELSRCC: Mask C Input Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM1H3
0100 = PWM1L3
0011 = PWM1H2
0010 = PWM1L2
0001 = PWM1H1
0000 = PWM1L1
bit 7-4
SELSRCB: Mask B Input Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM1H3
0100 = PWM1L3
0011 = PWM1H2
0010 = PWM1L2
0001 = PWM1H1
0000 = PWM1L1
2011-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000652F-page 237
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-3: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT REGISTER (CONTINUED)
bit 3-0
SELSRCA: Mask A Input Select bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM1H3
0100 = PWM1L3
0011 = PWM1H2
0010 = PWM1L2
0001 = PWM1H1
0000 = PWM1L1
DS70000652F-page 238
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-4:
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
OANEN
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NAGS
PAGS
ACEN
ACNEN
ABEN
ABNEN
AAEN
AANEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
HLMS: High or Low Level Masking Select bits
1 = The masking (blanking) function will prevent any asserted (‘0’) comparator signal from propagating
0 = The masking (blanking) function will prevent any asserted (‘1’) comparator signal from propagating
bit 14
Unimplemented: Read as ‘0’
bit 13
OCEN: OR Gate C Input Inverted Enable bit
1 = MCI is connected to OR gate
0 = MCI is not connected to OR gate
bit 12
OCNEN: OR Gate C Input Inverted Enable bit
1 = Inverted MCI is connected to OR gate
0 = Inverted MCI is not connected to OR gate
bit 11
OBEN: OR Gate B Input Inverted Enable bit
1 = MBI is connected to OR gate
0 = MBI is not connected to OR gate
bit 10
OBNEN: OR Gate B Input Inverted Enable bit
1 = Inverted MBI is connected to OR gate
0 = Inverted MBI is not connected to OR gate
bit 9
OAEN: OR Gate A Input Enable bit
1 = MAI is connected to OR gate
0 = MAI is not connected to OR gate
bit 8
OANEN: OR Gate A Input Inverted Enable bit
1 = Inverted MAI is connected to OR gate
0 = Inverted MAI is not connected to OR gate
bit 7
NAGS: Negative AND Gate Output Select
1 = Inverted ANDI is connected to OR gate
0 = Inverted ANDI is not connected to OR gate
bit 6
PAGS: Positive AND Gate Output Select
1 = ANDI is connected to OR gate
0 = ANDI is not connected to OR gate
bit 5
ACEN: AND Gate A1 C Input Inverted Enable bit
1 = MCI is connected to AND gate
0 = MCI is not connected to AND gate
bit 4
ACNEN: AND Gate A1 C Input Inverted Enable bit
1 = Inverted MCI is connected to AND gate
0 = Inverted MCI is not connected to AND gate
2011-2014 Microchip Technology Inc.
DS70000652F-page 239
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-4:
CMxMSKCON: COMPARATOR x MASK GATING CONTROL
REGISTER (CONTINUED)
bit 3
ABEN: AND Gate A1 B Input Inverted Enable bit
1 = MBI is connected to AND gate
0 = MBI is not connected to AND gate
bit 2
ABNEN: AND Gate A1 B Input Inverted Enable bit
1 = Inverted MBI is connected to AND gate
0 = Inverted MBI is not connected to AND gate
bit 1
AAEN: AND Gate A1 A Input Enable bit
1 = MAI is connected to AND gate
0 = MAI is not connected to AND gate
bit 0
AANEN: AND Gate A1 A Input Inverted Enable bit
1 = Inverted MAI is connected to AND gate
0 = Inverted MAI is not connected to AND gate
DS70000652F-page 240
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-5:
CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
CFSEL2
CFSEL1
CFSEL0
CFLTREN
CFDIV2
CFDIV1
CFDIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
CFSEL: Comparator Filter Input Clock Select bits
111 = Reserved
110 = Reserved
101 = Timer3
100 = Timer2
011 = Reserved
010 = PWM Special Event Trigger
001 = FOSC
000 = FCY
bit 3
CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0
CFDIV: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
2011-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000652F-page 241
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 20-6:
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
VREFSEL
BGSEL1
BGSEL0
bit 15
bit 8
R/W-0
R/W-0
CVREN
CVROE
(1)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
CVRR
—
CVR3
CVR2
CVR1
CVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10
VREFSEL: Voltage Reference Select bit
1 = CVREFIN = CVREF pin
0 = CVREFIN is generated by the resistor network
bit 9-8
BGSEL: Band Gap Reference Source Select bits
11 = INTREF = CVREF pin
10 = INTREF = 1.2V (nominal)(2)
0x = Reserved
bit 7
CVREN: Comparator Voltage Reference Enable bit
1 = Comparator voltage reference circuit is powered on
0 = Comparator voltage reference circuit is powered down
bit 6
CVROE: Comparator Voltage Reference Output Enable bit(1)
1 = Voltage level is output on CVREF pin
0 = Voltage level is disconnected from CVREF pin
bit 5
CVRR: Comparator Voltage Reference Range Selection bit
1 = CVRSRC/24 step-size
0 = CVRSRC/32 step-size
bit 4
Unimplemented: Read as ‘0’
bit 3-0
CVR: Comparator Voltage Reference Value Selection 0 CVR 15 bits
When CVRR = 1:
CVREFIN = (CVR/24) • (CVRSRC)
When CVRR = 0:
CVREFIN = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC)
Note 1:
2:
CVROE overrides the TRISx bit setting.
This reference voltage is generated internally on the device. Refer to Section 26.0 “Electrical Characteristics”
for the specified voltage range.
DS70000652F-page 242
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
21.0
REAL-TIME CLOCK AND
CALENDAR (RTCC)
Some of the key features of the RTCC module are:
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
device families of devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to “Real-Time Clock
and Calendar (RTCC)” (DS70310) in the
“dsPIC33/PIC24 Family Reference Manual”, which is available on the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This chapter discusses the Real-Time Clock
and Calendar (RTCC) module, available
on
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 devices, and its
operation.
•
•
•
•
•
•
•
•
•
•
•
•
Time: hours, minutes and seconds
24-hour format (military time)
Calendar: weekday, date, month and year
Alarm configurable
Year range: 2000 to 2099
Leap year correction
BCD format for compact firmware
Optimized for low-power operation
User calibration with auto-adjust
Calibration range: ±2.64 seconds error per month
Requirements: external 32.768 kHz clock crystal
Alarm pulse or seconds clock output on RTCC pin
The RTCC module is intended for applications where
accurate time must be maintained for extended periods
of time with minimum to no intervention from the CPU.
The RTCC module is optimized for low-power usage to
provide extended battery lifetime while keeping track of
time.
The RTCC module is a 100-year clock and calendar
with automatic leap year detection. The range of the
clock is from 00:00:00 (midnight) on January 1, 2000 to
23:59:59 on December 31, 2099.
The hours are available in 24-hour (military time)
format. The clock provides a granularity of one second
with half-second visibility to the user.
FIGURE 21-1:
RTCC BLOCK DIAGRAM
RTCC Clock Domain
32.768 kHz Input
from SOSC Oscillator
CPU Clock Domain
RCFGCAL
RTCC Prescalers
ALCFGRPT
0.5s
RTCC Timer
RTCVAL
Alarm
Event
Comparator
Compare Registers
with Masks
ALRMVAL
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE
2011-2014 Microchip Technology Inc.
DS70000652F-page 243
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
21.1
RTCC Module Registers
The RTCC module registers are organized into three
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
21.1.1
By writing the ALRMVALH byte, the Alarm Pointer
value (ALRMPTR bits) decrements by one until it
reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and
ALRMSEC value will be accessible through
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
TABLE 21-2:
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through
corresponding register pointers. The RTCC Value
register window (RTCVALH and RTCVALL) uses the
RTCPTR bits (RCFGCAL) to select the desired
Timer register pair (see Table 21-1).
By writing the RTCVALH byte, the RTCC Pointer value
(RTCPTR bits) decrements by one until it
reaches ‘00’. Once it reaches ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
TABLE 21-1:
RTCVAL REGISTER MAPPING
ALRMPTR
RTCVAL
RTCVAL
00
MINUTES
SECONDS
01
WEEKDAY
HOURS
10
MONTH
DAY
11
—
YEAR
ALRMMIN
ALRMSEC
01
ALRMWD
ALRMHR
10
ALRMMNTH
ALRMDAY
11
—
—
21.1.2
This only applies to read operations and
not write operations.
WRITE LOCK
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL) must be
set (refer to Example 21-1).
Note:
To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only 1 instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 21-1.
SETTING THE RTCWREN BIT
#NVMKEY, W1
#0x55, W2
#0xAA, W3
W2, [W1]
W3, [W1]
RCFGCAL, #13
DS70000652F-page 244
ALRMVAL ALRMVAL
00
Note:
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits (ALCFGRPT)
to select the desired Alarm register pair (see Table 21-2).
EXAMPLE 21-1:
Alarm Value Register Window
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL, bytes will decrement the ALRMPTR
value. The same applies to the RTCVALH or RTCVALL
bytes with the RTCPTR being decremented.
RTCC Value Register Window
RTCPTR
MOV
MOV
MOV
MOV
MOV
BSET
ALRMVAL REGISTER
MAPPING
REGISTER MAPPING
;move the address of NVMKEY into W1
;start 55/AA sequence
;set the RTCWREN bit
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
21.2
RTCC Control Registers
REGISTER 21-1:
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
R/W-0
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
RTCEN(2)
—
RTCWREN
RTCSYNC
HALFSEC(3)
RTCOE
RTCPTR1
RTCPTR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
RTCWREN: RTCC Value Registers Write Enable bit
1 = RTCVALH and RTCVALL registers can be written to by the user
0 = RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading, due to a rollover ripple,
resulting in an invalid data read. If the register is read twice and the results are the same data, the
data can be assumed to be valid.
0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11
HALFSEC: Half-Second Status bit(3)
1 = Second half period of a second
0 = First half period of a second
bit 10
RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8
RTCPTR: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers;
the RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL:
00 = MINUTES
01 = WEEKDAY
10 = MONTH
11 = Reserved
RTCVAL:
00 = SECONDS
01 = HOURS
10 = DAY
11 = YEAR
Note 1:
2:
3:
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
2011-2014 Microchip Technology Inc.
DS70000652F-page 245
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-1:
bit 7-0
Note 1:
2:
3:
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED)
CAL: RTC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute
•
•
•
00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
•
•
•
10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
The RCFGCAL register is only affected by a POR.
A write to the RTCEN bit is only allowed when RTCWREN = 1.
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.
DS70000652F-page 246
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-2:
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
U-0
—
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
(1)
RTSECSEL
bit 7
—
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-2
Unimplemented: Read as ‘0’
bit 1
RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1 = RTCC seconds clock is selected for the RTCC pin
0 = RTCC alarm pulse is selected for the RTCC pin
bit 0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
2011-2014 Microchip Technology Inc.
DS70000652F-page 247
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-3:
ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
ALRMPTR1
ALRMPTR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 0x00 and
CHIME = 0)
0 = Alarm is disabled
bit 14
CHIME: Chime Enable bit
1 = Chime is enabled; ARPT bits are allowed to roll over from 0x00 to 0xFF
0 = Chime is disabled; ARPT bits stop once they reach 0x00
bit 13-10
AMASK: Alarm Mask Configuration bits
0000 = Every half second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved – do not use
11xx = Reserved – do not use
bit 9-8
ALRMPTR: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;
the ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL:
00 = ALRMMIN
01 = ALRMWD
10 = ALRMMNTH
11 = Unimplemented
ALRMVAL:
00 = ALRMSEC
01 = ALRMHR
10 = ALRMDAY
11 = Unimplemented
bit 7-0
ARPT: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
•
•
•
00000000 = Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to
0xFF unless CHIME = 1.
DS70000652F-page 248
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-4:
RTCVAL (WHEN RTCPTR = 11): RTCC YEAR VALUE REGISTER(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
Unimplemented: Read as ‘0’
bit 7-4
YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits
Contains a value from 0 to 9.
bit 3-0
YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
REGISTER 21-5:
RTCVAL (WHEN RTCPTR = 10): RTCC MONTH AND DAY VALUE
REGISTER(1)
U-0
U-0
U-0
R-x
R-x
R-x
R-x
R-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8
MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
2011-2014 Microchip Technology Inc.
DS70000652F-page 249
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-6:
RTCVAL (WHEN RTCPTR = 01): RTCC WEEKDAY AND HOURS VALUE
REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
WDAY: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
DS70000652F-page 250
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-7:
RTCVAL (WHEN RTCPTR = 00): RTCC MINUTES AND SECONDS VALUE
REGISTER
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
2011-2014 Microchip Technology Inc.
x = Bit is unknown
DS70000652F-page 251
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-8:
ALRMVAL (WHEN ALRMPTR = 10): ALARM MONTH AND DAY VALUE
REGISTER(1)
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit
Contains a value of 0 or 1.
bit 11-8
MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits
Contains a value from 0 to 9.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits
Contains a value from 0 to 3.
bit 3-0
DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
A write to this register is only allowed when RTCWREN = 1.
DS70000652F-page 252
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-9:
ALRMVAL (WHEN ALRMPTR = 01): ALARM WEEKDAY AND HOURS
VALUE REGISTER(1)
U-0
U-0
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
—
—
—
—
—
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
—
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10-8
WDAY: Binary Coded Decimal Value of Weekday Digit bits
Contains a value from 0 to 6.
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits
Contains a value from 0 to 9.
Note 1:
x = Bit is unknown
A write to this register is only allowed when RTCWREN = 1.
2011-2014 Microchip Technology Inc.
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dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 21-10: ALRMVAL (WHEN ALRMPTR = 00): ALARM MINUTES AND SECONDS
VALUE REGISTER
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 15
bit 8
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits
Contains a value from 0 to 5.
bit 11-8
MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits
Contains a value from 0 to 5.
bit 3-0
SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits
Contains a value from 0 to 9.
DS70000652F-page 254
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
22.0
CHARGE TIME
MEASUREMENT UNIT (CTMU)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
device families of devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to “Charge Time
Measurement Unit (CTMU)” (DS70635)
in the “dsPIC33/PIC24 Family Reference
Manual”, which is available on the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Together with other on-chip analog modules, the CTMU
can be used to precisely measure time, measure
capacitance, measure relative changes in capacitance
or generate output pulses that are independent of the
system clock.
The CTMU module is ideal for interfacing with
capacitive-based sensors. The CTMU is controlled
through three registers: CTMUCON1, CTMUCON2
and CTMUICON. CTMUCON1 enables the module,
the edge delay generation, sequencing of edges, and
controls the current source and the output trigger.
CTMUCON2 controls the edge source selection, edge
source polarity selection and edge sampling mode. The
CTMUICON register controls the selection and trim of
the current source.
Figure 22-1 shows the CTMU block diagram.
The Charge Time Measurement Unit (CTMU) is a flexible
analog module that provides accurate differential time
measurement between pulse sources, as well as
asynchronous pulse generation. Its key features include:
•
•
•
•
•
•
Four edge input trigger sources
Polarity control for each edge source
Control of edge sequence
Control of response to edges
Precise time measurement resolution of 200 ps
Accurate current source suitable for capacitive
measurement
• On-chip temperature measurement using a
built-in diode
2011-2014 Microchip Technology Inc.
DS70000652F-page 255
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 22-1:
CTMU BLOCK DIAGRAM
CTMUCON1 or CTMUCON2
CTMUICON
ITRIM
IRNG
Current Source
Edge
Control
Logic
CTED1
CTED2
Timer1
OC1
IC1
CMP2
EDG1STAT
EDG2STAT
TGEN
Current
Control
CTMUP
CTMU
Control
Logic
Pulse
Generator
Analog-to-Digital
Trigger
CTPLS
CTMUI to ADC
CTMU TEMP
CTMU
Temperature
Sensor
C2INA
CDelay
Comparator 2
External Capacitor
for Pulse Generation
Current Control Selection
CTMU TEMP
DS70000652F-page 256
TGEN
EDG1STAT, EDG2STAT
0
EDG1STAT = EDG2STAT
CTMUI
0
EDG1STAT EDG2STAT
CTMUP
1
EDG1STAT EDG2STAT
No Connect
1
EDG1STAT = EDG2STAT
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
22.1
CTMU Control Registers
REGISTER 22-1:
CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CTMUEN
—
CTMUSIDL
TGEN(1)
EDGEN
EDGSEQEN
IDISSEN(2)
CTTRIG
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13
CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12
TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11
EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10
EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9
IDISSEN: Analog Current Source Control bit(2)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8
CTTRIG: CTMU Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
2:
x = Bit is unknown
If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more
information, see Section 10.4 “Peripheral Pin Select (PPS)”.
The ADC module S&H capacitor is not automatically discharged between sample/conversion cycles.
Software using the ADC as part of a capacitance measurement must discharge the ADC capacitor before
conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC must be
sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array.
2011-2014 Microchip Technology Inc.
DS70000652F-page 257
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 22-2:
CTMUCON2: CTMU CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG1MOD
EDG1POL
EDG1SEL3
EDG1SEL2
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
EDG2MOD
EDG2POL
EDG2SEL3
EDG2SEL2
EDG2SEL1
EDG2SEL0
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
EDG1MOD: Edge 1 Edge Sampling Selection bit
1 = Edge 1 is edge-sensitive
0 = Edge 1 is level-sensitive
bit 14
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 13-10
EDG1SEL: Edge 1 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED1 pin
0010 = CTED2 pin
0001 = OC1 module
0000 = Timer1 module
bit 9
EDG2STAT: Edge 2 Status bit
Indicates the status of Edge 2 and can be written to control the edge source.
1 = Edge 2 has occurred
0 = Edge 2 has not occurred
bit 8
EDG1STAT: Edge 1 Status bit
Indicates the status of Edge 1 and can be written to control the edge source.
1 = Edge 1 has occurred
0 = Edge 1 has not occurred
bit 7
EDG2MOD: Edge 2 Edge Sampling Selection bit
1 = Edge 2 is edge-sensitive
0 = Edge 2 is level-sensitive
bit 6
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 5-2
EDG2SEL: Edge 2 Source Select bits
1xxx = Reserved
01xx = Reserved
0011 = CTED2 pin
0010 = CTED1 pin
0001 = Comparator 2 module
0000 = IC1 module
bit 1-0
Unimplemented: Read as ‘0’
DS70000652F-page 258
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 22-3:
CTMUICON: CTMU CURRENT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-10
ITRIM: Current Source Trim bits
011111 = Nominal current output specified by IRNG + 62%
011110 = Nominal current output specified by IRNG + 60%
•
•
•
000001 = Nominal current output specified by IRNG + 2%
000000 = Nominal current output specified by IRNG
111111 = Nominal current output specified by IRNG – 2%
•
•
•
100010 = Nominal current output specified by IRNG – 62%
100001 = Nominal current output specified by IRNG – 64%
bit 9-8
IRNG: Current Source Range Select bits
11 = 100 Base Current(1)
10 = 10 Base Current
01 = Base current level (0.55 A nominal)
00 = Reserved
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
x = Bit is unknown
This setting must be used for the CTMU temperature sensor.
2011-2014 Microchip Technology Inc.
DS70000652F-page 259
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
NOTES:
DS70000652F-page 260
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.0
SPECIAL FEATURES
Note 1: This data sheet summarizes the
features of the dsPIC33FJ16(GP/
MC)101/102
and
dsPIC33FJ32(GP/
MC)101/102/104 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to “Programming
and Diagnostics” (DS70207) and
“Device Configuration” (DS70194) in
the “dsPIC33/PIC24 Family Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/
MC)101/102/104 devices include several features
intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
•
•
•
•
•
Flexible Configuration
Watchdog Timer (WDT)
Code Protection
In-Circuit Serial Programming™ (ICSP™)
In-Circuit Emulation
23.1
Configuration Bits
The Configuration Shadow register bits can be configured (read as ‘0’) or left unprogrammed (read as ‘1’) to
select various device configurations. These read-only
bits are mapped starting at program memory location,
0xF80000. A detailed explanation of the various bit
functions is provided in Table 23-4.
In
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 devices, the Configuration bytes are implemented as volatile memory.
This means that configuration data must be programmed
each time the device is powered up. Configuration data
is stored in the two words at the top of the on-chip program memory space, known as the Flash Configuration
Words. Their specific locations are shown in Table 23-2.
These are packed representations of the actual device
Configuration bits, whose actual locations are distributed
among several locations in configuration space. The configuration data is automatically loaded from the Flash
Configuration Words to the proper Configuration
registers during device Resets.
Note:
Configuration data is reloaded on all types
of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in program memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
Note:
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
operations on the last page of program
memory.
Note that address, 0xF80000, is beyond the user program memory space and belongs to the configuration
memory space (0x800000-0xFFFFFF), which can only
be accessed using Table Reads.
2011-2014 Microchip Technology Inc.
DS70000652F-page 261
TABLE 23-1:
File Name
CONFIGURATION SHADOW REGISTER MAP
Addr.
FGS
F80004
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
GCP
GWRP
FOSCSEL
F80006
IESO
PWMLOCK(1)
—
WDTWIN1
WDTWIN0
FNOSC2
FNOSC1
FNOSC0
FOSC
F80008
FCKSM1
FCKSM0
IOL1WAY
—
—
OSCIOFNC
POSCMD1
POSCMD0
FWDT
F8000A
FWDTEN
WINDIS
PLLKEN
WDTPRE
WDTPOST3
WDTPOST2
WDTPOST1
WDTPOST0
FPOR
F8000C
PWMPIN(1)
HPOL(1)
LPOL(1)
ALTI2C1
—
—
—
—
FICD
F8000E
Reserved(2)
—
Reserved(3)
Reserved(3)
—
—
ICS1
ICS0
Legend:
Note 1:
2:
3:
— = unimplemented, read as ‘1’.
These bits are available in dsPIC33FJ(16/32)MC10X devices only.
This bit is reserved for use by development tools.
These bits are reserved, program as ‘0’.
The Configuration Flash Word maps are shown in Table 23-2 and Table 23-3.
TABLE 23-2:
File
Name
Addr.
CONFIG2 002BFC
CONFIG1 002BFE
Legend:
Note 1:
2:
3:
4:
5:
2011-2014 Microchip Technology Inc.
Addr.
CONFIG2 0057FC
CONFIG1 0057FE
Legend:
Note 1:
2:
3:
4:
5:
Bits 23-16
Bit 15
—
IESO
—
Reserved(3)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
PWMLOCK(2) PWMPIN(2) WDTWIN1 WDTWIN0 FNOSC2 FNOSC1 FNOSC0 FCKSM1 FCKSM0 OSCIOFNC(5) IOL1WAY
Reserved(3)
GCP
GWRP
Reserved(4)
HPOL(2)
ICS1
ICS0
FWDTEN WINDIS
PLLKEN
Bit 3
Bit 2
Bit 1
Bit 0
LPOL(2)
ALTI2C1
POSCMD1
POSCMD0
WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0
— = unimplemented, read as ‘1’.
During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
These bits are reserved in dsPIC33FJ16GP10X devices and read as ‘1’.
These bits are reserved, program as ‘0’.
This bit is reserved for use by development tools and must be programmed as ‘1’.
This bit is programmed to ‘0’ during final tests in the factory.
TABLE 23-3:
File
Name
CONFIGURATION FLASH WORDS FOR dsPIC33FJ16(GP/MC)10X DEVICES(1)
CONFIGURATION FLASH WORDS FOR dsPIC33FJ32(GP/MC)10X DEVICES(1)
Bits 23-16
Bit 15
—
IESO
—
Reserved(3)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
PWMLOCK(2) PWMPIN(2) WDTWIN1 WDTWIN0 FNOSC2 FNOSC1 FNOSC0 FCKSM1 FCKSM0 OSCIOFNC(5) IOL1WAY
Reserved(3)
GCP
GWRP
Reserved(4)
HPOL(2)
ICS1
ICS0
FWDTEN WINDIS
— = unimplemented, read as ‘1’.
During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
These bits are reserved in dsPIC33FJ32GP10X devices and read as ‘1’.
These bits are reserved, program as ‘0’.
This bit is reserved for use by development tools and must be programmed as ‘1’.
This bit is programmed to ‘0’ during final tests in the factory.
PLLKEN
Bit 3
Bit 2
Bit 1
Bit 0
LPOL(2)
ALTI2C1
POSCMD1
POSCMD0
WDTPRE WDTPOST3 WDTPOST2 WDTPOST1 WDTPOST0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 262
The Configuration Shadow register map is shown in Table 23-1.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 23-4:
dsPIC33F CONFIGURATION BITS DESCRIPTION
Bit Field
Description
GCP
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = Code protection is enabled for the entire program memory space
GWRP
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
IESO
Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the user-selected oscillator source
when ready
0 = Starts up device with user-selected oscillator source
PWMLOCK
PWM Lock Enable bit
1 = Certain PWM registers may only be written after a key sequence
0 = PWM registers may be written without a key sequence
WDTWIN
Watchdog Timer Window Select bits
11 = WDT window is 24% of WDT period
10 = WDT window is 37.5% of WDT period
01 = WDT window is 50% of WDT period
00 = WDT window is 75% of WDT period
FNOSC
Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Reserved; do not use
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL)
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator with Divide-by-N and PLL module (FRCDIVN + PLL)
000 = Fast RC Oscillator (FRC)
FCKSM
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
OSCIOFNC
OSC2 Pin Function bit (except in MS and HS modes)
1 = OSC2 is a clock output
0 = OSC2 is a general purpose digital I/O pin
POSCMD
Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode (10 MHz-32 MHz)
01 = MS Crystal Oscillator mode (3 MHz-10 MHz)
00 = EC (External Clock) mode (DC-32 MHz)
FWDTEN
Watchdog Timer Enable bit
1 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN
bit in the RCON register will have no effect)
0 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by clearing the
SWDTEN bit in the RCON register)
WINDIS
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
2011-2014 Microchip Technology Inc.
DS70000652F-page 263
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 23-4:
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
WDTPRE
Description
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1
PLLKEN
PLL Lock Enable bit
1 = Clock switch to PLL will wait until the PLL lock signal is valid
0 = Clock switch will not wait for the PLL lock signal
ALTI2C
Alternate I2C™ Pins bit
1 = I2C is mapped to SDA1/SCL1 pins
0 = I2C is mapped to ASDA1/ASCL1 pins
ICS
ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
PWMPIN
Motor Control PWM Module Pin Mode bit
1 = PWM module pins controlled by PORT register at device Reset (tri-stated)
0 = PWM module pins controlled by PWM module at device Reset (configured as output pins)
HPOL
Motor Control PWM High Side Polarity bit
1 = PWM module high side output pins have active-high output polarity
0 = PWM module high side output pins have active-low output polarity
LPOL
Motor Control PWM Low Side Polarity bit
1 = PWM module low side output pins have active-high output polarity
0 = PWM module low side output pins have active-low output polarity
DS70000652F-page 264
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
REGISTER 23-1:
R
DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
(1)
DEVID
bit 23
bit 16
R
R
R
R
R
DEVID
R
R
R
(1)
bit 15
bit 8
R
R
R
R
R
DEVID
R
R
R
(1)
bit 7
bit 0
Legend: R = Read-Only bit
bit 23-0
Note 1:
DEIDV: Device Identifier bits(1)
Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits”
(DS70659) for the list of device ID values.
REGISTER 23-2:
R
U = Unimplemented bit
DEVREV: DEVICE REVISION REGISTER
R
R
R
R
R
R
R
DEVREV(1)
bit 23
bit 16
R
R
R
R
R
R
R
R
DEVREV(1)
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVREV(1)
bit 7
bit 0
Legend: R = Read-only bit
bit 23-0
Note 1:
U = Unimplemented bit
DEVREV: Device Revision bits(1)
Refer to the “dsPIC33F Flash Programming Specification for Devices with Volatile Configuration Bits”
(DS70659) for the list of device revision values.
2011-2014 Microchip Technology Inc.
DS70000652F-page 265
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.2
On-Chip Voltage Regulator
All of the dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices power
their core digital logic at a nominal 2.5V. This can
create a conflict for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the dsPIC33FJ16(GP/
MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP pin
(Figure 23-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor is provided in Table 26-14 located in Section 26.1
“DC Characteristics”.
Note:
It is important for low-ESR capacitors to be
placed as close as possible to the VCAP pin.
On a POR, it takes approximately 20 s for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 23-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
23.3
BOR: Brown-out Reset
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the
regulated supply voltage, VCAP. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC and
POSCMD).
If an Oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON) is ‘1’.
Concurrently, the PWRT Time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR status bit (RCON) is set to indicate that a
BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
3.3V
dsPIC33F
VDD
CEFC
10 µF
Tantalum
VCAP
VSS
Note 1: These are typical operating voltages. Refer to
Table 26-14 located in Section 26.1 “DC
Characteristics” for the full operating ranges
of VDD and VCAP.
2: It is important for low-ESR capacitors to be
placed as close as possible to the VCAP pin.
3: Typical VCAP pin voltage = 2.5V when
VDD VDDMIN.
DS70000652F-page 266
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.4
23.4.2
Watchdog Timer (WDT)
For
dsPIC33FJ16(GP/MC)101/102
and
dsPIC33FJ32(GP/MC)101/102/104 devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
23.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT Time-out (TWDT) period of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST
Configuration bits (FWDT), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
Note:
SLEEP AND IDLE MODES
If the WDT is enabled, it will continue to run during Sleep
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE bits
(RCON) will need to be cleared in software after the
device wakes up.
23.4.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed to
‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON). The SWDTEN control
bit is cleared on any device Reset. The software WDT
option allows the user application to enable the WDT for
critical code segments and disables the WDT during
non-critical segments for maximum power savings.
Note:
If the WINDIS bit (FWDT) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
The WDT flag bit, WDTO (RCON), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 23-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
Sleep/Idle
WDTPOST
WDTPRE
SWDTEN
FWDTEN
WDT
Wake-up
RS
Prescaler
(divide-by-N1)
LPRC Clock
1
RS
Postscaler
(divide-by-N2)
0
WINDIS
WDT
Reset
WDT Window Select
CLRWDT Instruction
2011-2014 Microchip Technology Inc.
DS70000652F-page 267
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
23.5
In-Circuit Serial Programming™
(ICSP™)
Devices can be serially programmed while in the end
application circuit. This is done with two lines for clock
and data and three other lines for power, ground and
the programming sequence. Serial programming
allows customers to manufacture boards with
unprogrammed devices and then program the Digital
Signal Controller just before shipping the product.
Serial programming also allows the most recent
firmware or a custom firmware to be programmed.
Refer to the “dsPIC33F Flash Programming
Specification for Devices with Volatile Configuration
Bits” (DS70659) for details about In-Circuit Serial
Programming (ICSP).
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS70000652F-page 268
23.6
In-Circuit Debugger
When MPLAB® ICD 3 is selected as a debugger, the incircuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
24.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes the
features of the dsPIC33FJ16(GP/
MC)101/102
and
dsPIC33FJ32(GP/
MC)101/102/104 devices. However, it is
not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
latest family reference sections of the
“dsPIC33/PIC24
Family
Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
•
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 24-1 shows the general symbols used in
describing the instructions.
The dsPIC33F instruction set summary in Table 24-2
lists all the instructions, along with the status flags
affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write-back destination
The other DSP instructions do not involve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
2011-2014 Microchip Technology Inc.
DS70000652F-page 269
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
Most instructions are a single word. Certain doubleword instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
TABLE 24-1:
as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all Table
Reads and Writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles.
Note:
For more details on the instruction set, refer
to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator write-back destination address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm, Wn
Dividend, Divisor Working register pair (direct addressing)
DS70000652F-page 270
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 24-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0..W15}
Wnd
One of 16 destination Working registers {W0..W15}
Wns
One of 16 source Working registers {W0..W15}
WREG
W0 (Working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X data space prefetch destination register for DSP instructions {W4..W7}
Wy
Y data space prefetch address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions {W4..W7}
2011-2014 Microchip Technology Inc.
DS70000652F-page 271
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 24-2:
Base
Instr
#
1
2
3
4
5
6
7
8
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
BCLR
BRA
BSET
BSW
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
ADD
Acc
Add Accumulators
1
1
ADD
f
f = f + WREG
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
C,DC,N,OV,Z
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
OA,OB,SA,SB
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
BCLR
f,#bit4
Bit Clear f
1
1
None
BCLR
Ws,#bit4
Bit Clear Ws
1
1
None
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if greater than or equal
1
1 (2)
None
BRA
GEU,Expr
Branch if unsigned greater than or equal
1
1 (2)
None
BRA
GT,Expr
Branch if greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if unsigned greater than
1
1 (2)
None
BRA
LE,Expr
Branch if less than or equal
1
1 (2)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1
1 (2)
None
BRA
LT,Expr
Branch if less than
1
1 (2)
None
BRA
LTU,Expr
Branch if unsigned less than
1
1 (2)
None
BRA
N,Expr
Branch if Negative
1
1 (2)
None
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1
1 (2)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
SA,Expr
Branch if Accumulator A saturated
1
1 (2)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws
1
1
None
DS70000652F-page 272
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 24-2:
Base
Instr
#
9
10
11
12
13
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTG
BTSC
BTSS
BTST
BTSTS
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws to C
1
1
C
BTST.Z
Ws,Wb
Bit Test Ws to Z
1
1
Z
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
lit23
Call subroutine
2
2
None
14
CALL
CALL
CALL
Wn
Call indirect subroutine
1
2
None
15
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA,OB,SA,SB
Clear Watchdog Timer
1
1
WDTO,Sleep
16
CLRWDT
17
COM
18
19
20
CP
CP0
CPB
CLRWDT
COM
f
f=f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
CP
Wb,#lit5
Compare Wb with lit5
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C,DC,N,OV,Z
CP0
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C,DC,N,OV,Z
21
CPSEQ
CPSEQ
Wb, Wn
Compare Wb with Wn, skip if =
1
1
(2 or 3)
None
22
CPSGT
CPSGT
Wb, Wn
Compare Wb with Wn, skip if >
1
1
(2 or 3)
None
23
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, skip if <
1
1
(2 or 3)
None
24
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, skip if
1
1
(2 or 3)
None
25
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
26
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C,DC,N,OV,Z
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
27
28
DEC2
DISI
2011-2014 Microchip Technology Inc.
DS70000652F-page 273
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 24-2:
Base
Instr
#
29
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
DIV
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
Signed 16/16-bit Fractional Divide
1
18
N,Z,C,OV
None
30
DIVF
DIVF
31
DO
DO
#lit14,Expr
Do code to PC + Expr, lit14 + 1 times
2
2
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
2
2
None
Wm,Wn
32
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
33
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
35
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
36
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
37
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
38
GOTO
GOTO
Expr
Go to address
2
2
None
GOTO
Wn
Go to indirect
1
2
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
INC
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
39
40
41
INC
INC2
IOR
INC2
Ws,Wd
Wd = Ws + 2
1
1
C,DC,N,OV,Z
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
42
LAC
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
43
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
44
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd, Multiply and Accumulate
AWB
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
N,Z
MOV
f,WREG
Move f to WREG
1
1
None
45
46
47
MAC
MOV
MOVSAC
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
Move WREG to f
1
1
None
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
Prefetch and store accumulator
1
1
None
MOVSAC
DS70000652F-page 274
Acc,Wx,Wxd,Wy,Wyd,AWB
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 24-2:
Base
Instr
#
48
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
MPY
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
49
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
(Multiply Wm by Wn) to Accumulator
1
1
None
50
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,
AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
51
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
52
53
54
NEG
NOP
POP
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
f
Push f to Top-of-Stack (TOS)
1
1
None
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
1
2
None
Push Shadow Registers
1
1
None
Go into Sleep or Idle mode
1
1
WDTO,Sleep
POP.S
55
PUSH
PUSH
PUSH.S
56
PWRSAV
PWRSAV
57
RCALL
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
None
58
REPEAT
#lit1
59
RESET
RESET
Software device Reset
1
1
60
RETFIE
RETFIE
Return from interrupt
1
3 (2)
None
61
RETLW
RETLW
Return with literal in Wn
1
3 (2)
None
62
RETURN
RETURN
Return from Subroutine
1
3 (2)
None
63
RLC
RLC
f
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
64
65
RLNC
RRC
#lit10,Wn
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
2011-2014 Microchip Technology Inc.
DS70000652F-page 275
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 24-2:
Base
Instr
#
66
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
RRNC
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
67
SAC
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
68
SE
SE
Ws,Wnd
Wnd = sign-extended Ws
1
1
C,N,Z
69
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
70
71
72
73
74
75
76
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
SWAP
SUBB
f
f = f – WREG – (C)
1
1
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
C,DC,N,OV,Z
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
SWAP.b
Wn
Wn = nibble swap Wn
1
1
None
SWAP
Wn
Wn = byte swap Wn
1
1
None
None
77
TBLRDH
TBLRDH
Ws,Wd
Read Prog to Wd
1
2
78
TBLRDL
TBLRDL
Ws,Wd
Read Prog to Wd
1
2
None
79
TBLWTH
TBLWTH
Ws,Wd
Write Ws to Prog
1
2
None
80
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog
1
2
None
81
ULNK
ULNK
Unlink Frame Pointer
1
1
None
82
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
1
1
C,Z,N
83
ZE
DS70000652F-page 276
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
25.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
25.1
MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for highperformance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
•
•
•
•
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2011-2014 Microchip Technology Inc.
DS70000652F-page 277
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
25.2
MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
25.3
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
25.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.5
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command-line interface
Rich directive set
Flexible macro language
MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS70000652F-page 278
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
25.6
MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
25.7
MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2011-2014 Microchip Technology Inc.
25.8
MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
25.9
PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
25.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
DS70000652F-page 279
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
25.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
25.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70000652F-page 280
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
26.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family
electrical characteristics. Additional information will be provided in future revisions of this document as it becomes
available.
Absolute maximum ratings for the dsPIC33FJ16(GP/MC)101/102 and dsPIC33FJ32(GP/MC)101/102/104 family are
listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional
operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this
specification, is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) ................................................... -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3) ........................................ -0.3V to (VDD + 0.3V)
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................250 mA
Maximum output current sourced and sunk by any I/O pin excluding OSCO .........................................................15 mA
Maximum output current sourced and sunk by OSCO............................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2) ...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of the device maximum power dissipation (see Table 26-2).
3: See the “Pin Diagrams” section for 5V tolerant pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 281
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
26.1
DC Characteristics
TABLE 26-1:
OPERATING MIPS vs. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Characteristic
DC5
Note 1:
Temp Range
(in °C)
dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104
VBOR-3.6V(1)
-40°C to +85°C
16
VBOR-3.6V(1)
-40°C to +125°C
16
Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
TABLE 26-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices
Extended Temperature Devices
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PIO
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 26-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 18-pin PDIP
JA
50
—
°C/W
1
Package Thermal Resistance, 20-pin PDIP
JA
50
—
°C/W
1
Package Thermal Resistance, 28-pin SPDIP
JA
50
—
°C/W
1
Package Thermal Resistance, 18-pin SOIC
JA
63
—
°C/W
1
Package Thermal Resistance, 20-pin SOIC
JA
63
—
°C/W
1
Package Thermal Resistance, 28-pin SOIC
JA
55
—
°C/W
1
Package Thermal Resistance, 20-pin SSOP
JA
90
—
°C/W
1
Package Thermal Resistance, 28-pin SSOP
JA
71
—
°C/W
1
Package Thermal Resistance, 28-pin QFN (6x6 mm)
JA
37
—
°C/W
1
Package Thermal Resistance, 36-pin VTLA (5x5 mm)
JA
31.1
—
°C/W
1
Package Thermal Resistance, 44-pin TQFP
JA
45
—
°C/W
1, 2
Package Thermal Resistance, 44-pin QFN
JA
32
—
°C/W
1, 2
Package Thermal Resistance, 44-pin VTLA
JA
30
—
°C/W
1, 2
Note 1:
2:
Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.
This package is available in dsPIC33FJ32(GP/MC)104 devices only.
DS70000652F-page 282
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
—
VBOR
—
3.6
V
Conditions
Operating Voltage
DC10
Supply Voltage(3)
VDD
Voltage(2)
DC12
VDR
RAM Data Retention
1.8
—
—
V
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
—
1.75
VSS
V
DC17
SVDD
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
0.024
—
—
V/ms
Note 1:
2:
3:
0-2.4V in 0.1s
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
This is the limit to which VDD may be lowered without losing RAM data.
Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
TABLE 26-5:
ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
Industrial and Extended
Symbol
Characteristic
BOR Event on VDD Transition
High-to-Low
Min(1)
Typ
Max
Units
2.40
2.48
2.55
V
Conditions
See Note 2
BO10
VBOR
Note 1:
2:
Parameters are for design guidance only and are not tested in manufacturing.
Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
2011-2014 Microchip Technology Inc.
DS70000652F-page 283
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2) – dsPIC33FJ16(GP/MC)10X Devices
DC20d
0.7
1.7
mA
-40°C
DC20a
0.7
1.7
mA
+25°C
DC20b
1.0
1.7
mA
+85°C
DC20c
1.3
1.7
mA
+125°C
DC21d
1.9
2.6
mA
-40°C
DC21a
1.9
2.6
mA
+25°C
DC21b
1.9
2.6
mA
+85°C
DC21c
2.0
2.6
mA
+125°C
DC22d
6.5
8.5
mA
-40°C
DC22a
6.5
8.5
mA
+25°C
DC22b
6.5
8.5
mA
+85°C
DC22c
6.5
8.5
mA
+125°C
DC23d
12.2
16
mA
-40°C
DC23a
12.2
16
mA
+25°C
DC23b
12.2
16
mA
+85°C
DC23c
12.2
16
mA
+125°C
DC24d
16
21
mA
-40°C
DC24a
16
21
mA
+25°C
DC24b
16
21
mA
+85°C
16
21
mA
+125°C
DC24c
Note 1:
2:
3:
3.3V
LPRC
(32.768 kHz)(3)
3.3V
1 MIPS(3)
3.3V
4 MIPS(3)
3.3V
10 MIPS(3)
3.3V
16 MIPS
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
• CPU executing while(1) statement
These parameters are characterized, but not tested in manufacturing.
DS70000652F-page 284
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2) – dsPIC33FJ32(GP/MC)10X Devices
DC20d
1
2
mA
-40°C
DC20a
1
2
mA
+25°C
DC20b
1.1
2
mA
+85°C
DC20c
1.3
2
mA
+125°C
DC21d
1.7
3
mA
-40°C
DC21a
2.3
3
mA
+25°C
DC21b
2.3
3
mA
+85°C
DC21c
2.4
3
mA
+125°C
DC22d
7
8.5
mA
-40°C
DC22a
7
8.5
mA
+25°C
DC22b
7
8.5
mA
+85°C
DC22c
7
8.5
mA
+125°C
DC23d
13.2
17
mA
-40°C
DC23a
13.2
17
mA
+25°C
DC23b
13.2
17
mA
+85°C
DC23c
13.2
17
mA
+125°C
DC24d
17
22
mA
-40°C
DC24a
17
22
mA
+25°C
DC24b
17
22
mA
+85°C
DC24c
17
22
mA
+125°C
Note 1:
2:
3:
3.3V
LPRC
(32.768 kHz)(3)
3.3V
1 MIPS(3)
3.3V
4 MIPS(3)
3.3V
10 MIPS(3)
3.3V
16 MIPS
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
• CPU executing while(1) statement
These parameters are characterized, but not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 285
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current(2) – dsPIC33FJ16(GP/MC)10X Devices
DC40d
0.4
1.0
mA
-40°C
DC40a
0.4
1.0
mA
+25°C
DC40b
0.4
1.0
mA
+85°C
DC40c
0.5
1.0
mA
+125°C
DC41d
0.5
1.1
mA
-40°C
DC41a
0.5
1.1
mA
+25°C
DC41b
0.5
1.1
mA
+85°C
DC41c
0.8
1.1
mA
+125°C
DC42d
0.9
1.6
mA
-40°C
DC42a
0.9
1.6
mA
+25°C
DC42b
1.0
1.6
mA
+85°C
DC42c
1.2
1.6
mA
+125°C
DC43a
1.6
2.6
mA
+25°C
DC43d
1.6
2.6
mA
-40°C
DC43b
1.7
2.6
mA
+85°C
DC43c
2
2.6
mA
+125°C
DC44d
2.4
3.8
mA
-40°C
DC44a
2.4
3.8
mA
+25°C
DC44b
2.6
3.8
mA
+85°C
2.9
3.8
mA
+125°C
DC44c
Note 1:
2:
3:
3.3V
LPRC
(32.768 kHz)(3)
3.3V
1 MIPS(3)
3.3V
4 MIPS(3)
3.3V
10 MIPS(3)
3.3V
16 MIPS(3)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
Base Idle current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as
digital I/O inputs)
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
These parameters are characterized, but not tested in manufacturing.
DS70000652F-page 286
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current(2) – dsPIC33FJ32(GP/MC)10X Devices
DC40d
0.4
1.0
mA
-40°C
DC40a
0.4
1.0
mA
+25°C
DC40b
0.4
1.0
mA
+85°C
DC40c
0.5
1.0
mA
+125°C
DC41d
0.5
1.1
mA
-40°C
DC41a
0.5
1.1
mA
+25°C
DC41b
0.5
1.1
mA
+85°C
DC41c
0.8
1.1
mA
+125°C
DC42d
0.9
1.6
mA
-40°C
DC42a
0.9
1.6
mA
+25°C
DC42b
1.0
1.6
mA
+85°C
DC42c
1.2
1.6
mA
+125°C
DC43a
1.6
2.6
mA
+25°C
DC43d
1.6
2.6
mA
-40°C
DC43b
1.7
2.6
mA
+85°C
DC43c
2.0
2.6
mA
+125°C
DC44d
2.4
3.8
mA
-40°C
DC44a
2.4
3.8
mA
+25°C
DC44b
2.6
3.8
mA
+85°C
2.9
3.8
mA
+125°C
DC44c
Note 1:
2:
3:
3.3V
LPRC
(32.768 kHz)(3)
3.3V
1 MIPS(3)
3.3V
4 MIPS(3)
3.3V
10 MIPS(3)
3.3V
16 MIPS(3)
Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
Base Idle current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as
digital I/O inputs)
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeroed)
These parameters are characterized, but not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 287
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD)(2) – dsPIC33FJ16(GP/MC)10X Devices
DC60d
27
250
µA
-40°C
DC60a
32
250
µA
+25°C
DC60b
43
250
µA
+85°C
DC60c
150
500
µA
+125°C
DC61d
420
600
µA
-40°C
DC61a
420
600
µA
+25°C
DC61b
530
750
µA
+85°C
DC61c
620
900
µA
+125°C
Power-Down Current
(IPD)(2)
27
250
µA
-40°C
DC60a
32
250
µA
+25°C
DC60b
43
250
µA
+85°C
DC60c
150
500
µA
+125°C
DC61d
420
600
µA
-40°C
DC61a
420
600
µA
+25°C
DC61b
530
750
µA
+85°C
620
900
µA
+125°C
Note 1:
2:
3:
4:
5:
Base Power-Down Current(3,4)
3.3V
Watchdog Timer Current: IWDT(3,5)
3.3V
Base Power-Down Current(3,4)
3.3V
Watchdog Timer Current: IWDT(3,5)
– dsPIC33FJ32(GP/MC)10X Devices
DC60d
DC61c
3.3V
Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode, OSC1 is driven with external square wave from
rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• External Secondary Oscillator (SOSC) is disabled (i.e., SOSCO and SOSCI pins are configured as
digital I/O inputs)
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• All peripheral modules are disabled (PMDx bits are all ones)
• VREGS bit (RCON) = 1 (i.e., core regulator is set to stand-by while the device is in Sleep mode)
• On applicable devices, RTCC is disabled, plus the VREGS bit (RCON) = 1
The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
These currents are measured on the device containing the most memory in this family.
These parameters are characterized, but not tested in manufacturing.
DS70000652F-page 288
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-9:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter No.
Typical(1)
Max
Doze
Ratio(2)
Units
Conditions
Doze Current (IDOZE)(2) – dsPIC33FJ16(GP/MC)10X Devices
DC73a
13.2
17.2
1:2
mA
DC73f
4.7
DC73g
4.7
6.2
1:64
mA
6.2
1:128
mA
DC70a
13.2
DC70f
4.7
17.2
1:2
mA
6.2
1:64
mA
DC70g
4.7
6.2
1:128
mA
DC71a
13.2
17.2
1:2
mA
DC71f
4.7
6.2
1:64
mA
DC71g
4.7
6.2
1:128
mA
DC72a
13.2
17.2
1:2
mA
DC72f
4.7
6.2
1:64
mA
DC72g
4.7
6.2
1:128
mA
-40°C
3.3V
16 MIPS
+25°C
3.3V
16 MIPS
+85°C
3.3V
16 MIPS
+125°C
3.3V
16 MIPS
-40°C
3.3V
16 MIPS
+25°C
3.3V
16 MIPS
+85°C
3.3V
16 MIPS
+125°C
3.3V
16 MIPS
Doze Current (IDOZE)(2) – dsPIC33FJ32(GP/MC)10X Devices
DC73a
13.2
17.2
1:2
mA
DC73f
4.7
6.2
1:64
mA
DC73g
4.7
6.2
1:128
mA
DC70a
13.2
17.2
1:2
mA
DC70f
4.7
6.2
1:64
mA
DC70g
4.7
6.2
1:128
mA
DC71a
13.2
17.2
1:2
mA
DC71f
4.7
6.2
1:64
mA
DC71g
4.7
6.2
1:128
mA
DC72a
13.2
17.2
1:2
mA
DC72f
4.7
6.2
1:64
mA
DC72g
4.7
6.2
1:128
mA
Note 1:
2:
Data in the Typical column is at 3.3V, +25°C unless otherwise stated.
IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode, OSC1 is driven with external square wave from rail-to-rail
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all
zeros)
• CPU executing while(1) statement
2011-2014 Microchip Technology Inc.
DS70000652F-page 289
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage
DI10
I/O Pins
VSS
—
0.2 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI18
I/O Pins with SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
DI19
I/O Pins with SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
VIH
Input High Voltage
DI20
I/O Pins Not 5V Tolerant(4)
I/O Pins 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI28
SDAx, SCLx
0.7 VDD
—
5.5
V
SMBus disabled
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled
50
250
450
A
VDD = 3.3V, VPIN = VSS
ICNPU
CNx Pull-up Current
DI30
IIL
Input Leakage
Current(2,3)
DI50
I/O Pins 5V Tolerant(4)
—
—
±2
A
VSS VPIN VDD,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(4)
—
—
±1
A
VSS VPIN VDD,
Pin at high-impedance,
-40°C TA +85°C
DI51a
I/O Pins Not 5V Tolerant(4)
—
—
±2
A
Shared with external
reference pins,
-40°C TA +85°C
DI51b
I/O Pins Not 5V Tolerant(4)
—
—
±3.5
A
VSS VPIN VDD,
Pin at high-impedance,
-40°C TA +125°C
DI51c
I/O Pins Not 5V Tolerant(4)
—
—
±8
A
Analog pins shared with
external reference pins,
-40°C TA +125°C
DI55
MCLR
—
—
±2
A
VSS VPIN VDD
DI56
OSC1
—
—
±2
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS70000652F-page 290
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
IICT
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Typ(1)
Max
Units
Conditions
0
-5(5,8)
—
mA
All pins except VDD, VSS,
AVDD, AVSS, MCLR,
VCAP, SOSCI, SOSCO
and RB14
0
—
+5(6,7,8)
mA
All pins except VDD,
VSS, AVDD, AVSS,
MCLR, VCAP, SOSCI,
SOSCO, RB14 and
digital 5V tolerant
designated pins
-20(9)
—
+20(9)
mA
Absolute instantaneous
sum of all ± input
injection currents from
all I/O pins
( | IICL + | IICH | ) IICT
Input High Injection Current
DI60b
DI60c
Min
Input Low Injection Current
DI60a
IICH
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Total Input Injection Current
(sum of all I/O and control
pins)
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See the “Pin Diagrams” section for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins, VIH source > (VDD + 0.3), 5V tolerant pins, VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins, not excluded under IICL or IICH conditions, are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2011-2014 Microchip Technology Inc.
DS70000652F-page 291
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
DO10
DO20
VOL
VOH
Characteristic
Min
Typ(1)
Max
Units
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – All Pins
excluding OSCO
—
—
0.4
V
IOL 6 mA, VDD = 3.3V,
See Note 1
Output Low Voltage
I/O Pins:
8x Sink Driver Pins – OSCO
—
—
0.4
V
IOL 10 mA, VDD = 3.3V,
See Note 1
Output High Voltage
I/O Pins:
4x Source Driver Pins – All
Pins excluding OSCO
2.4
—
—
V
IOL -6 mA, VDD = 3.3V,
See Note 1
Output High Voltage
I/O Pins:
8x Source Driver Pins – OSCO
2.4
—
—
V
IOL -10 mA, VDD = 3.3V,
See Note 1
1.5
—
—
2.0
—
—
3.0
—
—
IOH -3 mA, VDD = 3.3V,
See Note 1
1.5
—
—
IOH -16 mA, VDD = 3.3V,
See Note 1
2.0
—
—
3.0
—
—
Output High Voltage
I/O Pins:
4x Source Driver Pins – All
Pins excluding OSCO
DO20A VOH1
Note 1:
Output High Voltage
I/O Pins:
8x Source Driver Pins – OSCO
Conditions
IOH -12 mA, VDD = 3.3V,
See Note 1
V
V
IOH -11 mA, VDD = 3.3V,
See Note 1
IOH -12 mA, VDD = 3.3V,
See Note 1
IOH -4 mA, VDD = 3.3V,
See Note 1
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS70000652F-page 292
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic(3)
Min
Typ(1)
Max
Units
10,000
—
—
E/W
Conditions
Program Flash Memory
D130a
EP
Cell Endurance
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132b
VPEW
VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D134
TRETD
Characteristic Retention
20
—
—
Year
D135
IDDP
Supply Current during
Programming
—
10
—
mA
D137a
TPE
Page Erase Time
20.1
—
26.5
ms
TPE = 168517 FRC cycles,
TA = +85°C, See Note 2
D137b
TPE
Page Erase Time
19.5
—
27.3
ms
TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
D138a
TWW
Word Write Cycle Time
47.4
—
49.3
µs
TWW = 355 FRC cycles,
TA = +85°C, See Note 2
D138b
TWW
Word Write Cycle Time
47.4
—
49.3
µs
TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1:
2:
3:
-40C to +125C
Provided no other specifications
are violated
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Other conditions: FRC = 7.37 MHz, TUN = b'011111 (for Min), TUN = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 26-18) and the value of the FRC Oscillator
Tuning register (see Register 8-3). For complete details on calculating the Minimum and Maximum time,
see Section 5.3 “Programming Operations”.
These parameters are ensured by design, but are not characterized or tested in manufacturing.
TABLE 26-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
No.
—
Note 1:
Symbol
CEFC
Characteristics
External Filter Capacitor
Value(1)
Min
Typ
Max
Units
4.7
10
—
µF
Comments
Capacitor must be low
series resistance
(< 5 ohms)
Typical VCAP voltage = 2.5V when VDD VDDMIN.
2011-2014 Microchip Technology Inc.
DS70000652F-page 293
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
26.2
AC Characteristics and Timing
Parameters
This section defines dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104 family AC
characteristics and timing parameters.
TABLE 26-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 26.1 “DC
Characteristics”.
AC CHARACTERISTICS
FIGURE 26-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 26-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
15
pF
In MS and HS modes when external
clock is used to drive OSC1
COSC2
OSC2/SOSC2 Pin
—
—
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
DO50
DS70000652F-page 294
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS31
OS31
OS25
CLKO
OS41
OS40
TABLE 26-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
Symb
FIN
OS20
TOSC
Min
Typ(1)
Max
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
32
MHz
EC
Oscillator Crystal Frequency
3.0
10
31
—
—
—
10
32
33
MHz
MHz
kHz
MS
HS
SOSC
31.25
—
DC
ns
Characteristic
TOSC = 1/FOSC
Time(2,4)
Conditions
OS25
TCY
Instruction Cycle
62.5
—
DC
ns
OS30
TosL,
TosH
External Clock in (OSC1)(5)
High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)(5)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3,5)
—
6
10
ns
OS41
TckF
CLKO Fall Time(3,5)
—
6
10
ns
OS42
GM
External Oscillator
Transconductance(4)
14
16
18
mA/V
Note 1:
2:
3:
4:
5:
VDD = 3.3V,
TA = +25°C
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
These parameters are characterized by similarity, but are tested in manufacturing at FIN = 32 MHz only.
These parameters are characterized by similarity, but are not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 295
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-17: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled Oscillator
(VCO) Input Frequency Range(2)
3.0
—
8
MHz ECPLL and MSPLL modes
OS51
FSYS
On-Chip VCO System
Frequency(3)
12
—
32
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)(3)
—
—
2
mS
-2
1
+2
%
OS53
DCLK
Note 1:
2:
3:
CLKO Stability (Jitter)
(3)
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only.
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. The effective jitter for individual time bases, or communication clocks used by the user application, are derived from dividing the CLKO stability specification by the
square root of “N” (where “N” is equal to FOSC, divided by the peripheral data rate clock). For example, if
FOSC = 32 MHz and the SPI bit rate is 5 MHz, the effective jitter of the SPI clock is equal to:
2%
D CLK
-------------- = ---------- = 0.79%
2.53
32
-----5
TABLE 26-18: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
+2
%
Conditions
Internal FRC Accuracy @ 7.37 MHz(1)
-40°C TA -10°C
F20a
FRC
-2
±0.25
F20b
FRC
-1
±0.25
+1
%
-10°C TA +85°C
VDD 3.0-3.6V
F20c
FRC
-5
±0.25
+5
%
+85°C TA +125°C
VDD 3.0-3.6V
Note 1:
VDD 3.0-3.6V
Frequency is calibrated at +25°C and 3.3V. TUNx bits may be used to compensate for temperature drift.
TABLE 26-19: INTERNAL LOW-POWER RC (LPRC) ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
Conditions
±10
+20
%
-40°C TA -10°C
LPRC @ 32.768 kHz(1,2)
F21a
LPRC
-30
F21b
LPRC
-20
±10
+30
%
-10°C TA +85°C
VDD 3.0-3.6V
F21c
LPRC
-35
±10
+35
%
+85°C TA +125°C
VDD 3.0-3.6V
Note 1:
2:
Change of LPRC frequency as VDD changes.
LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 23.4 “Watchdog
Timer (WDT)” for more information.
DS70000652F-page 296
VDD 3.0-3.6V
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(2)
Min
Typ(1)
Max
Units
—
10
25
ns
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
10
25
ns
DI35
TINP
INTx Pin High or Low Time (input)
25
—
—
ns
TRBP
CNx High or Low Time (input)
2
—
—
TCY
DI40
Note 1:
2:
Port Output Rise Time
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
These parameters are characterized, but are not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 297
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
VDD
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symb
No.
Min
Typ(2)
Max
Units
2
—
—
s
Characteristic(1)
Conditions
SY10
TMCL
SY11
TPWRT Power-up Timer Period
—
64
—
ms
SY12
TPOR
Power-on Reset Delay
3
10
30
s
SY13
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
1.2
s
SY20
TWDT1 Watchdog Timer Time-out
Period
—
—
—
ms
See Section 23.4 “Watchdog
Timer (WDT)” and LPRC
Parameter F21a (Table 26-19).
SY30
TOST
—
1024 * TOSC
—
—
TOSC = OSC1 period
SY35
TFSCM Fail-Safe Clock Monitor Delay
—
500
900
s
Note 1:
2:
MCLR Pulse Width (low)
Oscillator Start-up Time
These parameters are characterized but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS70000652F-page 298
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-5:
TIMER1/2/3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
Symbol
TTXH
Characteristic(2)
T1CK High
Time
Min
Typ
Max
Units
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Asynchronous
35
—
—
ns
Synchronous
mode
Greater of:
20 ns or
(TCY + 20)/N
—
—
ns
TA11
TTXL
T1CK Low
Time
TA15
TTXP
T1CK Input
Period
OS60
Ft1
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
the TCS (T1CON) bit)
TA20
0.75 TCY + 40
TCKEXTMRL Delay from External T1CK
Clock Edge to Timer Increment
Note 1:
2:
Asynchronous
10
—
—
ns
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
DC
—
50
kHz
—
1.75 TCY + 40
ns
Conditions
Must also meet
Parameter TA15,
N = prescale value
(1, 8, 64, 256)
Must also meet
Parameter TA15,
N = prescale value
(1, 8, 64, 256)
N = prescale value
(1, 8, 64, 256)
Timer1 is a Type A.
These parameters are characterized by similarity, but are not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 299
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-23: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic(1)
Min
Typ
Max
Units
Conditions
TB10
TtxH
TxCK High Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = prescale value
(1, 8, 64, 256)
TB11
TtxL
TxCK Low
Time
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = prescale value
(1, 8, 64, 256)
TB15
TtxP
TxCK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = prescale value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK 0.75 TCY + 40
Clock Edge to Timer
Increment
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized, but are not tested in manufacturing.
TABLE 26-24: TIMER3/5 EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic(1)
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High Synchronous
Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TtxL
TxCK Low Synchronous
Time
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TtxP
TxCK Input Synchronous,
Period
with Prescaler
2 TCY + 40
—
—
ns
N = prescale value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized, but are not tested in manufacturing.
DS70000652F-page 300
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-6:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-25: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IC10
TccL
Characteristic(1)
ICx Input Low Time
No Prescaler
With Prescaler
IC11
TccH
ICx Input High Time No Prescaler
With Prescaler
IC15
Note 1:
TccP
ICx Input Period
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(TCY + 40)/N
—
ns
Conditions
N = prescale value
(1, 4, 16)
These parameters are characterized by similarity, but are not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 301
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-7:
OUTPUT COMPARE x (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-26: OUTPUT COMPARE x (OCx) MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 26-8:
OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
Active
Tri-State
TABLE 26-27: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic(1)
Min
Typ
Max
Units
OC15
TFD
Fault Input to PWMx I/O
Change
—
—
TCY + 20 ns
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20 ns
—
—
ns
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing.
DS70000652F-page 302
Conditions
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-9:
MOTOR CONTROL PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA1
MP20
PWMx
Note 1:
See Note 1
For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register.
FIGURE 26-10:
MOTOR CONTROL PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-28: MOTOR CONTROL PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
MP10
TFPWM
PWM Output Fall Time
—
—
—
ns
See Parameter DO32
MP11
TRPWM
PWM Output Rise Time
—
—
—
ns
See Parameter DO31
MP20
TFD
Fault Input to PWM
I/O Change
—
—
50
ns
MP30
TFH
Minimum Pulse Width
50
—
—
ns
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing.
2011-2014 Microchip Technology Inc.
DS70000652F-page 303
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 26-30
—
—
0,1
0,1
0,1
10 MHz
—
Table 26-31
—
1
0,1
1
10 MHz
—
Table 26-32
—
0
0,1
1
15 MHz
—
—
Table 26-33
1
0
0
11 MHz
—
—
Table 26-34
1
1
0
15 MHz
—
—
Table 26-35
0
1
0
11 MHz
—
—
Table 26-36
0
0
0
FIGURE 26-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 304
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
LSb
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 305
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP40
SDIx
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
SP20
TscP
TscF
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
10
—
MHz
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
DS70000652F-page 306
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP30, SP31
SDIx
MSb In
LSb
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40°C to +125°C,
see Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
TscP
Maximum SCKx Frequency
—
—
10
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
2011-2014 Microchip Technology Inc.
DS70000652F-page 307
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-15:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 308
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 309
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-16:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 310
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 311
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-17:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 312
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 313
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ16(GP/MC)10X
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 314
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ16(GP/MC)10X
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 315
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-37: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 26-30
—
—
0,1
0,1
0,1
9 MHz
—
Table 26-31
—
1
0,1
1
9 MHz
—
Table 26-32
—
0
0,1
1
15 MHz
—
—
Table 26-33
1
0
0
11 Mhz
—
—
Table 26-34
1
1
0
15 MHz
—
—
Table 26-35
0
1
0
11 MHz
—
—
Table 26-36
0
0
0
FIGURE 26-19:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
SP30, SP31
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 316
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-20:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
LSb
SP30, SP31
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-38: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 317
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-21:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP35
SP20
SP21
SCKx
(CKP = 1)
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP40
SDIx
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-39: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2sc,
TdoV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
DS70000652F-page 318
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-22:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP30, SP31
SDIx
MSb In
LSb
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-40: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40°C to +125°C,
see Note 3
SP10
TscP
Maximum SCKx Frequency
—
—
9
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data
Input to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 319
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-23:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 320
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-41: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 321
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-24:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 322
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-42: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 323
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-25:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SDOX
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 324
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-43: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—w
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the Master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 325
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-26:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS FOR dsPIC33FJ32(GP/MC)10X
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 326
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-44: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS FOR dsPIC33FJ32(GP/MC)10X
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the Master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2011-2014 Microchip Technology Inc.
DS70000652F-page 327
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-27:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM34
IM31
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 26-1 for load conditions.
FIGURE 26-28:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 26-1 for load conditions.
DS70000652F-page 328
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-45: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note
Characteristic
Min(1)
Max
Units
Conditions
Clock Low Time 100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
(2)
TCY/2 (BRG + 1)
—
s
1 MHz mode
THI:SCL Clock High Time 100 kHz mode
TCY/2 (BRG + 1)
—
s
400 kHz mode
TCY/2 (BRG + 1)
—
s
TCY/2 (BRG + 1)
—
s
1 MHz mode(2)
TF:SCL
SDAx and SCLx 100 kHz mode
—
300
ns
CB is specified to be
Fall Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
—
100
ns
1 MHz mode
TR:SCL
SDAx and SCLx 100 kHz mode
—
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(2)
1 MHz mode
40
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(2)
0.2
—
s
TSU:STA Start Condition 100 kHz mode
TCY/2 (BRG + 1)
—
s
Only relevant for
Setup Time
Repeated Start
400 kHz mode
TCY/2 (BRG + 1)
—
s
condition
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
THD:STA Start Condition 100 kHz mode
TCY/2 (BRG + 1)
—
s
After this period the first
Hold Time
clock pulse is generated
400 kHz mode
TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
TSU:STO Stop Condition 100 kHz mode
TCY/2 (BRG + 1)
—
s
Setup Time
400 kHz mode
TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
THD:STO Stop Condition 100 kHz mode
TCY/2 (BRG + 1)
—
ns
Hold Time
400 kHz mode
TCY/2 (BRG + 1)
—
ns
1 MHz mode(2)
TCY/2 (BRG + 1)
—
ns
100 kHz mode
—
3500
ns
TAA:SCL Output Valid
from Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
4.7
—
s
Time the bus must be
TBF:SDA Bus Free Time 100 kHz mode
free
before a new
400 kHz mode
1.3
—
s
transmission
can start
(2)
1 MHz mode
0.5
—
s
Bus Capacitive Loading
—
400
pF
CB
TPGD
Pulse Gobbler Delay
65
390
ns
See Note 3
2
1: BRG is the value of the I C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit (I2C™)” (DS70195) in
the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip web site for the latest “dsPIC33/
PIC24 Family Reference Manual” sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
TLO:SCL
2011-2014 Microchip Technology Inc.
DS70000652F-page 329
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
FIGURE 26-29:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 26-30:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
DS70000652F-page 330
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-46: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
IS10
IS11
IS20
IS21
IS25
Characteristic
TLO:SCL Clock Low Time
THI:SCL
TF:SCL
TR:SCL
Min
Max
Units
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
Clock High Time 100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
TSU:DAT Data Input
Setup Time
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
mode(1)
1 MHz
IS26
THD:DAT Data Input
Hold Time
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
0
0.3
s
4.7
—
s
1 MHz
IS30
IS31
IS33
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
IS40
IS45
IS50
Note 1:
THD:STO Stop Condition
Hold Time
TAA:SCL
Output Valid
from Clock
TBF:SDA Bus Free Time
CB
mode(1)
100 kHz mode
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
0.6
—
s
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
250
100 kHz mode
0
3500
ns
400 kHz mode
0
1000
ns
1 MHz mode(1)
0
350
ns
1 MHz
IS34
Conditions
mode(1)
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
CB is specified to be from
10 to 400 pF
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2011-2014 Microchip Technology Inc.
DS70000652F-page 331
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-47: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V(6)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply(2,4)
Greater of:
VDD – 0.3
or 2.9
—
Lesser of:
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply(2,5)
VSS – 0.3
—
VSS + 0.3
V
AD09
IAD
Operating Current
—
7.0
9.0
mA
See Note 1
Analog Input
AD12
VINH
Input Voltage Range
VINH(2)
VINL
—
AVDD
V
This voltage reflects S&H
Channels 0, 1, 2 and 3
(CH0-CH3), positive input
AD13
VINL
Input Voltage Range
VINL(2)
AVSS
—
AVSS + 1V
V
This voltage reflects S&H
Channels 0, 1, 2 and 3
(CH0-CH3), negative input
AD17
RIN
Recommended
Impedance of Analog
Voltage Source(3)
—
—
200
Note 1:
2:
3:
4:
5:
6:
These parameters are not characterized or tested in manufacturing.
These parameters are characterized, but are not tested in manufacturing.
These parameters are assured by design, but are not characterized or tested in manufacturing.
This pin may not be available on all devices; in which case, this pin will be connected to VDD internally.
See the “Pin Diagrams” section for availability.
This pin may not be available on all devices; in which case, this pin will be connected to VSS internally. See
the “Pin Diagrams” section for availability.
Overall functional device operation at VBOR < VDD < VDDMIN is ensured but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
DS70000652F-page 332
2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
TABLE 26-48: 10-BIT ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V(4)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
10-Bit ADC Accuracy – Measurements with AVDD/AVSS(3)
AD20b
Nr
Resolution
10 Data Bits
bits
AD21b
INL
Integral Nonlinearity
-1
—
+1
LSb
VINL = AVSS = 0V, AVDD = 3.6V
AD22b
DNL
Differential Nonlinearity
>-1
—
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2011-2014 Microchip Technology Inc.
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
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