DSPIC33FJ16GP304-I/PT

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 16-Bit Digital Signal Controllers with Advanced Analog Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40°C to +150°C, DC to 20 MIPS • 3.0V to 3.6V, -40°C to +125°C, DC to 40 MIPS • Three 16-bit timers/counters; can pair up two to make one 32-bit • Two OC modules, configurable as timers/counters • Four IC modules • Peripheral Pin Select (PPS) to allow function remap Core: 16-Bit dsPIC33F CPU • • • • Code-efficient (C and Assembly) architecture Two 40-bit wide accumulators Single-cycle (MAC/MPY) with dual data fetch Single-cycle, mixed-sign MUL plus hardware divide Clock Management • • • • • ±2% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Fast wake-up and start-up Communication Interfaces • One UART module (10 Mbps) - With support for LIN/J2602 protocols and IrDA® • One 4-wire SPI module (15 Mbps) • One I2C™ module (up to 1 Mbaud) with SMBus support • PPS to allow function remap Input/Output • Low-power management modes (Sleep, Idle, Doze) • Integrated Power-on Reset and Brown-out Reset • 1.35 mA/MHz dynamic current (typical) • 55 μA IPD current (typical) • Sink/Source up to 10 mA (pin-specific) for standard VOH/VOL, up to 16 mA (pin-specific) for non-standard VOH1 • 5V tolerant pins • Selectable open-drain, pull-ups, and pull-downs • Up to 5 mA overvoltage clamp current • External interrupts on all I/O pins Advanced Analog Features Qualification and Class B Support • ADC module: - Configurable as 10-bit, 1.1 Msps with four S/H (Sample-and-Hold) or 12-bit, 500 ksps with one S/H - Ten analog inputs on 28-pin devices and up to 13 analog inputs on 44-pin devices • Flexible and independent ADC trigger sources • AEC-Q100 REVG (Grade 1 -40°C to +125°C) • AEC-Q100 REVG (Grade 0 -40°C to +150°C) • Class B Safety Library, IEC 60730 Power Management © 2007-2011 Microchip Technology Inc. Debugger Development Support • • • • In-circuit and in-application programming Two program and two complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Trace and run-time watch DS70290J-page 1 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. Device Program Flash Memory (Kbytes) RAM (Kbytes) Remappable Pins 16-Bit Timer Input Capture Output Compare Std. PWM UART External Interrupts(2) SPI I2C™ I/O Pins (Max) dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CONTROLLER FAMILIES Pins TABLE 1: dsPIC33FJ32GP202 28 32 2 16 3(1) 4 2 1 3 1 1 ADC, 10 ch 1 21 SPDIP SOIC SSOP QFN-S dsPIC33FJ32GP204 44 32 2 26 3(1) 4 2 1 3 1 1 ADC, 13 ch 1 35 QFN TQFP dsPIC33FJ16GP304 44 16 2 26 3(1) 4 2 1 3 1 1 ADC, 13 ch 1 35 QFN TQFP Note 1: 2: Packages 10-Bit/12-Bit ADC Remappable Peripherals Only two out of three timers are remappable. Only two out of three interrupts are remappable. DS70290J-page 2 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Pin Diagrams 28-Pin SPDIP, SOIC, SSOP = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ32GP202 MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4(1)/CN1/RB4 SOSCO/T1CK/CN0/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/RB5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN9/RP15(1)/CN11/RB15 AN10/RP14(1)/CN12/RB14 AN11/RP13(1)/CN13/RB13 AN12/RP12(1)/CN14/RB12 PGEC2/TMS/RP11(1)/CN15/RB11 PGED2/TDI/RP10(1)/CN16/RB10 VCAP VSS TDO/SDA1/RP9(1)/CN21/RB9 TCK/SCL1/RP8(1)/CN22/RB8 INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6(1)/CN24/RB6 28-Pin QFN-S(2) AN10/RP14(1)/CN12/RB14 AVDD AVSS AN9/RP15(1)/CN11/RB15 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR = Pins are up to 5V tolerant 28 27 26 25 24 23 22 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 1 21 2 20 AN12/RP12(1)/CN14/RB12 AN4/RP2(1)/CN6/RB2 3 19 PGEC2/TMS/RP11(1)(1)/CN15/RB11 AN5/RP3(1)/CN7/RB3 VSS 4 dsPIC33FJ32GP202 18 5 17 VCAP OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 6 16 Vss 7 15 TDO/SDA1/RP9(1)/CN21/RB9 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7(1(1))/CN23/RB7 TCK/SCL1/RP8(1)/CN22/RB8 PGED3/ASDA1/RP5(1)/CN27/RB5 SOSCI/RP4/CN1/RB4 2: PGED2/TDI/RP10/CN16/RB10 9 10 11 12 13 14 SOSCO/T1CK/CN0/RA4 VDD 8 Note 1: AN11/RP13(1)/CN13/RB13 The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2011 Microchip Technology Inc. DS70290J-page 3 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Pin Diagrams (Continued) 44-Pin QFN(2) PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/RB15 AN10/RP14(1)/CN12/RB14 TCK/RA7 TMS/RA10 = Pins are up to 5V tolerant 23 11 AN11/RP13(1)/CN13/RB13 24 10 AN12/RP12(1)/CN14/RB12 AN6/RP16(1)/CN8/RC0 25 9 AN7/RP17(1)/CN9/RC1 26 8 PGED2/RP10(1)/CN16/RB10 AN8/RP18(1)/CN10/RC2 27 7 VDD VSS 28 VCAP VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 30 31 3 RP25(1)/CN19/RC9 RP24(1)/CN20/RC8 RP23(1)/CN17/RC7 TDO/RA8 SOSCI/RP4(1)/CN1/RB4 32 2 RP22(1)/CN18/RC6 1 SDA1/RP9(1)/CN21/RB9 6 5 4 PGEC2/RP11(1)/CN15/RB11 SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19(1)/CN28/RC3 RP20(1)/CN25/RC4 RP21(1)/CN26/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/RB5 PGEC3/ASCL1/RP6(1)/CN24/RB6 INT0/RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 33 dsPIC33FJ32GP204 dsPIC33FJ16GP304 34 35 36 37 38 39 40 41 42 43 44 29 22 21 20 19 18 17 16 15 14 13 12 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 Note 1: 2: DS70290J-page 4 The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to Vss externally. © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP 11 10 9 8 7 6 5 4 3 2 1 AN11/RP13(1)/CN13/RB13 AN12/RP12(1)/CN14/RB12 PGEC2/RP11(1)/CN15/RB11 PGED2/RP10(1)/CN16/RB10 VCAP VSS RP25(1)/CN19/RC9 RP24(1)/CN20/RC8 RP23(1)/CN17/RC7 RP22/CN18/RC6 SDA1(1)/RP9(1)/CN21/RB9 38 39 40 41 42 43 44 dsPIC33FJ32GP204 dsPIC33FJ16GP304 34 35 36 37 23 24 25 26 27 28 29 30 31 32 33 SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19(1)/CN28/RC3 RP20(1)/CN25/RC4 RP21(1)/CN26/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/RB5 PGEC3/ASCL1/RP6(1)/CN24/RB6 INT0/ RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/RP18(1)/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4(1)/CN1/RB4 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/RB15 AN10/RP14(1)/CN12/RB14 TCK/RA7 TMS/RA10 = Pins are up to 5V tolerant Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. © 2007-2011 Microchip Technology Inc. DS70290J-page 5 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 13 3.0 CPU............................................................................................................................................................................................ 17 4.0 Memory Organization ................................................................................................................................................................. 29 5.0 Flash Program Memory .............................................................................................................................................................. 55 6.0 Resets ....................................................................................................................................................................................... 61 7.0 Interrupt Controller ..................................................................................................................................................................... 71 8.0 Oscillator Configuration .............................................................................................................................................................. 97 9.0 Power-Saving Features............................................................................................................................................................ 109 10.0 I/O Ports ................................................................................................................................................................................... 115 11.0 Timer1 ...................................................................................................................................................................................... 137 12.0 Timer2/3 Feature...................................................................................................................................................................... 141 13.0 Input Capture............................................................................................................................................................................ 147 14.0 Output Compare....................................................................................................................................................................... 151 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 155 16.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 161 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 169 18.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 175 19.0 Special Features ...................................................................................................................................................................... 189 20.0 Instruction Set Summary .......................................................................................................................................................... 197 21.0 Development Support............................................................................................................................................................... 205 22.0 Electrical Characteristics .......................................................................................................................................................... 209 23.0 High Temperature Electrical Characteristics ............................................................................................................................ 253 24.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 263 25.0 Packaging Information.............................................................................................................................................................. 267 Appendix A: Revision History............................................................................................................................................................. 281 Index ................................................................................................................................................................................................. 291 The Microchip Web Site ..................................................................................................................................................................... 295 Customer Change Notification Service .............................................................................................................................................. 295 Customer Support .............................................................................................................................................................................. 295 Reader Response .............................................................................................................................................................................. 296 Product Identification System............................................................................................................................................................. 297 DS70290J-page 6 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007-2011 Microchip Technology Inc. DS70290J-page 7 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ32GP204 product page of the Microchip web site (www.microchip.com). In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • • • • • • • • • • • • • • • • • • • DS70290J-page 8 Section 1. “Introduction” (DS70197) Section 2. “CPU” (DS70204) Section 3. “Data Memory” (DS70202) Section 4. “Program Memory” (DS70202) Section 5. “Flash Programming” (DS70191) Section 6. “Interrupts (DS70184) Section 7. “Oscillator” (DS70186) Section 8. “Reset” (DS70192) Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) Section 10. “I/O Ports” (DS70193) Section 11. “Timers” (DS70205) Section 12. “Input Capture” (DS70198) Section 13. “Output Compare” (DS70209) Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) Section 17. “UART” (DS70188) Section 18. “Serial Peripheral Interface (SPI)” (DS70206) Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) Section 23. “CodeGuard™ Security” (DS70199) Section 25. “Device Configuration” (DS70194) © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This document contains device-specific information for the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Digital Signal Controller (DSC) devices. The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007-2011 Microchip Technology Inc. DS70290H-page 9 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 1-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 PORTB 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 16 16 PORTC 16 Address Generator Units Address Latch Remappable Pins Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg Control Signals to Various Blocks Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator VCAP 16 DSP Engine Power-up Timer Divide Support 16 x 16 W Register Array 16 Oscillator Start-up Timer Power-on Reset 16-bit ALU Watchdog Timer 16 Brown-out Reset VDD, VSS Timers 1-3 IC1,2,7,8 Note: Literal Data Instruction Decode and Control OSC2/CLKO OSC1/CLKI 16 16 MCLR UART1 ADC1 OC/ PWM1-2 CNx I2C1 SPI1 Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features present on each device. DS70290H-page 10 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Description AN0-AN12 I Analog No Analog input channels. CLKI CLKO I O ST/CMOS — No No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No OSC2 I/O — No Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI SOSCO I O ST/CMOS — No No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. CN0-CN30 I ST No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 IC7-IC8 I ST Yes Yes Capture inputs 1/2. Capture inputs 7/8. OCFA OC1-OC2 I O ST — Yes Yes Compare Fault A input (for Compare Channels 1 and 2). Compare outputs 1 through 2. INT0 INT1 INT2 I I I ST ST ST No Yes Yes External interrupt 0. External interrupt 1. External interrupt 2. RA0-RA4 RA7-RA10 I/O ST No No PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC9 I/O ST No PORTC is a bidirectional I/O port. T1CK T2CK T3CK I I I ST ST ST No Yes Yes Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. U1CTS U1RTS U1RX U1TX I O I O ST — ST — Yes Yes Yes Yes UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCL1 SDA1 ASCL1 ASDA1 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. TMS TCK TDI TDO I I I O ST ST ST — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST No No No No No No Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select © 2007-2011 Microchip Technology Inc. Analog = Analog input; O = Output; P = Power I = Input DS70290H-page 11 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. Pin Name Description VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. AVDD P P No Positive supply for analog modules. This pin must be connected at all times. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. Avss P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select DS70290H-page 12 Analog = Analog input; O = Output; P = Power I = Input © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (even if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP (see Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2007-2011 Microchip Technology Inc. DS70290J-page 13 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD • Device Reset • Device programming and debugging C dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1Ω and the inductor capacity greater than 10 mA. Where: CNV ------------f = F 2 1 f = ----------------------( 2π LC ) Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: MCLR 0.1 µF Ceramic The placement of this capacitor should be close to the VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 19.2 “On-Chip Voltage Regulator” for details. (i.e., ADC conversion rate/2) During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that capacitor C is isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: VDD 2 1 L = ⎛⎝ ---------------------⎞⎠ ( 2πf C ) 2.2.1 R(1) TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. 2.3 EXAMPLE OF MCLR PIN CONNECTIONS CPU Logic Filter Capacitor Connection (VCAP) JP R1(2) MCLR dsPIC33F C Note 1: R ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 22.0 “Electrical Characteristics” for additional information. DS70290J-page 14 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 2.5 ICSP Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™ in-circuit emulator. For more information on MPLAB ICD 3 or MPLAB REAL ICE™ in-circuit emulator connection requirements, refer to the following documents that are available on the Microchip web site. • “Using MPLAB® ICD 3” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™” (poster) DS51749 © 2007-2011 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring 14 15 Guard Trace Secondary Oscillator 16 17 18 19 20 DS70290J-page 15 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤8 MHz for start-up with PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration Word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE in-circuit emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 3 or MPLAB REAL ICE in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 3 or MPLAB REAL ICE in-circuit emulator is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor between VSS and the unused pins. DS70290J-page 16 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.0 CPU 3.1 Data Addressing Overview Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site: (www.microchip.com). The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 instruction set has two classes of instructions: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. 3.2 DSP Engine Overview The DSP engine features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space. A block diagram of the CPU is shown in Figure 3-1. The programmer’s model for the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 is shown in Figure 3-2. © 2007-2011 Microchip Technology Inc. DS70290J-page 17 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.3 Special MCU Features The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0). FIGURE 3-1: A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 8 16 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 16 16 16 Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 24 Instruction Reg 16 Literal Data Instruction Decode and Control 16 Control Signals to Various Blocks 16 DSP Engine Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70290J-page 18 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 3-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.S Shadow W1 DO Shadow W2 W3 Legend W4 DSP Operand Registers W5 W6 W7 Working Registers W8 W9 DSP Address Registers W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer Stack Pointer Limit Register SPLIM AD39 AD15 AD31 AD0 AccA DSP Accumulators AccB PC22 PC0 Program Counter 0 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG Program Space Visibility Page Address 15 0 RCOUNT REPEAT Loop Counter 15 0 DCOUNT DO Loop Counter 22 0 DOSTART DO Loop Start Address DOEND DO Loop End Address 22 15 0 Core Configuration Register CORCON OA OB SA SB OAB SAB DA SRH © 2007-2011 Microchip Technology Inc. DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register SRL DS70290J-page 19 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.4 CPU Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 3.4.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530331 KEY RESOURCES • • • • • • Section 2. “CPU” (DS70204) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools DS70290J-page 20 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.5 CPU Control Registers REGISTER 3-1: R-0 OA SR: CPU STATUS REGISTER R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OB SA(1) SB(1) OAB SAB DA DC bit 15 bit 8 R/W-0(2) R/W-0(3) R/W-0(3) IPL(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 OA: Accumulator A Overflow Status bit 1 = Accumulator A overflowed 0 = Accumulator A has not overflowed bit 14 OB: Accumulator B Overflow Status bit 1 = Accumulator B overflowed 0 = Accumulator B has not overflowed bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1) 1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not saturated bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1) 1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not saturated bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit 1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit 1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated Note: This bit can be read or cleared (not set). Clearing this bit will clear SA and SB. bit 9 DA: DO Loop Active bit 1 = DO loop in progress 0 = DO loop not in progress bit 8 DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred Note 1: 2: 3: This bit can be read or cleared (not set). The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. The IPL Status bits are read only when NSTDIS = 1 (INTCON1). © 2007-2011 Microchip Technology Inc. DS70290J-page 21 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 1 Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: 3: This bit can be read or cleared (not set). The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. The IPL Status bits are read only when NSTDIS = 1 (INTCON1). DS70290J-page 22 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clear only bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ US: DSP Multiply Unsigned/Signed Control bit 1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed EDT: Early DO Loop Termination Control bit(1) 1 = Terminate executing DO loop at end of current loop iteration 0 = No effect DL: DO Loop Nesting Level Status bits 111 = 7 DO loops active • • • 001 = 1 DO loop active 000 = 0 DO loops active SATA: AccA Saturation Enable bit 1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled SATB: AccB Saturation Enable bit 1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled SATDW: Data Space Write from DSP Engine Saturation Enable bit 1 = Data space write saturation enabled 0 = Data space write saturation disabled ACCSAT: Accumulator Saturation Mode Select bit 1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation) IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space RND: Rounding Mode Select bit 1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled IF: Integer or Fractional Multiplier Mode Select bit 1 = Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops This bit will always read as ‘0’. The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level. © 2007-2011 Microchip Technology Inc. DS70290J-page 23 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.6 Arithmetic Logic Unit (ALU) 3.7 DSP Engine The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic). The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. The DSP engine can also perform accumulator-to-accumulator operations that require no additional data. These instructions are ADD, SUB and NEG. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. 3.6.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned 3.6.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: • • • • 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by the same instruction (e.g., ED, EDAC). The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below: • • • • Fractional or integer DSP multiply (IF) Signed or unsigned DSP multiply (US) Conventional or convergent rounding (RND) Automatic saturation on/off for AccA (SATA), AccB (SATB) and writes to data memory (SATDW) • Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. TABLE 3-1: Instruction CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC DSP INSTRUCTIONS SUMMARY Algebraic Operation ACC Write Back A=0 Yes No No Yes No Yes No No No Yes A = (x - y)2 A = A + (x - y)2 A = A + (x * y) A = A + x2 No change in A A=x• y A = x2 A=-x• y A=A-x•y The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. DS70290J-page 24 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array © 2007-2011 Microchip Technology Inc. DS70290J-page 25 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.7.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/scaler is a 33-bit value that is sign-extended to 40 bits. Integer data is inherently represented as a signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. • The range of an N-bit 2’s complement integer is -2N-1 to 2N-1 - 1. • For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’. • For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF). When the multiplier is configured for fractional multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the radix point is implied to lie just after the sign bit (QX format). The range of an N-bit 2’s complement fraction with this implied radix point is -1.0 to (1 - 21-N). For a 16-bit fraction, the Q15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF) including ‘0’ and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10-10. The same multiplier is used to support the MCU multiply instructions which include integer 16-bit signed, unsigned and mixed-sign multiply operations. The MUL instruction can be directed to use byte or word sized operands. Byte operands will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array. 3.7.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER The data accumulator consists of a 40-bit adder/subtracter with automatic sign extension logic. It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation. DS70290J-page 26 3.7.2.1 Adder/Subtracter, Overflow and Saturation The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. • In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented). • In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed. • Overflow into guard bits 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other. The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously and the SAT (CORCON) and ACCSAT (CORCON) mode control bits to determine when and to what value to saturate. Six STATUS register bits have been provided to support saturation and overflow: • OA: AccA overflowed into guard bits • OB: AccB overflowed into guard bits • SA: AccA saturated (bit 31 overflow and saturation) or AccA overflowed into guard bits and saturated (bit 39 overflow and saturation) • SB: AccB saturated (bit 31 overflow and saturation) or AccB overflowed into guard bits and saturated (bit 39 overflow and saturation) • OAB: Logical OR of OA and OB • SAB: Logical OR of SA and SB The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1 register are set (refer to Section 7.0 “Interrupt Controller”). This allows the user application to take immediate action, for example, to correct system gain. © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus indicate that a catastrophic overflow has occurred. If the COVTE bit in the INTCON1 register is set, SA and SB bits will generate an arithmetic warning trap when saturation is disabled. The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programs can check one bit in the STATUS register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators. The device supports three Saturation and Overflow modes: • Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations). • Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect, the guard bits are not used, so the OA, OB or OAB bits are never set. • Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user application. No saturation operation is performed and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap exception. 3.7.2.2 Accumulator ‘Write Back’ The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded version of the high word (bits 31 through 16) of the accumulator that is not targeted by the instruction © 2007-2011 Microchip Technology Inc. into data space memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported: • W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a 1.15 fraction. • [W13]+ = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write). 3.7.2.3 Round Logic The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function during an accumulator write (store). The Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the least significant word (lsw) is simply discarded. Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through 31 of the accumulator). • If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000 included), ACCxH is incremented. • If ACCxL is between 0x0000 and 0x7FFF, ACCxH is left unchanged. A consequence of this algorithm is that over a succession of random rounding operations, the value tends to be biased slightly positive. Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined. • If it is ‘1’, ACCxH is incremented. • If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate. The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 3.7.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. DS70290J-page 27 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 3.7.2.4 Data Space Write Saturation 3.7.3 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder. These inputs are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory. The barrel shifter can perform up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to support multi-bit shifts of register or memory data). If the SATDW bit in the CORCON register is set, data (after rounding or truncation) is tested for overflow and adjusted accordingly: The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result for DSP shift operations and a 16-bit result for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts. • For input data greater than 0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. • For input data less than 0xFF8000, data written to memory is forced to the maximum negative 1.15 value, 0x8000. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. The Most significant bit of the source (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. DS70290J-page 28 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70202) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: Program Address Space The program address memory space of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.8 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices are shown in Figure 4-1. PROGRAM MEMORY FOR dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DEVICES dsPIC33FJ32GP202/204 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Memory Space 4.1 User Program Flash Memory (11264 instructions) dsPIC33FJ16GP304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x0057FE 0x005800 Unimplemented (Read ‘0’s) User Memory Space 4.0 User Program Flash Memory (5632 instructions) 0xF7FFFE 0xF80000 0xF80017 0xF80018 0xFEFFFE 0xFF0000 0xFFFFFE Configuration Memory Space Configuration Memory Space Reserved Reserved © 2007-2011 Microchip Technology Inc. 0x002BFE 0x002C00 0x7FFFFE 0x800000 Reserved DEVID (2) 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Device Configuration Registers 0x000000 0x000002 0x000004 Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Reserved DEVID (2) 0xFEFFFE 0xFF0000 0xFFFFFE DS70290J-page 29 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. FIGURE 4-2: msw Address PROGRAM MEMORY ORGANIZATION 16 8 PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) DS70290J-page 30 least significant word most significant word 23 0x000001 0x000003 0x000005 0x000007 INTERRUPT AND TRAP VECTORS Instruction Width © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.2 Data Address Space The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 4.8.3 “Reading Data from Program Memory Using Program Space Visibility”). All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the instruction occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices implement up to 2 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.1 4.2.3 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007-2011 Microchip Technology Inc. SFR SPACE The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A complete listing of implemented SFRs, including their addresses, is shown in Table 4-1 through Table 4-22. Note: 4.2.4 The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer. DS70290J-page 31 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DEVICES WITH 2 Kbytes RAM MSB Address MSb 2 Kbyte SFR Space 2 Kbyte SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x0BFF 0x0001 X Data RAM (X) Y Data RAM (Y) 0x0FFF 0x1001 0x07FE 0x0800 0x0BFE 0x0C00 8 Kbyte Near data space 0x0FFE 0x1000 0x1FFF 0x2001 0x1FFE 0x2000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70290J-page 32 LSB Address 16 bits 0xFFFE © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concurrently fetch two words from RAM, thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT). The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X data prefetch path for the dual operand DSP instructions (MAC class). The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space. 4.3 Program Memory Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 4.3.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530331 KEY RESOURCES • • • • • • Section 4. “Program Memory” (DS70202) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable. All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2007-2011 Microchip Technology Inc. DS70290J-page 33 Special Function Register Maps TABLE 4-1: SFR Name CPU CORE REGISTERS MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets © 2007-2011 Microchip Technology Inc. WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 WREG13 001A Working Register 13 0000 WREG14 001C Working Register 14 0000 WREG15 001E Working Register 15 0800 SPLIM 0020 Stack Pointer Limit Register xxxx ACCAL 0022 Accumulator A Low Word Register 0000 ACCAH 0024 Accumulator A High Word Register 0000 ACCAU 0026 Accumulator A Upper Word Register 0000 ACCBL 0028 Accumulator B Low Word Register 0000 ACCBH 002A Accumulator B High Word Register 0000 ACCBU 002C Accumulator B Upper Word Register 0000 PCL 002E Program Counter Low Word Register PCH 0030 — — — — — — — — Program Counter High Byte Register 0000 TBLPAG 0032 — — — — — — — — Table Page Address Pointer Register 0000 PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register 0000 RCOUNT 0036 Repeat Loop Counter Register xxxx DCOUNT 0038 DCOUNT xxxx DOSTARTL 003A DOSTARTH 003C DOENDL 003E 0000 DOSTARTL — — — — — — — — — — 0 xxxx 0 xxxx DOSTARTH 00xx DOENDL DOENDH 0040 — — — — — — — — — — SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000 CORCON 0044 — — — US EDT SATA SATB SATDW ACCSAT IPL3 PSV RND IF 0020 Legend: DL x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DOENDH 00xx dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DS70290J-page 34 4.4 CPU CORE REGISTERS MAP (CONTINUED) Bit 0 All Resets XS 0 xxxx 004A XE 1 xxxx 004C YS 0 xxxx YE 1 xxxx SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND YMODSRT YMODEND 004E XBREV 0050 BREN DISICNT 0052 — SFR Name Legend: Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 BWM Bit 5 Bit 3 Bit 2 YWM Bit 1 XWM 0000 XB — xxxx Disable Interrupts Counter Register xxxx x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP202 SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE —- — 0062 — — — CN24IE CN7IE CNEN2 CN23IE CNPU1 0068 CN7PUE CN6PUE CN5PUE CNPU2 006A Legend: Bit 4 CN30IE CN29IE CN27IE — — CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN30PUE CN29PUE — — CN27PUE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CN6IE CN5IE CN4IE CN3IE CN2IE CN22IE CN21IE — CN4PUE — CN3PUE — CN2PUE — CN24PUE CN23PUE CN22PUE CN21PUE — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: — — Bit 0 All Resets CN1IE CN0IE 0000 — CN1PUE CN16IE 0000 CN0PUE 0000 — — CN16PUE 0000 CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 CNEN2 0062 — CN30IE CN29IE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN19IE CN18IE CN17IE CN16IE 0000 CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 CNPU2 006A CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE 0000 Legend: — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All Resets DS70290J-page 35 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 © 2007-2011 Microchip Technology Inc. TABLE 4-1: INTERRUPT CONTROLLER REGISTER MAP SFR Name SFR Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 — — — Bit 10 Bit 9 Bit 8 OVBTE COVTE — — — Bit 6 SFTACERR DIV0ERR Bit 5 — — — — Bit 4 Bit 3 Bit 2 Bit 1 MATHERR ADDRERR STKERR — — INT2EP Bit 0 All Resets OSCFAIL — 0000 INT1EP INT0EP 0000 IFS0 0084 — — AD1IF U1TXIF U1RXIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000 IFS1 0086 — — INT2IF — — — — — IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF 0000 IFS4 008C — — — — — — — — — — — — — — U1EIF — 0000 IEC0 0094 — — AD1IE U1TXIE U1RXIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 — — INT2IE — — — — — IC8IE IC7IE — INT1IE CNIE — IEC4 009C — — — — — — — — — — — — — — IPC0 00A4 — IPC1 00A6 IPC2 00A8 IPC3 00AA — — — — — IPC4 00AC — CNIP — — — — IPC5 00AE — IC8IP — IPC7 00B2 — — — — — — — — — INT2IP — — — — IPC16 00C4 — — — — — — — — — U1EIP — — — — INTTREG 00E0 — — — — Legend: T1IP — — T2IP — U1RXIP — — — SPI1IF SPI1EIF Bit 7 SPI1IE SPI1EIE OC1IP — — OC2IP — SPI1IP IC7IP ILR IC1IP — — IC2IP — — SPI1EIP — — AD1IP — MI2C1IP — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — — MI2C1IE SI2C1IE U1EIE — INT0IP — — 0000 0000 4444 — 4440 T3IP 4444 — U1TXIP 0044 — SI2C1IP 4044 — INT1IP VECNUM 4404 0040 0040 0000 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DS70290J-page 36 TABLE 4-4: SFR Name TIMER REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TMR2 0106 Timer2 Register 0000 TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx TMR3 010A Timer3 Register 0000 PR2 010C Period Register 2 FFFF PR3 010E Period Register 3 T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS T32 — TCS — 0000 T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS — — TCS — 0000 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM ICI ICOV ICBNE ICM Bit 4 Bit 3 Legend: TSIDL — — — — — — FFFF TGATE SFR Addr IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 IC7BUF 0158 IC7CON 015A IC8BUF 015C IC8CON 015E — TSYNC TCS — 0000 FFFF Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 Bit 6 Bit 5 Input 1 Capture Register — xxxx ICTMR 0000 Input 2 Capture Register — — ICSIDL — — — — — xxxx ICTMR 0000 Input 7 Capture Register — — ICSIDL — — — — — xxxx ICTMR 0000 Input 8 Capture Register — — ICSIDL — — — — — xxxx ICTMR 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 DS70290J-page 37 OC1RS 0180 Output Compare 1 Secondary Register OC1R 0182 Output Compare 1 Register OC1CON 0184 OC2RS 0186 Output Compare 2 Secondary Register OC2R 0188 Output Compare 2 Register OC2CON 018A Legend: TCKPS INPUT CAPTURE REGISTER MAP SFR Name SFR Name — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-6: Legend: TON 0000 — — — — OCSIDL OCSIDL — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 5 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx — — OCFLT OCTSEL OCM 0000 xxxx xxxx — — OCFLT OCTSEL OCM 0000 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 © 2007-2011 Microchip Technology Inc. TABLE 4-5: I2C1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — Receive Register 0000 I2C1TRN 0202 — — — — — — — — Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000 I2C1ADD 020A — — — — — — Address Register 0000 I2C1MSK 020C — — — — — — Address Mask Register 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-9: SFR Name SFR Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Baud Rate Generator Register All Resets 0000 UART1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 WAKE LPBACK Bit 5 Bit 4 Bit 3 ABAUD URXINV BRGH ADDEN RIDLE PERR Bit 2 Bit 1 All Resets STSEL 0000 URXDA 0110 U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT U1TXREG 0224 — — — — — — — UART Transmit Register xxxx U1RXREG 0226 — — — — — — — UART Receive Register 0000 U1BRG 0228 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-10: SFR Name URXISEL PDSEL Bit 0 FERR OERR Baud Rate Generator Prescaler 0000 SPI1 REGISTER MAP © 2007-2011 Microchip Technology Inc. SFR Addr Bit 15 Bit 14 Bit 13 SPI1STAT 0240 SPIEN — SPISIDL — — — — SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — SPI1BUF 0248 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — CKE SSEN SPIROV — — CKP MSTEN — — — SPI1 Transmit and Receive Buffer Register Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — SPITBF SPIRBF 0000 SPRE — — PPRE — FRMDLY — 0000 0000 0000 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DS70290J-page 38 TABLE 4-8: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 RPINR0 0680 — — — RPINR1 0682 — — — RPINR3 0686 — — — T3CKR RPINR7 068E — — — RPINR10 0694 — — — RPINR11 0696 — — — RPINR18 06A4 — — — U1CTSR RPINR20 06A8 — — — SCK1R RPINR21 06AA — — — Legend: Bit 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 1F00 — — — INT2R 001F — — — T2CKR 1F1F IC2R — — — IC1R 1F1F IC8R — — — IC7R 1F1F — — — OCFAR 001F — — — U1RX 1F1F — — — SDI1R 1F1F — — — SS1R 001F Bit 10 Bit 9 Bit 8 INT1R — — — — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: File Name Bit 12 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32GP202 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06C0 — — — RP1R — — — RP0R 0000 RPOR1 06C2 — — — RP3R — — — RP2R 0000 RPOR2 06C4 — — — RP5R — — — RP4R 0000 RPOR3 06C6 — — — RP7R — — — RP6R 0000 RPOR4 06C8 — — — RP9R — — — RP8R 0000 RPOR5 06CA — — — RP11R — — — RP10R 0000 RPOR6 06CC — — — RP13R — — — RP12R 0000 RPOR7 06CE — — — RP15R — — — RP14R 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70290J-page 39 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 © 2007-2011 Microchip Technology Inc. TABLE 4-11: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 File Name Addr Bit 15 Bit 14 Bit 13 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — RPOR3 06C6 — — RPOR4 06C8 — RPOR5 06CA RPOR6 Bit 11 Bit 10 Bit 9 Bit 8 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Bit 7 Bit 6 Bit 5 RP1R — — — RP0R 0000 RP3R — — — RP2R 0000 — RP5R — — — RP4R 0000 — RP7R — — — RP6R 0000 — — RP9R — — — RP8R 0000 — — — RP11R — — — RP10R 0000 06CC — — — RP13R — — — RP12R 0000 RPOR7 06CE — — — RP15R — — — RP14R 0000 RPOR8 06D0 — — — RP17R — — — RP16R 0000 RPOR9 06D2 — — — RP19R — — — RP18R 0000 RPOR10 06D4 — — — RP21R — — — RP20R 0000 RPOR11 06D6 — — — RP23R — — — RP22R 0000 RPOR12 06D8 — — — RP25R — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — RP24R 0000 Legend: Bit 12 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DS70290J-page 40 TABLE 4-13: ADC1 REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 Bit 15 Addr ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10 xxxx ADC1BUFB 0316 ADC Data Buffer 11 xxxx ADC1BUFC 0318 ADC Data Buffer 12 xxxx ADC1BUFD 031A ADC Data Buffer 13 xxxx ADC1BUFE 031C ADC Data Buffer 14 xxxx ADC1BUFE 031E ADC Data Buffer 15 AD1CON1 0320 AD1CON2 0322 AD1CON3 0324 AD1CHS123 AD1CHS0 ADON Bit 14 — Bit 13 ADSIDL VCFG Bit 12 Bit 10 Bit 9 Bit 8 — — AD12B FORM — — CSCNA CHPS ADRC — — 0326 — — — 0328 CH0NB — — AD1PCFGL 032C — — — PCFG12 AD1CSSL 0330 — — — CSS12 Legend: Bit 11 Bit 7 Bit 6 Bit 5 — — — CH123NB CSS11 CSS10 Bit 1 Bit 0 SIMSAM ASAM SAMP DONE BUFM ALTS ADCS CH123SB CH0SB PCFG11 PCFG10 Bit 2 SMPI SAMC — Bit 3 xxxx SSRC BUFS Bit 4 All Resets File Name — — — CH0NA — — — — 0000 0000 0000 CH123NA CH123SA CH0SA 0000 0000 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70290J-page 41 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 © 2007-2011 Microchip Technology Inc. TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ32GP202 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets File Name Addr ADC1BUF0 0300 ADC Data Buffer 0 xxxx ADC1BUF1 0302 ADC Data Buffer 1 xxxx ADC1BUF2 0304 ADC Data Buffer 2 xxxx ADC1BUF3 0306 ADC Data Buffer 3 xxxx ADC1BUF4 0308 ADC Data Buffer 4 xxxx ADC1BUF5 030A ADC Data Buffer 5 xxxx ADC1BUF6 030C ADC Data Buffer 6 xxxx ADC1BUF7 030E ADC Data Buffer 7 xxxx ADC1BUF8 0310 ADC Data Buffer 8 xxxx ADC1BUF9 0312 ADC Data Buffer 9 xxxx ADC1BUFA 0314 ADC Data Buffer 10 xxxx ADC1BUFB 0316 ADC Data Buffer 11 xxxx ADC1BUFC 0318 ADC Data Buffer 12 xxxx © 2007-2011 Microchip Technology Inc. ADC1BUFD 031A ADC Data Buffer 13 xxxx ADC1BUFE 031C ADC Data Buffer 14 xxxx ADC1BUFF 031E AD1CON1 0320 AD1CON2 0322 AD1CON3 0324 ADRC — — AD1CHS123 0326 — — — AD1CHS0 0328 CH0NB — — AD1PCFGL 032C — — — 0330 — — — AD1CSSL Legend: ADC Data Buffer 15 ADON — ADSIDL VCFG — — AD12B FORM — — CSCNA CHPS — — xxxx SSRC BUFS — — — — CSS11 CSS10 SAMP DONE 0000 BUFM ALTS 0000 CH123SA 0000 ADCS CH123NB CH123SB CH0SB CSS12 ASAM SMPI SAMC PCFG12 PCFG11 PCFG10 SIMSAM — — — 0000 CH123NA CH0NA — — PCFG9 — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 CSS9 — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. CH0SA 0000 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DS70290J-page 42 TABLE 4-15: PORTA REGISTER MAP FOR dsPIC33FJ32GP202 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — — — — — — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. File Name TABLE 4-17: PORTA REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — TRISA10 TRISA9 TRISA8 TRISA7 — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — RA10 RA9 RA8 RA7 — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — LATA10 LATA9 LATA8 LATA7 — — LATA4 LATA3 LATA2 LATA1 LATA0 xxxx ODCA 02C6 — — — — — ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. File Name TABLE 4-18: PORTB REGISTER MAP Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF PORTB 02CA RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx LATB 02CC LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. File Name TABLE 4-19: File Name PORTC REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets DS70290J-page 43 TRISC 02D0 — — — — — — TRISC9 TRISC8 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 03FF PORTC 02D2 — — — — — — RC9 RC8 RC7 RC6 RC5 RC4 RC4 RC2 RC1 RC0 xxxx LATC 02D4 — — — — — — LATC9 LATC8 LATC7 LATC6 LATC5 LATC4 LATC4 LATC2 LATC1 LATC0 xxxx 02D6 — — — — — — ODCC9 ODCC8 ODCC7 ODCC6 ODCC5 ODCC4 ODCC4 ODCC2 ODCC1 ODCC0 0000 ODCC Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 © 2007-2011 Microchip Technology Inc. TABLE 4-16: SYSTEM CONTROL REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) OSCCON 0742 — — CF — LPOSCEN OSWEN 0300(2) CLKDIV 0744 ROI PLLFBD 0746 — — — — — — — OSCTUN 0748 — — — — — — — Legend: Note 1: 2: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 4-21: COSC — DOZE DOZEN Addr Bit 15 Bit 14 Bit 13 NVMCON 0760 WR WREN WRERR — — — NVMKEY 0766 — — — — — — LOCK FRCDIV PLLPOST — PLLPRE 3040 PLLDIV — — 0030 — TUN 0000 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — — — ERASE — — — Bit 4 Bit 3 — Bit 2 Bit 1 Bit 0 All Resets 0000(1) NVMOP NVMKEY 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 4-22: File Name CLKLOCK IOLOCK NVM REGISTER MAP File Name Legend: Note 1: NOSC Addr PMD REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets PMD1 0770 — — T3MD T2MD T1MD — — — I2C1MD — U1MD — SPI1MD — — AD1MD 0000 PMD2 0772 IC8MD IC7MD — — — — IC2MD IC1MD — — — — — — OC2MD OC1MD 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 DS70290J-page 44 TABLE 4-20: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.4.1 4.4.2 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word-aligned. When an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1000 in RAM, initialize the SPLIM with the value 0x0FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 4-4: Stack Grows Toward Higher Address 0x0000 15 CALL STACK FRAME 0 DATA RAM PROTECTION FEATURE The dsPIC33F product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for Boot Segment) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 4-1 for an overview of the BSRAM and SSRAM SFRs. 4.5 Instruction Addressing Modes The addressing modes shown in Table 4-23 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.5.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.5.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where: Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: © 2007-2011 Microchip Technology Inc. Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. DS70290J-page 45 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TABLE 4-23: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA.) Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset 4.5.3 The sum of Wn and a literal forms the EA. MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). In summary, the following addressing modes are supported by move and accumulator instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: 4.5.4 The two-source operand prefetch registers must be members of the set {W8, W9, W10, W11}. For data reads, W8 and W9 are always directed to the X RAGU, and W10 and W11 are always directed to the Y AGU. The effective addresses generated (before and after modification) must, therefore, be valid addresses within X data space for W8 and W9 and Y data space for W10 and W11. Note: Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). In summary, the following addressing modes are supported by the MAC class of instructions: • • • • • Register Indirect Register Indirect Post-Modified by 2 Register Indirect Post-Modified by 4 Register Indirect Post-Modified by 6 Register Indirect with Register Offset (Indexed) 4.5.5 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. MAC INSTRUCTIONS The dual source operand DSP instructions (CLR, ED, EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred to as MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. DS70290J-page 46 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.6 Modulo Addressing Note: Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into program space) and Y data spaces. Modulo Addressing can operate on any W register pointer. However, it is not advisable to use W14 or W15 for Modulo Addressing since these two registers are used as the Stack Frame Pointer and Stack Pointer, respectively. In general, any particular circular buffer can be configured to operate in only one direction, as there are certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing buffers), based upon the direction of the buffer. The only exception to the usage restrictions is for buffers that have a power-of-two length. As these buffers satisfy the start and end address criteria, they can operate in a bidirectional mode (that is, address boundary checks are performed on both the lower and upper address boundaries). 4.6.1 START AND END ADDRESS The Modulo Addressing scheme requires that a starting and ending address be specified and loaded into the 16-bit Modulo Buffer Address registers: XMODSRT, XMODEND, YMODSRT and YMODEND (see Table 4-1). FIGURE 4-5: Y space Modulo Addressing EA calculations assume word sized data (LSB of every EA is always clear). The length of a circular buffer is not directly specified. It is determined by the difference between the corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes). 4.6.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control register, MODCON, contains enable flags as well as a W register field to specify the W Address registers. The XWM and YWM fields select the registers that will operate with Modulo Addressing: • If XWM = 15, X RAGU and X WAGU Modulo Addressing is disabled. • If YWM = 15, Y AGU Modulo Addressing is disabled. The X Address Space Pointer W register (XWM), to which Modulo Addressing is to be applied, is stored in MODCON (see Table 4-1). Modulo Addressing is enabled for X data space when XWM is set to any value other than ‘15’ and the XMODEN bit is set at MODCON. The Y Address Space Pointer W register (YWM) to which Modulo Addressing is to be applied is stored in MODCON. Modulo Addressing is enabled for Y data space when YWM is set to any value other than ‘15’ and the YMODEN bit is set at MODCON. MODULO ADDRESSING OPERATION EXAMPLE Byte Address 0x1100 MOV MOV MOV MOV MOV MOV #0x1100, W0 W0, XMODSRT #0x1163, W0 W0, MODEND #0x8001, W0 W0, MODCON MOV #0x0000, W0 ;W0 holds buffer fill value MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 MOV W0, [W1++] AGAIN: INC W0, W0 0x1163 ;set modulo start address ;set modulo end address ;enable W1, X AGU for modulo ;fill the 50 buffer locations ;fill the next location ;increment the fill value Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2007-2011 Microchip Technology Inc. DS70290J-page 47 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.6.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: • The upper boundary addresses for incrementing buffers • The lower boundary addresses for decrementing buffers It is important to realize that the address boundaries also check for addresses less than or greater than these addresses. Address changes can, therefore, jump beyond boundaries and still be adjusted correctly. Note: 4.7 The modulo corrected effective address is written back to the register only when Pre-Modify or Post-Modify Addressing mode is used to compute the effective address. When an address offset (such as [W7+W2]) is used, Modulo Address correction is performed but the contents of the register remain unchanged. Bit-Reversed Addressing Bit-Reversed Addressing mode is intended to simplify data re-ordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. 4.7.1 BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-Reversed Addressing mode is enabled in any of these situations: If the length of a bit-reversed buffer is M = 2N bytes, the last ‘N’ bits of the data buffer start address must be zeros. XB is the Bit-Reversed Address modifier, or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word sized data (LSB of every EA is always clear). The XB value is scaled accordingly to generate compatible (byte) addresses. When enabled, Bit-Reversed Addressing is executed only for Register Indirect with Pre-Increment or Post-Increment Addressing and word sized data writes. It will not function for any other addressing mode or for byte sized data, and normal addresses are generated instead. When Bit-Reversed Addressing is active, the W Address Pointer is always added to the address modifier (XB), and the offset associated with the Register Indirect Addressing mode is ignored. In addition, as word sized data is a requirement, the LSb of the EA is ignored (and always clear). Note: Modulo Addressing and Bit-Reversed Addressing should not be enabled together. If an application attempts to do so, Bit-Reversed Addressing will assume priority when active for the X WAGU and X WAGU Modulo Addressing will be disabled. However, Modulo Addressing will continue to function in the X RAGU. If Bit-Reversed Addressing has already been enabled by setting the BREN bit (XBREV), a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. • BWM bits (W register selection) in the MODCON register are any value other than ‘15’ (the stack cannot be accessed using Bit-Reversed Addressing). • The BREN bit is set in the XBREV register. • The addressing mode used is Register Indirect with Pre-Increment or Post-Increment. DS70290J-page 48 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 4-6: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-24: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 8 0 0 1 0 2 0 1 0 0 4 0 0 1 1 3 1 1 0 0 12 0 1 0 0 4 0 0 1 0 2 0 1 0 1 5 1 0 1 0 10 0 1 1 0 6 0 1 1 0 6 0 1 1 1 7 1 1 1 0 14 1 0 0 0 8 0 0 0 1 1 1 0 0 1 9 1 0 0 1 9 1 0 1 0 10 0 1 0 1 5 1 0 1 1 11 1 1 0 1 13 1 1 0 0 12 0 0 1 1 3 1 1 0 1 13 1 0 1 1 11 1 1 1 0 14 0 1 1 1 7 1 1 1 1 15 1 1 1 1 15 © 2007-2011 Microchip Technology Inc. DS70290J-page 49 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.8 Interfacing Program and Data Memory Spaces 4.8.1 Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). Aside from normal execution, the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-25: ADDRESSING PROGRAM SPACE Table 4-25 and Figure 4-7 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word. PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG Configuration TBLPAG Data EA 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility (Block Remap/Read) Note 1: PC 0 0xx xxxx xxxx 0xxx xxxx User 0 xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx 0 PSVPAG 0 xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. DS70290J-page 50 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 FIGURE 4-7: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space (Remapping) Visibility(1) 0 1 EA 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2007-2011 Microchip Technology Inc. DS70290J-page 51 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.8.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D). FIGURE 4-8: In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom byte’, will always be ‘0’. In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, as in the TBLRDL instruction. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 23 15 0 0x000000 23 16 8 0 00000000 0x020000 0x030000 00000000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W 0x800000 DS70290J-page 52 The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 4.8.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDH). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 4-9), only the lower 16 bits of the FIGURE 4-9: 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data to execute in a single cycle. PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 Data Space 0 0x000000 0x0000 Data EA 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... 0x8000 PSV Area 0x800000 © 2007-2011 Microchip Technology Inc. ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. DS70290J-page 53 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 NOTES: DS70290J-page 54 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 5.0 FLASH PROGRAM MEMORY ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Note 1: This data sheet summarizes the features of the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Programming” (DS70191) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 5.1 The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), FIGURE 5-1: Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter Program Counter 0 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits User/Configuration Space Select © 2007-2011 Microchip Technology Inc. 16 bits 24-bit EA Byte Select DS70290J-page 55 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 5.2 RTSP Operation The dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. 5.3 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 22-18) and the value of the FRC Oscillator Tuning register (see Register 8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 22-12). EQUATION 5-1: PROGRAMMING TIME The maximum row write time is equal to Equation 5-3. EQUATION 5-3: MAXIMUM ROW WRITE TIME 11064 Cycles T RW = ------------------------------------------------------------------------------------------------ = 1.586ms 7.37 MHz × ( 1 – 0.05 ) × ( 1 – 0.00375 ) Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Flash Memory Resources Many useful resources are provided on the main product page of the Microchip web site for the devices listed in this data sheet. This product page, which can be accessed using this link, contains the latest updates and additional information. Note: 5.4.1 In the event you are not able to access the product page using the link above, enter this URL in your browser: http://www.microchip.com/wwwproducts/ Devices.aspx?dDocName=en530331 KEY RESOURCES • • • • • • Section 5. “Flash Programming” (DS70191) Code Samples Application Notes Software Libraries Webinars All related dsPIC33F/PIC24H Family Reference Manuals Sections • Development Tools 5.5 Control Registers The two SFRs that are used to read and write the program Flash memory are: • NVMCON: Flash Memory Control Register • NVMKEY: Nonvolatile Memory Key Register T --------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy )% × ( FRC Tuning )% The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. For example, if the device is operating at +125° C, the FRC accuracy will be ±5%. If the TUN bits (see Register 8-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. NVMKEY (Register 5-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. EQUATION 5-2: MINIMUM ROW WRITE TIME 11064 Cycles T RW = ------------------------------------------------------------------------------------------------ = 1.435ms 7.37 MHz × ( 1 + 0.05 ) × ( 1 – 0.00375 ) DS70290J-page 56 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 U-0 bit 8 R/W-0(1) — U-0 ERASE — U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) (2) — NVMOP bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: 2: These bits can only be reset on POR. All other combinations of NVMOP bits are unimplemented. © 2007-2011 Microchip Technology Inc. DS70290J-page 57 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY: Key Register (Write Only) bits DS70290J-page 58 x = Bit is unknown © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE bit (NVMCON) and the WREN bit (NVMCON). b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 5-1: For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. ERASING A PROGRAM MEMORY PAGE ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP 6. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR © 2007-2011 Microchip Technology Inc. ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority 4)16@ ZLWKPP&RQWDFW/HQJWK 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS70290J-page 276 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 6.30 6.45 6.80 b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 8.00 BSC 6.30 6.45 6.80 8.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103B © 2007-2011 Microchip Technology Inc. DS70290J-page 277 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS70290J-page 278 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.20 1.00 REF Foot Angle φ Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC 0° 3.5° 7° Lead Thickness c 0.09 – 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B © 2007-2011 Microchip Technology Inc. DS70290J-page 279 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70290J-page 280 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 APPENDIX A: REVISION HISTORY Revision A (July 2007) This is the initial released version of the document. Revision B (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name “High-Performance, 16-bit Digital Signal Controllers” Update Description Added Extended Interrupts column to Remappable Peripherals in the Controller Families table and Note 2 (see Table 1). Added Note 1 to all pin diagrams, which references RPn pin usage by remappable peripherals (see “Pin Diagrams”). Section 1.0 “Device Overview” Changed PORTA pin name from RA15 to RA10 (see Table 1-1). Section 3.0 “Memory Organization” Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and ACCBU) to the CPU Core Register Map (see Table 3-1). Updated Reset value for CORCON (see Table 3-1). Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7, IPC16 and INTTREG (see Table 3-4). Updated the Reset value for CLKDIV in the System Control Register Map (see Table 3-20). Section 6.0 “Resets” Entire section was replaced to maintain consistency with other dsPIC33F data sheets. Section 7.0 “Oscillator Configuration” Removed the first sentence of the third clock source item (External Clock) in Section 7.1.1.2 “Primary”. Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register 7-2). Added the center frequency in the OSCTUN register for the FRC Tuning bits (TUN) value 011111 and updated the center frequency for bits value 011110 (see Register 7-4). Section 8.0 “Power-Saving Features” Added the following two registers: • PMD1: Peripheral Module Disable Control Register 1 • PMD2: Peripheral Module Disable Control Register 2 Section 9.0 “I/O Ports” Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain Configuration”, which provides details on I/O pins and their functionality. Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 9.4.2 “Available Peripherals” • 9.4.3.3 “Mapping” • 9.4.5 “Considerations for Peripheral Pin Selection” Section 13.0 “Output Compare” © 2007-2011 Microchip Technology Inc. Replaced sections 13.1, 13.2 and 13.3 and related figures and tables with entirely new content. DS70290J-page 281 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 14.0 “Serial Peripheral Interface (SPI)” Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 14.1 “Interrupts” • 14.2 “Receive Operations” • 14.3 “Transmit Operations” • 14.4 “SPI Setup” (retained Figure 14-1: SPI Module Block Diagram) Section 15.0 “Inter-Integrated Circuit (I2C™)” Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 15.3 “I2C Interrupts” • 15.4 “Baud Rate Generator” (retained Figure 15-1: I2C Block Diagram) • 15.5 “I2C Module Addresses” • 15.6 “Slave Address Masking” • 15.7 “IPMI Support” • 15.8 “General Call Address Support” • 15.9 “Automatic Clock Stretch” • 15.10 “Software Controlled Clock Stretching (STREN = 1)” • 15.11 “Slope Control” • 15.12 “Clock Arbitration” • 15.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration” • 15.14 “Peripheral Pin Select Limitations” Section 16.0 “Universal Removed the following sections, which are now available in the related Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual: (UART)” • 16.1 “UART Baud Rate Generator” • 16.2 “Transmitting in 8-bit Data Mode” • 16.3 “Transmitting in 9-bit Data Mode” • 16.4 “Break and Sync Transmit Sequence” • 16.5 “Receiving in 8-bit or 9-bit Data Mode” • 16.6 “Flow Control Using UxCTS and UxRTS Pins” • 16.7 “Infrared Support” Removed IrDA references and Note 1, and updated the bit and bit value descriptions for UTXINV (UxSTA) in the UARTx Status and Control Register (see Register 16-2). Section 17.0 “10-bit/12-bit Analogto-Digital Converter (ADC)” Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2: ADC Transfer Function (10-Bit Example). Added ADC1 Module Block Diagram for dsPIC33FJ16GP304 and dsPIC33FJ32GP204 Devices (Figure 18-1) and ADC1 Module Block Diagram FOR dsPIC33FJ32GP202 Devices (Figure 17-2). Added Note 2 to Figure 17-3: ADC Conversion Clock Period Block Diagram. Added device-specific information to Note 1 in the ADC1 Input Scan Select Register Low (see Register 17-6), and updated the default bit value for bits 12-10 (CSS12-CSS10) from U-0 to R/W-0. Added device-specific information to Note 1 in the ADC1 Port Configuration Register Low (see Register 17-7), and updated the default bit value for bits 12-10 (PCFG12-PCFG10) from U-0 to R/W-0. DS70290J-page 282 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 18.0 “Special Features” Update Description Added FICD register information for address 0xF8000E in the Device Configuration Register Map (see Table 18-1). Added FICD register content (BKBUG, COE, JTAGEN, and ICS to the dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Configuration Bits Description (see Table 18-2). Added a note regarding the placement of low-ESR capacitors, after the second paragraph of Section 18.2 “On-Chip Voltage Regulator” and to Figure 18-1. Removed the words “if enabled” from the second sentence in the fifth paragraph of Section 18.3 “BOR: Brown-out Reset”. Section 21.0 “Electrical Characteristics” Updated Max MIPS value for -40ºC to +125ºC temperature range in Operating MIPS vs. Voltage (see Table 21-1). Removed Typ value for parameter DC12 (see Table 22-4). Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f and DC72g (see Table 21-5, Table 21-6 and Table 21-8). Added Note 4 (reference to new table containing digital-only and analog pin information to I/O Pin Input Specifications (see Table 21-9). Updated Typ, Min, and Max values for Program Memory parameters D136, D137, and D138 (see Table 21-12). Updated Max value for Internal RC Accuracy parameter F21 for -40°C ≤TA ≤ +125°C condition and added Note 2 (see Table 21-19). Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and Power-up Timer parameter SY20 and updated conditions, which now refers to Section 18.4 “Watchdog Timer (WDT)” and LPRC parameter F21a (see Table 21-21). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table 21-37). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table 21-38). © 2007-2011 Microchip Technology Inc. DS70290J-page 283 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Revision C (December 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Diagrams”). Section 2.0 “Guidelines for Getting Started with 16-bit Digital Signal Controllers” Added new section to the data sheet that provides guidelines on getting started with 16-bit Digital Signal Controllers. Section 10.0 “I/O Ports” Updated 5V tolerant status for I/O pin RB4 from Yes to No (see Table 10-1). Section 22.0 “Electrical Characteristics” Removed the maximum value for parameter DC12 (RAM Data Retention Voltage) in Table 22-4. Updated typical values for Operating Current (IDD) and added Note 3 in Table 22-5. Updated typical and maximum values for Idle Current (IIDLE): Core OFF Clock ON Base Current and added Note 3 in Table 22-6. Updated typical and maximum values for Power Down Current (IPD) and added Note 5 in Table 22-7. Updated typical and maximum values for Doze Current (IDOZE) and added Note 2 in Table 22-8. Added Note 3 to Table 22-12. Updated minimum value for Internal Voltage Regulator Specifications in Table 22-13. Added parameter OS42 (GM) and Notes 4, 5, and 6 to Table 22-16. Added Notes 2 and 3 to Table 22-17. Added Note 2 to Table 22-20. Added Note 2 to Table 22-21. Added Note 2 to Table 22-22. Added Note 1 to Table 22-23. Added Note 1 to Table 22-24. Added Note 3 to Table 22-32. Added Note 2 to Table 22-33. Updated typical value for parameter AD08 (ADC in operation) and added Notes 2 and 3 in Table 22-34. Updated minimum, typical, and maximum values for parameters AD23a, AD24a, AD30a, AD32a, AD32a, and AD34a, and added Notes 2 and 3 in Table 22-35. Updated minimum, typical, and maximum values for parameters AD23b, AD24b, AD30b, AD32b, AD32b, and AD34b, and added Notes 2 and 3 in Table 22-36. DS70290J-page 284 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Revision D (October 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2. • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2 or 3) to PGECx and PGEDx. Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE All other major changes are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section 8.0 “Oscillator Configuration” Updated the Oscillator System Diagram (see Figure 8-1). Added Note 1 to the Oscillator Tuning (OSCTUN) register (see Register 8-4). Section 10.0 “I/O Ports” Removed Table 10-1 and added reference to pin diagrams for I/O pin availability and functionality. Section 15.0 “Serial Peripheral Interface (SPI)” Added Note 2 to the SPIx Control Register 1 (see Register 15-2). Section 17.0 “Universal Asynchronous Receiver Transmitter (UART)” Updated the UTXINV bit settings in the UxSTA register and added Note 1 (see Register 17-2). Section 22.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage) and added Note 4 to the DC Temperature and Voltage Specifications (see Table 22-4). Updated the Min value for parameter DI35 (see Table 22-20). Updated AD08 and added reference to Note 2 for parameters AD05a, AD06a and AD08a (see Table 22-34). © 2007-2011 Microchip Technology Inc. DS70290J-page 285 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Revision E (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Added information on high temperature operation (see “Operating Range:”). Section 10.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section 10.2 “Open-Drain Configuration”. Section 17.0 “Universal Asynchronous Receiver Transmitter (UART)” Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 MIPS. Section 18.0 “10-bit/12-bit Analog-to-Digital Converter (ADC)” Updated the ADC1 block diagrams (see Figure 18-1 and Figure 18-2). Section 19.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section 19.1 “Configuration Bits”. Section 22.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated the Device Configuration Register Map (see Table 19-1). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure 22-12). Updated the Internal RC Accuracy parameter numbers (see Table 22-18 and Table 22-19). Section 23.0 “High Temperature Electrical Characteristics” Added new chapter with high temperature specifications. “Product Identification System” Added the “H” definition for high temperature. Revision F (November 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-5: MAJOR SECTION UPDATES Section Name “High-Performance, 16-bit Digital Signal Controllers” DS70290J-page 286 Update Description Updated MIPS rating from 16 to 20 for high temperature devices in “Operating Range:” and in TABLE 22-1: “Operating MIPS vs. Voltage”. © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Revision G (January 2011) This revision includes typographical and formatting changes throughout the data sheet text. In addition, all instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table. TABLE A-6: MAJOR SECTION UPDATES Section Name Update Description High-Performance, 16-bit Digital Signal Controllers Added the SSOP package information (see “Packaging:”, Table 1, and “Pin Diagrams”). Section 2.0 “Guidelines for Getting Started with 16-bit Digital Signal Controllers” Updated the title of Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”. The frequency limitation for device PLL start-up conditions was updated in Section 2.7 “Oscillator Value Conditions on Device Start-up”. The second paragraph in Section 2.9 “Unused I/Os” was updated. Section 3.0 “CPU” Removed references to DMA in the CPU Core Block Diagram (see Figure 3-1). Section 4.0 “Memory Organization” Updated the data memory reference in the third paragraph in Section 4.2 “Data Address Space”. The All Resets values for the following SFRs in the Timer Register Map were changed (see Table 4-5): • TMR1 • TMR2 • TMR3 Section 8.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see Register 8-1). Added Note 2 to the CLKDIV: Clock Divisor Register (see Register 8-2). Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see Register 8-3). Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see Register 8-4). Section 18.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams (see Figure 18-1 and Figure 18-2). Converter (ADC)” Section 19.0 “Special Features” Added a new paragraph and removed the third paragraph in Section 19.1 “Configuration Bits”. Added the column “RTSP Effects” to the Configuration Bits Descriptions (see Table 19-2). Section 24.0 “Packaging Information” © 2007-2011 Microchip Technology Inc. Added the 28-Lead SSOP package information (see Section 24.1 “Package Marking Information” and Section 24.2 “Package Details”). DS70290J-page 287 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 TABLE A-6: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 22.0 “Electrical Characteristics” Update Description Added the 28-pin SSOP Thermal Packaging Characteristics (see Table 22-3). Removed Note 4 from the DC Temperature and Voltage Specifications (see Table 22-4). Updated the maximum value for parameters DI18 and DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table 22-9). Updated Note 3 in the PLL Clock Timing Specifications (see Table 22-17). Removed Note 2 from the AC Characteristics: Internal RC Accuracy (see Table 22-18). Updated the characteristic description for parameter DI35 in the I/O Timing Requirements (see Table 22-20). Updated all SPI specifications (see Table 22-28 through Table 22-35 and Figure 22-10 through Figure 22-16). Added Note 4 to the 12-bit mode ADC Module Specifications (see Table 22-39). Added Note 4 to the 10-bit mode ADC Module Specifications (see Table 22-40). Section 23.0 “High Temperature Electrical Characteristics” Updated all ambient temperature end range values to +150ºC throughout the chapter. Updated the storage temperature end range to +160ºC. Updated the maximum junction temperature from +145ºC to +155ºC. Updated Note 1 in the PLL Clock Timing Specifications (see Table 23-10). Added Note 3 to the 12-bit Mode ADC Module Specifications (see Table 23-17). Added Note 3 to the 10-bit Mode ADC Module Specifications (see Table 23-18). “Product Identification System” DS70290J-page 288 Added the “SS” definition for the SSOP package. © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Revision H (July 2011) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-7: MAJOR SECTION UPDATES Section Name Update Description Section 19.0 “Special Features” Added Note 3 to the Connections for the On-chip Voltage Regulator diagram (see Figure 19-1). Section 22.0 “Electrical Characteristics” Removed Note 3 and parameter DC10 (VCORE) from the DC Temperature and Voltage Specifications (see Table 22-4). Updated the Characteristics definition and Conditions for parameter BO10 in the Electrical Characteristics: BOR (see Table 22-11). Added Note 1 to the Internal Voltage Regulator Specifications (see Table 22-13). Revision J (June 2012) This revision includes typographical and formatting changes throughout the data sheet text. In addition, where applicable, new sections were added to each peripheral chapter that provide information and links to related resources, as well as helpful tips. For examples, see Section 8.2 “Oscillator Resources” and Section 18.3 “ADC Helpful Tips”. All other major changes are referenced by their respective section in the following table. TABLE A-8: MAJOR SECTION UPDATES Section Name Update Description Section 22.0 “Electrical Characteristics” Added Note 1 to the Operating MIPS vs. Voltage (see Table 22-1). Updated the notes in the following tables: • Operating Current (IDD) (see Table 22-5) • Idle Current (IIDLE) (see Table 22-6) • Power-Down Current (IPD) (see Table 22-7) • Doze Current (IDOZE) (see Table 22-8) Updated the conditions for Program Memory parameters D136b, D137b, and D138b (TA = +150ºC) (see Table 22-12). Section 23.0 “High Temperature Electrical Characteristics” Removed Table 23-8: DC Characteristics: Program Memory. Section 24.0 “DC and AC Device Characteristics Graphs” Added new chapter. © 2007-2011 Microchip Technology Inc. DS70290J-page 289 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 NOTES: DS70290J-page 290 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 INDEX A A/D Converter ................................................................... 175 Initialization ............................................................... 175 Key Features............................................................. 175 AC Characteristics .................................................... 220, 257 ADC Module.............................................................. 260 ADC Module (10-bit Mode) ....................................... 261 ADC Module (12-bit Mode) ....................................... 260 Internal RC Accuracy ................................................ 222 Load Conditions ................................................ 220, 257 ADC Module ADC11 Register Map ...................................... 39, 41, 42 Alternate.............................................................................. 71 Alternate Interrupt Vector Table .......................................... 71 Alternate Interrupt Vector Table (AIVT) .............................. 71 Arithmetic Logic Unit (ALU)................................................. 24 Assembler MPASM Assembler................................................... 206 B Barrel Shifter ....................................................................... 28 Bit-Reversed Addressing .................................................... 48 Example ...................................................................... 49 Implementation ........................................................... 48 Sequence Table (16-Entry)......................................... 49 Block Diagrams 16-bit Timer1 Module ................................................ 137 A/D Module ....................................................... 176, 177 Connections for On-Chip Voltage Regulator............. 193 Device Clock ......................................................... 97, 99 DSP Engine ................................................................ 25 dsPIC33F .................................................................... 10 dsPIC33F CPU Core................................................... 18 Input Capture ............................................................ 147 Output Compare ....................................................... 151 PLL.............................................................................. 99 Reset System.............................................................. 61 Shared Port Structure ............................................... 115 SPI ............................................................................ 155 Timer2 (16-bit) .......................................................... 142 Timer2/3 (32-bit) ....................................................... 142 UART ........................................................................ 169 Watchdog Timer (WDT) ............................................ 194 C C Compilers MPLAB C18 .............................................................. 206 Clock Switching................................................................. 107 Enabling .................................................................... 107 Sequence.................................................................. 107 Code Examples Erasing a Program Memory Page............................... 59 Initiating a Programming Sequence............................ 60 Loading Write Buffers ................................................. 60 Port Write/Read ........................................................ 116 PWRSAV Instruction Syntax..................................... 109 Code Protection ........................................................ 189, 195 Configuration Bits.............................................................. 189 Description (Table).................................................... 190 Configuration Register Map .............................................. 189 Configuring Analog Port Pins ............................................ 116 CPU Control Register .......................................................... 21 CPU Clocking System......................................................... 98 © 2007-2011 Microchip Technology Inc. Options ....................................................................... 98 Selection..................................................................... 98 Customer Change Notification Service............................. 295 Customer Notification Service .......................................... 295 Customer Support............................................................. 295 D Data Accumulators and Adder/Subtractor .......................... 26 Data Space Write Saturation ...................................... 28 Overflow and Saturation ............................................. 26 Round Logic ............................................................... 27 Write Back .................................................................. 27 Data Address Space........................................................... 31 Alignment.................................................................... 31 Memory Map for dsPIC33F Devices with 8 KBs RAM 32 Near Data Space ........................................................ 31 Software Stack ........................................................... 45 Width .......................................................................... 31 DC and AC Characteristics Graphs and Tables ................................................... 263 DC Characteristics............................................................ 210 Doze Current (IDOZE)................................................ 255 High Temperature..................................................... 254 I/O Pin Input Specifications ...................................... 216 I/O Pin Output Specifications............................ 218, 256 Idle Current (IDOZE) .................................................. 215 Idle Current (IIDLE) .................................................... 213 Operating Current (IDD) ............................................ 212 Operating MIPS vs. Voltage ..................................... 254 Power-Down Current (IPD)........................................ 214 Power-down Current (IPD) ........................................ 255 Program Memory...................................................... 219 Temperature and Voltage......................................... 254 Temperature and Voltage Specifications.................. 211 Thermal Operating Conditions.................................. 254 Development Support ....................................................... 205 DSP Engine ........................................................................ 24 Multiplier ..................................................................... 26 E Electrical Characteristics .................................................. 209 AC..................................................................... 220, 257 Equations Device Operating Frequency...................................... 98 Errata .................................................................................... 7 F Flash Program Memory ...................................................... 55 Control Registers........................................................ 56 Operations .................................................................. 56 Programming Algorithm.............................................. 59 RTSP Operation ......................................................... 56 Table Instructions ....................................................... 55 Flexible Configuration ....................................................... 189 H High Temperature Electrical Characteristics .................... 253 I I/O Ports ........................................................................... 115 Parallel I/O (PIO) ...................................................... 115 Write/Read Timing.................................................... 116 I2 C Operating Modes ...................................................... 161 DS70290J-page 291 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Registers ................................................................... 163 I2C Module I2C1 Register Map ...................................................... 38 In-Circuit Debugger ........................................................... 196 In-Circuit Emulation........................................................... 189 In-Circuit Serial Programming (ICSP) ....................... 189, 196 Input Capture Registers ................................................................... 149 Input Change Notification.................................................. 116 Instruction Addressing Modes............................................. 45 File Register Instructions ............................................ 45 Fundamental Modes Supported.................................. 46 MAC Instructions......................................................... 46 MCU Instructions ........................................................ 45 Move and Accumulator Instructions ............................ 46 Other Instructions........................................................ 46 Instruction Set Overview ................................................................... 200 Summary................................................................... 197 Instruction-Based Power-Saving Modes ........................... 109 Idle ............................................................................ 110 Sleep ......................................................................... 109 Internal RC Oscillator Use with WDT ........................................................... 194 Internet Address................................................................ 295 Interrupt Control and Status Registers................................ 74 IECx ............................................................................ 74 IFSx............................................................................. 74 INTCON1 .................................................................... 74 INTCON2 .................................................................... 74 IPCx ............................................................................ 74 Interrupt Setup Procedures ................................................. 96 Initialization ................................................................. 96 Interrupt Disable.......................................................... 96 Interrupt Service Routine ............................................ 96 Trap Service Routine .................................................. 96 Interrupt Vector Table (IVT) ................................................ 71 Interrupts Coincident with Power Save Instructions.......... 110 J JTAG Boundary Scan Interface ........................................ 189 M Memory Organization.......................................................... 29 Microchip Internet Web Site .............................................. 295 Modulo Addressing ............................................................. 47 Applicability ................................................................. 48 Operation Example ..................................................... 47 Start and End Address ................................................ 47 W Address Register Selection .................................... 47 MPLAB ASM30 Assembler, Linker, Librarian ................... 206 MPLAB Integrated Development Environment Software .. 205 MPLAB PM3 Device Programmer..................................... 208 MPLAB REAL ICE In-Circuit Emulator System................. 207 MPLINK Object Linker/MPLIB Object Librarian ................ 206 N NVM Module Register Map............................................................... 44 O Open-Drain Configuration ................................................. 116 Output Compare................................................................ 151 Registers ................................................................... 154 DS70290J-page 292 P Packaging ......................................................................... 267 Details....................................................................... 269 Marking ............................................................. 267, 268 Peripheral Module Disable (PMD) .................................... 110 Pinout I/O Descriptions (table)............................................ 11 PMD Module Register Map .............................................................. 44 PORTA Register Map .............................................................. 43 PORTB Register Map .............................................................. 43 Power-on Reset (POR)....................................................... 67 Power-Saving Features .................................................... 109 Clock Frequency and Switching ............................... 109 Program Address Space..................................................... 29 Construction ............................................................... 50 Data Access from Program Memory Using Program Space Visibility..................................... 53 Data Access from Program Memory Using Table Instructions ............................................... 52 Data Access from, Address Generation ..................... 51 Memory Map............................................................... 29 Table Read Instructions TBLRDH ............................................................. 52 TBLRDL.............................................................. 52 Visibility Operation ...................................................... 53 Program Memory Interrupt Vector ........................................................... 30 Organization ............................................................... 30 Reset Vector ............................................................... 30 R Reader Response............................................................. 296 Registers AD1CHS0 (ADC1 Input Channel 0 Select ................ 185 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 183 AD1CON1 (ADC1 Control 1) .................................... 179 AD1CON2 (ADC1 Control 2) .................................... 181 AD1CON3 (ADC1 Control 3) .................................... 182 AD1CSSL (ADC1 Input Scan Select Low)................ 187 AD1PCFGL (ADC1 Port Configuration Low) ............ 187 CLKDIV (Clock Divisor) ............................................ 103 CORCON (Core Control) ...................................... 23, 75 I2CxCON (I2Cx Control) ........................................... 164 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 168 I2CxSTAT (I2Cx Status) ........................................... 166 ICxCON (Input Capture x Control)............................ 149 IEC0 (Interrupt Enable Control 0) ................... 83, 85, 86 IFS0 (Interrupt Flag Status 0) ..................................... 79 IFS1 (Interrupt Flag Status 1) ..................................... 81 IFS4 (Interrupt Flag Status 4) ..................................... 82 INTCON1 (Interrupt Control 1).................................... 76 INTCON2 (Interrupt Control 2).................................... 78 INTTREG Interrupt Control and Status Register ........ 95 IPC0 (Interrupt Priority Control 0) ............................... 87 IPC1 (Interrupt Priority Control 1) ............................... 88 IPC16 (Interrupt Priority Control 16) ........................... 94 IPC2 (Interrupt Priority Control 2) ............................... 89 IPC3 (Interrupt Priority Control 3) ............................... 90 IPC4 (Interrupt Priority Control 4) ............................... 91 IPC5 (Interrupt Priority Control 5) ............................... 92 IPC7 (Interrupt Priority Control 7) ............................... 93 NVMCOM (Flash Memory Control)....................... 57, 58 OCxCON (Output Compare x Control) ..................... 154 OSCCON (Oscillator Control) ................................... 101 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 OSCTUN (FRC Oscillator Tuning) ............................ 106 PLLFBD (PLL Feedback Divisor).............................. 105 PMD1 (Peripheral Module Disable Control Register 1) ........................................................ 112 PMD2 (Peripheral Module Disable Control Register 2) ........................................................ 113 RCON (Reset Control) ................................................ 63 SPIxCON1 (SPIx Control 1)...................................... 158 SPIxCON2 (SPIx Control 2)...................................... 160 SPIxSTAT (SPIx Status and Control) ....................... 157 SR (CPU Status)................................................... 21, 75 T1CON (Timer1 Control)........................................... 139 TxCON (T2CON, T4CON, T6CON or T8CON Control) ................................................ 144 TyCON (T3CON, T5CON, T7CON or T9CON Control) ................................................ 145 UxMODE (UARTx Mode).......................................... 171 UxSTA (UARTx Status and Control)......................... 173 Reset Illegal Opcode ....................................................... 61, 69 Trap Conflict.......................................................... 68, 69 Uninitialized W Register........................................ 61, 69 Reset Sequence ................................................................. 71 Resets ................................................................................. 61 S Serial Peripheral Interface (SPI) ....................................... 155 Software Reset Instruction (SWR) ...................................... 68 Software Simulator (MPLAB SIM)..................................... 207 Software Stack Pointer, Frame Pointer CALL Stack Frame...................................................... 45 Special Features of the CPU ............................................ 189 SPI Module SPI1 Register Map...................................................... 38 Symbols Used in Opcode Descriptions............................. 198 System Control Register Map............................................................... 44 T Temperature and Voltage Specifications AC ..................................................................... 220, 257 Timer1 ............................................................................... 137 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 141 Timing Characteristics CLKO and I/O ........................................................... 223 Timing Diagrams 10-bit A/D Conversion............................................... 250 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .................................. 250 12-bit A/D Conversion (ASAM = 0, SSRC = 000) ..... 249 Brown-out Situations................................................... 68 © 2007-2011 Microchip Technology Inc. External Clock .......................................................... 221 I2Cx Bus Data (Master Mode) .................................. 242 I2Cx Bus Data (Slave Mode) .................................... 244 I2Cx Bus Start/Stop Bits (Master Mode)................... 242 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 244 Input Capture (CAPx) ............................................... 228 OC/PWM .................................................................. 229 Output Compare (OCx) ............................................ 228 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 224 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 226 Timing Requirements ADC Conversion (10-bit mode) ................................ 262 ADC Conversion (12-bit Mode) ................................ 262 CLKO and I/O ........................................................... 223 External Clock .......................................................... 221 Input Capture............................................................ 228 SPIx Master Mode (CKE = 0) ................................... 258 SPIx Module Master Mode (CKE = 1) ...................... 258 SPIx Module Slave Mode (CKE = 0) ........................ 259 SPIx Module Slave Mode (CKE = 1) ........................ 259 Timing Specifications 10-bit A/D Conversion Requirements ....................... 251 12-bit A/D Conversion Requirements ....................... 249 I2Cx Bus Data Requirements (Master Mode)........... 243 I2Cx Bus Data Requirements (Slave Mode)............. 245 Output Compare Requirements................................ 228 PLL Clock ......................................................... 222, 257 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements......................................... 225 Simple OC/PWM Mode Requirements ..................... 229 Timer1 External Clock Requirements....................... 226 Timer2 External Clock Requirements....................... 227 Timer3 External Clock Requirements....................... 227 U UART Module UART1 Register Map ................................................. 38 Using the RCON Status Bits............................................... 69 V Voltage Regulator (On-Chip) ............................................ 193 W Watchdog Time-out Reset (WDTR).................................... 68 Watchdog Timer (WDT)............................................ 189, 194 Programming Considerations ................................... 194 WWW Address ................................................................. 295 WWW, On-Line Support ....................................................... 7 DS70290J-page 293 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 NOTES: DS70290J-page 294 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2007-2011 Microchip Technology Inc. DS70290J-page 295 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Literature Number: DS70290J Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70290J-page 296 © 2007-2011 Microchip Technology Inc. dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 GP2 02 T E / SP - XXX Examples: a) Microchip Trademark Architecture dsPIC33FJ32GP202-E/SP: General-purpose dsPIC33, 32-Kbyte program memory, 28-pin, Extended temp., SPDIP package. Flash Memory Family Program Memory Size (Kbyte) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: GP2 GP3 = = General purpose family General purpose family Pin Count: 02 03 = = 28-pin 44-pin Temperature Range: I E H = = = -40° C to +85° C (Industrial) -40° C to +125° C (Extended) -40° C to +150° C (High) Package: SP SO SS ML PT MM = = = = = = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) Plastic Small Outline - Wide - 7.5 mm body (SOIC) Plastic Shrink Small Outline - 5.3 mm body (SSOP) Plastic Quad, No Lead Package - 8x8 mm body (QFN) Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP) Plastic Quad, No Lead Package - 6x6 mm body (QFN-S) © 2007-2011 Microchip Technology Inc. DS70290J-page 297 dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 NOTES: DS70290J-page 298 © 2007-2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-334-6 QUALITY MANAGEMENT  SYSTEM  CERTIFIED BY DNV  == ISO/TS 16949 ==  © 2007-2011 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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