DSPIC33FJ16MC304-H/PT

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 16-bit Digital Signal Controllers (up to 32 KB Flash and 2 KB SRAM) with Motor Control and Advanced Analog Operating Conditions • Six analog inputs on 28-pin devices and up to nine analog inputs on 44-pin devices • Flexible and independent ADC trigger sources • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS Timers/Output Compare/Input Capture Core: 16-bit dsPIC33F CPU • • • • • Three 16-bit timers/counters. Can pair up two to make one 32-bit. • Two Output Capture modules configurable as timers/counters • Four Input Capture modules • Peripheral Pin Select (PPS) to allow function remap Code-efficient (C and Assembly) architecture Two 40-bit wide accumulators Single-cycle (MAC/MPY) with dual data fetch Single-cycle mixed-sign MUL plus hardware divide Clock Management • • • • • 2% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer (WDT) Fast wake-up and start-up Communication Interfaces • • • • One UART module (10 Mbps) With support for LIN 2.0 protocols and IrDA® One 4-wire SPI module (15 Mbps) One I2C™ module (up to 1 Mbaud) with SMBus support • PPS to allow function remap Power Management • • • • Low-power management modes (Sleep, Idle, Doze) Integrated Power-on Reset and Brown-out Reset 1.35 mA/MHz dynamic current (typical) 55 μA IPD current (typical) Input/Output • Sink/Source up to 10 mA (pin specific) for standard VOH/VOL, up to 16 mA (pin specific) for non-standard VOH1 • 5V-tolerant pins • Selectable open drain, pull-ups, and pull-downs • Up to 5 mA overvoltage clamp current • External interrupts on all I/O pins High-Speed PWM • • • • Up to four PWM pairs with independent timing Dead time for rising and falling edges 12.5 ns PWM resolution PWM support for: - DC/DC, AC/DC, Inverters, PFC, Lighting - BLDC, PMSM, ACIM, SRM • Programmable Fault inputs • Flexible trigger configurations for ADC conversions Qualification and Class B Support • AEC-Q100 REVG (Grade 0 -40ºC to +150ºC) • Class B Safety Library, IEC 60730 Debugger Development Support Advanced Analog Features • • • • • ADC module: - Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H In-circuit and in-application programming Two program and two complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Trace and run-time watch Packages Type SPDIP SOIC Pin Count 28 28 Contact Lead/Pitch .100'' 1.27 I/O Pins 21 21 Dimensions 1.365x.285x.135'' 17.9xx7.50x2.05 Note: All dimensions are in millimeters (mm) unless specified. © 2007-2012 Microchip Technology Inc. SSOP QFN-S QFN TQFP 28 0.65 21 10.2x5.3x1.75 28 0.65 21 6x6x0.9 44 0.65 35 8x8x0.9 44 0.80 35 10x10x1 DS70283K-page 1 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. Device Pins RAM (Kbyte) Remappable Pins 16-bit Timer Input Capture Output Compare Standard PWM Motor Control PWM Quadrature Encoder Interface UART External Interrupts(3) SPI dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CONTROLLER FAMILIES Program Flash Memory (Kbyte) TABLE 1: dsPIC33FJ32MC202 28 32 2 16 3(1) 4 2 6ch(2) 2ch(2) 1 1 3 1 1ADC, 6 ch 1 21 SPDIP SOIC SSOP QFN-S dsPIC33FJ32MC204 44 32 2 26 3(1) 4 2 6ch(2) 2ch(2) 1 1 3 1 1ADC, 9 ch 1 35 QFN TQFP dsPIC33FJ16MC304 44 16 2 26 3(1) 4 2 6ch(2) 2ch(2) 1 1 3 1 1ADC, 9 ch 1 35 QFN TQFP Note 1: 2: 3: Packages I/O Pins I2C™ 10-Bit/12-Bit ADC Remappable Peripherals Only two out of three timers are remappable. Only PWM fault inputs are remappable. Only two out of three interrupts are remappable. DS70283K-page 2 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams 28-PIN SPDIP, SOIC, SSOP = Pins are up to 5V tolerant 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ32MC202 MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4(1)/CN1/RB4 SOSCO/T1CK/CN0/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/RB5 28 27 26 25 24 AVDD AVSS PWM1L1/RP15(1)/CN11/RB15 PWM1H1/RP14(1)/CN12/RB14 PWM1L2/RP13(1)/CN13/RB13 PWM1H2/RP12(1)/CN14/RB12 PGEC2/TMS/PWM1L3/RP11(1)/CN15/RB11 PGED2/TDI/PWM1H3/RP10(1)/CN16/RB10 VCAP VSS TDO/PWM2L1/SDA1/RP9(1)/CN21/RB9 TCK/PWM2H1/SCL1/RP8(1)/CN22/RB8 INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6(1)/CN24/RB6 23 22 21 20 19 18 17 16 15 28-Pin QFN-S(2) PWM1H1/RP14(1)/CN12/RB14 AVDD AVSS PWM1L1/RP15(1)/CN11/RB15 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR = Pins are up to 5V tolerant 28 27 26 25 24 23 22 PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1 1 21 PWM1L2/RP13(1)/CN13/RB13 AN4/RP2(1)/CN6/RB2 2 3 PGEC2/EMUC2/TMS/PWM1L3/RP11(1)/CN15/RB11 AN5/RP3(1)/CN7/RB3 VSS 20 19 4 dsPIC33FJ32MC202 18 5 OSC1/CLKI/CN30/RA2 6 OSC2/CLKO/CN29/RA3 7 17 VCAP 16 VSS 15 TDO/PWM2L1/SDA1/RP9(1)/CN21/RB9 TCK/PWM2H1/SCL1/RP8(1)/CN22/RB8 PGEC3/EMUC3/ASCL1/RP6(1)/CN24/RB6 INT0/RP7(1)/CN23/RB7 PGED3/EMUD3/ASDA1/RP5(1)/CN27/RB5 SOSCI/RP4/CN1/RB4 PGED2/EMUD2/TDI/PWM1H3/RP10(1)/CN16/RB10 9 10 11 12 13 14 SOSCO/T1CK/CN0/RA4 VDD 8 PWM1H2/RP12(1)/CN14/RB12 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2007-2012 Microchip Technology Inc. DS70283K-page 3 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams (Continued) 44-Pin QFN(2) TMS/RA10 TCK/RA7 PWM1H1/RP14(1)/CN12/RB14 PWM1L1/RP15(1)/CN11/RB15 AVSS MCLR AVDD AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1 = Pins are up to 5V tolerant 22 21 20 19 18 17 16 15 14 13 12 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/RP18(1)/CN10/RC2 11 24 10 25 9 26 8 PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10 7 VCAP 6 VSS 5 RP25/CN19/RC9 RP24/CN20/RC8 27 dsPIC33FJ32MC204 dsPIC33FJ16MC304 VDD 28 VSS 29 OSC1/CLKI/CN30/RA2 30 4 OSC2/CLKO/CN29/RA3 31 3 TDO/RA8 32 2 33 1 SOSCI/RP4(1)/CN1/RB4 PWM1L2/RP13(1)/CN13/RB13 23 PWM1H2/RP12(1)/CN14/RB12 PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11 PWM2L1/RP23(1)/CN17/RC7 PWM2H1/RP22(1)/CN18/RC6 SDA1/RP9(1)/CN21/RB9 INT0/RP7/CN23/RB7 SCL1/RP8(1)/CN22/RB8 PGEC3/EMUC3/ASCL1/RP6 /CN24/RB6 (1) VDD PGED3/EMUD3/ASDA1/RP5(1)/CN27/RB5 VSS RP21(1)/CN26/RC5 RP20(1)/CN25/RC4 RP19(1)/CN28/RC3 TDI/RA9 SOSCO/T1CK/CN0/RA4 34 35 36 37 38 39 40 41 42 43 44 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS70283K-page 4 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Pin Diagrams (Continued) 44-Pin TQFP PGEC1/EMUC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/EMUD1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS PWM1L1/RP15(1)/CN11/RB15 PWM1H1/RP14(1)/CN12/RB14 TCK/RA7 TMS/RA10 = Pins are up to 5V tolerant 12 13 14 15 16 17 18 19 20 21 22 11 10 9 8 7 6 5 4 3 2 1 PWM1L2/RP13(1)/CN13/RB13 PWM1H2/RP12(1)/CN14/RB12 PGEC2/EMUC2/PWM1L3/RP11(1)/CN15/RB11 PGED2/EMUD2/PWM1H3/RP10(1)/CN16/RB10 VCAP VSS RP25(1)/CN19/RC9 RP24(1)/CN20/RC8 PWM2L1/RP23(1)/CN17/RC7 PWM2H1/RP22(1)/CN18/RC6 SDA1/RP9(1)/CN21/RB9 38 39 40 41 42 43 44 dsPIC33FJ32MC204 dsPIC33FJ16MC304 34 35 36 37 23 24 25 26 27 28 29 30 31 32 33 SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19/(1)CN28/RC3 RP20(1)/CN25/RC4 RP21(1)/CN26/RC5 VSS VDD PGED3/EMUD3/ASDA1/RP5(1)/CN27/RB5 PGEC3/EMUC3/ASCL1/RP6(1)/CN24/RB6 INT0/RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/RP18(1)/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4(1)/CN1/RB4 Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. © 2007-2012 Microchip Technology Inc. DS70283K-page 5 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Table of Contents dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Product Families.................................................................................................. 2 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 13 3.0 CPU............................................................................................................................................................................................ 17 4.0 Memory Organization ................................................................................................................................................................. 29 5.0 Flash Program Memory .............................................................................................................................................................. 55 6.0 Resets ....................................................................................................................................................................................... 61 7.0 Interrupt Controller ..................................................................................................................................................................... 71 8.0 Oscillator Configuration ............................................................................................................................................................ 101 9.0 Power-Saving Features............................................................................................................................................................ 111 10.0 I/O Ports ................................................................................................................................................................................... 117 11.0 Timer1 ...................................................................................................................................................................................... 143 12.0 Timer2/3 feature ...................................................................................................................................................................... 147 13.0 Input Capture............................................................................................................................................................................ 151 14.0 Output Compare....................................................................................................................................................................... 155 15.0 Motor Control PWM Module ..................................................................................................................................................... 159 16.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 173 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 179 18.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 185 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 193 20.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 199 21.0 Special Features ...................................................................................................................................................................... 211 22.0 Instruction Set Summary .......................................................................................................................................................... 219 23.0 Development Support............................................................................................................................................................... 227 24.0 Electrical Characteristics .......................................................................................................................................................... 231 25.0 High Temperature Electrical Characteristics ............................................................................................................................ 281 26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 291 27.0 Packaging Information.............................................................................................................................................................. 295 Appendix A: Revision History............................................................................................................................................................. 309 Index ................................................................................................................................................................................................. 321 The Microchip Web Site ..................................................................................................................................................................... 325 Customer Change Notification Service .............................................................................................................................................. 325 Customer Support .............................................................................................................................................................................. 325 Reader Response .............................................................................................................................................................................. 326 Product Identification System............................................................................................................................................................. 327 DS70283K-page 6 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products © 2007-2012 Microchip Technology Inc. DS70283K-page 7 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the dsPIC33FJ32MC204 product page of the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • • • • • • • • • • • • • • • • • • • • • Section 1. “Introduction” (DS70197) Section 2. “CPU” (DS70204) Section 3. “Data Memory” (DS70202) Section 4. “Program Memory” (DS70202) Section 5. “Flash Programming” (DS70191) Section 7. “Oscillator” (DS70186) Section 8. “Reset” (DS70192) Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) Section 10. “I/O Ports” (DS70193) Section 11. “Timers” (DS70205) Section 12. “Input Capture” (DS70198) Section 13. “Output Compare” (DS70209) Section 14. “Motor Control PWM” (DS70187) Section 15. “Quadrature Encoder Interface (QEI)” (DS70208) Section 16. “Analog-to-Digital Converter (ADC)” (DS70183) Section 17. “UART” (DS70188) Section 18. “Serial Peripheral Interface (SPI)” (DS70206) Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195) Section 23. “CodeGuard™ Security” (DS70199) Section 25. “Device Configuration” (DS70194) Section 32. “Interrupts (Part III)” (DS70214) DS70283K-page 8 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This document contains device-specific information for the following Digital Signal Controller (DSC) devices: • dsPIC33FJ32MC202 • dsPIC33FJ32MC204 • dsPIC33FJ16MC304 The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007-2012 Microchip Technology Inc. DS70283K-page 9 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 1-1: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB 16 23 16 16 PORTC Address Generator Units Address Latch Program Memory Remappable EA MUX Data Latch ROM Latch 24 FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator VCAP Divide Support 16 x 16 W Register Array 16 Oscillator Start-up Timer Power-on Reset 16-bit ALU Watchdog Timer 16 Brown-out Reset MCLR UART1 IC1,2,7,8 Note: 16 DSP Engine Power-up Timer VDD, VSS Timers 1-3 Literal Data Instruction Reg Control Signals to Various Blocks Timing Generation 16 16 Instruction Decode and Control OSC2/CLKO OSC1/CLKI Pins SPI1 ADC1 OC/ PWM1-2 PWM 2 Ch CNx I2C1 QEI PWM 6 Ch Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features present on each device. DS70283K-page 10 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Description AN0-AN8 I Analog No Analog input channels. CLKI CLKO I O ST/CMOS — No No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 I ST/CMOS No OSC2 I/O — No Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI SOSCO I O ST/CMOS — No No 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. CN0-CN30 I ST No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. IC1-IC2 IC7-IC8 I I ST ST Yes Yes Capture inputs 1/2. Capture inputs 7/8. OCFA OC1-OC2 I O ST — Yes Yes Compare Fault A input (for Compare Channels 1 and 2). Compare outputs 1 through 2. INT0 INT1 INT2 I I I ST ST ST No Yes Yes External interrupt 0. External interrupt 1. External interrupt 2. RA0-RA4 RA7-RA10 I/O ST No No PORTA is a bidirectional I/O port. RB0-RB15 I/O ST No PORTB is a bidirectional I/O port. RC0-RC9 I/O ST No PORTC is a bidirectional I/O port. T1CK T2CK T3CK I I I ST ST ST No Yes Yes Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. U1CTS U1RTS U1RX U1TX I O I O ST — ST — Yes Yes Yes Yes UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. SCK1 SDI1 SDO1 SS1 I/O I O I/O ST ST — ST Yes Yes Yes Yes Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. SCL1 SDA1 ASCL1 ASDA1 I/O I/O I/O I/O ST ST ST ST No No No No Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. TMS TCK TDI TDO I I I O ST ST ST — No No No No JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select © 2007-2012 Microchip Technology Inc. Analog = Analog input; O = Output; P = Power I = Input DS70283K-page 11 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS INDX QEA I I ST ST Yes Yes QEB I ST Yes UPDN O CMOS Yes Quadrature Encoder Index Pulse input. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Quadrature Encoder Phase A input in QEI mode. Auxiliary Timer External Clock/Gate input in Timer mode. Position Up/Down Counter Direction State. FLTA1 PWM1L1 PWM1H1 PWM1L2 PWM1H2 PWM1L3 PWM1H3 FLTA2 PWM2L1 PWM2H1 I O O O O O O I O O ST — — — — — — ST — — Yes No No No No No No Yes No No PWM1 Fault A input. PWM1 Low output 1. PWM1 High output 1. PWM1 Low output 2. PWM1 High output 2. PWM1 Low output 3. PWM1 High output 3. PWM2 Fault A input. PWM2 Low output 1. PWM2 High output 1. PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 I/O I I/O I I/O I ST ST ST ST ST ST No No No No No No Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device. Pin Name Description AVDD P P No Positive supply for analog modules. This pin must be connected at all times. AVSS P P No Ground reference for analog modules. VDD P — No Positive supply for peripheral logic and I/O pins. VCAP P — No CPU logic filter capacitor connection. VSS P — No Ground reference for logic and I/O pins. VREF+ I Analog No Analog voltage reference (high) input. VREF- I Analog No Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; PPS = Peripheral Pin Select DS70283K-page 12 Analog = Analog input; O = Output; P = Power I = Input © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 family of 16-bit Digital Signal Controllers (DSCs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (even if the ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP (see Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have a resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2007-2012 Microchip Technology Inc. DS70283K-page 13 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD • Device Reset • Device programming and debugging C dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) Note 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1Ω and the inductor capacity greater than 10 mA. Where: CNV ------------f = F 2 1 f = ---------------------( 2π LC ) Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: MCLR 0.1 µF Ceramic The placement of this capacitor should be close to the VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 21.2 “On-Chip Voltage Regulator” for details. (i.e., ADC conversion rate/2) During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that capacitor C is isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: VDD 2 1 L = ⎛ ---------------------⎞ ⎝ ( 2πf C )⎠ 2.2.1 R(1) TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including DSCs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. 2.3 EXAMPLE OF MCLR PIN CONNECTIONS CPU Logic Filter Capacitor Connection (VCAP) JP R1(2) MCLR dsPIC33F C Note 1: R ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R1 ≤ 470W will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. A low-ESR (4)16@ ZLWKPP&RQWDFW/HQJWK 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS70283K-page 304 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Width E Exposed Pad Width E2 Overall Length D Exposed Pad Length D2 6.30 6.45 6.80 b 0.25 0.30 0.38 Contact Length L 0.30 0.40 0.50 Contact-to-Exposed Pad K 0.20 – – Contact Width 8.00 BSC 6.30 6.45 6.80 8.00 BSC Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103B © 2007-2012 Microchip Technology Inc. DS70283K-page 305 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 /HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS70283K-page 306 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.15 Foot Length L 0.45 0.60 0.75 Footprint L1 1.20 1.00 REF Foot Angle φ Overall Width E 12.00 BSC Overall Length D 12.00 BSC Molded Package Width E1 10.00 BSC Molded Package Length D1 10.00 BSC 0° 3.5° 7° Lead Thickness c 0.09 – 0.20 Lead Width b 0.30 0.37 0.45 Mold Draft Angle Top α 11° 12° 13° Mold Draft Angle Bottom β 11° 12° 13° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B © 2007-2012 Microchip Technology Inc. DS70283K-page 307 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70283K-page 308 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 APPENDIX A: REVISION HISTORY Revision A (February 2007) This is the initial released version of the document. Revision B (May 2007) This revision includes the following corrections and updates: • Minor typographical and formatting corrections throughout the data sheet text. • New content: - Addition of bullet item (16-word conversion result buffer) (see Section 20.1 “Key Features”) • Updated register map information for RPINR14 and RPINR15 (see Table 4-16) • Figure updates: - Updated Oscillator System Diagram (see Figure 8-1) - Updated WDT Block Diagram (see Figure 21-2) • Equation update: - Serial Clock Rate (see Equation 17-1) • Register updates: - Peripheral Pin Select Input Registers (see Register 10-1 through Register 10-13) - Updated ADC1 Input Channel 0 Select register (see Register 20-5) © 2007-2012 Microchip Technology Inc. • The following tables in Section 24.0 “Electrical Characteristics” have been updated with preliminary values: - Updated Max MIPS for -40°C to +125°C Temp Range (see Table 24-1) - Updated parameter DC18 (see Table 24-4) - Added new parameters for +125°C, and updated Typical and Max values for most parameters (see Table 24-5) - Added new parameters for +125°C, and updated Typical and Max values for most parameters (see Table 24-6) - Added new parameters for +125°C, and updated Typical and Max values for most parameters (see Table 24-7) - Added new parameters for +125°C, and updated Typical and Max values for most parameters (see Table 24-8) - Updated parameter DI51, added parameters DI51a, DI51b, and DI51c (see Table 24-9) - Added Note 1 (see Table 24-11) - Updated parameters OS10 and OS30 (see Table 24-16) - Updated parameter OS52 (see Table 24-17) - Updated parameter F20, added Note 2 (see Table 24-18) - Updated parameter F21 (see Table 24-19) - Updated parameter TA15 (see Table 24-22) - Updated parameter TB15 (see Table 24-23) - Updated parameter TC15 (see Table 24-24) - Updated parameter IC15 (see Table 24-26) - Updated parameters AD05, AD06, AD07, AD08, AD10 through AD13 and AD17; added parameters AD05a and AD06a; added Note 2; modified ADC Accuracy headings to include measurement information (see Table 24-38) - Separated the ADC Module Specifications table into three tables (see Table 24-38, Table 24-39, and Table 24-40) - Updated parameter AD50 (see Table 24-41) - Updated parameters AD50 and AD57 (see Table 24-42) DS70283K-page 309 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision C (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name “High-Performance, 16-bit Digital Signal Controllers” Update Description Added Extended Interrupts column to Remappable Peripherals in the Controller Families table and Note 3 (see Table 1). Added Note 1 to all pin diagrams, which references RPn pin usage by remappable peripherals (see “Pin Diagrams”). Section 1.0 “Device Overview” Changed PORTA pin name from RA15 to RA10 (see Table 1-1). Section 4.0 “Memory Organization” Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and ACCBU) to the CPU Core Register Map (see Table 4-1). Updated Reset value for CORCON (see Table 4-1). Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7, IPC16, and INTTREG (see Table 4-4). Updated all SFR names in QEI1 Register Map (see Table 4-10). Updated the bit range for AD1CON3 from ADCS to ADCS) (see Table 4-14 and Table 4-15). Updated the Reset value for CLKDIV in the System Control Register Map (see Table 4-23). Section 6.0 “Resets” Entire section was replaced to maintain consistency with other dsPIC33F data sheets. Section 8.0 “Oscillator Configuration” Removed the first sentence of the third clock source item (External Clock) in Section 8.1.1.2 “Primary”. Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register 8-2). Added the center frequency in the OSCTUN register for the FRC Tuning bits (TUN) value 011111 and updated the center frequency for bits value 011110 (see Register 8-4). Section 9.0 “Power-Saving Features” Added the following two registers: Section 10.0 “I/O Ports” Added paragraph and Table 10-1 to Section 10.2 “Open-Drain Configuration”, which provides details on I/O pins and their functionality. • PMD1: Peripheral Module Disable Control Register 1 • PMD2: Peripheral Module Disable Control Register 2 • PMD3: Peripheral Module Disable Control Register 3 Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 9.4.2 “Available Peripherals” • 9.4.3.3 “Mapping” • 9.4.5 “Considerations for Peripheral Pin Selection” Section 14.0 “Output Compare” DS70283K-page 310 Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with entirely new content. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 15.0 “Motor Control PWM Module” Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • • • • • • • • • • • • • • • • Section 16.0 “Quadrature Encoder Interface (QEI) Module” Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • • • • • • • • Section 17.0 “Serial Peripheral Interface (SPI)” 15.1 “Quadrature Encoder Interface Logic” 15.2 “16-bit Up/Down Position Counter Mode” 15.3 “Position Measurement Mode” 15.4 “Programmable Digital Noise Filters” 15.5 “Alternate 16-bit Timer/Counter” 15.6 QEI Module Operation During CPU Sleep Mode” 15.7 “QEI Module Operation During CPU Idle Mode” 15.8 “Quadrature Encoder Interface Interrupts” Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • • • • © 2007-2012 Microchip Technology Inc. 14.3 “PWM Time Base” 14.4 “PWM Period” 14.5 “Edge-Aligned PWM” 14.6 “Center-Aligned PWM” 14.7 “PWM Duty Cycle Comparison Units” 14.8 “Complementary PWM Operation” 14.9 “Dead-Time Generators” 14.10 “Independent PWM Output” 14.11 “Single Pulse PWM Operation” 14.12 “PWM Output Override” 14.13 “PWM Output and Polarity Control” 14.14 “PWM Fault Pins” 14.15 “PWM Update Lockout” 14.16 “PWM Special Event Trigger” 14.17 “PWM Operation During CPU Sleep Mode” 14.18 “PWM Operation During CPU Idle Mode” 16.1 “Interrupts” 16.2 “Receive Operations” 16.3 “Transmit Operations” 16.4 “SPI Setup” (retained Figure 17-1: SPI Module Block Diagram) DS70283K-page 311 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 18.0 “Inter-Integrated Circuit™ (I2C™)” Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • • • • • • • • • • • • 17.3 “I2C Interrupts” 17.4 “Baud Rate Generator” (retained Figure 15-1: I2C Block Diagram) 17.5 “I2C Module Addresses” 17.6 “Slave Address Masking” 17.7 “IPMI Support” 17.8 “General Call Address Support” 17.9 “Automatic Clock Stretch” 17.10 “Software Controlled Clock Stretching (STREN = 1)” 17.11 “Slope Control” 17.12 “Clock Arbitration” 17.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration” 17.14 “Peripheral Pin Select Limitations” Section 19.0 “Universal Removed the following sections, which are now available in the related Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual: (UART)” • 18.1 “UART Baud Rate Generator” • 18.2 “Transmitting in 8-bit Data Mode” • 18.3 “Transmitting in 9-bit Data Mode” • 18.4 “Break and Sync Transmit Sequence” • 18.5 “Receiving in 8-bit or 9-bit Data Mode” • 18.6 “Flow Control Using UxCTS and UxRTS Pins” • 18.7 “Infrared Support” Removed IrDA references and Note 1, and updated the bit and bit value descriptions for UTXINV (UxSTA) in the UARTx Status and Control Register (see Register 19-2). Section 20.0 “10-bit/12-bit Analog-to-Digital Converter (ADC)” Removed Equation 19-1: ADC Conversion Clock Period and Figure 19-2: ADC Transfer Function (10-Bit Example). Added ADC1 Module Block Diagram for dsPIC33FJ16MC304 and dsPIC33FJ32MC204 Devices (Figure 20-1) and ADC1 Module Block Diagram FOR dsPIC33FJ32MC202 Devices (Figure 20-2). Added Note 2 to Figure 20-3: ADC Conversion Clock Period Block Diagram. Updated ADC Conversion Clock Select bits in the AD1CON3 register from ADCS to ADCS. Any references to these bits have also been updated throughout this data sheet (Register 20-3). Added device-specific information to Note 1 in the ADC1 Input Scan Select Register Low (see Register 20-6), and updated the default bit value for bits 12-10 (CSS12-CSS10) from U-0 to R/W-0. Added device-specific information to Note 1 in the ADC1 Port Configuration Register Low (see Register 20-7), and updated the default bit value for bits 12-10 (PCFG12-PCFG10) from U-0 to R/W-0. DS70283K-page 312 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 21.0 “Special Features” Update Description Added FICD register information for address 0xF8000E in the Device Configuration Register Map (see Table 21-1). Added FICD register content (BKBUG, COE, JTAGEN, and ICS to the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Configuration Bits Description (see Table 21-2). Added a note regarding the placement of low-ESR capacitors, after the second paragraph of Section 21.2 “On-Chip Voltage Regulator” and to Figure 19-1. Removed the words “if enabled” from the second sentence in the fifth paragraph of Section 21.3 “BOR: Brown-out Reset”. Section 24.0 “Electrical Characteristics” Updated Max MIPS value for -40ºC to +125ºC temperature range in Operating MIPS vs. Voltage (see Table 24-1). Removed Typ value for parameter DC12 (see Table 24-4). Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f and DC72g (see Table 24-5, Table 24-6, and Table 24-8). Added Note 4 (reference to new table containing digital-only and analog pin information to I/O Pin Input Specifications (see Table 24-4). Updated Typ, Min and Max values for Program Memory parameters D136, D137 and D138 (see Table 24-12). Updated Max value for Internal RC Accuracy parameter F21 for -40°C ≤TA ≤ +125°C condition and added Note 2 (see Table 24-19). Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and Power-up Timer parameter SY20 and updated conditions, which now refers to Section 21.4 “Watchdog Timer (WDT)” and LPRC parameter F21a (see Table 24-21). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table 24-41). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table 24-42). © 2007-2012 Microchip Technology Inc. DS70283K-page 313 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision D (December 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Diagrams”). Section 2.0 “Guidelines for Getting Started with 16-bit Digital Signal Controllers” Added new section to the data sheet that provides guidelines on getting started with 16-bit Digital Signal Controllers. Section 10.0 “I/O Ports” Updated 5V tolerant status for I/O pin RB4 from Yes to No (see Table 10-1). Section 24.0 “Electrical Characteristics” Removed the maximum value for parameter DC12 (RAM Data Retention Voltage) in Table 24-4. Updated typical values for Operating Current (IDD) and added Note 3 in Table 24-5. Updated typical and maximum values for Idle Current (IIDLE): Core OFF Clock ON Base Current and added Note 3 in Table 24-6. Updated typical and maximum values for Power Down Current (IPD) and added Note 5 in Table 24-7. Updated typical and maximum values for Doze Current (IDOZE) and added Note 2 in Table 24-8. Added Note 3 to Table 24-12. Updated minimum value for Internal Voltage Regulator Specifications in Table 24-13. Added parameter OS42 (GM) and Notes 4, 5 and 6 to Table 24-16. Added Notes 2 and 3 to Table 24-17. Added Note 2 to Table 24-20. Added Note 2 to Table 24-21. Added Note 2 to Table 24-22. Added Note 1 to Table 24-23. Added Note 1 to Table 24-24. Added Note 3 to Table 24-36. Added Note 2 to Table 24-37. Updated typical value for parameter AD08 (ADC in operation) and added Notes 2 and 3 in Table 24-38. Updated minimum, typical, and maximum values for parameters AD23a, AD24a, AD30a, AD32a, AD32a and AD34a, and added Notes 2 and 3 in Table 24-39. Updated minimum, typical, and maximum values for parameters AD23b, AD24b, AD30b, AD32b, AD32b and AD34b, and added Notes 2 and 3 in Table 24-40. DS70283K-page 314 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision E (June 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2 or 3) to PGECx and PGEDx Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE All other major changes are referenced by their respective section in the following table. TABLE A-3: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Section 7.0 “Interrupt Controller” Updated addresses for interrupt vectors 80, 81, 82 and 83-125 (see Table 7-1). Section 8.0 “Oscillator Configuration” Updated the Oscillator System Diagram (see Figure 8-1). Added Note 1 to the Oscillator Tuning register (OSCTUN) (see Register 8-4). Section 10.0 “I/O Ports” Removed Table 10-1 and added reference to pin diagrams for I/O pin availability and functionality. Section 17.0 “Serial Peripheral Interface (SPI)” Added Note 2 to the SPIx Control Register 1 (see Register 17-2). Section 19.0 “Universal Asynchronous Receiver Transmitter (UART)” Updated the UTXINV bit settings in the UxSTA register and added Note 1 (see Register 19-2). Section 24.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage) and added Note 4 to the DC Temperature and Voltage Specifications (see Table 24-4). Updated the Min value for parameter DI35 (see Table 24-20). Updated AD08 and added reference to Note 2 for parameters AD05a, AD06a and AD08a (see Table 24-38). © 2007-2012 Microchip Technology Inc. DS70283K-page 315 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision F (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-4: MAJOR SECTION UPDATES Section Name Update Description “High-Performance, 16-bit Digital Signal Controllers” Added information on high temperature operation (see “Operating Range:”). Section 10.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section 10.2 “Open-Drain Configuration”. Section 19.0 “Universal Asynchronous Receiver Transmitter (UART)” Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 MIPS. Section 20.0 “10-bit/12-bit Analog-to-Digital Converter (ADC)” Updated the ADC1 block diagrams (see Figure 20-1 and Figure 20-2). Section 21.0 “Special Features” Updated the second paragraph and removed the fourth paragraph in Section 21.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table 21-1). Section 24.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure 24-17). Updated the Internal RC Accuracy parameter numbers (see Table 24-18 and Table 24-19). Section 25.0 “High Temperature Electrical Characteristics” Added new chapter with high temperature specifications. “Product Identification System” Added the “H” definition for high temperature. Revision G (November 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-5: MAJOR SECTION UPDATES Section Name Section 25.0 “High Temperature Electrical Characteristics” DS70283K-page 316 Update Description Updated MIPS rating from 16 to 20 for high temperature devices in “Operating Range:” and in Table 25-1: Operating MIPS vs. Voltage. © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision H (February 2011) This revision includes typographical and formatting changes throughout the data sheet text. In addition, all instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table. TABLE A-6: MAJOR SECTION UPDATES Section Name Update Description High-Performance, 16-bit Digital Signal Controllers Added the SSOP package information (see “Packaging:”, Table 1, and “Pin Diagrams”). Section 2.0 “Guidelines for Getting Started with 16-bit Digital Signal Controllers” Updated the title of Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”. The frequency limitation for device PLL start-up conditions was updated in Section 2.7 “Oscillator Value Conditions on Device Start-up”. The second paragraph in Section 2.9 “Unused I/Os” was updated. Section 3.0 “CPU” Removed references to DMA in the CPU Core Block Diagram (see Figure 3-1). Section 4.0 “Memory Organization” Updated the data memory reference in the third paragraph in Section 4.2 “Data Address Space”. All Resets values for the following SFRs in the Timer Register Map were changed (see Table 4-5): • TMR1 • TMR2 • TMR3 Section 8.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see Register 8-1). Added Note 2 to the CLKDIV: Clock Divisor Register (see Register 8-2). Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see Register 8-3). Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see Register 8-4). Section 20.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams Converter (ADC)” (see Figure 20-1 and Figure 20-2). Section 21.0 “Special Features” Added a new paragraph and removed the third paragraph in Section 21.1 “Configuration Bits”. Added the column “RTSP Effects” to the Configuration Bits Descriptions (see Table 21-2). © 2007-2012 Microchip Technology Inc. DS70283K-page 317 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 TABLE A-6: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Added the 28-pin SSOP Thermal Packaging Characteristics (see Table 24-3). Removed Note 4 from the DC Temperature and Voltage Specifications (see Table 24-4). Updated the maximum value for parameter DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table 24-9). Updated Note 3 of the PLL Clock Timing Specifications (see Table 24-17). Removed Note 2 from the AC Characteristics: Internal RC Accuracy (see Table 24-18). Updated the characteristic description for parameter DI35 in the I/O Timing Requirements (see Table 24-20). Updated all SPI specifications (see Table 24-32 through Table 24-39 and Figure 24-14 through Figure 24-21). Added Note 4 to the 12-bit mode ADC Module Specifications (see Table 24-43). Added Note 4 to the 10-bit mode ADC Module Specifications (see Table 24-44). Section 25.0 “High Temperature Electrical Characteristics” Updated all ambient temperature and range values to +150ºC throughout the chapter. Updated the storage temperature and range to +160ºC. Updated the maximum junction temperature from +145ºC to +155ºC. Updated Note 1 in the PLL Clock Timing Specifications (see Table 25-10). Added Note 3 to the 12-bit Mode ADC Module Specifications (see Table 25-17). Added Note 3 to the 10-bit Mode ADC Module Specifications (see Table 25-18). Section 26.0 “Packaging Information” Added the 28-Lead SSOP package information (see Section 26.1 “Package Marking Information” and Section 26.2 “Package Details”). “Product Identification System” Added the “SS” definition for the SSOP package. DS70283K-page 318 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Revision J (July 2011) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-7: MAJOR SECTION UPDATES Section Name Update Description Section 21.0 “Special Features” Added Note 3 to the Connections for the On-chip Voltage Regulator diagram (see Figure 21-1). Section 24.0 “Electrical Characteristics” Removed Note 3 and parameter DC10 (VCORE) from the DC Temperature and Voltage Specifications (see Table 24-4). Updated the Characteristics definition and Conditions for parameter BO10 in the Electrical Characteristics: BOR (see Table 24-11). Added Note 1 to the Internal Voltage Regulator Specifications (see Table 24-13). Revision K (June 2012) This revision includes typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-8: MAJOR SECTION UPDATES Section Name Update Description Section 24.0 “Electrical Characteristics” Added Note 1 to the Operating MIPS vs. Voltage (see Table 24-1). Updated the notes in the following tables: • Operating Current (IDD) (see Table 24-5) • Idle Current (IIDLE) (see Table 24-6) • Power-Down Current (IPD) (see Table 24-7) • Doze Current (IDOZE) (see Table 24-8) Updated the conditions for Program Memory parameters D136b, D137b, and D138b (TA = +150ºC) (see Table 24-12). Section 25.0 “High Temperature Electrical Characteristics” Removed Table 23-8: DC Characteristics: Program Memory. Section 26.0 “DC and AC Device Characteristics Graphs” Added new chapter. © 2007-2012 Microchip Technology Inc. DS70283K-page 319 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 320 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 INDEX A AC Characteristics .................................................... 244, 285 ADC Module.............................................................. 288 ADC Module (10-bit Mode) ....................................... 289 ADC Module (12-bit Mode) ....................................... 288 Internal RC Accuracy ................................................ 246 Load Conditions ................................................ 244, 285 ADC Initialization ............................................................... 199 Key Features............................................................. 199 ADC Module ADC1 Register Map for dsPIC33FJ32MC202 ............ 40 ADC1 Register Map for dsPIC33FJ32MC204 and dsPIC33FJ16MC304 .......................................... 41 Alternate Interrupt Vector Table (AIVT) .............................. 71 Analog-to-Digital Converter (ADC).................................... 199 Arithmetic Logic Unit (ALU)................................................. 24 Assembler MPASM Assembler................................................... 228 B Barrel Shifter ....................................................................... 28 Bit-Reversed Addressing .................................................... 49 Example ...................................................................... 50 Implementation ........................................................... 49 Sequence Table (16-Entry)......................................... 50 Block Diagrams 16-bit Timer1 Module ................................................ 143 A/D Module ....................................................... 200, 201 Connections for On-Chip Voltage Regulator............. 215 Device Clock ............................................................. 101 DSP Engine ................................................................ 25 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 .. 10 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 CPU Core ........................................................... 18 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PLL 103 Input Capture ............................................................ 151 Output Compare ....................................................... 155 PLL............................................................................ 103 PWM Module .................................................... 160, 161 Quadrature Encoder Interface .................................. 173 Reset System.............................................................. 61 Shared Port Structure ............................................... 117 SPI ............................................................................ 179 Timer2 (16-bit) .......................................................... 148 Timer2/3 (32-bit) ....................................................... 148 UART ........................................................................ 193 Watchdog Timer (WDT) ............................................ 216 C C Compilers MPLAB C18 .............................................................. 228 Clock Switching................................................................. 110 Enabling .................................................................... 110 Sequence.................................................................. 110 Code Examples Erasing a Program Memory Page............................... 59 Initiating a Programming Sequence............................ 60 Loading Write Buffers ................................................. 60 Port Write/Read ........................................................ 118 PWRSAV Instruction Syntax..................................... 111 Code Protection ........................................................ 211, 218 Configuration Bits.............................................................. 211 © 2007-2012 Microchip Technology Inc. Configuration Register Map .............................................. 211 Configuring Analog Port Pins............................................ 118 CPU Control Register.......................................................... 21 CPU Clocking System ...................................................... 102 PLL Configuration..................................................... 102 Selection................................................................... 102 Sources .................................................................... 102 Customer Change Notification Service............................. 325 Customer Notification Service .......................................... 325 Customer Support............................................................. 325 D Data Accumulators and Adder/Subtracter .......................... 26 Data Space Write Saturation ...................................... 28 Overflow and Saturation ............................................. 26 Round Logic ............................................................... 27 Write Back .................................................................. 27 Data Address Space........................................................... 31 Alignment.................................................................... 31 Memory Map for dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Devices with 2 KBs RAM . 32 Near Data Space ........................................................ 31 Software Stack ........................................................... 46 Width .......................................................................... 31 DC and AC Characteristics Graphs and Tables ................................................... 291 DC Characteristics............................................................ 232 Doze Current (IDOZE)................................................ 283 High Temperature..................................................... 282 I/O Pin Input Specifications ...................................... 238 I/O Pin Output Specifications............................ 241, 284 Idle Current (IDOZE) .................................................. 237 Idle Current (IIDLE) .................................................... 235 Operating Current (IDD) ............................................ 234 Operating MIPS vs. Voltage ..................................... 282 Power-Down Current (IPD)........................................ 236 Power-down Current (IPD) ........................................ 283 Program Memory...................................................... 242 Temperature and Voltage......................................... 282 Temperature and Voltage Specifications.................. 233 Thermal Operating Conditions.................................. 282 Development Support ....................................................... 227 Doze Mode ....................................................................... 112 DSP Engine ........................................................................ 24 Multiplier ..................................................................... 26 E Electrical Characteristics .................................................. 231 AC..................................................................... 244, 285 Equations Device Operating Frequency.................................... 102 Errata .................................................................................... 7 F Fail-Safe Clock Monitor .................................................... 110 Flash Program Memory ...................................................... 55 Control Registers........................................................ 56 Operations .................................................................. 56 Programming Algorithm.............................................. 59 RTSP Operation ......................................................... 56 Table Instructions ....................................................... 55 Flexible Configuration ....................................................... 211 DS70283K-page 321 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 H High Temperature Electrical Characteristics..................... 281 I I/O Ports ............................................................................ 117 Parallel I/O (PIO)....................................................... 117 Write/Read Timing .................................................... 118 I2 C Addresses ................................................................. 187 Operating Modes ...................................................... 185 Registers ................................................................... 187 Software Controlled Clock Stretching (STREN = 1).. 187 I2C Module I2C1 Register Map ...................................................... 39 In-Circuit Debugger ........................................................... 217 In-Circuit Emulation........................................................... 211 In-Circuit Serial Programming (ICSP) ....................... 211, 217 Input Capture .................................................................... 151 Registers ................................................................... 153 Input Change Notification.................................................. 118 Instruction Addressing Modes............................................. 46 File Register Instructions ............................................ 46 Fundamental Modes Supported.................................. 47 MAC Instructions......................................................... 47 MCU Instructions ........................................................ 46 Move and Accumulator Instructions ............................ 47 Other Instructions........................................................ 47 Instruction Set Overview ................................................................... 222 Summary................................................................... 219 Instruction-Based Power-Saving Modes ........................... 111 Idle ............................................................................ 112 Sleep ......................................................................... 111 Interfacing Program and Data Memory Spaces .................. 51 Internal RC Oscillator Use with WDT ........................................................... 216 Internet Address................................................................ 325 Interrupt Control and Status Registers................................ 74 IECx ............................................................................ 74 IFSx............................................................................. 74 INTCON1 .................................................................... 74 INTCON2 .................................................................... 74 IPCx ............................................................................ 74 Interrupt Setup Procedures ............................................... 100 Initialization ............................................................... 100 Interrupt Disable........................................................ 100 Interrupt Service Routine .......................................... 100 Trap Service Routine ................................................ 100 Interrupt Vector Table (IVT) ................................................ 71 Interrupts Coincident with Power Save Instructions.......... 112 J JTAG Boundary Scan Interface ........................................ 211 JTAG Interface .................................................................. 217 M Memory Organization.......................................................... 29 Microchip Internet Web Site .............................................. 325 Modulo Addressing ............................................................. 48 Applicability ................................................................. 49 Operation Example ..................................................... 48 Start and End Address ................................................ 48 W Address Register Selection .................................... 48 Motor Control PWM........................................................... 159 Motor Control PWM Module 2-Output Register Map................................................ 38 DS70283K-page 322 6-Output Register Map for dsPIC33FJ12MC202........ 38 MPLAB ASM30 Assembler, Linker, Librarian ................... 228 MPLAB Integrated Development Environment Software.. 227 MPLAB PM3 Device Programmer .................................... 230 MPLAB REAL ICE In-Circuit Emulator System ................ 229 MPLINK Object Linker/MPLIB Object Librarian ................ 228 N NVM Module Register Map .............................................................. 45 O Open-Drain Configuration................................................. 118 Oscillator Configuration .................................................... 101 Output Compare ............................................................... 155 P Packaging ......................................................................... 295 Details....................................................................... 297 Marking ............................................................. 295, 296 Peripheral Module Disable (PMD) .................................... 112 Pinout I/O Descriptions (table)............................................ 11 PMD Module Register Map .............................................................. 45 PORTA Register Map for dsPIC33FJ32MC202....................... 43 Register Map for dsPIC33FJ32MC204 and dsPIC33FJ16MC304 .......................................... 43 PORTB Register Map .............................................................. 44 PORTC Register Map dsPIC33FJ32MC204 and dsPIC33FJ16MC304 .......................................... 44 Power-on Reset (POR)....................................................... 67 Power-Saving Features .................................................... 111 Clock Frequency and Switching ............................... 111 Program Address Space..................................................... 29 Construction ............................................................... 51 Data Access from Program Memory Using Program Space Visibility..................................... 54 Data Access from Program Memory Using Table Instructions ..................................... 53 Data Access from, Address Generation ..................... 52 Memory Map............................................................... 29 Table Read Instructions TBLRDH ............................................................. 53 TBLRDL.............................................................. 53 Visibility Operation ...................................................... 54 Program Memory Interrupt Vector ........................................................... 30 Organization ............................................................... 30 Reset Vector ............................................................... 30 PWM Time Base............................................................... 163 Q Quadrature Encoder Interface (QEI)................................. 173 Quadrature Encoder Interface (QEI) Module Register Map .............................................................. 39 R Reader Response............................................................. 326 Registers AD1CHS0 (ADC1 Input Channel 0 Select ................ 209 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 207 AD1CON1 (ADC1 Control 1) .................................... 203 AD1CON2 (ADC1 Control 2) .................................... 205 AD1CON3 (ADC1 Control 3) .................................... 206 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 AD1CSSL (ADC1 Input Scan Select Low)................ 210 AD1PCFGL (ADC1 Port Configuration Low) ............ 210 CLKDIV (Clock Divisor)............................................. 107 CORCON (Core Control) ...................................... 23, 75 DFLTCON (QEI Control)........................................... 177 I2CxCON (I2Cx Control) ........................................... 188 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 192 I2CxSTAT (I2Cx Status) ........................................... 190 ICxCON (Input Capture x Control) ............................ 153 IEC0 (Interrupt Enable Control 0) ............................... 84 IEC1 (Interrupt Enable Control 1) ............................... 86 IEC3 (Interrupt Enable Control 3) ............................... 87 IEC4 (Interrupt Enable Control 4) ............................... 88 IFS0 (Interrupt Flag Status 0) ..................................... 79 IFS1 (Interrupt Flag Status 1) ..................................... 81 IFS3 (Interrupt Flag Status 3) ..................................... 82 IFS4 (Interrupt Flag Status 4) ..................................... 83 INTCON1 (Interrupt Control 1).................................... 76 INTCON2 (Interrupt Control 2).................................... 78 INTTREG Interrupt Control and Status Register......... 99 IPC0 (Interrupt Priority Control 0) ............................... 89 IPC1 (Interrupt Priority Control 1) ............................... 90 IPC14 (Interrupt Priority Control 14) ........................... 96 IPC15 (Interrupt Priority Control 15) ........................... 97 IPC16 (Interrupt Priority Control 16) ........................... 97 IPC18 (Interrupt Priority Control 18) ........................... 98 IPC2 (Interrupt Priority Control 2) ............................... 91 IPC3 (Interrupt Priority Control 3) ............................... 92 IPC4 (Interrupt Priority Control 4) ............................... 93 IPC5 (Interrupt Priority Control 5) ............................... 94 IPC7 (Interrupt Priority Control 7) ............................... 95 NVMCON (Flash Memory Control) ............................. 57 NVMKEY (Nonvolatile Memory Key) .......................... 58 OCxCON (Output Compare x Control) ..................... 158 OSCCON (Oscillator Control) ................................... 105 OSCTUN (FRC Oscillator Tuning) ............................ 109 P1DC2 (PWM Duty Cycle 2)..................................... 172 P1DC3 (PWM Duty Cycle 3)..................................... 172 PDC1 (PWM Duty Cycle 1)....................................... 172 PLLFBD (PLL Feedback Divisor).............................. 108 PMD1 (Peripheral Module Disable Control Register 1) ........................................................ 114 PMD1 (Peripheral Module Disable Control Register 1) .. 114 PMD2 (Peripheral Module Disable Control Register 2) ........................................................ 115 PMD3 (Peripheral Module Disable Control Register 3) ........................................................ 116 PMD3 (Peripheral Module Disable Control Register 3) .. 116 PTCON (PWM Time Base Control) .......................... 163 PTMR (PWM Timer Count Value)............................. 164 PTPER (PWM Time Base Period) ............................ 164 PWMxCON1 (PWM Control 1).................................. 166 PWMxCON2 (PWM Control 2).................................. 167 PxDTCON1 (Dead-Time Control 1) .......................... 168 PxDTCON2 (Dead-Time Control 2) .......................... 169 PxFLTACON (Fault A Control).................................. 170 PxOVDCON (Override Control) ................................ 171 PxSECMP (Special Event Compare)........................ 165 QEICON (QEI Control).............................................. 175 RCON (Reset Control) ................................................ 63 SPIxCON1 (SPIx Control 1)...................................... 182 SPIxCON2 (SPIx Control 2)...................................... 184 SPIxSTAT (SPIx Status and Control) ....................... 181 SR (CPU Status)................................................... 21, 75 © 2007-2012 Microchip Technology Inc. T1CON (Timer1 Control) .......................................... 145 T2CON Control)........................................................ 149 T3CON Control......................................................... 150 UxMODE (UARTx Mode) ......................................... 195 UxSTA (UARTx Status and Control) ........................ 197 Reset Illegal Opcode....................................................... 61, 69 Trap Conflict ......................................................... 68, 69 Uninitialized W Register ....................................... 61, 69 Reset Sequence ................................................................. 71 Resets ................................................................................ 61 S Serial Peripheral Interface (SPI) ....................................... 179 Software Reset Instruction (SWR)...................................... 68 Software Simulator (MPLAB SIM) .................................... 229 Software Stack Pointer, Frame Pointer CALLL Stack Frame ................................................... 46 Special Features of the CPU ............................................ 211 SPI Module SPI1 Register Map ..................................................... 39 Symbols Used in Opcode Descriptions ............................ 220 System Control Register Map .............................................................. 44 T Temperature and Voltage Specifications AC..................................................................... 244, 285 Timer1 .............................................................................. 143 Timer2/3 ........................................................................... 147 Timing Characteristics CLKO and I/O ........................................................... 247 Timing Diagrams 10-bit ADC Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000)......................... 278 10-bit ADC Conversion (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)....................................... 278 12-bit ADC Conversion (ASAM = 0, SSRC = 000) ........................................... 277 Brown-out Situations .................................................. 68 External Clock .......................................................... 245 I2Cx Bus Data (Master Mode) .................................. 270 I2Cx Bus Data (Slave Mode) .................................... 272 I2Cx Bus Start/Stop Bits (Master Mode)................... 270 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 272 Input Capture (CAPx) ............................................... 253 Motor Control PWM .................................................. 255 Motor Control PWM Fault ......................................... 255 OC/PWM .................................................................. 254 Output Compare (OCx) ............................................ 253 QEA/QEB Input ........................................................ 256 QEI Module Index Pulse........................................... 257 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 248 Timer1, 2, 3 External Clock ...................................... 250 TimerQ (QEI Module) External Clock ....................... 252 Timing Requirements ADC Conversion (10-bit mode) ................................ 290 ADC Conversion (12-bit Mode) ................................ 290 CLKO and I/O ........................................................... 247 External Clock .......................................................... 245 Input Capture............................................................ 253 SPIx Master Mode (CKE = 0) ................................... 286 SPIx Module Master Mode (CKE = 1) ...................... 286 SPIx Module Slave Mode (CKE = 0) ........................ 287 DS70283K-page 323 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 SPIx Module Slave Mode (CKE = 1)......................... 287 Timing Specifications 10-bit ADC Conversion Requirements ...................... 279 12-bit ADC Conversion Requirements ...................... 277 I2Cx Bus Data Requirements (Master Mode) ........... 271 I2Cx Bus Data Requirements (Slave Mode) ............. 273 Motor Control PWM Requirements ........................... 255 Output Compare Requirements ................................ 253 PLL Clock.......................................................... 246, 285 QEI External Clock Requirements ............................ 252 QEI Index Pulse Requirements................................. 257 Quadrature Decoder Requirements .......................... 256 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ......................................... 249 Simple OC/PWM Mode Requirements ..................... 254 Timer1 External Clock Requirements ....................... 250 Timer2 External Clock Requirements ....................... 251 DS70283K-page 324 Timer3 External Clock Requirements ....................... 251 U UART Module UART1 Register Map.................................................. 39 Universal Asynchronous Receiver Transmitter (UART) ... 193 Using the RCON Status Bits............................................... 69 V Voltage Regulator (On-Chip) ............................................ 215 W Watchdog Time-out Reset (WDTR).................................... 68 Watchdog Timer (WDT)............................................ 211, 216 Programming Considerations ................................... 216 WWW Address ................................................................. 325 WWW, On-Line Support ....................................................... 7 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. 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Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. 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If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 Literature Number: DS70283K Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70283K-page 326 © 2007-2012 Microchip Technology Inc. dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 32 MC2 02 T E / SP - XXX Examples: a) Microchip Trademark Architecture dsPIC33FJ32MC202TE/SP: Motor Control dsPIC33, 32 KB program memory, 28-pin, Extended temp., SPDIP package. Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture: 33 = 16-bit Digital Signal Controller Flash Memory Family: FJ = Flash program memory, 3.3V Product Group: MC2 MC3 = = Motor Control family Motor Control family Pin Count: 02 04 = = 28-pin 44-pin Temperature Range: I E H = = = -40° C to+85° C (Industrial) -40° C to+125° C (Extended) -40° C to+150° C (High) Package: SP SO SS ML PT MM = = = = = = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) Plastic Small Outline - Wide - 7.50 mil body (SOIC) Plastic Shrink Small Outline - 5.3 mm body (SSOP) Plastic Quad, No Lead Package - 8x8 mm body (QFN) Plastic Thing Quad Flatpack - 10x10x1 mm body (TQFP) Plastic Quad, No Lead Package - 6x6 mm body (QFN-S) © 2007-2012 Microchip Technology Inc. DS70283K-page 327 dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 NOTES: DS70283K-page 328 © 2007-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-62076-335-3 QUALITY MANAGEMENT  SYSTEM  CERTIFIED BY DNV  == ISO/TS 16949 ==  © 2007-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70283K-page 329 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-66-152-7160 Fax: 81-66-152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS70283K-page 330 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 11/29/11 © 2007-2012 Microchip Technology Inc.