dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
16-Bit Digital Signal Controllers with High-Speed PWM,
ADC and Comparators
Operating Conditions
Timers/Output Compare/Input Capture
• 3.0V to 3.6V, -40ºC to +85ºC, DC to 50 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• Six General Purpose Timers:
- Five 16-bit and up to two 32-bit timers/counters
• Four Output Compare (OC) modules Configurable as
Timers/Counters
• Quadrature Encoder Interface (QEI) module
Configurable as Timer/Counter
• Four Input Capture (IC) modules
Core: 16-Bit dsPIC33F
•
•
•
•
•
Code-Efficient (C and Assembly) Architecture
Two 40-Bit Wide Accumulators
Single-Cycle (MAC/MPY) with Dual Data Fetch
Single-Cycle Mixed-Sign MUL plus Hardware Divide
32-Bit Multiply Support
Clock Management
•
•
•
•
•
±1% Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast Wake-up and Start-up
Power Management
•
•
•
•
Low-Power Management modes (Sleep, Idle, Doze)
Integrated Power-on Reset and Brown-out Reset
1.7 mA/MHz Dynamic Current (typical)
50 µA IPD Current (typical)
High-Speed PWM
•
•
•
•
Up to 9 PWM Pairs with Independent Timing
Dead Time for Rising and Falling Edges
1.04 ns PWM Resolution
PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• High-Speed ADC module:
- 10-bit resolution with up to two Successive
Approximation Register (SAR) converters
(up to 4 Msps)
- Up to 24 input channels grouped into
12 conversion pairs plus two voltage reference
monitoring inputs
- Dedicated result buffer for each analog channel
• Flexible and Independent ADC Trigger Sources
• Up to 4 High-Speed Comparators with Direct
Connection to the PWM module:
- 10-bit Digital-to-Analog Converter (DAC) for each
comparator
- DAC reference output
- Programmable references with 1024 voltage points
2009-2014 Microchip Technology Inc.
Communication Interfaces
• Two UART modules (12.5 Mbps):
- With support for LIN/J2602 2.0 protocols and IrDA®
• Two 4-Wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) with ECAN 2.0B Support
• Two I2C™ modules (up to 1 Mbaud) with SMBus
Support
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority
Arbitration
• UART, SPI, ECAN, IC, OC and Timers
Input/Output
• Sink/Source 18 mA on 18 Pins, 10 mA on 1 Pin or
6 mA on 66 Pins
• 5V Tolerant Pins
• Selectable Open-Drain and Pull-ups
• 29 External Interrupts
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC)
• Class B Safety Library, IEC 60730, VDE Certified
Debugger Development Support
•
•
•
•
In-Circuit and In-Application Programming
Two Program and Two Complex Data Breakpoints
IEEE 1149.2 Compatible (JTAG) Boundary Scan
Trace and Run-Time Watch
DS7000591F-page 1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610
PRODUCT FAMILIES
The device names, pin counts, memory sizes and
peripheral availability of each device are listed in Table 1.
The following pages show their pinout diagrams.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
CONTROLLER FAMILIES
Program Flash Memory (Kbytes)
RAM (Bytes)
16-Bit Timers
Input Capture
Output Compare
UART
Quadrature Encoder Interfaces
SPI
ECAN™
DMA Channels
PWM
Analog Comparators
External Interrupts
DAC Output
I2C™
SARs
Sample-and-Hold (S&H) Circuits
Analog-to-Digital Inputs
I/O Pins
Packages
ADC
Pins
TABLE 1:
dsPIC33FJ32GS406 64
32
4K
5
4
4
2
1
2
0
0
6x2
0
5
0
2
1
5
16
58
PT,
MR
dsPIC33FJ32GS606 64
32
4K
5
4
4
2
2
2
0
0
6x2
4
5
1
2
2
6
16
58
PT,
MR
dsPIC33FJ32GS608 80
32
4K
5
4
4
2
2
2
0
0
8x2
4
5
1
2
2
6
18
74
PT
dsPIC33FJ32GS610 100 32
4K
5
4
4
2
2
2
0
0
9x2
4
5
1
2
2
6
24
85
PT,
PF
dsPIC33FJ64GS406 64
64
8K
5
4
4
2
1
2
0
0
6x2
0
5
0
2
1
5
16
58
PT,
MR
dsPIC33FJ64GS606 64
64
9K(1)
5
4
4
2
2
2
1
4
6x2
4
5
1
2
2
6
16
58
PT,
MR
dsPIC33FJ64GS608 80
64
9K(1)
5
4
4
2
2
2
1
4
8x2
4
5
1
2
2
6
18
74
PT
dsPIC33FJ64GS610 100 64
9K(1)
5
4
4
2
2
2
1
4
9x2
4
5
1
2
2
6
24
85
PT,
PF
Device
Note 1:
RAM size is inclusive of 1-Kbyte DMA RAM.
DS7000591F-page 2
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS406
dsPIC33FJ64GS406
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
AN14/SS1/U2RTS/RB14
AN15/CN12/RB15
U2RX/SDA2/FLT17/CN17/RF4
U2TX/SCL2/FLT18/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/CN11/RG9
VSS
VDD
AN5/AQEB1/CN7/RB5
AN4/AQEA1/CN6/RB4
AN3/AINDX1/CN5/RB3
AN2/ASS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
2009-2014 Microchip Technology Inc.
DS7000591F-page 3
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
64-Pin QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/CN11/RG9
VSS
VDD
AN5/AQEB1/CN7/RB5
AN4/AQEA1/CN6/RB4
AN3/AINDX1/CN5/RB3
AN2/ASS1/CN4/RB2
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS406
dsPIC33FJ64GS406
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVss
AN8/U2CTS/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
AN14/SS1/U2RTS/RB14
AN15/CN12/RB15
U2RX/SDA2/FLT17/CN17/RF4
U2TX/SCL2/FLT18/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS7000591F-page 4
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
2009-2014 Microchip Technology Inc.
DS7000591F-page 5
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
C1TX/RF1
C1RX/SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
DS7000591F-page 6
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
RF1
SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
64-Pin QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ32GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2009-2014 Microchip Technology Inc.
DS7000591F-page 7
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/FLT8/RE0
C1TX/RF1
C1RX/SYNCI4/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
64-Pin QFN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/SYNCI2/T5CK/CN11/RG9
VSS
VDD
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ64GS606
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/INT4/RD11
IC3/INDX1/FLT3/INT3/RD10
IC2/FLT2/U1CTS/INT2/RD9
IC1/FLT1/SYNCI1/INT1/RD8
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
AVDD
AVSS
AN8/U2CTS/RB8
AN9/DACOUT/RB9
TMS/AN10/INDX2/RB10
TDO/AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U2RX/SDA2/QEA2/FLT17/CN17/RF4
U2TX/SCL2/QEB2/FLT18/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS7000591F-page 8
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
61
66
65
QEA2/RD12
PWM7H/OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
PWM5L/CN15/RD6
68
67
63
62
PWM5H/UPDN1/CN16/RD7
69
64
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
QEB2/RG1
73
72
70
INDX2/SYNCI4/RG0
74
71
PWM1L/FLT8/RE0
75
PWM2L/RE2
PWM1H/RE1
77
76
PWM2H/RE3
78
80
79
PWM3L/RE4
80-Pin TQFP
PWM3H/RE5
1
60
PWM4L/RE6
2
59
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
3
58
4
57
5
56
6
55
7
54
8
53
9
52
SS2/FLT9/T5CK/CN11/RG9
VSS
VDD
TMS/FLT13/INT1/RE8
TDO/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
10
51
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
dsPIC33FJ32GS608
11
50
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/SYNCI1/RD8
SDA2/INT4/FLT19/RA15
SCL2/INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
2009-2014 Microchip Technology Inc.
28
29
30
31
32
33
34
35
36
37
38
39
40
AN10/RB10
AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
U2TX/FLT18/CN18/RF5
U1RX/RF2
U1TX/RF3
AN9/DACOUT/RB9
41
27
20
AN8/U2CTS/RB8
SDO1/RF8
42
26
43
19
AVSS
18
25
SCK1/INT0/RF6
SDI1/RF7
AVDD
44
PWM8H/RA10
45
17
24
46
16
23
15
22
47
PWM8L/RA9
48
14
21
13
PGED1/AN7/CMP4B/RB7
49
PGEC1/AN6CMP3C/CMP4A/OCFA/RB6
12
VDD
SCL1/RG2
SDA1/RG3
DS7000591F-page 9
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
61
66
65
62
PWM5L/CN15/RD6
68
67
QEA2/RD12
PWM7H/OC4/SYNCO1/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
PWM5H/UPDN1/CN16/RD7
69
64
63
QEB2/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
74
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
INDX2/SYNCI4/RG0
75
70
PWM1L/FLT8/RE0
76
71
PWM2L/RE2
PWM1H/RE1
73
72
PWM2H/RE3
78
77
PWM3L/RE4
80
79
80-Pin TQFP
PWM3H/RE5
1
60
PWM4L/RE6
2
59
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
3
58
4
57
5
56
6
55
7
54
8
53
52
9
SS2/FLT9/T5CK/CN11/RG9
VSS
VDD
TMS/FLT13/INT1/RE8
TDO/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
10
51
dsPIC33FJ64GS608
DS7000591F-page 10
29
30
31
32
33
34
35
36
37
38
39
AN11/EXTREF/RB11
VSS
VDD
TCK/AN12/CMP1D/RB12
TDI/AN13/CMP2D/RB13
AN14/CMP3D/SS1/U2RTS/RB14
AN15/CMP4D/CN12/RB15
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/SYNCI1/RD8
SDA2/INT4/FLT19/RA15
SCL2/INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
U2TX/FLT18/CN18/RF5
40
28
41
AN10/RB10
20
AN9/DACOUT/RB9
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
AN8/U2CTS/RB8
42
27
43
19
26
18
25
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
AVSS
44
AVDD
45
17
24
46
16
PWM8H/RA10
15
23
47
22
48
14
PWM8L/RA9
13
21
49
PGED1/AN7/CMP4B/RB7
50
12
PGEC1/AN6CMP3C/CMP4A/OCFA/RB6
11
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM9H/RG13
PWM9L/RG12
SYNCO1/FLT23/RG14
PWM1H/RE1
PWM1L/FLT8/RE0
AN23/CN23/RA7
AN22/CN22/RA6
INDX2/RG0
QEB2/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
QEA2/RD12
PWM7H/OC4/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
100-Pin TQFP
SYNCI1/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
AN18/T4CK/RC3
AN19/T5CK/RC4
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/CN11/RG9
VSS
VDD
TMS/RA0
2
3
4
5
6
7
8
9
10
11
12
73
72
71
70
69
68
67
66
dsPIC33FJ32GS610
13
14
15
16
17
18
19
20
65
64
63
62
61
60
59
58
57
56
21
22
23
24
25
55
54
53
52
51
Vss
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/RD8
INT4/FLT19/SYNCI4/RA15
INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/FLT21/RA3
SCL2/FLT22/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
PWM8L/RA9
PWM8H/RA10
AVDD
AVSS
AN8/RB8
AN9/DACOUT/RB9
AN10/RB10
AN11/EXTREF/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/CMP1D/RB12
AN13/CMP2D/RB13
AN14/CMP3D/SS1/RB14
AN15/CMP4D/CN12/RB15
VSS
VDD
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
U2TX/FLT18/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN20/FLT13/INT1/RE8
AN21/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
75
74
1
2009-2014 Microchip Technology Inc.
DS7000591F-page 11
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM9H/RG13
PWM9L/RG12
SYNCO1/FLT23/RG14
PWM1H/RE1
PWM1L/FLT8/RE0
AN23/CN23/RA7
AN22/CN22/RA6
INDX2/RG0
QEB2/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM5H/UPDN1/CN16/RD7
PWM5L/CN15/RD6
PWM6H/CN14/RD5
PWM6L/CN13/RD4
PWM7L/CN19/RD13
QEA2/RD12
PWM7H/OC4/RD3
OC3/FLT7/RD2
OC2/SYNCO2/FLT6/RD1
100-Pin TQFP
SYNCI1/RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/RC1
AN17/T3CK/RC2
AN18/T4CK/RC3
AN19/T5CK/RC4
SCK2/FLT12/CN8/RG6
SDI2/FLT11/CN9/RG7
SDO2/FLT10/CN10/RG8
MCLR
SS2/FLT9/CN11/RG9
VSS
VDD
TMS/RA0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
dsPIC33FJ64GS610
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vss
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/QEB1/FLT5/RD0
IC4/QEA1/FLT4/RD11
IC3/INDX1/FLT3/RD10
IC2/FLT2/RD9
IC1/FLT1/RD8
INT4/FLT19/SYNCI4/RA15
INT3/FLT20/RA14
VSS
OSC2/REFCLKO/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/FLT21/RA3
SCL2/FLT22/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/CMP3C/CMP4A/OCFA/RB6
PGED1/AN7/CMP4B/RB7
PWM8L/RA9
PWM8H/RA10
AVDD
AVSS
AN8/RB8
AN9/DACOUT/RB9
AN10/RB10
AN11/EXTREF/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/CMP1D/RB12
AN13/CMP2D/RB13
AN14/CMP3D/SS1/RB14
AN15/CMP4D/CN12/RB15
VSS
VDD
U1CTS/FLT15/SYNCI3/CN20/RD14
U1RTS/FLT16/SYNCI2/CN21/RD15
U2RX/FLT17/CN17/RF4
U2TX/FLT18/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AN20/FLT13/INT1/RE8
AN21/FLT14/INT2/RE9
AN5/CMP3B/AQEB1/CN7/RB5
AN4/CMP2C/CMP3A/AQEA1/CN6/RB4
AN3/CMP2B/AINDX1/CN5/RB3
AN2/CMP1C/CMP2A/ASS1/CN4/RB2
PGEC3/AN1/CMP1B/CN3/RB1
PGED3/AN0/CMP1A/CMP4C/CN2/RB0
1
DS7000591F-page 12
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Table of Contents
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 Product Families ............................................................... 2
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 23
3.0 CPU............................................................................................................................................................................................ 33
4.0 Memory Organization ................................................................................................................................................................. 45
5.0 Flash Program Memory............................................................................................................................................................ 109
6.0 Resets ..................................................................................................................................................................................... 115
7.0 Interrupt Controller ................................................................................................................................................................... 123
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 179
9.0 Oscillator Configuration ............................................................................................................................................................ 189
10.0 Power-Saving Features............................................................................................................................................................ 203
11.0 I/O Ports ................................................................................................................................................................................... 213
12.0 Timer1 ...................................................................................................................................................................................... 217
13.0 Timer2/3/4/5 features .............................................................................................................................................................. 219
14.0 Input Capture............................................................................................................................................................................ 225
15.0 Output Compare....................................................................................................................................................................... 227
16.0 High-Speed PWM..................................................................................................................................................................... 231
17.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 261
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 265
19.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................ 271
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 279
21.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 285
22.0 High-Speed, 10-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 313
23.0 High-Speed Analog Comparator .............................................................................................................................................. 345
24.0 Special Features ...................................................................................................................................................................... 349
25.0 Instruction Set Summary .......................................................................................................................................................... 357
26.0 Development Support............................................................................................................................................................... 365
27.0 Electrical Characteristics .......................................................................................................................................................... 369
28.0 50 MIPS Electrical Characteristics ........................................................................................................................................... 417
29.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 423
30.0 Packaging Information.............................................................................................................................................................. 427
Appendix A: Migrating from dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 to dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 Devices ................................................................................................................... 441
Appendix B: Revision History............................................................................................................................................................. 442
Index ................................................................................................................................................................................................. 449
The Microchip Web Site ..................................................................................................................................................................... 457
Customer Change Notification Service .............................................................................................................................................. 457
Customer Support .............................................................................................................................................................................. 457
Product Identification System ............................................................................................................................................................ 459
2009-2014 Microchip Technology Inc.
DS7000591F-page 13
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS7000591F-page 14
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Referenced Sources
This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Reference
Manual”. These documents should be considered as the
primary reference for the operation of a particular module
or device feature.
Note 1: To access the documents listed below,
browse to the documentation section
of the dsPIC33FJ64GS610 product
page of the Microchip web site
(www.microchip.com) to select a family
reference manual section from the
following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“CPU” (DS70204)
“Data Memory” (DS70202)
“Program Memory” (DS70203)
“Flash Programming” (DS70191)
“Reset” (DS70192)
“Watchdog Timer (WDT) and Power-Saving Modes” (DS70196)
“I/O Ports” (DS70193)
“Timers” (DS70205)
“Input Capture” (DS70198)
“Output Compare” (DS70005157)
“Quadrature Encoder Interface (QEI)” (DS70208)
“Analog-to-Digital Converter (ADC)” (DS70183)
“UART” (DS70188)
“Serial Peripheral Interface (SPI)” (DS70206)
“Inter-Integrated Circuit™ (I2C™)” (DS70000195)
“ECAN™” (DS70185)
“Direct Memory Access (DMA)” (DS70182)
“CodeGuard™ Security” (DS70199)
“Programming and Diagnostics” (DS70207)
“Device Configuration” (DS70194)
“Development Tool Support” (DS70200)
“Oscillator (Part IV)” (DS70307)
“High-Speed PWM” (DS70000323)
“High-Speed 10-Bit ADC” (DS70000321)
“High-Speed Analog Comparator” (DS70296)
“Interrupts (Part V)” (DS70597)
2009-2014 Microchip Technology Inc.
DS7000591F-page 15
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 16
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the latest sections in the
“dsPIC33/PIC24
Family
Reference
Manual”, which are available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 families of devices
contain extensive Digital Signal Processor (DSP) functionality with a high-performance 16-bit microcontroller
(MCU) architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the dsPIC33FJ32GS406/
606/608/610 and dsPIC33FJ64GS406/606/608/610
devices. Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
This document contains device-specific information for
the following dsPIC33F Digital Signal Controller (DSC)
devices:
•
•
•
•
•
•
•
•
dsPIC33FJ32GS406
dsPIC33FJ32GS606
dsPIC33FJ32GS608
dsPIC33FJ32GS610
dsPIC33FJ64GS406
dsPIC33FJ64GS606
dsPIC33FJ64GS608
dsPIC33FJ64GS610
2009-2014 Microchip Technology Inc.
DS7000591F-page 17
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 1-1:
DEVICE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
8
PORTA
DMA
RAM
16
16
16
Data Latch
Data Latch
PCU PCH PCL
Program Counter
X RAM
Y RAM
Loop
Control
Logic
Address
Latch
Address
Latch
16
23
23
Stack
Control
Logic
PORTB
DMA
Controller
16
23
16
16
16
PORTC
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
FRC/LPRC
Oscillators
VCAP
Note:
PORTE
16
Divide Support
16 x 16
W Register Array
16
PORTF
Oscillator
Start-up Timer
Power-on
Reset
16-Bit ALU
Watchdog
Timer
Voltage
Regulator
16
DSP Engine
Power-up
Timer
Timing
Generation
Literal Data
16
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
PORTD
ROM Latch
16
PORTG
Brown-out
Reset
VDD, VSS
MCLR
Timers
1-5
UART1/2
ECAN1
ADC1
OC1-4
PWM
9x2
Analog
Comparator 1-4
IC1-4
QEI1,2
CNx
I2C1/2
SPI1,2
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
DS7000591F-page 18
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Type
Buffer
Type
AN0-AN23
I
CLKI
CLKO
I
O
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
I
OSC2
I/O
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
CN0-CN23
I
ST
Change Notification inputs. Can be software programmed for internal
weak pull-ups on all inputs.
C1RX
C1TX
I
O
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
IC1-IC4
I
ST
Capture Inputs 1 through 4.
INDX1, INDX2, AINDX1
QEA1, QEA2, AQEA1
I
I
ST
ST
QEB1, QEB2, AQEB1
I
ST
UPDN1
O
CMOS
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
OCFA
OC1-OC4
I
O
ST
—
Compare Fault A input.
Compare Outputs 1 through 4.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
External Interrupt 3.
External Interrupt 4.
RA0-RA15
I/O
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC0-RC15
I/O
ST
PORTC is a bidirectional I/O port.
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE9
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF13
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG15
I/O
ST
PORTG is a bidirectional I/O port.
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
T1CK
T2CK
T3CK
T4CK
T5CK
Analog
Description
Analog input channels.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
2009-2014 Microchip Technology Inc.
Analog = Analog input
P = Power
I = Input
O = Output
DS7000591F-page 19
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 Clear-to-Send.
UART1 Request-to-Send.
UART1 receive.
UART1 transmit.
UART2 Clear-to-Send.
UART2 Request-to-Send.
UART2 receive.
UART2 transmit.
SCK1
SDI1
SDO1
SS1, ASS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
O
I/O
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
TMS
TCK
TDI
TDO
I
I
I
O
TTL
TTL
TTL
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
DACOUT
O
—
EXTREF
I
Analog
REFCLK
O
—
Pin Name
Description
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
Comparator 3 Channel A.
Comparator 3 Channel B.
Comparator 3 Channel C.
Comparator 3 Channel D.
Comparator 4 Channel A.
Comparator 4 Channel B.
Comparator 4 Channel C.
Comparator 4 Channel D.
DAC output voltage.
External voltage reference input for the reference DACs.
REFCLK output signal is a postscaled derivative of the system clock.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
DS7000591F-page 20
Analog = Analog input
P = Power
I = Input
O = Output
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
FLT1-FLT23
SYNCI1-SYNCI4
SYNCO1-SYNCO2
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
PWM5L
PWM5H
PWM6L
PWM6H
PWM7L
PWM7H
PWM8L
PWM8H
PWM9L
PWM9H
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Fault inputs to PWM module.
External synchronization signal to PWM master time base.
PWM master time base for external device synchronization.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM3 low output.
PWM3 high output.
PWM4 low output.
PWM4 high output.
PWM5 low output.
PWM5 high output.
PWM6 low output.
PWM6 high output.
PWM7 low output.
PWM7 high output.
PWM8 low output.
PWM8 high output.
PWM9 low output.
PWM9 high output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD
P
P
Pin Name
Description
Positive supply for analog modules.
AVSS
P
P
Ground reference for analog modules.
VDD
P
—
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
CPU logic filter capacitor connection.
VSS
P
—
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = Transistor-Transistor Logic
2009-2014 Microchip Technology Inc.
Analog = Analog input
P = Power
I = Input
O = Output
DS7000591F-page 21
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 22
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
family of devices. It is not intended to
be a comprehensive reference source.
To complement the information in
this data sheet, refer to the “dsPIC33/
PIC24 Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
dsPIC33/PIC24 Family Reference Manual sections. The information in this
data sheet supersedes the information
in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ32GS406/606/
608/610 and dsPIC33FJ64GS406/606/608/610
family of 16-bit Digital Signal Controllers (DSC)
requires attention to a minimal set of device pin
connections before proceeding with development.
The following is a list of pin names, which must
always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2009-2014 Microchip Technology Inc.
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation of
0.1 µF (100 nF), 10-20V. This capacitor should be a
low-ESR and have resonance frequency in the
range of 20 MHz and higher. It is recommended that
ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close to
the pins as possible. It is recommended to place the
capacitors on the same side of the board as the
device. If space is constricted, the capacitor can be
placed on another layer on the PCB using a via;
however, ensure that the trace length from the pin to
the capacitor is within one-quarter inch (6 mm) in
length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of tens
of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor.
The value of the second capacitor can be in the
range of 0.01 µF to 0.001 µF. Place this second
capacitor next to the primary decoupling capacitor.
In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the
power and ground pins as possible. For example,
0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first, and
then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track inductance.
DS7000591F-page 23
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
R
R1
2.4
VSS
VCAP
VDD
22 µF
Tantalum
VDD
• Device Reset
• Device programming and debugging
C
dsPIC33F
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note 1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = -------------2
1
f = ---------------------- 2 LC
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
MCLR
0.1 µF
Ceramic
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 24.2
“On-Chip Voltage Regulator” for details.
(i.e., ADC conversion rate/2)
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS(1,2)
VDD
2
1
L = ----------------------
2f C
R
R1
MCLR
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
2.3
Capacitor on Internal Voltage
Regulator (VCAP)
JP
dsPIC33F
C
Note 1:
R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2:
R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR (< 0.5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD, and must have a minimum capacitor
of 22 µF, 16V connected to ground. The type can be
ceramic or tantalum. Refer to Section 27.0 “Electrical
Characteristics” for additional information.
DS7000591F-page 24
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 3 or MPLAB REAL ICE™.
For more information on ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “Using MPLAB® ICD 3” (poster) (DS51765)
• “MPLAB® ICD 3 Design Advisory” (DS51764)
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” (DS51616)
• “Using MPLAB® REAL ICE™” (poster) (DS51749)
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
2009-2014 Microchip Technology Inc.
DS7000591F-page 25
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the Analogto-Digital input pins (ANx) as “digital” pins, by setting all
bits in the ADPCFG and ADPCFG2 registers.
If your application needs to use certain Analog-toDigital pins as analog input pins during the debug
session, the user application must clear the
corresponding bits in the ADPCFG and ADPCFG2
registers during initialization of the ADC module.
When MPLAB ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the ADPCFG and ADPCFG2
registers. Automatic initialization of these registers is
only done during debugger operation. Failure to
correctly configure the register(s) will result in all
Analog-to-Digital pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins and drive the output to logic low.
2.10
Typical Application Connection
Examples
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-11.
The bits in the registers that correspond to the Analog-toDigital pins that are initialized by MPLAB ICD 2, ICD 3, or
REAL ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
DS7000591F-page 26
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-4:
DIGITAL PFC
IPFC
VHV_BUS
|VAC|
k1
k3
VAC
ADC Channel
k2
FET
Driver
ADC Channel
PWM
Output
ADC Channel
dsPIC33FJ32GS406
FIGURE 2-5:
BOOST CONVERTER IMPLEMENTATION
IPFC
VINPUT
VOUTPUT
k1
k3
ADC Channel
k2
FET
Driver
ADC
Channel
PWM
Output
ADC Channel
dsPIC33FJ32GS406
2009-2014 Microchip Technology Inc.
DS7000591F-page 27
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-6:
SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER
12V Input
5V Output
I5V
PWM
ADC
Channel
PWM
FET
Driver
k7
k1
k2
Analog
Comp.
ADC
Channel
dsPIC33FJ32GS606
FIGURE 2-7:
MULTIPHASE SYNCHRONOUS BUCK CONVERTER
3.3V Output
12V Input
PWM
dsPIC33FJ32GS608
PWM
FET
Driver
PWM
ADC
Channel
FET
Driver
PWM
k6
k7
PWM
PWM
Analog Comparator
FET
Driver
k3
Analog Comparator
k4
Analog Comparator
k5
ADC Channel
DS7000591F-page 28
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-8:
OFF-LINE UPS
VDC
Push-Pull Converter
Full-Bridge Inverter
VOUT+
VBAT
+
VOUTGND
GND
FET
Driver
FET
Driver
PWM
PWM
k2
k1
ADC ADC
or
Analog Comp.
k3
FET
Driver
FET
Driver
FET
Driver
FET
Driver
PWM
PWM
PWM
PWM
dsPIC33FJ64GS610
ADC
k4
k5
ADC
ADC
ADC
PWM
FET
Driver
k6
+
Battery Charger
2009-2014 Microchip Technology Inc.
DS7000591F-page 29
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-9:
INTERLEAVED PFC
VOUT+
|VAC|
k4
VAC
k3
k2
k1
VOUTFET
Driver
ADC Channel
ADC Channel
DS7000591F-page 30
PWM
FET
Driver
ADC
Channel
PWM
ADC
Channel
ADC
Channel
dsPIC33FJ32GS608
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 2-10:
PHASE-SHIFTED FULL-BRIDGE CONVERTER
VIN+
Gate 6
Gate 3
Gate 1
VOUT+
S1
S3
VOUT-
Gate 2
Gate 4
Gate 5
Gate 6
Gate 5
VIN-
FET
Driver
k2
PWM
ADC
Channel
k1
Analog
Ground
Gate 1
S1
FET
Driver
PWM
Gate 3
S3
FET
Driver
ADC
Channel
dsPIC33FJ32GS606
PWM
Gate 2
Gate 4
2009-2014 Microchip Technology Inc.
DS7000591F-page 31
AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V AND 3.3V)
ZVT with Current Doubler Synchronous Rectifier
VHV_BUS
Isolation
Barrier
VOUT
IZVT
3.3V Multiphase Buck Stage
3.3V Output
12V Input
I3.3V_1
FET
Driver
FET
Driver
k4
FET
Driver
5V Output
5V Buck Stage
I3.3V_2
ADC
ADC
Channel Channel
FET
Driver
PWM
UART
RX
PWM
Output
ADC
Ch.
ADC
Channel
FET
Driver
k7
Analog
Comp.
ADC
Channel
Secondary Controller
dsPIC33FJ64GS610
PFC Stage
k2
UART
TX
FET Driver
FET
Driver
I3.3V_3
k6
PWM
PWM
ADC
Ch.
k5
PWM
PWM
PWM
ADC
Ch.
Primary Controller
dsPIC33FJ64GS610
PWM
PWM
PWM
PWM
PWM
PWM
I5V
PWM
PWM
Analog Comparator
k8
Analog Comparator
k9
Analog Comparator
k10
ADC Channel
2009-2014 Microchip Technology Inc.
VAC
k3
k1
|VAC|
VHV_BUS
IPFC
FET
Driver
k11
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 32
FIGURE 2-11:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.0
CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to “CPU” (DS70204) in the
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 CPU module has a
16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies from device to
device. A single-cycle instruction prefetch mechanism is
used to help maintain throughput and provides
predictable execution. All instructions execute in a single
cycle, with the exception of instructions that change the
program flow, the double-word move (MOV.D) instruction
and the table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices have sixteen, 16-bit Working registers in the programmer’s
model. Each of the Working registers can serve as a
data, address or address offset register. The sixteenth
Working register (W15) operates as a Software Stack
Pointer (SSP) for interrupts and calls.
There are two classes of instruction in the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set includes
many addressing modes and is designed for optimum C
compiler efficiency. For most instructions, the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices are capable
of executing a data (or program data) memory read, a
Working register (data) read, a data memory write and a
program (instruction) memory read per instruction cycle.
2009-2014 Microchip Technology Inc.
As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a
single cycle.
A block diagram of the CPU is shown in
Figure 3-1, and the programmer’s model for
the
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 is shown in
Figure 3-2.
3.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through
the X memory AGU, which accesses the entire
memory map as one linear data space. Certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y data space
boundary is device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data space mapping feature lets any
instruction access program space as if it were data
space.
3.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits, right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal realtime performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain Working
registers to each address space.
DS7000591F-page 33
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.3
Special MCU Features
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 supports 16/16 and
32/16 divide operations, both fractional and integer. All
divide instructions are iterative operations. They must
be executed within a REPEAT loop, resulting in a total
execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 features a 17-bit by
17-bit single-cycle multiplier that is shared by both the
MCU ALU and DSP engine. The multiplier can perform
signed, unsigned and mixed sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 CPU
CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
23
16
16
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
ROM Latch
24
Instruction Reg
16
Literal Data
Instruction
Decode and
Control
16
16
Control Signals
to Various Blocks
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS7000591F-page 34
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 3-2:
PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
W5
DSP Operand
Registers
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write-Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
DSP
Accumulators
AD15
AD31
AD0
ACCA
ACCB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
2009-2014 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS7000591F-page 35
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.4
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
R/C-0
R/C-0
OB
SA(1)
(1)
SB
R-0
OAB
R/C-0
(1,4)
SAB
R-0
R/W-0
DA
DC
bit 15
bit 8
R/W-0(3)
IPL2
R/W-0(3)
(2)
IPL1
(2)
R/W-0(3)
IPL0
(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Neither Accumulator A or B has overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4)
1 = Accumulator A or B is saturated or has been saturated at some time in the past
0 = Neither Accumulator A or B is saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when NSTDIS = 1 (INTCON1).
Clearing this bit will clear SA and SB.
DS7000591F-page 36
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2,3)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
4:
This bit can be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read-only when NSTDIS = 1 (INTCON1).
Clearing this bit will clear SA and SB.
2009-2014 Microchip Technology Inc.
DS7000591F-page 37
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
R/W-0
SATA
bit 7
R/W-0
SATB
bit 11
bit 10-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
R/W-0
US
R/W-0
EDT(1)
R-0
DL2
R-0
DL1
R-0
DL0
bit 8
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
U-0
—
R/W-1
SATDW
R/W-0
ACCSAT
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at the end of the current loop iteration
0 = No effect
DL: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation is enabled
0 = Data space write saturation is disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space is visible in data space
0 = Program space is not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply operations
0 = Fractional mode is enabled for DSP multiply operations
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level.
DS7000591F-page 38
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.5
Arithmetic Logic Unit (ALU)
3.6
DSP Engine
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 ALU is 16 bits wide
and is capable of addition, subtraction, bit shifts and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending on
the operation, the ALU can affect the values of the Carry
(C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry
(DC) Status bits in the SR register. The C and DC Status
bits operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
The DSP engine consists of a high-speed, 17-bit x 17-bit
multiplier, a barrel shifter and a 40-bit adder/subtracter
(with two target accumulators, round and saturation logic).
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The DSP engine can also perform inherent
accumulator-to-accumulator operations that require no
additional data. These instructions are ADD, SUB and
NEG.
Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR
bits affected by each instruction.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 CPU incorporates
hardware support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit divisor division.
3.5.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the DSP
engine, the ALU supports unsigned, signed or mixed sign
operation in several MCU multiplication modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (for example, ED, EDAC).
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
•
•
•
•
•
•
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for ACCA (SATA)
Automatic saturation on/off for ACCB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
Instruction
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC
Write-Back
Yes
CLR
A=0
ED
A = (x – y)2
No
2
EDAC
A = A + (x – y)
No
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
MAC
A = A + (x * y)
Yes
•
•
•
•
3.5.2
DIVIDER
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and
the remainder in W1. 16-bit signed and unsigned DIV
instructions can specify any W register for both the 16-bit
divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
2009-2014 Microchip Technology Inc.
x2
No
MAC
A=A+
MOVSAC
No change in A
Yes
MPY
A=x*y
No
MPY
A = x2
No
MPY.N
A=–x*y
No
MSC
A=A–x*y
Yes
DS7000591F-page 39
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-Bit Accumulator A
40-Bit Accumulator B
Carry/Borrow Out
Saturate
Carry/Borrow In
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
16
Zero Backfill
32
33
17-Bit
Multiplier/Scaler
16
16
To/From W Array
DS7000591F-page 40
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a
1.31 product that has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its preaccumulation
source
and
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
2009-2014 Microchip Technology Inc.
3.6.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS Register (SR):
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits, 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT
(CORCON) and ACCSAT (CORCON) mode
control bits to determine when and to what value to
saturate.
Six STATUS Register bits support saturation and
overflow:
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the corresponding Overflow Trap Flag Enable bits (OVATE, OVBTE) in
the INTCON1 register are set (refer to Section 7.0
“Interrupt Controller”). This allows the user application to take immediate action, for example, to correct
system gain.
DS7000591F-page 41
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred. If the COVTE bit in the
INTCON1 register is set, SA and SB bits will generate
an arithmetic warning trap when saturation is disabled.
The Overflow and Saturation Status bits can optionally be
viewed in the STATUS Register (SR) as the logical OR of
OA and OB (in bit OAB) and the logical OR of SA and SB
(in bit SAB). Programmers can check one bit in the
STATUS Register to determine if either accumulator has
overflowed, or one bit to determine if either accumulator
has saturated. This is useful for complex number
arithmetic, which typically uses both accumulators.
The device supports three Saturation and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive
9.31 (0x7FFFFFFFFF) or maximally negative
9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set
until cleared by the user application. This
condition is referred to as ‘super saturation’ and
provides protection against erroneous data or
unexpected algorithm problems (such as
gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are
never set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
DS7000591F-page 42
3.6.3
ACCUMULATOR ‘WRITE-BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target accumulator
are written into W13 as a 1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target
accumulator are written into the address pointed
to by W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
3.6.3.1
Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit,
1.15 data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the
accumulator) is between 0x8000 and 0xFFFF
(0x8000 included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a
succession of random rounding operations, the value
tends to be biased slightly positive.
Convergent (or unbiased) rounding operates in the same
manner as conventional rounding, except when ACCxL
equals 0x8000. In this case, the Least Significant bit
(bit 16 of the accumulator) of ACCxH is examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature, this
scheme removes any rounding bias that may accumulate.
The SAC and SAC.R instructions store either a truncated
(SAC), or rounded (SAC.R) version of the contents of the
target accumulator to data memory via the X bus, subject
to data saturation (see Section 3.6.3.2 “Data Space
Write Saturation”). For the MAC class of instructions, the
accumulator write-back operation functions in the same
manner, addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data is
always subject to rounding.
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
3.6.3.2
Data Space Write Saturation
3.6.4
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate
1.15 fractional value as output to write to data space
memory.
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative
1.15 value, 0x8000.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The Most Significant bit of the source (bit 39) is used to
determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2009-2014 Microchip Technology Inc.
DS7000591F-page 43
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
NOTES:
DS7000591F-page 44
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the dsPIC33/PIC24 Family
Reference Manual, Program Memory”
(DS70203), which is available from the
Microchip web site (www.microchip.com).
The information in this data sheet
supersedes the information in the FRM.
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 architecture features
separate program and data memory spaces and buses.
This architecture also allows the direct access to program
memory from the data space during code execution.
User Memory Space
FIGURE 4-1:
4.1
Program Address Space
The program address memory space is 4M instructions. The space is addressable by a 24-bit value
derived either from the 23-bit Program Counter (PC)
during program execution, or from table operation or
data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory maps are shown in Figure 4-1.
PROGRAM MEMORY MAPS FOR dsPIC33FJ32GS406/606/608/610 and
dsPIC33FJ64GS406/606/608/610 DEVICES
dsPIC33FJ32GS406/606/608/610
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
Interrupt Vector Table
0x0000FE
0x000100
Reserved
0x000104
Alternate Vector Table
0x0001FE
0x000200
User Program
Flash Memory
(11008 instructions)
0x0057FE
0x005800
User Memory Space
4.0
dsPIC33FJ64GS406/606/608/610
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
Interrupt Vector Table
0x0000FE
0x000100
Reserved
0x000104
Alternate Vector Table
0x0001FE
0x000200
User Program
Flash Memory
(21760 instructions)
0x00ABFE
0x00AC00
Unimplemented
Unimplemented
(Read ‘0’s)
(Read ‘0’s)
0x7FFFFE
0x800000
0x7FFFFE
0x800000
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
DEVID (2)
Reserved
2009-2014 Microchip Technology Inc.
0xFEFFFE
0xFF0000
0xFF0002
0xFFFFFE
Configuration Memory Space
Configuration Memory Space
Reserved
Device Configuration
Registers
0xF7FFFE
0xF80000
0xF80017
0xF80018
Reserved
0xFEFFFE
DEVID (2)
Reserved
0xFF0000
0xFF0002
0xFFFFFE
DS7000591F-page 45
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices reserve the
addresses between 0x00000 and 0x000200 for hardcoded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO instruction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (see Figure 4-2).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during the code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
FIGURE 4-2:
msw
Address
least significant word
most significant word
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS7000591F-page 46
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices also have
two Interrupt Vector Tables (IVT), located from
0x000004 to 0x0000FF and 0x000100 to 0x0001FF.
These vector tables allow each of the device interrupt
sources to be handled by separate Interrupt Service
Routines (ISRs). A more detailed discussion of the
Interrupt Vector Tables is provided in Section 7.1
“Interrupt Vector Table”.
PROGRAM MEMORY ORGANIZATION
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.2
Data Address Space
The CPU has a separate 16-bit-wide data memory space.
The data space is accessed using separate Address
Generation Units (AGUs) for read and write operations.
The data memory maps is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
The
dsPIC33FJ32GS406/606/608/610
and
dsPIC33FJ64GS406/606/608/610 devices implement
up to 9 Kbytes of data memory. Should an EA point to
a location outside of this area, an all-zero word or byte
will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
efficiency, the instruction set supports both word and
byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally
scaled to step through word-aligned memory. For
example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] that results
in a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
2009-2014 Microchip Technology Inc.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the core and
peripheral modules for controlling the operation of the
device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note:
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Refer to the
corresponding device tables and pinout
diagrams for device-specific information.
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a Working
register as an Address Pointer.
DS7000591F-page 47
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-3:
DATA MEMORY MAP FOR DEVICES WITH 4-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x0FFF
0x1001
0x07FE
0x0800
X Data RAM (X)
Y Data RAM (Y)
0x0FFE
0x1000
0x17FF
0x1801
0x17FE
0x1800
0x8001
0x8000
6-Kbyte
Near Data
Space
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS7000591F-page 48
LSB
Address
16 Bits
0xFFFE
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-4:
DATA MEMORY MAP FOR DEVICES WITH 8-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
LSB
Address
16 Bits
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x07FE
0x0800
X Data RAM (X)
0x17FF
0x1801
0x17FE
0x1800
8-Kbyte
Near Data
Space
Y Data RAM (Y)
0x1FFF
0x2001
0x1FFE
0x27FF
0x2801
0x27FE
0x2800
0x8001
0x8000
0x2000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
2009-2014 Microchip Technology Inc.
0xFFFE
DS7000591F-page 49
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 4-5:
DATA MEMORY MAP FOR DEVICES WITH 9-KBYTE RAM
MSB
Address
MSb
2-Kbyte
SFR Space
LSB
Address
16 Bits
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x07FE
0x0800
X Data RAM (X)
0x17FF
0x1801
0x17FE
0x1800
8-Kbyte
Near Data
Space
Y Data RAM (Y)
0x1FFF
0x2001
0x1FFE
0x27FF
0x2801
0x27FE
0x2800
0x2000
DMA RAM
0x2BFF
0x2C01
0x2BFE
0x2C00
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS7000591F-page 50
0xFFFE
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
4.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED, EDAC,
MAC, MOVSAC, MPY, MPY.N and MSC) to provide two
concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
2009-2014 Microchip Technology Inc.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All Effective Addresses (EAs) are 16 bits wide and point
to bytes within the data space. Therefore, the data
space address range is 64 Kbytes, or 32K words,
though the implemented memory locations vary by
device.
4.2.6
DMA RAM
Some devices contain 1 Kbyte of dual ported DMA
RAM, which is located at the end of Y data space.
Memory locations that are part of Y data RAM and are in
the DMA RAM space are accessible simultaneously by
the CPU and the DMA Controller module. DMA RAM is
utilized by the DMA Controller to store data to be
transferred to various peripherals using DMA, as well as
data transferred from various peripherals using DMA.
The DMA RAM can be accessed by the DMA Controller
without having to steal cycles from the CPU.
When the CPU and the DMA Controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
DS7000591F-page 51
File
Name
SFR
Addr
CPU CORE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
WREG0
0000
Working Register 0
0000
WREG1
0002
Working Register 1
0000
WREG2
0004
Working Register 2
0000
WREG3
0006
Working Register 3
0000
WREG4
0008
Working Register 4
0000
WREG5
000A
Working Register 5
0000
WREG6
000C
Working Register 6
0000
WREG7
000E
Working Register 7
0000
WREG8
0010
Working Register 8
0000
WREG9
0012
Working Register 9
0000
WREG10
0014
Working Register 10
0000
WREG11
0016
Working Register 11
0000
2009-2014 Microchip Technology Inc.
WREG12
0018
Working Register 12
0000
WREG13
001A
Working Register 13
0000
WREG14
001C
Working Register 14
0000
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
ACCAL
xxxx
ACCAH
0024
ACCAH
ACCAU
0026
ACCBL
0028
ACCBL
ACCBH
002A
ACCBH
ACCBU
002C
PCL
002E
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
PSVPAG
0034
—
—
—
—
—
—
—
RCOUNT
0036
REPEAT Loop Counter Register
DCOUNT
0038
DCOUNT
DOSTARTL
003A
ACCA
ACCB
ACCA
ACCB
ACCA
ACCB
ACCA
ACCB
ACCA
ACCB
ACCA
ACCB
xxxx
ACCA ACCA
ACCAU
xxxx
xxxx
ACCB ACCB
ACCBU
xxxx
Program Counter High Byte Register
0000
—
Table Page Address Pointer Register
0000
—
Program Memory Visibility Page Address Pointer Register
0000
Program Counter Low Byte Register
0000
xxxx
xxxx
DOSTARTL
DOSTARTH
003C
DOENDL
003E
DOENDH
0040
—
—
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
IPL2
IPL1
Legend:
xxxx
—
—
—
—
—
—
—
—
—
—
xxxx
0
xxxx
DOSTARTH
00xx
DOENDL
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0
DOENDH
IPL0
RA
N
00xx
OV
Z
C
0000
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 52
TABLE 4-1:
File
Name
SFR
Addr
CORCON
0044
MODCON
0046
CPU CORE REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
—
—
—
US
EDT
DL2
DL1
DL0
XMODEN
YMODEN
—
—
BWM3
BWM2
BWM1
BWM0
Bit 7
Bit 6
Bit 5
Bit 4
SATA
SATB
SATDW
ACCSAT
YWM3 YWM2
YWM1
YWM0
Bit 3
Bit 2
Bit 1
Bit 0
IPL3
PSV
RND
IF
XWM3 XWM2 XWM1 XWM0
All
Resets
0000
0000
XMODSRT
0048
XS
0
xxxx
XMODEND
004A
XE
1
xxxx
YMODSRT
004C
YS
0
xxxx
YMODEND
004E
YE
1
xxxx
XBREV
0050
BREN
XB14
DISICNT
0052
—
—
Legend:
XB13
XB12
XB11
XB10
XB9
XB8
XB7
XB6
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
XB5
XB4
XB3
XB2
XB1
XB0
xxxx
xxxx
DS7000591F-page 53
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-1:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CNEN2
0062
—
—
—
—
—
—
—
—
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CNPU2
006A
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
—
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CNEN2
0062
—
—
—
—
—
—
—
—
CNPU1
0068
CN8PUE
CN7PUE
CNPU2
006A
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
—
Bit 7
Bit 0
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
CN0PUE
0000
CN18PUE CN17PUE CN16PUE
0000
Bit 6
Bit 5
Bit 4
Bit 3
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN23IE
CN22IE
—
—
—
CN18IE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
—
—
—
CN23PUE CN22PUE
Bit 2
Bit 1
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 54
TABLE 4-2:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES
Bit 15
Bit 14
Bit 13
INTCON1 0080 NSTDIS
OVAERR
OVBERR
INTCON2 0082 ALTIVT
DISI
—
—
—
DMA1IF
ADIF
U1TXIF
U2RXIF
INT2IF
—
Bit 12
Bit 11
Bit 6
Bit 4
OSCFAIL
—
0000
INT1EP
INT0EP
0000
OC1IF
IC1IF
INT0IF
0000
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
Bit 8
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
—
—
SFTACERR DIV0ERR
Bit 5
All
Resets
Bit 9
COVAERR COVBERR
Bit 7
Bit 0
Bit 10
Bit 3
Bit 2
Bit 1
STKERR
INT2EP
T1IF
INT1IF
DMACERR MATHERR ADDRERR
DS7000591F-page 55
IFS0
0084
IFS1
0086 U2TXIF
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
C1TXIF
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
ADCP11IF
ADCP10IF
ADCP9IF
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
DMA1IE
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096 U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
C1TXIE
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
PWM1IE
ADCP12IE
—
—
—
—
—
—
—
—
ADCP11IE
ADCP10IE
ADCP9IE
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
PWM9IE
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2
DMA0IP1
DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
0444
IPC3
00AA
—
—
—
—
—
DMA1IP2 DMA1IP1 DMA1IP0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2
DMA2IP1
DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
4444
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2
DMA3IP1
DMA3IP0
0444
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
MI2C2IP2 MI2C2IP1 MI2C2IP0
INT4IP2
INT4IP1
INT4IP0
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-4:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS610 DEVICES (CONTINUED)
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC17
00C6
—
—
—
—
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
0400
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC20
00CC
—
—
ADCP8IP2 ADCP8IP1
ADCP8IP0
—
—
—
—
4440
IPC21
00CE
—
—
—
—
—
—
ADCP12IP2 ADCP12IP1 ADCP12IP0
—
IPC23
00D2
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
—
—
—
—
—
4400
IPC24
00D4
—
PWM6IP2
PWM6IP1
PWM6IP0
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
4444
IPC25
00D6
—
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2 PWM9IP1 PWM9IP0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2
PWM7IP1
PWM7IP0
4444
IPC26
00D8
—
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1
ADCP3IP0
—
ADCP2IP2 ADCP2IP1
ADCP2IP0
4444
IPC29
00DE
—
—
—
—
—
—
—
—
—
ADCP7IP2 ADCP7IP1
ADCP7IP0
—
ADCP6IP2 ADCP6IP1
ADCP6IP0
0044
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
ADCP10IP2 ADCP10IP1 ADCP10IP0
—
ADCP9IP2 ADCP9IP1 ADCP9IP0
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ADCP11IP2 ADCP11IP1 ADCP11IP0
0044
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 56
TABLE 4-4:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
OVBERR
INTCON2 0082
ALTIVT
DISI
—
—
—
COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 1
DS7000591F-page 57
IFS0
0084
—
DMA1IF
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
C1TXIF
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
—
—
—
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF ADCP3IF ADCP2IF
0000
IEC0
0094
—
DMA1IE
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
DMA2IE
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
C1TXIE
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
PWM1IE
ADCP12IE
—
—
—
—
—
—
—
—
—
—
—
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2 DMA0IP1 DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
DMA1IP2
DMA1IP1
DMA1IP0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2 DMA2IP1 DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
IPC8
00B4
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2 SPI2EIP1 SPI2EIP0
4444
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2 DMA3IP1 DMA3IP0
0444
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP0
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC17
00C6
—
—
—
—
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
0400
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
—
—
—
—
4040
Legend:
MI2C2IP2 MI2C2IP1 MI2C2IP0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PSESMIP2 PSESMIP1 PSESMIP0
T5IP2
INT0IP1
INT1IP1
T5IP1
T5IP0
4444
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-5:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS608 DEVICES (CONTINUED)
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
IPC20
00CC
—
—
—
—
—
—
—
—
—
IPC21
00CE
—
—
—
—
—
—
—
—
—
IPC23
00D2
—
PWM2IP2
PWM2IP1
PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
IPC24
00D4
—
PWM6IP2
PWM6IP2
PWM6IP2
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
IPC25
00D6
—
AC2IP2
AC2IP1
AC2IP0
—
—
—
—
—
IPC26
00D8
—
—
—
—
—
—
—
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1
ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1
ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
Legend:
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADCP8IP2 ADCP8IP1 ADCP8IP0
—
—
—
—
0040
ADCP12IP2 ADCP12IP1 ADCP12IP0
—
—
—
—
0040
—
—
—
—
—
4400
PWM4IP1
PWM4IP0
—
PWM3IP2 PWM3IP1 PWM3IP0
4444
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2 PWM7IP1 PWM7IP0
4044
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0 4444
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0 0044
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 58
TABLE 4-5:
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES
File
Name
SFR
Addr
Bit 15
Bit 14
DS7000591F-page 59
Bit 0
All
Resets
INTCON1
0080
NSTDIS
OVAERR
INTCON2
0082
ALTIVT
DISI
—
—
—
OSCFAIL
—
0000
INT1EP
INT0EP
IFS0
0084
—
DMA1IF
ADIF
U1TXIF
0000
OC1IF
IC1IF
INT0IF
IFS1
0086
U2TXIF
U2RXIF
INT2IF
0000
CNIF
AC1IF
MI2C1IF
SI2C1IF
IFS2
0088
—
—
0000
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
IFS3
008A
—
0000
INT3IF
—
—
MI2C2IF
SI2C2IF
—
IFS4
008C
—
0000
C1TXIF
—
—
—
U2EIF
U1EIF
—
IFS5
008E PWM2IF
0000
—
—
—
—
—
—
—
—
IFS6
0090 ADCP1IF ADCP0IF
0000
AC3IF
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
IFS7
0092
—
0000
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF ADCP3IF ADCP2IF
IEC0
0094
0000
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
IEC1
0000
T4IE
OC4IE
OC3IE
DMA2IE
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
—
—
—
—
—
—
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
—
—
QEI2IE
—
PSESMIE
—
—
C1TXIE
—
—
—
U2EIE
U1EIE
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
AC4IE
AC3IE
AC2IE
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP0
4444
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
DMA0IP2 DMA0IP1 DMA0IP0
4444
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
DMA1IP2
DMA1IP1 DMA1IP0
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
4444
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP2
MI2C1IP2
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
DMA2IP2 DMA2IP1 DMA2IP0
4444
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
IPC8
00B4
—
C1IP2
C1IP1
C1IP0
—
C1RXIP2
C1RXIP1
C1RXIP0
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2 SPI2EIP1 SPI2EIP0
4444
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
DMA3IP2 DMA3IP1 DMA3IP0
0444
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC17
00C6
—
—
—
—
—
C1TXIP2
C1TXIP1
C1TXIP0
—
—
—
—
—
—
—
—
0400
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
—
—
—
—
4040
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
OVATE
OVBTE
COVTE
SFTACERR
DIV0ERR
DMACERR
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
T5IF
T4IF
OC4IF
OC3IF
DMA2IF
—
—
—
INT1IF
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
—
—
—
—
—
AC4IF
—
—
—
—
—
—
DMA1IE
ADIE
U1TXIE
U1RXIE
0096
U2TXIE
U2RXIE
INT2IE
T5IE
IEC2
0098
—
—
—
IEC3
009A
—
—
IEC4
009C
—
—
IEC5
009E PWM2IE
IEC6
00A0 ADCP1IE ADCP0IE
IEC7
00A2
—
IPC0
00A4
IPC1
OVBERR COVAERR COVBERR
PWM1IF ADCP12IF
PWM1IE ADCP12IE
MI2C2IP2 MI2C2IP1 MI2C2IP0
Bit 4
Bit 3
Bit 2
MATHERR ADDRERR STKERR
PSESMIP2 PSESMIP1 PSESMIP0
T5IP2
Bit 1
INT0IP1
INT1IP1
T5IP1
T5IP0
4444
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-6:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ64GS606 DEVICES (CONTINUED)
SFR
Addr
Bit 15
IPC21
00CE
—
IPC23
00D2
—
PWM2IP2 PWM2IP1 PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
—
IPC24
00D4
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2 PWM3IP1 PWM3IP0
4444
IPC25
00D6
—
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2 PWM9IP1 PWM9IP0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2 PWM7IP1 PWM7IP0
4000
IPC26
00D8
—
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2
ADCP3IP1
ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
IPC29
00DE
—
—
—
—
—
—
—
—
—
ADCP7IP2
ADCP7IP1
ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6
VECNUM5
VECNUM4
VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
—
—
—
—
Bit 10
Bit 9
Bit 8
Bit 7
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
ADCP12IP2 ADCP12IP1 ADCP12IP0
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
0040
—
—
—
—
4400
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 60
TABLE 4-6:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
INTCON2 0082
ALTIVT
DISI
—
—
—
OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
Bit 2
MATHERR ADDRERR STKERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 1
DS7000591F-page 61
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
—
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
—
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E
PWM2IF
PWM1IF ADCP12IF
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS6
0090 ADCP1IF
ADCP0IF
—
—
—
—
—
—
—
—
—
—
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
—
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
—
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E
PWM2IE
PWM1IE ADCP12IE
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC6
00A0
—
ADCP0IE
—
—
—
—
—
—
—
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
0000
IPC0
00A4
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
—
—
—
—
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP0
0044
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP2
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
—
—
—
—
—
—
—
—
—
—
—
—
0040
IPC23
00D2
—
—
PWM1IP2
—
—
—
—
4400
Legend:
PWM2IP2 PWM2IP1 PWM2IP0
MI2C2IP1 MI2C2IP0
PWM1IP1 PWM1IP0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
MI2C1IP2 MI2C1IP1 MI2C1IP0
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
SPI2EIP2 SPI2EIP1
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-7:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES (CONTINUED)
All
Resets
SFR
Addr
Bit 15
IPC24
00D4
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2
PWM5IP1 PWM5IP0
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
IPC29
00DE
—
—
—
—
—
—
—
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 6
Bit 5
Bit 4
PWM4IP2 PWM4IP1 PWM4IP0
—
—
—
Bit 3
—
—
Bit 2
Bit 1
Bit 0
PWM3IP2 PWM3IP1 PWM3IP0
—
—
—
4444
4400
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 62
TABLE 4-7:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
OVBERR
INTCON2 0082
ALTIVT
DISI
—
—
—
COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
MATHERR ADDRERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 2
Bit 1
STKERR
INT2EP
DS7000591F-page 63
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
ADCP9IF
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
PWM9IF
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
PWM1IE
ADCP12IE
—
—
—
—
—
—
—
—
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
PWM9IE
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE
ADCP3IE
ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2
SI2C1IP1
SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
SPI2EIP2
SPI2EIP1
SPI2EIP0
0044
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC20
00CC
—
—
ADCP8IP2 ADCP8IP1 ADCP8IP0
—
—
—
—
4440
Legend:
ADCP10IP2 ADCP10IP1 ADCP10IP0
—
MI2C2IP2 MI2C2IP1 MI2C2IP0
ADCP9IP2 ADCP9IP1 ADCP9IP0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
ADCP11IF ADCP10IF
ADCP11IE ADCP10IE ADCP9IE
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-8:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS610 DEVICES (CONTINUED)
SFR
Addr
Bit 15
IPC21
00CE
—
—
IPC23
00D2
—
PWM2IP2
IPC24
00D4
—
PWM6IP2
IPC25
00D6
—
IPC26
00D8
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
Legend:
Bit 14
Bit 13
Bit 10
Bit 9
Bit 8
Bit 7
—
—
—
—
Bit 11
—
—
—
PWM2IP1
PWM2IP0
—
PWM1IP2 PWM1IP1 PWM1IP0
—
—
—
—
—
—
—
—
4400
PWM6IP1
PWM6IP0
—
PWM5IP2 PWM5IP1 PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2
PWM3IP1
PWM3IP0
4444
AC2IP2
AC2IP1
AC2IP0
—
PWM9IP2 PWM9IP1 PWM9IP0
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2
PWM7IP1
PWM7IP0
4444
—
—
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0044
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 5
Bit 4
ADCP12IP2 ADCP12IP1 ADCP12IP0
Bit 3
—
Bit 2
Bit 1
Bit 0
All
Resets
Bit 12
ADCP11IP2 ADCP11IP1 ADCP11IP0 0044
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 64
TABLE 4-8:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
INTCON1 0080
NSTDIS
OVAERR
INTCON2 0082
ALTIVT
DISI
—
—
—
OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OVATE
OVBTE
COVTE
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
Bit 2
MATHERR ADDRERR STKERR
Bit 0
All
Resets
OSCFAIL
—
0000
INT1EP
INT0EP
0000
Bit 1
DS7000591F-page 65
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
PWM1IF
ADCP12IF
—
—
—
—
—
—
—
—
—
—
—
ADCP8IF
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
PWM8IF
PWM7IF
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF ADCP3IF ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
—
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE
—
—
—
—
—
—
—
—
—
—
—
ADCP8IE
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
PWM8IE
PWM7IE
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP2
U1RXIP1
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC20
00CC
—
—
—
—
—
—
—
—
—
ADCP8IP2 ADCP8IP1 ADCP8IP0
—
—
—
—
0040
Legend:
PWM1IE ADCP12IE
MI2C2IP2 MI2C2IP1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2EIP2 SPI2EIP1 SPI2EIP0
0044
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-9:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS608 (CONTINUED)
SFR
Addr
Bit 15
IPC21
00CE
—
IPC23
00D2
—
PWM2IP2 PWM2IP1
IPC24
00D4
—
PWM6IP2 PWM6IP1
IPC25
00D6
—
AC2IP2
IPC26
00D8
—
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
—
—
Bit 10
Bit 9
—
—
PWM2IP0
—
PWM1IP2 PWM1IP1
—
—
PWM6IP0
—
PWM5IP2 PWM5IP1
AC2IP1
AC2IP0
—
—
—
—
—
—
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
0040
—
—
—
—
4400
Bit 7
—
—
PWM1IP0
—
—
—
—
PWM5IP0
—
PWM4IP2
PWM4IP1
PWM4IP0
—
PWM3IP2 PWM3IP1 PWM3IP0
4444
—
—
—
PWM8IP2
PWM8IP1
PWM8IP0
—
PWM7IP2 PWM7IP1 PWM7IP0
4044
—
—
—
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
—
—
—
—
—
—
—
4400
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0044
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
Bit 3
Bit 8
ADCP12IP2 ADCP12IP1 ADCP12IP1
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 66
TABLE 4-9:
File
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
OVAERR OVBERR COVAERR COVBERR
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
SFTACERR DIV0ERR
Bit 5
—
Bit 4
Bit 3
MATHERR ADDRERR
Bit 2
Bit 1
Bit 0
All
Resets
INTCON1 0080
NSTDIS
OVATE
OVBTE
COVTE
STKERR
OSCFAIL
—
0000
INTCON2 0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
DS7000591F-page 67
IFS0
0084
—
—
ADIF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
OC3IF
—
—
—
—
INT1IF
CNIF
AC1IF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
IC4IF
IC3IF
—
—
—
SPI2IF
SPI2EIF
0000
IFS3
008A
—
—
—
—
—
QEI1IF
PSEMIF
—
—
INT4IF
INT3IF
—
—
MI2C2IF
SI2C2IF
—
0000
IFS4
008C
—
—
—
—
QEI2IF
—
PSESMIF
—
—
—
—
—
—
U2EIF
U1EIF
—
0000
IFS5
008E PWM2IF
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IFS6
0090 ADCP1IF ADCP0IF
—
—
—
—
AC4IF
AC3IF
AC2IF
—
—
—
PWM6IF
PWM5IF
PWM4IF
PWM3IF
0000
IFS7
0092
—
—
—
—
—
—
—
—
—
—
ADCP7IF
ADCP6IF
ADCP5IF
ADCP4IF
ADCP3IF
ADCP2IF
0000
IEC0
0094
—
—
ADIE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
OC3IE
—
—
—
—
INT1IE
CNIE
AC1IE
MI2C1IE
SI2C1IE
0000
IEC2
0098
—
—
—
—
—
—
—
—
—
IC4IE
IC3IE
—
—
—
SPI2IE
SPI2EIE
0000
IEC3
009A
—
—
—
—
—
QEI1IE
PSEMIE
—
—
INT4IE
INT3IE
—
—
MI2C2IE
SI2C2IE
—
0000
IEC4
009C
—
—
—
—
QEI2IE
—
PSESMIE
—
—
—
—
—
—
U2EIE
U1EIE
—
0000
IEC5
009E PWM2IE PWM1IE ADCP12IE
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
IEC6
00A0 ADCP1IE ADCP0IE
—
—
—
—
AC4IE
AC3IE
AC2IE
—
—
—
PWM6IE
PWM5IE
PWM4IE
PWM3IE
0000
IEC7
00A2
—
—
—
—
—
—
—
—
—
—
ADCP7IE
ADCP6IE
ADCP5IE
ADCP4IE ADCP3IE ADCP2IE
0000
IPC0
00A4
—
T1IP2
T1IP1
T1IP0
—
OC1IP2
OC1IP1
OC1IP0
—
IC1IP2
IC1IP1
IC1IP0
—
INT0IP2
INT0IP1
INT0IP0
4444
IPC1
00A6
—
T2IP2
T2IP1
T2IP0
—
OC2IP2
OC2IP1
OC2IP0
—
IC2IP2
IC2IP1
IC2IP0
—
—
—
—
4440
IPC2
00A8
—
U1RXIP0
—
SPI1IP2
SPI1IP1
SPI1IP0
—
SPI1EIP2
SPI1EIP1
SPI1EIP0
—
T3IP2
T3IP1
T3IP0
4444
IPC3
00AA
—
—
—
—
—
—
—
—
—
ADIP2
ADIP1
ADIP0
—
U1TXIP2
U1TXIP1
U1TXIP0
0044
IPC4
00AC
—
CNIP2
CNIP1
CNIP0
—
AC1IP2
AC1IP1
AC1IP0
—
MI2C1IP2
MI2C1IP1
MI2C1IP0
—
SI2C1IP2 SI2C1IP1 SI2C1IP0
4444
IPC5
00AE
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1IP2
INT1IP1
INT1IP0
0004
IPC6
00B0
—
T4IP2
T4IP1
T4IP0
—
OC4IP2
OC4IP1
OC4IP0
—
OC3IP2
OC3IP1
OC3IP0
—
—
—
—
4440
IPC7
00B2
—
U2TXIP2
U2TXIP1
U2TXIP0
—
U2RXIP2
U2RXIP1
U2RXIP0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
T5IP1
T5IP0
4444
IPC8
00B4
—
—
—
—
—
—
—
—
—
SPI2IP2
SPI2IP1
SPI2IP0
—
IPC9
00B6
—
—
—
—
—
IC4IP2
IC4IP1
IC4IP0
—
IC3IP2
IC3IP1
IC3IP0
—
—
—
—
0440
IPC12
00BC
—
—
—
—
—
MI2C2IP2
MI2C2IP1
MI2C2IP0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
—
—
—
—
0440
IPC13
00BE
—
—
—
—
—
INT4IP2
INT4IP1
INT4IP0
—
INT3IP2
INT3IP1
INT3IP0
—
—
—
—
0440
IPC14
00C0
—
—
—
—
—
QEI1IP2
QEI1IP1
QEI1IP0
—
PSEMIP2
PSEMIP1
PSEMIP0
—
—
—
—
0440
IPC16
00C4
—
—
—
—
—
U2EIP2
U2EIP1
U2EIP0
—
U1EIP2
U1EIP1
U1EIP0
—
—
—
—
0440
IPC18
00C8
—
QEI2IP2
QEI2IP1
QEI2IP0
—
—
—
—
—
PSESMIP2 PSESMIP1 PSESMIP0
—
—
—
—
4040
IPC21
00CE
—
—
—
—
—
—
—
—
—
ADCP12IP2 ADCP12IP1 ADCP12IP0
—
—
—
—
0040
Legend:
PWM1IF ADCP12IF
U1RXIP2 U1RXIP1
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2EIP2 SPI2EIP1 SPI2EIP0
0044
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-10:
File
Name
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ32GS606 DEVICES (CONTINUED)
SFR
Addr
Bit 15
IPC23
00D2
—
IPC24
00D4
—
IPC25
00D6
—
AC2IP2
AC2IP1
IPC26
00D8
—
—
—
IPC27
00DA
—
ADCP1IP2 ADCP1IP1 ADCP1IP0
—
IPC28
00DC
—
ADCP5IP2 ADCP5IP1 ADCP5IP0
—
IPC29
00DE
—
—
—
—
—
—
—
INTTREG 00E0
—
—
—
—
ILR3
ILR2
ILR1
Legend:
Bit 14
Bit 13
Bit 12
Bit 9
Bit 8
Bit 6
Bit 5
Bit 1
Bit 0
All
Resets
—
—
—
4400
Bit 10
PWM2IP2 PWM2IP1 PWM2IP0
—
PWM1IP2
PWM1IP1 PWM1IP0
—
—
PWM6IP2 PWM6IP1 PWM6IP0
—
PWM5IP2
PWM5IP1 PWM5IP0
—
PWM4IP2
AC2IP0
—
—
—
—
—
—
—
—
—
—
—
—
ADCP0IP2 ADCP0IP1 ADCP0IP0
—
ADCP4IP2 ADCP4IP1 ADCP4IP0
—
ADCP3IP2 ADCP3IP1 ADCP3IP0
—
ADCP2IP2 ADCP2IP1 ADCP2IP0
4444
—
—
ADCP7IP2 ADCP7IP1 ADCP7IP0
—
ADCP6IP2 ADCP6IP1 ADCP6IP0
0004
ILR0
—
VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 2
Bit 11
Bit 4
Bit 3
—
—
—
PWM4IP1
PWM4IP0
—
—
—
—
—
—
—
4000
AC4IP2
AC4IP1
AC4IP0
—
AC3IP2
AC3IP1
AC3IP0
0044
—
—
—
—
—
—
—
4400
PWM3IP2 PWM3IP1 PWM3IP0
4444
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 68
TABLE 4-10:
File
Name
SFR
Addr
TIMERS REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
T32
—
TCS
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
—
—
TCS
—
TMR4
0114
Timer4 Register
TMR5HLD
0116
Timer5 Holding Register (for 32-bit timer operations only)
xxxx
TMR5
0118
Timer5 Register
0000
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
T32
—
TCS
—
0000
T5CON
0120
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS1 TCKPS0
—
—
TCS
—
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
ICI1
ICI0
ICOV
ICBNE
ICM2
ICM1
ICM0
0000
Legend:
—
TSIDL
—
—
—
—
—
—
FFFF
TGATE
TCKPS1 TCKPS0
—
TSYNC
TCS
—
0000
0000
FFFF
0000
0000
0000
FFFF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
File
Name
TON
0000
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Input 1 Capture Register
—
ICTMR
xxxx
Input 2 Capture Register
DS7000591F-page 69
—
—
ICSIDL
—
—
—
—
—
—
ICSIDL
—
—
—
—
—
—
ICSIDL
—
—
—
—
—
ICTMR
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
Input 3 Capture Register
—
ICTMR
xxxx
Input 4 Capture Register
—
ICTMR
xxxx
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-11:
File
Name
SFR
Addr
OUTPUT COMPARE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
—
—
—
OCSIDL
—
—
OCSIDL
—
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC4CON
0196
Legend:
—
—
—
All
Resets
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
xxxx
Output Compare 4 Register
—
Bit 0
xxxx
—
Output Compare 4 Secondary Register
—
Bit 1
xxxx
0192
—
Bit 2
xxxx
—
0194
OCSIDL
Bit 3
xxxx
OC4R
—
Bit 4
xxxx
—
OC4RS
—
Bit 5
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
xxxx
xxxx
—
—
OCFLT
OCTSEL
OCM2
OCM1
OCM0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
File
Name
QEI1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
QEI1CON
01E0
CNTERR
—
QEISIDL
INDX
UPDN
QEIM2 QEIM1 QEIM0
DFLT1CON
01E2
—
—
—
—
—
IMV1
Bit 9
IMV0
Bit 8
CEID
All
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWPAB
PCDOUT
TQGATE
TQCKPS1
TQCKPS0
POSRES
TQCS
UPDN_SRC
0000
QEOUT
QECK2
QECK1
QECK0
—
—
—
—
0000
POS1CNT
01E4
Position Counter
0000
MAX1CNT
01E6
Maximum Count
FFFF
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009-2014 Microchip Technology Inc.
TABLE 4-15:
File
Name
QEI2CON
QEI2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
01F0
CNTERR
—
QEISIDL
INDX
UPDN
QEIM2 QEIM1 QEIM0
—
—
—
—
—
DFLT2CON 01F2
IMV1
Bit 9
IMV0
Bit 8
CEID
All
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SWPAB
PCDOUT
TQGATE
TQCKPS1
TQCKPS0
POSRES
TQCS
UPDN_SRC
0000
QEOUT
QECK2
QECK1
QECK0
—
—
—
—
0000
POS2CNT
01F4
Position Counter
0000
MAX2CNT
01F6
Maximum Count
FFFF
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 70
TABLE 4-13:
File
Name
HIGH-SPEED PWM REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
PTCON
0400
PTEN
—
PTSIDL
SESTAT
SEIEN
EIPU
SYNCPOL
SYNCOEN
SYNCEN
PTCON2
0402
—
—
—
—
—
—
—
—
—
PTPER
0404
SEVTCMP
0406
MDC
040A
STCON
040E
—
—
—
SESTAT
SEIEN
EIPU
SYNCPOL
SYNCOEN
SYNCEN
STCON2
0410
—
—
—
—
—
—
—
—
—
STPER
0412
Legend:
Bit 4
SYNCSRC2 SYNCSRC1 SYNCSRC0
—
—
—
Bit 3
SEVTPS3
Bit 2
Bit 0
All
Resets
SEVTPS0
0000
Bit 1
SEVTPS2 SEVTPS1
—
PCLKDIV
0000
FFF8
SEVTCMP
—
—
—
MDC
—
—
—
SEVTPS3
SEVTPS2 SEVTPS1 SEVTPS0
0000
—
PCLKDIV
0000
FFF8
SSEVTCMP
—
—
—
—
—
0000
0000
SYNCSRC2 SYNCSRC1 SYNCSRC0
STPER
041A CHPCLKEN
CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
—
—
—
0000
—
—
—
0000
Bit 0
All
Resets
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17:
File
Name
Bit 5
PTPER
SSEVTCMP 0414
CHOP
Bit 6
SFR
Addr
HIGH-SPEED PWM GENERATOR 1 REGISTER MAP
Bit 11
Bit 10
PWMCON1 0420 FLTSTAT CLSTAT TRGSTAT FLTIEN
CLIEN
TRGIEN
ITB
MDCS
—
IOCON1
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0 FLTDAT1
FLTDAT0
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC1
FLTSRC0
0422
Bit 15
PENH
Bit 14
PENL
Bit 13
POLH
Bit 12
POLL
FCLCON1 0424 IFLTMOD CLSRC4 CLSRC3 CLSRC2
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
DTC1
DTC0
DTCP
FLTSRC2
Bit 4
Bit 3
Bit 2
Bit 1
MTBS
CAM
XPRES
IUE
0000
CLDAT1
CLDAT0
SWAP
OSYNC
0000
FLTPOL
FLTMOD1
FLTMOD0
0000
PDC1
0426
PDC1
0000
PHASE1
0428
PHASE1
0000
DTR1
042A
—
—
DTR1
0000
ALTDTR1
042C
—
—
ALTDTR1
0000
SDC1
042E
SDC1
SPHASE1 0430
TRIG1
0432
0000
TRGCMP
TRGCON1 0434 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG1
0000
SPHASE1
—
—
—
—
—
DTM
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
DS7000591F-page 71
0436
STRGCMP
—
—
—
0000
PWMCAP1 0438
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
LEBCON1 043A
LEBDLY1
043C
PHR
PHF
PLR
PLF
—
—
—
—
—
—
AUXCON1 043E HRPDIS HRDDIS
Legend:
FLTLEBEN
CLLEBEN
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-16:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 2 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
POLH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
0000
FLTMOD1
FLTMOD0
0000
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON2
0442
FCLCON2
0444 IFLTMOD CLSRC4 CLSRC3 CLSRC2
PDC2
0446
PDC2
0000
PHASE2
0448
PHASE2
0000
DTR2
044A
—
—
DTR2
0000
ALTDTR2
044C
—
—
ALTDTR2
0000
SDC2
044E
SDC2
SPHASE2
0450
SPHASE2
TRIG2
0452
TRGCON2
0454 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG2
0456
STRGCMP
—
—
—
0000
PWMCAP2 0458
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
0000
TRGCMP
LEBCON2
045A
PHR
PHF
PLR
PLF
LEBDLY2
045C
—
—
—
—
AUXCON2
045E HRPDIS
HRDDIS
—
—
Legend:
0000
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 72
TABLE 4-18:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 3 REGISTER MAP
Bit 15
Bit 14
Bit 13
PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT
PENL
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON3
0462
FCLCON3
0464 IFLTMOD CLSRC4
PDC3
0466
PDC3
0000
PHASE3
0468
PHASE3
0000
DTR3
046C
—
—
DTR3
0000
ALTDTR3
046C
—
—
ALTDTR3
0000
SDC3
046E
SDC3
SPHASE3
0470
SPHASE3
TRIG3
0472
TRGCON3
0474 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG3
0476
STRGCMP
—
—
—
0000
PWMCAP3
0478
PWMCAP
—
—
—
0000
LEBCON3
047A
PHR
PHF
PLR
PLF
BPHL
BPLH
BPLL
0000
LEBDLY3
047C
—
—
—
—
—
—
—
0000
AUXCON3
047E
HRPDIS
HRDDIS
—
—
Legend:
PENH
Bit 12
FLTSRC3
0000
0000
TRGCMP
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
—
DTM
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
0000
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS7000591F-page 73
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-19:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 4 REGISTER MAP
Bit 15
PWMCON4 0480 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON4
0482
FCLCON4
0484 IFLTMOD CLSRC4
PDC4
0486
PDC4
0000
PHASE4
0488
PHASE4
0000
DTR4
048A
—
—
DTR4
0000
ALTDTR4
048A
—
—
ALTDTR4
0000
SDC4
048E
SDC4
SPHASE4
0490
SPHASE4
TRIG4
0492
TRGCON4
0494 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG4
0496
STRGCMP
—
—
—
0000
PWMCAP4 0498
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
0000
0000
TRGCMP
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON4
049A
PHR
PHF
PLR
PLF
LEBDLY4
049C
—
—
—
—
AUXCON4
049E
HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
0000
0000
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 74
TABLE 4-20:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 5 REGISTER MAP
Bit 15
PWMCON5 04A0 FLTSTAT
PENH
Bit 14
Bit 13
Bit 12
CLSTAT TRGSTAT FLTIEN
PENL
POLH
POLL
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON5
04A2
FCLCON5
04A4 IFLTMOD CLSRC4 CLSRC3 CLSRC2
PDC5
04A6
PDC5
0000
PHASE5
04A8
PHASE5
0000
DTR5
04AA
—
—
DTR5
0000
ALTDTR5
04AA
—
—
ALTDTR5
0000
SDC5
04AE
SDC5
SPHASE5
04B0
SPHASE5
TRIG5
04B2
0000
TRGCMP
TRGCON5 04B4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG5
0000
—
—
—
—
—
DTM
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
0000
0000
04B6
STRGCMP
—
—
—
0000
PWMCAP5 04B8
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
LEBCON5
04BA
PHR
PHF
PLR
PLF
LEBDLY5
04BC
—
—
—
—
HRDDIS
—
—
AUXCON5 04BE HRPDIS
Legend:
FLTLEBEN
CLLEBEN
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS7000591F-page 75
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-21:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 6 REGISTER MAP
Bit 15
PWMCON6 04C0 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON6
04C2
FCLCON6
04C4 IFLTMOD CLSRC4
PDC6
04C6
PDC6
0000
PHASE6
04C8
PHASE6
0000
DTR6
04CA
—
—
DTR6
0000
ALTDTR6
04CA
—
—
ALTDTR6
0000
SDC6
04CE
SDC6
SPHASE6
04D0
SPHASE6
TRIG6
04D2
TRGCON6
04D4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG6
04D6
STRGCMP
—
—
—
0000
PWMCAP6 04D8
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
0000
0000
TRGCMP
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON6
04DA
PHR
PHF
PLR
PLF
LEBDLY6
04DC
—
—
—
—
AUXCON6
04DE HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
0000
0000
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 76
TABLE 4-22:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 7 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES)
Bit 15
PWMCON7 04E0 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
POLH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
0000
FLTMOD1
FLTMOD0
0000
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON7
04E2
FCLCON7
04E4 IFLTMOD CLSRC4
PDC7
04E6
PDC7
0000
PHASE7
04E8
PHASE7
0000
DTR7
04EA
—
—
DTR7
0000
ALTDTR7
04EA
—
—
ALTDTR7
0000
SDC7
04EE
SDC7
SPHASE7
04F0
SPHASE7
TRIG7
04F2
TRGCON7
04F4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG7
04F6
STRGCMP
—
—
—
0000
PWMCAP7 04F8
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
CLSRC3 CLSRC2
0000
0000
TRGCMP
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON7
04FA
PHR
PHF
PLR
PLF
LEBDLY7
04FC
—
—
—
—
AUXCON7
04FE HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
0000
0000
DS7000591F-page 77
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-23:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 8 REGISTER MAP (EXCLUDES dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES)
Bit 15
Bit 14
Bit 13
PWMCON8 0500 FLTSTAT CLSTAT TRGSTAT
PENH
PENL
POLH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
Bit 0
All
Resets
XPRES
IUE
0000
SWAP
OSYNC
0000
FLTMOD1
FLTMOD0
0000
Bit 2
Bit 1
MTBS
CAM
CLDAT1
CLDAT0
FLTPOL
IOCON8
0502
FCLCON8
0504 IFLTMOD CLSRC4 CLSRC3
PDC8
0506
PDC8
0000
PHASE8
0508
PHASE8
0000
DTR8
050A
—
—
DTR8
0000
ALTDTR8
050A
—
—
ALTDTR8
0000
SDC8
050E
SDC8
SPHASE8
0510
SPHASE8
TRIG8
0512
TRGCON8
0514 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG8
0516
STRGCMP
—
—
—
0000
PWMCAP8 0518
PWMCAP
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPLEN
0000
0000
0000
TRGCMP
—
FLTLEBEN
—
CLLEBEN
—
—
—
—
LEBCON8
051A
PHR
PHF
PLR
PLF
LEBDLY8
051C
—
—
—
—
AUXCON8
051E HRPDIS HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DTM
—
—
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
—
—
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
BCH
BCL
BPHH
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
0000
0000
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 78
TABLE 4-24:
File
Name
SFR
Addr
HIGH-SPEED PWM GENERATOR 9 REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
Bit 15
PWMCON9 0520 FLTSTAT
PENH
Bit 14
Bit 13
CLSTAT TRGSTAT
PENL
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DTC1
DTC0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
FLTIEN
CLIEN
TRGIEN
ITB
MDCS
DTCP
—
MTBS
CAM
XPRES
IUE
0000
POLH
POLL
PMOD1
PMOD0
OVRENH
OVRENL
OVRDAT1 OVRDAT0
FLTDAT1
FLTDAT0
CLDAT1
CLDAT0
SWAP
OSYNC
0000
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL
CLMOD
FLTSRC4 FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL
FLTMOD1
FLTMOD0
0000
IOCON9
0522
FCLCON9
0524 IFLTMOD CLSRC4
PDC9
0526
PDC9
0000
PHASE9
0528
PHASE9
0000
DTR9
052A
—
—
DTR9
0000
ALTDTR9
052A
—
—
ALTDTR9
0000
SDC9
052E
SDC9
0000
SPHASE9
0530
SPHASE9
0000
TRIG9
0532
TRGCMP
TRGCON9
0534 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0
STRIG9
0536
—
—
—
—
DTM
0000
—
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
STRGCMP
PWMCAP9 0538
0000
PWMCAP
LEBCON9
053A
PHR
PHF
PLR
PLF
FLTLEBEN
CLLEBEN
—
—
LEBDLY9
053C
—
—
—
—
AUXCON9
053E HRPDIS
HRDDIS
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
LEB
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
—
0000
—
BCH
BCL
BPHH
—
—
—
0000
BPHL
BPLH
BPLL
0000
—
—
—
0000
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
0000
DS7000591F-page 79
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-25:
I2C1 REGISTER MAP
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
I2C1STAT 0208 ACKSTAT TRSTAT
GCSTAT
ADD10
IWCOL
I2COV
I2C1ADD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
D_A
P
S
R_W
RBF
TBF
0000
—
—
—
BCL
020A
—
—
—
—
—
—
I2C1 Address Register
0000
I2C1MSK 020C
—
—
—
—
—
—
I2C1 Address Mask Register
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-27:
File
Name
I2C2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
I2C2RCV
0210
—
—
—
—
—
—
—
—
I2C2 Receive Register
I2C2TRN
0212
—
—
—
—
—
—
—
—
I2C2 Transmit Register
I2C2BRG
0214
—
—
—
—
—
—
—
I2C2CON
0216
I2CEN
—
Bit 2
Bit 1
Bit 0
All
Resets
0000
00FF
Baud Rate Generator Register
0000
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
I2C2STAT 0218 ACKSTAT TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
I2C2ADD
1000
0000
021A
—
—
—
—
—
—
I2C2 Address Register
0000
I2C2MSK
021C
—
—
—
—
—
—
I2C2 Address Mask Register
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 80
TABLE 4-26:
File Name
SFR
Addr.
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
—
USIDL
IREN
Bit 11
Bit 10
RTSMD
—
Bit 9
Bit 8
UEN1
UEN0
UTXBF
TRMT
Bit 7
Bit 6
WAKE
LPBACK
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
0110
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1 UTXINV UTXISEL0
U1TXREG
0224
—
—
—
—
—
—
—
UART1 Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
UART1 Receive Register
0000
U1BRG
0228
Legend:
UTXBRK UTXEN
Baud Rate Generator Prescaler
0000
SFR
Addr
UART2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U2TXREG
0234
—
—
—
—
—
—
—
U2RXREG
0236
—
—
—
—
—
—
—
U2BRG
0238
Legend:
URXISEL1 URXISEL0
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-29:
File
Name
—
Bit 7
Bit 6
WAKE
LPBACK
URXISEL1 URXISEL0
Baud Rate Generator Prescaler
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 0
All
Resets
PDSEL0
STSEL
0000
OERR
URXDA
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ABAUD
URXINV
BRGH
PDSEL1
ADDEN
RIDLE
PERR
FERR
0110
UART2 Transmit Register
xxxx
UART2 Receive Register
0000
0000
DS7000591F-page 81
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-28:
File Name
SPI1 REGISTER MAP
SFR
Addr.
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
SPI1CON1
0242
—
—
—
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
SPI1BUF
0248
Legend:
—
—
—
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
0000
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
FRMDLY
—
0000
—
0000
SPI2 REGISTER MAP
Bit 15
Bit 14
Bit 13
SPI2STAT
0260
SPIEN
—
SPISIDL
SPI2CON1
0262
—
—
—
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
Legend:
—
DISSCK DISSDO
Bit 10
SPI1 Transmit and Receive Buffer Register
SFR
Addr.
SPI2BUF
Bit 11
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-31:
File Name
Bit 12
0268
Bit 12
Bit 11
Bit 10
—
—
—
DISSCK DISSDO MODE16
—
—
—
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
—
—
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
SMP
CKE
SSEN
CKP
MSTEN
SPRE2
SPRE1
SPRE0
PPRE1
PPRE0
0000
—
—
—
—
—
—
—
—
FRMDLY
—
0000
SPI2 Transmit and Receive Buffer Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 82
TABLE 4-30:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
EIE
ADPCFG
0302
ADPCFG2
0304
—
—
—
—
—
—
—
—
ADSTAT
0306
—
—
—
P12RDY
P11RDY
P10RDY
P9RDY
P8RDY
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1
SWTRG1
TRGSRC14
TRGSRC13
TRGSRC12
TRGSRC11
TRGSRC10
IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03
TRGSRC02
ADCPC1
030C IRQEN3
PEND3
SWTRG3
TRGSRC34
TRGSRC33
TRGSRC32
TRGSRC31
TRGSRC30
IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
ADCPC2
030E
IRQEN5
PEND5
SWTRG5
TRGSRC54
TRGSRC53
TRGSRC52
TRGSRC51
TRGSRC50
IRQEN4
PEND4
SWTRG4
TRGSRC44
ADCPC3
0310
IRQEN7
PEND7
SWTRG7
TRGSRC74
TRGSRC73
TRGSRC72
TRGSRC71
TRGSRC70
IRQEN6
PEND6
SWTRG6
ADCPC4
0312
IRQEN9
PEND9
SWTRG9
TRGSRC94
TRGSRC93
TRGSRC92
TRGSRC94
TRGSRC90
IRQEN8
PEND8
SWTRG8
Bit 6
Bit 5
Bit 4
ORDER SEQSAMP ASYNCSAMP
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
ADCS2
ADCS1
ADCS0
0003
PCFG
0000
PCFG
P6RDY
P5RDY
P4RDY
P3RDY
0000
DS7000591F-page 83
P0RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC43
TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC64
TRGSRC63
TRGSRC62
TRGSRC61 TRGSRC640
0000
TRGSRC84
TRGSRC83
TRGSRC82
TRGSRC81
TRGSRC80
0000
ADCPC5
0314 IRQEN11 PEND11 SWTRG11 TRGSRC114 TRGSRC113 TRGSRC112 TRGSRC111 TRGSRC110 IRQEN10 PEND10 SWTRG10 TRGSRC104 TRGSRC103 TRGSRC102 TRGSRC101 TRGSRC100
0000
ADCPC6
0316
0000
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10 0354
ADC Data Buffer 10
xxxx
ADCBUF11 0356
ADC Data Buffer 11
xxxx
ADCBUF12 0358
ADC Data Buffer 12
xxxx
ADCBUF13 035A
ADC Data Buffer 13
xxxx
ADCBUF14 035C
ADC Data Buffer 14
xxxx
ADCBUF15 035E
ADC Data Buffer 15
xxxx
ADCBUF16 0360
ADC Data Buffer 16
xxxx
ADCBUF17 0362
ADC Data Buffer 17
xxxx
ADCBUF18 0364
ADC Data Buffer 18
xxxx
ADCBUF19 0366
ADC Data Buffer 19
xxxx
ADCBUF20 0368
ADC Data Buffer 20
xxxx
ADCBUF21 036A
ADC Data Buffer 21
xxxx
Legend:
P7RDY
P2RDY
P1RDY
ADBASE
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
IRQEN12 PEND12 SWTRG12 TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-32:
File
Name
SFR
Addr
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES ONLY (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ADCBUF22 036C
ADC Data Buffer 22
xxxx
ADCBUF23 036E
ADC Data Buffer 23
xxxx
ADCBUF24 0370
ADC Data Buffer 24
xxxx
ADCBUF25 0372
ADC Data Buffer 25
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 84
TABLE 4-32:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
DS7000591F-page 85
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
ADPCFG
0302
ADPCFG2
0304
—
—
—
—
—
—
—
—
—
—
ADSTAT
0306
—
—
—
P12RDY
—
—
—
P8RDY
P7RDY
P6RDY
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1 SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10
IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03
TRGSRC02
ADCPC1
030C
IRQEN3
PEND3 SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30
IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
ADCPC2
030E
IRQEN5
PEND5 SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50
IRQEN4
PEND4
SWTRG4
TRGSRC44
ADCPC3
0310
IRQEN7
PEND7 SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70
IRQEN6
PEND6
SWTRG6
ADCPC4
0312
—
—
—
—
—
—
—
—
IRQEN8
PEND8
ADCPC6
0316
—
—
—
—
—
—
—
—
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10
0354
ADC Data Buffer 10
xxxx
ADCBUF11
0356
ADC Data Buffer 11
xxxx
ADCBUF12
0358
ADC Data Buffer 12
xxxx
ADCBUF13
035A
ADC Data Buffer 13
xxxx
ADCBUF14
035C
ADC Data Buffer 14
xxxx
ADCBUF15
035E
ADC Data Buffer 15
xxxx
ADCBUF16
0360
ADC Data Buffer 16
xxxx
ADCBUF17
0362
ADC Data Buffer 17
xxxx
ADCBUF24
0370
ADC Data Buffer 24
xxxx
ADCBUF25
0372
ADC Data Buffer 25
xxxx
Legend:
Bit 7
EIE
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
ASYNCSAMP
—
ADCS2
ADCS1
ADCS0
0003
—
—
—
—
P5RDY
P4RDY
P3RDY
P2RDY
Bit 5
ORDER SEQSAMP
PCFG
0000
PCFG
P1RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC43
TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC64
TRGSRC63
TRGSRC62
TRGSRC61 TRGSRC640
0000
SWTRG8
TRGSRC84
TRGSRC83
TRGSRC82
TRGSRC81
TRGSRC80
0000
IRQEN12 PEND12 SWTRG12
TRGSRC124
TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
0000
ADBASE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
P0RDY
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-33:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS606 AND dsPIC33FJ64GS606 DEVICES
2009-2014 Microchip Technology Inc.
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
ADPCFG
0302
ADSTAT
0306
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1
SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03
TRGSRC02
ADCPC1
030C
IRQEN3
PEND3
SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2
PEND2
SWTRG2
TRGSRC24
TRGSRC23
ADCPC2
030E
IRQEN5
PEND5
SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4
PEND4
SWTRG4
TRGSRC44
ADCPC3
0310
IRQEN7
PEND7
SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6
PEND6
SWTRG6
TRGSRC64
ADCPC6
0316
—
—
IRQEN12 PEND12
SWTRG12
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10
0354
ADC Data Buffer 10
xxxx
ADCBUF11
0356
ADC Data Buffer 11
xxxx
ADCBUF12
0358
ADC Data Buffer 12
xxxx
ADCBUF13 035A
ADC Data Buffer 13
xxxx
ADCBUF14 035C
ADC Data Buffer 14
xxxx
ADCBUF15 035E
ADC Data Buffer 15
xxxx
ADCBUF24
0370
ADC Data Buffer 24
xxxx
ADCBUF25
0372
ADC Data Buffer 25
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 7
Bit 6
EIE
ORDER
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
ADCS2
ADCS1
ADCS0
0003
P3RDY
P2RDY
P1RDY
P0RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC43
TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC63
TRGSRC62
TRGSRC61 TRGSRC640
0000
TRGSRC124 TRGSRC123 TRGSRC122 TRGSRC121 TRGSRC120
0000
Bit 4
SEQSAMP ASYNCSAMP
PCFG
—
—
—
P12RDY
—
—
—
—
P7RDY
0000
P6RDY
P5RDY
P4RDY
ADBASE
—
—
—
—
—
—
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 86
TABLE 4-34:
File
Name
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ32GS406 AND dsPIC33FJ64GS406 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADCON
0300
ADON
—
ADSIDL
SLOWCLK
—
GSWTRG
—
FORM
ADPCFG
0302
ADSTAT
0306
ADBASE
0308
ADCPC0
030A
IRQEN1
PEND1
SWTRG1 TRGSRC14 TRGSRC13 TRGSRC12 TRGSRC11 TRGSRC10 IRQEN0
PEND0
SWTRG0
TRGSRC04
TRGSRC03 TRGSRC02
ADCPC1
030C
IRQEN3
PEND3
SWTRG3 TRGSRC34 TRGSRC33 TRGSRC32 TRGSRC31 TRGSRC30 IRQEN2
PEND2
SWTRG2
TRGSRC24
ADCPC2
030E
IRQEN5
PEND5
SWTRG5 TRGSRC54 TRGSRC53 TRGSRC52 TRGSRC51 TRGSRC50 IRQEN4
PEND4
SWTRG4
ADCPC3
0310
IRQEN7
PEND7
SWTRG7 TRGSRC74 TRGSRC73 TRGSRC72 TRGSRC71 TRGSRC70 IRQEN6
PEND6
SWTRG6
ADCBUF0
0340
ADC Data Buffer 0
xxxx
ADCBUF1
0342
ADC Data Buffer 1
xxxx
ADCBUF2
0344
ADC Data Buffer 2
xxxx
ADCBUF3
0346
ADC Data Buffer 3
xxxx
ADCBUF4
0348
ADC Data Buffer 4
xxxx
ADCBUF5
034A
ADC Data Buffer 5
xxxx
ADCBUF6
034C
ADC Data Buffer 6
xxxx
ADCBUF7
034E
ADC Data Buffer 7
xxxx
ADCBUF8
0350
ADC Data Buffer 8
xxxx
ADCBUF9
0352
ADC Data Buffer 9
xxxx
ADCBUF10
0354
ADC Data Buffer 10
xxxx
ADCBUF11
0356
ADC Data Buffer 11
xxxx
ADCBUF12
0358
ADC Data Buffer 12
xxxx
ADCBUF13
035A
ADC Data Buffer 13
xxxx
ADCBUF14
035C
ADC Data Buffer 14
xxxx
ADCBUF15
035E
ADC Data Buffer 15
xxxx
Legend:
Bit 7
EIE
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
ADCS2
ADCS1
ADCS0
0003
P3RDY
P2RDY
P1RDY
P0RDY
0000
—
0000
TRGSRC01
TRGSRC00
0000
TRGSRC23 TRGSRC22
TRGSRC21
TRGSRC20
0000
TRGSRC44
TRGSRC43 TRGSRC42
TRGSRC41
TRGSRC40
0000
TRGSRC64
TRGSRC63 TRGSRC62
TRGSRC61 TRGSRC640
0000
Bit 4
ORDER SEQSAMP ASYNCSAMP
PCFG
—
—
—
P12RDY
—
—
—
—
P7RDY
0000
P6RDY
P5RDY
P4RDY
ADBASE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS7000591F-page 87
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-35:
File
Name
SFR
Addr
DMA REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
DMA0CON 0380
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
DMA0REQ 0382
FORCE
—
—
—
—
—
—
—
Bit 4
Bit 3
Bit 2
—
—
AMODE1
AMODE0
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
Bit 0
All
Resets
MODE1
MODE0
0000
IRQSEL1
IRQSEL0
007F
Bit 1
DMA0STA
0384
STA
0000
DMA0STB
0386
STB
0000
DMA0PAD
0388
PAD
0000
DMA0CNT 038A
—
—
—
—
—
—
DMA1CON 038C
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
0000
—
—
—
—
—
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
IRQSEL1
IRQSEL0
007F
DMA1REQ 038E FORCE
CNT
0000
DMA1STA
0390
STA
0000
DMA1STB
0392
STB
0000
DMA1PAD
0394
PAD
DMA1CNT
0396
DMA2CON 0398
0000
—
—
—
—
—
—
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
0000
—
—
—
—
—
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
IRQSEL1
IRQSEL0
007F
DMA2REQ 039A FORCE
CNT
0000
DMA2STA
039C
STA
0000
DMA2STB
039E
STB
0000
DMA2PAD
03A0
PAD
0000
DMA2CNT 03A2
—
—
—
—
—
—
DMA3CON 03A4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
AMODE1
AMODE0
—
—
MODE1
MODE0
0000
—
—
—
—
—
—
—
—
IRQSEL6
IRQSEL5
IRQSEL4
IRQSEL3
IRQSEL2
IRQSEL1
IRQSEL0
007F
DMA3REQ 03A6 FORCE
DMA3STA
CNT
0000
03A8
STA
0000
DMA3STB 03AA
STB
0000
DMA3PAD 03AC
PAD
2009-2014 Microchip Technology Inc.
—
—
—
—
DMACS0
03E0
—
—
—
—
PWCOL3 PWCOL2 PWCOL1 PWCOL0
—
—
—
—
XWCOL3
XWCOL2
XWCOL1
XWCOL0
0000
DMACS1
03E2
—
—
—
—
LSTCH3
—
—
—
—
PPST3
PPST2
PPST1
PPST0
0F00
DSADR
03E4
Legend:
—
0000
DMA3CNT 03AE
—
LSTCH2
CNT
LSTCH1
LSTCH0
DSADR
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 88
TABLE 4-36:
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1) = 0 OR 1
Bit 2
Bit 1
Bit 0
All
Resets
—
—
WIN
0480
ICODE2
ICODE1
ICODE0
0000
FSA3
FSA2
FSA1
FSA0
0000
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
0000
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
0000
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
0000
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
C1CTRL1
0600
—
—
CSIDL
ABAT
—
REQOP2
REQOP1
REQOP0
C1CTRL2
0602
—
—
—
—
—
—
—
—
—
—
—
C1VEC
0604
—
—
—
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
—
ICODE6
ICODE5
ICODE4
ICODE3
C1FCTRL
0606
DMABS2
DMABS1
DMABS0
—
—
—
—
—
—
—
—
FSA4
C1FIFO
0608
—
—
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
—
—
FNRB5
C1INTF
060A
—
—
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
IVRIF
WAKIF
C1INTE
060C
—
—
—
—
—
—
—
—
IVRIE
WAKIE
C1EC
060E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0
0000
C1CFG1
0610
—
—
—
—
—
—
—
C1CFG2
0612
—
WAKFIL
—
—
—
SEG2PH2
SEG2PH1
C1FEN1
0614
—
Bit 7
Bit 6
Bit 5
OPMODE2 OPMODE1 OPMODE0
SJW1
SEG2PH0 SEG2PHTS
Bit 4
Bit 3
—
CANCAP
DNCNT
0000
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
0000
SAM
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
0000
FLTEN
FFFF
C1FMSKSEL1 0618
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK0
0000
C1FMSKSEL2 061A
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK1
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
0000
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-38:
File
Name
SFR
Addr
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1) = 0
Bit 15
0600061E
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 4
Bit 3
See definition when WIN = x
C1RXFUL1
0620
RXFUL
0000
C1RXFUL2
0622
RXFUL
0000
C1RXOVF1
0628
RXOVF
0000
C1RXOVF2
062A
RXOVF
0000
C1TR01CON 0630
TXEN1
TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI1 TX1PRI0
TXEN0
TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI1 TX0PRI0
0000
C1TR23CON 0632
TXEN3
TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI1 TX3PRI0
TXEN2
TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI1 TX2PRI0
0000
C1TR45CON 0634
TXEN5
TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI1 TX5PRI0
TXEN4
TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI1 TX4PRI0
0000
C1TR67CON 0636
TXEN7
TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI1 TX7PRI0
TXEN6
TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI1 TX6PRI0
0000
DS7000591F-page 89
C1RXD
0640
ECAN1 Received Data Word Register
xxxx
C1TXD
0642
ECAN1 Transmit Data Word Register
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-37:
File
Name
SFR
Addr
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1) = 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0600061E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
C1BUFPNT1
0620
F3BP3
F3BP2
F3BP1
F3BP0
F2BP3
F2BP2
F2BP1
F2BP0
F1BP3
F1BP2
F1BP1
F1BP0
F0BP3
F0BP2
F0BP1
F0BP0
0000
C1BUFPNT2
0622
F7BP3
F7BP2
F7BP1
F7BP0
F6BP3
F6BP2
F6BP1
F6BP0
F5BP3
F5BP2
F5BP1
F5BP0
F4BP3
F4BP2
F4BP1
F4BP0
0000
2009-2014 Microchip Technology Inc.
C1BUFPNT3
0624
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
F9BP3
F9BP2
F9BP1
F9BP0
F8BP3
F8BP2
F8BP1
F8BP0
0000
C1BUFPNT4
0626
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1 F12BP0
0000
C1RXM0SID
0630
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM0EID
0632
C1RXM1SID
0634
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM1EID
0636
C1RXM2SID
0638
SID1
SID0
—
MIDE
—
EID17
EID16
xxxx
C1RXM2EID
063A
C1RXF0SID
0640
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF0EID
0642
C1RXF1SID
0644
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF1EID
0646
C1RXF2SID
0648
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
C1RXF2EID
064A
C1RXF3SID
064C
C1RXF3EID
064E
C1RXF4SID
0650
C1RXF4EID
0652
C1RXF5SID
0654
C1RXF5EID
0656
C1RXF6SID
0658
C1RXF6EID
065A
C1RXF7SID
065C
C1RXF7EID
065E
C1RXF8SID
0660
C1RXF8EID
0662
C1RXF9SID
0664
C1RXF9EID
0666
C1RXF10SID
0668
C1RXF10EID
066A
C1RXF11SID
066C
Legend:
EID
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 90
TABLE 4-39:
File
Name
SFR
Addr
C1RXF11EID
066E
C1RXF12SID
0670
C1RXF12EID
0672
C1RXF13SID
0674
C1RXF13EID
0676
C1RXF14SID
0678
C1RXF14EID
067A
C1RXF15SID
067C
C1RXF15EID
067E
Legend:
ECAN1 REGISTER MAP WHEN WIN (C1CTRL1) = 1 (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
SID1
SID0
—
EXIDE
—
EID17
EID16
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
SID2
xxxx
EID
xxxx
ANALOG COMPARATOR CONTROL REGISTER MAP
File
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
—
DACOE
CMPCON1
0540
CMPON
—
CMPSIDL
—
—
—
CMPDAC1
0542
—
—
-
—
—
—
CMPCON2
0544
CMPON
—
CMPSIDL
—
—
—
CMPDAC2
0546
—
—
-
—
—
—
CMPCON3
0548
CMPON
—
CMPSIDL
—
—
—
CMPDAC3
054A
—
—
-
—
—
—
CMPCON4
054C
CMPON
—
CMPSIDL
—
—
—
054E
—
—
—
—
—
—
Legend:
Bit 5
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-40:
CMPDAC4
Bit 6
Bit 7
Bit 6
INSEL1 INSEL0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
EXTREF
—
CMPSTAT
—
CMPPOL
RANGE
0000
CMPSTAT
—
CMPPOL
RANGE
0000
CMPSTAT
—
CMPPOL
RANGE
0000
CMPSTAT
—
CMPPOL
RANGE
0000
CMREF
—
DACOE
INSEL1 INSEL0
EXTREF
—
DACOE
INSEL1 INSEL0
EXTREF
—
DACOE
INSEL1 INSEL0
EXTREF
—
0000
CMREF
—
0000
CMREF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
CMREF
0000
0000
DS7000591F-page 91
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-39:
File
Name
SFR
Addr
TRISA
02C0
PORTA
02C2
LATA
ODCA
Legend:
Bit 15
Bit 14
Bit 10
Bit 9
Bit 8
Bit 7
Bit 12
Bit 11
TRISA
—
—
—
TRISA
—
TRISA
C6FF
RA
—
—
—
RA
—
RA
xxxx
02C4
LATA
—
—
—
LATA
—
LATA
02C6
ODCA
—
—
—
ODCA
—
—
Bit 6
—
Bit 5
Bit 4
ODCA
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 13
0000
—
—
ODCA
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-42:
File
Name
PORTA REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
SFR
Addr
PORTA REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
02C0
TRISA
—
—
—
TRISA
—
—
—
—
—
—
—
—
—
C600
PORTA
02C2
RA
—
—
—
RA
—
—
—
—
—
—
—
—
—
xxxx
LATA
02C4
LATA
—
—
—
LATA
—
—
—
—
—
—
—
—
—
0000
ODCA
02C6
ODCA
—
—
—
ODCA
—
—
—
—
—
—
—
—
—
0000
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-43:
File
Name
SFR
Addr
PORTB REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TRISB
02C8
TRISB
PORTB
02CA
RB
xxxx
LATB
02CC
LATB
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
2009-2014 Microchip Technology Inc.
TABLE 4-44:
File
Name
SFR
Addr
FFFF
PORTC REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
02D0
TRISC
—
—
—
—
—
—
—
TRISC
—
F01E
PORTC
02D2
RC
—
—
—
—
—
—
—
RC
—
xxxx
LATC
02D4
LATC
—
—
—
—
—
—
—
LATC
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 92
TABLE 4-41:
File
Name
SFR
Addr
PORTC REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
02D0
TRISC
—
—
—
—
—
—
—
—
—
TRISC
—
F006
PORTC
02D2
RC
—
—
—
—
—
—
—
—
—
RC
—
xxxx
LATC
02D4
LATC
—
—
—
—
—
—
—
—
—
LATC
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-46:
File
Name
SFR
Addr
PORTC REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISC
02D0
TRISC
—
—
—
—
—
—
—
—
—
—
—
—
F000
PORTC
02D2
RC
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
LATC
02D4
LATC
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 2
Bit 1
Bit 0
All
Resets
TABLE 4-47:
File
Name
SFR
Addr
PORTD REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TRISD
02D8
TRISD
FFFF
PORTD
02DA
RD
xxxx
LATD
02DC
LATD
0000
ODCD
02DE
ODCD
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-48:
File
Name
PORTD REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
DS7000591F-page 93
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
TRISD
02D8
—
—
—
—
TRISD
0FFF
PORTD
02DA
—
—
—
—
RD
xxxx
LATD
02DC
—
—
—
—
LATD
0000
ODCD
02DE
—
—
—
—
ODCD
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
2009-2014 Microchip Technology Inc.
TABLE 4-45:
File
Name
PORTE REGISTER MAP FOR dsPIC33FJ32GS608/610 AND dsPIC33FJ64GS608/610 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISE
02E0
—
—
—
—
—
—
TRISE
03FF
PORTE
02E2
—
—
—
—
—
—
RE
xxxx
LATE
02E4
—
—
—
—
—
—
LATE
ODCE
02E6
—
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-50:
File
Name
Bit 9
—
Bit 8
Bit 7
Bit 6
Bit 5
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
ODCE
0000
PORTE REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TRISE
02E0
—
—
—
—
—
—
—
—
TRISE
00FF
PORTE
02E2
—
—
—
—
—
—
—
—
RE
xxxx
LATE
02E4
—
—
—
—
—
—
—
—
LATE
0000
ODCE
02E6
—
—
—
—
—
—
—
—
ODCE
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-51:
File
Name
Bit 7
2009-2014 Microchip Technology Inc.
Bit 15
Bit 14
TRISF
02E8
—
—
PORTF
02EA
—
—
LATF
02EC
—
ODCF
02EE
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
File
Name
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PORTF REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
SFR
Addr
TABLE 4-52:
Bit 6
Bit 13
Bit 12
Bit 8
Bit 7
Bit 6
Bit 10
Bit 9
TRISF
—
—
—
TRISF
30FF
RF
—
—
—
RF
xxxx
—
LATF
—
—
—
LATF
—
ODCF
—
—
—
ODCF
Bit 5
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Bit 11
0000
—
ODCF
—
0000
Bit 0
All
Resets
PORTF REGISTER MAP FOR dsPIC33FJ32GS608 AND dsPIC33FJ64GS608 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
TRISF
02E8
—
—
—
—
—
—
—
TRISF
01FF
PORTF
02EA
—
—
—
—
—
—
—
RF
xxxx
LATF
02EC
—
—
—
—
—
—
—
LATF
ODCF
02EE
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 8
Bit 7
ODCF
Bit 6
Bit 5
—
Bit 4
—
Bit 3
Bit 2
Bit 1
0000
ODCF
—
0000
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
DS7000591F-page 94
TABLE 4-49:
File
Name
PORTF REGISTER MAP FOR dsPIC33FJ32GS406/606 AND dsPIC33FJ64GS406/606 DEVICES
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TRISF
02E8
—
—
—
—
—
—
—
—
—
TRISF
007F
PORTF
02EA
—
—
—
—
—
—
—
—
—
RF
xxxx
LATF
02EC
—
—
—
—
—
—
—
—
—
LATF
ODCF
02EE
—
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-54:
File
Name
SFR
Addr
Bit 6
ODCF6
Bit 5
Bit 4
—
Bit 3
Bit 2
—
Bit 1
Bit 0
All
Resets
0000
ODCF
—
0000
Bit 0
All
Resets
PORTG REGISTER MAP FOR dsPIC33FJ32GS610 AND dsPIC33FJ64GS610 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TRISG
02F0
TRISG (VDD + 0.3) for non-5V tolerant pins only.
7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
10: RB11 has also been tested up to ±8 µA test limits.
DS70000591F-page 378
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
VOL
DO10
Characteristic
Output Low Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15,
RC1-RC4, RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Output Low Voltage
I/O Pins:
8x Sink Driver Pin – RC15
Output Low Voltage
I/O Pins:
16x Sink Driver Pins – RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
VOH
DO20
Output High Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15,
RC1-RC4, RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Output High Voltage
I/O Pins:
8x Sink Driver Pin – RC15
Output High Voltage
I/O Pins:
16x Sink Driver Pins – RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
Note 1:
Min.
Typ.
Max.
Units
Conditions
—
—
0.4
V
IOL 6 mA, VDD = 3.3V
(See Note 1)
—
—
0.4
V
IOL 10 mA, VDD = 3.3V
(See Note 1)
—
—
0.4
V
IOL 18 mA, VDD = 3.3V
(See Note 1)
2.4
—
—
V
IOH -6 mA, VDD = 3.3V
(See Note 1)
2.4
—
—
V
IOH -10 mA, VDD = 3.3V
(See Note 1)
2.4
—
—
V
IOH -18 mA, VDD = 3.3V
(See Note 1)
Parameters are characterized, but not tested.
2009-2014 Microchip Technology Inc.
DS70000591F-page 379
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
VOH1
DO20A
Characteristic
Output High Voltage
I/O Pins:
4x Sink Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15,
RC1-RC4, RC12-RC14, RD0-RD2,
RD8-RD12, RD14, RD15, RE8,
RE9, RF0-RF8, RF12, RF13,
RG0-RG3, RG6-RG9, RG14, RG15
Output High Voltage
I/O Pins:
8x Sink Driver Pin – RC15
Output High Voltage
I/O Pins:
16x Sink Driver Pins – RA9, RA10,
RD3-RD7, RD13, RE0-RE7,
RG12, RG13
Note 1:
Min.
Typ.
Max.
Units
Conditions
1.5
—
—
V
IOH -12 mA, VDD = 3.3V
(See Note 1)
2.0
—
—
V
IOH -11 mA, VDD = 3.3V
(See Note 1)
3.0
—
—
V
IOH -3 mA, VDD = 3.3V
(See Note 1)
1.5
—
—
V
IOH -16 mA, VDD = 3.3V
(See Note 1)
2.0
—
—
V
IOH -12 mA, VDD = 3.3V
(See Note 1)
3.0
—
—
V
IOH -4 mA, VDD = 3.3V
(See Note 1)
1.5
—
—
V
IOH -30 mA, VDD = 3.3V
(See Note 1)
2.0
—
—
V
IOH -25 mA, VDD = 3.3V
(See Note 1)
3.0
—
—
V
IOH -8 mA, VDD = 3.3V
(See Note 1)
Parameters are characterized, but not tested.
TABLE 27-11: ELECTRICAL CHARACTERISTICS: BROWN-OUT RESET (BOR)
DC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions: 3.0V to 3.6V(3)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristic
BOR Event on VDD Transition
High-to-Low
Min(1)
Typ
Max
Units
2.6
—
2.95
V
Conditions
See Note 2
BO10
VBOR
Note 1:
2:
3:
Parameters are for design guidance only and are not tested in manufacturing.
The device will operate as normal until the VDDMIN threshold is reached.
Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device
analog modules, such as the ADC, etc., will function but with degraded performance below VDDMIN.
DS70000591F-page 380
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
D130
EP
Cell Endurance
10,000
—
—
E/W
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132B
VPEW
VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D134
TRETD
Characteristic Retention
20
—
—
Year
D135
IDDP
Supply Current during
Programming
—
10
—
mA
D136a
TRW
Row Write Time
1.488
—
1.518
ms
TRW = 11064 FRC cycles,
TA = +85°C (See Note 2)
D136b
TRW
Row Write Time
1.473
—
1.533
ms
TRW = 11064 FRC cycles,
TA = +125°C (See Note 2)
D137a
TPE
Page Erase Time
22.7
—
23.1
ms
TPE = 168517 FRC cycles,
TA = +85°C (See Note 2)
D137b
TPE
Page Erase Time
22.4
—
23.3
ms
TPE = 168517 FRC cycles,
TA = +125°C (See Note 2)
D138a
TWW
Word Write Cycle Time
47.7
—
48.7
µs
TWW = 355 FRC cycles,
TA = +85°C (See Note 2)
D138b
TWW
Word Write Cycle Time
47.3
—
49.2
µs
TWW = 355 FRC cycles,
TA = +125°C (See Note 2)
Note 1:
2:
-40C to +125C
Provided no other specifications
are violated, -40C to +125C
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Other conditions: FRC = 7.37 MHz, TUN = b'011111 (for Min.), TUN = b'100000 (for Max.).
This parameter depends on the FRC accuracy (see Table 27-20) and the value of the FRC Oscillator
Tuning register (see Register 9-4). For complete details on calculating the minimum and maximum time,
see Section 5.3 “Programming Operations”.
TABLE 27-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions:
Param
No.
—
Note 1:
Symbol
CEFC
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Characteristics
External Filter Capacitor
Value(1)
Min
Typ
Max
Units
22
—
—
µF
Comments
Capacitor must be low
series resistance
(< 0.5 Ohms)
Typical VCAP voltage = 2.5 volts when VDD VDDMIN.
2009-2014 Microchip Technology Inc.
DS70000591F-page 381
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
27.2
AC Characteristics and Timing Parameters
This section defines dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 AC characteristics and
timing parameters.
TABLE 27-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 27.0 “Electrical
Characteristics”.
AC CHARACTERISTICS
FIGURE 27-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 27-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
DO50
COSCO
OSC2 Pin
—
—
15
pF
In XT and HS modes, when
external clock is used to drive
OSC1
DO56
CIO
All I/O Pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
DS70000591F-page 382
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS31
OS31
OS25
CLKO
OS41
OS40
TABLE 27-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
Symb
FIN
OS20
TOSC
Min
Typ(1)
Max
Units
External CLKI Frequency
(external clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz
EC
Oscillator Crystal Frequency
3.5
—
10
—
—
—
10
33
40
MHz
kHz
MHz
XT
SOSC
HS
TOSC = 1/FOSC
12.5
—
DC
ns
Characteristic
Time(2)
Conditions
OS25
TCY
Instruction Cycle
25
—
DC
ns
OS30
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
—
0.625 x TOSC
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3)
—
5.2
—
ns
OS41
TckF
CLKO Fall Time(3)
—
5.2
—
ns
OS41
GM
External Oscillator
Transconductance
14
16
18
mA/V
Note 1:
2:
3:
VDD = 3.3V,
TA = +25ºC
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“Max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
2009-2014 Microchip Technology Inc.
DS70000591F-page 383
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
OS50
Characteristic
Min
Typ(1)
Max
Units
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
OS52
TLOCK
PLL Start-up Time (Lock Time)
0.9
1.5
3.1
mS
-3
0.5
3
%
OS53
DCLK
Note 1:
2:
CLKO Stability (Jitter)
(2)
Conditions
ECPLL, XTPLL modes
Measured over a 100 ms
period
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks, use this formula:
D CLK
Peripheral Clock Jitter = -----------------------------------------------------------------------F OSC
-------------------------------------------------------------
Peripheral Bit Rate Clock
For example: FOSC = 32 MHz, DCLK = 3%, SPI bit rate clock (i.e., SCK) is 2 MHz.
D CLK
3%
3%
SPI SCK Jitter = ------------------------------ = ---------- = -------- = 0.75%
4
16
32
MHz
--------------------
2 MHz
TABLE 27-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
OS56
FHPOUT
On-Chip, 16x PLL CCO
Frequency
112
118
120
MHz
OS57
FHPIN
On-Chip, 16x PLL Phase
Detector Input Frequency
7.0
7.37
7.5
MHz
OS58
TSU
Frequency Generator Lock
Time
—
—
10
µs
Note 1:
Conditions
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
DS70000591F-page 384
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a
FRC
-1
—
+1
%
-40°C TA +85°C
VDD = 3.0-3.6V
F20b
FRC
-2
—
+2
%
-40°C TA +125°C
VDD = 3.0-3.6V
Note 1:
Frequency calibrated at +25°C and 3.3V. The TUN bits can be used to compensate for temperature
drift.
TABLE 27-20: AC CHARACTERISTICS: INTERNAL LPRC ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a
LPRC
-40
—
+40
%
-40°C TA +85°C
F21b
LPRC
-50
—
+50
%
-40°C TA +125°C
Note 1:
Change of LPRC frequency as VDD changes.
2009-2014 Microchip Technology Inc.
DS70000591F-page 385
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Min
Typ(1)
Max
Units
4x Source Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15, RC1-RC4,
RC12-RC14, RD0-RD2, RD8-RD12,
RD14, RD15, RE8, RE9, RF0-RF8,
RF12, RF13, RG0-RG3, RG6-RG9,
RG14, RG15
—
10
25
ns
8x Source Driver Pins – RC15
—
8
20
ns
16x Source Driver Pins – RE0-RE7,
RG12, RG13
—
6
15
ns
4x Source Driver Pins – RA0-RA7,
RA14, RA15, RB0-RB15, RC1-RC4,
RC12-RC14, RD0-RD2, RD8-RD12,
RD14, RD15, RE8, RE9, RF0-RF8,
RF12, RF13, RG0-RG3, RG6-RG9,
RG14, RG15
—
10
25
ns
8x Source Driver Pins – RC15
—
8
20
ns
16x Source Driver Pins – RE0-RE7,
RG12, RG13
—
6
15
ns
TINP
INTx Pin High or Low Time (input)
20
—
—
ns
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TCY
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DO31
DO32
DI35
Symbol
TIOR
TIOF
DS70000591F-page 386
Characteristic
Conditions
Port Output Rise Time
Refer to Figure 27-1
for test conditions
Port Output Fall Time
Refer to Figure 27-1
for test conditions
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-4:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
OSC
Time-out
SY30
Internal
Reset
Watchdog
Timer Reset
SY13
SY20
SY13
I/O Pins
FSCM
Delay
SY35
Note: Refer to Figure 27-1 for load conditions.
2009-2014 Microchip Technology Inc.
DS70000591F-page 387
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SY10
TMCL
MCLR Pulse Width (low)
2
—
—
s
-40°C to +85°C
SY11
TPWRT
Power-up Timer Period
—
2
4
8
16
32
64
128
—
ms
-40°C to +85°C,
User programmable
SY12
TPOR
Power-on Reset Delay
3
10
30
s
-40°C to +85°C
SY13
TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
0.68
0.72
1.2
s
SY20
TWDT1
Watchdog Timer Time-out
Period
—
—
—
ms
See Section 24.4 “Watchdog
Timer (WDT)” and LPRC
Parameter F21a (Table 27-20)
SY30
TOST
Oscillator Start-up Time
—
1024 TOSC
—
—
TOSC = OSC1 period
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
DS70000591F-page 388
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-5:
TIMER1/2/3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10
Tx11
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
Symbol
TTXH
Characteristic
T1CK High Time Synchronous,
no Prescaler
Synchronous,
with Prescaler
Asynchronous
TA11
TTXL
TTXP
T1CK Input
Period
Typ
Max
Units
Conditions
TCY + 20
—
—
ns
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TA15,
N = Prescale value
(1, 8, 64, 256)
20
—
—
ns
(TCY + 20)
—
—
ns
(TCY + 20)/N
—
—
ns
Asynchronous
20
—
—
ns
Synchronous,
no Prescaler
2 TCY + 40
—
—
ns
Synchronous,
with Prescaler
Greater of:
40 ns or
(2 TCY + 40)/N
—
—
—
40
—
—
ns
DC
—
50
kHz
—
1.75 TCY + 40
—
T1CK Low Time Synchronous,
no Prescaler
Synchronous,
with Prescaler
TA15
Min
Asynchronous
OS60
Ft1
TA20
TCKEXTMRL Delay from External T1CK Clock 0.75 TCY + 40
Edge to Timer Increment
Note 1:
SOSCI/T1CK Oscillator Input
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON))
Must also meet
Parameter TA15,
N = Prescale value
(1, 8, 64, 256)
N = Prescale value
(1, 8, 64, 256)
Timer1 is a Type A.
2009-2014 Microchip Technology Inc.
DS70000591F-page 389
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-24: TIMER2/4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ
Max
Units
Conditions
TB10
TtxH
TxCK High Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB11
TtxL
TxCK Low
Time
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
Parameter TB15,
N = Prescale value
(1, 8, 64, 256)
TB15
TtxP
TxCK Input Synchronous
Period
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = Prescale value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
Synchronous
mode
These parameters are characterized, but are not tested in manufacturing.
TABLE 27-25: TIMER3/5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC11
TtxL
TxCK Low
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
TC15
TtxP
TxCK Input
Period
Synchronous,
with Prescaler
2 TCY + 40
—
—
ns
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
These parameters are characterized, but are not tested in manufacturing.
DS70000591F-page 390
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-6:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-26: INPUT CAPTURE x TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IC10
TccL
Characteristic(1)
ICx Input Low Time
No Prescaler
With Prescaler
IC11
TccH
ICx Input High Time No Prescaler
With Prescaler
IC15
TccP
Note 1:
ICx Input Period
Min
Max
Units
0.5 TCY + 20
—
ns
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(TCY + 40)/N
—
ns
Conditions
N = Prescale value
(1, 4, 16)
These parameters are characterized but not tested in manufacturing.
FIGURE 27-7:
OUTPUT COMPARE x (OCx) MODULE TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
OC10
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-27: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Min
Typ
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See Parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See Parameter DO31
Note 1:
These parameters are characterized but not tested in manufacturing.
2009-2014 Microchip Technology Inc.
DS70000591F-page 391
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-8:
OUTPUT COMPARE x/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
Active
Tri-State
TABLE 27-28: SIMPLE OCx/PWMx MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
OC15
TFD
Fault Input to PWM I/O
Change
—
—
TCY + 20
ns
OC20
TFLT
Fault Input Pulse Width
TCY + 20
—
—
ns
Note 1:
These parameters are characterized but not tested in manufacturing.
DS70000591F-page 392
Conditions
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-9:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTx
MP20
PWMx
FIGURE 27-10:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11
MP10
PWMx
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-29: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
—
ns
MP10
TFPWM
PWMx Output Fall Time
—
2.5
MP11
TRPWM
PWMx Output Rise Time
—
2.5
—
ns
MP20
TFD
Fault Input to PWMx
I/O Change
—
—
15
ns
MP30
TFH
Minimum PWMx Fault Pulse
Width
8
—
—
ns
MP31
TPDLY
Tap Delay
1.04
—
—
ns
MP32
ACLK
PWMx Input Clock
—
—
120
MHz
Note 1:
2:
Conditions
DTC = 10
ACLK = 120 MHz
See Note 2
These parameters are characterized but not tested in manufacturing.
This parameter is a maximum allowed input clock for the PWM module.
2009-2014 Microchip Technology Inc.
DS70000591F-page 393
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 27-31
—
—
0,1
0,1
0,1
10 MHz
—
Table 27-32
—
1
0,1
1
10 MHz
—
Table 27-33
—
0
0,1
1
15 MHz
—
—
Table 27-34
1
0
0
11 MHz
—
—
Table 27-35
1
1
0
15 MHz
—
—
Table 27-36
0
1
0
11 MHz
—
—
Table 27-37
0
0
0
FIGURE 27-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP30, SP31
LSb
SP30, SP31
Note: Refer to Figure 27-1 for load conditions.
FIGURE 27-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SDOx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 394
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP10
TscP
Maximum SCKx Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
2009-2014 Microchip Technology Inc.
DS70000591F-page 395
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
LSb
SP30, SP31
SP40
SDIx
Bit 14 - - - - - -1
MSb In
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
SP20
TscP
TscF
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
10
—
MHz
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
DS70000591F-page 396
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
SP30, SP31
SDIx
MSb In
LSb
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 27-1 for load conditions.
TABLE 27-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40ºC to +125ºC and
see Note 3
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
See Parameter DO32
and Note 4
See Parameter DO31
and Note 4
SP10
TscP
Maximum SCKx Frequency
—
—
10
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
2009-2014 Microchip Technology Inc.
DS70000591F-page 397
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-15:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
SP51
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 398
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2009-2014 Microchip Technology Inc.
DS70000591F-page 399
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-16:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDIx
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 400
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2009-2014 Microchip Technology Inc.
DS70000591F-page 401
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-17:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SDOX
Bit 14 - - - - - -1
MSb
LSb
SP51
SP30, SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 402
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2009-2014 Microchip Technology Inc.
DS70000591F-page 403
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
SDOX
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
SDIX
MSb In
Bit 14 - - - -1
LSb In
SP41
SP40
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 404
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
TscP
Maximum SCKx Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See Parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See Parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
SP50
TssL2scH,
TssL2scL
SSx to SCKx or SCKx Input
120
—
—
ns
SP51
TssH2doZ
SSx to SDOx Output
High-Impedance
10
—
50
ns
See Note 4
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
See Note 3
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock, generated by the master, must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
2009-2014 Microchip Technology Inc.
DS70000591F-page 405
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-19:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Start
Condition
Stop
Condition
Note: Refer to Figure 27-1 for load conditions.
FIGURE 27-20:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 27-1 for load conditions.
DS70000591F-page 406
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note
Characteristic
Min(1)
Max
Units
Conditions
—
s
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
—
s
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
s
1 MHz mode(2) TCY/2 (BRG + 1)
—
s
SDAx and SCLx 100 kHz mode
—
300
ns
CB is specified to be
TF:SCL
Fall Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
100
ns
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
400 kHz mode
20 + 0.1 CB
300
ns
(2)
1 MHz mode
—
300
ns
TSU:DAT Data Input
100 kHz mode
250
—
ns
Setup Time
400 kHz mode
100
—
ns
(2)
1 MHz mode
40
—
ns
THD:DAT Data Input
100 kHz mode
0
—
s
Hold Time
400 kHz mode
0
0.9
s
1 MHz mode(2)
0.2
—
s
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
Only relevant for
Setup Time
Repeated Start
400 kHz mode TCY/2 (BRG + 1)
—
s
condition
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
After this period, the
Hold Time
first clock pulse is
400 kHz mode TCY/2 (BRG + 1)
—
s
generated
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
s
(2)
1 MHz mode
TCY/2 (BRG + 1)
—
s
—
ns
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
ns
1 MHz mode(2) TCY/2 (BRG + 1)
—
ns
100 kHz mode
—
3500
ns
TAA:SCL Output Valid
from Clock
400 kHz mode
—
1000
ns
1 MHz mode(2)
—
400
ns
4.7
—
s
Time the bus must be
TBF:SDA Bus Free Time 100 kHz mode
free before a new
400 kHz mode
1.3
—
s
transmission can start
(2)
1 MHz mode
0.5
—
s
Bus Capacitive Loading
—
400
pF
CB
TPGD
Pulse Gobbler Delay
65
390
ns
See Note 3
2
1: BRG is the value of the I C™ Baud Rate Generator. Refer to “Inter-Integrated Circuit™ (I2C™)”
(DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
2009-2014 Microchip Technology Inc.
DS70000591F-page 407
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
FIGURE 27-21:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 27-22:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
DS70000591F-page 408
2009-2014 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
IS10
IS11
IS20
IS21
IS25
IS26
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
Characteristic
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
THD:DAT Data Input
Hold Time
Min
Max
Units
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
100
—
ns
100 kHz mode
0
—
s
400 kHz mode
0
0.9
s
(1)
1 MHz mode
IS30
IS31
IS33
IS34
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO
Stop Condition
Setup Time
THD:STO Stop Condition
Hold Time
100 kHz mode
IS45
IS50
Note 1:
TAA:SCL
Output Valid
From Clock
TBF:SDA Bus Free Time
CB
0
0.3
s
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.6
—
s
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
(1)
250
1 MHz mode
IS40
Conditions
CB is specified to be from
10 to 400 pF
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
ns
100 kHz mode
0
3500
ns
400 kHz mode
0
1000
ns
1 MHz mode(1)
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
1 MHz mode(1)
0.5
—
s
—
400
pF
Bus Capacitive Loading
CB is specified to be from
10 to 400 pF
Time the bus must be free
before a new transmission
can start
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2009-2014 Microchip Technology Inc.
DS70000591F-page 409
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
TABLE 27-40: 10-BIT, HIGH-SPEED ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V and 3.6V(2)
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of:
VDD – 0.3
or 3.0
—
Lesser of
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply
Vss – 0.3
—
VSS + 0.3
V
Analog Input
AD10
VINH-VINL Full-Scale Input Span
AD11
VIN
Absolute Input Voltage
AD12
IAD
AD13
—
VSS
—
VDD
V
AVSS
—
AVDD
V
Operating Current
—
8
—
mA
Leakage Current
—
±0.6
—
A
—
—
100
AD17
RIN
Recommended Impedance
of Analog Voltage Source
AD20
Nr
Resolution
VINL = AVSS = 0V,
AVDD = 3.3V,
Source Impedance = 100
DC Accuracy
10 data bits
bits
AD21A INL
Integral Nonlinearity
> -2
±0.5
-1
±0.5
-5
±2.0
-3
±0.75
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