dsPIC33FJXXXMCX06A/X08A/X10A
16-bit Digital Signal Controllers (up to 256 KB Flash and
30 KB SRAM) with Motor Control and Advanced Analog
Operating Conditions
Timers/Output Compare/Input Capture
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
• Up to nine 16-bit timers/counters. Can pair up to
make four 32-bit timers.
• Eight Output Compare modules configurable as
timers/counters
• Eight Input Capture modules
Core: 16-bit dsPIC33F CPU
•
•
•
•
Code-efficient (C and Assembly) architecture
Two 40-bit wide accumulators
Single-cycle (MAC/MPY) with dual data fetch
Single-cycle mixed-sign MUL plus hardware
divide
Communication Interfaces
• Two UART modules (10 Mbps)
- With support for LIN 2.0 protocols and IrDA®
• Two 4-wire SPI modules (15 Mbps)
• Up to two I2C™ modules (up to 1 Mbaud) with
SMBus support
• Up to two Enhanced CAN (ECAN) modules
(1 Mbaud) with 2.0B support
• Quadrature Encoder Interface (QEI) module
• Data Converter Interface (DCI) module with I2S
codec support
Clock Management
•
•
•
•
•
±2% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast wake-up and start-up
Power Management
Input/Output
• Low-power management modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
• 1.35 mA/MHz dynamic current (typical)
• 55 μA IPD current (typical)
• Sink/Source up to 10 mA (pin specific) for standard VOH/VOL, up to 16 mA (pin specific) for nonstandard VOH1
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• Up to 5 mA overvoltage clamp current
• External interrupts on all I/O pins
Motor Control PWM
•
•
•
•
Up to four PWM generators with eight outputs
Dead Time for rising and falling edges
12.5 ns PWM resolution
PWM support for Motor Control: BLDC, PMSM, ACIM,
and SRM
• Programmable Fault inputs
• Flexible trigger for ADC conversions and configurations
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)
• Class B Safety Library, IEC 60730
Debugger Development Support
Advanced Analog Features
•
•
•
•
• Two ADC modules:
- Configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- 18 analog inputs on 64-pin devices and up to
32 analog inputs on 100-pin devices
• Flexible and independent ADC trigger sources
In-circuit and in-application programming
Two program and two complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Trace and run-time watch
Packages
Type
QFN
Pin Count
64
Contact Lead/Pitch
0.50
I/O Pins
53
Dimensions
9x9x0.9
Note: All dimensions are in millimeters (mm) unless specified.
2009-2012 Microchip Technology Inc.
TQFP
TQFP
TQFP
64
0.50
53
10x10x1
80
0.50
69
12x12x1
100
0.40
85
14x14x1
DS70594D-page 1
dsPIC33FJXXXMCX06A/X08A/X10A
The device names, pin counts, memory sizes and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
dsPIC33F PRODUCT FAMILIES
The dsPIC33FJXXXMCX06A/X08A/X10A family of
devices supports a variety of motor control applications,
such as brushless DC motors, single and 3-phase
induction motors and switched reluctance motors. The
dsPIC33F Motor Control products are also well-suited
for Uninterrupted Power Supply (UPS), inverters,
Switched mode power supplies, power factor correction
and also for controlling the power management module
in servers, telecommunication equipment and other
industrial equipment.
Timer 16-bit
Input Capture
Output Compare
Std. PWM
Motor Control PWM
Quadrature Encoder
Interface
Codec Interface
ADC
UART
SPI
2
I C™
Enhanced CAN
I/O Pins (Max)(2)
Packages
dsPIC33FJXXXMCX06A/X08A/X10A Controller Families
dsPIC33FJ64MC506A
64
64
8
9
8
8
8 ch
1
0
1 ADC,
16 ch
2
2
2
1
53
PT, MR
dsPIC33FJ64MC508A
80
64
8
9
8
8
8 ch
1
0
1 ADC,
18 ch
2
2
2
1
69
PT
dsPIC33FJ64MC510A
100
64
8
9
8
8
8 ch
1
0
1 ADC,
24 ch
2
2
2
1
85
PF, PT
dsPIC33FJ64MC706A
64
64
16
9
8
8
8 ch
1
0
2 ADC,
16 ch
2
2
2
1
53
PT, MR
dsPIC33FJ64MC710A
100
64
16
9
8
8
8 ch
1
0
2 ADC,
24 ch
2
2
2
2
85
PF, PT
dsPIC33FJ128MC506A
64
128
8
9
8
8
8 ch
1
0
1 ADC,
16 ch
2
2
2
1
53
PT, MR
dsPIC33FJ128MC510A
100
128
8
9
8
8
8 ch
1
0
1 ADC,
24 ch
2
2
2
1
85
PF, PT
dsPIC33FJ128MC706A
64
128
16
9
8
8
8 ch
1
0
2 ADC,
16 ch
2
2
2
1
53
PT, MR
dsPIC33FJ128MC708A
80
128
16
9
8
8
8 ch
1
0
2 ADC,
18 ch
2
2
2
2
69
PT
dsPIC33FJ128MC710A
100
128
16
9
8
8
8 ch
1
0
2 ADC,
24 ch
2
2
2
2
85
PF, PT
dsPIC33FJ256MC510A
100
256
16
9
8
8
8 ch
1
0
1 ADC,
24 ch
2
2
2
1
85
PF, PT
dsPIC33FJ256MC710A
100
256
30
9
8
8
8 ch
1
0
2 ADC,
24 ch
2
2
2
2
85
PF, PT
Device
Note 1:
2:
Program
Flash
RAM
Pins
Memory (Kbyte)(1)
(Kbyte)
RAM size is inclusive of 2 Kbytes DMA RAM.
Maximum I/O pin count includes pins shared by the peripheral functions.
DS70594D-page 2
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams
64-Pin QFN(1)
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C1TX/RF1
C1RX/RF0
VDD
VCAP
OC8/UPDN/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ128MC506A
dsPIC33FJ64MC506A
dsPIC33FJ128MC706A
dsPIC33FJ64MC706A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected
to VSS externally.
2009-2012 Microchip Technology Inc.
DS70594D-page 3
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams (Continued)
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
C1TX/RF1
C1RX/RF0
VDD
VCAP
OC8/UPDN/CN16/RD7
OC7/CN15/RD6
OC6/IC6/CN14/RD5
OC5/IC5/CN13/RD4
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
dsPIC33FJ128MC506A
dsPIC33FJ256MC506A
dsPIC33FJ128MC706A
dsPIC33FJ64MC706A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/T4CK/CN1/RC13
OC1/RD0
IC4/INT4/RD11
IC3/INT3/RD10
IC2/U1CTS/FLTB/INT2/RD9
IC1/FLTA/INT1/RD8
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
SCL1/RG2
SDA1/RG3
U1RTS/SCK1/INT0/RF6
U1RX/SDI1/RF2
U1TX/SDO1/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
AVDD
AVSS
U2CTS/AN8/RB8
AN9/RB9
TMS/AN10/RB10
TDO/AN11/RB11
VSS
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
U2RX/SDA2/CN17/RF4
U2TX/SCL2/CN18/RF5
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
AN5/QEB/IC8/CN7/RB5
AN4/QEA/IC7/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/VREF-/CN3/RB1
PGED3/AN0/VREF+/CN2/RB0
DS70594D-page 4
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
63
62
61
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
OC7/CN15/RD6
C1TX/RF1
C1RX/RF0
VDD
VCAP
OC8/CN16/UPDN/RD7
75
74
73
72
71
70
69
68
67
66
65
64
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
RG0
RG1
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
80-Pin TQFP
PWM3H/RE5
1
60
PGEC2/SOSCO/T1CK/CN0/RC14
PWM4L/RE6
2
59
PGED2/SOSCI/CN1/RC13
OC1/RD0
PWM4H/RE7
3
58
AN16/T2CK/T7CK/RC1
4
57
IC4/RD11
AN17/T3CK/T6CK/RC2
5
56
IC3/RD10
SCK2/CN8/RG6
6
55
IC2/RD9
SDI2/CN9/RG7
7
54
IC1/RD8
SDO2/CN10/RG8
8
53
SDA2/INT4/RA3
MCLR
9
52
SS2/CN11/RG9
VSS
10
51
SCL2/INT3/RA2
VSS
50
OSC2/CLKO/RC15
VDD
12
49
OSC1/CLKIN/RC12
TMS/FLTA/INT1/RE8
13
14
48
VDD
47
SCL1/RG2
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
15
46
SDA1/RG3
16
45
SCK1/INT0/RF6
AN3/INDX/CN5/RB3
17
44
SDI1/RF7
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
18
43
SDO1/RF8
19
42
U1RX/RF2
PGED3/AN0/CN2/RB0
20
41
U1TX/RF3
30
31
32
33
34
35
36
37
38
39
40
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
27
U2CTS/AN8/RB8
VSS
26
AVSS
AN11/RB11
25
AVDD
29
24
28
23
VREF-/RA9
VREF+/RA10
AN9/RB9
22
PGED1/AN7/RB7
2009-2012 Microchip Technology Inc.
AN10/RB10
21
PGEC1/AN6/OCFA/RB6
TDO/FLTB/INT2/RE9
dsPIC33FJ256MC508A
11
DS70594D-page 5
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
OC2/RD1
IC5/RD12
OC4/RD3
OC3/RD2
OC8/CN16/UPDN/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
CRX2/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
PWM2L/RE2
PWM1H/RE1
PWM1L/RE0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PWM3L/RE4
PWM2H/RE3
80-Pin TQFP
PWM3H/RE5
1
60
PGEC2/SOSCO/T1CK/CN0/RC14
PWM4L/RE6
2
59
PGED2/SOSCI/CN1/RC13
OC1/RD0
PWM4H/RE7
3
58
AN16/T2CK/T7CK/RC1
4
57
AN17/T3CK/T6CK/RC2
SCK2/CN8/RG6
5
56
IC4/RD11
IC3/RD10
6
55
IC2/RD9
SDI2/CN9/RG7
SDO2/CN10/RG8
7
54
IC1/RD8
8
53
SDA2/INT4/RA3
MCLR
9
52
SCL2/INT3/RA2
SS2/CN11/RG9
10
51
VSS
VSS
11
50
OSC2/CLKO/RC15
VDD
12
49
OSC1/CLKIN/RC12
TMS/FLTA/INT1/RE8
48
VDD
TDO/FLTB/INT2/RE9
13
14
47
SCL1/RG2
AN5/QEB/CN7/RB5
15
46
SDA1/RG3
AN4/QEA/CN6/RB4
16
45
SCK1/INT0/RF6
AN3/INDX/CN5/RB3
17
44
SDI1/RF7
AN2/SS1/CN4/RB2
18
43
SDO1/RF8
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
19
42
U1RX/RF2
20
41
U1TX/RF3
DS70594D-page 6
30
31
32
33
34
35
36
37
38
39
40
VDD
TCK/AN12/RB12
TDI/AN13/RB13
U2RTS/AN14/RB14
AN15/OCFB/CN12/RB15
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
27
U2CTS/AN8/RB8
VSS
26
AVSS
29
25
AVDD
AN11/RB11
24
28
23
VREF-/RA9
VREF+/RA10
AN9/RB9
22
PGED1/AN7/RB7
AN10/RB10
21
PGEC1/AN6/OCFA/RB6
dsPIC33FJ128MC708A
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
VSS
74
73
PGEC2/SOSCO/T1CK/CN0/RC14
72
OC1/RD0
IC4/RD11
71
70
69
68
67
66
dsPIC33FJ64MC510A
PGED2/SOSCI/CN1/RC13
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
65
64
INT3/RA14
VSS
OSC2/CLKO/RC15
63
62
61
OSC1/CLKIN/RC12
VDD
TDO/RA5
60
59
58
57
56
TDI/RA4
SDA2/RA3
SCL2/RA2
55
54
53
52
51
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
RG13
RG12
RG14
PWM1H/RE1
PWM1L/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
OC8/UPDN//CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
2009-2012 Microchip Technology Inc.
DS70594D-page 7
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
VSS
73
72
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
71
70
69
68
67
66
65
64
dsPIC33FJ128MC510A
dsPIC33FJ256MC510A
63
62
61
60
59
58
57
56
55
54
53
52
51
PGEC2/SOSCO/T1CK/CN0/RC14
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGEC3/AN1/CN3/RB1
PGED3/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
RG13
RG12
RG14
PWM1H/RE1
PWM1L/RE0
AN23/CN23/RA7
AN22/CN22/RA6
RG0
RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
OC8/UPDN//CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
DS70594D-page 8
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
Pin Diagrams (Continued)
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PWM3L/RE4
PWM2H/RE3
PWM2L/RE2
RG13
RG12
RG14
PWM1H/RE1
PWM1L/RE0
AN23/CN23/RA7
AN22/CN22/RA6
C2RX/RG0
C2TX/RG1
C1TX/RF1
C1RX/RF0
VDD
VCAP
OC8/UPDN//CN16/RD7
OC7/CN15/RD6
OC6/CN14/RD5
OC5/CN13/RD4
IC6/CN19/RD13
IC5/RD12
OC4/RD3
OC3/RD2
OC2/RD1
= Pins are up to 5V tolerant
RG15
VDD
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
AN16/T2CK/T7CK/RC1
AN17/T3CK/T6CK/RC2
AN18/T4CK/T9CK/RC3
AN19/T5CK/T8CK/RC4
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
SS2/CN11/RG9
VSS
VDD
TMS/RA0
AN20/FLTA/INT1/RE8
AN21/FLTB/INT2/RE9
AN5/QEB/CN7/RB5
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
AN2/SS1/CN4/RB2
PGEC3/AN1/CN3/RB1
75
2
3
4
5
6
7
8
9
10
11
12
74
73
13
14
15
16
17
18
19
20
21
22
23
24
25
72
71
70
69
68
67
66
dsPIC33FJ64MC710A
dsPIC33FJ128MC710A
dsPIC33FJ256MC710A
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
PGEC2/SOSCO/T1CK/CN0/RC14
PGED2/SOSCI/CN1/RC13
OC1/RD0
IC4/RD11
IC3/RD10
IC2/RD9
IC1/RD8
INT4/RA15
INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKIN/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
SCL1/RG2
SDA1/RG3
SCK1/INT0/RF6
SDI1/RF7
SDO1/RF8
U1RX/RF2
U1TX/RF3
PGEC1/AN6/OCFA/RB6
PGED1/AN7/RB7
VREF-/RA9
VREF+/RA10
AVDD
AVSS
AN8/RB8
AN9/RB9
AN10/RB10
AN11/RB11
VSS
VDD
TCK/RA1
U2RTS/RF13
U2CTS/RF12
AN12/RB12
AN13/RB13
AN14/RB14
AN15/OCFB/CN12/RB15
VSS
VDD
IC7/U1CTS/CN20/RD14
IC8/U1RTS/CN21/RD15
U2RX/CN17/RF4
U2TX/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGED3/AN0/CN2/RB0
1
2009-2012 Microchip Technology Inc.
DS70594D-page 9
dsPIC33FJXXXMCX06A/X08A/X10A
Table of Contents
dsPIC33F Product Families ................................................................................................................................................................... 2
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 19
3.0 CPU ............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 35
5.0 Flash Program Memory .............................................................................................................................................................. 73
6.0 Reset ......................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 85
8.0 Direct Memory Access (DMA) .................................................................................................................................................. 133
9.0 Oscillator Configuration ............................................................................................................................................................ 143
10.0 Power-Saving Features ............................................................................................................................................................ 153
11.0 I/O Ports ................................................................................................................................................................................... 161
12.0 Timer1 ...................................................................................................................................................................................... 165
13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 167
14.0 Input Capture............................................................................................................................................................................ 173
15.0 Output Compare ....................................................................................................................................................................... 175
16.0 Motor Control PWM Module ..................................................................................................................................................... 179
17.0 Quadrature Encoder Interface (QEI) Module ........................................................................................................................... 193
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 197
19.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 203
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 211
21.0 Enhanced CAN Module ............................................................................................................................................................ 217
22.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 245
23.0 Special Features ...................................................................................................................................................................... 259
24.0 Instruction Set Summary .......................................................................................................................................................... 267
25.0 Development Support............................................................................................................................................................... 275
26.0 Electrical Characteristics .......................................................................................................................................................... 279
27.0 High Temperature Electrical Characteristics ............................................................................................................................ 329
28.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 339
29.0 Packaging Information.............................................................................................................................................................. 343
Appendix A: Migrating from dsPIC33FJXXXMCX06/X08/X10 Devices to dsPIC33FJXXXMCX06A/X08A/X10A Devices ............... 357
Appendix B: Revision History............................................................................................................................................................. 358
Index ................................................................................................................................................................................................. 363
The Microchip Web Site ..................................................................................................................................................................... 369
Customer Change Notification Service .............................................................................................................................................. 369
Customer Support .............................................................................................................................................................................. 369
Reader Response .............................................................................................................................................................................. 370
Product Identification System............................................................................................................................................................. 371
DS70594D-page 10
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via Email at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2009-2012 Microchip Technology Inc.
DS70594D-page 11
dsPIC33FJXXXMCX06A/X08A/X10A
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note:
To access the documents listed below,
browse to the documentation section of
the dsPIC33FJ256MC710A product page
on
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory” (DS70202)
Section 4. “Program Memory” (DS70203)
Section 5. “Flash Programming” (DS70191)
Section 6. “Interrupts” (DS70184)
Section 7. “Oscillator” (DS70186)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 14. “Motor Control PWM” (DS70187)
Section 15. “Quadrature Encoder Interface (QEI)” (DS70208)
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)” (DS70206)
Section 19. “Inter-Integrated Circuit™ (I2C™)” (DS70195)
Section 20. “Data Converter Interface (DCI)” (DS70288)
Section 21. “Enhanced Controller Area Network (ECAN™)” (DS70185)
Section 22. “Direct Memory Access (DMA)” (DS70182)
Section 23. “CodeGuard™ Security” (DS70199)
Section 24. “Programming and Diagnostics” (DS70207)
Section 25. “Device Configuration” (DS70194)
DS70594D-page 12
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to the
“dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This document contains device-specific information for
the following devices:
•
•
•
•
•
•
•
•
•
•
•
•
dsPIC33FJ64MC506A
dsPIC33FJ64MC508A
dsPIC33FJ64MC510A
dsPIC33FJ64MC706A
dsPIC33FJ64MC710A
dsPIC33FJ128MC506A
dsPIC33FJ128MC510A
dsPIC33FJ128MC706A
dsPIC33FJ128MC708A
dsPIC33FJ128MC710A
dsPIC33FJ256MC510A
dsPIC33FJ256MC710A
These features make this family suitable for a wide
variety of high-performance, digital signal control applications. The devices are pin compatible with the PIC24H
family of devices, and also share a very high degree of
compatibility with the dsPIC30F family devices. This
allows easy migration between device families as may be
necessitated by the specific functionality, computational
resource and system cost requirements of the
application.
The dsPIC33FJXXXMCX06A/X08A/X10A family of
devices employs a powerful 16-bit architecture that
seamlessly integrates the control features of a
Microcontroller (MCU) with the computational
capabilities of a Digital Signal Processor (DSP). The
resulting functionality is ideal for applications that rely
on high-speed, repetitive computations, as well as
control.
The DSP engine, dual 40-bit accumulators, hardware
support for division operations, barrel shifter, 17 x 17
multiplier, a large array of 16-bit working registers and
a wide variety of data addressing modes, together,
provide the dsPIC33FJXXXMCX06A/X08A/X10A
Central Processing Unit (CPU) with extensive
mathematical processing capability. Flexible and
deterministic interrupt handling, coupled with a
powerful array of peripherals, renders the
dsPIC33FJXXXMCX06A/X08A/X10A devices suitable
for control applications. Further, Direct Memory Access
(DMA) enables overhead-free transfer of data between
several peripherals and a dedicated DMA RAM.
Reliable, field programmable Flash program memory
ensures scalability of applications that use
dsPIC33FJXXXMCX06A/X08A/X10A devices.
The dsPIC33FJXXXMCX06A/X08A/X10A includes
devices with a wide range of pin counts (64, 80 and
100), different program memory sizes (64 Kbytes,
128 Kbytes and 256 Kbytes) and different RAM sizes
(8 Kbytes, 16 Kbytes and 30 Kbytes).
2009-2012 Microchip Technology Inc.
DS70594D-page 13
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 1-1:
dsPIC33FJXXXMCX06A/X08A/X10A GENERAL BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
8
PORTA
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
DMA
RAM
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
PORTB
DMA
16
16
16
Controller
PORTC
Address Generator Units
Address Latch
Program Memory
EA MUX
Data Latch
24
Instruction Reg
Control Signals
to Various Blocks
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP
Note:
16
PORTE
16
DSP Engine
Power-up
Timer
Oscillator
Start-up Timer
Divide Support
16 x 16
W Register Array
PORTF
16
Power-on
Reset
Watchdog
Timer
16-Bit ALU
Brown-out
Reset
VDD, VSS
PWM
IC1-8
Literal Data
16
Instruction
Decode and
Control
OSC2/CLKO
OSC1/CLKI
PORTD
ROM Latch
OC/
PWM1-8
PORTG
16
MCLR
QEI
Timers
1-9
ADC1,2
ECAN1,2
CN1-23
SPI1,2
I2C1,2
UART1,2
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins
and features present on each device.
DS70594D-page 14
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
AN0-AN31
I
Analog
AVDD
P
P
Positive supply for analog modules. This pin must be connected at all times.
AVSS
P
P
Ground reference for analog modules.
CLKI
CLKO
I
O
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
C1RX
C1TX
C2RX
C2TX
I
O
I
O
ST
—
ST
—
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
ECAN2 bus receive pin.
ECAN2 bus transmit pin.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
IC1-IC8
I
ST
Capture Inputs 1 through 8.
INDX
QEA
I
I
ST
ST
QEB
I
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode. Auxiliary timer external clock/
gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode. Auxiliary timer external clock/
gate input in Timer mode.
Position up/down counter direction state.
Pin Name
Description
Analog input channels.
ST/CMOS External clock source input. Always associated with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
UPDN
O
CMOS
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External Interrupt 0.
External Interrupt 1.
External Interrupt 2.
External Interrupt 3.
External Interrupt 4.
FLTA
FLTB
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM3 low output.
PWM3 high output.
PWM4 low output.
PWM4 high output.
MCLR
I/P
ST
Master Clear (Reset) input. This pin is an active-low Reset to the device.
OCFA
OCFB
OC1-OC8
I
I
O
ST
ST
—
Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Compare Fault B input (for Compare Channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OSC1
I
OSC2
I/O
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
2009-2012 Microchip Technology Inc.
Analog = Analog input
O = Output
P = Power
I = Input
DS70594D-page 15
dsPIC33FJXXXMCX06A/X08A/X10A
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
RA0-RA7
RA9-RA10
RA12-RA15
I/O
I/O
I/O
ST
ST
ST
PORTA is a bidirectional I/O port.
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
RC1-RC4
RC12-RC15
I/O
I/O
ST
ST
PORTC is a bidirectional I/O port.
Pin Name
Description
RD0-RD15
I/O
ST
PORTD is a bidirectional I/O port.
RE0-RE9
I/O
ST
PORTE is a bidirectional I/O port.
RF0-RF8
RF12-RF13
I/O
ST
PORTF is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
PORTG is a bidirectional I/O port.
SCK1
SDI1
SDO1
SS1
SCK2
SDI2
SDO2
SS2
I/O
I
O
I/O
I/O
I
O
I/O
ST
ST
—
ST
ST
ST
—
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
Synchronous serial clock input/output for SPI2.
SPI2 data in.
SPI2 data out.
SPI2 slave synchronization or frame pulse I/O.
SCL1
SDA1
SCL2
SDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SOSCI
SOSCO
I
O
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
T1CK
T2CK
T3CK
T4CK
T5CK
T6CK
T7CK
T8CK
T9CK
I
I
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
Timer6 external clock input.
Timer7 external clock input.
Timer8 external clock input.
Timer9 external clock input.
U1CTS
U1RTS
U1RX
U1TX
U2CTS
U2RTS
U2RX
U2TX
I
O
I
O
I
O
I
O
ST
—
ST
—
ST
—
ST
—
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
UART2 clear to send.
UART2 ready to send.
UART2 receive.
UART2 transmit.
VDD
P
—
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
CPU logic filter capacitor connection.
ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
DS70594D-page 16
Analog = Analog input
O = Output
P = Power
I = Input
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
VSS
P
—
VREF+
I
Analog
Analog voltage reference (high) input.
VREF-
I
Analog
Analog voltage reference (low) input.
Pin Name
Description
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
2009-2012 Microchip Technology Inc.
Analog = Analog input
O = Output
P = Power
I = Input
DS70594D-page 17
dsPIC33FJXXXMCX06A/X08A/X10A
NOTES:
DS70594D-page 18
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
G ettin g
star ted
w ith
t he
dsPIC33FJXXXMCX06A/X08A/X10A family of 16-bit
Digital Signal Controllers (DSC) requires attention to a
minimal set of device pin connections before
proceeding with development. The following is a list of
pin names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
2.2
Decoupling Capacitors
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 F (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, upward of
tens of MHz, add a second ceramic type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 F to 0.001 F. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 F in parallel with 0.001 F.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2009-2012 Microchip Technology Inc.
DS70594D-page 19
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
R
R1
VSS
VDD
2.4
VCAP
VDD
• Device Reset
• Device Programming and Debugging
C
dsPIC33F
VSS
VDD
VSS
VDD
AVSS
VDD
AVDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
L1(1)
Note
1:
As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Where:
F CNV
f = ------------2
1
f = ---------------------- 2 LC
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
MCLR
0.1 µF
Ceramic
The placement of this capacitor should be close to the
VCAP. It is recommended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 23.2
“On-Chip Voltage Regulator” for details.
(i.e., ADC conversion rate/2)
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
For example, as shown in Figure 2-2, it is
recommended that the capacitor, C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
2
1
L = ----------------------
2f C
R(1)
R1(2)
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 F to 47 F.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
JP
MCLR
dsPIC33F
C
Note 1:
R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output voltage. The VCAP pin must not be
connected to VDD and must have a capacitor between
4.7 F and 10 F, 16V connected to ground. The type
can be ceramic or tantalum. Refer to Section 26.0
“Electrical
Characteristics”
for
additional
information.
DS70594D-page 20
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging
purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the “dsPIC33F/
PIC24H Flash Programming Specification” (DS70152)
for information on capacitive loading limits, and pin
input voltage high (VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to the
MPLAB® ICD 3 or REAL ICE™ in-circuit emulator.
For more information on the ICD 3 and REAL ICE
in-circuit emulator connection requirements, refer to
the following documents that are available on the
Microchip web site.
• “Using MPLAB® ICD 3” (poster) (DS51765)
• “MPLAB® ICD 3 Design Advisory” (DS51764)
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” (DS51616)
• “Using MPLAB® REAL ICE™ In-Circuit Emulator”
(poster) (DS51749)
2009-2012 Microchip Technology Inc.
2.6
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
16
17
18
19
20
DS70594D-page 21
dsPIC33FJXXXMCX06A/X08A/X10A
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 8 MHz for start-up with PLL enabled to comply with
device PLL start-up conditions. This means that if the
external oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If the MPLAB ICD 3 or REAL ICE in-circuit emulator is
selected as a debugger, it automatically initializes all of
the A/D input pins (ANx) as “digital” pins by setting all
bits in the AD1PCFGL register.
DS70594D-page 22
The bits in this register that correspond to the A/D pins
that are initialized by the MPLAB ICD 3 or REAL ICE
in-circuit emulator, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When the MPLAB ICD 3 or REAL ICE in-circuit
emulator is used as a programmer, the user application
firmware must correctly configure the AD1PCFGL
register. Automatic initialization of this register is only
done during debugger operation. Failure to correctly
configure the register(s) will result in all A/D pins being
recognized as analog input pins, resulting in the port
value being read as a logic ‘0’, which may affect user
application functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and the unused pins.
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
3.0
CPU
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section
2. “CPU” (DS70204) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJXXXMCX06A/X08A/X10A CPU module
has a 16-bit (data) modified Harvard architecture with
an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word
with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space. The actual
amount of program memory implemented varies by
device. A single-cycle instruction prefetch mechanism is
used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle,
with the exception of instructions that change the program flow, the double word move (MOV.D) instruction
and the table instructions. Overhead-free program loop
constructs are supported using the DO and REPEAT
instructions, both of which are interruptible at any point.
The dsPIC33FJXXXMCX06A/X08A/X10A devices
have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve
as a data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
The dsPIC33FJXXXMCX06A/X08A/X10A instruction
set has two classes of instructions: MCU and DSP.
These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes
many addressing modes and is designed for optimum
‘C’ compiler efficiency. For most instructions, the
dsPIC33FJXXXMCX06A/X08A/X10A devices are
capable of executing a data (or program data) memory
read, a working register (data) read, a data memory
write and a program (instruction) memory read per
instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations
to be executed in a single cycle.
3.1
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes, and is split into two blocks referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with
any of the MCU class of instructions. The X AGU also
supports Bit-Reversed Addressing to greatly simplify
input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page register (PSVPAG). The
program to data space mapping feature lets any
instruction access program space as if it were data
space.
The data space also includes 2 Kbytes of DMA RAM,
which is primarily used for DMA data transfers but may
be used as general purpose RAM.
3.2
DSP Engine Overview
The DSP engine features a high-speed, 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel
shifter is capable of shifting a 40-bit value up to 16 bits
right or left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have
been designed for optimal real-time performance. The
MAC instruction and other associated instructions can
concurrently fetch two data operands from memory
while multiplying two W registers, and accumulating
and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM
memory data space be split for these instructions and
linear for all others. Data space partitioning is achieved
in a transparent and flexible manner through dedicating
certain working registers to each address space.
A block diagram of the CPU is shown in Figure 3-1
and
the
programmer’s
model
for
the
dsPIC33FJXXXMCX06A/X08A/X10A is shown in
Figure 3-2.
2009-2012 Microchip Technology Inc.
DS70594D-page 23
dsPIC33FJXXXMCX06A/X08A/X10A
3.3
The dsPIC33FJXXXMCX06A/X08A/X10A devices
support 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative
operations. They must be executed within a REPEAT
loop, resulting in a total execution time of 19 instruction
cycles. The divide operation can be interrupted during
any of those 19 cycles without a loss of data.
Special MCU Features
The dsPIC33FJXXXMCX06A/X08A/X10A devices
feature a 17-bit by 17-bit, single-cycle multiplier that is
shared by both the MCU ALU and DSP engine. The
multiplier can perform signed, unsigned and mixed sign
multiplication. Using a 17-bit by 17-bit multiplier for 16-bit
by 16-bit multiplication not only allows you to perform
mixed sign multiplication, it also achieves accurate
results for special operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
dsPIC33FJXXXMCX06A/X08A/X10A CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
16
23
23
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
23
16
DMA
RAM
16
DMA
Controller
Address Generator Units
Address Latch
16
Program Memory
EA MUX
Data Latch
ROM Latch
24
Control Signals
to Various Blocks
Instruction Reg
Literal Data
Instruction
Decode and
Control
16
16
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-Bit ALU
16
To Peripheral Modules
DS70594D-page 24
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 3-2:
dsPIC33FJXXXMCX06A/X08A/X10A PROGRAMMER’S MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
DSP
Accumulators
AD15
AD31
AD0
AccA
AccB
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
REPEAT Loop Counter
15
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
2009-2012 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
DS70594D-page 25
dsPIC33FJXXXMCX06A/X08A/X10A
3.4
CPU Control Registers
REGISTER 3-1:
R-0
OA
SR: CPU STATUS REGISTER
R-0
R/C-0
R/C-0
OB
SA(1)
(1)
SB
R-0
OAB
R/C-0
(4)
SAB
R -0
R/W-0
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
R/W-0(3)
(2)
IPL
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Settable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(4)
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
4:
This bit may be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU interrupt priority
level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
DS70594D-page 26
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL: CPU Interrupt Priority Level Status bits(2)
111 = CPU interrupt priority level is 7 (15), user interrupts disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU interrupt priority level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
4:
This bit may be read or cleared (not set).
The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU interrupt priority
level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when
IPL = 1.
The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
2009-2012 Microchip Technology Inc.
DS70594D-page 27
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
bit 15
U-0
—
R/W-0
SATA
bit 7
R/W-0
SATB
bit 11
bit 10-8
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
DL
R-0
bit 8
Legend:
R = Readable bit
0’ = Bit is cleared
bit 15-13
bit 12
U-0
—
R/W-1
SATDW
R/W-0
ACCSAT
C = Clearable bit
W = Writable bit
‘x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
001 = 1 DO loop active
000 = 0 DO loops active
SATA: AccA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: AccB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.
DS70594D-page 28
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
3.5
Arithmetic Logic Unit (ALU)
3.6
DSP Engine
The dsPIC33FJXXXMCX06A/X08A/X10A ALU is
16 bits wide and is capable of addition, subtraction, bit
shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in
nature. Depending on the operation, the ALU may
affect the values of the Carry (C), Zero (Z), Negative
(N), Overflow (OV) and Digit Carry (DC) Status bits in
the SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
The DSP engine consists of a high-speed, 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations which
require no additional data. These instructions are ADD,
SUB and NEG.
Refer to the “16-bit MCU and DSC Programmer’s
Reference Manual” (DS70157) for information on the
SR bits affected by each instruction.
The
dsPIC33FJXXXMCX06A/X08A/X10A
CPU
incorporates hardware support for both multiplication
and division. This includes a dedicated hardware
multiplier and support hardware for 16-bit-divisor
division.
3.5.1
MULTIPLIER
Using the high-speed, 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed sign operation in several MCU multiplication
modes:
1.
2.
3.
4.
5.
6.
7.
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
3.5.2
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
The dsPIC33FJXXXMCX06A/X08A/X10A devices are
a single-cycle, instruction flow architecture; therefore,
concurrent operation of the DSP engine with MCU
instruction flow is not possible. However, some MCU
ALU and DSP engine resources may be used
concurrently by the same instruction (e.g., ED, EDAC).
The DSP engine has various options selected through
various bits in the CPU Core Control register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for AccA (SATA)
Automatic saturation on/off for AccB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
Accumulator Saturation mode selection (ACCSAT)
Table 2-1 provides a summary of DSP instructions. A
block diagram of the DSP engine is shown in
Figure 3-3.
TABLE 3-1:
Instruction
CLR
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
A=0
A = (x – y)2
A = A + (x – y)2
A = A + (x • y)
A = A + x2
No change in A
A=x•y
A = x2
A=–x•y
A=A–x•y
Yes
No
No
Yes
No
Yes
No
No
No
Yes
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both the
16-bit divisor (Wn) and any W register (aligned) pair
(W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/
16-bit and 16-bit/16-bit instructions take the same
number of cycles to execute.
2009-2012 Microchip Technology Inc.
DS70594D-page 29
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-Bit Accumulator A
40-Bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
16
X Data Bus
Barrel
Shifter
40
Y Data Bus
Sign-Extend
32
Zero Backfill
16
32
33
17-Bit
Multiplier/Scaler
16
16
To/From W Array
DS70594D-page 30
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
3.6.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value which is
sign-extended to 40 bits. Integer data is inherently represented as a signed two’s complement value, where
the MSb is defined as a sign bit. Generally speaking,
the range of an N-bit two’s complement integer is -2N-1
to 2N-1 – 1. For a 16-bit integer, the data range is
-32768 (0x8000) to 32767 (0x7FFF) including 0. For a
32-bit integer, the data range is -2,147,483,648
(0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).
When the multiplier is configured for fractional multiplication, the data is represented as a two’s complement
fraction, where the MSb is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX
format). The range of an N-bit two’s complement
fraction with this implied radix point is -1.0 to (1 – 21-N).
For a 16-bit fraction, the Q15 data range is -1.0
(0x8000) to 0.999969482 (0x7FFF) including 0 and has
a precision of 3.01518 x 10-5. In Fractional mode, the
16 x 16 multiply operation generates a 1.31 product
which has a precision of 4.65661 x 10-10.
The same multiplier is used to support the MCU
multiply instructions which include integer 16-bit
signed, unsigned and mixed sign multiplies.
3.6.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true, or complement
data into the other input. In the case of addition, the
Carry/Borrow input is active-high and the other input is
true data (not complemented); whereas in the case of
subtraction, the Carry/Borrow input is active-low and
the other input is complemented. The adder/subtracter
generates Overflow Status bits, SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described above and the SAT (CORCON)
and ACCSAT (CORCON) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
3.
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
3.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its
pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter prior to accumulation.
2009-2012 Microchip Technology Inc.
Adder/Subtracter, Overflow and
Saturation
4.
5.
6.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
The OA and OB bits are modified each time data passes
through the adder/subtracter. When set, they indicate
that the most recent operation has overflowed into the
accumulator guard bits (bits 32 through 39). The OA and
OB bits can also optionally generate an arithmetic
warning trap when they and the corresponding Overflow
Trap Flag Enable bits (OVATE, OVBTE) in the INTCON1
register (refer to Section 7.0 “Interrupt Controller”)
are set. This allows the user to take immediate action, for
example, to correct system gain.
DS70594D-page 31
dsPIC33FJXXXMCX06A/X08A/X10A
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user. When set, they indicate that the
accumulator has overflowed its maximum range (bit 31
for 32-bit saturation or bit 39 for 40-bit saturation) and
will be saturated (if saturation is enabled). When
saturation is not enabled, SA and SB default to bit 39
overflow, and thus, indicate that a catastrophic overflow
has occurred. If the COVTE bit in the INTCON1 register
is set, SA and SB bits will generate an arithmetic
warning trap when saturation is disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB), and the logical OR of
SA and SB (in bit SAB). This allows programmers to
check one bit in the STATUS register to determine if
either accumulator has overflowed or one bit to determine if either accumulator has saturated. This would be
useful for complex number arithmetic, which typically
uses both the accumulators.
The device supports three Saturation and Overflow
modes:
1.
2.
3.
Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until
cleared by the user. This is referred to as ‘super
saturation’ and provides protection against
erroneous data or unexpected algorithm
problems (e.g., gain calculations).
Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive 1.31 value (0x007FFFFFFF) or maximally
negative 1.31 value (0x0080000000) into the
target accumulator. The SA or SB bit is set and
remains set until cleared by the user. When this
Saturation mode is in effect, the guard bits are
not used (so the OA, OB or OAB bits are never
set).
Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user. No saturation operation
is performed and the accumulator is allowed to
overflow (destroying its sign). If the COVTE bit in
the INTCON1 register is set, a catastrophic
overflow can initiate a trap exception.
DS70594D-page 32
3.6.2.2
Accumulator ‘Write Back’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
1.
2.
W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
[W13]+ = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then
incremented by 2 (for a word write).
3.6.2.3
Round Logic
The round logic is a combinational block which
performs a conventional (biased) or convergent
(unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a
16-bit, 1.15 data value which is passed to the data
space write saturation logic. If rounding is not indicated
by the instruction, a truncated 1.15 data value is stored
and the least significant word is simply discarded.
Conventional rounding zero-extends bit 15 of the accumulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator). If the ACCxL word (bits 0
through 15 of the accumulator) is between 0x8000 and
0xFFFF (0x8000 included), ACCxH is incremented. If
ACCxL is between 0x0000 and 0x7FFF, ACCxH is left
unchanged. A consequence of this algorithm is that
over a succession of random rounding operations, the
value tends to be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is
examined. If it is ‘1’, ACCxH is incremented. If it is ‘0’,
ACCxH is not modified. Assuming that bit 16 is
effectively random in nature, this scheme removes any
rounding bias that may accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC) or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the X bus, subject to data saturation (see
Section 3.6.2.4 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator
write-back operation will function in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
3.6.2.4
Data Space Write Saturation
3.6.3
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated – but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate
1.15 fractional value as output to write to data space
memory.
The barrel shifter is capable of performing up to 16-bit
arithmetic or logic right shifts, or up to 16-bit left shifts
in a single cycle. The source can be either of the two
DSP accumulators or the X bus (to support multi-bit
shifts of register or memory data).
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly. For input data greater than
0x007FFF, data written to memory is forced to the maximum positive 1.15 value, 0x7FFF. For input data less
than 0xFF8000, data written to memory is forced to the
maximum negative 1.15 value, 0x8000. The Most
Significant bit of the source (bit 39) is used to determine
the sign of the operand being tested.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions
16 to 31 for right shifts and between bit positions 0 to
16 for left shifts.
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
2009-2012 Microchip Technology Inc.
DS70594D-page 33
dsPIC33FJXXXMCX06A/X08A/X10A
NOTES:
DS70594D-page 34
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
4.0
MEMORY ORGANIZATION
4.1
Note 1: This data sheet summarizes the features of the dsPIC33FJXXXMCX06A/
X08A/X10A family of devices. However, it is not intended to be a comprehensive
reference
source.
To
complement the information in this data
sheet, refer to Section 3. “Data
Memory” (DS70202) and Section 4.
“Program Memory” (DS70203) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip
web
site
(www.microchip.com).
The dsPIC33FJXXXMCX06A/X08A/X10A architecture
features separate program and data memory spaces,
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
FIGURE 4-1:
The program address memory space of the
dsPIC33FJXXXMCX06A/X08A/X10A devices is 4M
instructions. The space is addressable by a 24-bit
value derived from either the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (0x000000 to
0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG to permit access to
the Configuration bits and Device ID sections of the
configuration memory space. Memory usage for the
dsPIC33FJXXXMCX06A/X08A/X10A family of devices
is shown in Figure 4-1.
PROGRAM MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES
dsPIC33FJ64MCXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Memory Space
Program Address Space
User Program
Flash Memory
(22K instructions)
dsPIC33FJ128MCXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
dsPIC33FJ256MCXXXA
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(44K instructions)
User Program
Flash Memory
(88K instructions)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x00ABFE
0x00AC00
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
0x02ABFE
0x02AC00
Unimplemented
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
Configuration Memory Space
0x7FFFFE
0x800000
Note:
Reserved
Reserved
Reserved
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
0xF7FFFE
0xF80000
0xF80017
0xF80010
0xFEFFFE
0xFF0000
0xFFFFFE
Memory areas are not shown to scale.
2009-2012 Microchip Technology Inc.
DS70594D-page 35
dsPIC33FJXXXMCX06A/X08A/X10A
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
All
dsPIC33FJXXXMCX06A/X08A/X10A
devices
reserve the addresses between 0x00000 and
0x000200 for hard-coded program execution vectors.
A hardware Reset vector is provided to redirect code
execution from the default value of the PC on device
Reset to the actual start of code. A GOTO instruction is
programmed by the user at 0x000000, with the actual
address for the start of code at 0x000002.
The program memory space is organized in
word-addressable blocks. Although it is treated as
24 bits wide, it is more appropriate to think of each
address of the program memory as a lower and upper
word, with the upper byte of the upper word being
unimplemented. The lower word always has an even
address, while the upper word has an odd address
(Figure 4-2).
dsPIC33FJXXXMCX06A/X08A/X10A devices also
have two interrupt vector tables located from 0x000004
to 0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the many device interrupt sources
to be handled by separate Interrupt Service Routines
(ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
FIGURE 4-2:
msw
Address
PROGRAM MEMORY ORGANIZATION
16
8
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS70594D-page 36
least significant word
most significant word
23
0x000001
0x000003
0x000005
0x000007
INTERRUPT AND TRAP VECTORS
Instruction Width
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
4.2
Data Address Space
The dsPIC33FJXXXMCX06A/X08A/X10A CPU has a
separate 16-bit wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. Data
memory maps of devices with different RAM sizes are
shown in Figure 4-3 through Figure 4-5.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA = 0) is used for
implemented memory addresses, while the upper half
(EA = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
dsPIC33FJXXXMCX06A/X08A/X10A devices implement a total of up to 30 Kbytes of data memory. Should
an EA point to a location outside of this area, an all-zero
word or byte will be returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes of each word have even addresses, while the
Most Significant Bytes have odd addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® microcontrollers and improve data space memory usage
efficiency, the dsPIC33FJXXXMCX06A/X08A/X10A
instruction set supports both word and byte operations.
As a consequence of byte accessibility, all Effective
Address calculations are internally scaled to step
through word-aligned memory. For example, the core
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] will result in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSb of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities
with shared (word) address decode but separate write
lines. Data byte writes only write to the corresponding
side of the array or register which matches the byte
address.
2009-2012 Microchip Technology Inc.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed; if it occurred on a
write, the instruction will be executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user to examine the
machine state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSb of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
4.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJXXXMCX06A/X08A/X10A
core
and
peripheral modules for controlling the operation of the
device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note:
4.2.4
The actual set of peripheral features and
interrupts varies by the device. Please
refer to the corresponding device tables
and pinout diagrams for device-specific
information.
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an Address Pointer.
DS70594D-page 37
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES WITH
8-Kbyte RAM
MSb
Address
MSb
2-Kbyte
SFR Space
LSb
Address
16 Bits
LSb
0x0000
0x0001
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8-Kbyte
Near
Data
Space
X Data RAM (X)
8-Kbyte
SRAM Space
0x17FF
0x1801
0x1FFF
0x2001
0x27FF
0x2801
0x17FE
0x1800
Y Data RAM (Y)
0x1FFE
0x2000
DMA RAM
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS70594D-page 38
0x27FE
0x2800
0xFFFE
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 4-4:
DATA MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES WITH
16-Kbyte RAM
MSb
Address
16 Bits
MSb
2-Kbyte
SFR Space
LSb
0x0000
0x0001
SFR Space
0x07FF
0x0801
0x1FFF
16-Kbyte
SRAM Space
LSb
Address
X Data RAM (X)
0x27FF
0x2801
0x3FFF
0x4001
0x47FF
0x4801
0x07FE
0x0800
8-Kbyte
Near
Data
Space
0x1FFE
0x27FE
0x2800
Y Data RAM (Y)
0x3FFE
0x4000
DMA RAM
0x8001
0x47FE
0x4800
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
2009-2012 Microchip Technology Inc.
0xFFFE
DS70594D-page 39
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 4-5:
DATA MEMORY MAP FOR dsPIC33FJXXXMCX06A/X08A/X10A DEVICES WITH
30-Kbyte RAM
MSb
Address
MSb
2-Kbyte
SFR Space
0x0001
LSb
Address
16 Bits
LSb
0x0000
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8-Kbyte
Near
Data
Space
X Data RAM (X)
30-Kbyte
SRAM Space
0x47FF
0x4801
0x47FE
0x4800
Y Data RAM (Y)
0x77FF
0x7800
0x7FFF
0x8001
Optionally
Mapped
into Program
Memory
X Data
Unimplemented (X)
0xFFFF
DS70594D-page 40
DMA RAM
0x77FE
0x7800
0x7FFE
0x8000
0xFFFE
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
4.2.5
X AND Y DATA SPACES
The core has two data spaces: X and Y. These data
spaces can be considered either separate (for some
DSP instructions) or as one unified, linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms,
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. There are separate
read and write data buses for X data space. The X read
data bus is the read data path for all instructions that
view data space as combined X and Y address space.
It is also the X data prefetch path for the dual operand
DSP instructions (MAC class).
4.2.6
DMA RAM
Every dsPIC33FJXXXMCX06A/X08A/X10A device
contains 2 Kbytes of dual ported DMA RAM located at
the end of Y data space. Memory location is part of Y
data RAM and is in the DMA RAM space, and is
accessible simultaneously by the CPU and the DMA
controller module. DMA RAM is utilized by the DMA
controller to store data to be transferred to various
peripherals using DMA, as well as data transferred from
various peripherals using DMA. The DMA RAM can be
accessed by the DMA controller without having to steal
cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED, EDAC,
MAC, MOVSAC, MPY, MPY.N and MSC) to provide two
concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All Effective Addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
2009-2012 Microchip Technology Inc.
DS70594D-page 41
CPU CORE REGISTERS MAP
2009-2012 Microchip Technology Inc.
SFR Name
SFR
Addr
WREG0
0000
Working Register 0
xxxx
WREG1
0002
Working Register 1
xxxx
WREG2
0004
Working Register 2
xxxx
WREG3
0006
Working Register 3
xxxx
WREG4
0008
Working Register 4
xxxx
WREG5
000A
Working Register 5
xxxx
WREG6
000C
Working Register 6
xxxx
WREG7
000E
Working Register 7
xxxx
WREG8
0010
Working Register 8
xxxx
WREG9
0012
Working Register 9
xxxx
WREG10
0014
Working Register 10
xxxx
WREG11
0016
Working Register 11
xxxx
WREG12
0018
Working Register 12
xxxx
WREG13
001A
Working Register 13
xxxx
WREG14
001C
Working Register 14
xxxx
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
Accumulator A Low Word Register
0000
ACCAH
0024
Accumulator A High Word Register
0000
ACCAU
0026
Accumulator A Upper Word Register
0000
ACCBL
0028
Accumulator B Low Word Register
0000
ACCBH
002A
Accumulator B High Word Register
0000
ACCBU
002C
Accumulator B Upper Word Register
0000
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
TBLPAG
0032
—
—
—
—
—
—
—
PSVPAG
0034
—
—
—
—
—
—
—
RCOUNT
0036
Repeat Loop Counter Register
xxxx
DCOUNT
0038
DCOUNT
xxxx
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
Program Counter High Byte Register
0000
—
Table Page Address Pointer Register
0000
—
Program Memory Visibility Page Address Pointer Register
0000
DOSTARTL
0
—
—
—
—
—
—
0040
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
CORCON
0044
—
—
—
US
EDT
MODCON
0046
XMODEN
YMODEN
—
—
XMODSRT
0048
XS
0
xxxx
XMODEND
004A
XE
1
xxxx
Legend:
—
—
—
DOSTARTH
—
—
DOENDH
xxxx
—
00xx
DOENDL
DL
0
xxxx
00xx
IPL2
IPL1
IPL0
RA
N
OV
Z
C
0000
SATA
SATB
SATDW
ACCSAT
IPL3
PSV
RND
IF
0020
BWM
YWM
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
XWM
0000
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 42
TABLE 4-1:
CPU CORE REGISTERS MAP (CONTINUED)
SFR Name
SFR
Addr
YMODSRT
004C
YMODEND
004E
XBREV
0050
BREN
DISICNT
0052
—
—
BSRAM
0750
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR
IR_BSR
RL_BSR
0000
0752
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_SSR
IR_SSR
RL_SSR
0000
SSRAM
Legend:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 0
All
Resets
YS
0
xxxx
YE
1
xxxx
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
XB
xxxx
Disable Interrupts Counter Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
xxxx
DS70594D-page 43
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-1:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX10A DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CNEN2
0062
—
—
—
—
—
—
—
—
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
0000
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
CNPU1
0068
CNPU2
006A
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
CN8PUE
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX08A DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CNEN2
0062
—
—
—
—
—
—
—
—
—
—
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
0000
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
—
—
—
CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
0000
CNPU1
0068
CNPU2
006A
Legend:
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-4:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJXXXMCX06A DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
CNEN1
0060
CN15IE
CN14IE
CN13IE
CN12IE
CN11IE
CN10IE
CN9IE
CN8IE
CN7IE
CN6IE
CNEN2
0062
—
—
—
—
—
—
—
—
—
—
CNPU1
0068
CN8PUE
CN7PUE
CN6PUE
CN5PUE
CNPU2
006A
—
—
—
2009-2012 Microchip Technology Inc.
Legend:
Bit 4
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 5
All
Resets
CN1IE
CN0IE
0000
CN17IE
CN16IE
0000
Bit 3
CN5IE
CN4IE
CN3IE
CN2IE
CN21IE
CN20IE
—
CN18IE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
CN18PUE CN17PUE CN16PUE
0000
CN21PUE CN20PUE
—
Bit 2
Bit 0
Bit 4
Bit 1
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 44
TABLE 4-2:
SFR
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
INTCON1
0080
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE
INTCON2
0082
ALTIVT
DISI
—
—
—
IFS0
0084
—
DMA1IF
AD1IF
U1TXIF
U1RXIF
IFS1
0086
U2TXIF
U2RXIF
INT2IF
T5IF
T4IF
OC4IF
Bit 5
Bit 4
Bit 3
OSCFAIL
—
0000
INT1EP
INT0EP
0000
OC1IF
IC1IF
INT0IF
0000
—
MI2C1IF
SI2C1IF
0000
OVBTE
COVTE
—
—
—
—
—
INT4EP
INT3EP
INT2EP
T3IF
T2IF
OC2IF
IC2IF
DMA0IF
T1IF
OC3IF
DMA2IF
IC8IF
IC7IF
AD2IF
INT1IF
CNIF
SPI1IF SPI1EIF
Bit 6
All
Resets
Bit 8
—
Bit 7
Bit 0
Bit 9
Bit 2
Bit 1
SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR
IFS2
0088
T6IF
DMA4IF
—
OC8IF
OC7IF
OC6IF
OC5IF
IC6IF
IC5IF
IC4IF
IC3IF
DMA3IF
C1IF
C1RXIF
SPI2IF
SPI2EIF
0000
IFS3
008A
FLTAIF
—
DMA5IF
—
—
QEIIF
PWMIF
C2IF
C2RXIF
INT4IF
INT3IF
T9IF
T8IF
MI2C2IF
SI2C2IF
T7IF
0000
—
—
0000
IFS4
008C
—
—
—
—
—
IEC0
0094
—
DMA1IE
AD1IE
U1TXIE
U1RXIE
IEC1
0096
U2TXIE
U2RXIE
INT2IE
T5IE
T4IE
OC4IE
—
C2TXIF
C1TXIF
DMA7IF
DMA6IF
—
U2EIF
U1EIF
FLTBIF
T3IE
T2IE
OC2IE
IC2IE
DMA0IE
T1IE
OC1IE
IC1IE
INT0IE
OC3IE
DMA2IE
IC8IE
IC7IE
AD2IE
INT1IE
CNIE
—
SPI1IE SPI1EIE
MI2C1IE SI2C1IE
0000
0000
IEC2
0098
T6IE
DMA4IE
—
OC8IE
OC7IE
OC6IE
OC5IE
IC6IE
IC5IE
IC4IE
IC3IE
DMA3IE
C1IE
C1RXIE
SPI2IE
SPI2EIE
0000
IEC3
009A
FLTAIE
—
DMA5IE
—
—
QEIIE
PWMIE
C2IE
C2RXIE
INT4IE
INT3IE
T9IE
T8IE
MI2C2IE
SI2C2IE
T7IE
0000
—
—
—
—
—
—
—
C2TXIE
C1TXIE
DMA7IE
DMA6IE
—
U2EIE
U1EIE
FLTBIE
0000
DS70594D-page 45
IEC4
009C
—
IPC0
00A4
—
T1IP
—
OC1IP
—
IC1IP
—
INT0IP
4444
IPC1
00A6
—
T2IP
—
OC2IP
—
IC2IP
—
DMA0IP
4444
IPC2
00A8
—
U1RXIP
—
SPI1IP
—
SPI1EIP
—
T3IP
4444
IPC3
00AA
—
—
DMA1IP
—
AD1IP
—
U1TXIP
0444
IPC4
00AC
—
CNIP
—
—
MI2C1IP
—
SI2C1IP
4044
IPC5
00AE
—
IC8IP
—
IC7IP
—
AD2IP
—
INT1IP
4444
IPC6
00B0
—
T4IP
—
OC4IP
—
OC3IP
—
DMA2IP
4444
IPC7
00B2
—
U2TXIP
—
U2RXIP
—
INT2IP
—
T5IP
4444
IPC8
00B4
—
C1IP
—
C1RXIP
—
SPI2IP
—
SPI2EIP
4444
IPC9
00B6
—
IC5IP
—
IC4IP
—
IC3IP
—
DMA3IP
4444
IPC10
00B8
—
OC7IP
—
OC6IP
—
OC5IP
—
IC6IP
4444
IPC11
00BA
—
T6IP
—
DMA4IP
—
—
OC8IP
4404
IPC12
00BC
—
T8IP
—
MI2C2IP
—
SI2C2IP
—
T7IP
4444
IPC13
00BE
—
—
INT4IP
—
INT3IP
—
T9IP
4444
IPC14
00C0
—
—
QEIIP
—
PWMIP
—
C2IP
IPC15
00C2
—
—
DMA5IP
—
IPC16
00C4
—
U2EIP
—
U1EIP
—
FLTBIP
0444
IPC17
00C6
—
C1TXIP
—
DMA7IP
—
DMA6IP
4444
INTTREG
00E0
—
Legend:
—
—
—
C2RXIP
—
—
—
FLTAIP
—
—
—
—
C2TXIP
—
—
—
—
—
—
—
—
—
ILR
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
VECNUM
—
—
0444
—
4040
0000
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-5:
SFR
Name
SFR
Addr
TIMER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
TON
—
TSIDL
—
—
—
TMR3HLD 0108
—
—
—
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000
FFFF
TGATE
TCKPS
—
TSYNC
TCS
—
0000
Timer2 Register
0000
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
T3CON
0112
TON
—
TSIDL
—
—
—
—
TMR4
0114
TMR5HLD 0116
FFFF
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Timer4 Register
0000
Timer5 Holding Register (for 32-bit operations only)
xxxx
TMR5
0118
Timer5 Register
0000
PR4
011A
Period Register 4
FFFF
PR5
011C
Period Register 5
T4CON
011E
TON
—
TSIDL
—
—
—
—
T5CON
0120
TON
—
TSIDL
—
—
—
—
TMR6
0122
TMR7HLD 0124
FFFF
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Timer6 Register
0000
Timer7 Holding Register (for 32-bit operations only)
xxxx
2009-2012 Microchip Technology Inc.
TMR7
0126
Timer7 Register
0000
PR6
0128
Period Register 6
FFFF
PR7
012A
Period Register 7
T6CON
012C
TON
—
TSIDL
—
—
—
—
T7CON
012E
TON
—
TSIDL
—
—
—
—
TMR8
0130
TMR9HLD 0132
FFFF
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Timer8 Register
0000
Timer9 Holding Register (for 32-bit operations only)
xxxx
TMR9
0134
Timer9 Register
0000
PR8
0136
Period Register 8
FFFF
PR9
0138
Period Register 9
T8CON
013A
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
T32
—
TCS
—
0000
T9CON
013C
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS
—
—
TCS
—
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
FFFF
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 46
TABLE 4-6:
SFR Name
SFR
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
IC6BUF
0154
IC6CON
0156
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
Legend:
INPUT CAPTURE REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
ICI
ICOV
ICBNE
ICM
Input 1 Capture Register
—
ICTMR
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
—
ICSIDL
—
—
—
—
—
ICTMR
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
xxxx
Input 8 Capture Register
—
0000
xxxx
Input 7 Capture Register
—
0000
xxxx
Input 6 Capture Register
—
0000
xxxx
Input 5 Capture Register
—
0000
xxxx
Input 4 Capture Register
—
0000
xxxx
Input 3 Capture Register
—
All
Resets
xxxx
Input 2 Capture Register
—
Bit 0
0000
xxxx
0000
DS70594D-page 47
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-7:
SFR Name
OUTPUT COMPARE REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
OC3RS
018C
Output Compare 3 Secondary Register
OC3R
018E
Output Compare 3 Register
OC3CON
0190
OC4RS
0192
Output Compare 4 Secondary Register
OC4R
0194
Output Compare 4 Register
OC4CON
0196
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC5RS
0198
Output Compare 5 Secondary Register
OC5R
019A
Output Compare 5 Register
OC5CON
019C
OC6RS
019E
Output Compare 6 Secondary Register
OC6R
01A0
Output Compare 6 Register
OC6CON
01A2
OC7RS
01A4
Output Compare 7 Secondary Register
OC7R
01A6
Output Compare 7 Register
OC7CON
01A8
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2009-2012 Microchip Technology Inc.
OC8RS
01AA
Output Compare 8 Secondary Register
OC8R
01AC
Output Compare 8 Register
OC8CON
01AE
Legend:
—
—
OCSIDL
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM
0000
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 48
TABLE 4-8:
SFR Name Addr.
8-OUTPUT PWM REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
PTSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
—
Bit 5
Bit 4
PTOPS
Bit 3
Bit 2
PTCKPS
Bit 1
Bit 0
PTMOD
Reset State
P1TCON
01C0
PTEN
P1TMR
01C2
PTDIR
PWM Timer Count Value Register
0000 0000 0000 0000
P1TPER
01C4
—
PWM Time Base Period Register
0000 0000 0000 0000
P1SECMP
01C6 SEVTDIR
PWM Special Event Compare Register
PWM1CON1 01C8
—
—
—
—
PWM1CON2 01CA
—
—
—
—
P1DTCON1 01CC
DTBPS
P1DTCON2
—
—
—
01CE
—
PMOD4
PMOD3
PMOD2
PMOD1
SEVOPS
DTB
—
—
0000 0000 0000 0000
PEN4H
PEN3H
PEN2H
PEN1H
PEN4L
PEN3L
PEN2L
PEN1L
0000 0000 1111 1111
—
—
—
—
—
IUE
OSYNC
UDIS
0000 0000 0000 0000
DTAPS
—
—
0000 0000 0000 0000
DTA
0000 0000 0000 0000
DTS4A
DTS4I
DTS3A
DTS3I
DTS2A
DTS2I
DTS1A
DTS1I
0000 0000 0000 0000
P1FLTACON 01D0 FAOV4H FAOV4L FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L
FLTAM
—
—
—
FAEN4
FAEN3
FAEN2
FAEN1
0000 0000 0000 0000
P1FLTBCON 01D2 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L
FLTBM
—
—
—
FBEN4
FBEN3
FBEN2
FBEN1
0000 0000 0000 0000
P1OVDCON 01D4 POVD4H POVD4L POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L POUT4H POUT4L POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L
1111 1111 0000 0000
P1DC1
01D6
PWM Duty Cycle #1 Register
0000 0000 0000 0000
P1DC2
01D8
PWM Duty Cycle #2 Register
0000 0000 0000 0000
P1DC3
01DA
PWM Duty Cycle #3 Register
0000 0000 0000 0000
P1DC4
01DC
PWM Duty Cycle #4 Register
0000 0000 0000 0000
Legend:
u = uninitialized bit, — = unimplemented, read as ‘0’
DS70594D-page 49
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-9:
SFR
Name
Addr
.
QEI REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12 Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
SWPAB
PCDOUT
CEID
QEOUT
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
QEI1CON
01E0 CNTERR
—
QEISIDL
INDX
UPDN
DFLT1CON
01E2
—
—
—
—
POS1CNT
01E4
Position Counter
0000 0000 0000 0000
MAX1CNT
01E6
Maximum Count
1111 1111 1111 1111
Legend:
—
QEIM
IMV
TQGATE
TQCKPS
QECK
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
—
—
—
—
0000 0000 0000 0000
u = uninitialized bit, — = unimplemented, read as ‘0’
TABLE 4-11:
I2C1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
I2C1 Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
I2C1 Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
I2C1 Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
I2C1 Address Mask Register
0000
SFR Name
Legend:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
All
Resets
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12:
SFR Name
Bit 7
I2C2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
2009-2012 Microchip Technology Inc.
I2C2RCV
0210
—
—
—
—
—
—
—
—
I2C2 Receive Register
I2C2TRN
0212
—
—
—
—
—
—
—
—
I2C2 Transmit Register
I2C2BRG
0214
—
—
—
—
—
—
—
Bit 2
Bit 1
Bit 0
All
Resets
0000
00FF
Baud Rate Generator Register
0000
I2C2CON
0216
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
I2C2STAT
0218
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
I2C2ADD
021A
—
—
—
—
—
—
I2C2 Address Register
0000
021C
—
—
—
—
—
—
I2C2 Address Mask Register
0000
I2C2MSK
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1000
0000
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 50
TABLE 4-10:
SFR Name
SFR
Addr
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
—
USIDL
IREN
RTSMD
—
—
UTXBRK
UTXEN
Bit 9
Bit 8
Bit 7
Bit 6
UEN1
UEN0
WAKE
LPBACK
UTXBF
TRMT
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
U1TXREG
0224
—
—
—
—
—
—
—
UART1 Transmit Register
U1RXREG
0226
—
—
—
—
—
—
—
UART1 Receive Register
U1BRG
0228
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14:
SFR
Name
SFR
Addr
UTXINV UTXISEL0
URXISEL
Bit 2
Bit 1
PDSEL
FERR
OERR
Bit 0
All
Resets
STSEL
0000
URXDA
0110
xxxx
0000
Baud Rate Generator Prescaler
0000
UART2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
U2MODE
0230
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U2STA
0232
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
URXISEL
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
PDSEL
FERR
OERR
Bit 0
All
Resets
STSEL
0000
URXDA
0110
U2TXREG
0234
—
—
—
—
—
—
—
UART2 Transmit Register
xxxx
U2RXREG
0236
—
—
—
—
—
—
—
UART2 Receive Register
0000
U2BRG
0238
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15:
SFR
Name
Baud Rate Generator Prescaler
SPI1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
—
—
CKE
SSEN
—
SPI1CON2
0244
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16:
SFR Name
0000
Bit 5
Bit 4
SPIROV
—
—
CKP
MSTEN
—
—
Bit 3
Bit 2
Bit 1
Bit 0
—
—
SPITBF
SPIRBF
SPRE
—
—
PPRE
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
All
Resets
0000
0000
0000
0000
SPI2 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
DS70594D-page 51
SPI2STAT
0260
SPIEN
—
SPISIDL
—
—
—
—
—
—
SPIROV
—
SPI2CON1
0262
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE
SSEN
CKP
MSTEN
SPI2CON2
0264
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
—
—
SPI2BUF
0268
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SPI2 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE
—
—
PPRE
—
FRMDLY
—
0000
0000
0000
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-13:
File Name
Addr
ADC1BUF0
0300
AD1CON1
0320
AD1CON2
0322
ADC1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
—
—
CSCNA
CHPS
—
—
Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
CH123SA
0000
ADC1 Data Buffer 0
VCFG
AD1CON3
0324
ADRC
—
—
AD1CHS123
0326
—
—
—
AD1CHS0
0328 CH0NB
—
—
xxxx
SSRC
BUFS
—
CH123SB
—
—
SMPI
SAMC
ADCS
CH123NB
—
—
—
0000
CH123NA
CH0NA
—
—
AD1PCFGH(1) 032A PCFG31 PCFG30 PCFG29
PCFG28
PCFG27 PCFG26 PCFG25
PCFG24
PCFG23
PCFG22
PCFG21
PCFG20
PCFG19 PCFG18 PCFG17
PCFG16
0000
AD1PCFGL
032C PCFG15 PCFG14 PCFG13
PCFG12
PCFG11 PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
AD1CSSH(1)
032E
CSS31
CSS30
CSS29
CSS28
CSS27
CSS26
CSS25
CSS24
CSS23
CSS22
CSS21
CSS20
CSS19
CSS18
CSS17
CSS16
0000
AD1CSSL
0330
CSS15
CSS14
CSS13
CSS12
CSS11
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
AD1CON4
0332
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 6
Bit 5
Legend:
Note 1:
Addr
ADC2BUF0
0340
AD2CON1
0360
AD2CON2
0362
AD2CON3
0364
0000
DMABL
0000
0000
ADC2 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
ADON
—
ADSIDL
ADDMABM
—
AD12B
FORM
—
—
CSCNA
CHPS
VCFG
ADRC
—
—
Bit 8
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
SIMSAM
ASAM
SAMP
DONE
0000
BUFM
ALTS
0000
xxxx
SSRC
BUFS
—
SMPI
SAMC
—
—
—
—
0368
CH0NB
—
—
—
Reserved
036A
—
—
—
—
AD2PCFGL
036C PCFG15
PCFG14
PCFG13
PCFG12
Reserved
036E
—
—
—
—
—
—
AD2CSSL
0370
CSS15
CSS14
CSS13
CSS12
CSS11
AD2CON4
0372
—
—
—
—
—
AD2CHS123 0366
Bit 9
ADC2 Data Buffer 0
AD2CHS0
2009-2012 Microchip Technology Inc.
Legend:
CH0SA
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Not all ANx inputs are available on all devices. Refer to the device pin diagrams for available ANx inputs.
TABLE 4-18:
File Name
CH0SB
All
Resets
Bit 4
—
ADCS
CH123NB
CH123SB
CH0SB
—
—
—
—
—
—
CH0NA
—
—
—
—
0000
CH123NA
CH123SA
0000
0000
CH0SA
0000
—
—
—
—
—
—
—
—
—
—
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
—
—
—
—
—
—
—
—
—
—
0000
CSS10
CSS9
CSS8
CSS7
CSS6
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
—
—
—
—
—
—
—
—
PCFG11 PCFG10
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DMABL
0000
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 52
TABLE 4-17:
File Name Addr
DMA REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
DMA0CON 0380
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
DMA0REQ 0382
FORCE
—
—
—
—
—
—
—
—
Bit 5
Bit 4
AMODE
Bit 3
Bit 2
—
—
Bit 1
Bit 0
MODE
IRQSEL
All
Resets
0000
0000
DMA0STA
0384
STA
0000
DMA0STB
0386
STB
0000
DMA0PAD
0388
PAD
DMA0CNT
038A
—
—
—
—
—
—
DMA1CON 038C
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA1REQ 038E
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA1STA
0390
STA
0000
DMA1STB
0392
STB
0000
DMA1PAD
0394
PAD
DMA1CNT
0396
—
—
—
—
—
—
DMA2CON 0398
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA2REQ 039A
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA2STA
039C
STA
0000
DMA2STB
039E
STB
0000
DMA2PAD
03A0
PAD
DMA2CNT
03A2
—
—
—
—
—
—
DMA3CON 03A4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA3REQ 03A6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA3STA
03A8
STA
0000
DMA3STB
03AA
STB
0000
DMA3PAD 03AC
PAD
DMA3CNT 03AE
—
—
—
—
—
—
DMA4CON 03B0
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA4REQ 03B2
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA4STA
03B4
STA
0000
DMA4STB
03B6
STB
0000
DMA4PAD
03B8
PAD
DS70594D-page 53
DMA4CNT 03BA
—
—
—
—
—
—
DMA5CON 03BC
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA5REQ 03BE
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
IRQSEL
—
MODE
0000
0000
DMA5STA
03C0
STA
0000
DMA5STB
03C2
STB
0000
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-19:
File Name Addr
DMA REGISTER MAP (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
DMA5CNT 03C6
—
—
—
—
—
—
DMA6CON 03C8
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
—
—
—
—
—
—
—
—
DMA5PAD
Bit 9
Bit 8
03C4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PAD
DMA6REQ 03CA FORCE
All
Resets
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA6STA
03CC
STA
0000
DMA6STB
03CE
STB
0000
DMA6PAD
03D0
PAD
DMA6CNT 03D2
—
—
—
—
—
—
DMA7CON 03D4
CHEN
SIZE
DIR
HALF
NULLW
—
—
—
—
DMA7REQ 03D6
FORCE
—
—
—
—
—
—
—
—
0000
CNT
—
AMODE
0000
—
—
MODE
IRQSEL
0000
0000
DMA7STA
03D8
STA
0000
DMA7STB
03DA
STB
0000
DMA7PAD 03DC
PAD
DMA7CNT 03DE
—
—
—
—
—
CNT
DMACS0
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0
DMACS1
03E2
DSADR
03E4
Legend:
—
—
—
—
0000
—
LSTCH
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
XWCOL7
PPST7
DSADR
XWCOL6 XWCOL5
PPST6
PPST5
0000
XWCOL4
XWCOL3
XWCOL2
PPST4
PPST3
PPST2
XWCOL1 XWCOL0
PPST1
PPST0
0000
0000
0000
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 54
TABLE 4-19:
File Name
ECAN1 REGISTER MAP WHEN WIN (C1CTRL) = 0 OR 1
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C1CTRL1
0400
—
—
CSIDL
ABAT
—
C1CTRL2
0402
—
—
—
—
—
C1VEC
0404
—
—
—
C1FCTRL
0406
—
—
C1FIFO
0408
—
—
DMABS
Bit 10
Bit 9
Bit 8
Bit 7
—
—
—
—
—
REQOP
—
Bit 5
OPMODE
FILHIT
—
Bit 6
—
—
—
—
—
—
—
Bit 4
Bit 3
—
CANCAP
Bit 1
Bit 0
—
—
WIN
DNCNT
—
FBP
Bit 2
All
Resets
0480
0000
ICODE
0000
FSA
0000
FNRB
0000
C1INTF
040A
—
—
TXBO
TXBP
RXBP
TXWAR
C1INTE
040C
—
—
—
—
—
—
C1EC
040E
C1CFG1
0410
—
—
—
—
—
C1CFG2
0412
—
WAKFIL
—
—
—
C1FEN1
0414
C1FMSKSEL1
0418
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C1FMSKSEL2
041A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
—
—
IVRIF
WAKIF
ERRIF
—
FIFOIF
RBOVIF
RBIF
TBIF
0000
IVRIE
WAKIE
ERRIE
—
FIFOIE
RBOVIE
RBIE
TBIE
0000
TERRCNT
RERRCNT
—
—
—
SEG2PH
FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10
FLTEN9 FLTEN8
SJW
0000
BRP
SEG2PHTS
SAM
SEG1PH
FLTEN7
FLTEN6
FLTEN5
FLTEN4
0000
PRSEG
FLTEN3
FLTEN2
FLTEN1
0000
FLTEN0
FFFF
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-21:
File Name
RXWAR EWARN
Addr
ECAN1 REGISTER MAP WHEN WIN (C1CTRL) = 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0400041E
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
See definition when WIN = x
C1RXFUL1
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9
RXFUL0
0000
C1RXFUL2
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
RXFUL8
0000
C1RXOVF1
0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9
RXOVF0
0000
C1RXOVF2
042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
0000
RXOVF8
RXFUL7
RXOVF7
RXFUL6
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
C1TR01CON 0430
TXEN1
TXABT1 TXLARB1 TXERR1
TXREQ1
RTREN1
TX1PRI
TXEN0
TXABAT0 TXLARB0 TXERR0
TXREQ0
RTREN0
TX0PRI
0000
C1TR23CON 0432
TXEN3
TXABT3 TXLARB3 TXERR3
TXREQ3
RTREN3
TX3PRI
TXEN2
TXABAT2 TXLARB2 TXERR2
TXREQ2
RTREN2
TX2PRI
0000
C1TR45CON 0434
TXEN5
TXABT5 TXLARB5 TXERR5
TXREQ5
RTREN5
TX5PRI
TXEN4
TXABAT4 TXLARB4 TXERR4
TXREQ4
RTREN4
TX4PRI
0000
C1TR67CON 0436
TXEN7
TXABT7 TXLARB7 TXERR7
TXREQ7
RTREN7
TX7PRI
TXEN6
TXABAT6 TXLARB6 TXERR6
TXREQ6
RTREN6
TX6PRI
xxxx
C1RXD
0440
ECAN1 Received Data Word
xxxx
C1TXD
0442
ECAN1 Transmit Data Word
xxxx
DS70594D-page 55
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-20:
File Name
ECAN1 REGISTER MAP WHEN WIN (C1CTRL) = 1
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0400041E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
2009-2012 Microchip Technology Inc.
C1BUFPNT1
0420
F3BP
F2BP
F1BP
F0BP
0000
C1BUFPNT2
0422
F7BP
F6BP
F5BP
F4BP
0000
C1BUFPNT3
0424
F11BP
F10BP
F9BP
F8BP
0000
C1BUFPNT4
0426
F15BP
F14BP
F13BP
F12BP
0000
C1RXM0SID
0430
SID
—
EID
xxxx
C1RXM0EID
0432
EID
C1RXM1SID
0434
SID
—
EID
C1RXM1EID
0436
EID
C1RXM2SID
0438
SID
—
EID
C1RXM2EID
043A
EID
C1RXF0SID
0440
SID
—
EID
C1RXF0EID
0442
EID
C1RXF1SID
0444
SID
—
EID
C1RXF1EID
0446
EID
C1RXF2SID
0448
SID
—
EID
C1RXF2EID
044A
EID
C1RXF3SID
044C
SID
—
EID
C1RXF3EID
044E
EID
C1RXF4SID
0450
SID
—
EID
C1RXF4EID
0452
EID
C1RXF5SID
0454
SID
—
EID
C1RXF5EID
0456
EID
C1RXF6SID
0458
SID
—
EID
C1RXF6EID
045A
EID
C1RXF7SID
045C
SID
—
EID
C1RXF7EID
045E
EID
C1RXF8SID
0460
SID
—
EID
C1RXF8EID
0462
EID
C1RXF9SID
0464
SID
—
EID
C1RXF9EID
0466
EID
C1RXF10SID
0468
SID
—
EID
C1RXF10EID
046A
EID
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SID
—
MIDE
EID
SID
—
MIDE
xxxx
EID
SID
—
MIDE
xxxx
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
xxxx
xxxx
xxxx
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 56
TABLE 4-22:
File Name
ECAN1 REGISTER MAP WHEN WIN (C1CTRL) = 1 (CONTINUED)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C1RXF11SID
046C
SID
C1RXF11EID
046E
EID
C1RXF12SID
0470
SID
C1RXF12EID
0472
EID
C1RXF13SID
0474
SID
C1RXF13EID
0476
EID
C1RXF14SID
0478
SID
C1RXF14EID
047A
EID
C1RXF15SID
047C
SID
C1RXF15EID
047E
EID
Legend:
Bit 10
Bit 9
Bit 8
Bit 7
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 6
SID
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
EXIDE
—
EID
—
EID
—
EID
—
EID
—
EID
EID
SID
—
EXIDE
—
EXIDE
—
EXIDE
—
EXIDE
EID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
All
Resets
xxxx
xxxx
xxxx
xxxx
DS70594D-page 57
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-22:
File Name
ECAN2 REGISTER MAP WHEN WIN (C1CTRL) = 0 OR 1 FOR dsPIC33FJXXXMC708A/710A DEVICES
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
C2CTRL1
0500
—
—
CSIDL
ABAT
—
C2CTRL2
0502
—
—
—
—
—
C2VEC
0504
—
—
—
C2FCTRL
0506
—
—
TXBP
RXBP
TXWAR
—
—
—
Bit 8
Bit 7
—
—
—
—
—
REQOP
—
Bit 5
OPMODE
FILHIT
DMABS
Bit 6
—
—
—
—
Bit 4
Bit 3
—
CANCAP
Bit 1
Bit 0
—
—
WIN
DNCNT
—
—
Bit 2
0480
0000
ICODE
—
All
Resets
0000
FSA
0000
C2FIFO
0508
—
—
C2INTF
050A
—
—
TXBO
C2INTE
050C
—
—
—
C2EC
050E
C2CFG1
0510
—
—
—
—
—
C2CFG2
0512
—
WAKFIL
—
—
—
SEG2PH
SEG2PHTS
C2FEN1
0514
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10 FLTEN9 FLTEN8
FLTEN7
C2FMSKSEL1
0518
F7MSK
F6MSK
F5MSK
F4MSK
F3MSK
F2MSK
F1MSK
F0MSK
0000
C2FMSKSEL2
051A
F15MSK
F14MSK
F13MSK
F12MSK
F11MSK
F10MSK
F9MSK
F8MSK
0000
Legend:
RXWAR EWARN
—
—
—
—
IVRIF
WAKIF
ERRIF
FNRB
IVRIE
WAKIE
ERRIE
TERRCNT
0000
—
FIFOIF
RBOVIF
RBIF
TBIF
—
FIFOIE
RBOVIE
RBIE
TBIE
RERRCNT
—
—
—
SJW
SEG1PH
FLTEN6 FLTEN5 FLTEN4
0000
PRSEG
FLTEN3
0000
0000
BRP
SAM
0000
FLTEN2 FLTEN1
0000
FLTEN0
FFFF
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24:
File Name
FBP
Addr
ECAN2 REGISTER MAP WHEN WIN (C1CTRL) = 0 FOR dsPIC33FJXXXMC708A/710A DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
0500051E
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
See definition when WIN = x
C2RXFUL1
0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10
RXFUL0
0000
C2RXFUL2
0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16
RXFUL9
RXFUL8
RXFUL7
RXFUL6
0000
C2RXOVF1
0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7
0000
C2RXOVF2
052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
0000
2009-2012 Microchip Technology Inc.
C2TR01CON 0530
TXEN1
TX
ABAT1
TX
LARB1
TX
ERR1
TX
REQ1
RTREN1
TX1PRI
TXEN0
TX
ABAT0
TX
LARB0
TX
ERR0
TX
REQ0
RTREN0
TX0PRI
0000
C2TR23CON 0532
TXEN3
TX
ABAT3
TX
LARB3
TX
ERR3
TX
REQ3
RTREN3
TX3PRI
TXEN2
TX
ABAT2
TX
LARB2
TX
ERR2
TX
REQ2
RTREN2
TX2PRI
0000
C2TR45CON 0534
TXEN5
TX
ABAT5
TX
LARB5
TX
ERR5
TX
REQ5
RTREN5
TX5PRI
TXEN4
TX
ABAT4
TX
LARB4
TX
ERR4
TX
REQ4
RTREN4
TX4PRI
0000
C2TR67CON 0536
TXEN7
TX
ABAT7
TX
LARB7
TX
ERR7
TX
REQ7
RTREN7
TX7PRI
TXEN6
TX
ABAT6
TX
LARB6
TX
ERR6
TX
REQ6
RTREN6
TX6PRI
xxxx
C2RXD
0540
ECAN2 Recieved Data Word
xxxx
C2TXD
0542
ECAN2 Transmit Data Word
xxxx
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 58
TABLE 4-23:
File Name
Addr
ECAN2 REGISTER MAP WHEN WIN (C1CTRL) = 1 FOR dsPIC33FJXXXMC708A/710A DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0500051E
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
See definition when WIN = x
DS70594D-page 59
C2BUFPNT1
0520
F3BP
F2BP
F1BP
F0BP
0000
C2BUFPNT2
0522
F7BP
F6BP
F5BP
F4BP
0000
C2BUFPNT3
0524
F11BP
F10BP
F9BP
F8BP
0000
C2BUFPNT4
0526
F15BP
F14BP
F13BP
F12BP
0000
C2RXM0SID
0530
SID
C2RXM0EID
0532
EID
C2RXM1SID
0534
SID
C2RXM1EID
0536
EID
C2RXM2SID
0538
SID
C2RXM2EID
053A
EID
C2RXF0SID
0540
SID
C2RXF0EID
0542
EID
C2RXF1SID
0544
SID
C2RXF1EID
0546
EID
C2RXF2SID
0548
SID
C2RXF2EID
054A
EID
C2RXF3SID
054C
SID
C2RXF3EID
054E
EID
C2RXF4SID
0550
SID
C2RXF4EID
0552
EID
C2RXF5SID
0554
SID
C2RXF5EID
0556
EID
C2RXF6SID
0558
SID
C2RXF6EID
055A
EID
C2RXF7SID
055C
SID
C2RXF7EID
055E
EID
C2RXF8SID
0560
SID
C2RXF8EID
0562
EID
C2RXF9SID
0564
SID
C2RXF9EID
0566
EID
C2RXF10SID
0568
SID
C2RXF10EID 056A
EID
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
SID
—
MIDE
—
EID
EID
SID
—
MIDE
—
EID
EID
SID
—
MIDE
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
EID
xxxx
xxxx
—
EID
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
xxxx
xxxx
—
EID
xxxx
xxxx
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-25:
File Name
Addr
ECAN2 REGISTER MAP WHEN WIN (C1CTRL) = 1 FOR dsPIC33FJXXXMC708A/710A DEVICES (CONTINUED)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
C2RXF11SID
056C
SID
C2RXF11EID
056E
EID
C2RXF12SID
0570
SID
C2RXF12EID
0572
EID
C2RXF13SID
0574
SID
C2RXF13EID
0576
EID
C2RXF14SID
0578
SID
C2RXF14EID 057A
EID
C2RXF15SID 057C
SID
C2RXF15EID 057E
EID
Legend:
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
SID
Bit 4
Bit 3
Bit 2
—
EXIDE
—
Bit 1
Bit 0
EID
EID
SID
—
EXIDE
—
EXIDE
—
EID
—
EXIDE
—
EID
—
EXIDE
xxxx
xxxx
—
EID
EID
SID
xxxx
xxxx
EID
SID
xxxx
xxxx
EID
SID
All
Resets
xxxx
xxxx
—
EID
EID
xxxx
xxxx
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-26:
PORTA REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISA
02C0
TRISA15
TRISA14
—
—
—
TRISA10
TRISA9
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
C6FF
PORTA
02C2
RA15
RA14
—
—
—
RA10
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
LATA
02C4
LATA15
LATA14
—
—
—
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
ODCA(2)
06C0
ODCA15
ODCA14
—
—
—
—
—
—
—
—
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-27:
PORTB REGISTER MAP(1)
2009-2012 Microchip Technology Inc.
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISB
02C6
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02C8
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CA
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 60
TABLE 4-25:
PORTC REGISTER MAP(1)
Bit 13
Bit 12
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
—
—
TRISC4
TRISC3
TRISC2
TRISC1
—
F01E
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
xxxx
—
—
—
—
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
TRISC
02CC
PORTC
02CE
RC15
RC14
RC13
RC12
LATC
02D0
LATC15
LATC14
LATC13
LATC12
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
Bit 14
Bit 10
Addr
TABLE 4-29:
Bit 15
Bit 11
File Name
TRISC15 TRISC14 TRISC13 TRISC12
PORTD REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISD
02D2
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
PORTD
02D4
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
LATD
02D6
LATD15
LATD14
LATD13
LATD12
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
ODCD
06D2
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-30:
PORTE REGISTER MAP(1)
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISE
02D8
—
—
—
—
—
—
TRISE9
TRISE8
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
01FF
PORTE
02DA
—
—
—
—
—
—
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
LATE
02DC
—
—
—
—
—
—
LATE9
LATE8
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
xxxx
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
File Name
TABLE 4-31:
PORTF REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
DS70594D-page 61
TRISF
02DE
—
—
TRISF13
TRISF12
—
—
—
TRISF8
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
31FF
PORTF
02E0
—
—
RF13
RF12
—
—
—
RF8
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
LATF
02E2
—
—
LATF13
LATF12
—
—
—
LATF8
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
ODCF
06DE
—
—
ODCF13
ODCF12
—
—
—
ODCF8
ODCF7
ODCF6
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
dsPIC33FJXXXMCX06A/X08A/X10A
2009-2012 Microchip Technology Inc.
TABLE 4-28:
PORTG REGISTER MAP(1)
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TRISG
02E4
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
PORTG
02E6
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
LATG
02E8
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
ODCG
06E4
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
0000
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams.
TABLE 4-33:
SYSTEM CONTROL REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
RCON
0740
TRAPR
IOPUWR
—
—
—
—
—
VREGS
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
BOR
POR
xxxx(1)
OSCCON
0742
—
CLKLOCK
—
LOCK
—
CF
—
LPOSCEN
OSWEN
0300(2)
COSC
—
CLKDIV
0744
ROI
PLLFBD
0746
—
—
—
—
—
—
—
OSCTUN
0748
—
—
—
—
—
—
—
Legend:
Note 1:
2:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and type of Reset.
TABLE 4-34:
DOZE
NOSC
DOZEN
FRCDIV
PLLPOST
—
PLLPRE
—
—
TUN
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
0766
—
—
—
—
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000(1)
NVMOP
NVMKEY
0000
2009-2012 Microchip Technology Inc.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 4-35:
File Name
0000
NVM REGISTER MAP
Addr
Legend:
Note 1:
0030
—
File Name
NVMKEY
3040
PLLDIV
Addr
PMD REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
PMD1
0770
T5MD
T4MD
T3MD
T2MD
T1MD
QEI1MD
PWMMD
—
I2C1MD
U2MD
U1MD
SPI2MD
SPI1MD
C2MD
C1MD
AD1MD
0000
PMD2
0772
IC8MD
IC7MD
IC6MD
IC5MD
IC4MD
IC3MD
IC2MD
IC1MD
OC8MD
OC7MD
OC6MD
OC5MD
OC4MD
OC3MD
OC2MD
OC1MD
0000
PMD3
0774
T9MD
T8MD
T7MD
T6MD
—
—
—
—
—
—
—
—
—
—
I2C2MD
AD2MD
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for high pin count devices.
dsPIC33FJXXXMCX06A/X08A/X10A
DS70594D-page 62
TABLE 4-32:
dsPIC33FJXXXMCX06A/X08A/X10A
4.2.7
4.2.8
SOFTWARE STACK
In addition to its use as a working register, the W15
register in the dsPIC33FJXXXMCX06A/X08A/X10A
devices is also used as a software Stack Pointer. The
Stack Pointer always points to the first available free
word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-6. For a PC push
during any CALL instruction, the MSb of the PC is
zero-extended before the push, ensuring that the MSb
is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 0x2000 in RAM, initialize the
SPLIM with the value 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
Stack Grows Towards
Higher Address
0x0000
CALL STACK FRAME
15
0
PC
000000000 PC
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
2009-2012 Microchip Technology Inc.
DATA RAM PROTECTION FEATURE
The dsPIC33FJXXXMCX06A/X08A/X10A devices
support data RAM protection features which enable
segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security.
BSRAM (Secure RAM segment for BS) is accessible
only from the Boot Segment Flash code when enabled.
SSRAM (Secure RAM segment for RAM) is accessible
only from the Secure Segment Flash code when
enabled. See Table 4-1 for an overview of the BSRAM
and SSRAM SFRs.
4.3
Instruction Addressing Modes
The addressing modes in Table 4-36 form the basis of
the addressing modes optimized to support the specific
features of individual instructions. The addressing
modes provided in the MAC class of instructions are
somewhat different from those in the other instruction
types.
4.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
4.3.2
MCU INSTRUCTIONS
The 3-operand MCU instructions are of the following
form:
Operand 3 = Operand 1 Operand 2
where Operand 1 is always a working register (i.e., the
addressing mode can only be Register Direct) which is
referred to as Wb. Operand 2 can be a W register
fetched from data memory or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-Bit or 10-Bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual instructions may support different
subsets of these addressing modes.
DS70594D-page 63
dsPIC33FJXXXMCX06A/X08A/X10A
TABLE 4-36:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
4.3.3
The sum of Wn and a literal forms the EA.
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-Bit Literal
16-Bit Literal
Note:
4.3.4
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
MAC INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, utilize a simplified set of
addressing modes to allow the user to effectively
manipulate the Data Pointers through register indirect
tables.
DS70594D-page 64
The 2-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 will always be directed to the Y
AGU. The Effective Addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9, and Y data space
for W10 and W11.
Note:
Register Indirect with Register Offset
Addressing mode is only available for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
4.3.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
4.4
Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
Modulo Addressing can operate in either data or program
space (since the Data Pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing,
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are
certain restrictions on the buffer start address (for incrementing buffers) or end address (for decrementing
buffers), based upon the direction of the buffer.
The only exception to the usage restrictions is for
buffers which have a power-of-2 length. As these
buffers satisfy the start and end address criteria, they
may operate in a bidirectional mode (i.e., address
boundary checks will be performed on both the lower
and upper address boundaries).
4.4.1
START AND END ADDRESS
The Modulo Addressing scheme requires that a starting
and ending address be specified and loaded into the
16-bit Modulo Buffer Address registers: XMODSRT,
XMODEND, YMODSRT and YMODEND (see
Table 4-1).
Note:
The length of a circular buffer is not directly specified. It
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
4.4.2
W ADDRESS REGISTER
SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select which registers will
operate with Modulo Addressing. If XWM = 15, X RAGU
and X WAGU Modulo Addressing are disabled. Similarly,
if YWM = 15, Y AGU Modulo Addressing is disabled.
The X Address Space Pointer W register (XWM) to
which Modulo Addressing is to be applied is stored in
MODCON (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than 15 and the XMODEN bit is set at
MODCON.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than 15
and the YMODEN bit is set at MODCON.
Y space Modulo Addressing EA calculations assume word-sized data (LSb of
every EA is always clear).
FIGURE 4-7:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
MOV
#0x0000, W0
;W0 holds buffer fill value
MOV
#0x1110, W1
;point W1 to buffer
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations
;fill the next location
;increment the fill value
0x1163
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 Words
2009-2012 Microchip Technology Inc.
DS70594D-page 65
dsPIC33FJXXXMCX06A/X08A/X10A
4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than or greater
than the upper (for incrementing buffers) and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
Note:
4.5
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (e.g.,
[W7+W2]) is used, Modulo Address
correction is performed but the contents of
the register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order;
thus, the only operand requiring reversal is the modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled when the
following conditions exist:
1.
2.
3.
The BWM bits (W register selection) in the
MODCON register are any value other than 15
(the stack cannot be accessed using
Bit-Reversed Addressing).
The BREN bit is set in the XBREV register.
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
DS70594D-page 66
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is only
executed for Register Indirect with Pre-Increment or
Post-Increment Addressing and word-sized data
writes. It will not function for any other addressing
mode or for byte-sized data; normal addresses are
generated instead. When Bit-Reversed Addressing is
active, the W Address Pointer is always added to the
address modifier (XB) and the offset associated with
the Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. In the event that the user
attempts to do so, Bit-Reversed Addressing will assume priority for the X WAGU,
and X WAGU Modulo Addressing will be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN bit (XBREV), then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the Bit-Reversed Pointer.
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 4-8:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2
b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-37:
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
2009-2012 Microchip Technology Inc.
DS70594D-page 67
dsPIC33FJXXXMCX06A/X08A/X10A
4.6
4.6.1
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The dsPIC33FJXXXMCX06A/X08A/X10A architecture
uses a 24-bit wide program space and a 16-bit wide
data space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full, 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG = 0) or the configuration memory
(TBLPAG = 1).
Aside
from
normal
execution,
the
dsPIC33FJXXXMCX06A/X08A/X10A architecture provides two methods by which program space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated from time to time. It also allows
access to all bytes of the program word. The
remapping method allows an application to access a
large block of data on a read-only basis, which is ideal
for look ups from a large table of static data. It can only
access the least significant word of the program word.
TABLE 4-38:
Table 4-38 and Figure 4-9 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P refers to a program
space word, whereas D refers to a data space
word.
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
Program Space Address
Program Space Visibility
(Block Remap/Read)
0xxx
xxxx
xxxx
TBLPAG
0xxx xxxx
User
PC
0
Configuration
Note 1:
ADDRESSING PROGRAM SPACE
0
xxxx
xxxx xxx0
Data EA
xxxx xxxx xxxx xxxx
TBLPAG
Data EA
1xxx xxxx
xxxx xxxx xxxx xxxx
0
PSVPAG
0
xxxx xxxx
Data EA(1)
xxx xxxx xxxx xxxx
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG.
DS70594D-page 68
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
FIGURE 4-9:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
0
EA
1
0
PSVPAG
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word
alignment of data in the program and data spaces.
2: Table operations are not required to be word-aligned. Table read operations are permitted
in the configuration memory space.
2009-2012 Microchip Technology Inc.
DS70594D-page 69
dsPIC33FJXXXMCX06A/X08A/X10A
4.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
2.
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit
word wide address spaces residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P) to a data address (D).
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P) to a data address. Note that
D, the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (byte select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and
configuration spaces. When TBLPAG = 0, the table
page is located in the user memory space. When
TBLPAG = 1, the page is located in configuration
space.
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-10:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
0x020000
0x030000
00000000
00000000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn = 0)
TBLRDL.B (Wn = 1)
TBLRDL.B (Wn = 0)
TBLRDL.W
0x800000
DS70594D-page 70
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
4.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access of stored
constant data from the data space without the need to
use special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-11), only the lower 16 bits of the
FIGURE 4-11:
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
PSV access is temporarily disabled during
table reads/writes.
Note:
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV and are executed inside a
REPEAT loop, there will be some instances that require
two instruction cycles in addition to the specified
execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data using PSV to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG
02
23
15
Data Space
0
0x000000
0x0000
Data EA
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
0x800000
2009-2012 Microchip Technology Inc.
...while the lower 15 bits
of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
DS70594D-page 71
dsPIC33FJXXXMCX06A/X08A/X10A
NOTES:
DS70594D-page 72
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
5.0
three other lines for power (VDD), ground (VSS) and
Master Clear (MCLR). This allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. This also allows the most recent
firmware or a custom firmware to be programmed.
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXMCX06A/X08A/
X10A family of devices. However, it is not
intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section
5. “Flash Programming” (DS70191) in
the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the
Microchip
web
site
(www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
can write program memory data by blocks (or ‘rows’) of
64 instructions (192 bytes) at a time or by single
program memory word; the user can erase program
memory in blocks or ‘pages’ of 512 instructions
(1536 bytes) at a time.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
The dsPIC33FJXXXMCX06A/X08A/X10A devices contain internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Flash memory can be programmed in two ways:
1.
2.
In-Circuit Serial Programming™ (ICSP™)
programming capability
Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJXXXMCX06A/X08A/X10A
device to be serially programmed while in the end
application circuit. This is simply done with two lines for
programming clock and programming data (one of the
alternate programming pin pairs: PGECx/PGEDx), and
FIGURE 5-1:
Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The TBLRDL and TBLWTL instructions are used to read
or write to bits of program memory. TBLRDL and
TBLWTL can access program memory in both Word
and Byte modes.
The TBLRDH and TBLWTH instructions are used to read
or write to bits of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
User/Configuration
Space Select
2009-2012 Microchip Technology Inc.
16 bits
24-bit EA
Byte
Select
DS70594D-page 73
dsPIC33FJXXXMCX06A/X08A/X10A
5.2
RTSP Operation
The
dsPIC33FJXXXMCX06A/X08A/X10A
Flash
program memory array is organized into rows of
64 instructions or 192 bytes. RTSP allows the user to
erase a page of memory at a time, which consists of
eight rows (512 instructions), and to program one row
or one word at a time. Table 26-12 shows typical erase
and programming times. The 8-row erase pages and
single row write rows are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes
and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundaries.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
written. A programming cycle is required for
programming each row.
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 26-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the row write time, page erase time and word write
cycle time parameters (see Table 26-12).
EQUATION 5-1:
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN bits (see
Register 9-4) are set to ‘b111111, the minimum row
write time is equal to Equation 5-2.
EQUATION 5-2:
MINIMUM ROW WRITE
TIME
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.435ms
7.37 MHz 1 + 0.05 1 – 0.00375
The maximum row write time is equal to Equation 5-3.
EQUATION 5-3:
MAXIMUM ROW WRITE
TIME
11064 Cycles
T RW = ---------------------------------------------------------------------------------------------- = 1.586ms
7.37 MHz 1 – 0.05 1 – 0.00375
Setting the WR bit (NVMCON) starts the
operation and the WR bit is automatically cleared
when the operation is finished.
5.4
Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------7.37 MHz FRC Accuracy % FRC Tuning %
DS70594D-page 74
2009-2012 Microchip Technology Inc.
dsPIC33FJXXXMCX06A/X08A/X10A
REGISTER 5-1:
R/SO-0(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WREN
WRERR
—
—
—
—
—
WR
bit 15
bit 8
R/W-0(1)
U-0
—
U-0
ERASE
—
U-0
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP(2)
—
bit 7
bit 0
Legend:
R = Readable bit
SO = Settable Only bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
x = Bit is unknown
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP on the next WR command
0 = Perform the program operation specified by NVMOP on the next WR command
Unimplemented: Read as ‘0’
NVMOP: NVM Operation Select bits(2)
If ERASE = 1:
1111 = Memory bulk erase operation
1110 = Reserved
1101 = Erase General Segment
1100 = Erase Secure Segment
1011 = Reserved
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte
If ERASE = 0:
1111 = No operation
1110 = Reserved
1101 = No operation
1100 = No operation
1011 = Reserved
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
Note 1:
2:
These bits can only be reset on POR.
All other combinations of NVMOP are unimplemented.
2009-2012 Microchip Technology Inc.
DS70594D-page 75
dsPIC33FJXXXMCX06A/X08A/X10A
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
4.
5.
The user can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is as follows:
1.
2.
3.
Read eight rows of program memory
(512 instructions) and store it in data RAM.
Update the program data in RAM with the
desired new data.
Erase the block (see Example 5-1):
a) Set the NVMOP bits (NVMCON) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON) and WREN
(NVMCON) bits.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON). The erase
cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
DS70594D-page 76
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-3.
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
#0x4042, W0
MOV
W0, NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
MOV
W0, TBLPAG
MOV
#tbloffset(PROG_ADDR), W0
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
6.
Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
Write the program block to Flash memory:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
Repeat steps 4 and 5 using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG until all
512 instructions are written back to Flash memory.
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
;
; Initialize NVMCON
;
;
;
;
;
;
;
;
;
;
;
;
Initialize PM Page Boundary SFR
Initialize in-page EA[15:0] pointer
Set base address of erase block
Block all interrupts with priority 74)3@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
D
D1
E
e
E1
N
b
NOTE 1
12 3
α
NOTE 2
A
c
β
φ
A2
A1
L1
L
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI/HDGV
0,//,0(7(56
0,1
1
120
0$;
/HDG3LWFK
H
2YHUDOO+HLJKW
$
±
%6&
±
0ROGHG3DFNDJH7KLFNQHVV
$
6WDQGRII
$
±
)RRW/HQJWK
/
)RRWSULQW
/
5()
)RRW$QJOH
2YHUDOO:LGWK
(
%6&
2YHUDOO/HQJWK
'
%6&
0ROGHG3DFNDJH:LGWK
(
%6&
0ROGHG3DFNDJH/HQJWK
'
%6&
/HDG7KLFNQHVV
F
±
/HDG:LGWK
E
0ROG'UDIW$QJOH7RS
0ROG'UDIW$QJOH%RWWRP
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
&KDPIHUVDWFRUQHUVDUHRSWLRQDO VL]HPD\YDU\
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(74)3@
1RWH
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWS ZZZPLFURFKLSFRPSDFNDJLQJ
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
A
NOTE 2
φ
c
β
A2
A1
L
L1
8QLWV
'LPHQVLRQ/LPLWV
1XPEHURI/HDGV
0,//,0(7(56
0,1
1
120
0$;
/HDG3LWFK
H
2YHUDOO+HLJKW
$
±
%6&
±
0ROGHG3DFNDJH7KLFNQHVV
$
6WDQGRII
$
±
)RRW/HQJWK
/
)RRWSULQW
/
5()
)RRW$QJOH
2YHUDOO:LGWK
(
%6&
2YHUDOO/HQJWK
'
%6&
0ROGHG3DFNDJH:LGWK
(
%6&
0ROGHG3DFNDJH/HQJWK
'
%6&
/HDG7KLFNQHVV
F
±
/HDG:LGWK
E
0ROG'UDIW$QJOH7RS
0ROG'UDIW$QJOH%RWWRP
1RWHV
3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
&KDPIHUVDWFRUQHUVDUHRSWLRQDO VL]HPD\YDU\
'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH
'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(
工商网监
湘ICP备2023018690号
