EMC2113
RPM-Based Fan Controller with Multiple Temperature
Zones & Hardware Thermal Shutdown
PRODUCT FEATURES
Datasheet
General Description
Features
The EMC2113 is an SMBus compliant fan controller.
The fan driver can be operated using two methods, each
with two modes. The methods include an RPM-based
Fan Speed Control Algorithm and a direct PWM drive
setting. The modes include manually programming the
desired settings or using the internal programmable
temperature look-up table to select the desired setting
based on measured temperature.
— 4-wire fan compatible
— Both Low and High frequency PWM
The device includes high and low limits for all
temperature channels as well as a hardware set critical
temperature limit. This hardware set limit drives a
dedicated system shutdown pin.
Up to Three External Temperature Channels
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Supports transistor model for 90nm - 45nm Intel CPUs
Resistance Error Correction and Beta Compensation
1°C accurate (60°C to 125°C)
0.125°C resolution
Programmable High and Low limits
Hardware Programmable Thermal Shutdown
Temperature
— Cannot be altered by software
— 65°C to 127°C Range
— Dedicated system shutdown interrupt pin
Finally, the device includes an open-drain, active low
interrupt pin to flag temperature or fan control errors.
Notebook Computers
Projectors
Graphics Cards
Industrial and Networking Equipment
Temperature Look-Up Table
— Controls fan speed or PWM drive setting
— Eight steps that incorporate up to four temperature
zones simultaneously (user selectable)
— Supports forced DTS or standard temperature data
— Allows external PWM input (150Hz to 40kHz)
RPM-based fan control algorithm
— 2% accurate from 500 RPM to 16k RPM
— Automatic Tachometer feedback
The EMC2113 includes a temperature monitor that
measures up to three (3) external diodes and the
internal diode. The temperature monitors offer 1°C
accuracy (for external diodes) with sophisticated
features to reduce errors introduced by series resistance
and beta variation of substrate thermal diode transistors
commonly found in processors.
Applications
Programmable Fan Control circuit
Internal Temperature Monitor
— ±1°C accuracy
— 0.125°C resolution
3.3V Supply Voltage
Open drain interrupt pin
SMBus 2.0 Interface
— SMBus Alert compatible
— Selectable SMBus Address via pull-up resistor and
ADDR_SEL pin
— Block Read and Write
2013 Microchip Technology Inc.
Available in 16-pin 4mm x 4mm QFN RoHS
Compliant package
DS20005251A-page 1
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
ORDERING INFORMATION:
ORDERING NUMBER
EMC2113-1-AP-TR
PACKAGE
16-pin 4mm x4mm QFN
(ROHS Compliant)
FEATURES
RPM-based Fan Speed Control
Algorithm, High Frequency PWM driver,
HW Thermal / Critical shutdown
This product meets the halogen maximum concentration values per IEC61249-2-21
DS20005251A-page 2
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table of Contents
Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2 Delta from EMC2103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1
4.2
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 5 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
5.2
System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1
SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2
SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.3
SMBus Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.4
SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.5
SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.6
SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.7
SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.3
Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.4
Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.5
Block Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.6
Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.7
Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 6 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1
SYS_SHDN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2
SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.3
TRIP_SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
PWM Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Fan Control Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1
Programming the Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2
DTS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
RPM-Based Fan Speed Control Algorithm (FSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.1
Programming the RPM-Based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . .
6.7
Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1
Stalled Fan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2
Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.1 Power Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 ALERT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2013 Microchip Technology Inc.
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DS20005251A-page 3
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
6.13
6.14
Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.1 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.2 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.3 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.4 Ideality Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13.5 Digital Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.1 Anti-Parallel Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14.2 Diode Faults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 7 Fan Control Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
7.24
7.25
7.26
7.27
7.28
7.29
7.30
7.31
7.32
7.33
7.34
7.35
7.36
7.37
7.38
7.39
7.40
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1
Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Critical/Thermal Shutdown Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pushed Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Input Duty Cycle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TRIP_SET Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Beta Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Critical Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14.1 Tcrit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Driver Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Driver Base Frequency Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Input Duty Cycle High Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Step Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Minimum Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Look Up Table Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Look Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS20005251A-page 4
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2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 8 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 9 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.1
9.2
EMC2113 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Appendix A Look Up Table Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A.1
A.2
A.3
Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.1
LUT Configuration Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.1
Fan Spin Up Configuration Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.2
LUT Configuration - Bit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3.1
LUT COnfiguration Bit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2013 Microchip Technology Inc.
DS20005251A-page 5
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table of Figures
Figure 1.1
Figure 3.1
Figure 5.1
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
EMC2113 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
EMC2113-1 Pin Diagram (16-Pin QFN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
System Diagram for EMC2113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Diagram of Critical/Thermal Shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Fan Control Look-Up Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16-Pin QFN 4mm x 4mm Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
16-Pin QFN 4mm x 4mm PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
16-Pin QFN 4mm x 4mm Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
EMC2113 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
DS20005251A-page 6
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
List of Tables
Table 2.1 LUT Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3.1 Pin Description for EMC2113-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.1 ADDR_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.6 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.1 SHDN_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.2 TRIP_SET Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.3 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.4 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.1 EMC2113 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.4 Critical/Thermal Shutdown Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.5 Critical/Thermal Shutdown Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.6 Pushed Temperature Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.7 PWM Duty Cycle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.8 TRIP_SET Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.9 Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.10 Ideality Factor Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.11 Substrate Diode Ideality Factor Look-Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.12 Beta Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.13 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.14 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.15 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.16 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.17 Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.18 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.19 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.20 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.21 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.22 Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.23 Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.24 Fan Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.25 PWM Driver Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.26 PWM Driver Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.27 PWM_BASEx[1:0] it Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.28 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.29 PWM Duty Cycle High Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.30 Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.31 PWM Divide Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.32 Fan Configuration 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.33 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.34 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2013 Microchip Technology Inc.
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DS20005251A-page 7
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.35 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.36 Fan Configuration 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.37 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.38 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.39 Gain Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.40 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.41 Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.42 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.43 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.44 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.45 Fan Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.46 Minimum Fan Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.47 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.48 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.49 TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.50 TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.51 Look Up Table Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.52 Look Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.53 Software Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.54 Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.55 ADDR_SEL[2:0] Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.56 SHDN_SEL[2:0] Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.57 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.58 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.59 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.1 Look Up Table Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.2 Look Up Table Example #1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.3 Fan Speed Control Table Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.4 Fan Speed Determination for Example #1 (using settings in Table A.3) . . . . . . . . . . . . . . . . .
Table A.5 Look Up Table Example #2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.6 Fan Speed Control Table Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.7 Fan Speed Determination for Example #2 (using settings in Table A.6) . . . . . . . . . . . . . . . . .
Table A.8 Look Up Table Example #3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.9 Fan Speed Control Table Example #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table A.10 Fan Speed Determination for Example #2 (using settings in Table A.9) . . . . . . . . . . . . . . . . .
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS20005251A-page 8
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2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 1 Block Diagram
Figure 1.1 EMC2113 Block Diagram
2013 Microchip Technology Inc.
DS20005251A-page 9
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 2 Delta from EMC2103
The EMC2113 is compatible with the EMC2103-2 with the following changes:
Removed two GPIOs - Pins 4 and 5 of the EMC2103-2 were GPIO pins. These have been
removed.
Added PWM Input functionality - This functionality allows the user to drive a PWM input into the
EMC2113. The duty cycle of the PWM represents a temperature value and can be used as an input
to the Fan Control Look Up Table.
Added ADDR_SEL functionality - This functionality allows the user to choose one of six SMBus
address options.
Updated Hysteresis within Look Up Table - The Fan Control Look Up Table in the EMC2113 allows
the user to program a different hysteresis value to apply to each temperature input channel instead
of a single hysteresis value that applies to all temperature input channels.
Updated input muxing for the Look Up Table - The Fan Control Look Up Table has more options
over which temperature channel is used for fan control.
Updated HW set shutdown functionality to include option for Internal diode
Added control to disable Ramp Rate control if one or more temperatures exceed the high limit
Added SMBus Block Read and Write capability
Table 2.1 LUT Options
TEMPERATURE INPUT
EMC2113 OPTIONS
Temperature Column 1
External Diode 1 -or- Pushed Temperature 1
Temperature Column 2
External Diode 2
Temperature Column 3
External Diode 3 -or- Pushed Temperature 1
Temperature Column 4
Internal Diode -or- Pushed Temperature 2
DS20005251A-page 10
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 3 Pin Layout
Figure 3.1 EMC2113-1 Pin Diagram (16-Pin QFN)
Table 3.1 Pin Description for EMC2113-1
PIN NUMBER
PIN NAME
PIN FUNCTION
PIN TYPE
1
DN1
Negative (cathode) analog input for External
Diode 1
AIO
2
DP1
Positive (anode) analog input for External
Diode 1
AIO
3
VDD
Power Supply
Power
4
PWM_IN
PWM input signal from host
DI (5V)
5
ADDR_SEL
Address Select Input
AIO
6
ALERT
Active low SMBus slave interrupt - requires
external pull-up resistor.
OD (5V)
7
SYS_SHDN
Active low Critical/Thermal Shutdown output requires external pull-up resistor
OD (5V)
2013 Microchip Technology Inc.
DS20005251A-page 11
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 3.1 Pin Description for EMC2113-1 (continued)
PIN NUMBER
PIN NAME
PIN FUNCTION
PIN TYPE
8
SMDATA
SMBus data input/output - requires external
pull-up resistor
DIOD (5V)
9
SMCLK
SMBus clock input - requires external pull-up
resistor
DI (5V)
10
TACH
Tachometer input for the Fan
DI (5V)
PWM - Open Drain PWM drive output for the
Fan (default)
OD (5V)
PWM - Push Pull PWM drive output for the
fan
DO
11
PWM
12
GND
Ground
Power
13
SHDN_SEL
Selects the hardware shutdown channel and
operating mode
AIO
14
TRIP_SET
Voltage input to set the Critical/Thermal
Shutdown threshold
AIO
DN2 - Negative (cathode) connection for
External Diode 2
AIO
DP3 - Positive (anode) connection for
External Diode 3
AIO
DP2 - Positive (anode connection for External
Diode 2
AIO
DN3 - Negative (cathode) connection for
External Diode 3
AIO
15
DN2 / DP3
16
DP2 / DN3
The pin types are described in detail below. All pins labelled with (5V) are 5V tolerant.
Note: For all 5V tolerant pins that require a pull-up resistor, the pull-up voltage cannot exceed 3.6V
when the device is unpowered.
Table 3.2 Pin Types
PIN TYPE
Power
DI
DESCRIPTION
This pin is used to supply power or ground to the device.
Digital Input - this pin is used as a digital input. This pin is 5V tolerant.
AIO
Analog Input / Output - this pin is used as an I/O for analog signals.
DO
Push / Pull Digital Output - this pin is used as a digital output. It can both source
and sink current.
DIO
Digital Input / Output this pin is used as a digital I/O. It can both source and
sink current.
OD
Open Drain Digital Output - this pin is used as a digital output. It is open drain
and requires a pull-up resistor. This pin is 5V tolerant.
DS20005251A-page 12
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 4 Electrical Characteristics
Table 4.1 Absolute Maximum Ratings
Voltage on 5V tolerant pins (VPULLUP)
-0.3 to 5.5
V
Voltage on 5V tolerant pins (|VPULLUP - VDD|) See Note 4.1
0 to 3.6
V
Voltage on VDD pin
-0.3 to 4
V
Voltage on any other pin to GND
-0.3 to VDD + 0.3
V
Package Power Dissipation
0.8W up to TA = 85°C
W
Junction to Ambient (JA)
50
°C/W
Operating Ambient Temperature Range
-40 to 125
°C
Storage Temperature Range
-55 to 150
°C
ESD Rating, All Pins, HBM
2000
V
Note: Stresses above those listed could cause permanent damage to the device. This is a stress
rating only and functional operation of the device at any other condition above those indicated
in the operation sections of this specification is not implied. When powering this device from
laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be
exceeded or device failure can result. Some power supplies exhibit voltage spikes on their
outputs when the AC power is switched on or off. In addition, voltage transients on the AC
power line may appear on the DC output. If this possibility exists, it is suggested that a clamp
circuit be used.
Note: All voltages are relative to ground.
Note: JA numbers are based on a recommended four 12 mil vias connecting the thermal pad to PCB
ground.
Note 4.1
For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed
3.6V when the EMC2113 is unpowered.
2013 Microchip Technology Inc.
DS20005251A-page 13
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
4.1
Electrical Specifications
Table 4.2 Electrical Specifications
VDD = 3V to 3.6V, TA = -40°C to 125°C, all Typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
DC Power
Supply Voltage
Supply Current
VDD
3
3.3
3.6
V
1.1
1.5
mA
4 Conversions/second, Fan
Driver active at maximum PWM
frequency, Dynamic Averaging
Enabled
0.7
1.1
mA
1 Conversion/second, Fan
Driver not active, Dynamic
Averaging Disabled
IDD
First Conversion
Ready
tCONV_T
150
300
ms
Time after power up before all
channels updated
SMBus Delay
tSMB_D
10
15
ms
Time before SMBus
communications should be sent
by host
External Temperature Monitors
Temperature
Accuracy
Temperature
Resolution
±0.5
±1
°C
60°C < TDIODE < 125°C
30°C < TA < 100°C
±1
±2
°C
-40°C < TDIODE < 125°C
0.125
Diode decoupling
capacitor
CFILTER
2200
Resistance Error
Corrected
RSERIES
100
°C
2700
pF
Connected across external
diode, CPU, GPU, or AMD diode
Ohm
Sum of series resistance in both
DP and DN lines
Internal Temperature Monitor
Temperature
Accuracy
TA
Temperature
Resolution
±0.5
±1
°C
±1
±2
°C
0.125
40°C < TA < 100°C
°C
RPM-Based Fan Controller
Tachometer Range
TACH
RPM Control
Accuracy
TACH
480
±1
16000
RPM
±2
%
PWM Fan Driver
PWM Resolution
PWM
PWM Duty Cycle
DUTY
DS20005251A-page 14
256
0
Steps
100
%
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 4.2 Electrical Specifications (continued)
VDD = 3V to 3.6V, TA = -40°C to 125°C, all Typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
PWM Input Detection
PWM Frequency
fPWM_IN
150
40k
Hz
TRIP_SET Measurement
TRIP_SET Decode
Accuracy
VTRIP
±0.5
±1
°C
TRIP_SET Decode
Accuracy
VTRIP
±1
±2
°C
1% resistor connected to ground
5% resistor connected to ground
Digital I/O pins
Input High Voltage
VIH
Input Low Voltage
VIL
Output High Voltage
VOH
Output Low Voltage
VOL
0.4
V
8 mA current sink
Leakage Current
ILEAK
±5
uA
ALERT and SYS_SHDN pins
Device powered or unpowered
TA < 85°C
4.2
2.0
V
0.8
V
VDD 0.4
8 mA current drive
V
SMBus Electrical Specifications
Table 4.3 SMBus Electrical Specifications
VDD= 3V to 3.6V, TA = -40°C to 125°C Typical values are at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface
Input High/Low Current
Input Capacitance
IIH / IIL
CIN
4
±5
uA
10
pF
Device powered or unpowered
TA < 85°C
SMBus Timing
Clock Frequency
fSMB
10
400
kHz
50
ns
Spike Suppression
tSP
Bus free time Start to
Stop
tBUF
1.3
us
Setup Time: Start
tSU:STA
0.6
us
Setup Time: Stop
tSU:STP
0.6
us
Data Hold Time
tHD:DAT
0.6
6
us
Data Setup Time
tSU:DAT
0.6
72
us
2013 Microchip Technology Inc.
DS20005251A-page 15
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 4.3 SMBus Electrical Specifications (continued)
VDD= 3V to 3.6V, TA = -40°C to 125°C Typical values are at TA = 27°C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
Clock Low Period
tLOW
1.3
us
Clock High Period
tHIGH
0.6
us
Clock/Data Fall time
tFALL
300
ns
Min = 20+0.1CLOAD ns
Clock/Data Rise time
tRISE
300
ns
Min = 20+0.1CLOAD ns
CLOAD
400
pF
Total per bus line
Capacitive Load
DS20005251A-page 16
TYP
MAX
UNITS
CONDITIONS
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 5 SMBus Slave Interface
The EMC2113 communicates with a host controller, such as an SIO, through the SMBus. The SMBus
is a two-wire serial communication protocol between a computer host and its peripheral devices.
5.1
System Management Bus Interface Protocol
The EMC2113 contains an SMBus slave interface. A detailed timing diagram is shown in Figure 5.1,
"SMBus Timing Diagram". Stretching of the SMCLK signal is supported, however the EMC2113 will not
stretch the clock signal.
Figure 5.1 SMBus Timing Diagram
5.1.1
SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
5.1.2
SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit slave address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the host device is writing data to the slave device. If this RD / WR
bit is a logic ‘1’, then the host device is reading data from the slave device.
The EMC2113 SMBus slave address is determined via the pull-up resistor connected to the
ADDR_SEL pin as shown Table 5.1, "ADDR_SEL Pin Decode".
Table 5.1 ADDR_SEL Pin Decode
PULL-UP RESISTOR VALUE
FAN CONTROL ADDRESS
4.7k Ohm ±5%
0101_100(r/w)
6.8k Ohm ±5%
0101_101(r/w)
10k Ohm ±5%
0101_110(r/w)
15k Ohm ±5%
1001_100(r/w)
2013 Microchip Technology Inc.
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Datasheet
Table 5.1 ADDR_SEL Pin Decode (continued)
5.1.3
PULL-UP RESISTOR VALUE
FAN CONTROL ADDRESS
22k Ohm ±5%
1001_101(r/w)
33k Ohm ±5%
1001_000(r/w)
SMBus Data Bytes
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
5.1.4
SMBus ACK and NACK Bits
The SMBus slave will acknowledge all data bytes that it receives. This is done by the slave device
pulling the SMBus Data line low after the 8th bit of each byte that is transmitted.
The Host will NACK (not acknowledge) the last data byte to be received from the slave by holding the
SMBus data line high after the 8th data bit has been sent.
5.1.5
SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC2113 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its slave interface and prepare
to receive further communications.
5.1.6
SMBus Time-out
The EMC2113 includes an SMBus time-out feature. Following a 30ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface.
The SMBus timeout defaults to enabled and can be disabled by setting the DIS_TO bit (see Section
7.12, "Configuration 2 Register").
5.1.7
SMBus and I2C Compliance
The major difference between SMBus and I2C devices is highlighted here. For complete compliance
information refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz.
2. The slave protocol will reset if the clock is held low longer than 30ms.
3. The slave protocol will reset if both the clock and the data line are high for longer than 150us (idle
condition).
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
5.2
SMBus Protocols
The EMC2113 slave interface is SMBus 2.0 compatible and support Send Byte, Read Byte, Receive
Byte, Write Byte, Block Read Byte, Block Write Byte, and the Alert Response Address as valid
protocols. These protocols are used as shown below.
All of the below protocols use the convention in Table 5.2, "Protocol Format". For the Slave Address
fields, the value of YYYY_YYY represents the programmed SMBus address.
DS20005251A-page 18
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 5.2 Protocol Format
DATA SENT TO
THE HOST
DATA SENT
TO DEVICE
# of bits sent
5.2.1
# of bits sent
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 5.3.
Table 5.3 Write Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
REGISTER
DATA
ACK
STOP
1 -> 0
YYYY_YYY
0
0
0 -> 1
0
XXh
0
0 -> 1
5.2.2
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 5.4.
Table 5.4 Read Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
START
SLAVE
ADDRESS
RD
ACK
REGISTER
DATA
NACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
0
1 -> 0
YYYY_YYY
1
0
XXh
1
0 -> 1
5.2.3
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol as shown in Table 5.5.
Table 5.5 Send Byte Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
STOP
1 -> 0
YYYY_YYY
0
0
XXh
1
0 -> 1
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
5.2.4
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register as shown in Table 5.6.
Table 5.6 Receive Byte Protocol
START
SLAVE
ADDRESS
RD
ACK
REGISTER DATA
NACK
STOP
1 -> 0
YYYY_YYY
1
0
XXh
1
0 -> 1
5.2.5
Block Write
The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in
Table 5.7. It is an extension of the Write Byte Protocol.
Table 5.7 Block Write Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
REGISTER
DATA
ACK
1 ->0
YYYY_YYY
0
0
XXh
0
XXh
0
REGISTER
DATA
ACK
REGISTER
DATA
ACK
...
REGISTER
DATA
ACK
STOP
XXh
0
XXh
0
...
XXh
0
0 -> 1
5.2.6
Block Read
The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in
Table 5.8. It is an extension of the Read Byte Protocol.
Table 5.8 Block Read Protocol
START
SLAVE
ADDRESS
WR
ACK
REGISTER
ADDRESS
ACK
START
SLAVE
ADDRESS
RD
ACK
REGISTER
DATA
1->0
YYYY_YYY
0
0
XXh
0
1 ->0
YYYY_YYY
1
0
XXh
ACK
REGISTER
DATA
ACK
REGISTER
DATA
ACK
REGISTER
DATA
ACK
...
REGISTER
DATA
NACK
STOP
0
XXh
0
XXh
0
XXh
0
...
XXh
1
0 -> 1
DS20005251A-page 20
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
5.2.7
Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert when configured to
operate as an interrupt.
When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA)
to the general address of 0001_100b. All devices with active interrupts will respond with their slave
address as shown in Table 5.9.
Table 5.9 Alert Response Address Protocol
START
ALERT
RESPONSE
ADDRESS
RD
ACK
DEVICE
ADDRESS
NACK
STOP
1 -> 0
0001_100
1
0
YYYY_YYY
1
0 -> 1
The EMC2113 slave interface will respond to the ARA in the following way if the ALERT pin is asserted.
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due to a bus contention event).
2. Set the MASK bit to clear the ALERT pin.
2013 Microchip Technology Inc.
DS20005251A-page 21
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Datasheet
Chapter 6 Product Description
The EMC2113 is an SMBus compliant fan controller with up to three (3) external and one (1) internal
temperature channels. The fan driver can be operated using two methods, each with two modes. The
methods include an RPM-based Fan Speed Control Algorithm and a direct PWM drive setting. The
modes include manually programming the desired settings or using the internal programmable
temperature look-up table to select the desired setting based on measured temperature.
The temperature monitors offer 1°C accuracy (for external diodes) with sophisticated features to
reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors
commonly found in processors (including support of the BJT or transistor model for a CPU diode).
The EMC2113 allows the user to program temperatures generated from external sources to control the
fan speed. This functionality also supports DTS data from the CPU. By pushing DTS or standard
temperature values into dedicated registers, the external temperature readings can be used in
conjunction with the external diode(s) and internal diode to control the fan speed.
The EMC2113 also allows the user to input a PWM input signal on the PWM_IN pin that is used as
an input to the Fan Speed Control Look Up Table.
The EMC2113 includes a hardware programmable temperature limit and dedicated system shutdown
output for thermal protection of critical circuitry.
Figure 6.1 shows a system diagram of the EMC2113.
Figure 6.1 System Diagram for EMC2113
DS20005251A-page 22
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
6.1
Critical/Thermal Shutdown
The EMC2113 provides a hardware Critical/Thermal Shutdown function for systems. Figure 6.2 is a
block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function
accepts configuration information from the pullup resistor of the SHDN_SEL pin.
The analog portion of the Critical/Thermal Shutdown function monitors the hardware determined
shutdown channel. This measured temperature is then compared with TRIP_SET point. This
TRIP_SET point is set by the system designer with a single external resistor.
The SYS_SHDN is asserted when the indicated temperature meets or exceeds the temperature
threshold (TTRIP) established by the TRIP_SET input pin for a number of consecutive measurements
defined by the fault queue.
Each of the software programmed temperature limits can be optionally configured to act as inputs to
the Critical/Thermal Shutdown independent of the hardware shutdown operation. When configured to
operate this way, the SYS_SHDN pin will be asserted when the temperature meets or exceeds the
programmed Tcrit Limit for the enabled channel (see Section 7.10).
Figure 6.2 Block Diagram of Critical/Thermal Shutdown
6.1.1
SYS_SHDN Pin
The SYS_SHDN pin is an active low dedicated system interrupt. This pin is asserted low when:
1. The programmed temperature channel (see Section 6.1.2) exceeds the hardware set limit (see
Section 6.1.3).
2. Any of the measured temperature channels meet or exceed their programmed TCRIT limits and
have been linked to the SYS_SHDN pin (see Section 7.10).
3. Any of the measured temperature channels meet or exceed their programmed High limits and have
been linked to the SYS_SHDN pin (see Section 7.11).
2013 Microchip Technology Inc.
DS20005251A-page 23
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
When the SYS_SHDN pin is asserted, it will remain asserted until the measured temperatures drop
below the respective limits minus the hysteresis. At this point, the pin will be released automatically.
6.1.2
SHDN_SEL Pin
The EMC2113 has a ‘strappable’ input (SHDN_SEL) allowing for configuration of the hardware
Critical/Thermal Shutdown input channel. The pull-up resistor used on this pin identifies which
configuration setting is used as shown in Table 6.1, "SHDN_SEL Pin Decode".
.
Table 6.1 SHDN_SEL Pin Decode
PULL UP
RESISTOR
MODE / DIODE
CHANNEL
< 4.7k Ohm
EXTERNAL DIODE 1 CONFIG
EXTERNAL DIODE 2 CONFIG
AMD CPU on
External Diode 1
Beta Compensation disabled
REC disabled
Beta and REC controls are locked
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
6.8k Ohm
2N3904 on External
Diode 1
Beta Compensation disabled
REC enabled
Beta and REC controls are locked
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
10k Ohm
Intel CPU or
2N3904 on External
Diode 1
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are locked
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
15k Ohm
Internal Diode
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
22k Ohm
Intel CPU or
2N3904 on External
Diode 2
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are locked
> 33k Ohm
Intel CPU or
2N3904 on External
Diode 1
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
Beta Compensation enabled (auto)
REC enabled
Beta and REC controls are not locked
APPLICATION NOTE: The SHDN_SEL pin decode settings with Beta Compensation enabled (auto) will support a
diode connected 2N3904 diode normally.
6.1.3
TRIP_SET Pin
The EMC2113’s TRIP_SET pin is an analog input to the Critical/Thermal Shutdown block which sets
the Thermal Shutdown temperature. The system designer creates a voltage level at the input through
a simple resistor connected to GND as shown in Figure 6.2, "Block Diagram of Critical/Thermal
Shutdown". The value of this resistor is used to create an input voltage on the TRIP_SET pin which
is translated into a temperature ranging from 65°C to 127°C.
APPLICATION NOTE: Current only flows when the TRIP_SET pin is being monitored. At all other times, the internal
reference voltage is removed and the TRIP_SET pin will be pulled down to ground.
DS20005251A-page 24
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
APPLICATION NOTE: The TRIP_SET pin circuitry is designed to use a 1% resistor externally. Using a 1% resistor
will result in the Thermal / Critical Shutdown temperature being decoded correctly. If a 5%
resistor is used, then the Thermal / Critical Shutdown temperature may be decoded with as
much as ±1°C error.
Table 6.2 TRIP_SET Resistor Setting
TTRIP (°C)
RSET (1%)
TTRIP (°C)
RSET (1%)
65
0.0
97
1240
66
28.7
98
1330
67
48.7
99
1400
68
69.8
100
1500
69
90.9
101
1580
70
113
102
1690
71
137
103
1820
72
158
104
1960
73
182
105
2050
74
210
106
2210
75
237
107
2370
76
261
108
2550
77
294
109
2740
78
324.
110
2940
79
348
111
3160
80
383
112
3480
81
412
113
3740
82
453
114
4120
83
487
115
4530
84
523
116
4990
85
562
117
5490
86
604
118
6040
87
649
119
6810
88
698
120
7870
89
750
121
9090
90
787
122
10700
91
845
123
12700
92
909
124
15800
93
953
125
20500
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DS20005251A-page 25
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 6.2 TRIP_SET Resistor Setting (continued)
6.2
TTRIP (°C)
RSET (1%)
TTRIP (°C)
RSET (1%)
94
1020
126
29400
95
1100
127
49900
96
1150
65
Open
Fan Control Modes of Operation
The EMC2113 has four modes of operation for the fan driver. Each mode uses Ramp Rate control and
the Spin Up Routine.
1. PWM Setting Mode - in this mode of operation, the user directly controls the PWM duty cycle
setting. Updating the Fan Driver Setting Register (see Section 7.22, "Fan Setting Registers") will
instantly update the fan drive. The driver uses the Spin Up Routine and has user definable ramp
rate controls.
This is the default mode. The PWM Setting Mode is enabled by clearing both the EN_ALGO
bit in the Fan Configuration Register (see Section 7.24) and the LUT_LOCK bit in the Look
Up Table Configuration Register (see Section 7.34).
Whenever the PWM Setting Mode is enabled, the current drive will be changed to what was
last written into the Fan Driver Setting Register.
The Ramp Rate is controlled by the settings of the Max Step register (see Section 7.28) and
Update Period controls (Section 7.24) and must be enabled via the EN_RRC bit (see
Section 7.25).
2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a fan speed and
the drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin
Up Routine and has user definable ramp rate controls.
This mode is enabled by clearing the LUT_LOCK bit in the Look Up Table (LUT)
Configuration Register and setting the EN_ALGO bit in the Fan Configuration Register.
3. Using the Look Up Table with Fan Drive Settings (PWM Setting w/ LUT Mode) - In this mode of
operation, the user programs the Look Up Table with PWM duty cycle settings and corresponding
temperature thresholds. The fan drive is set based on the measured temperatures and the
corresponding drive settings. The fan driver uses the Spin Up Routine and has user definable ramp
rate controls.
This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit
while the EN_ALGO bit is set to ‘0’.
The RPM / PWM bit in the Look Up Table Configuration Register MUST be set to ‘1’ or the
PWM drive settings will be incorrectly set.
4. Using the Look Up Table with Fan Speed Control algorithm (FSC w/ LUT Mode)- In this mode of
operation, the user programs the Look Up Table with fan speed target values and corresponding
temperature thresholds. The TACH Target Register will be set based on the measured
temperatures and the corresponding target settings. The PWM drive settings will be determined
automatically based on the RPM-based Fan Speed Control Algorithm. PWM drive settings will be
determined automatically based on the RPM-based Fan Speed Control Algorithm
This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit
while the EN_ALGO bit is set to ‘1’.
The RPM / PWM bit in the Look Up Table Configuration Register MUST be set to ‘0’ or the
TACH Target values will be incorrectly set.
APPLICATION NOTE: It is important that the TACH Target settings are in the proper format when using the RPMbased Fan Speed Control Algorithm.
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Table 6.3 Fan Controls Active for Operating Mode
DIRECT PWM
SETTING MODE
FSC MODE
Fan Driver Setting (read
/ write)
Fan Driver Setting (read
only)
Fan Driver Setting (read only)
Fan Driver Setting (read
only)
EDGES[1:0]
EDGES[1:0]
(Fan Configuration)
EDGES[1:0]
EDGES[1:0]
-
RANGE[1:0]
(Fan Configuration)
-
RANGE[1:0]
(Fan Configuration)
UPDATE[2:0]
(Fan Configuration)
UPDATE[2:0]
(Fan Configuration)
UPDATE[2:0]
(Fan Configuration)
UPDATE[2:0]
(Fan Configuration)
LEVEL
(Spin Up Configuration)
LEVEL
(Spin Up Configuration)
LEVEL
(Spin Up Configuration)
LEVEL
(Spin Up Configuration)
SPINUP_TIME[1:0]
(Spin Up Configuration)
SPINUP_TIME[1:0]
(Spin Up Configuration)
SPINUP_TIME[1:0]
(Spin Up Configuration)
SPINUP_TIME[1:0]
(Spin Up Configuration)
Fan Max Step
Fan Max Step
Fan Max Step
Fan Max Step
-
Fan Minimum Drive
Valid TACH Count
Valid TACH Count
Valid TACH Count
Valid TACH Count
-
TACH Target (read /
write)
-
TACH Target (read only)
TACH Reading
TACH Reading
TACH Reading
TACH Reading
-
-
Look Up Table Drive /
Temperature Settings (read
only)
Look up Table Drive /
Temperature Settings
(read only)
-
DRIVE_FAIL_CNT [1:0]
(Spin Up Configuration) +
Fan Drive Fail Band
-
DRIVE_FAIL_CNT [1:0]
(Spin Up Configuration)
+ Fan Drive Fail Band
6.3
DIRECT PWM SETTING W/
LUT MODE
FSC W/ LUT MODE
Fan Minimum Drive
PWM Fan Driver
The EMC2113 supports a high or low frequency PWM driver. The output can be configured as either
push-pull or open drain and the frequency ranges from 9.5Hz to 26kHz in four programmable
frequency bands.
The PWM frequency range is coarsely adjusted via the PWM Base Frequency register (Section 7.19)
with a fine tune adjustment performed via the PWM Divider registers (see Section 7.23). General PWM
operation is governed by the PWM Configuration register (see Section 7.18).
6.4
Fan Control Look-Up Table
The EMC2113 uses a look-up table to apply a user-programmable fan control profile based on
measured temperature to the fan driver. In this look-up table, each temperature channel is allowed to
control the fan drive output independently (or jointly) by programming up to eight pairs of temperature
and drive setting entries.
The Look Up Table supports external data pushed into the device by the Host in either DTS or standard
format. Each of the four temperature channels used by the Look Up table is generated from measured
temperature sensors on the EMC2113 or from an external source.
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The user programs the look-up table based on the desired operation. If the RPM-based Fan Speed
Control Algorithm is to be used (see Section 6.6, "RPM-Based Fan Speed Control Algorithm (FSC)"),
then the user must program a fan speed target for each temperature setting of interest. Alternately, if
the RPM-based Fan Speed Control Algorithm is not to be used, then the user must program a PWM
setting for each temperature setting of interest.
If the measured temperature on the External Diode channel meets or exceeds any of the temperature
thresholds for any of the channels, the fan output will be automatically set to the desired setting
corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds
are exceeded, the highest fan drive setting will take precedence. Figure 6.3, "Fan Control Look-Up
Table Example" shows an example of this behavior using a single channel.
When the measured temperature drops to a point below a lower threshold minus the hysteresis value,
the fan output will be set to the corresponding lower set point.
To turn the fan off, there are 2 methods:
The first is to set the Temps1-4 Setting 1 values (+ hysteresis) above the temperatures desired for
the fan to turn off. When the temperatures fall below Temps1-4 (out of the LUT) by the hysteresis
amount, the fan drive will be set to 0.
The second is to set the Drive 1 value to 0% (or 0RPM) as well as the Temp 1-4 values to the
temperatures (+ hysteresis) at which the fan should turn off. This method will reduce the effective
amount of fan drive settings to 7.
Figure 6.3 Fan Control Look-Up Table Example
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6.4.1
Programming the Look Up Table
When the Look Up Table is used, it must be loaded and configured correctly based on the system
requirements. The following steps outline the procedure.
1. Determine whether the Look Up Table will drive a PWM duty cycle or a tachometer target value
and set the RPM / PWM bit in the Fan LUT Configuration Register (see Section 7.34, "Look Up
Table Configuration Register").
2. Determine which measurement channels (up to four) are to be used with the Look Up Table and
set the TEMP1_CFG, TEMP3_CFG and TEMP4_CFG bits accordingly in the Fan LUT
Configuration Register.
3. For each step to be used in the LUT, set the Fan Setting (either PWM or TACH Target as set by
the RPM / PWM bit). If a setting is not used, then set it to FFh (if a PWM) or 00h (if a TACH Target).
Load the lowest settings first in ascending order (i.e. Fan Setting 1 is the lowest setting greater
than “off”. Fan Setting 2 is the next highest setting, etc.). See Section 7.35, "Look Up Table
Registers".
4. For each step to be used in the LUT, set each of the measurement channel thresholds. These
values must be set in the same data format that the data is presented. If DTS is to be used, then
the format should be in temperature with a maximum threshold of 100°C (64h). If a measurement
channel is not used, then set the threshold at FFh.
5. Update the threshold hysteresis to be smaller than the smallest table step.
6. Configure the RPM-based Fan Speed Control Algorithm if it is to be used. See Section 7.24, "Fan
Configuration 1 Register" for more details.
7. Set the LUT_LOCK bit to enable the Look Up Table and begin fan control in the Fan LUT
Configuration Register.
6.4.2
DTS Support
The EMC2113 supports DTS (Intel’s Digital Temperature Sensor) data in the Fan Control Look Up
Table. Intel’s DTS data is a positive number that represents the processor’s relative temperature below
a fixed value called TCONTROL which is generally equal to 100°C for Intel Mobile processors. For
example, a DTS value of 10°C means that the actual processor temperature is 10°C below TCONTROL
or equal to 90°C.
Either or both of the Pushed Temperature Registers can be written with DTS data and used to control
the fan driver. When DTS data is entered, then the USE_DTS_Fx bit must be set in the Fan LUT
Configuration register. Once this bit is set, the DTS data entered is automatically subtracted from a
value of 100°C. This delta value is then used in the Look Up Table as standard temperature data.
APPLICATION NOTE: The device is designed with the assumption that TCONTROL is 100°C. As such, all DTS
related conversions are done based on this value including Look Up Table comparisons. If
TCONTROL is adjusted (i.e. TCONTROL is shifted to 105°C), then all of the Look Up Table
thresholds should be adjusted by a value equal to TCONTROL - 100°C.
6.5
PWM Input
The EMC2113 supports a PWM input that is used as an input to the fan speed control Look Up Table.
This is controlled by the PUSH1_CFG bit and either the TEMP1_CFG or TEMP3_CFG bits in the Look
Up Table Configuration register (see Section 7.34).
When a signal is driven into the PWM_IN pin, then the device will automatically calculate the duty cycle
of the input signal (provided that the frequency is within the specified range). This value is stored in
the PWM Input Duty Cycle register and may be used as an input to the Look Up Table.
APPLICATION NOTE: The PWM Input duty cycle value is a unit-less value that does not correspond to specific
temperature values. When used in the Fan Control LUT, It is compared against unit-less 7bit values that represent PWM duty cycle thresholds to control the desired fan speed.
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This functionality is always active. If the pin does not transition, then it will assume 100% duty cycle
or 0% duty cycle based on the pin voltage. The data range required by the Look Up Table is 0 to 127
so 100% duty cycle corresponds to 127 and 0% corresponds to 0.
The duty cycle measured on the PWM_IN pin is compared against a user programmed PWM High
Limit. If the measured duty cycle meets or exceeds this value, then it may cause the ALERT pin to be
asserted (default operation is to mask this event from asserting the ALERT pin).
6.6
RPM-Based Fan Speed Control Algorithm (FSC)
The EMC2113 includes an RPM-based Fan Speed Control Algorithm.
This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach
and maintain the system’s desired fan speed to an accuracy directly proportional to the accuracy of
the clock source.
The desired tachometer count is set by the user inputting the desired number of 32.768KHz cycles
that occur per fan revolution. This is done either manually or by programming the Temperature LookUp Table. The user may change the target count at any time. The user may also set the target count
to FFh in order to disable the fan driver for lower current operation.
For example, if a desired RPM rate for a 2-pole fan is 3000 RPM then the user would input the
hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number
of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution
when it is spinning at 3000RPMs.
The EMC2113’s RPM-based Fan Speed Control Algorithm has programmable configuration settings
for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects
and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT pin. The
EMC2113 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal.
6.6.1
Programming the RPM-Based Fan Speed Control Algorithm
The RPM-based Fan Speed Control Algorithm powers-up disabled. The following registers control the
algorithm. The EMC2113 fan control registers are pre-loaded with defaults that will work for a wide
variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control
registers can be used to fine-tune the algorithm behavior based on application requirements.
Note that steps 1 - 7 are optional and need only be performed if the default settings do not provide
the desired fan response.
1. Set the Valid TACH Count Register to maximum number of tach counts to indicate the fan is
spinning.
2. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired.
3. Set the Fan Step Register to the desired step size.
4. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation.
5. Set the Update Time and Edges options in the Fan Configuration Register.
6. Set the TACH Target Register to the desired tachometer count.
7. Enable the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit.
6.7
Tachometer Measurement
The tachometer measurement circuitry is used in conjunction with the RPM-based Fan Speed Control
Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a
diagnostic for host based fan control.
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The EMC2113 monitors the TACH signal in real time. It constantly updates the tachometer
measurement by reporting the number of clocks between a user programmed number of edges on the
TACH signal (see Table 7.34, "Minimum Edges for Fan Rotation").
Using the Tach Period Measurement method provides fast response times for the RPM-based Fan
Speed Control Algorithm and the data is presented as a count value that represents the fan RPM
period. When this method is used, all fan target values must be input as a count value for proper
operation.
APPLICATION NOTE: The Tach Period Measurement method works independently of the drive settings. If the
device is put into Direct Setting and the fan drive is set at a level that is lower than the fan
can operate (including zero drive), then the tachometer measurement may signal a Stalled
Fan condition and assert an interrupt.
6.7.1
Stalled Fan
A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting.
The EMC2113 will flag the fan as stalled and trigger an interrupt.
If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to
restart the fan until it detects a valid tachometer level or is disabled.
The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally
depending on the mode of operation.
6.7.2
When the Direct Setting Mode or Direct Setting with LUT Mode are enabled, the FAN_STALL
interrupt will be masked for the duration of the programmed Spin Up Time (see Table 7.44, "Spin
Time"). This is to allow the fan opportunity to reach a valid speed without generating unnecessary
interrupts.
In Direct Setting Mode or Direct Setting with LUT Mode, whenever the drive value is changed from
00h, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time to
allow the fan opportunity to reach a valid speed without generating unnecessary interrupts.
In Direct Setting Mode or Direct Setting w/ LUT Mode, and the tachometer measurement is using
the Tach Period Measurement method, then whenever the TACH Reading Register value exceeds
the Valid TACH Count Register setting, the FAN_STALL status bit will be set.
When using the RPM-based Fan Speed Control Algorithm (either FSC Mode or LUT with FSC
Mode), the stalled fan condition is checked whenever the Update Time is met and the fan drive
setting is updated. It is not a continuous check.
Aging Fan or Invalid Drive Detection
The EMC2113 contains circuitry that detects that the programmed fan speed can be reached by the
fan. If the target fan speed cannot be reached within a user defined band of tach counts at maximum
drive then the DRIVE_FAIL status bit is set and the ALERT pin is asserted. This is useful to detect
aging fan conditions (where the fan’s natural maximum speed degrades over time) or incorrect fan
speed settings.
6.8
Spin Up Routine
The EMC2113 also contains programmable circuitry to control the spin up behavior of the fan driver
to ensure proper fan operation. The Spin Up Routine is initiated under the following conditions when
the Tach Period Measurement method of tach measurement is used: This applies to both the RPMbased Fan Speed Control Algorithm mode, or Direct Setting mode (with or without the Look Up Table
- when enabled).
1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid
TACH Count (see Section 7.30, "Valid TACH Count Register").
2. The RPM-based Fan Speed Control Algorithm’s measured TACH Reading Register value is greater
than the Valid TACH Count setting.
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When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of
the total user defined spin up time. For the remaining spin up time, the fan driver output is set to a
user defined level (30% through 65% drive).
After the Spin Up Routine has finished, the EMC2113 measures the TACH signal. If the measured
TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN
status bit is set and the Spin Up Routine will automatically attempt to restart the fan.
Figure 6.4, "Spin Up Routine" shows an example of the Spin Up Routine in response to a programmed
fan speed change based on the first condition above.
Figure 6.4 Spin Up Routine
6.9
Ramp Rate Control
The PWM output drive can be configured with automatic ramp rate control. If the RPM-based Fan
Speed Control Algorithm is used, then this ramp rate control is automatically used based on the fan
control derivative option settings. The user programs a maximum step size for the PWM setting and
an update time. The update time varies from 100ms to 1.6s while the PWM maximum step can vary
from 1 PWM count to 31 PWM counts.
When a new PWM duty cycle value is entered (either directly, as a result of the FSC Algorithm
adjusting the output PWM to meet the programmed TACH Target value, or as a result of the ramp rate
control circuitry), the delta from the next PWM and the previous PWM is determined. If this delta is
greater than the maximum fan step settings, then the PWM is adjusted by the maximum fan step
settings.
The PWM duty cycle is adjusted (and the delta recalculated) every 100ms to 1.6s as determined by
the Update Time until the target PWM setting is reached. See Figure 6.5, "Ramp Rate Control".
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Datasheet
Figure 6.5 Ramp Rate Control
6.10
Watchdog Timer
The EMC2113 contains an internal Watchdog Timer for the fan driver. The Watchdog timer monitors
the SMBus traffic for signs of activity and works in two different modes based upon device operation.
These modes are Power Up Operation and Continuous Operation as described below.
For either mode of operation, if four (4) seconds elapse without activity detected by the host, then the
watchdog will be triggered and the following will occur:
1. The WATCH status bit will be set which will cause the ALERT pin to be asserted.
2. The fan driver will be set to full scale drive. It will remain at full scale drive until it is disabled.
APPLICATION NOTE: When the Watchdog timer is activated the Fan Speed Control Algorithm is automatically
disabled. Disabling the Watchdog will not automatically set the fan drive nor re-activate the
Fan Speed Control Algorithm. This must be done manually.
6.10.1
Power Up Operation
The Watchdog Timer only starts immediately after power-up and once it has been triggered or
deactivated will not restart although it can be configured to operate in Continuous operation.
In the Power Up Operation, the Watchdog Timer is disabled by any of the following actions:
1. Writing the Fan Setting Register will disable the Watchdog Timer.
2. Enabling the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the
Watchdog Timer. The fan driver will be set based on the RPM-based Fan Speed Control Algorithm.
3. Changing the Watchdog operating mode by setting the WD_EN bit.
Writing any other configuration registers will not disable the Watchdog Timer upon power up.
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6.10.2
Continuous Operation
When configured to operate in Continuous Operation, the Watchdog timer will start immediately. It can
be disabled by any access (read or write) to the SMBus register set. Upon completion of SMBus
activity, the Watchdog timer is reset and restarted.
6.11
Fault Queue
The EMC2113 contains a programmable fault queue on all fault conditions. The fault queue defines
how many consecutive out-of-limit conditions must be reported before the corresponding status bit is
set (and the ALERT pin asserted).
6.12
ALERT Pin
The ALERT pin acts as an active low open drain interrupt that flags several conditions. It will be
asserted low when:
1. The FSC Algorithm detects a stalled fan.
2. The measured temperature meets or exceeds its programmed high limit or drops below its
programmed low limit.
3. A diode fault is detected.
4. The PWM input duty cycle has exceeded its programmed limit.
Once asserted, the ALERT pin will remain asserted until the status bits have been cleared or the MASK
bit has been set.
6.13
Temperature Monitoring
The EMC2113 can monitor the temperature of up to three (3) externally connected diodes as well as
the internal or ambient temperature. Each channel is configured with Resistance Error Correction, BJT
Transistor model support, and Averaging enabled or disabled based on user settings and system
requirements. All temperature channels offer 1°C accuracy and 0.125°C resolution.
6.13.1
Dynamic Averaging
The EMC2113 supports dynamic averaging. When enabled, this feature changes the conversion time
for all channels based on the selected conversion rate. This essentially increases the averaging factor
as shown in Table 6.4, "Dynamic Averaging Behavior". The benefits of Dynamic Averaging are
improved noise rejection due to the longer integration time as well as less random variation on the
temperature measurement.
Table 6.4 Dynamic Averaging Behavior
AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSI0N)
CONVERSION RATE
DYNAMIC AVERAGING
ENABLED
DYNAMIC AVERAGING
DISABLED
1 / sec
8x
1x
2 / sec
4x
1x
4 / sec
2x
1x
Continuous
1x
1x
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6.13.2
Resistance Error Correction
The EMC2113 includes active Resistance Error Correction to remove the effect of up to 100 ohms of
series resistance. Without this automatic feature, voltage developed across the parasitic resistance in
the remote diode path causes the temperature to read higher than the true temperature is. The error
induced by parasitic resistance is approximately +0.7°C per ohm. Sources of parasitic resistance
include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU,
and resistance in the printed circuit board traces and package leads. Resistance error correction in the
EMC2113 eliminates the need to characterize and compensate for parasitic resistance in the remote
diode path.
6.13.3
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well,
it is not constant over changes in temperature. The variation in beta causes an error in temperature
reading that is proportional to absolute temperature. This correction is done by implementing the BJT
or transistor model for temperature measurement.
For discrete transistors configured with the collector and base shorted together, the beta is generally
sufficiently high such that the percent change in beta variation is very small. For example, a 10%
variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute
approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction
is used for temperature measurement and the collector is tied to the substrate, the proportional beta
variation will cause large error. For example, a 10% variation in beta for two forced emitter currents
with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.
The Beta Compensation circuitry in the EMC2113 corrects for this beta variation to eliminate any error
which would normally be induced. It automatically detects the appropriate beta setting to use.
6.13.4
Ideality Configuration
The EMC2113 is designed for external diodes with an ideality factor of 1.008. Not all external diodes,
processor or discrete, will have this exact value. This variation of the ideality factor introduces error in
the temperature measurement which must be corrected for. This correction is typically done using
programmable offset registers. Since an ideality factor mismatch introduces an error that is a function
of temperature, this correction is only accurate within a small range of temperatures. To provide
maximum flexibility to the user, the EMC2113 provides a register for each external diode where the
ideality factor of the diode used may be programmed to eliminate errors across all temperatures.
APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the
Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most
ideality errors.
6.13.5
Digital Averaging
The external diode channels support a 4x digital averaging filter. Every cycle, this filter updates the
temperature data based an a running average of the last 4 measured temperature values. The digital
averaging reduces temperature flickering and increases temperature measurement stability.
The digital averaging can be disabled by setting the DIS_AVG bit in the Configuration 2 Register (see
Section 7.25, "Fan Configuration 2 Register").
6.14
Diode Connections
The External Diode 1 channel can support a diode-connected transistor (such as a 2N3904) or a
substrate transistor requiring the BJT or transistor model (such as those found in a CPU or GPU) as
shown in Figure 6.6, "Diode Connections".
The External Diode 2 channel supports any diode connection shown or it can be configured to operate
in anti-parallel diode (APD) mode. When configured in APD mode, a third temperature channel is
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available that shares the DP2 and DN2 pins. When in this mode, both the external diode 2 channel
and external diode 3 channel thermal diodes must be connected as diodes.
Figure 6.6 Diode Connections
6.14.1
Anti-Parallel Diodes
The EMC2113 supports connecting two external diodes to the DN2 / DP3 and DP2 / DN3 pins. This
second diode is connected in an anti-parallel configuration with respect to the first diode. When the
the External Diode 2 channel is measured, the anti-parallel diode will be reverse biased. Likewise,
when the External Diode 3 channel is measured, the first diode will be reverse biased. CPU diodes
should not be used with anti-parallel diode connections.
6.14.2
Diode Faults
The EMC2113 actively detects an open and short condition on each measurement channel. When a
diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is
set in the Status Register. When the External Diode 2 channel is configured to operate in APD mode,
the circuitry will detect independent open fault conditions; however, a short condition will be shared
between the External Diode 2 and External Diode 3 channels.
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Datasheet
Chapter 7 Fan Control Register Set
7.1
Register Map
The following registers are accessible through the SMBus Interface. All register bits marked as ‘-’ will
always read ‘0’. A write to these bits will have no effect.
Table 7.1 EMC2113 Register Set
ADDR
R/W
REGISTER
NAME
DEFAULT
VALUE
LOCK
PAGE
Stores the integer data of the Internal
Diode
00h
No
Page 44
Stores the fractional data of the
Internal Diode
00h
No
Page 44
FUNCTION
Temperature Registers
00h
R
Internal Temp
Reading High
Byte
01h
R
Internal Temp
Reading Low Byte
02h
R
External Diode 1
Temp Reading
High Byte
Stores the integer data of External
Diode 1
00h
No
Page 44
03h
R
External Diode 1
Temp Reading
Low Byte
Stores the fractional data of External
Diode 1
00h
No
Page 44
04h
R
External Diode 2
Temp Reading
High Byte
Stores the integer data of External
Diode 2
00h
No
Page 44
05h
R
External Diode 2
Temp Reading
Low Byte
Stores the fractional data of External
Diode 2
00h
No
Page 44
06h
R
External Diode 3
Temp Reading
High Byte
Stores the integer data of External
Diode 3
00h
No
Page 44
07h
R
External Diode 3
Temp Reading
Low Byte
Stores the fractional data of External
Diode 3
00h
No
Page 44
0Ah
R
Critical/Thermal
Shutdown
Temperature
Stores the calculated Critical/Thermal
Shutdown temperature high limit
derived from TRIP_SET pin voltage
N/A
No
Page 45
0Ch
R/W
Pushed
Temperature 1
Stores the integer data for Pushed
Temperature 1 to drive the LUT
00h
No
Page 45
0Dh
R/W
Pushed
Temperature 2
Stores the integer data for Pushed
Temperature 2 to drive the LUT
00h
No
Page 45
0Fh
R
PWM Input Duty
Cycle
Stores the calculated duty cycle on
the PWM pin
00h
No
Page 46
10h
R
TRIP_SET
Voltage
Stores the measured voltage on the
TRIP_SET pin
FFh
No
Page 46
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Table 7.1 EMC2113 Register Set (continued)
ADDR
REGISTER
NAME
R/W
FUNCTION
DEFAULT
VALUE
LOCK
PAGE
Diode Configuration
11h
R/W
External Diode 1
Ideality Register
Stores the Ideality Factor used for
External Diode 1
12h
SWL
Page 46
12h
R/W
External Diode 2
Ideality Register
Stores the Ideality factor used for
External Diode 2
12h
SWL
Page 46
13h
R/W
External Diode 3
Ideality Register
Stores the Ideality factor used for
External Diode 3
12h
SWL
14h
R/W
External Diode 1
Beta Configuration
Configures the beta compensation
settings for External Diode 1
10h
SWL
Page 48
15h
R/W
External Diode 2
Beta Configuration
Configures the beta compensation
settings for External Diode 2
10h
SWL
Page 48
17h
R/W
External Diode
REC
Configuration
Configures the Resistance Error
Correction functionality for all
external diodes
07h
SWL
Page 49
Page 46
Critical Temperature Limit Registers
19h
R/W
once
External Diode 1
Tcrit Limit
Stores the critical temperature limit
for External Diode 1
64h
(100°C)
Write
Once
Page 50
1Ah
R/W
once
External Diode 2
Tcrit Limit
Stores the critical temperature limit
for External Diode 2
64h
(100°C)
Write
Once
Page 50
1Bh
R/W
once
External Diode 3
Tcrit Limit
Stores the critical temperature limit
for External Diode 3
64h
(100°C)
Write
Once
Page 50
1Dh
R/W
once
Internal Diode
Tcrit Limit
Stores the critical temperature limit
for the Internal Diode
64h
(100°C)
Write
Once
Page 50
Stores the status bits for all
temperature channel tcrit limits
00h
No
Page 53
Configuration and control
1Fh
R
Tcrit Status
20h
R/W
Configuration
Configures the Thermal / Critical
Shutdown masking options
00h
SWL
Page 50
21h
R/W
Configuration 2
Controls the conversion rate for
monitoring of all channels
0Eh
SWL
Page 51
23h
R
Interrupt Status
Stores the status bits for temperature
channels
00h
No
Page 53
24h
R-C
High Limit Status
Stores the status bits for all
temperature channel high limits
00h
No
Page 53
25h
R-C
Low Limit Status
Stores the status bits for all
temperature channel low limits
00h
No
Page 53
26h
R-C
Diode Fault
Stores the status bits for all
temperature channel diode faults
00h
No
Page 53
27h
R-C
Fan Status
Stores the status bits for the RPMbased Fan Speed Control Algorithm
00h
No
Page 54
28h
R/W
Interrupt Enable
Register
Controls the masking of interrupts on
all temperature channels
00h
No
Page 54
DS20005251A-page 38
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.1 EMC2113 Register Set (continued)
REGISTER
NAME
FUNCTION
R/W
Fan Interrupt
Enable Register
2Ah
R/W
PWM Driver
Config
2Bh
R/W
PWM Driver Base
Frequency
ADDR
R/W
29h
DEFAULT
VALUE
LOCK
PAGE
Controls the masking of interrupts for
the Fan Driver
00h
No
Page 55
Configures the PWM driver
00h
No
Page 56
Controls the base frequency of the
PWM driver
00h
No
Page 56
Temperature High Limit Registers
30h
R/W
External Diode 1
Temp High Limit
High limit for External Diode 1
55h
(+85°C)
SWL
Page 57
31h
R/W
External Diode 2
Temp High Limit
High limit for External Diode 2
55h
(+85°C)
SWL
Page 57
32h
R/W
External Diode 3
Temp High Limit
High limit for External Diode 3
55h
(+85°C)
SWL
Page 57
34h
R/W
Internal Diode
High Limit
High Limit for Internal Diode
55h
(85°C)
SWL
Page 57
Temperature Low Limit Registers
38h
R/W
External Diode 1
Temp Low Limit
Low Limit for External Diode 1
00h
(0°C)
SWL
Page 57
39h
R/W
External Diode 2
Temp Low Limit
Low Limit for External Diode 2
00h
(0°C)
SWL
Page 57
3Ah
R/W
External Diode 3
Temp Low Limit
Low Limit for External Diode 3
00h
(0°C)
SWL
Page 57
3Ch
R/W
Internal Diode
Low Limit
Low Limit for Internal Diode
00h
(0°C)
SWL
Page 57
7Fh
SWL
Page 57
PWM Input Duty Cycle Limit
3Dh
R/W
PWM Input Duty
Cycle High Limit
Stores the high limit for the PWM
input Duty Cycle
Fan Control Registers
40h
R/W
Fan Setting
Always displays the most recent fan
driver input setting for Fan. If the
RPM-based Fan Speed Control
Algorithm is disabled, allows direct
user control of the fan driver.
00h
No
Page 58
41h
R/W
PWM Divide
Stores the divide ratio to set the
frequency for the Fan
01h
No
Page 58
42h
R/W
Fan Configuration
1
Sets configuration values for the
RPM-based Fan Speed Control
Algorithm for the Fan
2Bh
No
Page 58
43h
R/W
Fan Configuration
2
Sets additional configuration values
for the Fan driver
28h
SWL
Page 60
45h
R/W
Gain
Holds the gain terms used by the
RPM-based Fan Speed Control
Algorithm for the Fan
2Ah
SWL
Page 62
2013 Microchip Technology Inc.
DS20005251A-page 39
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.1 EMC2113 Register Set (continued)
REGISTER
NAME
FUNCTION
R/W
Fan Spin Up
Configuration
47h
R/W
Fan Step
48h
R/W
Fan Minimum
Drive
49h
R/W
Fan Valid TACH
Count
4Ah
R/W
Fan Drive Fail
Band Low Byte
4Bh
R/W
Fan Drive Fail
Band High Byte
4Ch
R/W
TACH Target Low
Byte
4Dh
R/W
TACH Target High
Byte
4Eh
R
4Fh
R
ADDR
R/W
46h
DEFAULT
VALUE
LOCK
PAGE
Sets the configuration values for Spin
Up Routine of the Fan driver
19h
SWL
Page 62
Sets the maximum change per
update for the Fan
10h
SWL
Page 64
66h
(40%)
SWL
Page 64
Holds the minimum tachometer
reading that indicates the fan is
spinning properly
F5h
SWL
Page 65
Stores the number of Tach counts
used to determine how the actual fan
speed must match the target fan
speed at full scale drive
00h
SWL
Page 65
00h
SWL
Holds the target tachometer reading
low byte for the Fan
F8h
No
Page 66
Holds the target tachometer reading
high byte for the Fan
FFh
No
Page 66
TACH Reading
High Byte
Holds the tachometer reading high
byte for the Fan
FFh
No
Page 66
TACH Reading
Low Byte
Holds the tachometer reading low
byte for the Fan
F8h
No
Page 66
Sets the minimum drive value for the
the Fan driver
Look Up Table (LUT)
50h
R/W
LUT Configuration
Stores and controls the configuration
for the LUT
00h
No
Page 67
51h
R/W
LUT Drive 1
Stores the lowest programmed drive
setting for the LUT
FBh
LUT
Lock
Page 68
52h
R/W
LUT Temp 1
Setting 1
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 1 value
7Fh
(127°C)
LUT
Lock
Page 68
53h
R/W
LUT Temp 2
Setting 1
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 1 value
7Fh
(127°C)
LUT
Lock
Page 68
54h
R/W
LUT Temp 3
Setting 1
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 1 value
7Fh
(127°C)
LUT
Lock
Page 68
55h
R/W
LUT Temp 4
Setting 1
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 1 value
7Fh
(127°C)
LUT
Lock
Page 68
56h
R/W
LUT Drive 2
Stores the second programmed drive
setting for the LUT
E6h
LUT
Lock
Page 68
57h
R/W
LUT Temp 1
Setting 2
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 2 value
7Fh
(127°C)
LUT
Lock
Page 68
DS20005251A-page 40
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.1 EMC2113 Register Set (continued)
REGISTER
NAME
DEFAULT
VALUE
LOCK
PAGE
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 2 value
7Fh
(127°C)
LUT
Lock
Page 68
LUT Temp 3
Setting 2
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 2 value
7Fh
(127°C)
LUT
Lock
Page 68
R/W
LUT Temp 4
Setting 2
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 2 value
7Fh
(127°C)
LUT
Lock
Page 68
5Bh
R/W
LUT Drive 3
Stores the third programmed drive
setting for the LUT
D1h
LUT
Lock
Page 68
5Ch
R/W
LUT Temp 1
Setting 3
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 3 value
7Fh
(127°C)
LUT
Lock
Page 68
5Dh
R/W
LUT Temp 2
Setting 3
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 3 value
7Fh
(127°C)
LUT
Lock
Page 68
5Eh
R/W
LUT Temp 3
Setting 3
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 3 value
7Fh
(127°C)
LUT
Lock
Page 68
5Fh
R/W
LUT Temp 4
Setting 3
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 3 value
7Fh
(127°C)
LUT
Lock
Page 68
60h
R/W
LUT Drive 4
Stores the fourth programmed drive
setting for the LUT
BCh
LUT
Lock
Page 68
61h
R/W
LUT Temp 1
Setting 4
Stores the threshold level for the
External Diode 1channel that is
associated with the Drive 4 value
7Fh
(127°C)
LUT
Lock
Page 68
62h
R/W
LUT Temp 2
Setting 4
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 4 value
7Fh
(127°C)
LUT
Lock
Page 68
63h
R/W
LUT Temp 3
Setting 4
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 4 value
7Fh
(127°C)
LUT
Lock
Page 68
64h
R/W
LUT Temp 4
Setting 4
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 4 value
7Fh
(127°C)
LUT
Lock
Page 68
65h
R/W
LUT Drive 5
Stores the fifth programmed drive
setting for the LUT
A7h
LUT
Lock
Page 68
66h
R/W
LUT Temp 1
Setting 5
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 5 value
7Fh
(127°C)
LUT
Lock
Page 68
ADDR
R/W
58h
R/W
LUT Temp 2
Setting 2
59h
R/W
5Ah
2013 Microchip Technology Inc.
FUNCTION
DS20005251A-page 41
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.1 EMC2113 Register Set (continued)
REGISTER
NAME
DEFAULT
VALUE
LOCK
PAGE
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 5 value
7Fh
(127°C)
LUT
Lock
Page 68
LUT Temp 3
Setting 5
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 5 value
7Fh
(127°C)
LUT
Lock
Page 68
R/W
LUT Temp 4
Setting 5
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 5 value
7Fh
(127°C)
LUT
Lock
Page 68
6Ah
R/W
LUT Drive 6
Stores the sixth programmed drive
setting for the LUT
92h
LUT
Lock
Page 68
6Bh
R/W
LUT Temp 1
Setting 6
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 6 value
7Fh
(127°C)
LUT
Lock
Page 68
6Ch
R/W
LUT Temp 2
Setting 6
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 6 value
7Fh
(127°C)
LUT
Lock
Page 68
6Dh
R/W
LUT Temp 3
Setting 6
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 6 value
7Fh
(127°C)
LUT
Lock
Page 68
6Eh
R/W
LUT Temp 4
Setting 6
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 6 value
7Fh
(127°C)
LUT
Lock
Page 68
6Fh
R/W
LUT Drive 7
Stores the seventh programmed drive
setting for the LUT
92h
LUT
Lock
Page 68
70h
R/W
LUT Temp 1
Setting 7
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 7 value
7Fh
(127°C)
LUT
Lock
Page 68
71h
R/W
LUT Temp 2
Setting 7
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 7 value
7Fh
(127°C)
LUT
Lock
Page 68
72h
R/W
LUT Temp 3
Setting 7
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 7 value
7Fh
(127°C)
LUT
Lock
Page 68
73h
R/W
LUT Temp 4
Setting 7
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 7 value
7Fh
(127°C)
LUT
Lock
Page 68
74h
R/W
LUT Drive 8
Stores the highest programmed drive
setting for the LUT
92h
LUT
Lock
Page 68
75h
R/W
LUT Temp 1
Setting 8
Stores the threshold level for the
External Diode 1 channel that is
associated with the Drive 8 value
7Fh
(127°C)
LUT
Lock
Page 68
ADDR
R/W
67h
R/W
LUT Temp 2
Setting 5
68h
R/W
69h
DS20005251A-page 42
FUNCTION
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.1 EMC2113 Register Set (continued)
REGISTER
NAME
DEFAULT
VALUE
LOCK
PAGE
Stores the threshold level for the
External Diode 2 channel that is
associated with the Drive 8 value
7Fh
(127°C)
LUT
Lock
Page 68
LUT Temp 3
Setting 8
Stores the threshold level for the
External Diode 3 channel (or Pushed
Temp 1 temp) that is associated with
the Drive 8 value
7Fh
(127°C)
LUT
Lock
Page 68
R/W
LUT Temp 4
Setting 8
Stores the threshold level for the
Internal Diode channel (or Pushed
Temp 2 temp) that is associated with
the Drive 8 value
7Fh
(127°C)
LUT
Lock
Page 68
79h
R/W
LUT Temp 1
Hysteresis
Stores the hysteresis that is used in
the LUT for the Temp 1 Settings
0Ah
(10°C)
LUT
Lock
Page 68
7Ah
R/W
LUT Temp 2
Hysteresis
Stores the hysteresis that is used in
the LUT for the Temp 2 Settings
0Ah
(10°C)
LUT
Lock
Page 68
7Bh
R/W
LUT Temp 3
Hysteresis
Stores the hysteresis that is used in
the LUT for the Temp 3 Settings
0Ah
(10°C)
LUT
Lock
Page 68
7Ch
R/W
LUT Temp 4
Hysteresis
Stores the hysteresis that is used in
the LUT for the Temp 4 Settings
0Ah
(10°C)
LUT
Lock
Page 68
7Dh
R/W
LUT Configuration
Stores and controls the configuration
for the LUT
00h
No
Page 67
00h
SWL
Page 70
Indicates which pin selected options
are enabled
00h
No
Page 70
Stores the unique Product ID
2Eh
No
Page 71
Manufacturer ID
5Dh
No
Page 72
Revision
81h
No
Page 72
ADDR
R/W
76h
R/W
LUT Temp 2
Setting 8
77h
R/W
78h
FUNCTION
Lock Register
EFh
R/W
Software Lock
Locks all SWL registers
Revision Registers
FCh
R
Product Features
FDh
R
Product ID
FEh
R
Manufacturer ID
FFh
R
Revision
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when
power is first applied to the part and the voltage on the VDD supply surpasses the POR level as
specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to
undefined registers will not have an effect.
7.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL
registers are Software Locked and therefore made read-only when the LOCK bit is set.
2013 Microchip Technology Inc.
DS20005251A-page 43
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.2
Temperature Data Registers
Table 7.2 Temperature Data Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
00h
R
Internal Diode
High Byte
Sign
64
32
16
8
4
2
1
00h
01h
R
Internal Diode
Low Byte
0.5
0.25
0.125
-
-
-
-
-
00h
64
32
16
8
4
2
1
00h
R
External
Diode 1 High
Byte
Sign
02h
0.25
0.125
-
-
-
-
-
00h
R
External
Diode 1 Low
Byte
0.5
03h
64
32
16
8
4
2
1
00h
R
External
Diode 2 High
Byte
Sign
04h
0.25
0.125
-
-
-
-
-
00h
R
External
Diode 2 Low
Byte
0.5
05h
64
32
16
8
4
2
1
00h
R
External
Diode 3 High
Byte
Sign
06h
0.25
0.125
-
-
-
-
-
00h
R
External
Diode 3 Low
Byte
0.5
07h
The temperature measurement range is from -64°C to +127.875°C. The data format is a signed two’s
complement number as shown in Table 7.3, "Temperature Data Format".
Table 7.3 Temperature Data Format
TEMPERATURE (°C)
BINARY
HEX (AS READ BY
REGISTERS)
Diode Fault
1000_0000_000b
80_00h
-63.875
1100_0000_001b
C0_20h
-63
1100_0001_000b
C1_00h
-1
1111_1111_000b
FF_00h
-0.125
1111_1111_111b
FF_E0h
0
0000_0000_000b
00_00h
0.125
0000_0000_001b
00_20h
1
0000_0001_000b
01_00h
63
0011_1111_000b
3F_00h
64
0100_0000_000b
40_00h
DS20005251A-page 44
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.3 Temperature Data Format (continued)
7.3
TEMPERATURE (°C)
BINARY
HEX (AS READ BY
REGISTERS)
65
0100_0001_000b
41_00h
127
0111_1111_000b
7F_00h
127.875
0111_1111_111b
7F_E0h
Critical/Thermal Shutdown Temperature Register
Table 7.4 Critical/Thermal Shutdown Temperature Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0Ah
R
Critical/Thermal
Shutdown
Temperature
128
64
32
16
8
4
2
1
7Fh
(+127°C)
The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage
Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents
of the register reflect the calculated temperature determined by the voltage on the TRIP_SET pin (see
Section 6.1.2, "SHDN_SEL Pin").
The data format is shown in Table 7.5, "Critical/Thermal Shutdown Data Format".
Table 7.5 Critical/Thermal Shutdown Data Format
7.4
TEMPERATURE (°C)
BINARY
HEX
0
0000_0000b
00h
1
0000_0001b
01h
63
0011_1111b
3Fh
64
0100_0000b
40h
65
0100_0001b
41h
127
0111_1111b
7Fh
Pushed Temperature Registers
Table 7.6 Pushed Temperature Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0Ch
R/W
Pushed / Polled
Temperature 1
Sign
64
32
16
8
4
2
1
00h
0Dh
R/W
Pushed / Polled
Temperature 2
Sign
64
32
16
8
4
2
1
00h
2013 Microchip Technology Inc.
DS20005251A-page 45
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
The Pushed Temperature Registers store user programmed temperature values or temperature values
polled from one or more slave devices. This temperature can be used by the look-up table to update
the fan control algorithm.
Data written in these registers is not compared against any limits and must match the data format
shown in Table 7.3, "Temperature Data Format".
7.5
PWM Input Duty Cycle Register
Table 7.7 PWM Duty Cycle Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
0Fh
R
PWM Input
Duty Cycle
-
64
32
16
8
4
2
1
00h
The PWM Input Duty Cycle register stores the calculated duty cycle of the signal on the PWM_IN pin.
The value is stored as an 7-bit PWM setting ranging from 0 to 127 and represents the duty cycle as
shown in Equation [1]. When used by the Fan Control Look Up Table (LUT), the 7-bit PWM Input Duty
Cycle register setting is used as a temperature input and compared against the programmed
thresholds.
VALUE
PWM Duty Cycle = --------------------- 100%
128
7.6
[1]
TRIP_SET Voltage Register
Table 7.8 TRIP_SET Voltage Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
10h
R
TRIP_SET
Voltage
750.0
375.0
187.5
93.75
46.88
23.43
11.72
5.86
FFh
The TRIP_SET Voltage Register stores data that is measured on the TRIP_SET Voltage input. Each
bit weight represents mV of resolution so that the final voltage can be determined by adding the
weighting of the set bits together.
7.7
Ideality Factor Registers
Table 7.9 Ideality Factor Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
11h
R/W
External Diode
1 Ideality
0
0
0
1
0
B2
B1
B0
12h
12h
R/W
External Diode
2 Ideality
0
0
0
1
0
B2
B1
B0
12h
13h
R/W
External Diode
3 Ideality
0
0
0
1
0
B2
B1
B0
12h
DS20005251A-page 46
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
These registers store the ideality factors that are applied to the external diodes.
Beta Compensation and Resistance Error Correction automatically correct for most diode ideality
errors, therefore it is not recommended that these settings be updated without consulting Microchip.
For CPU substrate transistors that require the BJT transistor model, the ideality factor behaves slightly
differently than for discrete diode-connected transistors. Refer to Table 7.11, "Substrate Diode Ideality
Factor Look-Up Table (BJT Model)" when using a CPU substrate transistor.
Only the lower three bits can be written. Writing to any other bit will be ignored.
The Ideality Factor Registers are software locked.
Table 7.10 Ideality Factor Look-Up Table
SETTING
FACTOR
10h
1.0053
11h
1.0066
12h
1.0080
13h
1.0093
14h
1.0106
15h
1.0119
16h
1.0133
17h
1.0146
Table 7.11 Substrate Diode Ideality Factor Look-Up Table (BJT Model)
SETTING
FACTOR
10h
0.9973
11h
0.9986
12h
1.0000
13h
1.0013
14h
1.0026
15h
1.0039
16h
1.0053
17h
1.0066
APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When
measuring 45nm Intel CPUs, the Ideality Setting should be 15h.
2013 Microchip Technology Inc.
DS20005251A-page 47
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.8
Beta Configuration Register
Table 7.12 Beta Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
14h
R/W
External Diode 1
Beta
Configuration
-
-
-
AUT
O1
-
BETA1[2:0]
10h
15h
R/W
External Diode 2
Beta
Configuration
-
-
-
AUT
O2
-
BETA2[2:0]
10h
The Beta Configuration Register controls advanced temperature measurement features of the External
Diode channels.
If External Diode 1 is selected as the hardware shutdown measurement channel (see Section 6.1,
"Critical/Thermal Shutdown") then the External Diode 1 Beta register will be read only. If the internal
diode is selected, then this register can be written normally. Likewise, if the External Diode 2 channel
is selected then this register can be written normally. Finally, if External Diode 2 is selected as the
hardware shutdown measurement channel, then the External Diode 2 Beta Configuration Register will
be read only.
The External Diode 3 channel beta configuration will always be set at 07h (disabled / diode mode).
Writing to a read only register will have no affect. The data will be ignored.
Bit 4 - AUTOx - Enables the Automatic Beta detection algorithm for the External Diode X channel.
‘0’ - The Automatic Beta detection algorithm is disabled. The BETAx[2:0] bit settings will be used
to control the beta compensation circuitry.
‘1’ (default) - The Automatic Beta detection algorithm is enabled. The circuitry will automatically
detect the transistor type and beta values and configure the BETAx[2:0] bits for optimal
performance.
Bits 2 - 0 - BETAx[2:0] - hold a value that corresponds to a range of betas that the Beta Compensation
circuitry can compensate for. These three bits will always show the current beta setting used by the
circuitry. If the AUTO bit is set (default), then these bits may be overwritten with every temperature
conversion. If the AUTO bit is not set, then the value of these bits is used to drive the beta
compensation circuitry. In this case, these bits should be set with a value corresponding to the lowest
expected value of beta for the PNP transistor being used as a temperature sensing device.
See Table 7.13, "Beta Compensation Look Up Table" for supported beta ranges. A value of 111b
indicates that the beta compensation circuitry is disabled. In this condition, the diode channels will
function with default current levels and will not automatically adjust for beta variation. This mode is
used when measuring a discrete 2N3904 transistor or AMD thermal diode.
The Beta Configuration Registers are Software Locked.
Table 7.13 Beta Compensation Look Up Table
BETAX[2:0]
2
1
0
MINIMUM BETA
0
0
0
< 0.08
0
0
1
< 0.111
DS20005251A-page 48
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.13 Beta Compensation Look Up Table (continued)
BETAX[2:0]
7.9
2
1
0
MINIMUM BETA
0
1
0
< 0.176
0
1
1
< 0.29
1
0
0
< 0.48
1
0
1
< 0.9
1
1
0
< 2.33
1
1
1
Disabled
REC Configuration Register
Table 7.14 REC Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
17h
R/W
REC
Configuration
-
-
-
-
-
REC3
REC2
REC1
07h
The REC Configuration Register determines whether Resistance Error Correction is used for each
external diode channel.
Bit 2 - REC3 - Controls the Resistance Error Correction functionality of External Diode 3
‘0’ - the REC functionality for External Diode 3 is disabled
‘1’ (default) - the REC functionality for External Diode 3 is enabled.
Bit 1 - REC2 - Controls the Resistance Error Correction functionality of External Diode 2.
‘0’ - the REC functionality for External Diode 2 is disabled
‘1’ (default) - the REC functionality for External Diode 2 is enabled.
Bit 0 - REC1 - Indicates the Resistance Error Correction functionality of External Diode 1. If External
Diode 1 is selected as the hardware shutdown channel then this bit is read only.
‘0’ - the REC functionality for External Diode 1 is disabled
‘1’ (default) - the REC functionality for External Diode 1 is enabled.
The REC Configuration Register is software locked.
2013 Microchip Technology Inc.
DS20005251A-page 49
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.10
Critical Temperature Limit Registers
Table 7.15 Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
19h
R/W
once
External Diode
1 Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
1Ah
R/W
once
External Diode
2 Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
1Bh
R/W
once
External Diode
3 Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
1Dh
R/W
once
Internal Diode
Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(+100°C)
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown
circuitry.
Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel meets or exceeds the critical limit, the SYS_SHDN pin will be asserted,
the appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register
will be set.
7.11
Configuration Register
Table 7.16 Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
20h
R/W
Configuration
MASK
WD_EN
-
-
SYS3
SYS2
SYS1
APD
00h
The Configuration Register controls the basic functionality of the EMC2113. The bits are described
below.
Bit 7 - MASK - Blocks the ALERT pin from being asserted.
‘0’ (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pin
will be asserted (unless individually masked via the Mask Register)
‘1’ - The ALERT pin is masked and will not be asserted.
Bit 6 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode.
‘0’ (default) - The Watchdog timer does not operate continuously. It will function upon power up and
at no other time.
‘1’ - The Watchdog timer operates continuously as described in Section 6.10.2, "Continuous
Operation".
Bit 3 - SYS3 - Enables the high temperature limit for the External Diode 3 channel to trigger the
Critical/Thermal Shutdown circuitry (see Section 6.1, "Critical/Thermal Shutdown").
‘0’ (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN pin. If the
temperature meets or exceeds the limit, the ALERT pin will be asserted normally.
DS20005251A-page 50
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
‘1’ - the External Diode 3 channel high limit will be linked to the SYS_SHDN pin. If the temperature
meets or exceeds the limit then the SYS_SHDN pin will be asserted. The SYS_SHDN pin will be
released when the temperature drops below the high limit. The ALERT pin will be asserted
normally.
Bit 2 - SYS2 - Enables the high temperature limit for the External Diode 2 channel to trigger the
Critical/Thermal Shutdown circuitry (see Section 6.1).
‘0’ (default) - the External Diode 2 channel high limit will not be linked to the SYS_SHDN pin. If the
temperature meets or exceeds the limit, the ALERT pin will be asserted normally.
‘1’ - the External Diode 2 channel high limit will be linked to the SYS_SHDN pin. If the temperature
meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be
asserted normally.
Bit 1 - SYS1 - Enables the high temperature limit for the External Diode 1 channel to trigger the
Critical/Thermal Shutdown circuitry (see Section 6.1).
‘0’ (default) - The External Diode 1 channel high limit will not be linked to the SYS_SHDN pin. If
the temperature meets or exceeds the limit, the ALERT pin will be asserted normally.
‘1’ - The External Diode 1 channel high limit will be linked to the SYS_SHDN pin. If the temperature
meets or exceeds the limit then the SYS_SHDN pin will be asserted. The ALERT pin will be
asserted normally.
Bit 0 - APD - This bit enables the Anti-parallel diode functionality on the External Diode 3 pins (DP3
and DN3).
‘0’ (default) - The Anti-parallel diode functionality is disabled. The External Diode 2 channel can be
configured for any type of diode
‘1’ - The Anti-parallel diode functionality is enabled. Both the External Diode 2 and 3 channels are
configured to support a diode or diode connected transistor (such as a 2N3904).
APPLICATION NOTE: When the APD diode is enabled, there will be a delay of a full temperature update before
any comparisons and functionality associated with the External Diode 3 channel will be
implemented. This includes the SYS3 bit operation, limit comparisons, and look up table
comparisons.
The Configuration Register is software locked.
7.12
Configuration 2 Register
Table 7.17 Configuration 2 Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
21h
R/W
Config 2
-
DIS_
DYN
DIS_
TO
DIS_
AVG
B3
B2
QUEUE[1:0]
B1
B0
CONV[1:0]
DEFAULT
0Eh
The Configuration 2 Register controls conversion rate of the temperature monitoring as well as the
fault queue.
Bit 6 - DIS_DYN - Disables the Dynamic Averaging Feature.
‘0’ (default) - The Dynamic Averaging function is enabled. The conversion time for all temperature
channels is scaled based on the chosen conversion rate to maximize accuracy and immunity to
random temperature measurement variation.
‘1’ - The Dynamic Averaging function is disabled. The conversion time for all temperature channels
is fixed regardless of the chosen conversion rate.
2013 Microchip Technology Inc.
DS20005251A-page 51
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Bit 5 - DIS_TO - Disables the SMBus timeout function.
‘0’ (default) - The SMBus timeout function is enabled.
‘1’ - The SMBus timeout function is disabled allowing the device to be fully I2C compliant.
Bit 4 - DIS_AVG - Disables digital averaging of the External Diode channels.
‘0’ (default) - The External Diode channels have digital averaging enabled. The temperature data
is the average of the previous four measurements.
‘1’ - The External Diode channels have digital averaging disabled. The temperature data is the last
measured data.
Bits 3-2 - QUEUE[1:0] - Determines the number of consecutive out of limit conditions that are
necessary to trigger an interrupt. Each measurement channel has a separate fault queue associated
with the high limit, low limit, and diode fault condition.
APPLICATION NOTE: If the fault queue for any channel is currently active (i.e. an out of limit condition has been
detected and caused the fault queue to increment) then changing the settings will not take
effect until the fault queue is zeroed. This occurs by the ALERT pin asserting or the out of
limit condition being removed.
Table 7.18 Fault Queue
QUEUE[1:0]
1
0
NUMBER OF CONSECUTIVE OUT OF LIMIT CONDITIONS
0
0
1 (disabled)
0
1
2
1
0
3
1
1
4 (default)
Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion
rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the
conversion rate and the average current will increase as the conversion rate increases.
Table 7.19 Conversion Rate
CONV[1:0]
1
0
CONVERSION RATE
0
0
1 / sec
0
1
2 / sec
1
0
4 / sec (default)
1
1
Continuous
The Configuration 2 Register is software locked.
DS20005251A-page 52
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.13
Interrupt Status Register
Table 7.20 Interrupt Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
23h
R
Interrupt
Status
Register
PWM
-
TCRIT
-
FAN
HIGH
LOW
FAULT
00h
The Interrupt Status Register reports the operating condition of the EMC2113. If any of the bits are set
to a logic ‘1’ (other than TCRIT) then the ALERT pin will be asserted low if the corresponding channel
is enabled. Reading from the status register clears the PWM bit. The other bits are cleared
automatically when the corresponding register is read. If there are no set status bits, then the ALERT
pin will be released.
The bits that cause the ALERT pin to be asserted can be masked based on the channel they are
associated with unless stated otherwise.
Bit 7 - PWM - This bit indicates that the PWM input duty cycle (on the PWM pin) meets or exceeds
the high limit. This bit is cleared when the register is read.
Bit 5 - TCRIT - This bit is set to ‘1’ if any bit in the Tcrit Status Register is set. This bit is automatically
cleared when the Tcrit Status Register is read and the bits are cleared.
Bit 3 - FAN - This bit is set to ‘1’ if any bit in the Fan Status Register is set. This bit is automatically
cleared when the Fan Status Register is read and the bits are cleared.
Bit 2 - HIGH - This bit is set to ‘1’ if any bit in the High Status Register is set. This bit is automatically
cleared when the High Status Register is read and the bits are cleared.
Bit 1- LOW - This bit is set to ‘1’ if any bit in the Low Status Register is set. This bit is automatically
cleared when the Low Status Register is read and the bits are cleared.
Bit 0 - FAULT - This bit is set to ‘1’ if any bit in the Diode Fault Register is set. This bit is automatically
cleared when the Diode Fault Register is read and the bits are cleared.
7.14
Error Status Registers
Table 7.21 Error Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Fh
R-C
Tcrit Status
HWS
-
-
-
EXT3_
TCRIT
EXT2_
TCRIT
EXT1_
TCRIT
INT_
TCRIT
00h
24h
R-C
High Status
-
-
-
-
EXT3_
HI
EXT2_
HI
EXT1_
HI
INT_HI
00h
25h
R-C
Low Status
-
-
-
-
EXT3_
LO
EXT2_
LO
EXT1_
LO
INT_LO
00h
26h
R-C
Diode Fault
-
-
-
-
EXT3_
FLT
EXT2_
FLT
EXT1_
FLT
-
00h
The Error Status Registers report the specific error condition for all measurement channels with limits.
If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault
bit is set in the Interrupt Status Register.
2013 Microchip Technology Inc.
DS20005251A-page 53
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status
Register that has bits set will clear the register and the corresponding bit in the Interrupt Status
Register if the error condition has been removed. If the error condition is persistent, reading the Error
Status Registers will have no effect.
7.14.1
Tcrit Status Register
The Tcrit Status Register stores which software enabled temperature channel has caused the
SYS_SHDN pin to be asserted. Each of the temperature channels must be associated with the
SYS_SHDN pin before they can be set (see Section 7.10, "Critical Temperature Limit Registers"). Once
the SYS_SHDN pin is asserted, it will be released when the temperature drops below the threshold
level; however, the individual status bit will not be cleared until read.
Bit 7 - HWS - This bit is set if the hardware set temperature channel caused the SYS_SHDN pin to
be asserted.
7.15
Fan Status Register
Table 7.22 Fan Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
27h
R-C
Fan Status
Register
WATCH
-
DRIVE_
FAIL
-
-
-
FAN_
SPIN
FAN_
STALL
00h
The Fan Status Register contains the status bits associated with each fan driver.
Bit 7 - WATCH - This bit is asserted ‘1’ if the Watchdog timer has expired (see Section 6.10, "Watchdog
Timer").
Bit 5 - DRIVE_FAIL - Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan
to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT pin.
‘0’ - The RPM-based Fan Speed Control Algorithm can drive Fan to the desired target setting.
‘1’ - The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target setting
at maximum drive.
Bit 1- FAN_SPIN - This bit is asserted ‘1’ if the Spin up Routine for the Fan cannot detect a valid
tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT
pin.
Bit 0 - FAN_STALL - This bit is asserted ‘1’ if the tachometer measurement on the Fan detects a stalled
fan. This bit can be masked from asserting the ALERT pin.
7.16
Interrupt Enable Register
Table 7.23 Interrupt Enable Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
28h
R/W
Interrupt
Enable
PWM_
INT_
EN
-
-
-
EXT3_
INT_
EN
EXT2_
INT_
EN
EXT1_
INT_
EN
INT_
INT_
EN
00h
The Interrupt Enable Register controls the masking for each temperature channel. When a channel is
masked, it will not cause the ALERT pin to be asserted when an error condition is detected.
DS20005251A-page 54
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Bit 7 - PWM_INT_EN - Allows the PWM input to assert the ALERT pin.
‘0’ (default) - The ALERT pin will not be asserted if the PWM input duty cycle meets or exceeds
its high limit.
‘1’ - The ALERT pin will be asserted if the PWM input duty cycle meets or exceeds its high limit.
Bit 3 - EXT3_INT_EN - Allows the External Diode 3 to assert the ALERT pin.
‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with External
Diode 3 channel.
‘1’ - The ALERT pin will be asserted for an error condition associated with External Diode 3
channel.
Bit 2 - EXT2_INT_EN - Allows the External Diode 2 to assert the ALERT pin.
‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with External
Diode 2 channel.
‘1’ - The ALERT pin will be asserted for an error condition associated with External Diode 2
channel.
Bit 1 - EXT1_INT_EN - Allows the External Diode 1 to assert the ALERT pin.
‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with External
Diode 1 channel.
‘1’ - The ALERT pin will be asserted for an error condition associated with External Diode 1
channel.
Bit 0 - INT_INT_EN - Allows the Internal Diode to assert the ALERT pin.
7.17
‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with the Internal
Diode.
‘1’ - The ALERT pin will be asserted for an error condition associated with the Internal Diode.
Fan Interrupt Enable Register
Table 7.24 Fan Interrupt Enable Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
29h
R/W
Fan
Interrupt
Enable
-
-
-
-
-
-
SPIN_
INT_EN
STALL_
INT_EN
00h
The Fan Interrupt Enable Register controls the masking for errors generated by the Fan Driver. When
a channel is masked, it will not cause the ALERT pin to be asserted when an error condition is
detected.
Bit 1 - SPIN_INT_EN - Allows the FAN_SPIN bit to assert the ALERT pin.
‘0’ (default) - the FAN_SPIN bit will not assert the ALERT pin though it will still update the Status
Register normally.
‘1’ - the FAN_SPIN bit will assert the ALERT pin.
Bit 0 - STALL_INT_EN - Allows the FAN_STALL bit or DRIVE_FAIL bit to assert the ALERT pin.
‘0’ (default) - the FAN_STALL bit or DRIVE_FAIL bit will not assert the ALERT pin though will still
update the Status Register normally.
‘1’ - the FAN_STALL bit will assert the ALERT pin.
2013 Microchip Technology Inc.
DS20005251A-page 55
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.18
PWM Driver Configuration Register
Table 7.25 PWM Driver Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
2Ah
R/W
PWM Driver
Config
-
-
-
PWM_
OT
-
-
-
POLARITY
00h
The PWM Driver Configuration Register controls the output type and polarity of the PWM fan drive
output.
Bit 4 - PWM_OT - Determines the output type for the PWM pin.
‘0’ (default) - The PWM pin is configured as an open drain output.
‘1’ - The PWM pin is configured as a push-pull output.
Bit 0 - POLARITY - Determines the polarity of the PWM pin.
7.19
‘0’ (default) - the Polarity of the PWM output driver is normal. A drive setting of 00h will cause the
output to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100%
duty cycle.
‘1’ - The Polarity of the PWM output driver is inverted. A drive setting of 00h will cause the output
to be set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty
cycle.
PWM Driver Base Frequency Register
Table 7.26 PWM Driver Base Frequency Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
2Bh
R/W
PWM Driver
Base
Frequency
-
-
-
-
-
-
B1
B0
PWM_BASE[1:0]
DEFAULT
00h
The PWM Driver Base Frequency Register controls base frequency of the PWM driver output.
Bits 1-0 - PWM_BASE[1:0] - Determines the base frequency of the PWM output driver.
Table 7.27 PWM_BASEx[1:0] it Decode
PWM_BASE[1:0]
1
0
BASE FREQUENCY
0
0
26.00kHz (default)
0
1
19.531kHz
1
0
4,882Hz
1
1
2,441Hz
DS20005251A-page 56
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.20
Limit Registers
Table 7.28 Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
30h
R/W
External Diode
1 High Limit
Sign
64
32
16
8
4
2
1
55h
(+85°C)
31h
R/W
External Diode
2 High Limit
Sign
64
32
16
8
4
2
1
55h
(+85°C)
32h
R/W
External Diode
3 High Limit
Sign
64
32
16
8
4
2
1
55h
(+85°C)
34h
R/W
Internal Diode
High Limit
Sign
64
32
16
8
4
2
1
55h
(+85°C)
38h
R/W
External Diode
1 Low Limit
Sign
64
32
16
8
4
2
1
00h
(0°C)
39h
R/W
External Diode
2 Low Limit
Sign
64
32
16
8
4
2
1
00h
(0°C)
3Ah
R/W
External Diode
3 Low Limit
Sign
64
32
16
8
4
2
1
00h
(0°C)
3Ch
R/W
Internal Diode
Low Limit
Sign
64
32
16
8
4
2
1
00h
(0°C)
The EMC2113 contains high limits for all temperature channels. If any measurement meets or exceeds
the high limit then the appropriate status bit is set and the ALERT pin is asserted (if enabled).
Additionally, the EMC2113 contains low limits for all temperature channels. If the temperature channel
drops below the low limit, then the appropriate status bit is set and the ALERT pin is asserted (if
enabled).
All Limit Registers are Software Locked.
7.21
PWM Input Duty Cycle High Limit Register
Table 7.29 PWM Duty Cycle High Limit Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
3Dh
R/W
PWM Input
Duty Cycle
High Limit
-
64
32
16
8
4
2
1
7Fh
The PWM Duty Cycle High Limit register stores a high limit on the Duty Cycle input on the PWM pin.
The data format for the register is the same as the PWM Input Duty Cycle register (see Section 7.5,
"PWM Input Duty Cycle Register") and it is compared at the sampling rate of the PWM Input duty cycle.
If the PWM Input Duty Cycle meets or exceeds this limit, then the PWM status bit is set (see Section
7.13, "Interrupt Status Register") and the ALERT pin is asserted. This is treated as a temperature limit
by the Fan Control circuitry.
2013 Microchip Technology Inc.
DS20005251A-page 57
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.22
Fan Setting Registers
Table 7.30 Fan Driver Setting Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
40h
R/W
Fan Setting
128
64
32
16
8
4
2
1
00h
The Fan Setting Register always displays the current setting of the Fan Driver. Reading from the
register will report the current fan speed setting of the fan driver regardless of the operating mode.
Therefore it is possible that reading from this register will not report data that was previously written
into this register.
While the RPM-based Fan Speed Control Algorithm and/or the Look Up Table are active, then the
register is read only. Writing to the register will have no effect and the data will not be stored.
If both the RPM-based Fan Control Algorithm and the Look Up Table are disabled, then the register
will be set with the previous value that was used. The register is read / write and writing to this register
will affect the fan speed.
The contents of the register represent the weighting of each bit in determining the final duty cycle. The
output drive for a PWM output is given by Equation [2].
VALUE
Drive = --------------------- 100%
255
7.23
[2]
PWM Divide Register
Table 7.31 PWM Divide Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
41h
R/W
PWM Divide
128
64
32
16
8
4
2
1
01h
The PWM Divide Register determines the final frequency of the PWM driver. The driver base frequency
is divided by the value of the PWM Divide Register to determine the final frequency. The duty cycle
settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h
will be decoded as 01h.
The final PWM frequency is derived as the base frequency divided by the value of this register as
shown in Equation [3].
PWM base freqeuncy
f PWM = ---------------------------------------------------------------PWM Divide Setting
7.24
[3]
Fan Configuration 1 Register
Table 7.32 Fan Configuration 1 Register
ADDR
R/W
REGISTER
B7
42h
R/W
Fan
Configuration 1
EN_
ALGO
DS20005251A-page 58
B6
B5
RANGE[1:0]
B4
B3
EDGES[1:0]
B2
B1
B0
UPDATE[2:0]
DEFAULT
2Bh
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
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The Fan Configuration 1 Register controls the general operation of the RPM-based Fan Speed Control
Algorithm used on the PWM pin.
Bit 7 - EN_ALGO - enables the RPM-based Fan Speed Control Algorithm. Based on the setting of the
RPM / PWM bit, this bit is automatically set or cleared when the LUT_LOCK bit is set (see Section
7.34, "Look Up Table Configuration Register").
‘0’ - (default) the control circuitry is disabled and the fan driver output is determined by the Fan
Driver Setting Register.
‘1’ - the control circuitry is enabled and the Fan Driver output will be automatically updated to
maintain the programmed fan speed as indicated by the TACH Target Register.
Bits 6- 5 - RANGE[1:0] - Adjusts the range of reported and programmed tachometer reading values.
The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH
Target, and TACH reading) as shown in Table 7.33, "Range Decode".
Table 7.33 Range Decode
RANGE[1:0]
1
0
REPORTED MINIMUM
RPM
TACH COUNT
MULTIPLIER
0
0
500
1
0
1
1000 (default)
2
1
0
2000
4
1
1
4000
8
Bits 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACH
signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more
accurate tachometer measurement, the minimum number of edges measured may be increased.
Increasing the number of edges measured with respect to the number of poles of the fan will cause
the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In
order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to
accommodate this shift. The Effective Tach Multiplier shown in Table 7.34, "Minimum Edges for Fan
Rotation" is used as a direct multiplier term that is applied to the Actual RPM to achieve the Reported
RPM. It should only be applied if the number of edges measured does not match the number of edges
expected based on the number of poles of the fan (which is fixed for any given fan).
Contact Microchip for recommended settings when using fans with more or less than 2 poles.
Table 7.34 Minimum Edges for Fan Rotation
EDGES[1:0]
EFFECTIVE TACH
MULTIPLIER (BASED ON 2
POLE FANS)
1
0
MINIMUM TACH
EDGES
0
0
3
1 pole
0
1
5
2 poles (default)
1
0
7
3 poles
1.5
1
1
9
4 poles
2
NUMBER OF FAN POLES
0.5
1
Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along
with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
transition of the actual fan operation as the desired fan speed changes. The Update Time is set as
shown in Table 7.35.
Table 7.35 Update Time
UPDATE[2:0]
7.25
2
1
0
UPDATE TIME
0
0
0
100ms
0
0
1
200ms
0
1
0
300ms
0
1
1
400ms (default)
1
0
0
500ms
1
0
1
800ms
1
1
0
1200ms
1
1
1
1600ms
Fan Configuration 2 Register
Table 7.36 Fan Configuration 2 Register
ADDR
R/W
REGISTER
B7
B6
B5
43h
R/W
Fan
Configuration 2
TEMP_
RR
EN_
RRC
GLITCH_
EN
B4
B3
DER_OPT [1:0]
B2
B1
ERR_RNG:0]
B0
DEFAULT
-
28h
The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the
RPM-based Fan Speed Control Algorithm.
Bit 7 - TEMP_RR - Overrides max step controls for the FSC algorithm when any temperature exceeds
its respective high limit.
‘0’ (default) - All ramp rate control circuitry works at all times for the FSC algorithm or as determined
by the EN_RRC bit for manual mode.
‘1’ - If any measured temperature or the PWM Input Duty cycle meets or exceeds its respective
high limit, then the Fan Max Step register settings are not used and the FSC algorithm acts as if
the Max Step settings were at 3Fh. The device will continue to operate in this way until all
temperatures (and the PWM input duty cycle) have dropped below the respective high limit.
Bit 6 - EN_RRC - Enables ramp rate control when the fan driver is operated in the Direct Setting mode
or the Direct Setting with LUT mode.
‘0’ (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode
or Direct Setting with LUT mode, the PWM setting will instantly transition to the next programmed
setting.
‘1’ - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode or Direct
Setting with LUT mode, the PWM setting will follow the ramp rate controls as determined by the
Fan Step and Update Time settings. The maximum PWM step is capped at the Fan Step setting
and is updated based on the Update Time as given by Table 7.35.
DS20005251A-page 60
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Bit 5 - GLITCH_EN - Disables the low pass glitch filter that removes high frequency noise injected on
the TACH pin.
‘0’ - The glitch filter is disabled.
‘1’ (default) - The glitch filter is enabled.
Bits 4 - 3 - DER_OPT[1:0] - Control some of the advanced options that affect the derivative portion of
the RPM-based Fan Speed Control Algorithm as shown in Table 7.37, "Derivative Options".
Table 7.37 Derivative Options
DER_OPT[1:0]
1
0
OPERATION
0
0
No derivative terms used
0
1
Basic derivative. The derivative of the error from
the current drive setting and the target is added
to the iterative Fan Drive setting (in addition to
proportional and integral terms - default)
1
0
Step derivative. The derivative of the error from
the current drive setting and the target is added
to the iterative Fan Drive setting and is not
capped by the maximum Fan Step Register
setting.
1
1
Both the basic derivative and the step derivative
are used effectively causing the derivative term to
have double the effect of the derivative term.
Bit 2 - 1 - ERR_RNG[1:0] - Control some of the advanced options that affect the error window. When
the measured fan speed is within the programmed error window around the target speed, then the fan
drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate
necessary drive setting changes based on the error; however, these changes are ignored.
Table 7.38 Error Range Options
ERR_RNG[1:0]
1
0
OPERATION
0
0
0 RPM (default)
0
1
50 RPM
1
0
100 RPM
1
1
200 RPM
The Fan Configuration 2 Register is Software Locked.
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.26
Gain Register
Table 7.39 Gain Register
ADDR
R/W
REGISTER
B7
B6
45h
R/W
Gain Register
-
-
B5
B4
GAIND[1:0]
B3
B2
GAINI[1:0]
B1
B0
DEFAULT
GAINP[1:0]
2Ah
The Gain Register stores the gain terms used by the proportional and integral portions of the RPMbased Fan Speed Control Algorithm. These terms will affect the FSC closed loop acquisition,
overshoot, and settling as would be expected in a classic PID system.
Table 7.40 Gain Decode
GAIND OR GAINP OR GAINI [1:0]
7.27
1
0
RESPECTIVE GAIN FACTOR
0
0
1x
0
1
2x
1
0
4x (default)
1
1
8x
Fan Spin Up Configuration Register
Table 7.41 Fan Spin Up Configuration Register
ADDR
R/W
REGISTER
B7
46h
R/W
Fan Spin Up
Configuration
B6
DRIVE_FAIL_
CNT [1:0]
B5
NOK
ICK
B4
B3
B2
SPIN_LVL[2:0]
B1
B0
DEFAULT
SPINUP_TIME
[1:0]
19h
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine.
Bit 7 - 6 - DRIVE_FAIL_CNT[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 7.42, "DRIVE_FAIL_CNT[1:0] Bit Decode". This circuitry
determines whether the fan can be driven to the desired tach target.
Table 7.42 DRIVE_FAIL_CNT[1:0] Bit Decode
DRIVE_FAIL_CNT[1:0]
1
0
0
0
Disabled - the Drive Fail detection circuitry is
disabled (default)
0
1
16 - the Drive Fail detection circuitry will count for 16
update periods
DS20005251A-page 62
NUMBER OF UPDATE PERIODS
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Table 7.42 DRIVE_FAIL_CNT[1:0] Bit Decode (continued)
DRIVE_FAIL_CNT[1:0]
1
0
NUMBER OF UPDATE PERIODS
1
0
32 - the Drive Fail detection circuitry will count for 32
update periods
1
1
64 - the Drive Fail detection circuitry will count for 64
update periods
Bit 5 - NOKICK - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the
programmed spin up time before driving it at the programmed level.
‘0’ (default) - The Spin Up Routine will drive the PWM to 100% for 1/4 of the programmed spin up
time before reverting to the programmed spin level.
‘1’ - The Spin Up Routine will not drive the PWM to 100%. It will set the drive at the programmed
spin level for the entire duration of the programmed spin up time.
Bits 4 - 2 - SPIN_LVL[2:0] - Determines the final drive level that is used by the Spin Up Routine as
shown in Table 7.43, "Spin Level".
Table 7.43 Spin Level
SPIN_LVL[2:0]
2
1
0
SPIN UP DRIVE LEVEL
0
0
0
30%
0
0
1
35%
0
1
0
40%
0
1
1
45%
1
0
0
50%
1
0
1
55%
1
1
0
60% (default)
1
1
1
65%
Bit 1 -0 - SPINUP_TIME[1:0] - determines the maximum Spin Time that the Spin Up Routine will run
for (see Section 6.8, "Spin Up Routine"). If a valid tachometer measurement is not detected before the
Spin Time has elapsed, then an interrupt will be generated. When the RPM-based Fan Speed Control
Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last
spin up attempt.
The Spin Time is set as shown in Table 7.44.
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.44 Spin Time
SPINUP_TIME[1:0]
1
0
TOTAL SPIN UP TIME
0
0
250 ms
0
1
500 ms (default)
1
0
1 sec
1
1
2 sec
The Fan Spin Up Configuration Register is software locked.
7.28
Fan Step Register
Table 7.45 Fan Step Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
47h
R/W
Fan Max Step
-
-
32
16
8
4
2
1
10h
The Fan Step Register, along with the Update Time, control the ramp rate of the fan driver response.
The value of the registers represents the maximum step size each fan driver will take between update
times (see Section 7.24, "Fan Configuration 1 Register").
All modes of operation have the options to use the Fan Step Register (and update times) for ramp rate
control based on the Fan Configuration 2 Register settings. The Fan Speed Control Algorithm will
always use the Fan Step Register settings (but see application note below).
The Fan Step Register is software locked.
7.29
Fan Minimum Drive Register
Table 7.46 Minimum Fan Drive Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
48h
R/W
Fan Minimum
Drive
128
64
32
16
8
4
2
1
66h
(40%)
The Fan Minimum Drive Register stores the minimum drive setting for the RPM-based Fan Speed
Control Algorithm. This register is not used if the FSC is not active. The RPM-based Fan Speed Control
Algorithm will not drive the fan at a level lower than the minimum drive unless the target TACH Target
is set at FFh. (See Section 7.32, "TACH Target Register".)
During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan
Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a
setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control
circuitry attempts to drive it at a level that cannot support fan operation.
The Fan Minimum Drive Register is software locked.
DS20005251A-page 64
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.30
Valid TACH Count Register
Table 7.47 Valid TACH Count Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
49h
R/W
Valid TACH
Count
4096
2048
1024
512
256
128
64
32
F5h
The Valid TACH Count Register store the maximum TACH Reading Register value to indicate that the
the fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine
if the fan has started operating and decide if the device needs to retry.
See Equation [5] for translating the count to an RPM.
If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan
RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the
algorithm will automatically begin its Spin Up Routine.
APPLICATION NOTE: The automatic invoking of the Spin Up Routine only applies if the Fan Speed Control
Algorithm is used. If the FSC is disabled, then the device will only invoke the Spin Up Routine
when the PWM setting changes from 00h.
If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored
and the algorithm will use the current fan drive setting.
The Valid TACH Count Register is software locked.
7.31
Fan Drive Fail Band Registers
Table 7.48 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ah
R/W
Fan Drive
Fail Band
Low Byte
16
8
4
2
1
-
-
-
00h
4Bh
R/W
Fan Drive
Fail Band
High Byte
4096
2048
1024
512
256
128
64
32
00h
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail
detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is
enabled, the actual measured fan speed is compared against the target fan speed.
This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually
capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan
Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0]
bits then the DRIVE_FAIL status bit will be set and an interrupt generated.
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
7.32
TACH Target Register
Table 7.49 TACH Target Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ch
R/W
Fan TACH
Target Low
Byte
16
8
4
2
1
-
-
-
F8h
4Dh
R/W
TACH Target
4096
2048
1024
512
256
128
64
32
FFh
The TACH Target Register holds the target tachometer value that is maintained by the RPM-based
Fan Speed Control Algorithm.
The value in the TACH Target Register will always reflect the current TACH Target value. If the Look
Up Table is active and configured to operate in RPM Mode, then this register will be read only. Writing
to this register will have no affect and the data will not be stored.
If the algorithm is enabled then setting the TACH Target Register to FFh will disable the fan driver (set
the PWM duty cycle to 0%). Setting the TACH Target to any other value (from a setting of FFh) will
cause the algorithm to invoke the Spin Up Routine after which it will function normally.
7.33
TACH Reading Register
Table 7.50 TACH Reading Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Eh
R
Fan TACH
4096
2048
1024
512
256
128
64
32
FFh
4Fh
R
Fan TACH
Low Byte
16
8
4
2
1
-
-
-
F8h
The TACH Reading Register contents describe the current tachometer reading for the fan. By default,
the data represents the fan speed as the number of 32kHz clock periods that occur for a single
revolution of the fan.
Equation [4] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation
[5] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan,
measuring 5 edges, with a frequency of 32.768kHz.
These equations are solved and tabulated for ease of use in AN17.4 RPM to TACH Counts
Conversion.
DS20005251A-page 66
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
where:
poles = number of poles of the fan
(typically 2)
1
n – 1
RPM = -------------------- ---------------------------------- 1,966,080
poles
1COUNT ---m
n = number of edges measured
(typically 5)
m = the multiplier defined by the
RANGE bits
3,932,160 m
RPM = -------------------------------------COUNT
7.34
[4]
[5]
COUNT = TACH Reading Register
value (in decimal)
Look Up Table Configuration Register
Table 7.51 Look Up Table Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R/W
LUT
Configuration
USE_
DTS_P1
USE_
DTS_P2
LUT
LOCK
RPM /
PWM
PUSH1_
CFG
TEMP1_
CFG
TEMP3_
CFG
TEMP4_
CFG
00h
50h
7Dh
The Look Up Table Configuration Register controls the setup information for the temperature to fan
drive look up table.
APPLICATION NOTE: This register is duplicated at 50h as well as 7Dh for ease of programming using block write
mode. Example: Set register 50h to unlock the table and register 7Dh to lock the table.
The External Diode 2 channel is always used as the Temperature 2 input to the Fan Control Look Up
Table.
Bit 7 - USE_DTS_P1 - This bit determines whether the Pushed Temperature 1 Register is using DTS
data.
‘0’ (default) - The Pushed Temperature 1 Register is not using DTS data. The contents of the
Pushed Temperature 1 registers are standard temperature data.
‘1’ - The Pushed Temperature 1 Register is loaded with DTS data. The contents of this register are
automatically subtracted from a fixed value of 100°C before being compared to the Look Up Table
threshold levels.
Bit 6 - USE_DTS_P2 - This bit determines whether the Pushed Temperature 2 Register is using DTS
data.
‘0’ (default) - The Pushed Temperature 2 Register is not using DTS data. The contents of this
register are standard 2’s complement temperature data.
‘1’ - The Pushed Temperature 2 Register is loaded with DTS data. The contents of this register are
automatically subtracted from a fixed value of 100°C before being compared to the Look Up Table
threshold levels.
Bit 5 - LUT_LOCK - This bit locks updating the Look Up Table entries and determines whether the look
up table is being used.
‘0’ (default) - The Look Up Table entries can be updated normally. The Look Up Table will not be
used while the Look Up Table entries are unlocked. During this condition, the PWM output will not
change states regardless of temperature or tachometer variation.
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
‘1’ - The Look Up Table entries are locked and cannot be updated. The Look Up Table is fully active
and will be used based on the loaded values. The PWM output will be updated depending on the
temperature and / or TACH variations.
APPLICATION NOTE: When the LUT_LOCK bit is set at a logic ‘0’, the PWM drive setting will be set at whatever
value was last used by the RPM-based Fan Speed Control Algorithm or the Look Up Table.
Bit 4 - RPM / PWM - This bit selects the data format for the LUT drive settings.
‘0’ (default) - The Look Up Table drive settings are RPM TACH count values for use by the RPMbased Fan Speed Control Algorithm. The Look Up Table drive settings should be loaded highest
value to lowest value (to coincide with the inversion between TACH counts and actual RPM).
‘1’ - The Look Up Table drive settings are PWM duty cycle values and are used directly. The drive
settings should be loaded lowest value to highest value.
Bit 3 - PUSH1_CFG - Determines whether the PWM Input duty cycle is used instead of the Pushed 1
Temperature data when the TEMP1_CFG bit is set.
‘0’ (default) - The Pushed Temperature 1 register can be written via the SMBus and will hold a
temperature value. The PWM Input Duty cycle is not used.
‘1’ - If the TEMP1_CFG or TEMP3_CFG bit is set, the PWM Input Duty cycle will be used. The
Pushed Temperature 1 register can be written via the SMBus and will hold a temperature value but
will not be used.
APPLICATION NOTE: If the Pushed Temperature 1 data is configured to hold the PWM input duty cycle and is used
in the Look Up Table, then the Look Up Table threshold levels must be programmed in the
same format as the PWM input duty cycle - see Section 7.5 and Section 7.35.
Bit 2 - TEMP1_CFG - Determine the temperature channel that is used for the Temperature 1 inputs to
the Look Up Table.
‘0’ (default) - The External Diode 1 channel is used by the Fan Look Up Table.
‘1’ - Either the data written into the Pushed Temperature 1 Register or the data in the PWM Input
Duty Cycle register is used by the Fan Look Up table as determined by the PUSH1_CFG bit.
Bit 1 - TEMP3_CFG - Determine the temperature channel that is used for the Temperature 3 inputs to
the Look Up Table.
‘0’ (default) - The External Diode 3 channel is used by the Fan Look Up Table (if enabled).
‘1’ - Either the data written into the Pushed Temperature 1 Register or the data in the PWM Input
Duty Cycle register is used by the Fan Look Up table as determined by the PUSH1_CFG bit.
Bit 0 - TEMP4_CFG - Determine the temperature channel that is used for the Temperature 4 inputs to
the Look Up Table.
7.35
‘0’ (default) -The Internal diode channel is used by the Fan Look Up Table.
‘1’ - The data written into the Pushed Temperature 2 Register is used by the Fan Look Up Table.
Look Up Table Registers
Table 7.52 Look Up Table Registers
ADDR
R/W
REGISTER
51h
R/W
LUT Drive
Setting 1
DS20005251A-page 68
RPM /
PWM
B7
B6
B5
B4
B3
B2
B1
B0
‘0’
4096
2048
1024
512
256
128
64
32
‘1’
128
64
32
16
8
4
2
1
DEFAULT
FBh
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
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Table 7.52 Look Up Table Registers (continued)
RPM /
PWM
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
LUT Temp 1
Setting 1
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
R/W
LUT Temp 2
Setting 1
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
54h
R/W
LUT Temp 3
Setting 1
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
55h
R/W
LUT Temp 4
Setting 1
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
...
...
...
...
...
...
...
...
...
...
...
...
...
4096
2048
1024
512
256
128
64
32
R/W
LUT Drive
Setting 8
‘0’
74h
‘1’
128
64
32
16
8
4
2
1
ADDR
R/W
REGISTER
52h
R/W
53h
92h
75h
R/W
LUT Temp
1Setting 8
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
76h
R/W
LUT Temp 2
Setting 8
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
77h
R/W
LUT Temp 3
Setting 8
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
78h
R/W
LUT Temp 4
Setting 8
X
-
64
32
16
8
4
2
1
7Fh
(127°C)
79h
R/W
LUT Temp 1
Hysteresis
X
-
-
-
16
8
4
2
1
0Ah
(10°C)
7Ah
R/W
LUT Temp 2
Hysteresis
X
-
-
-
16
8
4
2
1
0Ah
(10°C)
7Bh
R/W
LUT Temp 3
Hysteresis
X
-
-
-
16
8
4
2
1
0Ah
(10°C)
7Ch
R/W
LUT Temp 4
Hysteresis
X
-
-
-
16
8
4
2
1
0Ah
(10°C)
The Look Up Table Registers hold the 40 entries of the Look Up Table that control the drive of the
PWM. As the temperature channels are updated, the measured value for each channel is compared
against the respective entries in the Look Up Table and the associated drive setting is loaded into an
internal shadow register and stored.
The bit weighting for temperature inputs represents °C and is compared against the measured data.
Note that the LUT entry does not include a sign bit. The Look Up Table does not support negative
temperature values and the MSBit should not be set for a temperature input.
APPLICATION NOTE: When the PWM Input Duty cycle values are used, then the bit weighting represents a unitless threshold that does not corresponded to specific temperature values. It is used to drive
the fan speed based on external temperatures known to a separate microcontroller driving
the PWM_IN pin.
Each temperature channel threshold for a single “column” shares the same hysteresis value; however,
each temperature input has a different hysteresis value. When the measured temperature for any of
the channels meets or exceeds the programmed threshold, the drive setting associated with that
threshold is used. The temperature must drop below the threshold minus the hysteresis value before
the drive setting will be set to the previous value.
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
If the RPM-based Fan Speed Control Algorithm is used, the TACH Target is updated after every
conversion. It is always set to the minimum TACH Target that is stored by the Look Up Table. The
PWM duty cycle is updated based on the RPM-based Fan Speed Control Algorithm configuration
settings.
If the RPM-based Fan Speed Control Algorithm is not used, then the output PWM duty cycle is updated
after every conversion. It is set to the maximum duty cycle that is stored by the Look Up Table.
If the measured temperature reading on all channels is less than the lowest threshold setting minus
the appropriate hysteresis setting, then the Fan driver will be set to 0% duty cycle and the fan will be
disabled.
7.36
Software Lock Register
Table 7.53 Software Lock
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
EFh
R/W
Software
Lock
-
-
-
-
-
-
-
LOCK
00h
The Software Lock Register controls the software locking of critical registers. This register is software
locked.
Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked
registers become read only and cannot be updated.
7.37
‘0’ (default) - all SWL registers can be updated normally.
‘1’ - all SWL registers cannot be updated and a hard-reset is required to unlock them.
Product Features Register
Table 7.54 Product Features Register
ADDR
R/W
REGISTER
B7
B6
FCh
R
Product
Features
-
-
B5
B4
B3
ADDR_SEL[2:0]
B2
B1
B0
SHDN_SEL[2:0]
DEFAULT
00h
The Product Features Register indicates which pin selected functionality is enabled.
Bits 5-3 - ADDR_SEL[2:0] - Indicates the address that is decoded by the ADDR_SEL pin as shown in
Table 7.55, "ADDR_SEL[2:0] Encoding".
Table 7.55 ADDR_SEL[2:0] Encoding
ADDR_SEL[2:0]
2
1
0
SMBUS ADDRESS
0
0
0
0101_100(r/w)
0
0
1
0101_101(r/w)
0
1
0
0101_110(r/w)
DS20005251A-page 70
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table 7.55 ADDR_SEL[2:0] Encoding (continued)
ADDR_SEL[2:0]
2
1
0
SMBUS ADDRESS
0
1
1
1001_100(r/w)
1
0
0
1001_101(r/w)
1
0
1
1001_000(r/w)
Bits 2-0 - SHDN_SEL[2:0] - Indicate the functionality enabled by the SHDN_SEL pin as shown in
Table 7.56, "SHDN_SEL[2:0] Encoding".
Table 7.56 SHDN_SEL[2:0] Encoding
SHDN_SEL[2:0]
2
1
0
0
0
0
External Diode 1 Simple Mode - Beta
compensation disabled, REC disabled recommended for AMD CPU diodes
none
0
0
1
External Diode 1 Diode Mode - Beta
compensation disabled, REC enabled
none
0
1
0
External Diode 1 Transistor Mode - Beta
compensation enabled, REC enabled - recommended for Intel 45nm and 65mn
CPU diodes
none
0
1
1
Internal Diode Transistor Mode - Beta
compensation enabled, REC enabled
none
1
0
0
External Diode 2 Transistor Mode - Beta
compensation enabled, REC enabled
none
1
0
1
External Diode 1 Transistor Mode - Beta
compensation enabled, REC enabled
none
7.38
DIODE MODE
OTHER FEATURES
Product ID Register
Table 7.57 Product ID Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FDh
R
Product ID
Register
0
0
1
0
0
1
0
0
2Eh
The Product ID Register contains a unique 8-bit word that identifies the product.
2013 Microchip Technology Inc.
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Datasheet
7.39
Manufacturer ID Register
Table 7.58 Manufacturer ID Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FEh
R
Manufacturer
ID
0
1
0
1
1
1
0
1
5Dh
The Manufacturer ID Register contains an 8-bit word that identifies Microchip.
7.40
Revision Register
Table 7.59 Revision Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
FFh
R
Revision
1
0
0
0
0
0
0
1
81h
The Revision Register contains an 8-bit word that identifies the die revision.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 8 Typical Operating Curves
The following Typical Operating Curves are included:
Supply Current vs. Temperature
Supply Current vs. Supply Voltage
Temperature Error vs. Series Resistance
Temperature Error vs. Ambient Temperature
Temperature Error vs. Supply Voltage
Fan TACH Accuracy vs. Temperature
Fan TACH Accuracy vs. Supply Voltage
PWM Output Frequency vs. Supply Voltage
PWM Output Frequency vs. Temperature
FSC Operation
Look Up Table operation - PWM / Direct Drive
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Datasheet
DS20005251A-page 74
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
2013 Microchip Technology Inc.
DS20005251A-page 75
DS20005251A-page 76
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Datasheet
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Chapter 9 Package Drawing
9.1
EMC2113 Package Information
Figure 9.1 16-Pin QFN 4mm x 4mm Package Dimensions
Figure 9.2 16-Pin QFN 4mm x 4mm PCB Footprint
2013 Microchip Technology Inc.
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DS20005251A-page 78
Figure 9.3 16-Pin QFN 4mm x 4mm Package Drawing
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
9.2
Package Markings
Figure 9.4 EMC2113 Package Markings
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Appendix A Look Up Table Operation
The EMC2113 uses a look-up table to apply a user-programmable fan control profile based on
measured temperature to the fan driver. In this look-up table, each temperature channel is allowed to
control the fan drive output independently (or jointly) by programming up to eight pairs of temperature
and drive setting entries.
The user programs the look-up table based on the desired operation. If the RPM-based Fan Speed
Control Algorithm is to be used (see Section 6.6), then the user must program an RPM target for each
temperature setting of interest. Alternately, if the RPM-based Fan Speed Control Algorithm is not to be
used, then the user must program a drive setting for each temperature setting of interest.
If the measured temperature on the External Diode channel meets or exceeds any of the temperature
thresholds for any of the channels, the fan output will be automatically set to the desired setting
corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds
are exceeded, the highest fan drive setting will take precedence.
When the measured temperature drops to a point below a lower threshold minus the hysteresis value,
the fan output will be set to the corresponding lower set point.
The following sections show examples of how the Look Up Table is used and configured. Each Look
Up Table Example uses the Fan 1 Look Up Table Registers configured as shown in Table A.1.
Table A.1 Look Up Table Format
STEP
TEMP 1
TEMP 2
TEMP 3
TEMP 4
LUT DRIVE
1
LUT Temp 1
Setting 1 (52h)
LUT Temp 2
Setting 1 (53h)
LUT Temp 3
Setting 1 (54h)
LUT Temp 4
Setting 1 (55h)
LUT Drive
Setting 1 (51h)
2
LUT Temp 1
Setting 2 (57h)
LUT Temp 2
Setting 2 (58h)
LUT Temp 3
Setting 2 (59h)
LUT Temp 4
Setting 2 (5Ah)
LUT Drive
Setting 2 (56h)
3
LUT Temp 1
Setting 3 (5Ch)
LUT Temp 2
Setting 3 (5Dh)
LUT Temp 3
Setting 3 (5Eh)
LUT Temp 4
Setting 3 (5Fh)
LUT Drive
Setting 3 (5Bh)
4
LUT Temp 1
Setting 4 (61h)
LUT Temp 2
Setting 4 (62h)
LUT Temp 3
Setting 4 (63h)
LUT Temp 4
Setting 4 (64h)
LUT Drive
Setting 4 (60h)
5
LUT Temp 1
Setting 5 (66h)
LUT Temp 2
Setting 5 (67h)
LUT Temp 3
Setting 5 (68h)
LUT Temp 4
Setting 5 (69h)
LUT Drive
Setting 5 (65h)
6
LUT Temp 1
Setting 6 (6Bh)
LUT Temp 2
Setting 6 (6Ch)
LUT Temp 3
Setting 6 (6Dh)
LUT Temp 4
Setting 6 (6Eh)
LUT Drive
Setting 6 (6Ah)
7
LUT Temp 1
Setting 7 (70h)
LUT Temp 2
Setting 7 (71h)
LUT Temp 3
Setting 7 (72h)
LUT Temp 4
Setting 7 (73h)
LUT Drive
Setting 7 (6Fh)
8
LUT Temp 1
Setting 8 (75h)
LUT Temp 2
Setting 8 (76h)
LUT Temp 3
Setting 8 (77h)
LUT Temp 4
Setting 8 (78h)
LUT Drive
Setting 8 (74h)
A.1
Example #1
This example does not use the RPM-based Fan Speed Control Algorithm. Instead, the Look Up Table
is configured to directly set a PWM setting based on the temperature of four of its measured inputs.
The configuration is set as shown in Table A.2, "Look Up Table Example #1 Configuration".
Once configured, the Look Up Table is loaded as shown in Section Table A.3, "Fan Speed Control
Table Example #1". Table A.4 shows three temperature configurations using the settings in Table A.3
and the final PWM output drive setting that the Look Up Table will select.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table A.2 Look Up Table Example #1 Configuration
ADDR
REGISTER
50h
LUT
Configuration
A.1.1
B7
B6
B5
B4
B3
B2
B1
B0
SETTING
USE_
DTS_F1
USE_
DTS_F2
LUT_
LOCK
RPM /
PWM
PUSH1_
CFG
TEMP1_
CFG
TEMP3_
CFG
TEMP4_
CFG
C0h
0
0
1
1
0
0
0
0
LUT Configuration Bit Description
Bit 7 - USE_DTS_F1 = ‘0b’ tells the circuitry that the Forced Temperature 1 register data is not in DTS
format.
Bit 6 - USE_DTS_F2 = ‘0b’ tells the circuitry that the Forced Temperature 2 register data is not in DTS
format.
Bit 5 - LUT_LOCK = ‘1b’ tells the circuitry that the LUT is programmed and is active. This bit must be
set for the LUT to function.
Bit 4 - RPM / PWM = ‘1b’ tells the Look Up Table that the FSC algorithm is not used and that the LUT
target values will be PWM drive settings instead of TACH Target settings.
Bit 3 - PUSH1_CFG = ‘0b’ tells the circuitry that the LUT should referenced the Forced Temperature
data instead of the PWM Input Duty Cycle data. This is the default setting.
Bit 2 - TEMP1_CFG = ‘0b’ tells the LUT to reference the External Diode 1 data instead of Forced
Temperature 1 data. This is the default setting.
Bit 1 - TEMP3_CFG = ‘0b’ tells the LUT to reference the External Diode 3 data instead of Forced
Temperature 1 data. This is the default setting.
Bit 0 - TEMP4_CFG = ‘0b’ tells the LUT to reference the Internal Diode data instead of Forced
Temperature 2 data. This is the default setting.
Table A.3 Fan Speed Control Table Example #1
FAN
SPEED
STEP #
EXTERNAL DIODE
1 TEMPERATURE
(CPU)
EXTERNAL
DIODE 2
TEMPERATURE
(GPU)
EXTERNAL DIODE
3 TEMPERATURE
(SKIN)
INTERNAL DIODE
TEMPERATURE
(AMBIENT)
PWM
SETTINGS
1
35oC
60oC
30oC
40oC
0%
2
40oC
70oC
35oC
45oC
30%
3
50oC
75oC
40oC
50oC
40%
4
60oC
80oC
45oC
55oC
50%
5
70oC
85oC
50oC
60oC
60%
6
80oC
90oC
55oC
65oC
70%
7
90oC
95oC
60oC
70oC
80%
8
100oC
100oC
65oC
75oC
100%
Note: The values shown in Table A.3 are example settings. All the cells in the look-up table are
programmable via SMBus.
2013 Microchip Technology Inc.
DS20005251A-page 81
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table A.4 Fan Speed Determination for Example #1 (using settings in Table A.3)
EXTERNAL
DIODE 1
TEMPERATURE
(CPU)
EXTERNAL
DIODE 2
TEMPERATURE
(GPU)
EXTERNAL
DIODE 3
TEMPERATURE
(SKIN)
INTERNAL DIODE
TEMPERATURE
(AMBIENT)
Example 1:
82°C
82°C
48°C
58°C
70% (CPU temp
requires highest drive)
Example 2:
82C°
97°C
62°C
58°C
80% (GPU and Skin
require highest drive)
Example 3:
82°C
97°C
62°C
75°C
100% (Internal temp
requires highest drive)
A.2
PWM RESULT
Example #2
This example uses the RPM-based Fan Speed Control Algorithm. The Spin Level (used by the Spin
Up Routine) should be changed to 40% drive for a total Spin Time of 1 second. For all other RPM
configuration settings, the default conditions are used.
For control inputs, it uses the External Diode 1 channel normally, the External Diode 2 channel
normally, and both Pushed Temperature registers in DTS format. The configuration is set as shown in
Table A.5, "Look Up Table Example #2 Configuration" while Table A.6, "Fan Speed Control Table
Example #2" shows how the table is loaded.
Note that when using DTS data, the USE_DTS_F1 and / or USE_DTS_F2 bits should be set. The
Pushed Temperature Registers are loaded with the normal DTS values as received by the processor.
When the DTS value is used by the Look Up Table, the value that is stored in the Pushed Temperature
Register is subtracted from a fixed temperature of 100°C. This resultant value is then compared
against the Look Up Table thresholds normally. When programming the Look Up Table, it is necessary
to take this translation into account or else incorrect settings may be selected.
Table A.5 Look Up Table Example #2 Configuration
ADDR
REGISTER
46h
Fan Spin Up
Configuration
50h
LUT
Configuration
A.2.1
B7
B6
DRIVE_FAIL_CNT
[1:0]
B5
B4
NOKICK
B3
B2
B1
SPIN_LVL[2:0]
B0
SETTING
SPINUP_TIME [1:0]
0Ah
0
0
0
0
1
0
1
0
USE_
DTS_F1
USE_
DTS_F2
LUT_
LOCK
RPM /
PWM
PUSH1_
CFG
TEMP1_
CFG
TEMP3_
CFG
TEMP4_
CFG
1
1
1
0
0
0
1
1
Fan Spin Up Configuration Bit Description
Bits 7-6 - DRIVE_FAIL_CNT[1:0] = ‘00b’ tells the circuitry that the drive fail detection circuitry is not
enabled. This is the default setting.
Bit 5 - NOKICK = ‘0b’ tells the circuitry that if than Spin Up Routine is invoked, it will drive to 100%
duty cycle for 25% of the spin up time. This is the default setting.
Bits 4-2 - SPIN_LVL[2:0] = ‘010b’ tells the circuitry that if the Spin Up Routine is invoked, it should run
at 40% drive.
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Bits 1-0 - SPINUP_TIME[1:0] = ‘10b’ tells the circuitry that if the Spin Up Routine is invoked, it will run
at 100% duty cycle for 250ms and at 40% duty cycle for 750ms for a total spin up time of 1s.
A.2.2
LUT Configuration - Bit Description
7 - USE_DTS_F1 = ‘1b’ tells the circuitry that the data in the Pushed Temperature 1 register is in DTS
format which means that the value in the register is equal to 100C - CPU Temp.
Bit 6 - USE_DTS_F2 = ‘1b’ tells the circuitry that the data in the Pushed Temperature 1 register is in
DTS format which means that the value in the register is equal to 100°C - CPU temp.
Bit 5 - LUT_LOCK = ‘1b’ tells the circuitry that the LUT is programmed and is active. This bit must be
set for the LUT to function.
Bit 4 - RPM_PWM = ‘0b’ tells the LUT circuitry that the FSC algorithm is active and that the LUT values
are TACH Target settings. This is the default setting.
Bit 3 - PUSH1_CFG = ‘0b’ tells the circuitry that the LUT should referenced the Forced Temperature
data instead of the PWM Input Duty Cycle data. This is the default setting.
Bit 2 - TEMP1_CFG = ‘0b’ tells the LUT to reference the External Diode 1 data instead of Forced
Temperature 1 data.
Bit 1 - TEMP3_CFG = ‘1’b tells the Look Up Table to reference the Forced Temperature 1 data instead
of the External Diode 3 data.
Bit 0- TEMP4_CFG = ‘1b’ tells the Look Up Table to reference the Forced Temperature 2 data instead
of the Internal Diode data.
Table A.6 Fan Speed Control Table Example #2
FAN
SPEED
STEP #
EXTERNAL
DIODE 1
TEMPERATURE
(CPU)
EXTERNAL
DIODE 2
TEMPERATURE
(GPU)
PUSHED
TEMPERATURE
SETTING (DTS1)
PUSHED
TEMPERATURE
SETTING (DTS2)
TACH
TARGET
HIGH BYTE
1
35oC
65oC
50oC
40oC
EFh
(1028 RPM)
2
40oC
75oC
55oC
45oC
A3h
(1508 RPM)
3
50oC
85oC
60oC
50oC
7Ah
(2014 RPM)
4
60oC
90oC
65oC
55oC
62h
(2508 RPM)
5
70oC
95oC
70oC
60oC
52h
(2997 RPM)
6
80oC
100oC
75oC
65oC
3Dh
(4029 RPM)
7
90oC
105oC
80oC
80oC
31h
(5016 RPM)
8
100oC
110oC
85oC
100oC
29h
(5994 RPM)
Note: The values shown in Table A.6 are example settings. All the cells in the look-up table are
programmable via SMBus.
2013 Microchip Technology Inc.
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Table A.7 Fan Speed Determination for Example #2 (using settings in Table A.6)
EXTERNAL
DIODE 1
TEMPERATURE
(CPU)
EXTERNAL
DIODE 2
TEMPERATURE
(GPU)
Example 1:
75°C
Example 2:
Example 3:
A.3
PUSHED
TEMPERATURE
(DTS1)
PUSHED
TEMPERATURE
(DTS2)
75°C
35°C
(translated as 65°C)
50°C
(translated as 50°C)
52h (2997 RPM) CPU requires highest
target
75°C
90°C
15°C
(translated as
85°C)
20°C
(translated as 80°C)
29h (5994 RPM) DTS1 requires
highest target
75°C
97.25°C
30°C
(translated as 70°C)
5°C
(translated as
95°C)
31h (5016 RPM) DTS2 requires
highest target
PWM RESULT
Example #3
This example uses the RPM-based Fan Speed Control Algorithm with default settings.
For control inputs, it uses the External Diode 1 channel normally, the External Diode 2 channel
normally, the PWM input instead of External Diode 3, and the Internal Diode. The configuration is set
as shown in Table A.8 while Table A.9 shows how the table is loaded.
Table A.8 Look Up Table Example #3 Configuration
ADDR
REGISTER
90h
LUT
Configuration
A.3.1
B7
B6
B5
B4
B3
B2
B1
B0
SETTING
USE_
DTS_F1
USE_
DTS_F2
LUT_
LOCK
RPM /
PWM
PUSH1_
CFG
TEMP1_
CFG
TEMP3_
CFG
TEMP4_
CFG
2Ah
0
0
1
0
1
0
1
0
LUT COnfiguration Bit Description
Bit 7 - USE_DTS_F1 = ‘0b’ tells the circuitry that the Forced Temperature 1 register data is not in DTS
format.
Bit 6 - USE_DTS_F2 = ‘0b’ tells the circuitry that the Forced Temperature 2 register data is not in DTS
format.
Bit 5 - LUT_LOCK = ‘1b’ tells the circuitry that the LUT is programmed and is active. This bit must be
set for the LUT to function.
Bit 4 - RPM_PWM = ‘0b’ tells the LUT circuitry that the FSC algorithm is active and that the LUT values
are TACH Target settings. This is the default setting.
Bit 3 - PUSH1_CFG = ‘1b’ tells the Look Up Table to reference the PWM Input Duty Cycle instead of
the Pushed Temperature 1 register.
Bit 2 - TEMP1_CFG = ‘0b’ tells the LUT to reference the External Diode 1 data instead of Forced
Temperature 1 data. This is the default setting.
DS20005251A-page 84
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RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Bit 1 - TEMP3_CFG = ‘1b’ tells the Look Up Table to reference Pushed Temperature 1 instead of
External Diode 3, except that PUSH1_CFG re-directs the logic to reference the PWM Input Duty Cycle
register instead.
Bit 0 - TEMP4_CFG = ‘0b’ tells the LUT to reference the Internal Diode data instead of Forced
Temperature 2 data. This is the default setting.
Table A.9 Fan Speed Control Table Example #3
FAN
SPEED
STEP #
EXTERNAL
DIODE 1
TEMPERATURE
(CPU)
EXTERNAL
DIODE 2
TEMPERATURE
(GPU)
1
35oC
65oC
20% Duty Cycle
(1Ah)
40oC
EFh
(1028 RPM)
2
40oC
75oC
30% Duty Cycle
(26h)
45oC
A3h
(1508 RPM)
3
50oC
85oC
40% Duty Cycle
(33h)
50oC
7Ah
(2014 RPM)
4
60oC
90oC
50% Duty Cycle
(40h)
55oC
62h
(2508 RPM)
5
70oC
95oC
60% Duty Cycle
(4Dh)
60oC
52h
(2997 RPM)
6
80oC
100oC
70% Duty Cycle
(5Ah)
65oC
3Dh
(4029 RPM)
7
90oC
105oC
80% Duty Cycle
(66h)
80oC
31h
(5016 RPM)
8
100oC
110oC
90% Duty Cycle
(73h)
100oC
29h
(5994 RPM)
PWM DUTY
CYCLE
TACH
TARGET
INTERNAL DIODE
Note: The values shown in Table A.9 are example settings. All the cells in the look-up table are
programmable via SMBus.
Table A.10 Fan Speed Determination for Example #2 (using settings in Table A.9)
EXTERNAL
DIODE 1
TEMPERATURE
(CPU)
EXTERNAL
DIODE 2
TEMPERATURE
(GPU)
PWM INPUT DUTY
CYCLE
INTERNAL DIODE
PWM RESULT
Example 1:
75°C
75°C
45% Duty Cycle
50°C
52h (2997 RPM) CPU requires highest
target
Example 2:
75°C
90°C
85% Duty Cycle
70°C
31h (5016 RPM) PWM requires highest
target
Example 3:
75°C
97.25°C
75% Duty Cycle
95°C
31h (5016 RPM) DTS2 requires
highest target
2013 Microchip Technology Inc.
DS20005251A-page 85
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Datasheet Revision History
Revision History
REVISION LEVEL & DATE
REV A
SECTION/FIGURE/ENTRY
CORRECTION
Replaces the previous SMSC version Rev. 1.2
Rev. 1.2 (10-08-09)
Chapter 8, Typical
Operating Curves
Added chapter.
Rev. 1.1 (07-21-09)
Section 6.1.1, "SYS_SHDN
Pin"
Added section to describe SYS_SHDN pin
operation.
Section 6.12, "ALERT Pin"
Added section to describe ALERT pin operation.
Cover and Features
Updated text to include ALERT pin and
temperature limits
General Description
Modified bullet under “Temperature Look-Up Table”
from: “Allows programmed fan response to
temperature”
to: “Allows external PWM input (50Hz-40kHz) as
an additional temperature input”
Table 4.2, "Electrical
Specifications"
“Tachometer Setting Accuracy” changed to “RPM
Control Accuracy”
Rev. 1.1 (05-22-09)
Value in MAX Column changed from: “+/- 3%”
to: “+/- 2%”
Rev. 1.1 (05-15-09)
Rev. 1.0 (02-11-09)
DS20005251A-page 86
Table 4.1, "Absolute
Maximum Ratings"
Updated table for 5V tolerant pins issue
Table 4.3, "SMBus Electrical
Specifications"
Updated electrical specifications for supply current
Section 7.40, "Revision
Register"
Updated revision history
Appendix B “RPM to
Tachometer Count Look Up
Tables”
Removed Appendix B and added reference to
AN17.4 RPM to TACH Counts Conversion, which
includes more information.
Initial release of datasheet
2013 Microchip Technology Inc.
RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32
logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM,
MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and ZScale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
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A more complete list of registered trademarks and common law trademarks owned by Standard Microsystems Corporation (“SMSC”)
is available at: www.smsc.com. The absence of a trademark (name, logo, etc.) from the list does not constitute a waiver of any
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All other trademarks mentioned herein are property of their respective companies.
© 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781620776506
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devices, Serial EEPROMs, microperipherals, nonvolatile memory and
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and manufacture of development systems is ISO 9001:2000 certified.
2013 Microchip Technology Inc.
DS20005251A-page 87
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DS20005251A-page 88
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10/28/13
2013 Microchip Technology Inc.