ENC424J600/624J600
Data Sheet
Stand-Alone 10/100 Ethernet Controller
with SPI or Parallel Interface
2010 Microchip Technology Inc.
DS39935C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
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© 2010, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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and manufacture of development systems is ISO 9001:2000 certified.
DS39935C-page ii
2010 Microchip Technology Inc.
ENC424J600/624J600
Stand-Alone 10/100 Ethernet Controller
with SPI or Parallel Interface
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEEE 802.3™ Compliant Fast Ethernet Controller
Integrated MAC and 10/100Base-T PHY
Hardware Security Acceleration Engines
24-Kbyte Transmit/Receive Packet Buffer SRAM
Supports one 10/100Base-T Port with Automatic
Polarity Detection and Correction
Supports Auto-Negotiation
Support for Pause Control Frames, including
Automatic Transmit and Receive Flow Control
Supports Half and Full-Duplex Operation
Programmable Automatic Retransmit on Collision
Programmable Padding and CRC Generation
Programmable Automatic Rejection of Erroneous
and Runt Packets
Factory Preprogrammed Unique MAC Address
MAC:
- Support for Unicast, Multicast and Broadcast
packets
- Supports promiscuous reception
- Programmable pattern matching
- Programmable filtering on multiple packet
formats, including Magic Packet™, Unicast,
Multicast, Broadcast, specific packet match,
destination address hash match or any packet
PHY:
- Wave shaping output filter
- Internal Loopback mode
- Energy Detect Power-Down mode
Available MCU Interfaces:
- 14 Mbit/s SPI interface with enhanced set of
opcodes (44-pin and 64-pin packages)
- 8-bit multiplexed parallel interface
(44-pin and 64-pin packages)
- 8-bit or 16-bit multiplexed or demultiplexed
parallel interface (64-pin package only)
• Security Engines:
- High-performance, modular exponentiation
engine with up to 1024-bit operands
- Supports RSA® and Diffie-Hellman key
exchange algorithms
- High-performance AES encrypt/decrypt
engine with 128-bit, 192-bit or 256-bit key
- Hardware AES ECB, CBC, CFB and OFB
mode capability
- Software AES CTR mode capability
- Fast MD5 hash computations
- Fast SHA-1 hash computations
• Buffer:
- Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- 8-bit or 16-bit random and sequential access
- High-performance internal DMA for fast
memory copying
- High-performance hardware IP checksum
calculations
- Accessible in low-power modes
- Space can be reserved for general purpose
application usage in addition to transmit and
receive packets
• Operational:
- Outputs for two LED indicators with support
for single and dual LED configurations
- Transmit and receive interrupts
- 25 MHz clock
- 5V tolerant inputs
- Clock out pin with programmable frequencies
from 50 kHz to 33.3 MHz
- Operating voltage range of 3.0V to 3.6V
- Temperature range: -40°C to +85°C industrial
• Available in 44-Pin (TQFP and QFN) and 64-Pin
TQFP Packages
Security
8-Bit
16-Bit
Demultiplexed
SRAM
(bytes)
16-Bit
Multiplexed
Device
8-Bit
Pin
Speed
Count (Mbps)
PSP
ENC424J600
24K
44
10/100
Y
Y
Y
Y
Y
N
N
N
ENC624J600
24K
64
10/100
Y
Y
Y
Y
Y
Y
Y
Y
2010 Microchip Technology Inc.
ModEx
MD5
AES
1024-Bit SHA-1 256-Bit
SPI
DS39935C-page 1
ENC424J600/624J600
Pin Diagrams
VSS
PSPCFG0
AD14
AD13
AD12
AD11
AD10
AD9
AD8
INT/SPISEL
CLKOUT
44-Pin TQFP and QFN
33 32 31 30 29 28 27 26 25 24 23
CS/CS
SO/WR/EN
SI/RD/RW
SCK/AL
AD0
AD1
AD2
AD3
VSS
VCAP
VDD
34
35
36
37
38
39
40
41
42
43
44
ENC424J600
22
21
20
19
18
17
16
15
14
13
12
VSSTX
TPOUTTPOUT+
VSSTX
VDDTX
TPINTPIN+
VDDRX
VSSRX
VSSPLL
VDDPLL
VSSOSC
OSC2
OSC1
VDDOSC
AD4
AD5
AD6
AD7
LEDB
LEDA
RBIAS
1 2 3 4 5 6 7 8 9 10 11
DS39935C-page 2
2010 Microchip Technology Inc.
ENC424J600/624J600
Pin Diagrams (Continued)
CLKOUT
INT/SPISEL
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
A12
A14/PSPCFG1
A13
VSS
VDD
WRH/B1SEL
64-Pin TQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
CS/CS
SO/WR/WRL/EN/B0SEL
49
32
VSSTX
50
31
TPOUT-
SI/RD/RW
51
30
TPOUT+
SCK/AL/PSPCFG4
AD0
52
29
53
28
AD1
AD2
54
27
VSSTX
VDDTX
TPIN-
55
26
TPIN+
AD3
56
25
A0
57
A1
A2
A3
58
23
VDDRX
VSSRX
VSSPLL
59
22
VDDPLL
60
21
VDD
A4
VSS
61
20
62
19
A11
A10
VCAP
VDD
63
18
64
17
2010 Microchip Technology Inc.
AD7
RBIAS
AD6
LEDA
AD5
PSPCFG3
PSPCFG2
9 10 11 12 13 14 15 16
LEDB
8
A9
7
24
A8
6
A7
5
A6
4
AD4
2
A5
3
VDDOSC
VSSOSC
1
OSC2
OSC1
ENC624J600
DS39935C-page 3
ENC424J600/624J600
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 External Connections ................................................................................................................................................................... 9
3.0 Memory Organization ................................................................................................................................................................. 17
4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 39
5.0 Parallel Slave Port Interface (PSP) ............................................................................................................................................ 51
6.0 Ethernet Overview ...................................................................................................................................................................... 71
7.0 Reset .......................................................................................................................................................................................... 73
8.0 Initialization................................................................................................................................................................................. 75
9.0 Transmitting and Receiving Packets .......................................................................................................................................... 83
10.0 Receive Filters............................................................................................................................................................................ 95
11.0 Flow Control ............................................................................................................................................................................. 105
12.0 Speed/Duplex Configuration and Auto-Negotiation.................................................................................................................. 109
13.0 Interrupts .................................................................................................................................................................................. 117
14.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 123
15.0 Cryptographic Security Engines ............................................................................................................................................... 125
16.0 Power-Saving Features ............................................................................................................................................................ 137
17.0 Electrical Characteristics .......................................................................................................................................................... 141
18.0 Packaging Information.............................................................................................................................................................. 149
Appendix A: Revision History............................................................................................................................................................. 157
Index .................................................................................................................................................................................................. 159
The Microchip Web Site ..................................................................................................................................................................... 163
Customer Change Notification Service .............................................................................................................................................. 163
Customer Support .............................................................................................................................................................................. 163
Reader Response .............................................................................................................................................................................. 164
Product Identification System............................................................................................................................................................. 165
TO OUR VALUED CUSTOMERS
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DS39935C-page 4
2010 Microchip Technology Inc.
ENC424J600/624J600
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• ENC424J600
• ENC624J600
Communication
with
the
microcontroller
is
implemented via the SPI or parallel interface, with data
rates ranging from 14 Mbit/s (SPI) to 160 Mbit/s
(demultiplexed, 16-bit parallel interface). Dedicated
pins are used for LED link and activity indication and for
transmit/receive/DMA interrupts.
The ENC424J600 and ENC624J600 are stand-alone,
Fast Ethernet controllers with an industry standard
Serial Peripheral Interface (SPI) or a flexible parallel
interface. They are designed to serve as an Ethernet
network interface for any microcontroller equipped with
SPI or a standard parallel port.
A generous 24-Kbyte on-chip RAM buffer is available
for TX and RX operations. It may also be used by the
host microcontroller for general purpose storage.
Communication protocols, such as TCP, can use this
memory for saving data which may need to be
retransmitted.
ENC424J600/624J600 devices meet all of the
IEEE 802.3 specifications applicable to 10Base-T and
100Base-TX Ethernet, including many optional
clauses, such as auto-negotiation. They incorporate a
number of packet filtering schemes to limit incoming
packets. They also provide an internal, 16-bit wide
DMA for fast data throughput and support for hardware
IP checksum calculations.
For easy end product manufacturability, each
ENC624J600 family device is preprogrammed with a
unique nonvolatile MAC address. In most cases, this
allows the end device to avoid a serialized
programming step.
For applications that require the security and authentication features of SSL, TLS and other protocols related
to cryptography, a block of security engines is provided.
The engines perform RSA, Diffie-Hellman, AES, MD5
and SHA-1 algorithm computations, allowing reduced
code size, faster connection establishment and
throughput, and reduced firmware development effort.
TABLE 1-1:
The only functional difference between the
ENC424J600 (44-pin) and ENC624J600 (64-pin)
devices are the number of parallel interface options
they support. These differences, along with a summary
of their common features, are provided in Table 1-1. A
general block diagram for the devices is shown in
Figure 1-1.
A list of the pin features, sorted by function, is
presented in Table 1-2.
DEVICE FEATURES FOR ENC424J600/624J600
Feature
Pin Count
Ethernet Operating Speed
Ethernet Duplex Modes
Ethernet Flow Control
Buffer Memory (bytes)
Internal Interrupt Sources
Serial Host Interface (SPI)
ENC424J600
ENC624J600
44
64
10/100 Mbps (auto-negotiate, auto-sense or manual)
Half and Full (auto-negotiate and manual)
Pause and Backpressure (auto and manual)
24K (organized as 12K word x 16)
11 (mappable to a single external interrupt flag)
Yes
Yes
Parallel Host Interface:
Operating modes
2
8
8-bit
Yes
Yes
16-bit
No
Yes
No
Yes
No
Yes
AES, 128/192/256-bit
Yes
Yes
MD5/SHA-1
Yes
Yes
Modular Exponentiation, 1024-bit
Yes
Yes
Muliplexed,
Demultiplexed, 8-bit
16-bit
Cryptographic Security Options:
Receive Filter Options
Packages
2010 Microchip Technology Inc.
Accept or reject packets with CRC match/mismatch, runt error collect
or reject, Unicast, Not-Me Unicast, Multicast, Broadcast,
Magic Packet™, Pattern Table and Hash Table
44-Pin TQFP, QFN
64-Pin TQFP
DS39935C-page 5
ENC424J600/624J600
FIGURE 1-1:
ENC424J600/624J600 BLOCK DIAGRAM
Bus
Interface
CS/CS
SCK/AL
SI/RD/RW
m3
m0
m1
PHY
TPOUT+
DMA and
Checksum
MII
Interface
TX
TPOUT-
TPIN+
RX
TPINm2
Parallel
WR/WRL/
EN/B0SEL(1)
MAC
Crypto Cores
AD(1)
A(1)
RX Control
Logic
RX Filter
Common
SO
Arbiter
SPI
I/O
Interface
TX Control
Logic
Flow Control
Memory
WRH/
B1SEL(1)
Control
Registers
SRAM
24 Kbytes
MIIM
Interface
RBIAS
Host Interface
PSPCFGx(1)
SPISEL
25 MHz
Oscillator
Control Logic
INT
Note 1:
LEDA LEDB
Power-on
Reset
PLL
Voltage
Regulator
CLKOUT
VCAP
OSC1
OSC2
A, AD15, WRL/B0SEL, WRH/B1SEL and PSPCFG are available on 64-pin devices only. PSPCFG0 is available on 44-pin
devices only.
DS39935C-page 6
2010 Microchip Technology Inc.
ENC424J600/624J600
TABLE 1-2:
ENC424J600/624J600 PINOUT DESCRIPTIONS
Pin Number
Pin Type
Input
Buffer
53
I/O
CMOS
39
54
I/O
CMOS
40
55
I/O
CMOS
AD3
41
56
I/O
CMOS
AD4
5
5
I/O
CMOS
AD5
6
6
I/O
CMOS
AD6
7
7
I/O
CMOS
Pin Name
44-Pin
64-Pin
AD0
38
AD1
AD2
AD7
8
8
I/O
CMOS
AD8
25
35
I/O
CMOS
AD9
26
36
I/O
CMOS
AD10
27
37
I/O
CMOS
AD11
28
38
I/O
CMOS
AD12
29
39
I/O
CMOS
AD13
30
40
I/O
CMOS
AD14
31
41
I/O
CMOS
AD15
—
42
I/O
CMOS
A0
—
57
I
CMOS
A1
—
58
I
CMOS
A2
—
59
I
CMOS
A3
—
60
I
CMOS
A4
—
61
I
CMOS
Description
PSP Multiplexed Address Input and/or Bidirectional
Data Bus
PSP Demultiplexed Address Input Bus
A5
—
9
I
CMOS
A6
—
10
I
CMOS
A7
—
11
I
CMOS
A8
—
12
I
CMOS
A9
—
13
I
CMOS
A10
—
19
I
CMOS
A11
—
20
I
CMOS
A12
—
43
I
CMOS
A13
—
44
I
CMOS
A14
—
45
I
CMOS
AL
37
52
I
CMOS
PSP Address Latch
B0SEL
—
50
I
CMOS
PSP Byte 0 Select
B1SEL
—
48
I
CMOS
CLKOUT
23
33
O
—
CS
34
49
I
CMOS
PSP Byte 1 Select
Programmable Clock Output for External Use
SPI Chip Select (active-low)
CS
34
49
I
CMOS
PSP Chip Select (active-high)
EN
35
50
I
CMOS
PSP R/W Enable strobe
INT
24
34
O
—
Interrupt Output (active-low)
LEDA
10
15
O
—
Programmable Ethernet Status/Activity LED
LEDB
9
14
O
—
Programmable Ethernet Status/Activity LED
Legend: I = Input; O = Output; P = Power; CMOS = CMOS compatible input buffer; ANA = Analog level input/output
2010 Microchip Technology Inc.
DS39935C-page 7
ENC424J600/624J600
TABLE 1-2:
Pin Name
ENC424J600/624J600 PINOUT DESCRIPTIONS (CONTINUED)
Pin Number
Pin Type
Input
Buffer
ANA
44-Pin
64-Pin
3
3
I
OSC1
Description
25 MHz Crystal Oscillator/Clock Input
OSC2
2
2
O
—
PSPCFG0
32
—
I
CMOS
PSP Mode Select 0
PSPCFG1
—
45
I
CMOS
PSP Mode Select 1
PSPCFG2
—
17
I
CMOS
PSP Mode Select 2
PSPCFG3
—
18
I
CMOS
PSP Mode Select 3
PSPCFG4
—
52
I
CMOS
PSP Mode Select 4
RBIAS
11
16
I
ANA
RD
36
51
I
CMOS
PSP Read Strobe
RW
36
51
I
CMOS
PSP Combined Read/Write Signal
SCK
37
52
I
CMOS
SPI Serial Clock Input
SI
36
51
I
CMOS
SO
35
50
O
—
SPISEL
24
34
I
CMOS
TPIN-
17
27
I
ANA
25 MHz Crystal Oscillator Output
PHY Bias (external resistor) Connection
SPI Serial Data Input (from Master)
SPI Serial Data Out (to Master)
SPI/PSP Interface Select
Differential Ethernet Receive Minus Signal Input
TPIN+
16
26
I
ANA
TPOUT-
21
31
O
—
Differential Ethernet Transmit Minus Signal Output
Differential Ethernet Receive Plus Signal Input
TPOUT+
20
30
O
—
Differential Ethernet Transmit Plus Signal Output
VCAP
43
63
P
—
Regulator External Capacitor connection
VDD
44
21, 47,
64
P
—
Positive 3.3V Power Supply for Digital Logic
VDDOSC
4
4
P
—
Positive 3.3V Power Supply for 25 MHz Oscillator
VDDPLL
12
22
P
—
Positive 3.3V Power Supply for PHY PLL Circuitry
VDDRX
15
25
P
—
Positive 3.3V Power Supply for PHY RX Circuitry
18
28
P
—
Positive 3.3V Power Supply for PHY TX Circuitry
33, 42
46, 62
P
—
Ground Reference for Digital Logic
VDDTX
VSS
VSSOSC
1
1
P
—
Ground Reference for 25 MHz Oscillator
VSSPLL
13
23
P
—
Ground Reference for PHY PLL Circuitry
VSSRX
14
24
P
—
Ground Reference for PHY RX Circuitry
VSSTX
19, 22
29, 32
P
—
Ground Reference for PHY TX Circuitry
WR
35
50
I
CMOS
PSP Write Strobe
WRH
—
48
I
CMOS
PSP Write High Strobe
WRL
—
50
I
CMOS
PSP Write Low Strobe
Legend: I = Input; O = Output; P = Power; CMOS = CMOS compatible input buffer; ANA = Analog level input/output
DS39935C-page 8
2010 Microchip Technology Inc.
ENC424J600/624J600
2.0
EXTERNAL CONNECTIONS
2.1
Oscillator
When clocking the device using a crystal, follow the
connections shown in Figure 2-1. When using a CMOS
clock oscillator or other external clock source, follow
Figure 2-2.
CRYSTAL OSCILLATOR
OPERATION
ENCX24J600
C1
(3)
OSC1
To Internal Logic
XTAL
RF(2)
C2(3)
EXTERNAL CLOCK
SOURCE
ENCX24J600
ENC424J600/624J600 devices are designed to
operate from a fixed 25 MHz clock input. This clock can
be generated by an external CMOS clock oscillator or
a parallel resonant, fundamental mode 25 MHz crystal
attached to the OSC1 and OSC2 pins. Use of a crystal,
rated for series resonant operation, will oscillate at an
incorrect frequency. To comply with IEEE 802.3 Ethernet
timing requirements, the clock must have no more than
±50 ppm of total error; avoid using resonators or clock
generators that exceed this margin.
FIGURE 2-1:
FIGURE 2-2:
RS(1)
OSC2
Note 1:
A series resistor, RS, may be required for
crystals with a low drive strength specification
or when using large loading capacitors.
2:
The feedback resistor, RF , is typically 1.5 M
approx.
3:
The load capacitors’ value should be derived
from the capacitive loading specification
provided by the crystal manufacture.
2010 Microchip Technology Inc.
3.3V Clock from
External System(1)
OSC1
Open
OSC2
Note 1:
2.2
Duty cycle restrictions must be observed.
CLKOUT Pin
The Clock Out pin (CLKOUT) is provided for use as the
host controller clock or as a clock source for other
devices in the system. Its use is optional.
The 25 MHz clock applied to OSC1 is multiplied by a
PLL to internally generate a 100 MHz base clock. This
100 MHz clock is driven through a configurable
postscaler to yield a wide range of different CLKOUT
frequencies. The PLL multiplication adds clock jitter,
subject to the PLL jitter specification in Section 17.0
“Electrical Characteristics”. However, the postscaler
ensures that the clock will have a nearly ideal duty
cycle.
The CLKOUT function is enabled and the postscaler is
selected via the COCON bits (ECON2).
To create a clean clock signal, the CLKOUT output and
COCON bits are unaffected by all resets and
power-down modes. The CLKOUT function is enabled
out of POR and defaults to producing a 4 MHz clock.
This allows the device to directly clock the host
processor.
When the COCON bits are written with a new
configuration, the CLKOUT output transitions to the
new frequency without producing any glitches. No high
or low pulses with a shorter period than the original or
new clock are generated.
DS39935C-page 9
ENC424J600/624J600
2.3
2.3.1
Voltage and Bias Pin
FIGURE 2-3:
VDD AND VSS PINS
3.3V
To reduce on-die noise levels and provide for the
high-current demands of Ethernet, there are many
power pins on ENC424J600/624J600 devices:
•
•
•
•
•
VDD and VSS
VDDOSC and VSSOSC
VDDPLL and VSSPLL
VDDRX and VSSRX
VDDTX and VSSTX
Each VDD and VSS pin pair above should have a 0.1 F
ceramic bypass capacitor placed as close to the pins as
possible. For best EMI emission suppression, other
smaller capacitors, such as 0.001 F, should be placed
immediately across VDDTX/VSSTX and VDDPLL/VSSPLL.
All VDD power supply pins must be externally connected to the same 3.3V ±10% power source. Similarly,
all VSS supply references must be externally connected
to the same ground node. If a ground connection
appears on two pins (e.g., VSSTX), connect both pins;
do not allow either to float. In addition, it is
recommended that the exposed bottom metal pad on
the 44-pin QFN package be tied to VSS.
Placing ferrite beads or inductors between any two of
the supply pins (e.g., between VDDOSC and VDDRX) is
not recommended. However, it is acceptable to isolate
all of the VDD supplies from the main circuit power supply through a single ferrite bead or inductor, if desired
for supply noise suppression reasons. Such isolation is
generally not necessary.
2.3.2
VCAP PIN
Most of the device’s digital logic operates at a nominal
1.8V. This voltage is supplied by an on-chip voltage
regulator, which generates the digital supply voltage
from the VDD rail. The only external component
required is an external filter capacitor, connected from
the VCAP pin to ground, as shown in Figure 2-3. A value
of at least 10 F is recommended.
VCAP CONNECTIONS
ENCX24J600
+3.3V
VDD
I/O, PHY
Regulator
VCAP
0.1 F
10 F
2.3.3
+1.8V
Core, RAM,
MAC
VSS
RBIAS PIN
The internal analog circuitry in the PHY module
requires that an external 12.4 kΩ, 1% resistor be
attached from RBIAS to ground, as shown in
Figure 2-4. The resistor influences the TPOUT+/signal amplitude. The RBIAS resistor should be placed
as close as possible to the chip with no immediately
adjacent signal traces in order to prevent noise
capacitively coupling into the pin and affecting the
transmit behavior. It is recommended that the resistor
be a surface mount type.
FIGURE 2-4:
RBIAS RESISTOR
ENCX24J600
PHY
RBIAS
12.4k1%
The capacitor must also have a relatively low Equivalent Series Resistance (ESR). It is recommended that
a low-ESR capacitor (ceramic, tantalum or similar)
should be used and high-ESR capacitors (such as
aluminum electrolytic) should be avoided.
The internal regulator is not designed to drive external
loads; therefore, do not attach other circuitry to VCAP.
DS39935C-page 10
2010 Microchip Technology Inc.
ENC424J600/624J600
2.4
Ethernet Signal Pins and External
Magnetics
Typical applications for ENC424J600/624J600 devices
require an Ethernet transformer module, and a few
resistors and capacitors to implement a complete
IEEE 802.3 compliant 10/100 Ethernet interface, as
shown in Figure 2-5.
The Ethernet transmit interface consists of two pins:
TPOUT+ and TPOUT-. These pins implement a
differential pair and a current-mode transmitter. To
generate an Ethernet waveform, ordinary applications
require the use of a 1:1 center tapped pulse
transformer, rated for 10/100 or 10/100/1000 Ethernet
operations. When the Ethernet module is enabled and
linked with a partner, current is continually sunk
through both TPOUT pins. When the PHY is actively
transmitting, a differential voltage is created on the
Ethernet cable by varying the relative current sunk by
TPOUT+ compared to TPOUT-.
The Ethernet receive interface similarly consists of a
differential pair: TPIN+ and TPIN-. To meet IEEE 802.3
compliance and help protect against electrostatic discharge, these pins are normally isolated from the
Ethernet cable by a 1:1 center tapped transformer
(available in the same package as the TX transformer).
Internally, the PHY uses a high-speed ADC to sample
the receive waveform and decodes it using a DSP. The
PHY implements many robustness features, including
FIGURE 2-5:
baseline wander correction (applicable to 100Base-TX)
and automatic RX polarity correction (applicable to
10Base-T).
Four 49.9Ω, 1% resistors are required for proper
termination of the TX and RX transmission lines. If the
board layout necessitates long traces between the
ENCX24J600 and Ethernet transformers, the termination resistors should be placed next to the silicon
instead of the transformers.
On the receive signal path, two 6.8 nF 10% capacitors
are used. These capacitors, in combination with the
49.9 termination resistors, form an RC high-pass filter
to reduce baseline wander. For best performance,
these capacitors should not be omitted or changed.
The various remaining capacitors provide DC current
blocking and provide stability to the common-mode
voltage of both of the differential pairs. The TPIN+/pins weakly output a common-mode voltage that is
acceptable to the internal ADC. For proper operation,
do not attempt to externally force the TPIN+/common-mode voltage to some other value.
The 10Ω 1% resistor provides a current path from the
power supply to the center tap of the TX transformer.
As mentioned previously, the TPOUT+/- pins
implement a Current mode drive topology in which the
pins are only capable of sinking current; they do not
produce a direct voltage. This current path through the
transformer generates the transmit waveform. The 10Ω
resistor reduces the amount of heat that the PHY would
have to dissipate, and therefore, must have a power
rating of 1/12W or better.
TYPICAL ETHERNET MAGNETICS CONNECTIONS
3.3V
1
10, 1/12W, 1%
ENCX24J600
RJ-45
TPOUT+
1
49.9, 1%
49.9, 1%
TPOUT-
6.8 nF, 10%
TPIN+
2
0.01 F
3
1:1 CT
4
49.9, 1%
49.9, 1%
TPIN-
5
6.8 nF, 10%
1:1 CT
6
7
0.01 F
8
75
75
75
75
1000 pF, 2 kV
2010 Microchip Technology Inc.
DS39935C-page 11
ENC424J600/624J600
2.4.1
ADDITIONAL EMI AND LAYOUT
CONSIDERATIONS
To reduce EMI emissions, common-mode chokes are
shown adjacent to the transformers on the cable
(RJ-45) side. These chokes come standard in typical
Ethernet transformer modules. Because the
ENCX24J600 PHY uses a current-mode drive topology, the transmit choke must normally be located on
the cable side of the transmit transformer. Orienting the
magnetics such that the choke is on the PHY side of the
transmit transformer usually results in a distorted,
non-compliant transmit waveform. However, some
magnetics which wrap the TX center tap wire around
the TX choke core can also be used to generate a
compliant waveform (Figure 2-6). These types of transformers may be desirable in some Power-over Ethernet
(PoE) applications.
FIGURE 2-6:
By default on POR, LEDA displays the Ethernet link
status, while LEDB displays PHY-level TX/RX activity.
Because the LEDs operate at the PHY level, RX
activity will be displayed on LEDB any time Ethernet
packets are detected, regardless of if the packet is valid
and meets the correct RX filtering criteria.
Normally, the device illuminates the LED by sourcing
current out of the pin, as shown in Figure 2-7. Connecting the LED in reverse, with the anode connected to
VDD and the cathode to LEDA/LEDB (through a
current-limiting resistor), causes the LED to show
“inverted sense” behavior, lighting the LED when it
should be off and extinguishing the LED when the LED
should be on.
FIGURE 2-7:
ALTERNATE TX CHOKE
TOPOLOGY
PHY
LEDA
or
LEDB
SINGLE COLOR LED
CONNECTION
180
LED
RJ-45
1:1 CT
The common-mode choke on the RX interface can be
placed on either the cable side or PHY side of the
receive transformer. Recommended and required magnetics characteristics are located in Section 17.0
“Electrical Characteristics”.
Both LEDs automatically begin operation whenever
power is applied, a 25 MHz clock is present and the
Ethernet magnetics are present and wired correctly. A
connection to the host microcontroller via the SPI or
PSP interface is not required. LEDA and LEDB can,
therefore, be used as a quick indicator of successful
assembly during initial prototype development.
2.5.1
USING BI-COLOR LEDs
The four 75Ω resistors and high-voltage capacitor in
Figure 2-5 are intended to prevent each of the twisted
pairs in the Ethernet cables from floating and radiating
EMI. Their implementation may require adjustment in
PoE applications.
In space constrained applications, it is frequently desirable to use a single bi-color LED to display multiple
operating parameters. These LEDs are connected
between LEDA and LEDB, as shown in Figure 2-8.
Unless the TX and RX signal pairs are kept short, they
should be routed between the ENCX24J600 and the
Ethernet connector following differential routing rules.
Like Ethernet cables, 100Ω characteristic impedance
should be targeted for the differential traces. The use of
vias, which introduce impedance discontinuities,
should be minimized. Other board level signals should
not run immediately parallel to the TX and RX pairs to
minimize capacitive coupling and crosstalk.
FIGURE 2-8:
2.5
LEDA and LEDB Pins
The LEDA and LEDB pins provide dedicated LED
status indicator outputs. The LEDs are intended to
display link status and TX/RX activity among other
programmable options; however, the use of one or both
is entirely optional. The pins are driven automatically by
the hardware and require no support from the host
microcontroller. Aside from the LEDs themselves, a
current-limiting resistor is generally the only required
component.
DS39935C-page 12
LEDA
BI-COLOR LED
CONNECTION
180
Bi-Color
LED
LEDB
ENCX24J600 devices include two special hardware
display modes to make maximal use of a bi-color LED.
These modes are selected when the LACFG and
LBCFG bits (EIDLED) are set to ‘1111’ or
‘1110’. In these configurations, the link state turns the
LED on, the speed/duplex state sets the LED color and
TX/RX events cause the LED to blink off. If a link is
present, no TX/RX events are occurring and the
speed/duplex state is 100 Mbps/full duplex,
respectively, then the LEDB pin will be driven high while
LEDA will be driven low.
2010 Microchip Technology Inc.
ENC424J600/624J600
2.6
INT Pin
The INT pin is an active-low signal that is used to flag
interrupt events to external devices. Depending on the
application, it can be used to signal the host microcontroller whenever a packet has been received or
transmitted, or that some other asynchronous
operation has occurred. It can also be used to wake-up
the microcontroller or other system components based
on LAN activity; its use is optional.
The INT pin is driven high when no interrupt is pending
and is driven low when an interrupt has occurred. It
does not go into a high-impedance state, except during
initial power-on while the multiplexed SPISEL pin
function is being used.
Since ENC424J600/624J600 devices incorporate a
buffer for storing transmit and receive packets, the host
microcontroller never needs to perform real-time
operations on the device. The microcontroller can poll
the device registers to discover if the device status has
changed.
2.7
Host Interface Pins
For the maximum degree of flexibility in interfacing with
microcontrollers, ENC424J600/624J600 devices offer
a choice between a serial interface based on the Serial
Peripheral Interface (SPI) standard, and a flexible 8 or
16-bit parallel slave port (PSP) interface. Only one
interface may be used at any given time.
The I/O interface is hardware selected on power-up
using the SPISEL function on the INT/SPISEL pin. This
is done by latching in the voltage level applied to the pin
FIGURE 2-9:
To ensure the SPI interface is selected upon power-up,
an external pull-up resistor to VDD must be connected
to the SPISEL pin. Alternatively, if the parallel interface
is to be used, a pull-down resistor to VSS must be
connected to the SPISEL pin. In most circuits, it is recommended that a 100 kΩ or smaller resistor be used to
ensure that the correct logic level is latched in reliably.
If a large capacitance is present in the SPISEL circuit,
such as from stray capacitance, a smaller pull-up or
pull-down resistor may be required to compensate and
ensure the correct level is sensed during power-up.
As SPISEL is multiplexed with the INT interrupt output
function, a direct connection to VDD or VSS without a
resistor is prohibited. If INT is connected to the host
microcontroller, the microcontroller must leave this
signal in a high-impedance state and not attempt to
drive it to an incorrect logic state during power-up.
If the VDD supply has a slow ramp rate, the device will
exit POR, exceed the 1 to 10 s latch timer and sample
the SPISEL pin state before VDD has reached the specified minimum operating voltage of the device. In this
case, the device will still latch in the correct value,
assuming the minimum VIH (D004) or maximum VIL
(D006) specification is met, which is a function of VDD.
USING THE INT/SPISEL PIN TO SELECT THE I/O INTERFACE
3.3V
MCU
approximately 1 to 10 s after power is applied to the
device and the device exits Power-on Reset. If SPISEL
is latched at a logic high state, the serial interface is
enabled. If SPISEL is latched at a logic low state, the
PSP interface is enabled. Figure 2-9 shows example
connections required to select the SPI or PSP interface
upon power-up.
ENCX24J600
~2.2V
100k
INT0
I/O
SCK
SDO
SDI
INT/SPISEL
CS
ENCX24J600
MCU
PMALL
AL
PMCS2
CS
RMRD
RD
PMWR
WR
PMAx/PMDx
ADx
SCK
SI
SO
VSS
INT/SPISEL
INT0
100k
SPI Selected
(internal weak pull-up on CS enabled)
2010 Microchip Technology Inc.
PSP Selected (Mode 5 shown)
(internal weak pull-down on CS enabled)
DS39935C-page 13
ENC424J600/624J600
2.7.1
SPI
parallel interfaces; not all available pins are used in
every configuration. Up to 8 different operating modes
are available. These are explained in detail in
Section 5.0 “Parallel Slave Port Interface (PSP)”.
When enabled, the SPI interface is implemented with
four pins:
•
•
•
•
CS
SO
SI
SCK
All four of these pins must be connected to use the SPI
interface.
The PSPCFG pins control which parallel interface
mode is used. The values on these pins are latched
upon device power-up in the same manner as the
SPISEL pin. The combinations of VDD and VSS voltages on the different PSPCFG mode pins determine
the PSP mode according to Table 2-1.
The CS, SI and SCK input pins are 5V tolerant. The SO
pin is also 5V tolerant when in a high-impedance state.
SO is always high-impedance when CS is connected to
logic high (i.e., chip not selected).
On ENC424J600 devices, only PSP Modes 5 and 6
(8-bit width, multiplexed data and address) are
available. The mode is selected by applying VSS or
VDD, respectively, to PSPCFG0.
When the SPI interface is enabled, all PSP interface
pins (except PSPCFG2 and PSPCFG3 on
ENC624J600 devices) are unused. They are placed in
a high-impedance state and their input buffers are disabled. For best ESD performance, it is recommended
that the unused PSP pins be tied to either VSS or VDD.
However, these pins may be left floating if it is desirable
for board level layout and routing reasons.
On ENC624J600 devices, all eight PSP modes are
available and are selected by connecting the
PSPCFG pins directly to VDD or ground. The
mode selection is encoded such that the multiplexed
pin functions, AD14 (on PSPCFG1) and SCK/AL (on
PSPCFG4), are used only in the “don’t care” positions.
Therefore, pull-up/pull-down resistors are not required
for these pins.
When using an ENC624J600 device in SPI mode, it is
recommended that the PSPCFG2 and PSPCFG3 pins
be tied to either VSS or any logic high voltage, and not
be left floating. The particular state used is unimportant.
All PSP pins, except for AD, are inputs to the
ENC624J600 family device and are 5V tolerant. The
AD pins are bidirectional I/Os and are 5V
tolerant in Input mode. The pins are always inputs
when the CS signal is low (chip not selected).
2.7.2
Any unused PSP pins are placed in a high-impedance
state. However, it is recommended that they be tied to
either Vss or a logic high voltage and not be left floating.
PSP
Depending on the particular device, the PSP interface
is implemented with up to 34 pins. The interface is
highly configurable to accommodate many different
TABLE 2-1:
Interface
Mode
PSP MODE SELECTION FOR ENC424J600/624J600 DEVICES
PSPCFG
Pins Used
INT/SPISEL
0
1
2
3
4
44-Pin
PSP Mode 5
Pull Down
0
—
—
—
—
AL, CS, RD, WR, AD
PSP Mode 6
Pull Down
1
—
—
—
—
AL, CS, RW, EN, AD
PSP Mode 1
Pull Down
—
x
0
0
64-Pin
0
CS, RD, WR, A14:A0, AD
PSP Mode 2
Pull Down
—
x
0
0
1
CS, RW, EN, A14:A0, AD
PSP Mode 3
Pull Down
—
x
1
0
0
CS, RD, WRL, WRH, A, AD
PSP Mode 4
Pull Down
—
x
1
0
1
CS, RW, B0SEL, B1SEL, A, AD
PSP Mode 5
Pull Down
—
0
0
1
x
AL, CS, RD, WR, AD
PSP Mode 6
Pull Down
—
1
0
1
x
AL, CS, RW, EN, AD
PSP Mode 9
Pull Down
—
0
1
1
x
AL, CS, RD, WRL, WRH, AD
PSP Mode 10
Pull Down
—
1
1
1
x
AL, CS, RW, B0SEL, B1SEL, AD
Legend: x = don’t care, 0 = logic low (tied to VSS), 1 = logic high (tied to VDD), — = pin not present
DS39935C-page 14
2010 Microchip Technology Inc.
ENC424J600/624J600
2.7.3
CS/CS PIN
The chip select functions for the serial and parallel
interfaces are shared on one common pin, CS/CS. This
pin is equipped with both internal weak pull-up and
weak pull-down resistors. If the SPI interface is
selected (CS), the pull-up resistor is automatically
enabled and the pull-down resistor is disabled. If the
PSP interface is chosen (CS), the pull-down resistor is
automatically enabled and the pull-up resistor is
disabled. This allows the CS/CS pin to stay in the
unselected state when not being driven, avoiding the
need for an external board level resistor on this pin.
When enabled by using SPI mode, the internal weak
pull-up only pulls the CS/CS pin up to approximately
VDD-1.1V or around 2.2V at typical conditions without
any loading; it does not pull all the way to VDD. When
using the PSP interface, the pull-down will be enabled,
which is capable of pulling all the way to VSS when
unloaded.
2.8
FIGURE 2-10:
LEVEL SHIFTING ON THE
SPI INTERFACE USING
AND GATES
3.3V
100k
MCU
ENCX24J600
INT/SPISEL
INTx
CLKOUT
OSC1
SDI
SO
I/O
CS
SCK
SCK
SDO
SI
Digital I/O Levels
All digital output pins on ENC424J600/624J600
devices contain CMOS output drivers that are capable
of sinking and sourcing up to 18 mA continuously. All
digital inputs and I/O pins operating as inputs are 5V
tolerant. These features generally mean that the
ENCX24J600 can connect directly to the host
microcontroller without the need of any glue logic.
However, some consideration may be necessary when
interfacing with 5V systems.
Since the digital outputs drive only up to the VDD
voltage (3.3V nominally), the voltage may not be high
enough to ensure a logical high is detected by 5V
systems which have high input thresholds. In such
cases, unidirectional level translation from the 3.3V
ENCX24J600 up to the 5V host microcontroller may be
needed.
FIGURE 2-11:
LEVEL SHIFTING ON THE
SPI INTERFACE USING
3-STATE BUFFERS
3.3V
100k
MCU
INTx
OSC1
SDI
I/O
ENCX24J600
INT/SPISEL
CLKOUT
SO
CS
SCK
SCK
SDO
SI
When using the SPI interface, an economical 74HCT08
(quad AND gate), 74ACT125 (quad 3-state buffer) or
other 5V CMOS chip with TTL level input buffers may
be used to provide the necessary level shifting. The
use of 3-state buffers permits easy integration into
systems which share the SPI bus with other devices.
However, users must make certain that the propagation delay of the level translator does not reduce the
maximum SPI frequency below desired levels.
Figure 2-10 and Figure 2-11 show two example
translation schemes.
When using the PSP interface, eight, or all sixteen of
the ADx pins, may need level translation when performing read operations on the ENCX24J600. The 8-bit
74ACT245 or 16-bit 74ACT16245 bus transceiver, or
similar devices, may be useful in these situations.
2010 Microchip Technology Inc.
DS39935C-page 15
ENC424J600/624J600
NOTES:
DS39935C-page 16
2010 Microchip Technology Inc.
ENC424J600/624J600
3.0
MEMORY ORGANIZATION
3.1.1
SPI INTERFACE MAP
All memory in ENC424J600/624J600 devices is
implemented as volatile RAM. Functionally, there are
four unique memories:
When the SPI interface is selected, the device memory
map is comprised of three memory address spaces
(Figure ):
•
•
•
•
• the SFR area
• the main memory area
• the PHY register area
Special Function Registers (SFRs)
PHY Special Function Registers
Cryptographic Data Memory
SRAM Buffer
The SFRs configure, control and provide status
information for most of the device. They are directly
accessible through the I/O interface.
The PHY SFRs configure, control and provide status
information for the PHY module. They are located
inside the PHY module and isolated from all other
normal SFRs, so they are not directly accessible
through the I/O interface.
The cryptography data memory is used to store key
and data material for the modular exponentiation, AES
and MD5/SHA-1 hashing engines. This memory area
can only be accessed through the DMA module.
The SRAM buffer is a bulk 12K x 16-bit (24 Kbyte) RAM
array used for TX and RX packet buffering, as well as
general purpose storage by the host microcontroller.
Although the SRAM uses a 16-bit word, it is
byte-writable. This memory is indirectly accessible
through pointers on all I/O interfaces. It can also be
accessed directly through the PSP interfaces.
3.1
I/O Interface and Memory Map
Depending on the I/O interface selected, the four
memories are arranged into two or three different memory
address spaces. When the serial interface is selected, the
memories are grouped into three address spaces. When
one of the parallel interfaces is selected, they are
arranged into two address spaces. In all cases, the PHY
SFRs reside in their own memory address space.
FIGURE 3-1:
SFR Area
The SFR area is directly accessible to the user. This is
a linear memory space that is 160 bytes long. For
efficiency, the SFR area can be addressed as four
banks of 32 bytes each, starting at the beginning of the
space (00h), with an additional unbanked area of
32 bytes at the end of the SFR memory. Banked
addressing allows SFRs to be addressed with fewer
address bits being exchanged over the serial interface
for each transaction. This decreases protocol overhead
and enhances performance. SFRs can also be directly
addressed by their 8-bit unbanked addresses using
unbanked SPI commands. This allows for a simpler
interface whenever transaction overhead is not critical.
The main memory area is organized as a linear,
byte-addressable space of 32 Kbytes. Of this, the first
24-Kbyte area (0000h through 5FFFh) is implemented
as the SRAM buffer. The buffer is accessed by the
device using several SFRs as memory pointers and
virtual data window registers, as described in
Section 3.5.5 “Indirect SRAM Buffer Access”.
Addresses in the main memory area, between 7800h
and 7C4Fh, are mapped to the memory for the cryptographic data modules. These addresses are not
directly accessible through the SPI interface; they can
only be accessed through the DMA.
The PHY SFRs are the final memory space. This is a
linear, word-addressable memory space of 32 words.
This area is only accessible by the MIIM interface (see
Section 3.3 “PHY Special Function Registers” for
more details).
ENC424J600/624J600 MEMORY MAP WITH SPI INTERFACE
Unbanked Opcodes
Banked Opcodes
Bank 0
Bank 1
Bank 2
Bank 3
Unbanked
(inaccessible using
banked opcodes)
Pointers
00h 00h
1Fh 1Fh
00h 20h
SRAM Buffer
1Fh 3Fh
00h 40h
1Fh 5Fh
00h 60h
5FFFh
1Fh 7Fh
80h
Unimplemented
9Fh
Cryptographic Data
(DMA access only)
MIREGADR
PHY Register
Area
16-Bit, MIIM Access Only
2010 Microchip Technology Inc.
0000h
Main Area
00h
1Fh
Unimplemented
7800h
7C4Fh
7FFFh
DS39935C-page 17
ENC424J600/624J600
3.1.2
PSP INTERFACE MAPS
When one of the parallel interfaces is selected, the
memory map is very different from the SPI map. There
are two different memory address spaces (Figure 3-2):
• the main memory area
• the PHY register area
As in the serial memory map, the main memory area is
a linear, byte-addressable space of 32 Kbytes, with the
SRAM buffer located in the first 24-Kbyte region. The
cryptographic data memory is also mapped to the same
location as in the serial memory map. The main difference is that the SFRs are now located to an area with a
higher address than the cryptographic data space. Additional memory areas above the SFRs are reserved for
their accompanying Bit Set and Bit Clear registers.
Except for the cryptographic data memory, all
addresses in the main memory area are directly
accessible using the PSP bus. As with the serial interface, the cryptographic memory can only be accessed
through the DMA.
The difference between the 8-bit and 16-bit interfaces is
how the SRAM buffer is addressed by the external
address bus. In 16-bit data modes, the address bus
treats the buffer as a 16-byte wide, word-addressable
space, spanning 000h to 3FFFh. In 8-bit data modes, the
address bus treats the buffer as an 8-bit, byte-addressable space, ranging from 0000h to 7FFFh. In either case,
the SFRs used as memory pointers still address the
buffer as a byte-wide, byte-addressable space.
The PHY SFR space is implemented in the same
manner as the SPI interface described above.
In both 8-bit and 16-bit PSP modes, full device functionality can be realized without using the full width of
the address bus. This is because the SRAM buffer can
still be read and written to by using SFR pointers. In
practical terms, this can allow designers in space or pin
constrained applications to only connect a subset of the
A or AD address pins to the host microcontroller. For
example, in the 8-Bit Multiplexed PSP Modes 5 or 6,
tying pins, AD to VDD, still allows direct address
access to all SFRs. This reduces the number of pins
required for connection to the host controller, including
the interface control pins to 12 or 13.
ENC424J600/624J600 MEMORY MAPS FOR PSP INTERFACES(1)
FIGURE 3-2:
8-Bit PSP
16-Bit PSP
Main Area
Main Area
PSP Address Bus (Word Address)
Pointers (Byte Address)
PSP Address Bus and
All Pointers
0000h
0000h 0000h
SRAM Buffer
SRAM Buffer
5FFFh 2FFFh
5FFFh
Unimplemented
Unimplemented
7800h(2)
Cryptographic Data
(DMA access only)
7C4Fh(2)
Unimplemented
Special Function
Registers (R/W)
SFR Bit Set Registers
SFR Bit Clear Registers
PHY Register Area
7C4Fh(2)
Unimplemented
3F00h
7E00h
Special Function Registers (R/W)
7E9Fh
7F00h
7F7Fh
7F80h
7FFFh
SFR Bit Set Registers
SFR Bit Clear Registers
MIREGADR
16-Bit, MIIM Access Only
Note 1:
2:
7800h(2)
Cryptographic Data
(DMA access only)
00h
1Fh
PHY Register Area
3F4Fh
3F80h
3FBFh
3FC0h
3FFFh
MIREGADR
16-Bit, MIIM Access Only
00h
1Fh
Memory areas not shown to scale.
Addresses in this range are accessible only through internal address pointers of the DMA module.
DS39935C-page 18
2010 Microchip Technology Inc.
ENC424J600/624J600
3.2
Special Function Registers
The SFRs provide the main interface between the host
controller and the on-chip Ethernet controller logic.
Writing to these registers controls the operation of the
interface, while reading the registers allows the host
controller to monitor operations.
All registers are 16 bits wide. On the SPI and 8-bit PSP
interfaces, which are inherently byte-oriented, the
registers are split into separate high and low locations
which are designated by an “H” or “L” suffix, respectively. All registers are organized in little-endian format
such that the low byte is always at the lower memory
address.
Some of the available addresses are unimplemented or
marked as reserved. These locations should not be
written to. Data read from reserved locations should be
ignored. Reading from unimplemented locations will
return ‘0’. When reading and writing to registers which
contain reserved bits, any rules stated in the register
definition should be observed.
The addresses of all user-accessible registers are
provided in Tables 3-1 through 3-6. A complete bit level
listing of the SFRs is presented in Table 3-7 (page 26).
3.2.1
E REGISTERS
SFRs with names starting with “E” are the primary
control and pointer registers. They configure and control all of the (non-MAC) top-level features of the
device, as well as manipulate the pointers that define
the memory buffers. These registers can be read and
written in any order, with any length, without concern
for address alignment.
3.2.2
3.2.3
SPI REGISTER MAP
As previously described, the SFR memory is
partitioned into four banks plus a special region that is
not bank addressable. Each bank is 32 bytes long and
addressed by a 5-bit address value. All SFR memory
may also be accessed via unbanked SPI opcodes
which use a full 8-bit address to form a linear address
map without banking.
The last 10 bytes (16h to 1Fh) of all SPI banks point to
a common set of five registers: EUDAST, EUDAND,
ESTAT, EIR and ECON1. These are key registers used
in controlling and monitoring the operation of the
device. Their common banked addresses allow easy
access without switching the bank.
The SPI interface implements a comprehensive
instruction set that allows for reading and writing of
registers, as well as setting and clearing individual bits
or bit fields within registers. The SPI instruction set is
explained in detail in Section 4.0 “Serial Peripheral
Interface (SPI)”.
The SFR map for the SPI interface is shown in
Table 3-1. Registers are presented by a bank. The
banked (5-bit) address applicable to the registers in
each row is shown in the left most column. The
unbanked (8-bit) address for each register is shown to
the immediate left of the register name.
Note:
SFRs in the unbanked region (80h through
9Fh) cannot be accessed using banked
addressing. The use of an unbanked SFR
opcode is required to perform operations
on these registers.
MAC REGISTERS
SFRs with names that start with “MA” or “MI” are
implemented in the MAC module hardware. For this
reason, their operation differs from “E” registers in two
ways.
First, MAC registers support read and write operations
only. Individual bit set and bit clear operations cannot
be performed.
Additionally, MAC registers must always be written as
a 16-bit word, regardless of the I/O interface being
used. That is, on the SPI or 8-bit PSP interfaces, all
write operations must be performed by writing to the
low byte, followed by a write to the associated high
byte. On 16-bit PSP interfaces, both write enables or
byte selects must be asserted to perform the 16-bit
write. Non-sequential writes, such as writing to the low
byte of one MAC register, the low byte of a second
MAC register and then the high byte of the first register
cannot be performed.
2010 Microchip Technology Inc.
DS39935C-page 19
ENC424J600/624J600
TABLE 3-1:
ENC424J600/624J600 SFR MAP (SPI INTERFACE)
Bank 2
(40h offset)
Unbanked(1)
(80h offset)
Bank 3
(60h offset)
ETXSTL
01
01
ETXSTH
21
EHT1H
41
MACON1H
61
MAADR3H
81
Reserved
02
02
ETXLENL
22
EHT2L
42
MACON2L
62
MAADR2L
82
ERXDATA(2)
03
03
ETXLENH
23
EHT2H
43
MACON2H
63
MAADR2H
83
Reserved
04
04
ERXSTL
24
EHT3L
44
MABBIPGL
64
MAADR1L
84
EUDADATA(2)
20
EHT1L
40
MACON1L
Name
Unbanked
Address
00
Name
Unbanked
Address
00
Name
Unbanked
Address
Name
Unbanked
Address
Unbanked
Address
Bank 1
(20h offset)
Banked Register
Addresses
Bank 0
(00h offset)
Name
60
MAADR3L
80
EGPDATA(2)
05
05
ERXSTH
25
EHT3H
45
MABBIPGH
65
MAADR1H
85
Reserved
06
06
ERXTAILL
26
EHT4L
46
MAIPGL
66
MIWRL
86
EGPRDPTL
07
07
ERXTAILH
27
EHT4H
47
MAIPGH
67
MIWRH
87
EGPRDPTH
08
08
ERXHEADL
28
EPMM1L
48
MACLCONL
68
MIRDL
88
EGPWRPTL
EGPWRPTH
09
09
ERXHEADH
29
EPMM1H
49
MACLCONH
69
MIRDH
89
0A
0A
EDMASTL
2A
EPMM2L
4A
MAMXFLL
6A
MISTATL
8A
ERXRDPTL
0B
0B
EDMASTH
2B
EPMM2H
4B
MAMXFLH
6B
MISTATH
8B
ERXRDPTH
0C
0C
EDMALENL
2C
EPMM3L
4C
Reserved
6C
EPAUSL
8C
ERXWRPTL
0D
0D
EDMALENH
2D
EPMM3H
4D
Reserved
6D
EPAUSH
8D
ERXWRPTH
0E
0E
EDMADSTL
2E
EPMM4L
4E
Reserved
6E
ECON2L
8E
EUDARDPTL
0F
0F
EDMADSTH
2F
EPMM4H
4F
Reserved
6F
ECON2H
8F
EUDARDPTH
10
10
EDMACSL
30
EPMCSL
50
Reserved
70
ERXWML
90
EUDAWRPTL
EUDAWRPTH
11
11
EDMACSH
31
EPMCSH
51
Reserved
71
ERXWMH
91
12
12
ETXSTATL
32
EPMOL
52
MICMDL
72
EIEL
92
Reserved
13
13
ETXSTATH
33
EPMOH
53
MICMDH
73
EIEH
93
Reserved
14
14
ETXWIREL
34
ERXFCONL
54
MIREGADRL
74
EIDLEDL
94
Reserved
15
15
ETXWIREH
35
ERXFCONH
55
MIREGADRH
75
EIDLEDH
95
Reserved
16
16
EUDASTL
36
EUDASTL
56
EUDASTL
76
EUDASTL
96
Reserved
17
17
EUDASTH
37
EUDASTH
57
EUDASTH
77
EUDASTH
97
Reserved
18
18
EUDANDL
38
EUDANDL
58
EUDANDL
78
EUDANDL
98
Reserved
Reserved
19
19
EUDANDH
39
EUDANDH
59
EUDANDH
79
EUDANDH
99
1A
1A
ESTATL
3A
ESTATL
5A
ESTATL
7A
ESTATL
9A
Reserved
1B
1B
ESTATH
3B
ESTATH
5B
ESTATH
7B
ESTATH
9B
Reserved
1C
1C
EIRL
3C
EIRL
5C
EIRL
7C
EIRL
9C
Reserved
1D
1D
EIRH
3D
EIRH
5D
EIRH
7D
EIRH
9D
Reserved
1E
1E
ECON1L
3E
ECON1L
5E
ECON1L
7E
ECON1L
9E
—
1F
1F
ECON1H
3F
ECON1H
5F
ECON1H
7F
ECON1H
9F
—
Note 1:
2:
Unbanked SFRs can be accessed only by unbanked SPI opcodes.
When using these registers to access the SRAM buffer, use only the N-byte SRAM instructions. See Section 4.6.2
“Unbanked SFR Operations” and Section 4.6.3 “SRAM Buffer Operations” for more details.
DS39935C-page 20
2010 Microchip Technology Inc.
ENC424J600/624J600
3.2.4
PSP REGISTER MAP
When using a PSP interface, the SFR memory is linear;
all registers are directly accessible without banking. To
maintain consistency with the SPI interface, the
EUDAST, EUDAND, ESTAT, EIR and ECON1 registers
are instantiated in four locations in the PSP memory
maps. Users may opt to use any one of these four
locations.
TABLE 3-2:
Addr
The SFR maps for the 8-bit and 16-bit PSP interfaces
are shown in Table 3-2 and Table 3-3, respectively.
ENC424J600/624J600 SFR MAP (BASE REGISTER MAP, 8-BIT PSP INTERFACE)
Name
Addr
Name
Addr
Name
Addr
Name
Addr
Name
EGPDATA
7E00
ETXSTL
7E20
EHT1L
7E40
MACON1L
7E60
MAADR3L
7E80
7E01
ETXSTH
7E21
EHT1H
7E41
MACON1H
7E61
MAADR3H
7E81
Reserved
7E02
ETXLENL
7E22
EHT2L
7E42
MACON2L
7E62
MAADR2L
7E82
ERXDATA
7E03
ETXLENH
7E23
EHT2H
7E43
MACON2H
7E63
MAADR2H
7E83
Reserved
EUDADATA
7E04
ERXSTL
7E24
EHT3L
7E44
MABBIPGL
7E64
MAADR1L
7E84
7E05
ERXSTH
7E25
EHT3H
7E45
MABBIPGH
7E65
MAADR1H
7E85
Reserved
7E06
ERXTAILL
7E26
EHT4L
7E46
MAIPGL
7E66
MIWRL
7E86
EGPRDPTL
7E07
ERXTAILH
7E27
EHT4H
7E47
MAIPGH
7E67
MIWRH
7E87
EGPRDPTH
7E08
ERXHEADL
7E28
EPMM1L
7E48
MACLCONL
7E68
MIRDL
7E88
EGPWRPTL
7E09
ERXHEADH
7E29
EPMM1H
7E49
MACLCONH
7E69
MIRDH
7E89
EGPWRPTH
7E0A
EDMASTL
7E2A
EPMM2L
7E4A
MAMXFLL
7E6A
MISTATL
7E8A
ERXRDPTL
7E0B
EDMASTH
7E2B
EPMM2H
7E4B
MAMXFLH
7E6B
MISTATH
7E8B
ERXRDPTH
7E0C
EDMALENL
7E2C
EPMM3L
7E4C
Reserved
7E6C
EPAUSL
7E8C
ERXWRPTL
7E0D
EDMALENH
7E2D
EPMM3H
7E4D
Reserved
7E6D
EPAUSH
7E8D
ERXWRPTH
7E0E
EDMADSTL
7E2E
EPMM4L
7E4E
Reserved
7E6E
ECON2L
7E8E
EUDARDPTL
7E0F
EDMADSTH
7E2F
EPMM4H
7E4F
Reserved
7E6F
ECON2H
7E8F
EUDARDPTH
7E10
EDMACSL
7E30
EPMCSL
7E50
Reserved
7E70
ERXWML
7E90
EUDAWRPTL
7E11
EDMACSH
7E31
EPMCSH
7E51
Reserved
7E71
ERXWMH
7E91
EUDAWRPTH
7E12
ETXSTATL
7E32
EPMOL
7E52
MICMDL
7E72
EIEL
7E92
Reserved
7E13
ETXSTATH
7E33
EPMOH
7E53
MICMDH
7E73
EIEH
7E93
Reserved
7E14
ETXWIREL
7E34
ERXFCONL
7E54
MIREGADRL
7E74
EIDLEDL
7E94
Reserved
7E15
ETXWIREH
7E35
ERXFCONH
7E55
MIREGADRH
7E75
EIDLEDH
7E95
Reserved
7E16
EUDASTL
7E36
EUDASTL
7E56
EUDASTL
7E76
EUDASTL
7E96
Reserved
7E17
EUDASTH
7E37
EUDASTH
7E57
EUDASTH
7E77
EUDASTH
7E97
Reserved
7E18
EUDANDL
7E38
EUDANDL
7E58
EUDANDL
7E78
EUDANDL
7E98
Reserved
7E19
EUDANDH
7E39
EUDANDH
7E59
EUDANDH
7E79
EUDANDH
7E99
Reserved
7E1A
ESTATL
7E3A
ESTATL
7E5A
ESTATL
7E7A
ESTATL
7E9A
Reserved
7E1B
ESTATH
7E3B
ESTATH
7E5B
ESTATH
7E7B
ESTATH
7E9B
Reserved
7E1C
EIRL
7E3C
EIRL
7E5C
EIRL
7E7C
EIRL
7E9C
Reserved
7E1D
EIRH
7E3D
EIRH
7E5D
EIRH
7E7D
EIRH
7E9D
Reserved
7E1E
ECON1L
7E3E
ECON1L
7E5E
ECON1L
7E7E
ECON1L
7E9E
—
7E1F
ECON1H
7E3F
ECON1H
7E5F
ECON1H
7E7F
ECON1H
7E9F
—
2010 Microchip Technology Inc.
DS39935C-page 21
ENC424J600/624J600
TABLE 3-3:
ENC424J600/624J600 SFR MAP (BASE REGISTER MAP, 16-BIT PSP INTERFACE)
Addr
Name
Addr
Name
Addr
Name
Addr
Name
Addr
Name
3F00
ETXST
3F10
EHT1
3F20
MACON1
3F30
MAADR3
3F40
EGPDATA
3F01
ETXLEN
3F11
EHT2
3F21
MACON2
3F31
MAADR2
3F41
ERXDATA
3F02
ERXST
3F12
EHT3
3F22
MABBIPG
3F32
MAADR1
3F42
EUDADATA
3F03
ERXTAIL
3F13
EHT4
3F23
MAIPG
3F33
MIWR
3F43
EGPRDPT
3F04
ERXHEAD
3F14
EPMM1
3F24
MACLCON
3F34
MIRD
3F44
EGPWRPT
3F05
EDMAST
3F15
EPMM2
3F25
MAMXFL
3F35
MISTAT
3F45
ERXRDPT
3F06
EDMALEN
3F16
EPMM3
3F26
Reserved
3F36
EPAUS
3F46
ERXWRPT
3F07
EDMADST
3F17
EPMM4
3F27
Reserved
3F37
ECON2
3F47
EUDARDPT
3F08
EDMACS
3F18
EPMCS
3F28
Reserved
3F38
ERXWM
3F48
EUDAWRPT
3F09
ETXSTAT
3F19
EPMO
3F29
MICMD
3F39
EIE
3F49
Reserved
3F0A
ETXWIRE
3F1A
ERXFCON
3F2A
MIREGADR
3F3A
EIDLED
3F4A
Reserved
3F0B
EUDAST
3F1B
EUDAST
3F2B
EUDAST
3F3B
EUDAST
3F4B
Reserved
3F0C
EUDAND
3F1C
EUDAND
3F2C
EUDAND
3F3C
EUDAND
3F4C
Reserved
3F0D
ESTAT
3F1D
ESTAT
3F2D
ESTAT
3F3D
ESTAT
3F4D
Reserved
3F0E
EIR
3F1E
EIR
3F2E
EIR
3F3E
EIR
3F4E
Reserved
3F0F
ECON1
3F1F
ECON1
3F2F
ECON1
3F3F
ECON1
3F4F
—
3.2.4.1
PSP Bit Set and Bit Clear Registers
A major difference between the SPI and PSP memory
maps is the inclusion of companion Bit Set and Bit
Clear registers for many of the E registers. Since the
PSP interface allows direct access to memory
locations, without a command interpreter, there are no
instructions implemented to perform single bit
manipulations. Instead, this interface implements
separate Bit Set and Bit Clear registers, allowing users
to individually work with volatile bits (such as interrupt
flags) without the risk of disturbing the values of other
bits. Setting the bit(s) in one of these registers sets or
clears the corresponding bit(s) in the base register.
In the PSP interface, Bit Set and Bit Clear registers are
located in different areas of the addressable memory
space from their corresponding “base” SFRs. The
address of the registers is always at a fixed offset from
their corresponding base register. For the 8-bit interface,
the offset is 100h (Set) or 180h (Clear). For the 16-bit
interface, the offset is 80H (Set) or C0 (Clear).
Symbolically, the names of the companion registers are
the names of the base registers, plus the suffix form
“-SET” (or “-SETH/SETL”) for Bit Set registers and
“-CLR” (“-CLRH/CLRL”) for Bit Clear registers.
DS39935C-page 22
Most SFRs have their own pair of Bit Set and Bit Clear
registers. However, these SFRs do not:
• MAC registers, including MI registers for PHY
access
• Read-only status registers (ERXHEAD, ETXSTAT,
ETXWIRE and ESTAT)
• All of the SRAM Buffer Pointers and data windows
(SFRs located at 7E80h to 7E9Fh in the 8-bit
interface, or 3F40h to 3F4Fh in the 16-bit
interface)
The Bit Set and Bit Clear registers for the 8-bit PSP
interface are listed in Table 3-4 and Table 3-5,
respectively. The registers for the 16-bit interface are
listed together in Table 3-6.
2010 Microchip Technology Inc.
ENC424J600/624J600
TABLE 3-4:
ENC424J600/624J600 SFR MAP (SET REGISTER MAP, 8-BIT PSP INTERFACE)
Bit Set Registers (7F00h to 7F7Fh)(1)
Addr
Name
Addr
Name
Addr
Name
Addr
Name
7F00
ETXSTSETL
7F20
EHT1SETL
7F40
Reserved
7F60
Reserved
7F01
ETXSTSETH
7F21
EHT1SETH
7F41
Reserved
7F61
Reserved
7F02
ETXLENSETL
7F22
EHT2SETL
7F42
Reserved
7F62
Reserved
7F03
ETXLENSETH
7F23
EHT2SETH
7F43
Reserved
7F63
Reserved
7F04
ERXSTSETL
7F24
EHT3SETL
7F44
Reserved
7F64
Reserved
7F05
ERXSTSETH
7F25
EHT3SETH
7F45
Reserved
7F65
Reserved
7F06
ERXTAILSETL
7F26
EHT4SETL
7F46
Reserved
7F66
Reserved
7F07
ERXTAILSETH
7F27
EHT4SETH
7F47
Reserved
7F67
Reserved
7F08
—
7F28
EPMM1SETL
7F48
Reserved
7F68
Reserved
Reserved
7F09
—
7F29
EPMM1SETH
7F49
Reserved
7F69
7F0A
EDMASTSETL
7F2A
EPMM2SETL
7F4A
Reserved
7F6A
Reserved
7F0B
EDMASTSETH
7F2B
EPMM2SETH
7F4B
Reserved
7F6B
Reserved
7F0C
EDMALENSETL
7F2C
EPMM3SETL
7F4C
Reserved
7F6C
EPAUSSETL
7F0D
EDMALENSETH
7F2D
EPMM3SETH
7F4D
Reserved
7F6D
EPAUSSETH
7F0E
EDMADSTSETL
7F2E
EPMM4SETL
7F4E
Reserved
7F6E
ECON2SETL
7F0F
EDMADSTSETH
7F2F
EPMM4SETH
7F4F
Reserved
7F6F
ECON2SETH
7F10
EDMACSSETL
7F30
EPMCSSETL
7F50
Reserved
7F70
ERXWMSETL
ERXWMSETH
7F11
EDMACSSETH
7F31
EPMCSSETH
7F51
Reserved
7F71
7F12
—
7F32
EPMOSETL
7F52
Reserved
7F72
EIESETL
7F13
—
7F33
EPMOSETH
7F53
Reserved
7F73
EIESETH
7F14
—
7F34
ERXFCONSETL
7F54
Reserved
7F74
EIDLEDSETL
7F15
—
7F35
ERXFCONSETH
7F55
Reserved
7F75
EIDLEDSETH
7F16
EUDASTSETL
7F36
EUDASTSETL
7F56
EUDASTSETL
7F76
EUDASTSETL
7F17
EUDASTSETH
7F37
EUDASTSETH
7F57
EUDASTSETH
7F77
EUDASTSETH
7F18
EUDANDSETL
7F38
EUDANDSETL
7F58
EUDANDSETL
7F78
EUDANDSETL
7F19
EUDANDSETH
7F39
EUDANDSETH
7F59
EUDANDSETH
7F79
EUDANDSETH
7F1A
—
7F3A
—
7F5A
—
7F7A
—
7F1B
—
7F3B
—
7F5B
—
7F7B
—
7F1C
EIRSETL
7F3C
EIRSETL
7F5C
EIRSETL
7F7C
EIRSETL
7F1D
EIRSETH
7F3D
EIRSETH
7F5D
EIRSETH
7F7D
EIRSETH
7F1E
ECON1SETL
7F3E
ECON1SETL
7F5E
ECON1SETL
7F7E
ECON1SETL
ECON1SETH
7F3F
ECON1SETH
7F5F
ECON1SETH
7F7F
ECON1SETH
7F1F
Note 1:
Bit Set and Bit Clear registers are not implemented for the base SFRs located between 7E80h and 7E9Fh.
2010 Microchip Technology Inc.
DS39935C-page 23
ENC424J600/624J600
TABLE 3-5:
ENC424J600/624J600 SFR MAP (CLR REGISTER MAP, 8-BIT PSP INTERFACE)
Bit Clear Registers (7F80h to 7FFFh)(1)
Addr
Name
Addr
Name
Addr
Name
Addr
Name
7F80
ETXSTCLRL
7FA0
EHT1CLRL
7FC0
Reserved
7FE0
Reserved
7F81
ETXSTCLRH
7FA1
EHT1CLRH
7FC1
Reserved
7FE1
Reserved
7F82
ETXLENCLRL
7FA2
EHT2CLRL
7FC2
Reserved
7FE2
Reserved
7F83
ETXLENCLRH
7FA3
EHT2CLRH
7FC3
Reserved
7FE3
Reserved
7F84
ERXSTCLRL
7FA4
EHT3CLRL
7FC4
Reserved
7FE4
Reserved
7F85
ERXSTCLRH
7FA5
EHT3CLRH
7FC5
Reserved
7FE5
Reserved
7F86
ERXTAILCLRL
7FA6
EHT4CLRL
7FC6
Reserved
7FE6
Reserved
7F87
ERXTAILCLRH
7FA7
EHT4CLRH
7FC7
Reserved
7FE7
Reserved
7F88
—
7FA8
EPMM1CLRL
7FC8
Reserved
7FE8
Reserved
Reserved
7F89
—
7FA9
EPMM1CLRH
7FC9
Reserved
7FE9
7F8A
EDMASTCLRL
7FAA
EPMM2CLRL
7FCA
Reserved
7FEA
Reserved
7F8B
EDMASTCLRH
7FAB
EPMM2CLRH
7FCB
Reserved
7FEB
Reserved
7F8C
EDMALENCLRL
7FAC
EPMM3CLRL
7FCC
Reserved
7FEC
EPAUSCLRL
7F8D
EDMALENCLRH
7FAD
EPMM3CLRH
7FCD
Reserved
7FED
EPAUSCLRH
7F8E
EDMADSTCLRL
7FAE
EPMM4CLRL
7FCE
Reserved
7FEE
ECON2CLRL
7F8F
EDMADSTCLRH
7FAF
EPMM4CLRH
7FCF
Reserved
7FEF
ECON2CLRH
7F90
EDMACSCLRL
7FB0
EPMCSCLRL
7FD0
Reserved
7FF0
ERXWMCLRL
7F91
EDMACSCLRH
7FB1
EPMCSCLRH
7FD1
Reserved
7FF1
ERXWMCLRH
7F92
—
7FB2
EPMOCLRL
7FD2
Reserved
7FF2
EIECLRL
7F93
—
7FB3
EPMOCLRH
7FD3
Reserved
7FF3
EIECLRH
7F94
—
7FB4
ERXFCONCLRL
7FD4
Reserved
7FF4
EIDLEDCLRL
7F95
—
7FB5
ERXFCONCLRH
7FD5
Reserved
7FF5
EIDLEDCLRH
7F96
EUDASTCLRL
7FB6
EUDASTCLRL
7FD6
EUDASTCLRL
7FF6
EUDASTCLRL
7F97
EUDASTCLRH
7FB7
EUDASTCLRH
7FD7
EUDASTCLRH
7FF7
EUDASTCLRH
7F98
EUDANDCLRL
7FB8
EUDANDCLRL
7FD8
EUDANDCLRL
7FF8
EUDANDCLRL
7F99
EUDANDCLRH
7FB9
EUDANDCLRH
7FD9
EUDANDCLRH
7FF9
EUDANDCLRH
7F9A
—
7FBA
—
7FDA
—
7FFA
—
7F9B
—
7FBB
—
7FDB
—
7FFB
—
7F9C
EIRCLRL
7FBC
EIRCLRL
7FDC
EIRCLRL
7FFC
EIRCLRL
7F9D
EIRCLRH
7FBD
EIRCLRH
7FDD
EIRCLRH
7FFD
EIRCLRH
7F9E
ECON1CLRL
7FBE
ECON1CLRL
7FDE
ECON1CLRL
7FFE
ECON1CLRL
ECON1CLRH
7FBF
ECON1CLRH
7FDF
ECON1CLRH
7FFF
ECON1CLRH
7F9F
Note 1:
Bit Set and Bit Clear registers are not implemented for the base SFRs located between 7E80h and 7E9Fh.
DS39935C-page 24
2010 Microchip Technology Inc.
ENC424J600/624J600
TABLE 3-6:
ENC424J600/624J600 SFR MAP (SET/CLR REGISTER MAP, 16-BIT PSP INTERFACE)
Bit Set Registers (3F80h to 3FBFh)(1)
Addr
Name
Addr
Name
Addr
Name
Addr
Name
3F80
ETXSTSET
3F90
EHT1SET
3FA0
Reserved
3FB0
Reserved
3F81
ETXLENSET
3F91
EHT2SET
3FA1
Reserved
3FB1
Reserved
3F82
ERXSTSET
3F92
EHT3SET
3FA2
Reserved
3FB2
Reserved
3F83
ERXTAILSET
3F93
EHT4SET
3FA3
Reserved
3FB3
Reserved
3F84
—
3F94
EPMM1SET
3FA4
Reserved
3FB4
Reserved
3F85
EDMASTSET
3F95
EPMM2SET
3FA5
Reserved
3FB5
Reserved
3F86
EDMALENSET
3F96
EPMM3SET
3FA6
Reserved
3FB6
EPAUSSET
3F87
EDMADSTSET
3F97
EPMM4SET
3FA7
Reserved
3FB7
ECON2SET
3F88
EDMACSSET
3F98
EPMCSSET
3FA8
Reserved
3FB8
ERXWMSET
3F89
—
3F99
EPMOSET
3FA9
Reserved
3FB9
EIESET
3F8A
—
3F9A
ERXFCON
3FAA
Reserved
3FBA
EIDLEDSET
3F8B
EUDASTSET
3F9B
EUDASTSET
3FAB
EUDASTSET
3FBB
EUDASTSET
3F8C
EUDANDSET
3F9C
EUDANDSET
3FAC
EUDANDSET
3FBC
EUDANDSET
3F8D
—
3F9D
—
3FAD
—
3FBD
—
3F8E
EIRSET
3F9E
EIRSET
3FAE
EIRSET
3FBE
EIRSET
3F8F
ECON1SET
3F9F
ECON1SET
3FAF
ECON1SET
3FBF
ECON1SET
Bit Clear Registers (3FC0h to
3FFFh)(1)
Addr
Name
Addr
Name
Addr
Name
Addr
Name
3FC0
ETXSTCLR
3FD0
EHT1CLR
3FE0
Reserved
3FF0
Reserved
3FC1
ETXLENCLR
3FD1
EHT2CLR
3FE1
Reserved
3FF1
Reserved
3FC2
ERXSTCLR
3FD2
EHT3CLR
3FE2
Reserved
3FF2
Reserved
3FC3
ERXTAILCLR
3FD3
EHT4CLR
3FE3
Reserved
3FF3
Reserved
3FC4
—
3FD4
EPMM1CLR
3FE4
Reserved
3FF4
Reserved
3FC5
EDMASTCLR
3FD5
EPMM2CLR
3FE5
Reserved
3FF5
Reserved
3FC6
EDMALENCLR
3FD6
EPMM3CLR
3FE6
Reserved
3FF6
EPAUSCLR
3FC7
EDMADSTCLR
3FD7
EPMM4CLR
3FE7
Reserved
3FF7
ECON2CLR
3FC8
EDMACSCLR
3FD8
EPMCSCLR
3FE8
Reserved
3FF8
ERXWMCLR
3FC9
—
3FD9
EPMOCLR
3FE9
Reserved
3FF9
EIECLR
3FCA
—
3FDA
ERXFCONCLR
3FEA
Reserved
3FFA
EIDLEDCLR
3FCB
EUDASTCLR
3FDB
EUDASTCLR
3FEB
EUDASTCLR
3FFB
EUDASTCLR
3FCC
EUDANDCLR
3FDC
EUDANDCLR
3FEC
EUDANDCLR
3FFC
EUDANDCLR
3FCD
—
3FDD
—
3FED
—
3FFD
—
3FCE
EIRCLR
3FDE
EIRCLR
3FEE
EIRCLR
3FFE
EIRCLR
ECON1CLR
3FDF
ECON1CLR
3FEF
ECON1CLR
3FFF
ECON1CLR
3FCF
Note 1:
Bit Set and Bit Clear registers are not implemented for the base SFRs located between 3F40h and 3F4Fh.
2010 Microchip Technology Inc.
DS39935C-page 25
High Byte (‘H’ Register)
8-Bit
File
Name
ENC424J600/624J600 REGISTER FILE SUMMARY
Bit 7
16-Bit
Bit 15
Low Byte (‘L’ Register)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EUDAST
—
User-Defined Area Start Pointer (EUDAST)
User-Defined Area Start Pointer (EUDAST)
EUDAND
—
User-Defined Area End Pointer (EUDAND)
User-Defined Area End Pointer (EUDAND)
ESTAT
INT
FCIDLE
RXBUSY
CLKRDY
r
PHYDPX
r
PHYLNK
00, 00
5F, FF
PKTCNT7 PKTCNT6 PKTCNT5 PKTCNT4 PKTCNT3
EIR
CRYPTEN MODEXIF
HASHIF
AESIF
LINKIF
r
r
r
r
PKTIF
DMAIF
ECON1
MODEXST HASHEN
HASHOP
HASHLST
AESST
AESOP1
AESOP0
PKTDEC
FCOP1
FCOP0
DMAST
Reset
r
TXIF
PKTCNT2 PKTCNT1 PKTCNT0 00, 00
TXABTIF
DMACPY DMACSSD DMANOCS
RXABTIF
TXRTS
PCFULIF 0A, 00
RXEN
00, 00
ETXST
—
TX Start Address (ETXST)
TX Start Address (ETXST)
00, 00
ETXLEN
—
TX Length (ETXLEN)
TX Length (ETXLEN)
00, 00
ERXST
—
RX Buffer Start Address (ERXST)
RX Buffer Start Address (ERXST)
53, 40
ERXTAIL
—
RX Tail Pointer (ERXTAIL)
RX Tail Pointer (ERXTAIL)
5F, FE
ERXHEAD
—
RX Head Pointer (ERXHEAD)
RX Head Pointer (ERXHEAD)
53, 40
EDMAST
—
DMA Start Address (EDMAST)
DMA Start Address (EDMAST)
00, 00
EDMALEN
—
DMA Length (EDMALEN)
DMA Length (EDMALEN)
00, 00
EDMADST
—
DMA Destination Address (EDMADST)
DMA Destination Address (EDMADST)
00, 00
DMA Checksum, Low Byte (EDMACS)
00, 00
EDMACS
ETXSTAT
DMA Checksum, High Byte (EDMACS)
—
—
—
r
r
LATECOL MAXCOL EXDEFER
DEFER
r
r
CRCBAD COLCNT3 COLCNT2 COLCNT1 COLCNT0 00, 00
ETXWIRE
Transmit Byte Count on Wire (including collision bytes), High Byte (ETXWIRE)
Transmit Byte Count on Wire (including collision bytes), Low Byte (ETXWIRE)
00, 00
EHT1
Hash Table Filter (EHT1)
Hash Table Filter (EHT1)
00, 00
EHT2
Hash Table Filter (EHT2)
Hash Table Filter (EHT2)
00, 00
ETH3
Hash Table Filter (EHT3)
Hash Table Filter (EHT3)
00, 00
ETH4
Hash Table Filter (EHT4)
Hash Table Filter (EHT4)
00, 00
EPMM1
Pattern Match Filter Mask (EPMM1)
Pattern Match Filter Mask (EPMM1)
00, 00
EPMM2
Pattern Match Filter Mask (EPMM2)
Pattern Match Filter Mask (EPMM2)
00, 00
EPMM3
Pattern Match Filter Mask (EPMM3)
Pattern Match Filter Mask (EPMM3)
00, 00
EPMM4
Pattern Match Filter Mask (EPMM4)
Pattern Match Filter Mask (EPMM4)
00, 00
EPMCS
Pattern Match Filter Checksum, High Byte (EPMCS)
Pattern Match Filter Checksum, Low Byte (EPMCS)
ERXFCON
2010 Microchip Technology Inc.
EPMO
HTEN
MPEN
—
NOTPM
PMEN3
PMEN2
PMEN1
PMEN0
Pattern Match Filter Offset, High Byte (EPMO)
CRCEEN
CRCEN
RUNTEEN RUNTEN
00, 00
UCEN
NOTMEEN
MCEN
BCEN
r
RXPAUS
PASSALL
r
HFRMEN
r
Pattern Match Filter Offset, Low Byte (EPMO)
r
r
—
—
r
r
r
r
MACON2
—
DEFER
BPEN
NOBKOFF
—
—
r
r
MABBIPG
—
—
—
—
—
—
—
—
—
BBIPG6
BBIPG5
BBIPG4
BBIPG3
BBIPG2
BBIPG1
BBIPG0
00, 12
MAIPG
—
r
r
r
r
r
r
r
—
IPG6
IPG5
IPG4
IPG3
IPG2
IPG1
IPG0
0C, 12
MACLCON
—
—
r
r
r
r
r
r
—
—
—
—
Legend:
MAC Maximum Frame Length, High Byte (MAMXFL)
—
—
LOOPBK
00, 00
MACON1
MAMXFL
—
00, 59
PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN
x0, 0D
FULDPX 40, B2
MAXRET3 MAXRET2 MAXRET1 MAXRET0 37, 0F
MAC Maximum Frame Length, Low Byte (MAMXFL)
— = unimplemented, read as ‘0’; q = unique MAC address or silicon revision nibble; r = reserved bit, do not modify; x = Reset value unknown. Reset values are shown in hexadecimal for each byte.
05, EE
ENC424J600/624J600
DS39935C-page 26
TABLE 3-7:
2010 Microchip Technology Inc.
TABLE 3-7:
High Byte (‘H’ Register)
8-Bit
File
Name
ENC424J600/624J600 REGISTER FILE SUMMARY (CONTINUED)
Low Byte (‘L’ Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MICMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MIISCAN
MIREGADR
—
—
—
r
r
r
r
r
—
—
—
PHREG4
PHREG3
PHREG2
PHREG1
16-Bit
MIIRD
Reset
--, 00
PHREG0 01, 00
MAADR3
MAC Address, Byte 6 (MAADR)
MAC Address, Byte 5 (MAADR)
qq, qq
MAADR2
MAC Address, Byte 4 (MAADR)
MAC Address, Byte 3 (MAADR)/OUI Byte 3
qq, a3
MAADR1
MAC Address, Byte 2 (MAADR)/OUI Byte 2
MAC Address, Byte 1 (MAADR)/OUI Byte 1
04, 00
MIWR
MII Management Write Data, High Byte (MIWR)
MII Management Write Data, Low Byte (MIWR)
00, 00
MIRD
MII Management Read Data, High Byte (MIRD)
MII Management Read Data, Low Byte (MIRD)
MISTAT
EPAUS
—
—
—
—
—
—
—
—
Pause Timer Value, High Byte (EPAUS)
ECON2
ETHEN
ERXWM
RXFWM7
STRCH
TXMAC
—
—
—
00, 00
r
NVALID
SCAN
BUSY
Pause Timer Value, Low Byte (EPAUS)
SHA1MD5
COCON3
COCON2 COCON1 COCON0
AUTOFC
TXRST
RXRST
ETHRST
RXFWM2 RXFWM1 RXFWM0 RXEWM7 RXEWM6 RXEWM5 RXEWM4
--, 00
10, 00
MODLEN1 MODLEN0 AESLEN1 AESLEN0 CB, 00
RXFWM4
RXFWM3
RXEWM3
RXEWM2
RXEWM1 RXEWM0 10, 0F
INTIE
MODEXIE
HASHIE
AESIE
LINKIE
r
r
r
r
PKTIE
DMAIE
r
TXIE
TXABTIE
RXABTIE
LACFG3
LACFG2
LACFG1
LACFG0
LBCFG3
LBCFG2
LBCFG1
LBCFG0
DEVID2
DEVID1
DEVID0
REVID4
REVID3
REVID2
REVID1
EGPDATA
r
r
r
r
r
r
r
r
General Purpose Data Window Register
--, xx
ERXDATA
r
r
r
r
r
r
r
r
Ethernet RX Data Window Register
--, xx
EUDADATA
r
r
r
r
r
r
r
r
User-Defined Area Data Window Register
--, xx
EGPRDPT
—
General Purpose Window Read Pointer, High Byte (ETXRDPT)
General Purpose Window Read Pointer, Low Byte (ETXRDPT)
05, FA
EGPWRPT
—
General Purpose Window Write Pointer, High Byte (ETXWRPT)
General Purpose Window Write Pointer, Low Byte (ETXWRPT)
00, 00
ERXRDPT
—
RX Window Read Pointer, High Byte (ERXRDPT)
RX Window Read Pointer, Low Byte (ERXRDPT)
05, FA
ERXWRPT
—
RX Window Write Pointer, High Byte (ERXWRPT)
RX Window Write Pointer, Low Byte (ERXWRPT)
00, 00
EUDARDPT
—
UDA Window Read Pointer (EUDARDPT)
UDA Window Read Pointer (EUDARDPT)
05, FA
EUDAWRPT
—
UDA Window Write Pointer (EUDAWRPT)
UDA Window Write Pointer (EUDAWRPT)
00, 00
EIE
EIDLED
PCFULIE 80, 10
REVID0
— = unimplemented, read as ‘0’; q = unique MAC address or silicon revision nibble; r = reserved bit, do not modify; x = Reset value unknown. Reset values are shown in hexadecimal for each byte.
26, qq
DS39935C-page 27
ENC424J600/624J600
Legend:
RXFWM6 RXFWM5
—
ENC424J600/624J600
3.3
PHY Special Function Registers
The PHY registers provide configuration and control of
the PHY module, as well as status information about its
operation. These 16-bit registers are located in their
own memory space, outside of the main SFR space.
Unlike other SFRs, the PHY SFRs are not directly
accessible through the SPI or PSP interfaces. Instead,
access is accomplished through a special set of MAC
control registers that implement a Media Independent
Interface Management (MIIM) defined by IEEE 802.3;
these are the MICMD, MISTAT and MIREGADR
registers.
There are a total of 32 PHY addresses; however, only
10 locations implement user-accessible registers listed
in Table 3-8. Writes to unimplemented locations are
ignored and any attempts to read these locations return
FFFFh. Do not write to reserved PHY register locations
and ignore their content if read.
TABLE 3-8:
PHY SPECIAL FUNCTION
REGISTER MAP
3.3.1
READING PHY REGISTERS
When a PHY register is read, the entire 16 bits are
obtained.
To read from a PHY register:
1.
2.
3.
4.
5.
Write the address of the PHY register to read
from
into
the
MIREGADR
register
(Register 3-1). Make sure to also set reserved
bit 8 of this register.
Set the MIIRD bit (MICMD, Register 3-2).
The read operation begins and the BUSY bit
(MISTAT, Register 3-3) is automatically set
by hardware.
Wait 25.6 s. Poll the BUSY (MISTAT) bit to
be certain that the operation is complete. While
busy, the host controller should not start any
MIISCAN operations or write to the MIWR
register. When the MAC has obtained the register
contents, the BUSY bit will clear itself.
Clear the MIIRD (MICMD) bit.
Read the desired data from the MIRD register.
For 8-bit interfaces, the order that these bytes
are read is unimportant.
Address
Name
Address
Name
00
PHCON1
10
Reserved
3.3.2
01
PHSTAT1
11
PHCON2
02
Reserved
12
Reserved
03
Reserved
13
—
04
PHANA
14
Reserved
05
PHANLPA
15
Reserved
When a PHY register is written to, the entire 16 bits are
written at once; selective bit writes are not
implemented. If it is necessary to reprogram only select
bits in the register, the host microcontroller must first
read the PHY register, modify the resulting data and
then write the data back to the PHY register.
06
PHANE
16
Reserved
To write to a PHY register:
07
—
17
Reserved
1.
08
—
18
—
09
—
19
—
0A
—
1A
—
0B
—
1B
PHSTAT2
0C
—
1C
Reserved
0D
—
1D
Reserved
0E
—
1E
Reserved
0F
—
1F
PHSTAT3
DS39935C-page 28
2.
3.
WRITING PHY REGISTERS
Write the address of the PHY register to write to
into the MIREGADR register. Make sure to also
set reserved bit 8 of this register.
Write the 16 bits of data into the MIWR register.
The low byte must be written first, followed by
the high byte.
Writing to the high byte of MIWR begins the
MIIM transaction and the BUSY (MISTAT)
bit is automatically set by hardware.
The PHY register is written after the MIIM operation
completes, which takes 25.6 s. When the write operation has completed, the BUSY bit clears itself. The host
controller should not start any MIISCAN, MIWR or
MIIRD operations while the BUSY bit is set.
2010 Microchip Technology Inc.
ENC424J600/624J600
3.3.3
SCANNING A PHY REGISTER
The MAC can be configured to perform automatic
back-to-back read operations on a PHY register. This
can reduce the host controller complexity when
periodic status information updates are desired.
To perform the scan operation:
1.
2.
Write the address of the PHY register to read
from into the MIREGADR register. Make sure to
also set reserved bit 8 of this register.
Set the MIISCAN (MICMD) bit. The scan
operation begins and the BUSY (MISTAT)
bit is automatically set by hardware. The first
read operation will complete after 25.6 s. Subsequent reads will be done at the same interval
until the operation is cancelled. The NVALID
(MISTAT) bit may be polled to determine
when the first read operation is complete.
REGISTER 3-1:
After setting the MIISCAN bit, the MIRD register will
automatically be updated every 25.6 s. There is no
status information which can be used to determine
when the MIRD registers are updated. On the SPI or
8-bit PSP interfaces, the host controller can only read
one register location at a time. Therefore, it must not be
assumed that the values of MIRDL and MIRDH were
read from the PHY at exactly the same time.
When the MIISCAN operation is in progress, the host
controller must not attempt to write to MIWR or start an
MIIRD operation. The MIISCAN operation can be
cancelled by clearing the MIISCAN (MICMD) bit
and then polling the BUSY (MISTAT) bit. New
operations may be started after the BUSY bit is cleared.
MIREGADR: MII MANAGEMENT ADDRESS REGISTER
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
—
r
r
r
r
r
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
PHREG4
PHREG3
PHREG2
PHREG1
PHREG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
Reserved: Write as ‘00001’ (01h)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
PHREG: MII Management PHY Register Address Select bits
The address of the PHY register which MII Management read and write operations will apply to.
2010 Microchip Technology Inc.
DS39935C-page 29
ENC424J600/624J600
REGISTER 3-2:
MICMD: MII MANAGEMENT COMMAND REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
MIISCAN
MIIRD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-2
Unimplemented: Read as ‘0’
bit 1
MIISCAN: MII Scan Enable bit
1 = PHY register designated by MIREGADR is continuously read and the data is copied to MIRD
0 = No MII Management scan operation is in progress
bit 0
MIIRD: MII Read Enable bit
1 = PHY register designated by MIREGADR is read once and the data is copied to MIRD
0 = No MII Management read operation is in progress
REGISTER 3-3:
MISTAT: MII MANAGEMENT STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R-0
R-0
R-0
R-0
—
—
—
—
r
NVALID
SCAN
BUSY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-4
Unimplemented: Read as ‘0’
bit 3
Reserved: Ignore on read
bit 2
NVALID: MII Management Read Data Not Valid Status bit
1 = The contents of MIRD are not valid yet
0 = The MII Management read cycle has completed and MIRD has been updated
bit 1
SCAN: MII Management Scan Status bit
1 = MII Management scan operation is in progress
0 = No MII Management scan operation is in progress
bit 0
BUSY: MII Management Busy Status bit
1 = A PHY register is currently being read or written to
0 = The MII Management interface is Idle
DS39935C-page 30
2010 Microchip Technology Inc.
2010 Microchip Technology Inc.
TABLE 3-9:
PHY REGISTER FILE SUMMARY
File Name
Bit 15
Bit 14
PHCON1
PRST
PLOOPBK
PHSTAT1
r
FULL100
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
SPD100
ANEN
PSLEEP
r
RENEG
PFULDPX
r
r
r
r
HALF100
FULL10
HALF10
r
r
r
r
r
ANDONE
LRFAULT
Bit 3
Bit 0
Value
on
Reset
r
10, 00
Bit 2
Bit 1
r
r
r
ANABLE
LLSTAT
r
EXTREGS 78, 09
ADIEEE0 01, E1
PHANA
ADNP
r
ADFAULT
r
ADPAUS1 ADPAUS0
r
AD100FD
AD100
AD10FD
AD10
ADIEEE4
ADIEEE3
ADIEEE2
ADIEEE1
PHANLPA
LPNP
LPACK
LPFAULT
r
LPPAUS1
LPPAUS0
LP100T4
LP100FD
LP100
LP10FD
LP10
LPIEEE4
LPIEEE3
LPIEEE2
LPIEEE1
LPIEEE0
PHANE
r
r
r
r
r
r
r
r
r
r
r
PDFLT
r
r
LPARCD
LPANABL 00, 00
xx, xx
PHCON2
r
r
EDPWRDN
r
EDTHRES
r
r
r
r
r
r
r
r
FRCLNK
EDSTAT
r
00, 02
PHSTAT2
r
r
r
r
r
r
r
r
r
r
r
PLRITY
r
r
r
r
xx, 0x
PHSTAT3
r
r
r
r
r
r
r
r
r
r
r
r
r
00, 40
Legend:
SPDDPX2 SPDDPX1 SPDDPX0
r = reserved bit, write as ‘0’; ignore on read; x = unknown. Reset values are shown in hexadecimal for each byte.
ENC424J600/624J600
DS39935C-page 31
ENC424J600/624J600
3.4
Cryptographic Data Memory
The cryptographic data memory is used to store key
and data information for the Modular Exponentiation,
AES and MD5/SHA-1 hashing engines. The RAM for
these modules is actually implemented inside of the
modules themselves; this allows fast memory access
for the access-intensive encryption engines, as well as
the simultaneous use of more than one module by an
application. This memory is mapped into an area of
address space that is accessible only by the DMA
controller. The host controller must write to the cryptographic data memory by writing data to the 24-Kbyte
SRAM buffer, then using the DMA to copy it into the
security engine. Reading is performed in the opposite
order, using the DMA to copy the data out of the
security engine and into the SRAM buffer.
The mapping of the cryptographic space is shown in
Figure 3-3. For additional information on the cryptographic engines, refer to Section 15.0 “Cryptographic
Security Engines”. For additional information on the
DMA controller, see Section 14.0 “Direct Memory
Access (DMA) Controller”.
FIGURE 3-3:
3.5
SRAM Buffer
The SRAM buffer is a bulk 12K word x 16-bit (24 Kbytes)
memory, used for TX/RX packet buffering and general
purpose storage by the host microcontroller. In most
cases, the memory is accessed using a byte-oriented
interface, so the memory can normally be thought of as
a simple 24-Kbyte memory buffer divided into a general
purpose/TX area and an RX area (Figure 3-4).
FIGURE 3-4:
SRAM BUFFER
ORGANIZATION
0000h
General Purpose
Buffer
CRYPTOGRAPHIC DATA
MEMORY MAPPING
ERXST – 1
ERXST
Modular Exponentiation
DMA Pointers
Exponent (E)
(up to 1024 bits)
Data/Result (X/Y)
(up to 1024 bits)
Modulus (M)
(512, 768 or 1024 bits)
7800h
787Fh
7880h
78FFh
7900h
797Fh
MD5/SHA-1 Hash
Unimplemented
Data In
(512 bits)
Initialization Vector/State In
(160 bits)
Length State In (55 bits)
Digest/State Out
(128 or 160 bits)
Length State Out (55 bits)
7A00h
7A3Fh
7A40h
7A53h
7A54h
7A5Bh
7A70h
7A83h
7A84h
7A8Bh
Unimplemented
AES
Encryption Key
(128, 192 or 256 bits)
Text A In/Out (128 bits)
Text B In/Out (128 bits)
XOR Out (128 bits)
DS39935C-page 32
Circular RX FIFO
Buffer
5FFFh
Ethernet communications on 10Base-T and
100Base-TX networks occur at a fixed speed of
10 Mbps or 100 Mbps, respectively. Intra-byte gaps are
not allowed. This requires the host controller to build
outbound transmit frames in their entirety in the SRAM
buffer before the hardware is allowed to begin transmission. Similarly, when receiving packets, the buffer
provides space for the hardware to write the incoming
packet without forcing the host microcontroller to
immediately read and process the packet.
After the part exits Reset, the entire buffer is accessible
by the host controller, regardless of other transmit,
receive or DMA operations that may simultaneously
also be accessing the general purpose or receive
buffer memory.
7C00h
7C1Fh
7C20h
7C2Fh
7C30h
7C3Fh
7C40h
7C4Fh
2010 Microchip Technology Inc.
ENC424J600/624J600
3.5.1
GENERAL PURPOSE BUFFER
The general purpose buffer memory starts at address
0000h and includes all memory up to, but not including,
the memory address pointed to by the ERXST register
(i.e., ERXST – 1).
This buffer can be used to store transmit packets,
received data that the host controller wishes to save for
an extended period, or any type of volatile or state
information that the host controller does not have room
internally to save. Upper layer communications protocols and applications, such as a TCP/IP stack with SSL
or TLS security, are generally infeasible or will perform
poorly over high latency Internet links without using
large buffers.
For reliable, connection oriented protocols like TCP, the
maximum theoretical throughput is directly proportional
to the round trip Acknowledgement latency of the link
and the size of the corresponding transmit or receive
buffer. The general purpose buffer memory on the
ENCX24J600 is well suited for use by TCP for
implementing
high-performance
communications
across the Internet, where round trip Acknowledgement
latency is in the order of many milliseconds.
3.5.2
RECEIVE BUFFER
The receive buffer constitutes a circular FIFO buffer
managed by hardware. The buffer extends inclusively
from the byte pointed to by the ERXST Pointer, to the
very end of the SRAM at address 5FFFh. The size of
the buffer, in bytes, is therefore defined as:
RX Buffer Size = 5FFFh – ERXST + 1
As bytes of data are received from the Ethernet
interface, they are written into the receive buffer
sequentially. However, after the memory at address
5FFFh is written to, the hardware will automatically
wrap around and write the next byte of received data to
the ERXST address. As a result, the receive hardware
will never write outside the boundaries of the RX FIFO
buffer.
For proper 16-bit word alignment, the ERXST Pointer is
required to point to an even memory address. The
Least Significant bit of this register is read-only and
fixed as ‘0’ to force even alignment. All other
implemented bits in this register are read/write and can
be programmed by software to point to any even
address, from 0000h to 5FFEh.
The default value of ERXST on device Reset is 5340h.
This allocates 21,312 bytes to the general purpose
buffer and 3,264 bytes to the RX buffer. This RX buffer
size is adequate to store at least two maximum length
Ethernet frames, or any combination of numerous
smaller packets.
2010 Microchip Technology Inc.
The host controller may only program the ERXST
Pointer when the receive logic is disabled. The pointer
must not be modified while the receive logic is enabled
by having RXEN (ECON1) set.
The receive memory is always accessible to the RX
hardware, regardless of transmit, DMA operations or
host controller read/write operations, which may be
accessing the SRAM simultaneously. The RX
hardware will never drop a packet due to insufficient
memory access bandwidth.
3.5.3
TRANSMIT BUFFER
The ENC624J600 family does not implement a dedicated transmit buffer. The transmit hardware has the
flexibility of transmitting data starting at any memory
address, including odd memory addresses which are
off of a 16-bit word boundary. The host controller can
transmit data from either the general purpose area or
RX FIFO area of the entire 24 Kbytes of SRAM.
Because of the transmit flexibility, the host controller may
store many prebuilt packets in the general purpose
buffer for quick transmission. Alternatively, because the
hardware can transmit data from the receive buffer, it is
possible to quickly modify certain packet header fields
and retransmit received packets without reading the
entire packet contents into the host microcontroller. This
feature may improve performance on certain proxy,
gateway or echoing (“ping”) applications.
The transmit hardware performs reads from the SRAM
only; it never writes anything into the SRAM.
The entire SRAM is always accessible to the TX
hardware, regardless of the receive activity, DMA
operations or host controller read/write operations,
which may be simultaneously attempting to access the
SRAM.
3.5.4
DIRECT SRAM BUFFER ACCESS
When one of the PSP interfaces is used, the SRAM
buffer is directly accessible through the interface.
Assuming that all necessary address lines are connected, all addresses in the memory maps shown in
Figure 3-2 (except for the cryptographic data memory)
may be directly read and written to. When accessed
through this manner, the host controller must handle all
address increment and wrap-around calculations that
may be necessary. This also includes translation from
byte to word addressing when a 16-bit PSP interface is
used.
Direct access is unavailable when the SPI interface is
used.
DS39935C-page 33
ENC424J600/624J600
3.5.5
INDIRECT SRAM BUFFER ACCESS
Indirect access to the SRAM buffer is available to all I/O
interfaces. For the SPI interface, it is the only method
available. For PSP interfaces, it may be used in
addition to the direct access method.
Three separate pointer pairs are available for the host
microcontroller to use when accessing the SRAM:
• General Purpose Buffer Read/Write Pointer
(EGPRDPT/EGPWRPT)
• Receive Buffer Read/Write Pointer
(ERXRDPT/ERXWRPT)
• User-Defined Area Read/Write Pointer
(EUDARDPT/EUDAWRPT)
Each of these pointer pairs provides an 8-bit virtual
window register (EGPDATA, ERXDATA and EUDATA)
through which the SRAM data is read or written. The
pointers and their associated data windows are shown
in Figure 3-5.
FIGURE 3-5:
EGPDATA, ERXDATA and EUDADATA are all 8 bits
wide. When writing to them using a 16-bit PSP
interface, the low-order byte select or write enable must
be used; strobing the high byte Byte Select or Write
Enable has no effect. When reading from a 16-bit PSP
interface, one byte of useful data will be returned on the
lower 8 bits of the data bus; the upper 8 bits are to be
ignored.
When a data window register is read, the memory
contents at the address indicated by the corresponding
Read Pointer are obtained and presented to the host
microcontroller. Similarly, when a data window register
is written, the memory contents at the address
indicated by the corresponding Write Pointer are
updated by the data from the host microcontroller.
Following a read/write operation, the appropriate
pointer is automatically incremented in hardware.
POINTERS FOR INDIRECT BUFFER ACCESS
Buffer Pointers
0000h
Data Windows
Write
EGPDATA
Write
ERXDATA
EGPDATA
EGPWRPT
ERXDATA
ERXWRPT
General Purpose
Buffer
Read
EUDADATA
EUDARDPT
EUDADATA
EUDAWRPT
EUDADATA
Write
ERXST – 1
ERXST
Read
EGPDATA
EGPRDPT
Circular RX FIFO
Buffer
Read
ERXDATA
Unimplemented
DS39935C-page 34
ERXRDPT
5FFFh
EUDAST
EUDAND
2010 Microchip Technology Inc.
ENC424J600/624J600
For example, to read data from address 5402h of the
buffer:
1.
2.
Write 5402h to EGPRDPT.
Read from EGPDATA.
Following the read, the EGPRDPT value normally
increments by 1 (to 5403h in this example). If the host
subsequently wants to read from address 5403h, it can
simply perform a second read from the EGPDATA
Window register. The Write Pointer, EGPWRPT, is not
affected by the read operation.
Similarly, to write A3h to address 0007h of the buffer:
1.
2.
Write 0007h to EGPWRPT.
Write A3h to EGPDATA.
3.5.5.1
Circular Wrapping with EGPDATA
Normally, operations involving EGPDATA cause the
EGPRDPT or EGPWRPT Pointer to automatically
increment by one byte address. However, if the end of
the general purpose buffer area (ERXST – 1) is
reached, or the end of the implemented SRAM (5FFFh)
is reached, the pointer will increment to address 0000h
instead, causing subsequent accesses to wrap around
to the beginning of the SRAM buffer (Figure 3-6). The
increment behavior logic is explained in Equation 3-1.
FIGURE 3-6:
CIRCULAR BUFFER
WRAPPING USING THE
EGPDATA WINDOW
Following the write, the EGPWRPT value normally
increments by 1 (to 0008h in this example). The Read
Pointer, EGPRDPT, is not affected by the write
operation.
Each of the three pointer sets (general purpose,
receive and user-defined area) can be used to access
any address within the SRAM buffer. They differ from
each other based on their address wrapping behavior.
Applications may choose to use all three pointer
interfaces to access the RAM. This may offer maximum
application performance as it will require minimal context switching overhead when, for example, switching
from reading a received packet to reading from general
purpose RAM. However, for simplicity, some
applications may prefer to use only one or two of the
three E*DATA interfaces.
EQUATION 3-1:
0000h
General Purpose
Buffer
ERXST – 1
ERXST
Circular RX FIFO
Buffer
5FFFh
Unimplemented
POINTER INCREMENT LOGIC FOR EGPRDPT AND EGPWRPT
if EGPRDPT/EGPWRPT = ERXST – 1, then
EGPRDPT/EGPWRPT = 0000h
else if EGPRDPT/EGPWRPT = 5FFFh, then
EGPRDPT/EGPWRPT = 0000h
else
EGPRDPT/EGPWRPT = EGPRDPT/EGPWRPT + 1
2010 Microchip Technology Inc.
DS39935C-page 35
ENC424J600/624J600
3.5.5.2
Circular Wrapping with ERXDATA
FIGURE 3-7:
As with the general purpose pointers, operations with
ERXDATA normally cause the ERXRDPT or
ERXWRPT Pointer to automatically increment by one
byte address. However, if the end of the receive buffer
area (5FFFh) is reached, the pointer will increment to
the start of the receive FIFO buffer area instead, as
defined by ERXST (Figure 3-7).
CIRCULAR BUFFER
WRAPPING USING THE
ERXDATA WINDOW
0000h
General Purpose
Buffer
The receive wrapping rules for the ERXDATA interface
are identical to the buffer wrapping rules used by the
receive hardware. Therefore, this register interface is
ideally suited to reading packet data from the receive
buffer. The host controller can set the ERXRDPT value
at the start of a packet in the receive buffer and sequentially read out the entire packet contents without having
to write to the ERXRDPT Read Pointer again.
ERXST – 1
ERXST
Circular RX FIFO
Buffer
5FFFh
Unimplemented
EQUATION 3-2:
POINTER INCREMENT LOGIC FOR ERXRDPT AND ERXWRPT
if ERXRDPT/ERXWRPT = 5FFFh, then
ERXRDPT/ERXWRPT = ERXST
else
ERXRDPT/ERXWRPT = ERXRDPT/ERXWRPT + 1
3.5.5.3
Circular Wrapping with EUDADATA
The user-defined buffer area is primarily useful for
setting up a circular FIFO within the general purpose
area for use by TCP/IP stacks or other applications. The
wrap-around behavior of the user-defined buffer area is
somewhat more complicated than with the general
purpose or receive buffer cases. This is because the
user-definable boundaries set by EUDAST and
EUDAND take priority over normal wrapping behavior.
Like other pointers, EUDAST and EUDAND are fully
user-configurable from the host microcontroller. Unlike
ERXST, which must not be modified while the receive
hardware is enabled, EUDAST and EUDAND can be
modified at any time.
EQUATION 3-3:
As in the previous instances, operations with
EUDADATA normally cause the EUDARDPT or
EUDAWRPT Pointer to automatically increment by one
byte address. If the value in EUDAND is reached, the
pointer will increment to the address specified by
EUDAST instead. However, if the end of memory
(5FFFh) is reached, and EUDAND is located at some
other address, the pointer will increment to the beginning of memory (0000h). If EUDAND is set to 5FFFh,
the pointer address increments to the value of
EUDAST, instead of 0000h.
The increment
Equation 3-3.
behavior
logic
is
explained
in
POINTER INCREMENT LOGIC FOR EUDARDPT AND EUDAWRPT
if EUDARDPT/EUDAWRPT = EUDAND, then
EUDARDPT/EUDAWRPT = EUDAST
else if EUDARDPT/EUDAWRPT = 5FFFh, then
EUDARDPT/EUDAWRPT = 0000h
else
EUDARDPT/EUDAWRPT = EUDARDPT/EUDAWRPT + 1
DS39935C-page 36
2010 Microchip Technology Inc.
ENC424J600/624J600
The user-defined area start address, EUDAST, is a
read/write register. For wrapping to work correctly, the
hardware enforces 16-bit even word alignment of this
register by internally having the Least Significant bit
tied off to ‘0’. Similarly, the user-defined area end
address, EUDAND, is a read/write register that is
forced to an odd memory address. The Least Significant bit of EUDAND is internally tied to ‘1’. Applications
wishing to set up general purpose circular FIFOs in
memory using these hardware features must observe
these same alignment requirements.
user-defined area pointers will jump over the range of
addresses between EUDAND and EUDAST. This is
shown in Case 2.
If the user-defined area end address, EUDAND, is at a
higher memory address relative to the start address,
EUDAST, the buffer wraps to either EUDAST or the
beginning of memory, depending on where the
EUDARDPT or EUDAWRPT Pointers are located. This
is shown in Case 1 of Figure 3-8.
When the user-defined buffer is disabled, the host controller can use the EUDADATA interface as a second
general purpose window into RAM. Unlike the original
general purpose pointers, however, EUDARDPT and
EUDAWRPT do not wrap at the ERXST boundary,
thereby allowing access to the full SRAM buffer area.
This may be beneficial for debugging and testing
purposes where it may be desirable to read or write the
entire SRAM buffer in a single operation.
In some cases (for example, when accessing
fragmented data), it may be useful to place the
EUDAST Pointer at a higher memory address relative
to the end address. When organized in such a manner,
an “exclusion zone” in the middle of the memory range
is created; sequential read/write operations with the
FIGURE 3-8:
If the user-defined buffer is not needed, it can
effectively be disabled by setting EUDAST and
EUDAND to addresses outside of the implemented
memory area. For example, if EUDAST is set to 6000h
and EUDAND is set to 6001h, EUDARDPT and
EUDAWRPT will never reach these addresses.
Instead, they wrap from the end of implemented RAM
to its beginning, as shown in Case 3.
CIRCULAR BUFFER WRAPPING USING THE EUDATA WINDOW
0000h
User-Defined
Buffer
0000h
0000h
EUDAST
EUDAND
General Purpose
Buffer
EUDAND
General Purpose
Buffer
Excluded
Circular RX FIFO
Buffer
Circular RX FIFO
Buffer
General Purpose
Buffer
EUDAST
5FFFh
Circular RX FIFO
Buffer
5FFFh
5FFFh
EUDAST
EUDAND
Unimplemented
Unimplemented
Case 1:
EUDAND > EUDAST
Normal User-Defined Buffer
Case 2:
EUDAST > EUDAND
Case 3:
EUDAST and EUDAND > 5FFFh
User-Defined Buffer with
“Exclusion Zone”
User-Defined Buffer Disabled
2010 Microchip Technology Inc.
Unimplemented
DS39935C-page 37
ENC424J600/624J600
NOTES:
DS39935C-page 38
2010 Microchip Technology Inc.
ENC424J600/624J600
4.0
SERIAL PERIPHERAL
INTERFACE (SPI)
ENC424J600/624J600 devices implement an optional
SPI I/O port for applications where a parallel microcontroller interface is not available or is undesirable. An
SPI port is commonly available on many microcontrollers, and can be simulated in software on regular
I/O pins where it is not implemented. This makes the
SPI port ideal for using ENC424J600/624J600 devices
with the widest possible range of host controllers.
4.2
SPI Instruction Set
The SPI interface supports a unique instruction set,
consisting of 47 distinct opcodes. These include a large
number of optimized opcodes that perform a wide
range of frequently performed operations with a minimum of SPI protocol overhead. Complete Ethernet
functionality can be achieved with as few as six N-byte
opcodes. The use of the other 41 is optional; however,
doing so will generally improve overall system
performance.
The SPI opcodes are divided into four families:
4.1
Physical Implementation
The SPI port on ENC424J600/624J600 devices
operates as a slave port only. The host controller must
be configured as an SPI master that generates the
Serial Clock (SCK) signal.
This implementation supports SPI Mode 0,0, which
requires:
• SCK is Idle at a logic low state
• Data is clocked in on rising clock edges and
changes on falling clock edges
Other SPI modes that use inverted clock polarity and/or
phase are not supported.
Commands and data are sent to the device on the SI
pin. Data is driven out on the SO line on the falling edge
of SCK. The CS pin must be held low while any
operation is performed, and returned to logic high when
finished.
• Single Byte: Direct opcode instructions; designed
for task-oriented SFR operations with no data
returned
• Two-Byte: Direct opcode instruction; designed for
SFR operation with byte data returned
• Three-Byte: Opcode with word length argument;
includes read and write operations, designed for
pointer manipulation with word length data
returned
• N-Byte: Opcode with one or more bytes of
argument; includes read and write operations
designed for general memory space access with
one or more bytes of data returned
A complete summary of all opcodes is provided in
Table 4-1. A detailed explanation of each opcode family
follows.
When CS is in the inactive (logic high) state, the SO pin
is set to a high-impedance state and becomes 5V tolerant. This allows the ENCX24J600 to be connected to a
single SPI bus shared by multiple SPI slave devices
that also go to a high-impedance state when inactive.
For details on the physical connections to the interface,
see Section 2.7 “Host Interface Pins”.
2010 Microchip Technology Inc.
DS39935C-page 39
ENC424J600/624J600
TABLE 4-1:
SPI INSTRUCTION SET
Instruction
Mnemonic
Instruction
1st Byte
2nd Byte
3rd Byte
Nth Byte
Bank 0 Select
B0SEL
1100 0000
—
—
—
Bank 1 Select
B1SEL
1100 0010
—
—
—
Bank 2 Select
B2SEL
1100 0100
—
—
—
Bank 3 Select
B3SEL
1100 0110
—
—
—
System Reset
SETETHRST
1100 1010
—
—
—
Flow Control Disable
FCDISABLE
1110 0000
—
—
—
Flow Control Single
FCSINGLE
1110 0010
—
—
—
Flow Control Multiple
FCMULTIPLE
1110 0100
—
—
—
Flow Control Clear
FCCLEAR
1110 0110
—
—
—
Decrement Packet Counter
SETPKTDEC
1100 1100
—
—
—
DMA Stop
DMASTOP
1101 0010
—
—
—
DMA Start Checksum
DMACKSUM
1101 1000
—
—
—
DMA Start Checksum with Seed
DMACKSUMS
1101 1010
—
—
—
DMA Start Copy
DMACOPY
1101 1100
—
—
—
DMA Start Copy and Checksum with Seed
DMACOPYS
1101 1110
—
—
—
Request Packet Transmission
SETTXRTS
1101 0100
—
—
—
Enable RX
ENABLERX
1110 1000
—
—
—
Disable RX
DISABLERX
1110 1010
—
—
—
Enable Interrupts
SETEIE
1110 1100
—
—
—
Disable Interrupts
CLREIE
1110 1110
—
—
—
Read Bank Select
RBSEL
1100 1000
xxxx xxxx
—
—
Write EGPRDPT
WGPRDPT
0110 0000
dddd dddd
DDDD DDDD
—
Read EGPRDPT
RGPRDPT
0110 0010
xxxx xxxx
XXXX XXXX
—
Write ERXRDPT
WRXRDPT
0110 0100
dddd dddd
DDDD DDDD
—
Read ERXRDPT
RRXRDPT
0110 0110
xxxx xxxx
XXXX XXXX
—
Write EUDARDPT
WUDARDPT
0110 1000
dddd dddd
DDDD DDDD
—
Read EUDARDPT
RUDARDPT
0110 1010
xxxx xxxx
XXXX XXXX
—
Write EGPWRPT
WGPWRPT
0110 1100
dddd dddd
DDDD DDDD
—
Read EGPWRPT
RGPWRPT
0110 1110
xxxx xxxx
XXXX XXXX
—
Write ERXWRPT
WRXWRPT
0111 0000
dddd dddd
DDDD DDDD
—
Read ERXWRPT
RRXWRPT
0111 0010
xxxx xxxx
XXXX XXXX
—
Write EUDAWRPT
WUDAWRPT
0111 0100
dddd dddd
DDDD DDDD
—
Read EUDAWRPT
RUDAWRPT
0111 0110
xxxx xxxx
XXXX XXXX
—
Read Control Register
RCR
000a aaaa
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write Control Register
WCR
010a aaaa
dddd dddd
DDDD DDDD
DDDD DDDD
Read Control Register Unbanked
RCRU
0010 0000
AAAA AAAA
xxxx xxxx
XXXX XXXX
Write Control Register Unbanked
WCRU
0010 0010
AAAA AAAA
dddd dddd
DDDD DDDD
Bit Field Set
BFS
100a aaaa
dddd dddd
DDDD DDDD
DDDD DDDD
Bit Field Clear
BFC
101a aaaa
dddd dddd
DDDD DDDD
DDDD DDDD
Bit Field Set Unbanked
BFSU
0010 0100
AAAA AAAA
dddd dddd
DDDD DDDD
Bit Field Clear Unbanked
BFCU
0010 0110
AAAA AAAA
dddd dddd
DDDD DDDD
Read EGPDATA
RGPDATA
0010 1000
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write EGPDATA
WGPDATA
0010 1010
dddd dddd
DDDD DDDD
DDDD DDDD
Read ERXDATA
RRXDATA
0010 1100
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write ERXDATA
WRXDATA
0010 1110
dddd dddd
DDDD DDDD
DDDD DDDD
Read EUDADATA
RUDADATA
0011 0000
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write EUDADATA
WUDADATA
0011 0010
dddd dddd
DDDD DDDD
DDDD DDDD
Legend:
x/X = read data, d/D = write data, a = banked SFR address, A = unbanked SFR address. ‘X’ and ‘D’ are optional.
DS39935C-page 40
2010 Microchip Technology Inc.
ENC424J600/624J600
4.3
Single Byte Instructions
4.3.1
The bank select opcodes, B0SEL, B1SEL, B2SEL and
B3SEL, switch the SFR bank to Bank 0, Bank 1, Bank 2
or Bank 3, respectively. The updated bank select state
is saved internally inside the ENCX24J600 in volatile
memory. Firmware can retrieve the currently selected
SFR bank state by using the Read Bank Select
(RBSEL) opcode.
All single byte instructions are designed to perform a
simple command that affects the ENCX24J600
device’s state. In most cases, they set or clear a small
number of control bits which would otherwise require
one or more N-byte opcodes to perform. None of these
instructions return any data to the host microcontroller.
Figure 4-1 shows the timing relationships for performing
a single byte operation. The opcode (‘11xxxxx0’) is
presented on the device’s SI pin starting with the Most
Significant bit of the opcode; the Least Significant bit is
always ‘0’. The SO pin is actively driven with
indeterminate ‘1’s or ‘0’s while the CS pin is driven low.
It continues to be driven until the CS pin is returned high.
The bank select opcodes are needed to access most
SFR addresses when using the RCR, WCR, BFS and
BFC instructions. These are discussed in more detail in
Section 4.6 “N-Byte Instructions”.
Upon device power-up or System Reset, Bank 0 is
automatically selected. After Reset, hardware does not
modify the bank state again. Any value programmed by
a BxSEL opcode is retained until the next BxSEL
opcode is executed or a System Reset is issued.
Because all single byte instructions are fixed length
with no optional parameters, it is possible to execute
any instruction immediately following the execution of
any single byte instruction without deasserting the chip
select line in between.
4.3.2
FC (FLOW CONTROL) OPCODES
The flow control opcodes, FCDISABLE, FCSINGLE,
FCMULTIPLE and FCCLEAR, all modify the device’s
Flow Control mode by changing the values of the
FCOP bits (ECON1). These opcodes
execute regardless of the currently selected SFR bank.
For more information on flow control operation, see
Section 11.0 “Flow Control”.
If the CS control signal is deactivated before the 8th bit
of the opcode is sent to the ENCX24J600, indeterminate
results will occur. In some cases, the instruction is
executed or partially executed. To avoid this, it is recommended that a single byte instruction should not be
interrupted. If it is unavoidable that an instruction gets
partially executed, have the application later reissue the
same instruction and let it complete to place the device
into a known state.
4.3.3
DMA OPCODES
The DMA opcodes, DMASTOP, DMACKSUM, DMACKSUMS,
DMACOPY and DMACOPYS, modify the operation of the
device’s DMA controller, all by simultaneously changing
the values of the DMAST, DMACPY, DMACSSD and
DMANOCS control bits (ECON1). For more information on DMA operation, see Section 14.0 “Direct
Memory Access (DMA) Controller”.
There are a total of 20 single byte opcodes, which are
listed in Table 4-2. All single byte opcodes will operate
regardless of which SFR bank is selected at the time.
Those opcodes that affect multiple bits, or affect SFR
addressing, are detailed below.
FIGURE 4-1:
BxSEL OPCODES
SINGLE BYTE INSTRUCTION TIMING
CS
1
2
3
4
5
6
7
8
1
1
c5
c4
c3
c2
c1
0
x
x
x
SCK
SI
Opcode
SO
Hi-Z
x
2010 Microchip Technology Inc.
x
x
x
x
x
Hi-Z
DS39935C-page 41
ENC424J600/624J600
TABLE 4-2:
SINGLE BYTE INSTRUCTIONS
Mnemonic
Opcode
Instruction
B0SEL
1100 0000 Selects SFR Bank 0
B1SEL
1100 0010 Selects SFR Bank 1
B2SEL
1100 0100 Selects SFR Bank 2
B3SEL
1100 0110 Selects SFR Bank 3
SETETHRST
1100 1010 Issues System Reset by setting ETHRST (ECON2)
FCDISABLE
1110 0000 Disables flow control (sets ECON1 = 00)
FCSINGLE
1110 0010 Transmits a single pause frame (sets ECON1 = 01)
FCMULTIPLE
1110 0100 Enables flow control with periodic pause frames (sets ECON1 = 10)
FCCLEAR
1110 0110 Terminates flow control with a final pause frame (sets ECON1 = 11)
SETPKTDEC
1100 1100 Decrements PKTCNT by setting PKTDEC (ECON1)
DMASTOP
1101 0010 Stops current DMA operation by clearing DMAST (ECON1)
DMACKSUM
1101 1000 Starts DMA and checksum operation (sets ECON1 = 1000)
DMACKSUMS
1101 1010 Starts DMA checksum operation with seed (sets ECON1 = 1010)
DMACOPY
1101 1100 Starts DMA copy and checksum operation (sets ECON1 = 1100)
DMACOPYS
1101 1110 Starts DMA copy and checksum operation with seed (sets ECON1 = 1110)
SETTXRTS
1101 0100 Sets TXRTS (ECON1), sends an Ethernet packet
ENABLERX
1110 1000 Enables packet reception by setting RXEN (ECON1)
DISABLERX
1110 1010 Disables packet reception by clearing RXEN (ECON1)
SETEIE
1110 1100 Enable Ethernet Interrupts by setting INT (ESTAT)
CLREIE
1110 1110 Disable Ethernet Interrupts by clearing INT (ESTAT)
4.4
Two-Byte Instructions
value (00h through 03h) is returned on the SO pin, MSb
first, while the second byte is being presented on the SI
pin.
There is only one instruction in the ENCX24J600 command set which uses two SPI bytes. The Read Bank
Select opcode, RBSEL, reads the internal SFR bank
select state and returns the value to the host controller.
Because this instruction is a fixed length with no
optional parameters, it is possible to execute any
instruction following the execution of RBSEL without
deasserting the chip select line in between.
Figure 4-2 shows the timing relationships for performing the two-byte operation. The first byte of the opcode
(‘11001000’) must be presented on the SI pin, MSb
first, followed by “don’t care” values for the second byte
(9th through 16th SCK rising edges). The bank select
FIGURE 4-2:
Since this opcode does not modify the ENCX24J600
internal state, it can be aborted at any time by returning
the CS pin to the inactive state.
TWO-BYTE INSTRUCTION TIMING (RBSEL OPCODE)
CS
1
2
3
4
5
6
7
8
1
1
0
0
1
0
0
0
9
10
11
12
13
14
15
16
d
d
SCK
SI
RBSEL Opcode
SO
Hi-Z
DS39935C-page 42
x
x
x
x
x
x
SFR Bank Select
x
x
0
0
0
0
0
0
x
Hi-Z
2010 Microchip Technology Inc.
ENC424J600/624J600
4.5
Three-Byte Instructions
For write commands (shown in Figure 4-4), the opcode
byte (‘011xxx00’) must be presented on the SI line,
MSb first, followed immediately by the pointer data to
be written. Like the data returned during a read
operation, the write data must be presented MSb first,
Least Significant Byte first.
All three-byte instructions are designed to quickly read
or update the Read and Write Pointers used to access
the SRAM buffer area. Unlike the single byte instructions and RBSEL, each instruction in this group has
distinct read and write implementations.
If the application only needs to write to the lower byte of
a 16-bit pointer, it can optionally skip the upper byte by
raising chip select after the 16th clock pulse and allowing
adequate chip select hold time to elapse. The hardware
would then update the lower byte of the pointer while
maintaining the original value in the upper byte.
For read commands (shown in Figure 4-3), the opcode
byte (‘011xxx10’) must be presented on the SI pin,
MSb first, followed by “don’t care” values for the second
and third bytes (9th through 24th SCK rising edges).
Response data is returned on the SO line during the
second and third bytes.
During write operations, the device actively drives the
SO line while the chip select line is active. The value
during this interval is to be ignored.
Data on the SO line is also presented in MSb first bit
ordering. However, read commands are intended to
read a 16-bit pointer in little-endian byte ordering.
Therefore, the first byte on the SO line (returned during
SCK clocks, 9 through 16) is the lower byte of the 16-bit
pointer and is followed by the upper byte (returned
during SCK clocks 17 through 24).
All three-byte instructions, including read operations,
are considered to be finished at the end of the 24th
SCK clock (if reached). The host controller may issue
another SPI instruction or multiple fixed length
instructions without deasserting chip select.
Read operations do not affect the ENCX24J600
device’s internal state, and therefore, can be aborted at
any time by deasserting chip select.
FIGURE 4-3:
There are 12 three-byte instructions, which are divided
equally between read and write instructions. They are
listed in Table 4-3.
THREE-BYTE READ INSTRUCTION TIMING
CS
1
2
3
4
5
6
7
8
0
1
1 c4 c3 c2 1
0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
SI
Opcode
SO
Hi-Z
x
FIGURE 4-4:
x
x
x
x
Read High Byte
(optional)
Read Low Byte
x
x
x d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5 D4 D3 D2 D1 D0
x
Hi-Z
x
Hi-Z
THREE-BYTE WRITE INSTRUCTION TIMING
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0
1
1
c4 c3 c2 0
0
d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5 D4 D3 D2 D1 D0
SCK
SI
Opcode
SO
Hi-Z
x
x
x
x
2010 Microchip Technology Inc.
x
Write High Byte
(optional)
Write Low Byte
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DS39935C-page 43
ENC424J600/624J600
TABLE 4-3:
Mnemonic
THREE-BYTE INSTRUCTIONS
Opcode
Argument
3rd Byte
Instruction
1st Byte
2nd Byte
WGPRDPT
0110 0000
dddd dddd
DDDD DDDD Write General Purpose Buffer Read Pointer
(EGPRDPT).
RGPRDPT
0110 0010
xxxx xxxx
XXXX XXXX Read General Purpose Buffer Read Pointer
(EGPRDPT).
WRXRDPT
0110 0100
dddd dddd
DDDD DDDD Write Receive Buffer Read Pointer (ERXRDPT).
RRXRDPT
0110 0110
xxxx xxxx
XXXX XXXX Read Receive Buffer Read Pointer (ERXRDPT).
WUDARDPT
0110 1000
dddd dddd
DDDD DDDD Write User-Defined Area Read Pointer (EUDARDPT).
RUDARDPT
0110 1010
xxxx xxxx
XXXX XXXX Read User-Defined Area Read Pointer (EUDARDPT).
WGPWRPT
0110 1100
dddd dddd
DDDD DDDD Write General Purpose Buffer Write Pointer
(EGPWRPT).
RGPWRPT
0110 1110
xxxx xxxx
XXXX XXXX Read General Purpose Buffer Write Pointer
(EGPWRPT).
WRXWRPT
0111 0000
dddd dddd
DDDD DDDD Write Receive Buffer Write Pointer (ERXWRPT).
RRXWRPT
0111 0010
xxxx xxxx
XXXX XXXX Read Receive Buffer Write Pointer (ERXWRPT).
WUDAWRPT
0111 0100
dddd dddd
DDDD DDDD Write User-Defined Area Write Pointer (EUDAWRPT).
RUDAWRPT
0111 0110
xxxx xxxx
XXXX XXXX Read User-Defined Area Write Pointer (EUDAWRPT).
Legend: x/d = pointer data (LSB), X/D = pointer data (MSB, optional).
DS39935C-page 44
2010 Microchip Technology Inc.
ENC424J600/624J600
4.6
N-Byte Instructions
bank prior to their execution. Because of this, they
cannot be used for the unbanked SFR space (80h
through 9Fh).
N-byte instructions make up the most versatile class of
SPI commands, as they can read or write to any
addressable SFR or SRAM space. Their name comes
from their variable length nature; they require a minimum of two bytes, but can take an indefinite number of
bytes of data argument, or return an unlimited number
of output bytes. This makes them useful for reading or
writing entire arrays of data to or from the SRAM buffer.
Figure 4-5 shows the timing relationships for these
operations. Like all other opcodes, data must be
presented on the SI pin, MSb first. For all banked
instructions, the first byte of data must be the opcode,
comprised of a 3-bit prefix designating the instruction
and a 5-bit banked SFR address. If the instruction is a
write or bit field set/clear opcode, the next bytes are the
data or bit mask to be written. For read instructions, the
next bytes on the SI pin are “don’t care”.
Since these instructions are of an intrinsically variable
length, no other opcode may follow any N-byte
instruction until the CS line is driven high. Driving CS
high terminates the instruction and then places the SO
pin in a high-impedance state.
For write and bit field set/clear instructions, the SO pin
is actively driven with indeterminate ‘1’s or ‘0’s while
the CS pin is driven low. For read instructions, indeterminate data is clocked out on SO during SCK clocks,
1 through 8. Starting with the 9th clock, valid data is
clocked out byte-wise on SO, MSb first.
The format of the N-byte instructions differs depending
on if a read versus a write command is executed, and
if a banked SFR, unbanked SFR or SRAM location is
accessed. The differences are discussed in the
following sections.
4.6.1
As long as the CS pin is held low, clocks on SCK are
provided and data is presented on SI, the instruction
continues to execute indefinitely, automatically incrementing to the next register address in the SFR Bank
and writing data from SI to, or outputting data on SO
from, subsequent registers. When the end of a bank is
reached, the address automatically wraps back to the
beginning (00h) of the bank and continues; the
selected bank does not change.
BANKED SFR OPERATION
The N-byte Banked SFR instructions are WCR, RCR, BFS
and BFC. These instructions depend on the use of the
appropriate BxSEL instructions to select the proper SFR
FIGURE 4-5:
N-BYTE SPI INSTRUCTION TIMING (BANKED SFR OPERATIONS)
Write Operation
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCK
c7 c6 c5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
SI
SO
Hi-Z
x
Write 2nd Byte
(optional)
Write 1st Byte
Opcode w/SFR Address
x
x
x
x
x
x
x
x
x
x
x
x
x
Additional
x
x
x
x
x
x
x
x
x
x
x
x
x
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Read Operation
CS
1
SCK
c7 c6 c5 a4 a3 a2 a1 a0
SI
Opcode w/SFR Address
SO
Hi-Z
x
x
x
2010 Microchip Technology Inc.
x
x
x
x
Read 1st Byte
Read 2nd Byte
(optional)
Additional
x d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
DS39935C-page 45
ENC424J600/624J600
There are four banked SFR opcodes, summarized in
Table 4-4. Additional details for these opcodes are
provided below.
4.6.1.1
WCR Opcode
The Write Control Register (WCR) opcode byte consists
of the prefix, ‘010’, concatenated with the 5-bit banked
SFR address of the first register to write to. For
example, if Bank 3 were currently selected and the host
microcontroller wanted to write to the ECON2L register
at banked address 0Eh, the 8-bit opcode would be
‘01001110’ or 4Eh.
Generally, WCR can be executed on most register
addresses, in any sequence and for any length. An
important exception is when WCR is used on any MAC
or MII register. These registers must be written as a
whole 16-bit register, low byte first (e.g., MACON1
must be written by first writing to MACON1L, then
MACON1H). Writing only to the upper byte of a MAC or
MII register results in a successful write to the upper
register, while the lower register is written with indeterminate data. If a WCR instruction is aborted by raising
CS while writing to the upper byte of a MAC or MII
register, neither upper nor lower byte will be updated.
4.6.1.2
RCR Opcode
The Read Control Register (RCR) opcode byte consists
of the prefix, ‘000’, concatenated with the 5-bit banked
SFR address of the first register to read from. Using the
previous example, the 8-bit opcode to read ECON2L
would be ‘00001110’ or 0Eh.
Read operations can be performed against any register
address, in any sequence and for any length. However,
due to volatile register shadowing, it is recommended
that the ERXHEADH:ERXHEADL register pair be read
in sequence (low byte first) to obtain the correct value.
See Section 9.2 “Receiving Packets” for additional
information.
4.6.1.3
and automatic address increment, they behave almost
identically to the WCR opcode. However, instead of
absolute data to be written to a register, the host
microcontroller provides a bit mask showing which bits
of the target register need to be set or cleared.
For BFS, the ENCX24J600 performs a logical OR
operation with the supplied bit field causing ‘1’ bits in the
bit field to become set bits in the register; ‘0’ bits in the bit
field have no effect on the corresponding register bits. For
BFC, the ENCX24J600 performs a logical AND with the
complement of the supplied mask. This causes ‘1’ bits in
the mask to become clear bits in the register; ‘0’ bits in the
mask do not affect the corresponding register bits.
The host controller must use bit field operations when
attempting to change bits in a volatile control or interrupt
flag register. Normally, changing such a bit might be
accomplished
by
the
application
as
a
“read-modify-write” operation: reading the control register’s contents, modifying the register copy in memory on
the controller side and writing the modified register data
back to the ENCX24J600. In a dynamic environment,
however, one or more control bits may change state
between the read and write, resulting in an incorrect
device state after the write. As an example, assume that
the DMA module is in use (ECON1L = 1) at the
same time that the application wants to transmit a packet
(i.e., setting ECON1L). By the time a
read-modify-write on ECON1L is complete, the DMA
operation may have completed and cleared
ECON1L. In this case, the write back erroneously
starts a new DMA operation.
Using BFS and BFC allows for bit level changes to one
or more control bits without the delay of a read and
write back. In the previous example, using BFS with a
bit mask of ‘00000010’ on ECON1L, sets ECON1L
and starts a packet transmission without affecting the
status of ECON1L.
Note:
BFS and BFC Opcodes
The Bit Field Set (BFS) and Bit Field Clear (BFC)
opcodes consist of the prefix, ‘100’ (for BFS) or ‘101’
(for BFC), concatenated with the 5-bit banked SFR
address of the first register to write to. In terms of timing
TABLE 4-4:
Unlike the WCR opcode, BFS and BFC
cannot be used to modify MAC or MII
registers. Never use these opcodes on
MAC and MII registers.
N-BYTE BANKED SFR INSTRUCTIONS
Instruction
Mnemonic
Opcode
Argument
1st Byte
2nd Byte
3rd Byte
Nth Byte
Read Control Register(s)
RCR
000a aaaa
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write Control Register(s)
WCR
010a aaaa
dddd dddd
DDDD DDDD
DDDD DDDD
Bit Field(s) Set
BFS
100a aaaa
dddd dddd
DDDD DDDD
DDDD DDDD
Bit Field(s) Clear
BFC
101a aaaa
dddd dddd
DDDD DDDD
DDDD DDDD
Legend: x/X = read data (LSB/MSB), d/D = write data (LSB/MSB), a = banked SFR address.
DS39935C-page 46
2010 Microchip Technology Inc.
ENC424J600/624J600
4.6.2
UNBANKED SFR OPERATIONS
byte-wise on SO, MSb first. As with three-byte
instructions, the lower byte of a data word is presented
first, followed by the upper byte.
The N-byte unbanked SFR instructions are WCRU,
RCRU, BFSU and BFCU. These instructions use an
opcode with a one-byte address argument and do not
depend on the use of BxSEL instructions for SFR bank
selection.
As long as the CS pin is held low, the instruction
continues to execute, automatically incrementing to the
next register address in the SFR space and writing data
from SI to, or outputting data on SO from, subsequent
registers. When the end of a bank is reached, the
address continues to the top of the next bank.
Addresses continue to increment through the banks
into the unbanked SFR area (addresses 80h through
9Fh), then wrap around to the start of Bank 0 (00h). The
SFR bank value used by the BxSEL and RBSEL
opcodes is not affected by the execution of unbanked
SFR instructions.
Figure 4-6 shows the timing relationships for these
operations. Like all other opcodes, data is presented on
the SI pin, MSb first. For this class of instructions, the
first byte of data is a specific opcode; the second byte
is the 8-bit absolute address of the target SFR. If the
instruction is a write or bit set/clear opcode, the next
bytes are the data or bit mask to be written. For read
instructions, the next bytes are don’t cares.
For write and bit set/clear instructions, the SO pin is
actively driven with indeterminate ‘1’s or ‘0’s while the
CS pin is driven low. For read instructions, random data
is clocked out on SO during SCK clocks, 1 through 16.
Starting with the 17th clock, data is clocked out
FIGURE 4-6:
There are four unbanked SFR opcodes, summarized in
Table 4-5. Except for addressing, the unbanked SFR
instructions are analogous to the banked SFR instructions. However, there are certain differences in their
behavior with certain pointer registers, as noted below.
N-BYTE SPI OPCODE (UNBANKED SFR OPERATIONS)
Write Operation
CS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
0
0
1
0
0 c2 c1 0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5
SCK
SI
Opcode
SO
Hi-Z
x
Unbanked SFR Address
x
x
x
x
x
x
Write 1st Byte
x
x
x
x
x
x
x
Additional
x
x
x
x
x
x
x
x
x
x
x
x
x
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
0
0
1
0
0 c2 c1 0 a7 a6 a5 a4 a3 a2 a1 a0
Read Operation
CS
SCK
SI
Opcode
SO
Hi-Z
x
x
x
2010 Microchip Technology Inc.
x
x
Unbanked SFR Address
x
x
x
x
x
x
x
x
x
x
Read 1st Byte
Additional
x d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5
DS39935C-page 47
ENC424J600/624J600
4.6.2.1
WCRU Opcode
The Write Control Register Unbanked (WCRU) opcode
starts with the opcode, ‘00100010’ (22h), followed by
the unbanked SFR register address during SPI clocks,
9 through 16. For example, to write to ECON2L at
address 6Eh, the instruction would be ‘22h 6Eh’,
followed by the data to be written.
When the host controller is finished writing data, it should
raise the CS line, putting the device in an inactive state
and preparing it for the next SPI instruction. When finishing a WCRU transaction, ensure that adequate CS hold
time is provided for the last write to complete before
raising CS.
Generally, WCRU can be executed on most register
addresses, in any sequence and for any length. An
important exception is when WCRU is used on any MAC
or MII register. These registers must be written as
whole 16-bit registers, low byte first (e.g., MACON1
must be written by first writing to MACON1L, then
MACON1H). Writing only to the upper byte of a MAC or
MII register results in a successful write to the upper
register, while the lower register is written with indeterminate data. If a WCRU instruction is aborted by raising
CS while writing to the upper byte of a MAC or MII
register, neither the upper nor lower byte will be
updated.
In addition, WCRU cannot be used to write to the SRAM
buffer virtual data windows (EGPDATA, ERXDATA and
EUDADATA). Writing to the buffer address indicated by
the corresponding address pointers’ attempts has no
effect on the memory location, and the pointers do not
auto-increment. To write to the SRAM buffer using the
virtual data windows, always use the SRAM buffer
opcodes (WGPDATA, WRXDATA and WUDADATA)
instead.
4.6.2.2
RCRU Opcode
Read operations can be performed on most register
addresses, in any sequence and for any length.
However, due to volatile register shadowing, it is
recommended that the ERXHEADH:ERXHEADL
register pair be read in sequence (low byte first) to
obtain the correct value. See Section 9.2 “Receiving
Packets” for additional information.
Similar to WCRU, RCRU cannot be used to read data
from the SRAM buffer using the virtual data windows.
Reading the buffer address indicated by the corresponding address pointers returns indeterminant data
and the pointers do not auto-increment. To read from
the buffer using the virtual data windows, always use
the SRAM buffer opcodes (RGPDATA, RRXDATA and
RUDADATA) instead.
4.6.2.3
The Bit Field Set Unbanked (BFSU) and Bit Filed Clear
Unbanked (BFCU) opcodes start with the opcode,
‘00100100’ (24h) for BFSU, or ‘00100110’ (26h) for
BFCU, followed by the unbanked SFR register address
during SPI clocks, 9 through 16. In terms of timing and
automatic address increment, they behave almost
identically to the WCRU opcode.
BFSU and BFCU function in the same manner as BFS
and BFC, by setting or clearing individual bits in the target register through the use of a bit mask. They are also
used in the same situations as BFS and BFC; namely,
when it is necessary to manipulate a single control bit
or interrupt flag in a dynamic situation, while avoiding
the disruption of other bits. See Section 4.6.1.3 “BFS
and BFC Opcodes” for a detailed explanation.
Note 1: Unlike WCRU, BFSU and BFCU cannot be
used to modify MAC or MII registers.
Never use these opcodes on MAC and
MII registers.
2: BFSU and BFCU opcodes have no effect
on any SFR in the unbanked region
(addresses 80h through 9Fh).
The Read Control Register Unbanked (RCRU) opcode
starts with the opcode, ‘00100000’ (20h), followed by
the unbanked SFR register address during SPI clocks,
9 through 16. Continuing the previous example, to read
ECON2L at address 6Eh, the complete two-byte
instruction would be ‘20h 6Eh’.
TABLE 4-5:
BFSU and BFCU Opcodes
N-BYTE UNBANKED SFR INSTRUCTIONS
Instruction
Mnemonic
Opcode
Argument
1st Byte
2nd Byte
3rd Byte
Nth Byte
Read Control Register(s), Unbanked
RCRU
0010 0000
AAAA AAAA
xxxx xxxx
XXXX XXXX
Write Control Register(s), Unbanked
WCRU
0010 0010
AAAA AAAA
dddd dddd
DDDD DDDD
Bit Field(s) Set, Unbanked
BFSU
0010 0100
AAAA AAAA
dddd dddd
DDDD DDDD
Bit Field(s) Clear, Unbanked
BFCU
0010 0110
AAAA AAAA
dddd dddd
DDDD DDDD
Legend:
x/X = read data (LSB/MSB), d/D = write data (LSB/MSB), A = unbanked SFR address. ‘X’ and ‘D’ are optional.
DS39935C-page 48
2010 Microchip Technology Inc.
ENC424J600/624J600
4.6.3
SRAM BUFFER OPERATIONS
SO during SCK clocks, 1 through 8. Starting with the
9th clock, data is clocked out byte-wise on SO, MSb
first.
The six N-byte SRAM instructions function in a similar
manner to the banked SFR instructions, in that they use
a single byte opcode to define the operation and target
register. In terms of timing, they are virtually identical, as
shown in Figure 4-7.
As long as the CS pin is held low, the instruction
continues to execute, automatically incrementing to the
next SRAM address according to the pointer wrapping
rules described in Section 3.5.5 “Indirect SRAM Buffer
Access”. The associated read or write pointer SFRs are
automatically updated for each 8 SCK clocks. To
terminate the read or write operation, the CS signal must
be returned high.
Like all other opcodes, data is presented on the SI pin,
MSb first. For all instructions, the first byte of data is the
opcode. If the instruction is a write opcode, the next
bytes are the data to be written. For read instructions,
the next bytes are don’t cares.
There are 6 instructions divided equally between read
and write instructions. They are summarized in
Table 4-6.
For write instructions, the SO pin is actively driven with
indeterminate ‘1’s or ‘0’s while the CS pin is driven low.
For read instructions, random data is clocked out on
FIGURE 4-7:
N-BYTE SPI OPCODE (SRAM BUFFER OPERATIONS)
Write Operation
CS
1
2
3
4
5
6
7
0
0
1 c4 c3 c2 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
SCK
SI
0 d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
Opcode
SO
Hi-Z
x
Write 2nd Byte
(optional)
Write 1st Byte
x
x
x
x
x
x
x
x
x
x
x
x
x
Additional
x
x
x
x
x
x
x
x
x
x
x
x
x
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
0
0
1 c4 c3 c2 0
0
Read Operation
CS
SCK
SI
Opcode
SO
Hi-Z
x
x
x
2010 Microchip Technology Inc.
x
x
Read 1st Byte
x
x
Read 2nd Byte
(optional)
Additional
x d7 d6 d5 d4 d3 d2 d1 d0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
DS39935C-page 49
ENC424J600/624J600
TABLE 4-6:
N-BYTE SRAM INSTRUCTIONS
Instruction
Mnemonic
Opcode
Argument
1st Byte
2nd Byte
3rd Byte
Nth Byte
Read Data from EGPDATA
RGPDATA
0010 1000
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write Data from EGPDATA
WGPDATA
0010 1010
dddd dddd
DDDD DDDD
DDDD DDDD
Read Data from ERXDATA
RRXDATA
0010 1100
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write Data from ERXDATA
WRXDATA
0010 1110
dddd dddd
DDDD DDDD
DDDD DDDD
Read Data from EUDADATA
RUDADATA
0011 0000
xxxx xxxx
XXXX XXXX
XXXX XXXX
Write Data from EUDADATA
WUDADATA
0011 0010
dddd dddd
DDDD DDDD
DDDD DDDD
Legend: x/X = read data (LSB/MSB), d/D = write data (LSB/MSB). ‘X’ and ‘D’ are optional.
DS39935C-page 50
2010 Microchip Technology Inc.
ENC424J600/624J600
5.0
PARALLEL SLAVE PORT
INTERFACE (PSP)
ENC424J600/624J600 devices are designed to
interface directly with the parallel port available on
many microcontrollers, including the Parallel Master
Port (PMP) available on many Microchip PIC® microcontrollers. The Parallel Slave Port interface is highly
flexible, and can communicate using either Intel® or
Motorola® formats for read and write control strobes. In
the event that a parallel port is not available on the host
microcontroller, a software-managed parallel interface
derived from general purpose I/O pins can be used.
When the PSP interface is enabled, the ENCX24J600
functions as a slave device on the parallel bus. The
host controller must be configured to generate the
destination or target address on the slave device, as
well as the necessary port control signals.
5.1
Physical Implementation
The PSP interface is mutually exclusive with the serial
interface. To enable the PSP and disable the SPI, tie
the INT/SPISEL pin to Vss through an external resistor.
The PSP interface can use from 12 to 34 pins, depending on the device pin count and the PSP operating
mode. There are up to eight modes, covering the
permutations of data widths, data/address multiplexing
and bus strobe formats. The modes are selected by
TABLE 5-1:
In PSP mode, the CS/CS pin becomes the active-high
Chip Select (CS) pin. A weak internal pull-down is automatically connected to the pin when the PSP interface
is selected, preventing the pin from floating to an
indeterminate state when an external Chip Select
signal is absent.
When CS is in the inactive (logic-low) state, the AD15
(64-pin devices only) and AD pins are placed in
a high-impedance state and are 5V tolerant. This
allows the ENCX24J600 to share a single parallel bus
with other slave devices that function the same way
while deselected. All other PSP pins, including the
A pins (64-pin devices only) and the port control
strobes, are 5V tolerant inputs at all times. Inputs on
these pins are ignored while the chip select pin is at
logic low.
Unlike the SPI port, the use of chip select is optional
with the PSP. The CS pin can be tied permanently to
VDD if the parallel bus is not shared with other slave
devices. This saves one I/O pin from the host controller
while leaving the ENCX24J600 in a perpetually
selected state.
OPERATING MODES SUPPORTED BY THE PSP INTERFACE
Availability
PSP
Mode
tieing each of the PSPCFG pins to either VDD or
VSS. The available combinations along with relative
performance metrics are summarized in Table 5-1.
Additional information on physical connections are
provided in Section 2.7.2 “PSP”.
44-pin 64-pin
# Pins(1)
Min
Max
Data
Width
Address/Data
Multiplexing
Theoretical
Performance
@ 10 MHz
(Mbit/s)
Control Lines
1
X
19
26
8 bit
No
CS, RD, WR
80
2
X
19
26
8 bit
No
CS, EN, R/W
80
3
X
26
34
16 bit
No
CS, RD, WRL, WRH
160
X
26
34
16 bit
No
CS, R/W, B0SEL, B1SEL
160
5
X
X
12
19
8 bit
Yes
AL, CS, RD, WR
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