EVB-LAN9250

EVB-LAN9250 Evaluation Board User’s Guide  2015 Microchip Technology Inc. DS50002426A Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-927-4 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == DS50002426A-page 2 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2015 Microchip Technology Inc. Object of Declaration:  2015 Microchip Technology Inc. DS50002426A-page 3 EVB-LAN9250 Evaluation Board User’s Guide NOTES: DS50002426A-page 4  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Table of Contents Preface ........................................................................................................................... 7 Introduction............................................................................................................ 7 Document Layout .................................................................................................. 7 Conventions Used in this Guide ............................................................................ 8 The Microchip Web Site ........................................................................................ 9 Development Systems Customer Change Notification Service ............................ 9 Customer Support ................................................................................................. 9 Document Revision History ................................................................................. 10 Chapter 1. Overview 1.1 Introduction ................................................................................................... 11 1.2 References ................................................................................................... 12 1.3 Terms and Abbreviations ............................................................................. 13 Chapter 2. Board Details 2.1 Power ........................................................................................................... 15 2.2 Power-On Reset ........................................................................................... 16 2.3 Clock ............................................................................................................ 16 Chapter 3. Board Configuration 3.1 Strap Options ............................................................................................... 17 3.1.1 GPIO Straps .............................................................................................. 17 3.1.2 GPIO Header ............................................................................................. 17 3.1.3 External SoC ............................................................................................. 19 3.1.4 HBI/SPI Selection ...................................................................................... 20 3.1.5 HBI Mode Selection ................................................................................... 21 3.1.6 SPI/SQI Mode Selection ............................................................................ 23 3.1.7 I2C Aardvark® Header and SPI Storm Header ......................................... 24 3.1.8 Copper and Fiber Mode Selections ........................................................... 24 3.2 LEDs ............................................................................................................. 26 3.3 Test Points ................................................................................................... 26 3.4 Mechanicals ................................................................................................. 27 Appendix A. EVB-LAN9250 Evaluation Board A.1 Introduction .................................................................................................. 29 Appendix B. EVB-LAN9250 Evaluation Board Schematics B.1 Introduction .................................................................................................. 31 Appendix C. Bill of Materials (BOM) C.1 Introduction .................................................................................................. 39 Worldwide Sales and Service .................................................................................... 44  2015 Microchip Technology Inc. DS50002426A-page 5 EVB-LAN9250 Evaluation Board User’s Guide NOTES: DS50002426A-page 6  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Preface NOTICE TO CUSTOMERS All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available. Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document. For the most up-to-date information on development tools, see the MPLAB® IDE online help. Select the Help menu, and then Topics to open a list of available online help files. INTRODUCTION This chapter contains general information that will be useful to know before using the EVB-LAN9250. Items discussed in this chapter include: • • • • • • Document Layout Conventions Used in this Guide The Microchip Web Site Development Systems Customer Change Notification Service Customer Support Document Revision History DOCUMENT LAYOUT This document describes how to use the EVB-LAN9250 Evaluation Board as a development tool for the LAN9250. The manual layout is as follows: • Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9250 Evaluation Board. • Chapter 2. “Board Details” – Includes instructions on how to get started with the EVB-LAN9250 Evaluation Board. • Chapter 3. “Board Configuration” – Provides information about the EVB-LAN9250 Evaluation Board battery charging features. • Appendix A. “EVB-LAN9250 Evaluation Board” – This appendix shows the EVB-LAN9250 Evaluation Board. • Appendix B. “EVB-LAN9250 Evaluation Board Schematics” – This appendix shows the EVB-LAN9250 Evaluation Board schematics. • Appendix C. “Bill of Materials (BOM)” – This appendix includes the EVB-LAN9250 Evaluation Board Bill of Materials (BOM).  2015 Microchip Technology Inc. DS50002426A-page 7 EVB-LAN9250 Evaluation Board User’s Guide CONVENTIONS USED IN THIS GUIDE This manual uses the following documentation conventions: DOCUMENTATION CONVENTIONS Description Arial font: Italic characters Represents Referenced books Emphasized text A window A dialog A menu selection A field name in a window or dialog A menu path MPLAB® IDE User’s Guide ...is the only compiler... the Output window the Settings dialog select Enable Programmer “Save project before build” A dialog button A tab A number in verilog format, where N is the total number of digits, R is the radix and n is a digit. A key on the keyboard Click OK Click the Power tab 4‘b0010, 2‘hF1 Italic Courier New Sample source code Filenames File paths Keywords Command-line options Bit values Constants A variable argument Square brackets [ ] Optional arguments Curly brackets and pipe character: { | } Ellipses... Choice of mutually exclusive arguments; an OR selection Replaces repeated text #define START autoexec.bat c:\mcc18\h _asm, _endasm, static -Opa+, -Opa0, 1 0xFF, ‘A’ file.o, where file can be any valid filename mcc18 [options] file [options] errorlevel {0|1} Initial caps Quotes Underlined, italic text with right angle bracket Bold characters N‘Rnnnn Text in angle brackets < > Courier New font: Plain Courier New Represents code supplied by user DS50002426A-page 8 Examples File>Save Press , var_name [, var_name...] void main (void) { ... }  2015 Microchip Technology Inc. Preface THE MICROCHIP WEB SITE Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. The Development Systems product group categories are: • Compilers – The latest information on Microchip C compilers, assemblers, linkers and other language tools. These include all MPLAB C compilers; all MPLAB assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK object linker); and all MPLAB librarians (including MPLIB object librarian). • Emulators – The latest information on Microchip in-circuit emulators.This includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators. • In-Circuit Debuggers – The latest information on the Microchip in-circuit debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug express. • MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows Integrated Development Environment for development systems tools. This list is focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and MPLAB SIM simulator, as well as general editing and debugging features. • Programmers – The latest information on Microchip programmers. These include production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included are nonproduction development programmers such as PICSTART Plus and PIC-kit 2 and 3. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support  2015 Microchip Technology Inc. DS50002426A-page 9 EVB-LAN9250 Evaluation Board User’s Guide Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support DOCUMENT REVISION HISTORY Revision A (November 2015) • Initial Release of this Document. DS50002426A-page 10  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Chapter 1. Overview 1.1 INTRODUCTION The LAN9250 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9250 has been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9250 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE) [100Mbps only], and the IEEE 1588v2 precision time protocol. 100BASE-FX is supported via an external fiber transceiver. The LAN9250 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The integrated checksum offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading the task from the CPU. The LAN9250 also includes large transmit and receive data FIFOs to accommodate high-latency applications. In addition, the LAN9250 memory buffer architecture allows highly efficient use of memory resources by optimizing packet granularity. The LAN9250 also supports features which reduce or eliminate packet loss. The internal 16KB SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9250 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions. This manual describes the EVB designed for LAN9250 to explore its various features. Figure 1-1 shows the block diagram.  2015 Microchip Technology Inc. DS50002426A-page 11 EVB-LAN9250 Evaluation Board User’s Guide FIGURE 1-1: 1.2 LAN9250 BLOCK DIAGRAM REFERENCES Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation. Document LAN9250 Datasheet Location Visit www.microchip.com. AN8-13 Suggested Mag- http://www.microchip.com/wwwApnetics pNotes/AppNotes.aspx?appnote=en562793 EVB-LAN9250 Evaluation Board Schematic DS50002426A-page 12 Visit www.microchip.com.  2015 Microchip Technology Inc. Overview 1.3 TERMS AND ABBREVIATIONS • • • • • • • • • • EVB - Evaluation Board DNP - Do Not Populate 100BASE-TX- 100 Mbps Fast Ethernet, IEEE802.3u Compliant GPIO - General Purpose I/O HBI - Host Bus Interface SPI - Serial Peripheral Interface I2C - Inter-Integrated Circuit EEE - Energy-Efficient Ethernet SFP - Small Form-factor Pluggable SoC - System on a Chip  2015 Microchip Technology Inc. DS50002426A-page 13 EVB-LAN9250 Evaluation Board User’s Guide NOTES: DS50002426A-page 14  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Chapter 2. Board Details The following sections describe the various board features, including jumpers, LEDs, test points, system connections, and switches. A top view of the EVB-LAN9250 is shown in Figure 2-1. FIGURE 2-1: LAN9250 BOARD REV-A WITH CALL OUTS SoC Header HBI Mode Select HBI or SPI/SQI Selection Strap EEPROM Reset Power Circuit Microchip LAN9250 Port Fibre Transceiver 2.1 Port 1 (integrated magnetics & RJ45) POWER DC 5V is applied through (J1) DC Socket, powered by a +5V external wall adapter (Manufacturer: TRIAD MAGNETICS and P/N: WSU050-3000). The switch (SW1) needs to be in the ON position for the 5V to reach the 3.3V regulator. Glowing of Green LED (D1) indicates successful generation of 3.3V o/p. This Power is supplied to the LAN9250 and it has internal 1.2 V regulator which supplies power to the internal core logic.  2015 Microchip Technology Inc. DS50002426A-page 15 EVB-LAN9250 Evaluation Board User’s Guide 2.2 POWER-ON RESET A power-on reset occurs whenever power is initially applied to the LAN9250 or if the power is removed and reapplied to the LAN9250. This event resets all circuitry within the LAN9250. After initial power-on, the LAN9250 can be reset by pressing the reset switch (SW2). The reset LED D2 will assert (Red) when the LAN9250 is in reset condition. For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset release. 2.3 CLOCK The LAN9250 requires a fixed-frequency 25MHz clock source for use by the internal clock oscillator and PLL. This is typically provided by attaching a 25MHz crystal to the OSCI and OSCO pins. Manufacturer: Cardinal Components Inc and P/N: CSM1Z-A5B2C5-40-25.0D18-F DS50002426A-page 16  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Chapter 3. Board Configuration 3.1 STRAP OPTIONS The following tables describe the default settings and jumper descriptions for the EVB-LAN9250. These defaults are the recommended configurations for evaluation of the LAN9250. These settings may be changed as needed, however, any deviation from the defaults settings should be approached with care and knowledge of the schematics and datasheet. An incorrect jumper setting may disable the board. 3.1.1 GPIO Straps The GPIO/LED Controller provides 3 configurable general purpose input/output pins, GPIO[2:0]. These pins can be individually configured to function as inputs, push-pull outputs or open drain outputs and each is capable of interrupt generation with configurable polarity. Alternatively, all 3 GPIO pins can be configured as LED outputs, enabling these pins to drive Ethernet status LEDs for external indication of various attributes of the port. All GPIOs also provide extended 1588 functionality. Table 3-1 illustrates how the GPIO lines are multiplexed with other signals. TABLE 3-1: 3.1.2 GPIO STRAPS GPIO Line Multiplexed Signals GPIO 0 LED0/MNGT0/TD0 GPIO 1 LED1/MNGT1/TD1 GPIO 2 LED2/E2PSIZE GPIO Header J16 is used GPIO Header for probing purpose. Respective pin details shared in Table 3-2. TABLE 3-2: GPIO HEADER GPIO Line Multiplexed Signals GPIO 0 J16.1 GPIO 1 J16.2 GPIO 2 J16.3 In the context of using the GPIO signals as LED controller, the Jumpers J4-J9 (operated in pairs) are configured as below. For example, J4 and J7 as a pair set as ‘0’ or ‘1’, decide whether LED0 (D3) is turned on or OFF. Likewise, J6 and J9 as a pair set as ‘0’ or ‘1’, decide whether LED1 (D4) is turned on or OFF.  2015 Microchip Technology Inc. DS50002426A-page 17 EVB-LAN9250 Evaluation Board User’s Guide FIGURE 3-1: LED STRAP CIRCUIT The following subsections detail the jumper pair settings, their associated strap settings, and the functional effects of setting the straps. All strap values are read during power-up and on the rising edge of nRST signal. Once the strap value is set, the LAN9250 will drive the LED’s high or low for illumination according the strap value. For other designs which may use these pins as GPIOs refer to LAN9250 datasheet for additional information. In those cases, internal default straps must be changed by an I2C or through EEPROM fields. 3.1.2.1 GPIO/LED CONFIGURATIONS GPIO/LED configuration straps are used to configure the LEDs and GPIOs through jumpers as shown below in Table 3-3. TABLE 3-3: GPIO/LED CONFIGURATIONS Header Pin Settings Signal Name Strap Value Description J4 & J7 1-2(default) GPIO0 /LED0 1 The LED (D3) is set as active LOW./ Serial Management Mode Stratp:0=SMI 0 The LED (D3) is set as active HIGH./ Serial Management Mode Strap:1=I2C 1 The LED (D4) is set as active LOW. 0 The LED (D4) is set as active HIGH. 1 The LED (D5) is set as active LOW./ EEPROM Size=32K bits 0 The LED (D5) is set as active HIGH./ EEPROM Size=1K bits 2 -3 J5 & J8 1-2(default) GPIO1 /LED1 2 -3 J6 & J9 1-2(default) 2 -3 DS50002426A-page 18 GPIO2 /LED2  2015 Microchip Technology Inc. Board Configuration 3.1.2.2 HOST INTERFACE MODE STRAP SELECTION MNGT0 strap along with MNGT1, MNGT2 and MNGT3 configures the host mode. MNGT0 and MNGT1 are multiplexed with GPIO0 and GPIO1 signals whereas MNGT3 and MNGT4 are multiplexed with address lines A3 and A4. Table 3-4 illustrates the selection of Host mode based on the values of MNGT straps. TABLE 3-4: MANAGEMENT STRAP SELECTION MNGT1 J5 & J8 MNGT0 J4 & J7 MNGT3 SW9 MNGT2 SW10 0 0 X X SPI 0 1 0 0 HBI Multiplexed 1 Phase 8-bit 0 1 0 1 HBI Multiplexed 1 Phase 16-bit 0 1 1 0 HBI Multiplexed 2 Phase 8-bit 0 1 1 1 HBI Multiplexed 2 Phase 16-bit (Default) 1 0 X X HBI Indexed 8-bit 1 1 X X HBI Indexed 16-bit 3.1.2.3 Host Mode EEPROM SIZE CONFIGURATION The EEPROM size configuration strap (J6 & J9) [Multiplexed with GPIO2 signal] determines the supported EEPROM size range. A low selects 1Kbit (128 x 8) through 16Kbits (2K x 8)_24C16. A high selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512 as shown below in Table 3-5. TABLE 3-5: EEPROM SIZE CONFIGURATION Header Pin Settings eeprom_size_strap Value J6 & J9 1-2 (default) 1 EEPROM size = 32K bits (4k x 8) through 512K bits (64K x 8) 2 -3 0 EEPROM size = 1K bits (128 x 8) through 16K bits (2K x 8) 3.1.3 Description External SoC Purpose of External SoC is to provide HBI and SPI access to the LAN9250. P8 and P9 connectors are used for mounting external SoC Module and which is compatible with BeagleBone (TI SoC). The jumper J13 is used to provide on-board 3.3V to BeagleBone Black. TABLE 3-6: EXTERNAL SOC SETTINGS Header Default Pin Settings Signal Name J3 1-2 (Short) VDD_5V J13 1-2 (Open) VDD3V3EXP Refer to this link for a detailed discussion on BeagleBone Black: http://www.newark.com/beagle-bone-accessories?rd=beaglebone&catalogId=15003&langId=-1&storeId=10194 Figure 3-2 shows how BeagleBone Black is mounted on EVB-LAN9250.  2015 Microchip Technology Inc. DS50002426A-page 19 EVB-LAN9250 Evaluation Board User’s Guide FIGURE 3-2: 3.1.4 EVB-LAN9250 WITH BEAGLEBONE BLACK HBI/SPI Selection The EVB-LAN9250 supports two host interface modes of LAN9250: • HBI Mode (default) • SPI/SQI Mode DS50002426A-page 20  2015 Microchip Technology Inc. Board Configuration The HBI or SPI/SQI configuration is selected using the DPDT SW11 to SW13 switches. TABLE 3-7: Switch Description SW11 to SW13 Up SW11 to SW13 Down FIGURE 3-3: 3.1.5 HBI AND SPI/SQI SWITCH CONFIGURATIONS Settings HBI Mode (Default) SPI/SQI Mode SW11-SW13 HBI AND SPI/SQI MODE SELECTION HBI Mode Selection The LAN9250 supports various HBI modes. The HBI modes (Multiplexed Modes and Indexed Modes) can be selected using the SPST switches (P/N: 450301014042-Wurth Electronics) SW4 through SW6 and SW11 through SW12. The LAN9250 HBI signals are connected to the SoC through the switches. 3.1.5.1 MULTIPLEXED MODES The following four HBI Multiplexed Modes are supported: 1. 2. 3. 4. 8-bit Multiplexed single-phase mode 16-bit Multiplexed single-phase mode 8-bit Multiplexed dual-phase mode 16-bit Multiplexed dual-phase mode The BeagleBone Black will be configured by installing a specific driver available from www.microchip.com. This is required to access LAN9250 through HBI Multiplexed mode. The switch selection for Multiplexed Mode is shown in Figure 3-4. All four Multiplexed Modes utilize the same switch positions.  2015 Microchip Technology Inc. DS50002426A-page 21 EVB-LAN9250 Evaluation Board User’s Guide FIGURE 3-4: TABLE 3-8: Note: 3.1.5.2 MULTIPLEXED HBI MODE SELECTION SWITCH SELECTION FOR MULTIPLEXED MODE Switch Description SW5 Down SW14 Down SW15 Down SW7 Down SW6 Down For Switches to short 1-2, knob position must be in the 1-3 position, and vice versa. INDEXED MODE Two Indexed modes are supported, namely 8-bit and 16-bit. The BeagleBone Black will be configured by installing a specific driver available from www.microchip.com. This is required to access LAN9250 through HBI Indexed mode. Note: DS50002426A-page 22 In this mode, DIP switch SW15 to ON Position for PIC32 SoC and OFF Position for SoC.  2015 Microchip Technology Inc. Board Configuration FIGURE 3-5: TABLE 3-9: 8-BIT INDEXED MODE SWITCH SELECTION SWITCH SELECTION FOR 8-BIT INDEXED MODE Switch Note: TABLE 3-10: 3.1.6 SW5 Up SW14 Down SW15 Down SW7 Up SW6 Up For Switches to short 1-2, knob position must be in the 1-3 position, and vice versa. FIGURE 3-6: Note: Description 16-BIT INDEXED MODE SWITCH SELECTION SWITCH SELECTION FOR 16-BIT INDEXED MODE Switch Description SW5 Down SW14 Up SW15 Up SW7 Down SW6 Down For Switches to short 1-2, knob position must be in the 1-3 position, and vice versa. SPI/SQI Mode Selection The LAN9250 supports SPI/SQI Mode. The SPI/SQI Mode will be selected using the DPDT SW11 to SW13 switches as shown in Figure 3-3.  2015 Microchip Technology Inc. DS50002426A-page 23 EVB-LAN9250 Evaluation Board User’s Guide 3.1.7 I2C Aardvark® Header and SPI Storm Header 3.1.7.1 I2C AARDVARK HEADER J10 connector is used for I2C Aardvark header. Respective pin details are given in Table 3-11. PIN NAMES FOR I2C AARDVARK HEADER TABLE 3-11: 3.1.7.2 Signal Name Pin Number I2C2_SCL J10.1 I2C2_SDA J10.3 GND J10.2 & J10.10 SPI STORM HEADER J10+J11 connectors are used for SPI Storm header. Respective pin details are given in Table 3-12. TABLE 3-12: 3.1.8 PIN NAMES FOR SPI STORM HEADER Signal Name Pin Number SIO1 J10.5 SCK J10.7 SCS# J10.9 SIO0 J10.8 SIO2 J11.3 SIO3 J11.4 GND J10.2, J10.10, J11.1 & J11.2 Copper and Fiber Mode Selections The LAN9250 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In 100BASE-FX operation, the presence of the receive signal is indicated by the external transceiver as either an open drain, CMOS level, Loss of Signal (SFP) or a LVPECL Signal Detect (SFF). This EVB supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) in SFP mode. By default, Copper Mode is active. Fiber Mode is supported as an assembly option. To select the Copper or Fiber Mode, the respective strap and signal routing resister assembly options must be configured. Note: 3.1.8.1 Vendor part number for SFP Transceiver: Finisar/FTLF1217P2. COPPER MODE The EVB-LAN9250 is set to Copper Mode by default. Table 3-13 details the required strap resistors settings for Copper Mode operation. TABLE 3-13: Resistors Signal Names Description R55 (10K) FXLOSEN Copper twisted pair for port 1 further determined by FXSDENA R51 (10K) FXSDA Configures Port 1 to Copper Mode Note: DS50002426A-page 24 COPPER MODE STRAP RESISTORS R54 and R50 must not be populated (DNP).  2015 Microchip Technology Inc. Board Configuration Additionally, the signal routing resistors detailed in Table 3-14 must be assembled for Copper Mode operation. TABLE 3-14: Note: 3.1.8.2 COPPER MODE SIGNAL ROUTING RESISTORS Resistors Description R17, R19, R21, R23 Port 1 Copper mode is Enabled R16, R18, R20, R22 (0402 package) must not be populated (DNP). FIBER MODE The LAN9250 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the respective strap and signal routing resisters must be configured. Note: Copper Mode related resistors must be DNP while Fiber Mode is active (refer to Section 3.1.8.1 “Copper Mode”). Table 3-15 details the required strap resistor settings for Fiber Mode operation. TABLE 3-15: Note: FIBER MODE STRAP RESISTORS Resistors Description R54 Port 0 Fiber mode is Enabled R50 Port 1 Fiber mode is Enabled R51 and R55 must not be populated (DNP). Additionally, the signal routing resistors detailed in Table 3-16 must be assembled as well for Fiber Mode operation. TABLE 3-16: Note: 3.1.8.3 FIBER MODE SIGNAL ROUTING RESISTORS Resistors Description R16, R18, R20, R22 Port 1 Fiber mode is Enabled R17, R19, R21, R23 (0402 package) must not be populated (DNP). FX-LOS FIBER MODE STRAP FX-LOS strap details are shown in Table 3-17. These strap settings determine if the ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode. TABLE 3-17: FX-LOS MODE STRAP SETTINGS R77 (10K) R79 (10K) Reference Voltage (v) Function Populate DNP 3.3 A level above 2V selects FX-LOS for Port 1 DNP Populate 0 (Default) A level of 0V selects FX-SD / Copper twisted pair for Port 1, further determined by FXSDA Note:  2015 Microchip Technology Inc. The above strap details describe the LAN9250 function. This EVB does not support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable. DS50002426A-page 25 EVB-LAN9250 Evaluation Board User’s Guide 3.2 LEDS LED details are shown in Table 3-18. TABLE 3-18: 3.3 LEDS Reference Color Indication D1 Green 3.3V Power active D2 Red LAN9250 is in reset condition Description Connection TP1 Single-pin populated 5V 5V_EXT TP2 Single-pin populated 3V3 3V3 TP3 Single-pin populated GND GND TP4 Single-pin populated GND GND TP5 Single-pin unpopulated VDDCR VDDCR/1.2V TEST POINTS Test points are shown in Table 3-19. TABLE 3-19: TEST POINTS Test Points DS50002426A-page 26  2015 Microchip Technology Inc. Board Configuration 3.4 MECHANICALS Figure 3-7 details for EVB-LAN9250 mechanical dimensions. Dimensions are in mm. FIGURE 3-7:  2015 Microchip Technology Inc. EVB-LAN9250 MECHANICAL DIMENSIONS DS50002426A-page 27 EVB-LAN9250 Evaluation Board User’s Guide NOTES: DS50002426A-page 28  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Appendix A. EVB-LAN9250 Evaluation Board A.1 INTRODUCTION This appendix shows the EVB-LAN9250 Evaluation Board. FIGURE A-1: EVB-LAN9250 EVALUATION BOARD  2015 Microchip Technology Inc. DS50002426A-page 29 EVB-LAN9250 Evaluation Board User’s Guide NOTES: DS50002426A-page 30  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Appendix B. EVB-LAN9250 Evaluation Board Schematics B.1 INTRODUCTION This appendix shows the EVB-LAN9250 Evaluation Board Schematics.  2015 Microchip Technology Inc. DS50002426A-page 31 POWER SUPPLY & RST POWER SUPPLY U1 5V_SW EN12_1 R1 2A/0.05DCR 2 Switch, SPDT, Slide P/N:1101M2S3CQE2 J1 2 1 0E C2 10uF 25V VIN ENABLE VOUT TRIM 3_Amp GND C3 4 5 R2 1K VOUT_3V3 C1 3 OKR-T/3-W12-C 0.1uF R3 3.30K 1% R4 470E 1% (Ra) (Rb) R4A 33E 1% C4 C5 10uF 4.7uF DNP 1 FB1 2 3 A 1 0.1uF D1 GRN C 5V_EXT 3 3V3 3V3 "3V3 Present" 1 TP2 ORANGE 3 V REGULATOR, 3A ( 3V3 fixed when Rb=470E) 5V SW1 2 TP1 RED 3V3 3V3 3V3 RESET NDS355AN_NMOS 1 3 R8 1K D RST# Q1 1 G 5 RESET# 3 MR# 2 3V3 VDD 4 5 U2 2 1/10W 1% 2 sw_pb_2P 1 R7 100 GND SW2 R5 4.75K 1% 0.1uF 2 1 C6 R6 10.0K 1/10W 1% S U3 2 4 TPS3125 74LVC1G14 1 R9 2.2K 1 3 SOT23_5 Threshold = 2.64V Delay = 180ms A D2 RED "Reset" Reset Generator  2015 Microchip Technology Inc. TP3 BLACK TP4 BLACK C 2 EVB-LAN9250 Evaluation Board User’s Guide DS50002426A-page 32 FIGURE B-1: LAN9250 (PART1) Power Supply Filtering VDD33TXRX1 0.1uF C27 18pF REG_EN R10 12.1K 1% RBIAS 7 57 RST# 11 IRQ 44 ATEST/FXLOSEN 8 41 I2C2_SCL I2C2_SDA 43 42 GPIO0 GPIO1 GPIO2 48 46 45 C20 C21 C22 470pF 0.1uF 0.1uF C19 1uF Low ESR C16 C14 C15 C13 C17 0.1uF 0.1uF 0.1uF 0.1uF 56 59 VDD12TX1 VDD12TX2 6 24 38 VDDCR1 VDDCR2 VDDCR3 14 20 32 37 47 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 58 5 VDD33BIAS VDD33 OSCVDD12 OSCI OSCO OSCVSS FXSDENA/FXSDA/FXLOSA INT PORT0 1 3 1 2 4 REG_EN RBIAS RST# TXNA TXPA RXNA RXPA 9 FXSDA/FXLOSA 52 53 54 55 TXNA TXPA RXNA RXPA IRQ ATEST/FXLOSEN TESTMODE EESCL/TCK EESDA/TMS Reserved1 Reserved2 Reserved3 Reserved4 I2C OSCI OSCO 3V3 OSC 25.000MHz 25ppm Y1 OTHER SIGNALS 18pF 2 C26 POWER Note: OSCVSS need to connect to Chip gnd. VDD33TXRX1 VDD33TXRX2 U4A 51 64 VDD12TX1 VDD12TX2 0.1uF FB5 2A/0.05DCR BLM18EG221SN1D C18 C25 0.1uF BLM18EG221SN1D C24 C12 DNP TP5 SMT VDDCR 0.1uF 2A/0.05DCR C23 1.0uF DNP 3V3 2A/0.05DCR 1.0uF 3V3 FB4 C11 3V3 0.1uF VDD33TXRX2 0.1uF FB3 C8 0.1uF C7 1.0uF DNP VDDCR VDD12TX1 VDD12TX2 C9 2A/0.05DCR DNP 1.0uF FB2 3V3 C10 3V3 VDD33TXRX1 VDD33TXRX2  2015 Microchip Technology Inc. FIGURE B-2: Reserved5 63 62 61 60 10 GPIO0/LED0/TDO/LEDPOL0/MNGT0 GPIO1/LED1/TDI/LEDPOL1/MNGT1 GPIO2/LED2/LEDPOL2/E2PSIZE DS50002426A-page 33 Schematics LAN9250 65 GND GPIO COPPER MODE INTERFACE /,1.$&7 R25 330E LED2_ANODE LED2_CATHODE VDD33TXRX1 FB6 TXPA DNP R16 R17 0E 0E TXNA DNP R18 R19 0E 0E FX_SFP-TXPA R11 49.9 1/10W 1% R12 49.9 1/10W 1% R13 49.9 1/10W 1% R14 49.9 1/10W 1% R15 0E 9 GRN 1 COP-TXPA 4 FX_SFP-TXNA 10 C 0E 2 COP-TXNA A 3257 T1 Pulse J0011D01BNL RJ45 XMIT TD+ 75 75 1 TXCT 4&5 TD- 2 'HIDXOWDVVHPEO\ LED1 (Green) = LINK/ACT 50V 10% 7 8 6 1000 pF NC CHS GND 13 Note: Capacitors C28 through C31 are optional for EMI purposes and are not populated on the LAN9250 evaluation board. These capacitors are required for operation in an EMI constrained environment. 2 kV YEL A1 DNP C31 10pF 50V 5% 12 DNP C30 10pF 50V 5% RD- C1 DNP C29 10pF 50V 5% 3 7&8 RXCT GND DNP C28 10pF 50V 5% C32 0.022uF 75 11 6 COP-RXNA 75 MTG1 FX_SFP-RXNA RD+ MTG 5 0E 0E LED2 (Yellow) = SPEED RCV 3 COP-RXPA 16 FX_SFP-RXPA 15 DNP R22 R23 0E 0E GND1 RXNA DNP R20 R21 14 RXPA R26 R24 0E RES1210 LED0_CATHODE 63((' 330E LED0_ANODE EVB-LAN9250 Evaluation Board User’s Guide DS50002426A-page 34 FIGURE B-3:  2015 Microchip Technology Inc.  2015 Microchip Technology Inc. FIGURE B-4: SFP INTERFACE 3V3 R27 82 R28 82 R29 49.9 R30 49.9 Note:Place capacitors, and resistors close to FOT C33 0.1uF C34 0.1uF C35 0.1uF Fiber Port 1 :SFP Interface Assemble 0E at C33,C34,C35,C36 FX_SFP-RXNA FX_SFP-RXPA FX_SFP-TXPA DNP R31 100 C36 DNP C37 10uF 16V SFP_RD+ SFP_RD- SFP_TDSFP_TD+ R33 130 L1 SFP_VCCR FX_SFP-TXNA R32 130 3V3 SFP_VCCT 0.1uF + 1uH C38 0.1uF + C40 0.1uF 1uH VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3 20 19 18 17 16 15 14 13 12 11 L2 C39 10uF 16V Note:Place resistors close to J2 FTLF1217P2 R34 4.7K R35 4.7K 31 30 29 28 27 26 25 24 23 22 21 + C42 0.1uF 1 2 3 4 5 6 7 8 9 10 SFP_VCCT VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1 ASIC 31 30 29 28 27 26 25 24 23 22 21 C41 10uF 16V R36 4.7K R37 4.7K FXSDA/FXLOSA Schematics DS50002426A-page 35 1RWH)LEHUPRGHUHODWHGFRPSRQHQWVDUH1RW3RSXODWHGRQ(9%'HIDXOW 3V3 GPIO [0:2] & LED_POL_Strap  2 J5 2 1 R44 10.0K R45 10.0K 7 2 2 2 SCL WP 2K 5 I2C2_SDA I2C2_SDA 6 I2C2_SCL I2C2_SCL 1RWH8,&',36RFNHW'LIIHUHQWVL]HVFDQEHPRXQWHG ,&((3520/RZHUVL]H%HORZ..; ,&((3520+LJKHUVL]H $ERYH..; >'HIDXOW.%,7@ 2   GPIO2 3 1 J8 3 1 SDA DNP R49 1K J9 3 A0 A1 A2 24FC04 2 2 1 GPIO0 1 2 3 LED1_CATHODE DNP R48 1K  J7 0E R46 10.0K LED0_CATHODE LED2_CATHODE DNP R47 1K R38 HDR_1x3 LED1_ANODE 1 2 1 LED0_ANODE LED2_ANODE 0.1uF VCC  J6 3 1 3 1 3 1  J4 1 2 3 2K U5 J15 GPIO0 GPIO1 GPIO2 8 GPIO1 R43 R42 3V3 GPIO2 GND 3V3 GPIO0 4 3V3 3V3 C43 I2C EEPROM GPIO1 FX_Mode_Strap_1 3V3 Management Strap Selection LED0_ANODE LED0_CATHODE LED0_ANODE LED0_CATHODE LED1_ANODE LED1_CATHODE LED2_ANODE LED2_CATHODE LED2_ANODE LED2_CATHODE DNP 63(('3RUW 2 D3 1 C GRN A D4 1 GRN A )8//'83/(; 2 C DNP /,1.$&73RUW 2 D5 1 C GRN A 01*7 01*7 01*7 01*7 J5 & J8 J4 & J7 SW9 SW10   ; ; 63,     +%,0XOWLSOH[HG3KDVHELW     +%,0XOWLSOH[HG3KDVHELW 3257 02'(     +%,0XOWLSOH[HG3KDVHELW 3257     +%,0XOWLSOH[HG3KDVHELW'HIDXOW &RSSHU 'HIDXOW )LEHU   ; ; +%,,QGH[HGELW   ; ; +%,,QGH[HGELW R50 DNP 10K R51 10K +26702'( FXSDA/FXLOSA 3RXSXODWH '13 5 5 5 5 FX_Los_Strap_1 3V3 6LJQDO1DPH /('32/ 01*7  2015 Microchip Technology Inc. /('32/ 01*7 /('32/ ((6,=( /RJLF &RQQHFWRU  --   --   --   --   --   --  /('3RODULW\6WUDS 7KH/('LVVHWDVDFWLYHKLJK 6HULDO0DQDJHPHQW0RGH6WUDWS ,& 7KH/('LVVHWDVDFWLYHORZ 6HULDO0DQDJHPHQW0RGH6WUDWS 60, 7KH/('LVVHWDVDFWLYHKLJK 7KH/('LVVHWDVDFWLYHORZ 5 5 3RXSXODWH '13 '13 'HIDXOW 3RXSXODWH 'HIDXOW 5HI9ROWDJH 9  'HIDXOW R54 10K DNP )XQFWLRQ $ERYH9VHOHFWV);/26IRUSRUWV /HYHORI96HOHFWV);6'FRSSHUWZLVWHGSDLU IRU3RUWIXUWKHUGHWHUPLQHGE\);6'$ 7KH/('LVVHWDVDFWLYHKLJK ((35206L]H .ELWV[WKURXJK.ELWV.[ 7KH/('LVVHWDVDFWLYHORZ ((35206L]H .ELWV.[WKURXJK.ELWV.[RU0ELWV.[/$1RQO\ *=Short (Default) ATEST/FXLOSEN R55 10K EVB-LAN9250 Evaluation Board User’s Guide DS50002426A-page 36 STRAP, GPIO, I2C & FX-LOS FIGURE B-5: LAN9250 (PART 2) 3V3 1 2 3 7 A0 A1 A2 SCL WP SW DIP-4/SM 'HIDXOW2))SRVLWLRQ 2K SDA 5 I2C1_SDA 6 I2C1_SCL I2C EEPROM Only for Host SOC 18 PME_LATCH1 4 24FC512 2K 8 I2C3_1 I2C3_2 I2C3_3 I2C3_7 VCC 4.7K 4.7K 1 2 3 4 31 30 28 RD_RDWR WR_ENB CS U6 GND 8 7 6 5 4.7K SW3 A4/MNGT3 A3/MNGT2 A2/ALEHI A1/ALELO R61 C44 0.1uF R60 U4B R59 R58 Host SOC EEPROM R57 R56 3V3 4.7K  2015 Microchip Technology Inc. FIGURE B-6: 34 FIFOSEL_LATCH0 P8 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 AD7 AD3 GPMC_OEN_REN GPMC_WEN AD12 AD10 AD14 AD5 AD1 CS PME_LATCH1 FIFOSEL_LATCH0 A3_SOC A1_SOC AD6 AD2 ALELO GPMC_BE0N_CLE AD13 AD9 AD15 AD11 AD8 FIFOSEL SYS_RESETN GPMC_DIR I2C2_SDA I2C1_SDA J14 2 1 Open SIO3 SCS# SIO1 AD15 2 A0 3 ALELO 2 A1 3 SW6 *(1-2) 1 ALEHI 2 A2 3 2 RST_GPIO 1 D6 2 3 SW8 *(1-3) 1 RST# JS102011CQN DIODE GPMC_DIR 2 GPMC_OEN_REN 3 GPMC_BE0N_CLE 2 GPMC_WEN 3 SW14 *(2-3) 1 A4_SOC A3_SOC A2_SOC A1_SOC A0_SOC A4_SOC A2_SOC A0_SOC 10 9 8 7 6 3V3 1 2 3 4 5 A4_MNGT3 A3_MNGT2 A2 A1 A0 SW9 10.0K 1 A4_MNGT3 R62 VDD3V3EXP VDD_5V 1 1 C45 DNP I2C1_SCL 1 ALEHI 2 J12 I2C2_SCL J12 = Open 3 *(1-3) SW9 SW14 & 15 SW10 10.0K 1 2 3 *(1-2) SW10 Short 1-2 = Knob position 1-3 JS102011CQN Aardvark / SPI Storm- Connector J10 HBI or SPI Config selection Short 1-2 & 4-5 for HBI Config I2C2_SCL I2C2_SDA SIO1 R64 SCK R65 SCS# 0 0 1 3 5 7 9 2 4 6 8 10 R66 0 SIO0 Short 2-3 & 5-6 for SPI+GPIO Config SW11 AD3 AD3_SIO3 SIO3 1 2 3 4 5 6 AD5 AD5_SCS# SCS# J11 SIO2 SIO3 AD1 AD1_SIO1 SIO1 1 2 3 AD9 AD9_SCK SCK 1 2 3 3 4 1 2 J10 - SPI AARDVAR HEADER J10+J11 - SPI STROM HEADER 4 5 6 AD2 AD2_SIO2 SIO2 4 5 6 AD0 AD0_SIO0 SIO0 SW13 HEADER 23x2 JS102011CQN 3V3 SW12 RST_GPIO SW15 *(2-3) 1 WR_ENB Short 1-3 = Knob position 1-2 SW11,SW12,SW13 = Short 1-2 & 4-5 for HBI Config SIO2 SIO0 SCK RD_RDWR JS102011CQN Short 1-3 = Knob position 1-2 Default : OFF position For TI SOC INDEX MODE: OFF position 3V3 power to SOC board 3V3 5V from EVB Board 2 J13 Open 2 J3 Short 5V power to 0.1uF SOC board from EVB Board 2 JS102011CQN 219-5MST ALEHI_A2 JS102011CQN Short 1 -2 = To Reset ASIC from SoC-GPIO Short 2-3 = To Reset SoC from ASIC SW4 ON ALELO_A1 JS102011CQN SW7 *(1-2) 1 SYS_RESETN A0_AD15 JS102011CQN Board to Board Connectors for SoC HBI or SPI selection *=Short (Default) Schematics DS50002426A-page 37 IRQ A0_AD15 AD14 AD13 AD12 AD11 AD10 AD9_SCK AD8 AD7 AD6 AD5_SCS# AD4 AD3_SIO3 AD2_SIO2 AD1_SIO1 AD0_SIO0 AD4 AD0 P9 VDD3V3EXP VDD_5V 33 15 16 21 22 23 19 40 39 36 50 49 35 12 13 17 LAN9250 R63 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 SW5 to 7 Short 1-2 = Knob position 1-3 SW8 Short 1-3 = KnobSW5 position *(1-2) 1-2 1 A0/D15/AD15 D14/AD14 D13/AD13 D12/AD12 D11/AD11 D10/AD10 D9/AD9/SCK D8/AD8 D7/AD7 D6/AD6 D5/AD5/SCS# D4/AD4 D3/AD3/SIO3 D2/AD2/SIO2 D1/AD1/SO/SIO1 D0/AD0/SI/SIO0 PME A3_MNGT2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 A4_MNGT3 A3_MNGT2 ALEHI_A2 ALELO_A1 RD/RD_WR WR/ENB CS HEADER 23x2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 27 26 29 25 EVB-LAN9250 Evaluation Board User’s Guide NOTES: DS50002426A-page 38  2015 Microchip Technology Inc. EVB-LAN9250 EVALUATION BOARD USER’S GUIDE Appendix C. Bill of Materials (BOM) C.1 INTRODUCTION This appendix includes the EVB-LAN9250 Evaluation Board Bill of Materials (BOM).  2015 Microchip Technology Inc. DS50002426A-page 39 EVB-LAN9250 EVALUATION BOARD BILL OF MATERIALS Item Qty Reference Part PCB Footprint DNP Manufacturer Manufacturer Part Number 2 2 C2,C4 10uF CAP0805 No Murata GRM21BR61E106KA73L 3 18 C3,C5,C6,C8,C10,C11,C13,C14,C15, 0.1uF C16,C17,C18,C21,C22,C24,C25,C43, C44 CAP0603 No Murata GRM155R61E104KA7D 5 1 C19 1uF CAP0603 No Murata GRM188R61C105KA93D 6 1 C20 470pF CAP0603 No Murata GRM033R71E471KA01D 7 2 C26,C27 18pF CAP0603 No Murata GRM1885C1H180JA01D 9 1 C32 0.022uF CAP0603 No Kemet C0603C223K5RACTU 12 2 D1,D4 GRN LED0603 No Wurth electronics 150 060 GS7 500 0 13 1 D2 RED LED0603 No Wurth electronics 150 060 RS7 500 0 15 1 D6 DIODE SOD123 No Micro Commercial Co 1N4148W-TP RES0603  2015 Microchip Technology Inc. 16 6 FB1,FB2,FB3,FB4,FB5,FB6 2A/0.05DCR No Murata BLM18EG221SN1D 17 1 J1 SKT_PWR_2R0mm_4A_THRU_RA th_conn_pwrjack_dc-210_rt No Cui Stack PJ-002AH 19 4 J3,J12,J13,J14 CONN_2P th_conn_1x2p No FCI 68000-102HLF 20 7 J4,J5,J6,J7,J8,J9,J16 HDR_1x3 TH_CONN_1X3P No FCI 68000-103HLF 21 1 J10 HEADER 5X2 TH_CONN_2X5P No FCI 67997-210HLF 22 1 J11 HEADER 2X2 TH_CONN_2X2P No FCI 67997-204HLF 24 2 P8,P9 HEADER 23x2 TH_CONN_2X23P_F No FCI 67996-8 46 150 030 LF 25 1 Q1 NDS355AN_NMOS sot23-NDS No Fairchild NDS355AN 26 2 R2,R8 1K RES0603 No Panasonic ERJ-3GEYJ102V 27 6 R1,R15,R38,R64,R65,R66 0E RES0603 No Panasonic ERJ-3GEY0R00V 28 1 R3 3.30K RES0603 No Yageo America 9C06031A3301FKHFT 29 1 R4 470E RES0603 No BOURNS CR0603-FX-4700ELF 30 1 R5 4.75K RES0603 No Panasonic ERJ-3EKF4751V 31 8 R6,R44,R45,R46,R51,R55,R62,R63 10.0K RES0603 No Panasonic ERJ-3EKF1002V 32 1 R7 100E RES0603 No Panasonic ERJ-3EKF1000V 33 1 R9 2.2K RES0603 No Panasonic ERJ-3GEYJ222V 34 1 R10 12.1K RES0603 No Rohm MCR01MZPF1202 35 4 R11,R12,R13,R14 49.9E RES0603 No Yageo America 9C06031A49R9FKHFT 38 4 R17,R19,R21,R23 0E RES0402 No Panasonic ERJ-2GE0R00X 39 1 R24 0E RES1210 No Vishay CRCW12100000Z0EA 40 2 R25,R26 330E RES0603 No Panasonic ERJ-3GEYJ331V EVB-LAN9250 Evaluation Board User’s Guide DS50002426A-page 40 TABLE C-1:  2015 Microchip Technology Inc. TABLE C-1: EVB-LAN9250 EVALUATION BOARD BILL OF MATERIALS (CONTINUED) Item Qty Reference Part PCB Footprint DNP Manufacturer Manufacturer Part Number 46 1 R4A 33E RES0603 No BOURNS CR0603-FX-33R0ELF 47 4 R42,R43,R60,R61 2K RES0603 No Panasonic ERJ-3GEYJ202V 51 4 R56,R57,R58,R59 4.7K RES0603 No Panasonic ERJ-3EKF4701V 54 1 SW1 SW-SPDT-SLIDE sw_ck_1101m2s3cqe2 No C&K 1101M2S3CQE2 55 1 SW2 sw_pb_2P sw_pb_2P No Panasonic EVQ-PJU04K 56 1 SW3 SW DIP-4/SM TH_SW_DIP4 No Wurth electronics 418117270904 57 1 SW4 219-5MST SW_DIP_5P-219-5MST No CTS Electrocomponents 219-5MST 58 8 SW5,SW6,SW7,SW8,SW9,SW10,SW JS102011CQN 14,SW15 TH_SW_SPST_3P_10x2p5 No Wurth electronics 450301014042 59 3 SW11,SW12,SW13 JS202011CQN TH_SW_DPDT_6P No C&K JS202011CQN 60 1 TP1 RED TH_TP_60D40 No Keystone 5000 61 1 TP2 ORANGE TH_TP_60D40 No Keystone 5003 62 2 TP3,TP4 BLACK TH_TP_60D40 No Keystone 5001 64 1 T1 Pulse - J0011D01BNL th_conn_pulse_rj45_j0026 No Pulse Electronics J0011D01BNL 65 1 U1 3_Amp TH_DC-DC_VERT_5PIN_P67 No Murata OKR-T/3-W12-C 66 1 U2 TPS3125 SOT23_5 No TI TPS3125L30DBVR 67 1 U3 74LVC1G14 SOT23_5 No TI SN74L VCIG14DBVR 68 1 U4 LAN9250 IC_QFN64 No Microchip LAN9250 24FC512-I/P 1 U5,U6 24FC512 IC_DIP8_300 No Microchip 71 1 Y1 25.000MHz XTAL_HCM49 No Cardinal Components Inc. CSM1Z-A5B2C5-40-25.0D18-F TABLE C-2: DNP COMPONENTS Item Qty Reference Part PCB Footprint DNP DS50002426A-page 41 1 1 C1 4.7uF CAP0603 DNP 4 4 C7,C9,C12,C23 1.0uF CAP0603 DNP 8 4 C28,C29,C30,C31 10pF CAP0402 DNP 10 8 C33,C34,C35,C36,C38,C40,C42,C45 0.1uF CAP0603 DNP 11 3 C37,C39,C41 10uF CAP_B_3528 DNP 14 2 D3,D5 GRN LED0603 DNP 18 1 J2 FTLF1217P2 CONN_FX_SFP_FTLF1217P2 DNP 23 2 L1,L2 1uH L0805 DNP 37 4 R16,R18,R20,R22 0E RES0402 DNP 41 2 R27,R28 82E RES0603 DNP Bill of Materials (BOM) 70 DNP COMPONENTS (CONTINUED) Item Qty Reference Part PCB Footprint DNP 42 2 R29,R30 49.9E RES0603 DNP 43 1 R31 100E RES0603 DNP 44 2 R32,R33 130E RES0603 DNP 45 4 R34,R35,R36,R37 4.7K RES0603 DNP 48 3 R47,R48,R49 1K RES0603 DNP 49 2 R50,R54 10K RES0603 DNP 63 1 TP5 SMT tp-smd40 DNP  2015 Microchip Technology Inc. EVB-LAN9250 Evaluation Board User’s Guide DS50002426A-page 42 TABLE C-2: Bill of Materials (BOM) NOTES:  2015 Microchip Technology Inc. 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