EVB-LAN9252-4PORT
EtherCAT® ESC Expansion Mode
Evaluation Board
User’s Guide
2014-2015 Microchip Technology Inc.
DS50002404A
Note the following details of the code protection feature on Microchip devices:
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Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,
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© 2014-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-682-2
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS50002404A-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2014-2015 Microchip Technology Inc.
Object of Declaration: EVB-LAN9252-4PORT
2014-2015 Microchip Technology Inc.
DS50002404A-page 3
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
NOTES:
DS50002404A-page 4
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT
ETHERCAT® ESC EXPANSION MODE
USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 7
Introduction............................................................................................................ 7
Document Layout .................................................................................................. 7
Conventions Used in this Guide ............................................................................ 8
The Microchip Web Site ........................................................................................ 9
Development Systems Customer Change Notification Service ............................ 9
Customer Support ................................................................................................. 9
Document Revision History ................................................................................. 10
Chapter 1. Overview
1.1 Introduction ................................................................................................... 11
1.2 References ................................................................................................... 13
Chapter 2. Board Details & Configuration
2.1 Power ........................................................................................................... 15
2.1.1 +5V Power ................................................................................................. 15
2.2 Reset ............................................................................................................ 15
2.3 Clock ............................................................................................................ 15
2.4 Configuration ................................................................................................ 16
2.4.1 Expansion Mode ........................................................................................ 16
2.4.2 Strap Options ............................................................................................ 19
2.4.3 LED Indicators ........................................................................................... 22
2.4.4 EEPROM Switch ....................................................................................... 23
2.4.5 SoC ........................................................................................................... 23
2.4.6 SPI/SQI/I2C Aardvark® ............................................................................. 26
2.5 Mechanicals ................................................................................................. 27
Appendix A. EVB-LAN9252-4PORT Evaluation Board
A.1 Introduction .................................................................................................. 29
Appendix B. EVB-LAN9252-4PORT Evaluation Board Schematics
B.1 Introduction .................................................................................................. 31
Appendix C. Bill of Materials (BOM)
C.1 Introduction .................................................................................................. 41
Worldwide Sales and Service .................................................................................... 46
2014-2015 Microchip Technology Inc.
DS50002404A-page 5
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
NOTES:
DS50002404A-page 6
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT
ETHERCAT® ESC EXPANSION MODE
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
EVB-LAN9252-4PORT. Items discussed in this chapter include:
•
•
•
•
•
•
Document Layout
Conventions Used in this Guide
The Microchip Web Site
Development Systems Customer Change Notification Service
Customer Support
Document Revision History
DOCUMENT LAYOUT
This document describes how to use the EVB-LAN9252-4PORT as a development tool
for the Microchip LAN9252 EtherCAT® slave controller. The manual layout is as
follows:
• Chapter 1. “Overview” – Shows a brief description of the
EVB-LAN9252-4PORT.
• Chapter 2. “Board Details & Configuration” – Includes details and instructions
for using the EVB-LAN9252-4PORT.
• Appendix A. “EVB-LAN9252-4PORT Evaluation Board” – This appendix
shows the EVB-LAN9252-4PORT.
• Appendix B. “EVB-LAN9252-4PORT Evaluation Board Schematics” – This
appendix shows the EVB-LAN9252-4PORT schematics.
• Appendix C. “Bill of Materials (BOM)” – This appendix includes the
EVB-LAN9252-4PORT Bill of Materials (BOM).
2014-2015 Microchip Technology Inc.
DS50002404A-page 7
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Arial font:
Italic characters
Represents
Examples
Referenced books
Emphasized text
A window
A dialog
A menu selection
A field name in a window or
dialog
A menu path
MPLAB® IDE User’s Guide
...is the only compiler...
the Output window
the Settings dialog
select Enable Programmer
“Save project before build”
A dialog button
A tab
A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
A key on the keyboard
Click OK
Click the Power tab
4‘b0010, 2‘hF1
Italic Courier New
Sample source code
Filenames
File paths
Keywords
Command-line options
Bit values
Constants
A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe
character: { | }
Ellipses...
Choice of mutually exclusive
arguments; an OR selection
Replaces repeated text
#define START
autoexec.bat
c:\mcc18\h
_asm, _endasm, static
-Opa+, -Opa0, 1
0xFF, ‘A’
file.o, where file can be
any valid filename
mcc18 [options] file
[options]
errorlevel {0|1}
Initial caps
Quotes
Underlined, italic text with
right angle bracket
Bold characters
N‘Rnnnn
Text in angle brackets < >
Courier New font:
Plain Courier New
Represents code supplied by
user
DS50002404A-page 8
File>Save
Press ,
var_name [,
var_name...]
void main (void)
{ ...
}
2014-2015 Microchip Technology Inc.
Preface
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.
To register, access the Microchip web site at www.microchip.com, click on Customer
Change Notification and follow the registration instructions.
The Development Systems product group categories are:
• Compilers – The latest information on Microchip C compilers, assemblers, linkers
and other language tools. These include all MPLAB C compilers; all MPLAB
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK
object linker); and all MPLAB librarians (including MPLIB object librarian).
• Emulators – The latest information on Microchip in-circuit emulators.This
includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.
• In-Circuit Debuggers – The latest information on the Microchip in-circuit
debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug
express.
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows
Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and
MPLAB SIM simulator, as well as general editing and debugging features.
• Programmers – The latest information on Microchip programmers. These include
production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included
are nonproduction development programmers such as PICSTART Plus and
PIC-kit 2 and 3.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
2014-2015 Microchip Technology Inc.
DS50002404A-page 9
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the web site at:
http://www.microchip.com/support
DOCUMENT REVISION HISTORY
Revision A (November 2014)
• Initial Release of this Document.
Revision B (August 2015)
•
•
•
•
•
DS50002404A-page 10
Updated Figure 1-1.
Updated Figure 2-2.
Updated Section 2.4.1 “Expansion Mode”.
Updated Table 2-7.
Added Section 2.4.2.5 “Copper and Fiber Mode Selections” and all its subsections.
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT
ETHERCAT® ESC EXPANSION MODE
USER’S GUIDE
Chapter 1. Overview
1.1
INTRODUCTION
The LAN9252 is a 2-port EtherCAT® slave controller with dual integrated Ethernet
PHYs which each contain a full-duplex 100BASE-TX transceiver and support 100Mbps
(100BASE-TX) operation. 100BASE-FX is supported via an external fiber transceiver.
Each port receives an EtherCAT frame, performs frame checking and forwards it to the
next port. Time stamps of received frames are generated when they are received. The
Loop-back function of each port forwards the frames to the next logical port if there is
either no link at a port, if the port is not available, or if the loop is closed for that port.
The Loop-back function of port 0 forwards the frames to the EtherCAT Processing Unit
(EPU). The loop settings can be controlled by the EtherCAT master.
Packets are forwarded in the following order:
Port 0 -> EtherCAT Processing Unit -> Port 1 -> Port 2 -> Port 3.
The EtherCAT Processing Unit receives, analyzes and processes the EtherCAT data
stream. The main purpose of the EtherCAT Processing unit is to enable and coordinate
access to the internal registers and the memory space of the ESC, which can be
addressed both from the EtherCAT master and from the local application. Data
exchange between master and slave applications is comparable to a dual-ported memory (process memory), enhanced by special functions for consistency checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise mapping of logical
EtherCAT system addresses to physical device addresses.
The scope of this document is to describe the EVB-LAN9252-4PORT setup, which supports Expansion Mode and corresponding jumper configurations. The LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for 100BASE-TX
connectivity. A simplified block diagram of the EVB-LAN9252-4PORT is shown in
Figure 1-1.
2014-2015 Microchip Technology Inc.
DS50002404A-page 11
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
FIGURE 1-1:
DS50002404A-page 12
EVB-LAN9252-4PORT BLOCK DIAGRAM
2014-2015 Microchip Technology Inc.
Overview
1.2
REFERENCES
Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation.
• LAN9252 Datasheet
• AN 8.13 Suggested Magnetics
• EVB-LAN9252-4PORT Schematics
2014-2015 Microchip Technology Inc.
DS50002404A-page 13
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
NOTES:
DS50002404A-page 14
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT
ETHERCAT® ESC EXPANSION MODE
USER’S GUIDE
Chapter 2. Board Details & Configuration
This section includes sub-sections on the following EVB-LAN9252-4PORT details:
•
•
•
•
•
2.1
Power
Reset
Clock
Configuration
Mechanicals
POWER
2.1.1
+5V Power
Power is supplied to the EVB-LAN9252-4PORT by a +3.3V on-board regulator, which
is powered by a +5V external wall adapter. The LAN9252 includes an internal +1.2V
regulator which supplies power to the internal core logic. Assertion of the D1 Green
LED indicates successful generation of +3.3V o/p. The SW1 switch must be in the ON
position for the +5V to power the +3.3V regulator.
2.2
RESET
A power-on reset occurs whenever power is initially applied to the LAN9252 or if the
power is removed and reapplied to the LAN9252. This event resets all circuitry within
the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset
switch SW2. The reset LED D2 will assert (red) when the LAN9252 is in reset condition.
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset
release.
2.3
CLOCK
The EVB-LAN9252-4PORT utilizes an external 25Mhz 25ppm crystal from Cardinal
Components Inc. (P/N: CSM1Z-A5B2C5-40-25.0D18-F).
2014-2015 Microchip Technology Inc.
DS50002404A-page 15
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
2.4
CONFIGURATION
The following sub-sections describe the various board features and configuration settings.
2.4.1
Expansion Mode
Two EtherCAT slave controllers can be connected back-to-back using the MII interface,
as shown in Figure 2-1. In this Expansion Mode, two EVB-LAN9252-4PORT boards
(Board 1 and Board 2) are used as shown in Figure 2-2. Board 1 and Board 2 use identical PCBs, but have different bills of material. The timing of RX_DV and RXD with
respect to RX_CLK has to be checked at both ESCs (LAN9252) to be compliant with
the IEEE 802.3 requirements of min.10 ns setup time and min. 10 ns hold time. The
timing can be adjusted by configuring the TX Shift settings of each ESC (LAN9252).
These differences are detailed in the following subsections.
FIGURE 2-1:
DS50002404A-page 16
BACK-TO-BACK CONNECTION VIA MII
2014-2015 Microchip Technology Inc.
Board Details & Configuration
FIGURE 2-2:
EVB-LAN9252-4PORT TOP VIEW WITH CALLOUTS
Port 3
RJ45
Port 0
Port 3
Port 0
LINK/ACT LED
(with Magnetics)
LINK/ACT LED
Run LED
Board 2
PIC32MX795F512L
EEPROM
EtherCAT
Device ID
Board to
Board
Connectors
Add-On
Soc Option
ICSP
for PIC
SoC
Reset
Board 1
SoC
Select
Straps
Reset
Microchip
LAN9252
TX Shift
Strap
2014-2015 Microchip Technology Inc.
Port 1
RJ45
Port 2
Port 1
Port 2
LINK/ACT LED
(with Magnetics)
LINK/ACT LED
DS50002404A-page 17
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
2.4.1.1
BOARD ASSEMBLY
J17 and J18 are used to stack the boards. On Board 1, thru-hole Berg stick headers
(gold plated 2.54mm) are placed on the top side of the PCB. On Board 2, thru-hole Berg
stick sockets (gold plated 2.54mm) are placed on the bottom side of the PCB. To use
these boards in Expansion Mode, Board 2 must be stacked on top of Board 2 via J17
and J18 (see Figure 2-2 and Table 2-1).
TABLE 2-1:
EXPANSION MODE JUMPERS J17 & J18
Jumper
Board 1
J17 & J18
2.4.1.2
Board 2
Thru-hole Berg stick headers on
top side
Thru-hole Berg stick sockets on
bottom side
JUMPER SETTINGS
The default jumpers settings for Board 1 and Board 2 are shown in Table 2-2.
TABLE 2-2:
Jumper
DEFAULT JUMPER SETTINGS
Board 1 (Short)
Board 2 (Short)
Signal
J14
1-2
1-2
CLK (25 MHz)
J4 & J7
2-3
1-2
CHIPMODE0
J5 & J8
1-2
1-2
CHIPMODE1
J6 & J9
2-3
2-3
RUNLED
J15 & J16
2-3
2-3
MII_LINKPOL
J19
1-2
1-2
5V
J20
1-2
1-2
MII_MDIO
J21
1-2
1-2
RESET
J22
1-2
1-2
MII_RXER
J23
1-2
1-2
MII_LINK
2.4.1.3
CLOCK, POWER, RESET CONFIGURATIONS
In Expansion Mode, there are two different sub-modes available:
• Separate Mode (Default): The LAN9252 clock on each board is provided separately (P/N: CSM1Z-A5B2C5-40-25.0D18-F). Power and reset are common for
this setup.
• Combined Mode: The LAN9252 clock on each board is provided via a single
25MHz oscillator (P/N: CB3LV-3C-25M0000). To enable Combined Mode, the J14
jumpers must be configured as shown in Table 2-3.
TABLE 2-3:
DS50002404A-page 18
J14 COMBINED MODE JUMPER SETTINGS
Jumper
Board 1 (Short)
Board 2 (Short)
J14
3-4 & 5-6
5-6
2014-2015 Microchip Technology Inc.
Board Details & Configuration
2.4.2
Strap Options
The following LAN9252 strap options are available.
2.4.2.1
CHIP MODE SELECTION
Table 2-4 details the LAN9252 chip mode configuration straps.
TABLE 2-4:
CHIP MODE CONFIGURATION STRAP
Jumper
Board 1 (Short)
Board 2 (Short)
J4 & J7
2-3
1-2
3-port downstream mode
J5 & J8
1-2
1-2
3-port upstream mode
Note:
2.4.2.2
Mode
For proper operation, Board 1 must be in 3-port downstream mode and
Board 2 must be in 3-port upstream mode. This requires J4, J5, J7, and J8
to be configured as shown in Table 2-4. All other configurations are not supported.
EEPROM SIZE CONFIGURATION
The EEPROM size configuration strap (J6 & J9) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512.
Table 2-5 details the LAN9252 chip mode configuration straps.
TABLE 2-5:
EEPROM SIZE CONFIGURATION STRAP
Header
Description
Pins
J6, J9
EEPROM size configuration
strap inputs. This strap determines the supported
EEPROM size range.
1-2
2-3
2.4.2.3
Settings
Short 1-2 for high (pull-up) (default)
Short 2-3 for low (pull-down)
MII_LINKPOL
This strap determines the polarity of the MII_LINK pin. On the EVB-LAN9252-4PORT
it is tied low. In this mode MII_LINK low equates to “100/Mbit/s Full-Duplex Link is
Established”.
2014-2015 Microchip Technology Inc.
DS50002404A-page 19
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
2.4.2.4
TX SHIFT STRAPS
The EtherCAT MII Port TX Timing Shift straps determine the value of the MII TX timing
shift. The SW9 and SW10 switches are used to determine the TX Shift straps as
detailed in Table 2-6 and Table 2-7.
TABLE 2-6:
TX_SHIFT DEFINITIONS
TX_SHIFT1
TX_SHIFT0
0
0
20
0
1
30 (Default)
1
0
0
1
1
10
TABLE 2-7:
TX Timing Shift (ns)
SW9 & SW10 SETTINGS
Switch
Short Pins
Switch Knob Position
SW9 (TX_SHIFT0=1)
1-2
Down
SW10 (TX_SHIFT=0)
1-3
Up
Note:
2.4.2.5
For switch P/N: 450301014042, pin 1 is at the middle of the switch. To short
1-2, knob position must be in the 1-3 position, and vice versa.
COPPER AND FIBER MODE SELECTIONS
The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).
This EVB supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) in SFP mode. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.
Note:
Vendor part number for SFP Transceiver: Finisar/FTLF1217P2.
2.4.2.5.1
Copper Mode
The EVB-LAN9252 is set to Copper Mode by default. Table 2-8 details the required
strap resistors settings for Copper Mode operation.
TABLE 2-8:
Resistors
Signal Names
R79 (10K)
FXLOSEN
Copper twisted pair for ports A and B further
determined by FXSDENA and FXSDENB
R76, R80 (10K)
FXSDA/FXSDB
Configures Port 0 and Port 1 to Copper Mode
Note:
DS50002404A-page 20
COPPER MODE STRAP RESISTORS
Description
R75, R77, and R78 must not be populated (DNP).
2014-2015 Microchip Technology Inc.
Board Details & Configuration
Additionally, the signal routing resistors detailed in Table 2-9 must be assembled for
Copper Mode operation.
TABLE 2-9:
COPPER MODE SIGNAL ROUTING RESISTORS
Resistors
Note:
Description
R17, R19,R21, R23
Port 0 Copper mode is Enabled
R31, R33, R35, R37
Port 1 Copper mode is Enabled
R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
2.4.2.5.2
Fiber Mode
The LAN9252 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the
respective strap and signal routing resisters must be configured.
Note:
Copper Mode related resistors must be DNP while Fiber Mode is active
(see Section 2.4.2.5.1 “Copper Mode”).
Table 2-10 details the required strap resistor settings for Fiber Mode operation
TABLE 2-10:
FIBER MODE STRAP RESISTORS
Resistors
R77 (10K)
R75, R78 (10K)
Note:
Description
Configures Port 0 & 1 to FX_LOS Mode
Configures Port 0 & 1 to Fiber mode, respectively
R76, R79, and R80 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-11 must be assembled for
Fiber Mode operation
TABLE 2-11:
FIBER MODE SIGNAL ROUTING RESISTORS
Resistors
Note:
Description
R17, R19,R21, R23
Port 0 Copper mode is Enabled
R31, R33, R35, R37
Port 1 Copper mode is Enabled
R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
2014-2015 Microchip Technology Inc.
DS50002404A-page 21
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
2.4.2.5.3
FX-LOS Fiber Mode Strap
FX-LOS strap details are shown in Table 2-12. These strap settings determine if the
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.
TABLE 2-12:
FX-LOS MODE STRAP SETTINGS
R77 (10K)
R79 (10K)
Reference Voltage
Populate
DNP
3.3
A level above 2V selects FX-LOS for
Port 0 and Port 1
Populate
Populate
1.5
A level of 1.5V selects FX-LOS for Port
0 and FX-SD / Copper twisted pair for
Port 1, further determined by FXSDB
DNP
Populate
0 (Default)
Note:
2.4.3
Function
A level of 0V selects FX-SD / Copper
twisted pair for Ports 0 and 1, further
determined by FXSDA, FXSDB
The above strap details describe the LAN9252 function. This EVB does not
support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable.
LED Indicators
The D3, D4, and D9 LEDs are used to indicate the Link/Activity status on the corresponding EVB ports, as detailed in Table 2-13. The Link/Act LED should be ON at each
port. If the Link/Act LED is not ON, it indicates there is an issue with the connection or
cable.
TABLE 2-13:
D3 AND D4 LINK/ACTIVITY LED STATUS INDICATORS
State
Description
Off
Link is down
Flashing Green
Link is up with activity
Steady Green
Link is up with no activity
Additionally, the D5 LED is used as a RUN indicator (green) to shows the status of the
EtherCAT State Machine (ESM), as detailed in Table 2-14.
TABLE 2-14:
D5 RUN LED STATUS INDICATOR
State
Description
Off
The device is in the INITIALIZATION state
Blinking (on 200ms, off 200ms)
The device is in the PRE-OPERATIONAL state
Single Flash (on 200ms, off 1000ms)
The device is in the SAFE-OPERATIONAL state
On
The device is in the OPERATIONAL state
Flickering (on 50ms, off 50ms)
The device is booting and has not yet entered
the INITIALIZATION state, or the device is in the
BOOTSTRAP state and firmware download is in
progress. (Optional. Off when not implemented.)
Table 2-15 details which LEDs are populated on Board 1 and Board 2 (Expansion
Mode).
TABLE 2-15:
DS50002404A-page 22
BOARD 1 & BOARD 2 LED POPULATION LIST
LED
Board 1
Board 2
Signal
Color
D1
Populated
Populated
3V3
Green
D2
Populated
Populated
RESET
Red
2014-2015 Microchip Technology Inc.
Board Details & Configuration
TABLE 2-15:
BOARD 1 & BOARD 2 LED POPULATION LIST (CONTINUED)
LED
Board 1
Board 2
Signal
Color
D3
Populated
Not Populated
LINK/ACT (Port 0)
Green
D4
Populated
Populated
LINK/ACT
(Port 1 on Board 1, Port 4 on Board 2)
Green
D5
Populated
Populated
RUNLED
Green
D7
Not Populated Not Populated
MII LINK
Green
D9
Not Populated
Populated
LINK/ACT (Port 3)
Green
D10
Populated
Populated
ERROR LED
Green
2.4.4
EEPROM Switch
The EVB-LAN9252-4PORT utilizes 0x50 (7-bit) I2C slave addressing. The SW3 switch
can be used to select the A0, A1, and A2 address bits, as shown in Figure 2-3 and
Table 2-16. The eighth bit of the slave address determines if the master device wants
to read or write to the 24FC512.
FIGURE 2-3:
SLAVE ADDRESS ALLOCATION
Start
1
Read/Write
0
1
0
A2
A1
A0 R/W
A
Slave Address
TABLE 2-16:
EEPROM SWITCH
Switch
Description
SW3
2.4.5
Settings
I2C
EEPROM address selection switch ON for logic 0 (default)
(A0, A1, A2). See Figure 2-3.
OFF for logic 1
SoC
The EVB-LAN9252-4PORT supports both an on-board SoC and add-on SoC. By
default, the on-board SoC is enabled. However, an external add-on SoC can be connected via the add-on SoC headers. The SoC selection is configured via the SW5
switch, as detailed in the following subsections.
2014-2015 Microchip Technology Inc.
DS50002404A-page 23
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
FIGURE 2-4:
EVB-LAN9252-4PORT SOC SECTION
Add-On
Soc Option
ICSP
for PIC
SoC
Reset
SoC
Select
2.4.5.1
ON-BOARD SOC/PIC
By default, the on-board Microchip PIC32MX795F512L (U7) is used as the default
SoC, which supports SPI.
2.4.5.1.1
Reset
SW6 is used to reset the on-board PIC. Additionally, when the LAN9252 is reset, it also
forces the PIC into a reset state. For stability, a delay of approximately 180ms is added
from the 3.3V o/p to reset release.
2.4.5.1.2
PIC Selection
The SW5 switch selects the enabled SoC. The SW5 switch knob position must be down
to select the on-board PIC. If the switch knob position is up, then the on-board PIC is
always in the reset state. Whenever an add-on board/SoC is used, the switch knob
must be in the up position.
TABLE 2-17:
SOC SELECTION
Switch
Position
Settings
SW5
Down
On-board PIC enabled
SW5
Up
Add-on board/SoC enabled
2.4.5.1.3
ICSP Header
SoC programing is performed using the ICSP header J13. Table 2-18 details the ICSP
header pinout
TABLE 2-18:
DS50002404A-page 24
J13 ICSP HEADER PINOUT
J13 Pin
Settings
1
MLCR
2
3V3
3
GND
4
PGD2
5
PGC2
2014-2015 Microchip Technology Inc.
Board Details & Configuration
TABLE 2-18:
J13 ICSP HEADER PINOUT (CONTINUED)
J13 Pin
Settings
6
NC
2.4.5.1.4
SoC EEPROM
The EVB-LAN9252-4PORT provides an optional SoC EEPROM. TI based SoCs
require an EEPROM. However, the PIC on-board SoC and PIC based add-on SoC
boards do not require this EEPROM.
2.4.5.2
ADD-ON SOC
An add-on board can be attached to the EVB-LAN9252-4PORT to use an add-on SoC.
The add-on board must be mounted to the P8 and P9 connectors (2x23, 100mil normal
gold plated Berg stick). The SW5 switch must be in the up position when using an
add-on SoC. Additionally, the J10 2-pin jumper must be shorted to route power to the
add-on board.
2.4.5.3
ID SELECT
The signals shown in Table 2-19 are used for ID selection. Switches SW7, SW8 and
respective pull-up resistors are used to configure the ID select signals high or low. By
default, the EtherCAT Device ID value is set to 5. To achieve this, ID0 and ID2 must be
high while the remaining ID select signals (ID1 and ID3 through ID15) must be low.
Signals are high via the pull-up resistors. When required, setting the respective switch
knob to the on position will change the ID select signal to low.
TABLE 2-19:
ID SELECT SIGNALS
ID Selection
Signal
Signal Name
PIC Pin
Number
Switch Pin
Number
Reference
Designator
ID0
ID_SELECT_RB0
25
SW7.1
R123
ID1
ID_SELECT_RB1
24
SW7.2
R124
ID2
ID_SELECT_RB2
23
SW7.3
R126
ID3
ID_SELECT_RB3
22
SW7.4
R125
ID4
ID_SELECT_RB4
21
SW7.5
R127
ID5
ID_SELECT_RB5
20
SW7.6
R128
ID6
ID_SELECT_RB8
32
SW7.7
R129
ID7
ID_SELECT_RB9
33
SW7.8
R130
ID8
ID_SELECT_RB10
34
SW8.1
R131
ID9
ID_SELECT_RB11
35
SW8.2
R133
ID10
ID_SELECT_RB12
41
SW8.3
R134
ID11
ID_SELECT_RB13
42
SW8.4
R132
ID12
ID_SELECT_RC1
6
SW8.5
R135
ID13
ID_SELECT_RC2
7
SW8.6
R136
ID14
ID_SELECT_RC3
8
SW8.7
R137
ID15
ID_SELECT_RC4
9
SW8.8
R138
2014-2015 Microchip Technology Inc.
DS50002404A-page 25
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
2.4.6
SPI/SQI/I2C Aardvark®
J11 and J12 are used as Aardvark/SPI headers. The respective pin details are shown
in Table 2-20. Registers R61, R62, and R122 must be populated to use this option. By
default, R61, R62, and R122 are not populated (DNP).
TABLE 2-20:
DS50002404A-page 26
J11 & J12 HEADER PINOUT
Signal
Pin Number
SCL
J11.1
SDA
J11.3
SCK
J11.7
SCS#
J11.9
SI(SIO0)
J11.8
SO(SIO1)
J11.5
SIO2
J12.3
SIO3
J12.4
2014-2015 Microchip Technology Inc.
Board Details & Configuration
2.5
MECHANICALS
FIGURE 2-5:
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT MECHANICAL DIMENSIONS
DS50002404A-page 27
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
NOTES:
DS50002404A-page 28
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT
ETHERCAT® ESC EXPANSION MODE
Appendix A. EVB-LAN9252-4PORT Evaluation Board
A.1
INTRODUCTION
This appendix shows the EVB-LAN9252-4PORT Evaluation Board.
FIGURE A-1:
EVB-LAN9252-4PORT EVALUATION BOARD
2014-2015 Microchip Technology Inc.
DS50002404A-page 29
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
NOTES:
DS50002404A-page 30
2014-2015 Microchip Technology Inc.
EVB-LAN9252-4PORT
ETHERCAT® ESC EXPANSION MODE
Appendix B. EVB-LAN9252-4PORT Evaluation Board
Schematics
B.1
INTRODUCTION
This appendix shows the EVB-LAN9252-4PORT Evaluation Board Schematics.
2014-2015 Microchip Technology Inc.
DS50002404A-page 31
EVB-LAN9252-4PORT SCHEMATIC POWER SUPPLY & RESET
POWER SUPPLY
U1
EN12_1
R1
2A/0.05DCR
2
Switch, SPDT, Slide
P/N:1101M2S3CQE2
J1
2
1
0E
C2
10uF
25V
C3
VIN
ENABLE
VOUT
TRIM
3_Amp
GND
4
5
3
0.1uF OKR-T/3-W12-C
R3
3.30K
1%
R4
470E
1%
3V3
0.1uF
4.7uF
RESET
3
R8
1K
2
NDS355AN_NMOS
1
D
RST#
Q1
1
G
5
RESET#
3
MR#
D1
GRN
Note:
1.POR -> Reset to ASIC & SOC (Default)
2.RESET O/P from ASIC -> Reset to EX-PHY (PORT2) & SOC :Only Ethercat sku
3.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC
4.RESET from Push Botton -> Reset to ASIC & SOC
3V3
VDD
4
C5
10uF
5
U2
2
1/10W
1%
2
1
R7
100
R5
4.75K
1%
0.1uF
GND
1
C6
2
SW2
sw_pb_2P
C4
RESET Options
3V3
R6
10.0K
1/10W
1%
R4A
33E
1%
(Rb)
(Ra)
3V3
Reset Generator
R2
1K
DNP
C1
1
5V_SW
A
FB1
2
3
C
1
3V3
3V3
"3V3 Present"
5V_EXT
3
TP2
ORANGE
S
SOT23_5
Threshold = 2.64V
Delay = 180ms
Br_Red-RA
U3
2
4
TPS3125
R9
74LVC1G14
2014-2015 Microchip Technology Inc.
TP8
BLACK
2.2K
1
D2
1
3
1
3 V REGULATOR, 3A
( 3V3 fixed when Rb=470E)
2
TP1
RED
5V
SW1
TP9
BLACK
A
C
"Reset"
2
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
DS50002404A-page 32
FIGURE B-1:
EVB-LAN9252-4PORT SCHEMATIC LAN9252
Power Supply Filtering
FB3
C26
18pF
(*short 1&2)
J14
25.000MHz
25ppm
Y1
DNP
R167
OSCI
OSCO
3V3
100K
3
1
2
4
C27
18pF
REG_EN
R10
12.1K
1%
RBIAS
7
57
RST#
11
IRQ
44
ATEST/FXLOSEN
8
41
I2C2_SCL
I2C2_SDA
43
42
GPIO0
GPIO1
GPIO2
48
46
45
6
24
38
VDDCR1
VDDCR2
VDDCR3
14
20
32
37
47
58
5
51
64
OSCVDD12
OSCI
OSCO
OSCVSS
FXSDENA/FXSDA/FXLOSA
INT PORT0
OSCI_Combined
REG_EN
RBIAS
RST#
TXNA
TXPA
RXNA
RXPA
C22
C18
C21
C17
0.1uF
0.1uF
C16
0.1uF
C20
C15
0.1uF
0.1uF
C14
0.1uF
C19
C13
0.1uF
1uF
C12 DNP
0.1uF
470pF
C11
9
FXSDA/FXLOSA
52
53
54
55
TXNA
TXPA
RXNA
RXPA
63
62
61
60
TXNB
TXPB
RXNB
RXPB
10
FXSDB/FXLOSB
IRQ
ATEST/FXLOSEN
TESTMODE
I2CSCL/EESCL/TCK
I2CSDA/EESDA/TMS
INT PORT1
(Only for
Lan9252)
2
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
3
I2C
GND
VDD33BIAS
VDD33
OUT
VCC
OSC
OE
5
3
1
OTHER
SIGNALS
4
6
4
2
POWER
1
HEADER 3X2
DNP
Y4
VDD33TXRX1
VDD33TXRX2
U4A
25MHz
OSCILLATOR
1.0uF
VDD12TX1
VDD12TX2
0.1uF
FB5
2A/0.05DCR
BLM18EG221SN1D
Note:
OSCVSS need to connect to Chip gnd.
100K
0.1uF
C25
0.1uF
3V3
DNP
R166
DNP
C85
C24
2
3V3
VDDCR
VDD33TXRX1
VDD33TXRX2
BLM18EG221SN1D
C23
1.0uF
DNP
3V3
2A/0.05DCR
C10
3V3
FB4
0.1uF
3V3
2A/0.05DCR
C9
0.1uF
VDD33TXRX2
0.1uF
C8
VDDCR
56
59
C7
1.0uF
DNP
DNP
2A/0.05DCR
VDD12TX1
VDD12TX2
FB2
3V3
VDD12TX1
VDD12TX2
Low ESR
VDD33TXRX1
1.0uF
3V3
1
2014-2015 Microchip Technology Inc.
FIGURE B-2:
TXNB
TXPB
RXNB
RXPB
FXSDENB/FXSDB/FXLOSB
LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0
LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1
RUNLED/LEDPOL2/E2PSIZE
LAN9252
65
GND
GPIO
Schematics
DS50002404A-page 33
EVB-LAN9252-4PORT SCHEMATIC COPPER MODE INTERFACE
VDD33TXRX1
PORT0
FX_SFP-RXPA
RXNA
3
FX_SFP-RXNA
9
4&5
TD-
2
RCV
5
0E
0E
A
C
COP-RXPA
1
75
6
COP-RXNA
DNP
C29
10pF
50V
5%
DNP
C30
10pF
50V
5%
DNP
C31
10pF
50V
5%
C32
0.022uF
7
8
50V
10%
75
3
75
7&8
RXCT
6
RD-
1000 pF
NC
CHS GND
14
13
GND
DNP
C28
10pF
50V
5%
RD+
Note:
Capacitors C28 through C31 are optional for EMI purposes
and are not populated on the LAN9252 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
2 kV
YEL
A1
0E
0E
DNP
R22
R23
2
75
TXCT
R24
12
DNP
R20
R21
COP-TXNA
TD+
C1
RXPA
4
RJ45
XMIT
11
FX_SFP-TXNA
1
MTG1
0E
0E
GRN
0E
COP-TXPA
MTG
DNP
R18
R19
TXNA
R15
16
FX_SFP-TXPA
R14
49.9
1/10W
1%
15
0E
0E
R13
49.9
1/10W
1%
GND1
DNP
R16
R17
TXPA
R12
49.9
1/10W
1%
10
T1
Pulse J0011D01BNL
R11
49.9
1/10W
1%
0E
RES1210
VDD33TXRX2
PORT1
3
2
DNP
C33
10pF
50V
5%
DNP
C34
10pF
50V
5%
DNP
C35
10pF
50V
5%
DNP
C36
10pF
50V
5%
C37
0.022uF
50V
10%
7
8
75
Note:
Capacitors C33 through C36 are optional for EMI purposes
and are not populated on the LAN9252 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
75
3
7&8
RXCT
6
RD-
1000 pF
NC
CHS GND
R38
2 kV
YEL
0E
RES1210
A1
6
COP-RXNB
RD+
GND
FX_SFP-RXNB
TD-
RCV
5
0E
0E
1
4&5
12
RXNB
COP-RXPB
75
C1
FX_SFP-RXPB
2
75
TXCT
11
0E
0E
DNP
R36
R37
COP-TXNB
TD+
MTG1
RXPB
DNP
R34
R35
4
RJ45
XMIT
MTG
FX_SFP-TXNB
GRN
1
COP-TXPB
16
0E
0E
0E
15
TXNB
DNP
R32
R33
FX_SFP-TXPB
R29
GND1
0E
0E
R28
49.9
1/10W
1%
14
DNP
R30
R31
R27
49.9
1/10W
1%
13
2014-2015 Microchip Technology Inc.
TXPB
R26
49.9
1/10W
1%
A
C
9
10
T2
Pulse J0011D01BNL
R25
49.9
1/10W
1%
EVB-LAN9252-4PORT EtherCAT® ESC Expansion Mode User’s Guide
DS50002404A-page 34
FIGURE B-3:
EVB-LAN9252-4PORT SCHEMATIC SFP INTERFACE
3V3
R39
82
R40
82
R41
49.9
R42
49.9
Note:Place
capacitors,
and resistors
close to FOT
C38
0.1uF
C40
0.1uF
Note:Place
capacitors,
and resistors
close to FOT
3V3
Fiber Port 0 :SFP Interface
R43
82
FX_SFP-RXNA
R44
82
R45
49.9
Fiber Port 1 :SFP Interface
R46
49.9
C39
0.1uF
C41
0.1uF
C43
0.1uF
C45
0.1uF
FX_SFP-RXNB
FX_SFP-RXPA
FX_SFP-RXPB
C42
0.1uF
FX_SFP-TXPA
FX_SFP-TXPB
3V3
R47
100
3V3
R48
SFP_VCCT
SFP_VCCT2
100
C44
0.1uF
L2
SFP_VCCR
FX_SFP-TXNA
1uH
C47
0.1uF
C48
10uF
16V
+
C49
0.1uF
R51
130
R52
130
C50
10uF
16V
DNP
SFP_RD2+
SFP_RD2-
+
SFP_TD2SFP_TD2+
R50
130
SFP_RD+
SFP_RD-
R49
130
C46
10uF
16V
DNP
L1
+
C51
R53
4.7K
R54
4.7K
20
19
18
17
16
15
14
13
12
11
C55
0.1uF
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
+
Note:Place
resistors
close to
ASIC
J3
FTLF1217P2
R55
4.7K
FXSDA/FXLOSA
R56
4.7K
1uH
31
30
29
28
27
26
25
24
23
22
21
31
30
29
28
27
26
25
24
23
22
21
C56
10uF
16V
+
C57
0.1uF
SFP_VCCT2
1
2
3
4
5
6
7
8
9
10
SFP_VCCT
C54
10uF
16V
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
FTLF1217P2
31
30
29
28
27
26
25
24
23
22
21
C53
0.1uF
1
2
3
4
5
6
7
8
9
10
J2
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
ASIC
31
30
29
28
27
26
25
24
23
22
21
+
1uH
20
19
18
17
16
15
14
13
12
11
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
Note:Place
resistors
close to
C52
10uF
16V
0.1uF
L3
L4
1uH
SFP_VCCR2
FX_SFP-TXNB
SFP_TDSFP_TD+
2014-2015 Microchip Technology Inc.
FIGURE B-4:
R57
4.7K
R58
4.7K
R59
4.7K
R60
4.7K
FXSDB/FXLOSB
Schematics
DS50002404A-page 35
GPIO [0:2] & LED_POL_Strap
I2C EEPROM
R140
332
1/10W
1%
SW DIP-4/SM
24FC04
2K
2K
I2C2_SDA
I2C2_SCL
TH IC.
Different sizes can be mounted
I2C EEPROM Lower size
Below 16K(2K X 8)
GPIO1
3
1
3
J16
1
3
1
J8
GPIO2
SCL
WP
5
6
2
2
2
2
3
J9
1
J7
GPIO0
SDA
4
R74
1K
A0
A1
A2
R68
R67
7
1
R73
1K
2
R72
1K
1
2
3
8
R65
R66
I2C2_1
I2C2_2
I2C2_3
I2C2_7
VCC
1
2
3
4
0.1uF
GND
2
2
2
8
7
6
5
4.7K
SW3
LED1_CATHODE
LEDPOL6_CATHODE
2
LED0_CATHODE
LED2_CATHODE
R63
U5
R139
10.0K
4.7K
R71
10.0K
R64
1
3
GPIO2
2
2
R70
10.0K
3V3
C58
GPIO1
LED1_ANODE
LEDPOL6_ANODE
1
1
1
R69
10.0K
3V3
GPIO0
J15
2
J5
LED0_ANODE
LED2_ANODE
3V3
MII_LINKPOL
3
1
3
1
3
1
GPIO1
J6
2
J4
3V3
GPIO2
4.7K
3V3
GPIO0
4.7K
3V3
1
3V3
MII_LINKPOL
I2C EEPROM Higher size
Above 16K(2K X 8)
LINK/ACT LED2
LINK/ACT
LED0_ANODE
LED0_CATHODE
D3 1
GRN A
LEDPOL6_ANODE
2
C
LEDPOL6_CATHODE
LINK/ACT
LED1_ANODE
LED1_CATHODE
D4 1
GRN A
2
LEDPOL6_ANODE
C
LED0_CATHODE
D7 1
LED A
C
2
DNP
D9 1
LED A
C
2
FX_Los_Strap_1 & 2
FX_Mode_Strap_1 & 2
3V3
RUNLED
LED2_ANODE
LED2_CATHODE
D5 1
GRN A
2
C
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