EVB-LAN9252-HBI+
EtherCAT® Evaluation Board
User’s Guide
2015-2016 Microchip Technology Inc.
DS50002333C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer,
LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST
Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch,
Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781522406839
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS50002333C-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2015-2016 Microchip Technology Inc.
Object of Declaration: EVB-LAN9252-HBI+
2015-2016 Microchip Technology Inc.
DS50002333C-page 3
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
NOTES:
DS50002333C-page 4
2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 7
Introduction............................................................................................................ 7
Document Layout .................................................................................................. 7
Conventions Used in this Guide ............................................................................ 8
The Microchip Web Site ........................................................................................ 9
Development Systems Customer Change Notification Service ............................ 9
Customer Support ................................................................................................. 9
Document Revision History ................................................................................. 10
Chapter 1. Overview
1.1 Introduction ................................................................................................... 11
1.2 References ................................................................................................... 13
1.3 Terms and Abbreviations ............................................................................. 13
Chapter 2. Board Details & Configuration
2.1 Power ........................................................................................................... 14
2.1.1 +5V Power ................................................................................................. 14
2.2 Resets .......................................................................................................... 14
2.2.1 Power-on Reset ......................................................................................... 14
2.2.2 Reset Out .................................................................................................. 14
2.2.3 GPIO Reset ............................................................................................... 14
2.3 Clock ............................................................................................................ 15
2.4 Configuration ................................................................................................ 15
2.4.1 Strap Options ............................................................................................ 16
2.4.2 LED Indicators ........................................................................................... 18
2.4.3 EEPROM Switch ....................................................................................... 19
2.4.4 DIGIO/HBI/SPI+GPIO Selection ................................................................ 19
2.4.5 SoC ........................................................................................................... 23
2.5 DIGIO & SPI+16GPIO Signals on P1 and P2 Headers ................................ 25
2.5.1 DIGIO on P1 and P2 Headers (up to 16 bits supported) ........................... 25
2.5.2 SPI+GPIO on P1 and P2 Headers (up to 16 bits supported) .................... 26
2.6 Additional Features ...................................................................................... 27
2.6.1 Potentiometer ............................................................................................ 27
2.6.2 Temperature Sensor ................................................................................. 27
2.6.3 UART RS-232 ........................................................................................... 27
2.6.4 DAC ........................................................................................................... 27
2.7 Limitations .................................................................................................... 27
2.8 Mechanicals ................................................................................................. 28
Chapter 3. Software Development Kit
3.1 Prerequisites ................................................................................................ 29
2015-2016 Microchip Technology Inc.
DS50002333C-page 5
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
3.1.1 Hardware Requirements ............................................................................29
3.1.2 Software Requirements .............................................................................29
3.2 ESC SDK Sample Overview ........................................................................ 29
3.2.1 User Module ...............................................................................................30
3.2.2 EtherCAT® Slave Stack .............................................................................30
3.2.3 Hardware Abstraction Layer (HAL) ............................................................30
3.3 Using the Sample Project ............................................................................. 31
3.3.1 MPLAB IDE Project Settings & Firmware Download .................................31
3.3.2 Compiling and Programming SoC Firmware .............................................33
3.4 Programming the LAN9252 EEPROM ......................................................... 34
3.4.1 Programming LAN9252 EEPROM using the TwinCAT Master Tool .........34
Appendix A. Evaluation Board Photo
A.1 Introduction .................................................................................................. 37
Appendix B. Evaluation Board Schematics
B.1 Introduction .................................................................................................. 38
Appendix C. Bill of Materials (BOM)
C.1 Introduction .................................................................................................. 49
Worldwide Sales and Service .....................................................................................54
DS50002333C-page 6
2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before using the
EVB-LAN9252-HBI+. Items discussed in this chapter include:
•
•
•
•
•
•
Document Layout
Conventions Used in this Guide
The Microchip Web Site
Development Systems Customer Change Notification Service
Customer Support
Document Revision History
DOCUMENT LAYOUT
This document describes how to use the EVB-LAN9252-HBI+ as a development tool
for the Microchip LAN9252 EtherCAT® slave controller. The manual layout is as
follows:
• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9252-HBI+.
• Chapter 2. “Board Details & Configuration” – Includes details and instructions
for using the EVB-LAN9252-HBI+.
• Chapter 3. “Software Development Kit” – Includes details and instructions for
using the LAN9252 EtherCAT® slave stack firmware and SDK framework.
• Appendix A. “Evaluation Board Photo” – This appendix shows the
EVB-LAN9252-HBI+.
• Appendix B. “Evaluation Board Schematics” – This appendix shows the
EVB-LAN9252-HBI+ schematics.
• Appendix C. “Bill of Materials (BOM)” – This appendix includes the
EVB-LAN9252-HBI+ Bill of Materials (BOM).
2015-2016 Microchip Technology Inc.
DS50002333C-page 7
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Arial font:
Italic characters
Represents
Examples
Referenced books
Emphasized text
A window
A dialog
A menu selection
A field name in a window or
dialog
A menu path
MPLAB® IDE User’s Guide
...is the only compiler...
the Output window
the Settings dialog
select Enable Programmer
“Save project before build”
A dialog button
A tab
A number in verilog format,
where N is the total number of
digits, R is the radix and n is a
digit.
A key on the keyboard
Click OK
Click the Power tab
4‘b0010, 2‘hF1
Italic Courier New
Sample source code
Filenames
File paths
Keywords
Command-line options
Bit values
Constants
A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe
character: { | }
Ellipses...
Choice of mutually exclusive
arguments; an OR selection
Replaces repeated text
#define START
autoexec.bat
c:\mcc18\h
_asm, _endasm, static
-Opa+, -Opa0, 1
0xFF, ‘A’
file.o, where file can be
any valid filename
mcc18 [options] file
[options]
errorlevel {0|1}
Initial caps
Quotes
Underlined, italic text with
right angle bracket
Bold characters
N‘Rnnnn
Text in angle brackets < >
Courier New font:
Plain Courier New
Represents code supplied by
user
DS50002333C-page 8
File>Save
Press ,
var_name [,
var_name...]
void main (void)
{ ...
}
2015-2016 Microchip Technology Inc.
Preface
THE MICROCHIP WEB SITE
Microchip provides online support via our web site at www.microchip.com. This web
site is used as a means to make files and information easily available to customers.
Accessible by using your favorite Internet browser, the web site contains the following
information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.
To register, access the Microchip web site at www.microchip.com, click on Customer
Change Notification and follow the registration instructions.
The Development Systems product group categories are:
• Compilers – The latest information on Microchip C compilers, assemblers, linkers
and other language tools. These include all MPLAB C compilers; all MPLAB
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK
object linker); and all MPLAB librarians (including MPLIB object librarian).
• Emulators – The latest information on Microchip in-circuit emulators.This
includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.
• In-Circuit Debuggers – The latest information on the Microchip in-circuit
debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug
express.
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows
Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and
MPLAB SIM simulator, as well as general editing and debugging features.
• Programmers – The latest information on Microchip programmers. These include
production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included
are nonproduction development programmers such as PICSTART Plus and
PIC-kit 2 and 3.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
2015-2016 Microchip Technology Inc.
DS50002333C-page 9
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
Customers should contact their distributor, representative or field application engineer
(FAE) for support. Local sales offices are also available to help customers. A listing of
sales offices and locations is included in the back of this document.
Technical support is available through the web site at:
http://www.microchip.com/support
DOCUMENT REVISION HISTORY
Revision
DS50002333C (06-17-16)
Section/Figure/Entry
Correction
All
Updated board name to “EVB-LAN9252-HBI+”
throughout document.
Figure 1-1
Updated figure to include UART, Temp. Sensor,
DAC, and ADC.
Chapter 2. “Board
Details & Configuration”
Updated Figures 1, 5, 6, 7, and 10. Added new Figure 2.
Updated Tables 13, 14, 15, 21.
2.1.1 “+5V Power”
Removed power supply manufacturer and part number.
2.6 “Additional Features” Added new section with new features.
Chapter 3. “Software
Development Kit”
Updated figures throughout chapter.
Appendix A. “Evaluation Updated appendix with new photos.
Board Photo”
Appendix B. “Evaluation Updated appendix with new schematics.
Board Schematics”
DS50002333B (05-12-15)
Appendix C. “Bill of
Materials (BOM)”
Updated appendix with updated BOM.
All
Updated board name to “EVB-LAN9252-HBI”
throughout document, corrected misc. typos and
grammatical errors.
Section 1.2 “References” Updated list of application notes.
Section 2.4.4 “DIGIO/HBI/ Added additional information on DIGIO mode.
SPI+GPIO Selection”
Table 2-13, Table 2-14,
and Table 2-15
DS50002333A (02-27-15)
DS50002333C-page 10
Simplified table and added note under each table for
clarity.
Initial Release of Document
2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Chapter 1. Overview
1.1
INTRODUCTION
The LAN9252 is a 2-port EtherCAT® Slave Controller (ESC) with dual integrated Ethernet PHYs which each contain a full-duplex 100BASE-TX transceiver and support
100Mbps (100BASE-TX) operation. 100BASE-FX is supported via an external fiber
transceiver.
Each port receives an EtherCAT® frame, performs frame checking and forwards it to
the next port. Time stamps of received frames are generated when they are received.
The Loop-back function of each port forwards the frames to the next logical port if there
is either no link at a port, if the port is not available, or if the loop is closed for that port.
The Loop-back function of port 0 forwards the frames to the EtherCAT® Processing
Unit. The loop settings can be controlled by the EtherCAT® master.
Packets are forwarded in the following order:
Port 0 -> EtherCAT® Processing Unit -> Port 1 -> Port 2.
The EtherCAT® Processing Unit (EPU) receives, analyzes and processes the EtherCAT® data stream. The main purpose of the EtherCAT® Processing unit is to enable
and coordinate access to the internal registers and the memory space of the ESC,
which can be addressed both from the EtherCAT® master and from the local application. Data exchange between master and slave applications is comparable to a
dual-ported memory (process memory), enhanced by special functions for consistency
checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise
mapping of logical EtherCAT® system addresses to physical device addresses.
The scope of this document is to describe the EVB-LAN9252-HBI+ setup, which supports a HBI/SPI+GPIO Interface and corresponding jumper configurations. The
LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for
100BASE-TX connectivity. A simplified block diagram of the EVB-LAN9252-HBI+ is
shown in Figure 1-1.
2015-2016 Microchip Technology Inc.
DS50002333C-page 11
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
FIGURE 1-1:
EVB-LAN9252-HBI+ BLOCK DIAGRAM
EVB-LAN9252-HBI+
UART
Temp
Sensor
DAC
ADC
Power
Supply
Module
Board to Board Connector
Onboard Soc
5V
PIC32MX795F512L
Board to Board Connector
SPI/SQI/I2C
AARDVARK
HBI Mode
Selection
HBI or SPI+GPIO
Selection
EEPROM
Microchip
LAN9252
Straps
Crystal
Port 0
FiberSFP
Port 0
100BASE-TX
Ethernet
Magnetics &
RJ45
Ethernet
DS50002333C-page 12
Port 1
100BASE-TX
Ethernet
Magnetics &
RJ45
FiberSFP
Port 1
Ethernet
2015-2016 Microchip Technology Inc.
Overview
1.2
REFERENCES
Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation.
•
•
•
•
LAN9252 Data Sheet
AN 8.13 Suggested Magnetics
EVB-LAN9252-HBI+ Schematics
The following application notes:
- AN1916 Integrating Microchip’s LAN9252 SDK with Beckhoff’s EtherCAT®
SSC
- AN1920 Microchip LAN9252 EEPROM Configuration and Programming
- AN1907 Microchip LAN9252 Migration from Beckhoff ET1100
1.3
TERMS AND ABBREVIATIONS
IDE - Integrated Development Environment
ESC - EtherCAT® Slave Controller
EVB - Engineering Validation Board
HAL - Hardware Abstraction Layer
HBI - Host Bus Interface
SPI - Serial Protocol Interface
SSC - Slave Stack Code
2015-2016 Microchip Technology Inc.
DS50002333C-page 13
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Chapter 2. Board Details & Configuration
This chapter includes sub-sections on the following EVB-LAN9252-HBI+ details:
•
•
•
•
•
•
•
2.1
Power
Resets
Clock
Configuration
Additional Features
Limitations
Mechanicals
POWER
2.1.1
+5V Power
Power is supplied to the LAN9252 by a +3.3V on-board regulator, which is powered by
a +5V external wall adapter. The LAN9252 includes an internal +1.2V regulator which
supplies power to the internal core logic. Assertion of the D1 Green LED indicates successful generation of +3.3V o/p. The SW1 switch must be in the ON position for the +5V
to power the +3.3V regulator.
2.2
RESETS
2.2.1
Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9252 or if the
power is removed and reapplied to the LAN9252. This event resets all circuitry within
the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset
switch SW2. The reset LED D2 will assert (red) when the LAN9252 is in reset condition.
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset
release.
2.2.2
Reset Out
The LAN9252 reset pin can be configured as an output to reset the SoC. The RST# pin
becomes an open-drain output and is asserted for the minimum required time of 80ms.
2.2.3
GPIO Reset
The EVB-LAN9252-HBI+ provides the option to reset the LAN9252 through a PIC
GPIO pin [95(RG14)]. The SW10 switch is used for this selection, as shown in
Table 2-1.
TABLE 2-1:
Switch
RESET CONFIGURATION SWITCH
Short Pins
Knob Position
Function
SW10
1-3
1-2
System Reset (SYS_RESETN) (Default)
SW10
1-2
1-3
GPIO Reset (RST_GPIO)
2015-2016 Microchip Technology Inc.
DS50002333C-page 14
Board Details & Configuration
2.3
CLOCK
The EVB-LAN9252-HBI+ utilizes an external 25MHz 25ppm crystal from Cardinal
Components Inc. (P/N: CSM1Z-A5B2C5-40-25.0D18-F).
2.4
CONFIGURATION
The following sub-sections describe the various board features and configuration settings. A top view of the EVB-LAN9252-HBI+ is shown in Figure 2-1. Figure 2-2 details
new features.
FIGURE 2-1:
2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+ TOP VIEW WITH CALLOUTS
DS50002333C-page 15
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
FIGURE 2-2:
EVB-LAN9252-HBI+ TOP VIEW NEW FEATURE CALLOUTS
2.4.1
Strap Options
2.4.1.1
CHIP MODE SELECTION
Table 2-2 details the LAN9252 chip mode configuration straps.
TABLE 2-2:
CHIP MODE CONFIGURATION STRAP
Header
Description
Pins
Settings
J4,J6,J7,J9
Chip mode configuration strap
inputs. This strap determines
the number of active ports and
port types.
1-2
Short 1-2 for high (pull-up)
(Not supported in this EVB)
Short 2-3 for low (pull-down) (default)
Note:
2.4.1.2
2-3
This EVB supports Chip mode 00 which is 2-port mode, where Port 0 = PHY
A and Port 1 = PHY B. This requires J4, J6, J7, and J9 to be pulled-down
(2-3) shorted. All other configurations are not supported with this EVB.
EEPROM SIZE CONFIGURATION
The EEPROM size configuration strap (J5 & J8) determines the supported EEPROM
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512.
TABLE 2-3:
EEPROM SIZE CONFIGURATION STRAP
Header
Description
Pins
J5, J8
EEPROM size configuration
strap inputs. This strap determines the supported
EEPROM size range.
1-2
2-3
2.4.1.3
Settings
Short 1-2 for high (pull-up) (default)
Short 2-3 for low (pull-down)
COPPER AND FIBER STRAPS
The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In
100BASE-FX operation, the presence of the receive signal is indicated by the external
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL
Signal Detect (SFF).
DS50002333C-page 16
2015-2016 Microchip Technology Inc.
Board Details & Configuration
This EVB supports 100BASE-TX (Copper) and SFP 100BASE-FX (Fiber) modes. By
default Copper Mode is active. Fiber Mode is supported as an assembly option. To
select the Copper or Fiber Mode, the respective strap and signal routing resister
assembly options must to be configured.
Note:
Vendor part number for SFP: Finisar/FTLF1217P2
2.4.1.3.1
Copper Mode
The EVB-LAN9252-HBI+ is set to Copper Mode by default. Table 2-4 details the
required strap resistor settings for Copper Mode operation.
TABLE 2-4:
COPPER MODE STRAP RESISTORS
Resistors
Description
R79 (10K)
Configures Port 0 & 1 to Copper Mode
R76, R80 (10K)
Configures Port 0 and Port 1 to Copper Mode, respectively
Note:
R75, R77, and R78 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-5 must be assembled for
Copper Mode operation.
TABLE 2-5:
COPPER MODE SIGNAL ROUTING RESISTORS
Resistors
Description
R17, R19, R21, R23
Port 0 Copper Mode enabled
R31, R33, R35, R37
Port 1 Copper mode enabled
Note:
R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be
populated (DNP).
2.4.1.3.2
Fiber Mode
The EVB-LAN9252-HBI+ support SFP type 100BASE-FX. To enable Fiber Mode, the
respective strap and signal routing resistors must be configured.
Note:
Copper Mode related resistors must be DNP while Fiber Mode is active
(See Section 2.4.1.3.1 “Copper Mode”).
Table 2-6 details the required strap resistor settings for Fiber Mode operation.
TABLE 2-6:
FIBER MODE STRAP RESISTORS
Resistors
Description
R77 (10K)
Configures Port 0 & 1 to FX-LOS Mode
R75, R78 (10K)
Configures Port 0 and Port 1 to Fiber Mode, respectively
Note:
R76, R79, and R80 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 2-7 must be assembled for
Fiber Mode operation.
TABLE 2-7:
FIBER MODE SIGNAL ROUTING RESISTORS
Resistors
Description
R16, R18, R20, R22
Port 0 Fiber Mode enabled
R30, R32, R34, R36
Port 1 Fiber mode enabled
2015-2016 Microchip Technology Inc.
DS50002333C-page 17
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
Note:
R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be
populated (DNP).
2.4.1.3.3
FX-LOS Fiber Mode Strap
FX-LOS strap details are shown in Table 2-8. These strap settings determine if the
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.
TABLE 2-8:
FX-LOS MODE STRAP SETTINGS
R77 (10K)
R79 (10K)
Reference
Voltage (V)
Populate
DNP
3.3
A level above 2V selects FX-LOS for Port 0 and
Port 1
Populate
Populate
1.5
A level greater than 1.5V and below 2V selects
FX-LOS for Port 0 and FX-SD / copper twisted
pair for Port 1, further determined by FXSDB
DNP
Populate
0 (Default)
Note:
2.4.2
Function
A level of 0V selects FX-SD / copper twisted pair
for Ports 0 and 1, further determined by FXSDA
and FXSDB
The above strap details describe the LAN9252 function. This EVB does not
support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable.
LED Indicators
The D3 and D4 LEDs are used to indicate the Link/Activity status on the corresponding
EVB ports, as detailed in Table 2-9. The Link/Act LED should be ON at each port when
the cable is present. If the Link/Act LED is not ON, it indicates there is an issue with the
connection or cable.
TABLE 2-9:
D3 AND D4 LINK/ACTIVITY LED STATUS INDICATORS
State
Description
Off
Link is down
Flashing Green
Link is up with activity
Steady Green
Link is up with no activity
Additionally, the D5 LED is used as a RUN indicator (green) to show the AL status of
the EtherCAT® State Machine (ESM), as detailed in Table 2-10.
TABLE 2-10:
D5 RUN LED STATUS INDICATOR
State
DS50002333C-page 18
Description
Off
The device is in the INITIALIZATION state
Blinking (on 200ms, off 200ms)
The device is in the PRE-OPERATIONAL state
Single Flash (on 200ms, off 1000ms)
The device is in the SAFE-OPERATIONAL state
On
The device is in the OPERATIONAL state
Flickering (on 50ms, off 50ms)
The device is booting and has not yet entered
the INITIALIZATION state, or the device is in the
BOOTSTRAP state and firmware download is in
progress. (Optional. Off when not implemented.)
2015-2016 Microchip Technology Inc.
Board Details & Configuration
2.4.3
EEPROM Switch
The EVB-LAN9252-HBI+ utilizes 0x50 (7-bit) I2C slave addressing. The SW3 switch
can be used to select the A0, A1, and A2 address bits, as shown in Figure 2-3 and
Table 2-11. The eighth bit of the slave address determines if the master device wants
to read or write to the EEPROM (24FC512).
FIGURE 2-3:
SLAVE ADDRESS ALLOCATION
Start
1
Read/Write
0
1
0
A2
A1
A0 R/W
A
Slave Address
TABLE 2-11:
EEPROM SWITCH
Switch
Description
SW3
2.4.4
Settings
I2C EEPROM address selection switch ON for logic 0 (default)
(A0, A1, A2). See Figure 2-3.
OFF for logic 1
DIGIO/HBI/SPI+GPIO Selection
The EVB-LAN9252-HBI+ supports three LAN9252 configurations:
• DIGIO Mode
• HBI Mode
• SPI + 16 GPIO Mode
DIGIO and HBI modes use the same switch configuration. The DIGIO/HBI or
SPI+GPIO configuration is selected using the DPDT SW11 to SW21 switches. By
default, the EVB is set to DIGIO mode and no code is programmed to the on-board
PIC32MX. In DIGIO mode, headers P1 and P2 can be used to probe the input and output control signals. It is not possible to configure the input or see to output on the LED
on the EVB. Refer to Table 2-22 for a mapping of the DIGIO signals on the P1 and P2
headers.
Note:
The PDI configuration which is selected in hardware must match with the
PDI configuration that is chosen in the EtherCAT SDK during the SSC integration process. An appropriate PDI configuration must be set in the ESC
configuration area of the EEPROM.
TABLE 2-12:
Switch
HBI/SPI+GPIO SWITCH CONFIGURATIONS
Description
SW11 to SW21
Up
SW11 to SW21
Down
2015-2016 Microchip Technology Inc.
Settings
DIGIO/HBI Mode (Default)
SPI+GPIO Mode
DS50002333C-page 19
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
FIGURE 2-4:
SW11-SW21 DIGIO/HBI/SPI+GPIO MODE SELECTION
DIGIO/HBI Mode
SPI+GPIO Mode
2.4.4.1
HBI MODE SELECTION
The LAN9252 supports six HBI modes. These six HBI modes (Multiplexed Modes and
Indexed Modes) can be selected using the SPST switches (P/N: 450301014042-Wurth
Electronics) SW5 through SW9 and SW22 through SW25. Through the switches the
LAN9252 HBI signals are connected to the SoC.
Note:
For switch P/N: 450301014042, pin 1 is at the middle of the switch. To short
1-2, knob position must be in the 1-3 position, and vice versa.
2.4.4.1.1
Multiplexed Modes
The following four HBI Multiplexed Modes are supported:
1.
2.
3.
4.
8-bit Multiplexed single-phase mode
16-bit Multiplexed single-phase mode
8-bit Multiplexed dual-phase mode
16-bit Multiplexed dual-phase mode
Each HBI Multiplexed Mode requires an updated ESI file, EEPROM and PDI driver with
configured SSC to be programmed to the PIC32MX. For additional software information, refer to Chapter 3. “Software Development Kit”.
Figure 2-5 details the switch selection for Multiplexed Mode. All four Multiplexed Modes
utilize the same switch positions.
FIGURE 2-5:
MULTIPLEXED HBI MODE SELECTION
Table 2-13 details the switch selection for Multiplexed Mode.
TABLE 2-13:
DS50002333C-page 20
MULTIPLEXED HBI MODE SELECTION
Switch
Switch Knob Position
Start
Destination
SW5
Down
A0_AD15
A0_CONFIG3
SW6
Up
RD_RDWR
GPMC_DIR
SW7
Down
ALELO_A1
A1_CONFIG3
SW8
Down
WR_ENB
GPMC_DE0N_CLE
SW9
Down
ALEHI_A2
A2_CONFIG3
SW24
Up
A0_CONFIG3
GPMC_A0_ALE
SW25
Up
A1_CONFIG3
GPMC_A1_ALEHI
2015-2016 Microchip Technology Inc.
Board Details & Configuration
Note:
When the switch knob is in the down position, pins 1-2 are shorted and the
dot on the switch can be seen. When the switch knob is in the up position,
pins 1-3 are shorted and no dot can be seen.
2.4.4.1.2
Indexed Mode
There are 2 different Indexed modes, 8-bit and 16-bit. Each HBI Indexed Mode requires
an updated ESI file, EEPROM and PDI driver with configured SSC to be programmed
to the PIC32MX. For additional software information, refer to Chapter 3. “Software
Development Kit”.
8-Bit Indexed Mode
Figure 2-6 details the switch selection for 8-Bit Indexed Mode.
FIGURE 2-6:
8-BIT INDEXED HBI MODE SELECTION
Table 2-14 details the switch selection for 8-bit Indexed HBI Mode.
TABLE 2-14:
8-BIT INDEXED HBI MODE SELECTION
Switch
Switch Knob Position
Start
Destination
SW5
Up
A0_AD15
AD15_CONFIG3
SW6
Up
RD_RDWR
GPMC_DIR
SW7
Up
ALELO_A1
ALELO_CONFIG3
SW8
Down
WR_ENB
GPMC_DE0N_CLE
SW9
Up
ALEHI_A2
ALEHI_CONFIG3
SW24
Down
ALELO_CONFIG3
GPMC_A0_ALE
SW25
Down
ALEHI_CONFIG3
GPMC_A1_ALEHI
Note:
When the switch knob is in the down position, pins 1-2 are shorted and the
dot on the switch can be seen. When the switch knob is in the up position,
pins 1-3 are shorted and no dot can be seen.
16-Bit Indexed Mode
Figure 2-7 details the switch selection for 16-Bit Indexed Mode.
FIGURE 2-7:
2015-2016 Microchip Technology Inc.
16-BIT INDEXED HBI MODE SELECTION
DS50002333C-page 21
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
Table 2-15 details the switch selection for 16-bit Indexed HBI Mode.
TABLE 2-15:
16-BIT INDEXED HBI MODE SELECTION
Switch
Switch Knob Position
Start
Destination
SW5
Down
A0_AD15
A0_CONFIG3
SW6
Up
RD_RDWR
GPMC_DIR
SW7
Up
ALELO_A1
ALELO_CONFIG3
SW8
Down
WR_ENB
GPMC_DE0N_CLE
SW9
Up
ALEHI_A2
ALEHI_CONFIG3
SW24
X (Don’t Care)
X
X
SW25
Down
ALEHI_CONFIG3
GPMC_A1_ALEHI
Note:
When the switch knob is in the down position, pins 1-2 are shorted and the
dot on the switch can be seen. When the switch knob is in the up position,
pins 1-3 are shorted and no dot can be seen.
Note:
If any other SoC is used, the user must check what modes are supported
and configure the HBI mode selection switches accordingly.
2.4.4.2
SPI+GPIO SELECTION
The knob position of SW11 to SW21 must be down to select the SPI+GPIO mode.
SW19, SW20, and SW21 are used to route the SPI/SQI signals from the LAN9252 to
the SoC. SW11 to SW18 are used to route the 16 GPIO signals from the LAN9252 to
the GPIO circuit.
TABLE 2-16:
SW19-SW21 SIGNAL DEFINITIONS
Switch
Signals
SW19 (pin 2-3 & pin 5-6)
SIO3 & SIO2
SW20 (pin 2-3 & pin 5-6)
SIO0 & SIO1
SW21 (pin 2-3 & pin 5-6)
SCK & SCS#
2.4.4.2.1
SPI/SQI/I2C Aardvark Header
J11 and J12 are used as Aardvark/SPI/SQI headers. The respective pin details are
shown in Table 2-17.
TABLE 2-17:
DS50002333C-page 22
J11 & J12 HEADER PINOUT
Signal
Pin Number
SCL
J11.1
SDA
J11.3
SCK
J11.7
SCS#
J11.9
SI(SIO0)
J11.8
SO(SIO1)
J11.5
SIO2
J12.3
SIO3
J12.4
2015-2016 Microchip Technology Inc.
Board Details & Configuration
2.4.4.3
GPIO INPUT/OUTPUT SELECTION
To enable the SPI+GPIO configuration, the SW11 to SW18 switches must be in the
down position. Additionally, the following switches must be configured to select the
input or output modes, as shown in Table 2-18.
TABLE 2-18:
GPIO MODE SWITCH CONFIGURATIONS
Switches
Switch Knob Position
Mode
SW28 to SW33
SW35 to SW39
SW41 to SW45
Short Pins 1 and 2
INPUT Mode
SW28 to SW33
SW35 to SW39
SW41 to SW45
Short Pins 1 and 3
OUTPUT Mode
2.4.4.3.1
GPIO INPUT Mode
In INPUT Mode, Digital I/O values can be selected through dip switches SW34 and
SW40:
• Logic 1 : (Default) SW34 & SW40 Off position. GPI0 to GPI15 tied to pull-up (R90
to R105)
• Logic 0 : The respective knob of 2-way, 8-position dip switch (SW34 & SW40)
need to be moved to ON side. Signals can be selected individually.
2.4.4.3.2
GPIO OUTPUT Mode
In OUTPUT Mode, updated GPO values will be seen on the green LEDs (D7 to D22):
• Logic 1 : LED illuminated (green)
• Logic 0 : LED not illuminated.
Note:
2.4.5
The LED (D7 to D22) anode is connected to ASIC.
SoC
The EVB-LAN9252-HBI+ supports both an on-board SoC and add-on SoC. By default,
the on-board SoC is enabled. However, an external add-on SoC can be connected via
the add-on SoC headers P1 and P2. The SoC selection is configured via the SW26
switch, as detailed in the following subsections.
2.4.5.1
SOC SELECTION
The SW26 switch selects the enabled SoC. The SW26 switch knob position must be
down (Text = “PIC”) to select the on-board PIC. If the switch knob position is up (Text =
“PIM”), then the add-on board/SoC is selected and the on-board PIC is always in the
reset state. Whenever an add-on board/SoC is used, the switch knob must be in the up
position.
TABLE 2-19:
SOC SELECTION
Switch
Position
SW26
Down
On-board PIC enabled
SW26
Up
Add-on board/SoC enabled
2015-2016 Microchip Technology Inc.
Settings
DS50002333C-page 23
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
2.4.5.2
ON-BOARD PIC
By default, the on-board Microchip PIC32MX795F512L (U7) is used as the default
SoC. The LAN9252 can be connected to the PIC using either an HBI or SPI interface.
The selection switches must be configured accordingly to enable the desired interface.
Refer to Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection” and Section 2.4.4.1 “HBI
Mode Selection” for additional details.
2.4.5.2.1
Reset
SW27 is used to reset the on-board PIC. The LAN9252 can also reset the SoC if the
reset pin is configured to output mode. For stability, a delay of approximately 180ms is
added from the 3.3V o/p to reset release.
2.4.5.2.2
ICSP Header
The on-board PIC programing is performed using the ICSP header J13. Table 2-20
details the ICSP header pinout
TABLE 2-20:
J13 ICSP HEADER PINOUT
J13 Pin
Settings
1
MLCR
2
3V3
3
GND
4
PGD2
5
PGC2
6
NC
2.4.5.2.3
SoC EEPROM
The EVB-LAN9252-HBI+ provides an optional SoC EEPROM. Some SoCs may
require an EEPROM. However, the PIC on-board SoC and PIC based add-on SoC
boards do not require this EEPROM.
2.4.5.3
ADD-ON SOC
An add-on board can be attached to the EVB-LAN9252-HBI+ to use an add-on SoC.
The add-on board must be mounted to the P1 and P2 connectors (2x23, 100mil normal
gold plated berg stick). The SW26 switch must be in the up position when using an
add-on SoC. Additionally, the J10 2-pin jumper must be shorted to route power to the
add-on board from the EVB-LAN9252-HBI+.
2.4.5.4
ESC ID SELECT
The signals shown in Table 2-21 are provided as EtherCAT® ID selection for complex
ESCs. Jumper J20 and respective pull-up resistors are used to configure the ID select
signals high or low. By default, there are no resistors populated and all signals are neither high or low. When required, populating the respective jumper or resistor will
change the ID select signal to low.
DS50002333C-page 24
TABLE 2-21:
ID SELECT SIGNALS
ID Selection
Signal
Signal Name
PIC Pin
Number
10k to Pull
High
Pins to Short
for Pull Low
ID0
ID0_SELECT_RB0
25
R123
32:31
ID1
ID_SELECT_RB1
24
R124
30:29
ID2
ID_SELECT_RB2
23
R125
28:27
ID3
ID_SELECT_RB3
22
R126
26:25
ID4
ID_SELECT_RB4
21
R127
24:23
2015-2016 Microchip Technology Inc.
Board Details & Configuration
TABLE 2-21:
2.5
ID SELECT SIGNALS (CONTINUED)
ID Selection
Signal
Signal Name
PIC Pin
Number
10k to Pull
High
Pins to Short
for Pull Low
ID5
ID_SELECT_RB5
20
R128
22:21
ID6
ID_SELECT_RB8
32
R129
20:19
ID7
ID_SELECT_RB9
33
R130
18:17
ID8
ID_SELECT_RB10
34
R131
16:15
ID9
ID_SELECT_RB11
35
R132
14:13
ID10
ID_SELECT_RB12
41
R133
12:11
ID11
ID_SELECT_RB13
42
R134
10:9
ID12
ID_SELECT_RC1
6
R135
8:7
ID13
ID_SELECT_RC2
7
R136
6:5
ID14
ID_SELECT_RC3
8
R137
4:3
ID15
ID_SELECT_RC4
9
R138
2:1
DIGIO & SPI+16GPIO SIGNALS ON P1 AND P2 HEADERS
2.5.1
DIGIO on P1 and P2 Headers (up to 16 bits supported)
The LAN9252 supports a DIGIO mode, where these signals can be probed on the P1
and P2 headers. To enable DIGIO mode, from the default state of the board, the SW26
switch must be changed to the PIM position (upward). The respective DIGIO signal
mappings on the P1 and P2 headers are detailed in Table 2-22.
Note 1:
2:
In the default state, headers P1 and P2 are not assembled. These headers
can each be populated with a Molex 87758-4616.
The user must ensure that the EEPROM is configured in DIGIO mode.
TABLE 2-22:
DIGIO MODE P1 & P2 HEADER SIGNALS
HBI Indexed
HBI Multiplexed
DIGIO
P1/P2 Pin
RD/RD_WR
RD/RD_WR
DIGIO15
P1.8
WR/ENB
WR/ENB
DIGIO14
P1.10
CS
CS
DIGIO13
P1.26
A4
-
DIGIO12
P1.41
A3
-
DIGIO11
P1.44
A2
ALEHI
DIGIO10
P2.21
A1
ALELO
OE_EXT
P1.7
A0/D15
AD15
DIGIO9
P1.15
D14
AD14
DIGIO8
P1.16
D13
AD13
DIGIO7
P1.11
D12
AD12
DIGIO6
P1.12
D11
AD11
DIGIO5
P1.17
D10
AD10
DIGIO4
P1.14
D9
AD9
LATCH_IN
P1.13
D8
AD8
DIGIO2
P1.19
D7
AD7
DIGIO1
P1.4
D6
AD6
DIGIO0
P1.3
D5
AD5
OUTVALID
P1.22
D4
AD4
DIGIO3
P1.23
2015-2016 Microchip Technology Inc.
DS50002333C-page 25
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
TABLE 2-22:
DIGIO MODE P1 & P2 HEADER SIGNALS (CONTINUED)
HBI Indexed
HBI Multiplexed
DIGIO
P1/P2 Pin
D3
AD3
WD_TRIG
P1.6
D2
AD2
SOF
P1.5
D1
AD1
EOF
P1.24
D0
AD0
WD_STATE
P1.25
2.5.2
SPI+GPIO on P1 and P2 Headers (up to 16 bits supported)
The LAN9252 supports an SPI+16GPIO mode, where these signals can be probed on
the P1 and P2 headers. To enable SPI+16GPIO mode, from the default state of the
board, the SW26 switch must be changed to the PIM position (upward) and SW19,
SW20, and SW21 must be changed to the downward side. The respective
SPI+16GPIO signal mappings on the P1 and P2 headers are detailed in Table 2-23.
Note 1:
2:
In the default state, headers P1 and P2 are not assembled. These headers
can each be populated with a Molex 87758-4616.
The user must ensure that the EEPROM is configured in DIGIO mode.
TABLE 2-23:
DS50002333C-page 26
SPI+16GPIO MODE P1 & P2 HEADER SIGNALS
HBI Indexed
HBI Multiplexed
SPI+16GPIO
P1/P2 Pin
RD/RD_WR
RD/RD_WR
GPI15/GPO15
P1.8
WR/ENB
WR/ENB
GPI14/GPO14
P1.10
CS
CS
GPI13/GPO13
P1.26
A4
-
GPI12/GPO12
P1.41
A3
-
GPI11/GPO11
P1.44
A2
ALEHI
GPI10/GPO10
P2.21
A0/D15
AD15
GPI9/GPO9
P1.15
D14
AD14
GPI8/GPO8
P1.16
D13
AD13
GPI7/GPO7
P1.11
D12
AD12
GPI6/GPO6
P1.12
D11
AD11
GPI5/GPO5
P1.17
D10
AD10
GPI4/GPO4
P1.14
D9
AD9
SCK
P1.13
D8
AD8
GPI2/GPO2
P1.19
D7
AD7
GPI1/GPO1
P1.4
D6
AD6
GPI0/GPO0
P1.3
D5
AD5
SCS#
P1.22
D4
AD4
GPI3/GPO3
P1.23
D3
AD3
SIO3
P1.6
D2
AD2
SIO2
P1.5
D1
AD1
SO/SIO1
P1.24
D0
AD0
SI/SIO0
P1.25
2015-2016 Microchip Technology Inc.
Board Details & Configuration
2.6
ADDITIONAL FEATURES
The EVB-LAN9252-HBI+ includes additional features that were not available in the previous revision of the board. This section details these additional features. To learn more
about how to use them refer to the Quick Start guide found at microchip.com.
2.6.1
Potentiometer
The EVB-LAN9252-HBI+ includes a potentiometer, as shown in Figure 2-8. The potentiometer is used as an input to the PIC32 and is labeled as “pot1” on the board.
FIGURE 2-8:
2.6.2
POTENTIOMETER POT1
Temperature Sensor
The EVB-LAN9252-HBI+ includes a Microchip temperature sensor (TC104AVNBTR),
as shown in Figure 2-9. The temperature sensor is used as an input into the PIC32 and
is labeled “U9” on the board.
FIGURE 2-9:
2.6.3
TEMPERATURE SENSOR U9
UART RS-232
A RS-232 connector is present on the board as J24. This allows serial communication
with the PIC32. With this connector UART communication is possible as both an input
and an output.
2.6.4
DAC
Through an on-board Microchip digital to analog converter (MCP4726) it is possible to
use the EtherCAT application to input a value to the DAC and get a calculated voltage
output on the DAC. It it labeled as U10 on the board and can be seen next to the potentiometer.
2.7
LIMITATIONS
The EVB-LAN9252-HBI+ has the following limitations:
1. While the LAN9252 supports both SFP and SFF Fiber Modes, the
EVB-LAN9252-HBI+ supports only the SFP Fiber Mode.
2. SQI is not supported when using the on-board PIC32MX.
2015-2016 Microchip Technology Inc.
DS50002333C-page 27
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
2.8
MECHANICALS
FIGURE 2-10:
DS50002333C-page 28
EVB-LAN9252-HBI+ MECHANICAL DIMENSIONS
2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Chapter 3. Software Development Kit
This chapter explains the architecture of the LAN9252 EtherCAT® slave stack firmware
sample and introduces the SDK framework for use with PIC32MX microcontroller for
EVB-LAN9252-HBI+ development.
This chapter includes the following sub-sections:
•
•
•
•
3.1
Prerequisites
ESC SDK Sample Overview
Using the Sample Project
Programming the LAN9252 EEPROM
PREREQUISITES
3.1.1
Hardware Requirements
• EVB-LAN9252-HBI+-SPI-SQI-GPIO
• Windows Host Machine with minimum 2GB RAM
• Programmers – Aardvark I2C/SPI Host Adapter, Pickit3 Programmer
3.1.2
Software Requirements
• MPLAB IDE v2.20 or higher
• MPLAB XC Compiler v1.33 or higher
• Total Phase Flash Centre V1.31 or higher
3.2
ESC SDK SAMPLE OVERVIEW
The LAN9252 ESC supports interfacing to an external SoC using an SPI or HBI interface. This PIC32 based SDK sample contains separate projects for HBI and SPI interfaces.
This software SDK is developed as a bare-metal firmware implementation (not specific
to any OS) designed to access the LAN9252 ESC features via an HBI or SPI interface.
The EtherCAT® slave stack portion of the source is obtained from EtherCAT Technology Group.
This software project has been tested with the EVB-LAN9252-HBI+ using the
PIC32MX SoC.
Figure 3-1 provides an architectural block diagram of the SDK’s various source modules. The subsequent sections detail these blocks.
2015-2016 Microchip Technology Inc.
DS50002333C-page 29
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
FIGURE 3-1:
PIC32 SOC FIRMWARE FRAMEWORK
3.2.1
User Module
3.2.1.1
SOC INITIALIZATION
This code block is part of the user application that boots the PIC microcontroller with
the desired RAM configuration, clock speed, clock source and other related features of
the controller, per the user’s configuration.
3.2.1.2
PERIPHERAL INITIALIZATION
This code block configures and initiates the core peripherals (UART, I2C, SPI) and
external peripherals (EEPROM, LAN9252).
3.2.1.3
MAIN APPLICATION
This code block contains the code that runs the LAN9252 EtherCAT® slave module
demo application.
3.2.2
EtherCAT® Slave Stack
This code block contains the EtherCAT slave stack.
3.2.3
Hardware Abstraction Layer (HAL)
This code block contains the low level layer that provides software hooks/APIs to the
application module and slave stack, allowing communication between these modules
and the hardware resources. For additional information, refer to the ReadMe.txt file
located in the project source folder.
DS50002333C-page 30
2015-2016 Microchip Technology Inc.
Software Development Kit
3.3
USING THE SAMPLE PROJECT
3.3.1
MPLAB IDE Project Settings & Firmware Download
1. Once the EtherCAT SSC is integrated with LAN9252 SDK as detailed in “Integrat‐
ing LAN9252 ‐ PIC32MX SDK with EtherCAT SSC from ETG” application note,
Copy it to the desired directory. (For the purposes of this document, the Desk‐
top will be the target folder).
2. Open the MPLAB IDE and import the SSC project into the IDE.
FIGURE 3-2:
MPLAB IDE OPEN PROJECT
FIGURE 3-3:
MPLAB IDE PROJECT DIRECTORY
The target directory contains two project folders:
• PIC32-HBI Project Folder
• PIC32 Project Folder
2015-2016 Microchip Technology Inc.
DS50002333C-page 31
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
3.3.1.1
PIC32-HBI PROJECT FOLDER
The PIC32 project folder contains the sample code that enables the LAN9252's HBI
interface to communicate with the SoC. HBI demo code is provided for each of the
LAN9252’s six HBI configurations. These configurations can be selected respectively
from the configuration drop down box as shown in Figure 3-4.
TABLE 3-1:
HBI CONFIGURATIONS
HBI Configuration (Project)
Description
HBI_INDEXED_8BIT_XC32_PIC32MX79F512
8-bit Indexed mode
HBI_INDEXED_16BIT_XC32_PIC32MX79F512
16-bit Indexed mode
HBI_MDP_8BIT_XC32_PIC32MX79F512
8-bit Multiplexed dual phase mode
HBI_MDP_16BIT_XC32_PIC32MX79F512
16-bit Multiplexed dual phase mode
HBI_MSP_8BIT_XC32_PIC32MX79F512
8-bit Multiplexed single phase mode
HBI_MSP_16BIT_XC32_PIC32MX79F512
16-bit Multiplexed single phase mode
FIGURE 3-4:
3.3.1.2
MPLAB IDE HBI CONFIGURATION SELECTION
PIC32 PROJECT FOLDER
The PIC32-SPI project folder contains the demo code that enables the LAN9252's SPI
interface to communicate with the SoC.
• Refer to the LAN9252 data sheet for more details on these HBI interface and its
modes.
• Refer to Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection” for SPI jumper configurations.
DS50002333C-page 32
2015-2016 Microchip Technology Inc.
Software Development Kit
3.3.2
Compiling and Programming SoC Firmware
1. Compile the source code (with corresponding configuration selected if HBI project is loaded).
FIGURE 3-5:
MPLAB IDE COMPILE PROJECT SELECTION
2. If the compilation is successful, the output window will display “BUILD SUCCESSFUL”, as shown in Figure 3-6.
FIGURE 3-6:
MPLAB IDE BUILD SUCCESSFUL
3. Before initiating the firmware download, ensure the debugger/programmer is
connected to the EVB’s JTAG pins. (This demo project is debugged with the
PICkit-3 In-Circuit debugger/programmer).
4. To program the PIC32 SoC, click the “Make and Program Device Main Project”
button.
FIGURE 3-7:
2015-2016 Microchip Technology Inc.
MPLAB IDE PROGRAM DEVICE
DS50002333C-page 33
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
5. To debug the PIC32 SoC, click “Debug Main Project” button.
FIGURE 3-8:
3.4
MPLAB IDE DEBUG DEVICE
PROGRAMMING THE LAN9252 EEPROM
The LAN9252 configures itself to the desired mode (SPI, 6 HBI modes) by reading the
strap settings located in EEPROM. The LAN9252 EEPROM is programmed and validated via the TwinCAT master tool. The EEPROM can also be programmed using an
external IIC Master, like AARDVARK.
3.4.1
Programming LAN9252 EEPROM using the TwinCAT Master
Tool
The programming procedure using the TwinCAT master tool is as follows:
Note 1:
This example utilizes the TwinCAT tool. Procedures may differ when using
other EtherCAT® master tools.
2:
Ensure the system network properties are configured properly for the EtherCAT® frames, Ethernet cable linking your system, and EtherCAT® slave
board.
1. Load the corresponding ESI file in the directory path "C:\TwinCAT\3.1\Config\Io\EtherCAT". For this demo, the ESI file for the 16-Bit Multiplexed Single-Phase Mode is used.
2. If TwinCAT installed successfully, a TwinCAT icon will be shown in the bottom-right corner of the desktop. After clicking the icon, a pop-up list will display.
Select “TwinCAT XAE (VS 2013)”, as shown in Figure 3-9.
FIGURE 3-9:
DS50002333C-page 34
TWINCAT SYSTEM MANAGER
2015-2016 Microchip Technology Inc.
Software Development Kit
3. Click on “New TwinCAT Project” as shown in Figure 3-10. Choose a name and
click “ok”.
FIGURE 3-10:
TWINCAT DELETE DEVICE
4. Scan for EtherCAT® slave devices by expanding “I/O” and right clicking
“Devices” and then selecting “Scan”, as shown in Figure 3-11.
FIGURE 3-11:
TWINCAT SCAN DEVICES
5. After scanning is complete, a window showing devices found will appear similar
to Figure 3-12.
2015-2016 Microchip Technology Inc.
DS50002333C-page 35
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
FIGURE 3-12:
TWINCAT DEVICE LIST
6. Click “Yes” for Scan for Boxes and “Yes” for Activate Free Run.
7. After a successful scan, click the “Device 2 (EtherCAT)” drop down bar on the left
panel of the TwinCAT tool (as highlighted in Figure 3-11). Then click the “Online”
tab on the right-side panel of the TwinCAT tool, as shown in Figure 3-13. Right
click the LAN9252 listing and select “EEPROM Update” from the contextual
menu.
FIGURE 3-13:
TWINCAT EEPROM UPDATE
8. Upon selecting “EEPROM Update”, the Write EEPROM window will open. Click
the “OK” button to initiate EEPROM programming (Figure 3-14).
FIGURE 3-14:
DS50002333C-page 36
TWINCAT WRITE EEPROM
2015-2016 Microchip Technology Inc.
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Appendix A. Evaluation Board Photo
A.1
INTRODUCTION
This appendix shows the EVB-LAN9252-HBI+ Evaluation Board.
FIGURE A-1:
EVB-LAN9252-HBI+ EVALUATION BOARD
2015-2016 Microchip Technology Inc.
DS50002333C-page 37
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Appendix B. Evaluation Board Schematics
B.1
INTRODUCTION
This appendix shows the EVB-LAN9252-HBI+ Evaluation Board Schematics.
2015-2016 Microchip Technology Inc.
DS50002333C-page 38
EVB-LAN9252-HBI+ SCHEMATIC POWER SUPPLY & RESET
5
4
3
2
POWER SUPPLY
3
5V_SW
3
R1
0R
2A/0.05DCR
2
Switch, SPDT, Slide
P/N:1101M2S3CQE2
J1
C2
10uF
25V
EN12_1
2
1
VIN
ENABLE
VOUT
TRIM
3_Amp
GND
C3
C1
3
0.1uF OKR-T/3-W12-C
R3
3.30K
1%
(Ra)
3V3
C5
4.7uF
DNP
0.1uF
D1
GRN
Note:
1.POR -> Reset to ASIC & SOC (Default)
2.RESET O/P from ASIC -> Reset to EX-PHY (PORT2) & SOC :Only Ethercat sku
3.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC
4.RESET from Push Botton -> Reset to ASIC & SOC
RESET
3
R8
1K
2
NDS355AN_NMOS
1
D
RST#
Q1
1
G
5
RESET#
3
MR#
S
Br_Red-RA
U3
2
4
TPS3125
74LVC1G14
R9
2.2K
1
A
C
2
D2
"Reset"
DS50002333C-page 39
Evaluation Board Schematics
SOT23_5
Threshold = 2.64V
Delay = 180ms
B
C4
10uF
3V3
VDD
4
(Rb)
R4A
33R
1%
5
U2
2
1/10W
1%
2
sw_pb_2P
1
R7
100E
GND
SW2
R5
4.75K
1%
0.1uF
2
1
C6
R6
10K
1/10W
1%
R4
470R
1%
RESET Options
3V3
Reset Generator
TP4
BLACK
R2
1K
4
5
3V3
C
TP3
BLACK
1
2
D
U1
FB1
A
1
C
5V_EXT
3V3
3V3
"3V3 Present"
SW1
1
TP2
ORANGE
3 V REGULATOR, 3A
( 3V3 fixed when Rb=503e)
5V
2
TP1
RED
1
3
2015-2016 Microchip Technology Inc.
FIGURE B-1:
EVB-LAN9252-HBI+ SCHEMATIC LAN9252
5
4
3V3
3
2
1
Power Supply Filtering
VDD33TXRX1
FB2
3V3
2A/0.05DCR
VDDCR
VDD12TX1
VDD12TX2
VDD33TXRX1
VDD33TXRX2
BLM18EG221SN1D
0.1uF
C20
C21
C22
470pF
0.1uF
0.1uF
C19
1uF
D
FB5
2A/0.05DCR
18pF
REG_EN
R10
12.1K
1%
RBIAS
7
57
RST#
11
IRQ
44
ATEST/FXLOSEN
8
41
B
I2C2_SCL
I2C2_SDA
43
42
GPIO0
GPIO1
GPIO2
48
46
45
56
59
6
24
38
14
20
32
37
47
VDD12TX1
VDD12TX2
VDDCR1
VDDCR2
VDDCR3
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDD33BIAS
VDD33
FXSDENA/FXSDA/FXLOSA
INT PORT0
C27
OSCVDD12
OSCI
OSCO
OSCVSS
REG_EN
RBIAS
RST#
TXNA
TXPA
RXNA
RXPA
9
FXSDA/FXLOSA
52
53
54
55
TXNA
TXPA
RXNA
RXPA
63
62
61
60
TXNB
TXPB
RXNB
RXPB
10
FXSDB/FXLOSB
IRQ
ATEST/FXLOSEN
TESTMODE
I2CSCL/EESCL/TCK
I2CSDA/EESDA/TMS
INT PORT1
(Only for
Lan9252)
1
3
1
2
4
I2C
OSCI
OSCO
3V3
OTHER
SIGNALS
25.000MHz
25ppm
Y1
OSC
POWER
2
18pF
VDD33TXRX1
VDD33TXRX2
C
Note:
OSCVSS need to connect to Chip gnd.
C26
58
5
U4A
C
51
64
VDD12TX1
VDD12TX2
0.1uF
C25
Low ESR
C16
C17
0.1uF
0.1uF
C14
C13
C15
0.1uF
0.1uF
0.1uF
C12
DNP
C11
VDDCR
C18
3V3
2A/0.05DCR
C24
0.1uF
3V3
FB4
C23
1.0uF
DNP
1.0uF
3V3
0.1uF
C9
2A/0.05DCR
0.1uF
FB3
0.1uF
VDD33TXRX2
C10
D
C8
DNP
1.0uF
C7
1.0uF
DNP
TXNB
TXPB
RXNB
RXPB
FXSDENB/FXSDB/FXLOSB
B
LINKACTLED0/TDO/LEDPOL0/CHIP_MODE0
LINKACTLED1/TDI/LEDPOL1/CHIP_MODE1
RUNLED/LEDPOL2/E2PSIZE
LAN9252
65
2015-2016 Microchip Technology Inc.
GND
GPIO
A
A
Chennai
India
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
LAN9252
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
D
4
of
12
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 40
FIGURE B-2:
EVB-LAN9252-HBI+ SCHEMATIC COPPER MODE INTERFACE
5
4
3
2
1
VDD33TXRX1
D
DNP
R16
R17
0R
0R
FX_SFP-TXPA
DNP
R18
R19
0R
0R
FX_SFP-TXNA
RXPA
DNP
R20
R21
0R
0R
FX_SFP-RXPA
RXNA
DNP
R22
R23
TXPA
TXNA
R13
49.9R
1/10W
1%
R14
49.9R
1/10W
1%
R15
0R
9
A
C
R12
49.9R
1/10W
1%
10
T1
Pulse J0011D01BNL
R11
49.9R
1/10W
1%
GRN
1
COP-TXPA
4
2
COP-TXNA
RJ45
D
XMIT
TD+
75
1
75
TXCT
4&5
TD-
2
LED1 (Green) = LINK/ACT
8
50V
10%
6
1000 pF
NC
CHS GND
Note:
Capacitors C10 through C13 are optional for EMI purposes
and are not populated on the LAN8740/41 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
2 kV
YEL
R24
C
A1
7
12
C32
0.022uF
C1
C31
10pF
50V
5%
DNP
11
C30
10pF
50V
5%
DNP
13
C
C29
10pF
50V
5%
DNP
7&8
RD-
MTG1
C28
10pF
50V
5%
DNP
3
75
RXCT
MTG
6
16
COP-RXNA
75
15
FX_SFP-RXNA
RD+
GND1
5
GND
0R
0R
LED2 (Yellow) = SPEED
RCV
3
COP-RXPA
14
2015-2016 Microchip Technology Inc.
FIGURE B-3:
0R
RES1210
VDD33TXRX2
B
TXPB
DNP
R30
R31
0R
0R
FX_SFP-TXPB
R28
49.9R
1/10W
1%
R29
0R
1
COP-TXPB
FX_SFP-TXNB
RXPB
DNP
R34
R35
0R
0R
FX_SFP-RXPB
RXNB
DNP
R36
R37
COP-TXNB
2
COP-RXPB
3
RJ45
B
XMIT
TD+
75
75
1
TXCT
4&5
TD-
2
LED1 (Green) = LINK/ACT
CHS GND
2 kV
YEL
A
DS50002333C-page 41
A1
8
6
1000 pF
NC
12
50V
10%
7
C1
C37
0.022uF
13
A
C36
10pF
50V
5%
DNP
11
C35
10pF
50V
5%
DNP
MTG1
C34
10pF
50V
5%
DNP
3
7&8
RD-
MTG
C33
10pF
50V
5%
DNP
75
RXCT
16
6
15
COP-RXNB
75
GND1
FX_SFP-RXNB
RD+
GND
5
14
0R
0R
LED2 (Yellow) = SPEED
RCV
Chennai
India
Note:
Capacitors C10 through C13 are optional for EMI purposes
and are not populated on the LAN8740/41 evaluation board.
These capacitors are required for operation in an EMI
constrained environment.
R38
0R
RES1210
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
Copper Mode Interface
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
5
of
D
12
Evaluation Board Schematics
0R
0R
9
GRN
A
C
R27
49.9R
1/10W
1%
4
DNP
R32
R33
TXNB
R26
49.9R
1/10W
1%
10
T2
Pulse J0011D01BNL
R25
49.9R
1/10W
1%
EVB-LAN9252-HBI+ SCHEMATIC SFP INTERFACE
5
4
3V3
R39
82R
D
R40
82R
R41
49.9R
R42
49.9R
3
Note:Place
capacitors,
and resistors
close to FOT
3V3
Fiber Port 0 :SFP Interface
R43
82R
C38
0.1uF
C40
0.1uF
FX_SFP-RXNA
R44
82R
R45
49.9R
2
1
Note:Place
capacitors,
and resistors
close to FOT
Fiber Port 1 :SFP Interface
R46
49.9R
C39
0.1uF
C41
0.1uF
C43
0.1uF
D
FX_SFP-RXNB
FX_SFP-RXPA
FX_SFP-RXPB
C42
FX_SFP-TXPA
0.1uF
FX_SFP-TXPB
3V3
R47
100E
3V3
R48
100E
SFP_VCCT
C44
L2
SFP_VCCR
FX_SFP-TXNA
1uH
C45
+
C47
0.1uF
C48
10uF
16V
+
C49
0.1uF
R51
130R
R52
130R
L1
1uH
SFP_VCCR2
C50
10uF
16V
DNP
+
C51
0.1uF
C56
31 10uF
30 16V
29
28
27
26
25
24
23
22
21
+
C57
0.1uF
SFP_RD2+
SFP_RD2-
C46
10uF
16V
DNP
SFP_TD2SFP_TD2+
SFP_RD+
SFP_RD-
SFP_TDSFP_TD+
R50
130R
0.1uF
FX_SFP-TXNB
0.1uF
R49
130R
SFP_VCCT2
C52
10uF
16V
L3
L4
B
R53
4.7K
R54
4.7K
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
ASIC
J3
FTLF1217P2
R55
4.7K
31
30
29
28
27
26
25
24
23
22
21
SFP_VCCT2
1
2
3
4
5
6
7
8
9
10
SFP_VCCT
Note:Place
resistors
close to
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
FTLF1217P2
31
30
29
28
27
26
25
24
23
22
21
C55
0.1uF
1
2
3
4
5
6
7
8
9
10
J2
VeeT
TXFault
TX Disable
MOD-DEF(2)
MOD-DEF (1)
MOD-DEF (0)
Rate Select
LOS
VeeR
VeeR1
ASIC
31
30
29
28
27
26
25
24
23
22
21
+
1uH
C
20
19
18
17
16
15
14
13
12
11
VeeT1
TDTD+
VeeT2
VccT
VccR
VeeR2
RD+
RDVeeR3
Note:Place
resistors
close to
C54
10uF
16V
C53
0.1uF
1uH
20
19
18
17
16
15
14
13
12
11
C
+
R56
4.7K
R57
4.7K
R58
4.7K
R59
4.7K
B
R60
4.7K
2015-2016 Microchip Technology Inc.
FXSDB/FXLOSB
FXSDA/FXLOSA
A
A
Chennai
India
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
SFP Interface
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
6
of
D
12
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 42
FIGURE B-4:
EVB-LAN9252-HBI+ SCHEMATIC STRAP, GPIO, I2C & FXLOS
5
4
3
2
1
GPIO [0:2] & LED_POL_Strap
I2C EEPROM
3V3
7
R73
1K
WP
SW DIP-4/SM
R74
1K
2
2
2
3
1
GPIO2
2K
2K
5
I2C2_SDA
6
I2C2_SCL
TH IC.
Different sizes can be mounted
I2C EEPROM Lower size
Below 16K(2K X 8)
J9
3
1
J8
3
1
J7
GPIO0
8
SCL
24FC04
C
SDA
4
R72
1K
A0
A1
A2
R68
R67
1
2
3
VCC
I2C2_1
I2C2_2
I2C2_3
I2C2_7
0.1uF
GND
2
1
2
3
4
4.7K
SW3
8
7
6
5
4.7K
LED1_ANODE
LED1_CATHODE
2
R66
R63
U5
4.7K
R71
10K
R64
3
1
2
R70
10K
D
GPIO2
LED0_CATHODE
LED2_CATHODE
3V3
C58
GPIO1
1
1
LED0_ANODE
LED2_ANODE
1
R69
10K
3V3
GPIO0
J6
2
J5
2
J4
3V3
GPIO1
3
1
3
1
D
GPIO2
R65
3V3
GPIO0
4.7K
3V3
2
2015-2016 Microchip Technology Inc.
FIGURE B-5:
GPIO1
I2C EEPROM Higher size
Above 16K(2K X 8)
C
LINK/ACT
LED0_ANODE
LED0_CATHODE
D3 1
GRN A
2
C
LINK/ACT
LED1_ANODE
LED1_CATHODE
D4 1
GRN A
FX_Los_Strap_1 & 2
2
C
3V3
RUNLED
LED2_ANODE
LED2_CATHODE
D5 1
GRN A
2
R77
10K
DNP
C
GPIO0 =LED0,LEDPOL0,MNGT0
GPIO1 = LED1,LEDPOL1,MNGT1
ATEST/FXLOSEN
R79
10K
GPIO2 = LED2,LEDPOL2,E2PSIZE
B
Management/LED Polarity Strap
Signal Name
Connector
Logic
3V3
FXSDA/FXLOSA
R76
10K
R78
DNP 10K
R80
10K
5 $VVHPEOH 5 '13
$ERYH9VHOHFWV);/26IRUSRUWV$DQG%
3V3
5 . 5 .
/HYHORI9VHOHFWV);/26IRUSRUW$DQG
);6'&RSSHUWZLVWHGSDLUIRUSRUW%IXUWKHUGHWHUPLQHGE\);6'(1%
FXSDB/FXLOSB
B
'HIDXOW
&RSSRUPRGH
55$VVHPEOH
5 5 '13
LED Polarity Strap
The LED is set as active high.
1
J48,J51 (1&2)
The LED is set as active low,
0
J50,J53 (2&3)
The LED is set as active high.
1
J50,J53 (1&2)
The LED is set as active low,
0
J49,J52 (2&3)
The LED is set as active high.
EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)
1
J49,J52 (1&2)
The LED is set as active low,
EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)
)LEHU0RGH
55'13
5 5 $VVHPEOH
MNGT1
A
DNP 10K
E\);6'(1$DQG);6'(1%
MNGT0
E2ESIZE
R75
Note:
--To use GPIOs as LED
* Short 2-3 of both jumpers (ex. for GPIO0 short 2-3 of J48 & J51)
A
DS50002333C-page 43
Chennai
India
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
STRAP,GPIO,I2C & FXLOS
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
7
of
D
12
Evaluation Board Schematics
J48,J51 (2&3)
0
FX_Mode_Strap_1 & 2
'HIDXOW
&RSSRUPRGH
5 '13 5 $VVHPEOH
6HOHFWV);6'FRSSHUWZLVWHGSDLUIRUSRUWV$DQG%IXUWKHUGHWHUPLQHG
EVB-LAN9252-HBI+ SCHEMATIC BOARD TO BOARD INTERFACE
5
4
R83 DNP
R86 DNP
DNP
C59
0.1uF
DNP
2K
DNP
R82
1
2
3
7
SW DIP-4/SM
DNP
U6
24FC512
DNP
VCC
4.7K
I2C3_1
I2C3_2
I2C3_3
I2C3_7
A0
A1
A2
SDA
A4/DIGIO12/GPI12/GPO12/MII_RXD0
A3/DIGIO11/GPI11/GPO11/MII_RXDV
A2/ALEHI/DIGIO10/GPI10/GPO10/LINKACTLED2/MII_LINKPOL/LEDPOL6
A1/ALELO/OE_EXT/MII_CLK25
SCL
WP
31
30
28
RD_RDWR
WR_ENB
CS
5
I2C1_SDA
6
I2C1_SCL
GND
1
2
3
4
I2C EEPROM
Only for Host SOC
PME_LATCH1
18
FIFOSEL_LATCH0
34
C
AD5_CONFIG3
AD1_CONFIG3
CS_CONFIG3
PME_LATCH1
FIFOSEL_LATCH0
A3_CONFIG3
A1_CONFIG3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
27
26
29
25
A4
A3
ALEHI_A2
ALELO_A1
33
15
16
21
22
23
19
40
39
36
50
49
35
12
13
17
A0_AD15
AD14
AD13
AD12
AD11
AD10
AD9_SCK
AD8
AD7
AD6
AD5_SCS#
AD4
AD3_SIO3
AD2_SIO2
AD1_SIO1
AD0_SIO0
RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3
WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2
CS/DIGIO13/GPI13/GPO13/MII_RXD1
A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER
D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1
D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0
D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1
D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0
D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN
D9/AD9/LATCH_IN/SCK
D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO
D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC
D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK
D5/AD5/OUTVALID/SCS#
D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK
D3/AD3/WD_TRIG/SIO3
D2/AD2/SOF/SIO2
D1/AD1/EOF/SO/SIO1
D0/AD0/WD_STATE/SI/SIO0
SYNC/LATCH1
SYNC/LATCH0
P1
AD7_CONFIG3
AD3_CONFIG3
GPMC_OEN_REN
GPMC_WEN
AD12_CONFIG3
AD10_CONFIG3
AD14_CONFIG3
1
U4B
4
8
7
6
5
4.7K
D
4.7K
4.7K
SW4
2
3V3
2K
DNP
R85
3
8
DNP
R84
Host SOC EEPROM
R81
3V3
D
LAN9252
AD6_CONFIG3
AD2_CONFIG3
ALELO_CONFIG3
GPMC_BE0N_CLE
AD13_CONFIG3
AD9_CONFIG3
AD15_CONFIG3
AD11_CONFIG3
AD8_CONFIG3
AD15_CONFIG3
2
A0_CONFIG3
3
ALELO_CONFIG3
2
A1_CONFIG3
3
AD4_CONFIG3
AD0_CONFIG3
1
2
A2_CONFIG3
3
GPMC_DIR
2
GPMC_OEN_REN
3
GPMC_WEN
2
1
A0_AD15_CONFIG3
JS102011CQN
SW7 *(1-2)
1
ALEHI_CONFIG3
SW6 *(2-3)
SW5 *(1-2)
1
GPMC_BE0N_CLE 3
1
2
RST_GPIO
ALEHI_A2_CONFIG3
JS102011CQN
1 D6
SYS_RESETN
2
C
SW8 *(1-2)
ALELO_A1
JS102011CQN
SW9 *(1-2)
RD_RDWR_CONFIG3
JS102011CQN
WR_ENB_CONFIG3
JS102011CQN
SW10 *(2-3)
1
RST#
JS102011CQN
3
DIODE
A4_CONFIG3
A2_CONFIG3
A0_CONFIG3
Short 1 -2 = To Reset ASIC from SoC-GPIO
Short 2-3 = To Reset SoC from ASIC
SW11
AD4_CONFIG3
HEADER 23x2
AD4
GPIO3_CONFIG5
1
2
3
4
5
6
AD8
AD8_CONFIG3
HBI or SPI+GPIO Config selection
Short 1-2 & 4-5 for HBI Config (2-3 & 5-6 open)
GPIO2_CONFIG5
SW12
TP5
ORANGE
B
AD7_CONFIG3
P2
VDD3V3EXP
VDD_5V
SYS_RESETN
GPMC_DIR
2015-2016 Microchip Technology Inc.
I2C1_SDA
SIO3_CONFIG5
SCS#_CONFIG5
SIO1_CONFIG5
A
IRQ
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
AD7
GPIO1_CONFIG5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
VDD3V3EXP
VDD_5V
C60
DNP
2
Short 2-3 & 5-6 for SPI+GPIO Config (1-2 & 4-5 open)
AD6
AD6_CONFIG3
B
SW19
GPIO0_CONFIG5
AD3_SIO3
SW13
5V power to
HOST SOC board
from EVB Board
0.1uF
4
5
6
AD3_CONFIG3
5V
J10
1
1
2
3
A0_AD15_CONFIG3
A0_AD15
GPIO9_CONFIG5
4
5
6
RD_RDWR
SIO3_CONFIG5
RD_RDWR_CONFIG3
GPIO15_CONFIG5
WR_ENB
GPIO14_CONFIG5
1
2
3
AD0_CONFIG3
ALEHI_CONFIG3
4
5
6
ALEHI_A2_CONFIG3
ALEHI_A2
CS_CONFIG3
CS
GPIO13_CONFIG5
1
2
3
A3_CONFIG3
A3
GPIO11_CONFIG5
1
2
3
AD2_SIO2
AD2_CONFIG3
SIO2_CONFIG5
1
2
3
4
5
6
AD1_SIO1
AD1_CONFIG3
SIO1_CONFIG5
GPIO10_CONFIG5
SW21
4
5
6
A4
4
5
6
AD10
4
5
6
AD12
AD9_CONFIG3
A4_CONFIG3
AD9_SCK
SCK_CONFIG5
GPIO12_CONFIG5
SW16
1
2
3
4
5
6
AD5_SCS#
AD5_CONFIG3
SCS#_CONFIG5
SW22,SW23 & SW24 = HBI or SPI selection
AD10_CONFIG3
GPIO4_CONFIG5
RST_GPIO
A
SW17
AD11_CONFIG3
AD11
1
2
3
AD13
1
2
3
GPIO5_CONFIG5
HEADER 23x2
AD12_CONFIG3
GPIO6_CONFIG5
Chennai
India
SW18
AD13_CONFIG3
Board to Board Connectors for SoC
GPIO7_CONFIG5
4
5
6
AD14
AD14_CONFIG3
GPIO8_CONFIG5
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
AD0_SIO0
SIO0_CONFIG5
SW15
SIO2_CONFIG5
SIO0_CONFIG5
SCK_CONFIG5
4
5
6
SW20
SW14
WR_ENB_CONFIG3
I2C1_SCL
1
2
3
1
2
3
4
3
2
B
JUTLAND
Page:
Board
Name:
LAN9252(Part2)
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
8
of
D
12
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 44
FIGURE B-6:
EVB-LAN9252-HBI+ SCHEMATIC PIC32MX
AD13_CONFIG3
AD12_CONFIG3
AD15_CONFIG3
AD14_CONFIG3
AD8_CONFIG3
AD9_CONFIG3
AD10_CONFIG3
AD11_CONFIG3
RA0
FIFOSEL_LATCH0
PME_LATCH1
0R
0R
0R
PIC_MCLR
SW26
JS202011CQN
1
4
2
5
3
6
PIM_MCLR
SW27
A0_CONFIG3
3
SoC_SOSCI
ALELO_CONFIG3
SoC_SOSCO
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C63
*(2-3)
SW25
2
A1_CONFIG3
3
ALEHI_CONFIG3
GPMC_A1_ALEHI 1
GPMC_A1_ALEHI
JS102011CQN
11pF
DNP
32Khz
Y2
IRQ
RD11
CS_CONFIG3
RD9
RD8
C64
Aardvark / SPI Storm- Connector
11pF
DNP
I2C_SDA_DAC_CTL
I2C_SCL_DAC_CTL
C65
20pF
SIO1_CONFIG5 0R
SCK_CONFIG5 0R
SCS#_CONFIG5
Y3
8 Mhz
RA5
RA4
I2C1_SDA
I2C1_SCL
RG2
RG3
C66
J11
I2C2_SCL
I2C2_SDA
SoC_OSC2
R62
R122
2
4
6
8
10
C
R61
0R SIO0_CONFIG5
20pF
SoC_OSC1
J12
3
4
SIO2_CONFIG5
SIO3_CONFIG5
TxD
RxD
RF3
1
3
5
7
9
1
2
J73 - SPI AARDVAR HEADER
J73+J74 - SPI STROM HEADER
R139
0R
3V3
SIO1_CONFIG5
SIO0_CONFIG5
B
J20
HEADER 16X2
ID_SELECT_RB0
ID_SELECT_RB1
ID_SELECT_RB2
ID_SELECT_RB3
ID_SELECT_RB4
ID_SELECT_RB5
ID_SELECT_RB8
ID_SELECT_RB9
ID_SELECT_RB10
ID_SELECT_RB11
ID_SELECT_RB12
ID_SELECT_RB13
ID_SELECT_RC1
ID_SELECT_RC2
ID_SELECT_RC3
ID_SELECT_RC4
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
3V3
1K
MCLR
J21
A
C74
J22
GND1
GND2
0.1uF
C72
C73
0.1uF
0.1uF
C70
C71
0.1uF
0.1uF
C68
C69
0.1uF
SYS_RESETN
0.1uF
0.1uF
C75
SW Position 1-2 & 4-5 = PIM ON
SW Position 2-3 & 5-6 = PIC ON
C67
DNP
sw_pb_2P
0.1uF
DS50002333C-page 45
R89
A
SIG
GND3
GND4
2
3
DNP
1 FIFOSEL_LATCH0
4
5
GND1
GND2
TP10
SIG
WHITE
GND3
GND4
2
3
1
PME_LATCH1
Chennai
India
TP11
WHITE
4
5
SMA for SYNC0 & SYNC1
Decap for U3
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
*(2-3)
2
1
GPMC_A0_ALE
JS102011CQN
J20 - Default OPEN; Used as probing header.
Short when EtherCAT ID need to be used.
Also respective 10K pullup resister
need to be assembled
3V3
WR_ENB_CONFIG3
SW24
RD14
RD15
RA1
ID_SELECT_RB12
ID_SELECT_RB13
GPMC_A1_ALEHI
GPMC_A0_ALE
PGC2
PGD2
DBG ICSP Header
RESET
10uF
SCK_CONFIG5
SCS#_CONFIG5
ID_SELECT_RB8
ID_SELECT_RB9
ID_SELECT_RB10
ID_SELECT_RB11
PGD2
PGC2
R87
0R
R88
4.7K
C62
RD_RDWR_CONFIG3
PMWR
4
3
2
B
JUTLAND
Page:
Board
Name:
ON-Board-PIC32MX
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
9
of
D
12
Evaluation Board Schematics
MCLR
DNP
0.1uF
PIC32MX775F256L
VSS4
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
INT0
EMDC
PMCS2
SS1/IC2/RD9
EMDIO
AETXEN
AETXCLK
VSS3
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD4
TDO/RA5
TDI/RA4
SDA2
SCL2
D+/RG2
D-/RG3
VUSB
VBUS
SCL3/SDO3/U1TX/RF8
SDA3/SDI3/U1RX/RF2
USBID/RF3
3V3
J13
1
2
3
4
5
6
C61
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RA9
RA10
Assemble R143,R144 & R152
if EtherCAT ID select is required.
Temp.Sener, ADC & DAC functions
will not work when
EtherCAT ID select is used
External
Power
Option
D
PMRD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AERXERR
VDD
PMD5
PMD6
PMD7
RC1
RC2
RC3
RC4
PMA5
PMA4
AERXDV
MCLR
AERXCLK/AEREFCLK
VSS
VDD1
TMS/RA0
AERXD0
AERXD1
AN5/C1IN+/VBUSON/CN7/RB5
RB4
RB3
RB2
RB1
RB0
DAC_OUT_ADC2
ADC1 IN
TEMP IN
1-2* = External PWR
2-3 = 5V (Default)
HEADER 3X2
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
DNP
A4_CONFIG3
A3_CONFIG3
1
J19
LED_OUT
2
TP9
2
PWM2
R123
R124
R125
R126
R127
R128
R129
R130
R131
R132
R133
R134
R135
R136
R137
R138
RG6
A2_CONFIG3
B
1
TP8
3
J18
1
3
5
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
ID_SELECT_RC1
ID_SELECT_RC2
ID_SELECT_RC3
ID_SELECT_RC4
DNP R152
DNP R144
DNP R143
2
4
6
PWM1
Error LED
PMD4
PMD3
PMD2
RG13
RG12
TRD2/RG14
PMD1
PMD0
RA7
RA6
PMD8
PMD9
PMD10
PMD11
VDD5
VCAP/VDDCORE
PMD15
PMD14
PMRD
PMWR
PMD13
PMD12
OC4/RD3
OC3/RD2
OC2/RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RG15
ID_SELECT_RB5
ID_SELECT_RB4
ID_SELECT_RB3
ID_SELECT_RB2
ID_SELECT_RB1
ID_SELECT_RB0
1 A
C
D23
GRN
5V
Switch _IN
3
GPMC_A0_ALE
U7
PIC_MCLR
1K
1
PWM1 & PWM2 Signal for Motor Control
PWM2
1
*(1-2)
*(1-2)
R140
VDDCORE
3V3
C
3
J16
2
RD3
RD2
TP6
WHITE
J17
2
PIC32MX Unused GPIOs with GND probing option
AD5_CONFIG3
AD6_CONFIG3
AD7_CONFIG3
2
TP7
WHITE
PMRD
PMWR
4
8
12
16
20
24
28
32
36
40
RD11
RD14
RA5
RD9
RF3
RA10
RA0
RG15
RG13
RA6
3
RST_GPIO
AD1_CONFIG3
AD0_CONFIG3
3
7
11
15
19
23
27
31
35
39
RD15
RG2
RG3
RA4
RD8
RA9
RA1
RG6
RG12
RA7
HEADER 10x4
J15D
RA7
RA6
2
6
10
14
18
22
26
30
34
38
HEADER 10x4
J15C
RG13
RG12
1
5
9
13
17
21
25
29
33
37
D
4
HEADER 10x4
J15B
AD4_CONFIG3
AD3_CONFIG3
AD2_CONFIG3
5
HEADER 10x4
J15A
PGEC2/AN6/RB6
PGED2/AN7/RB7
AERXD2
AERXD3
AVDD
AVSS
RB8
RB9
RB10
AETXERR
VSS1
VDD2
TCK/RA1
SCK4
SS4
AECRS
MII2_COL
PMA1/AETXD3/PMALH
PMALL/PMA0/AETXD2
VSS2
VDD3
AETXD0
AETXD1
SDI4
SDO4
2015-2016 Microchip Technology Inc.
FIGURE B-7:
EVB-LAN9252-HBI+ SCHEMATIC GPIOS
5
4
SW28
GPIO1_CONFIG5
GPIO2_CONFIG5
GPIO3_CONFIG5
GPIO4_CONFIG5
GPIO5_CONFIG5
C
GPIO6_CONFIG5
GPIO7_CONFIG5
GPI0
3
GPO0
1
1
JS102011CQN
2
SW29
GPI1
1
3
GPO1
JS102011CQN
2
SW30
GPI2
1
3
GPO2
Digital INPUTS
3V3
JS102011CQN
2
SW31
GPI3
1
3
GPO3
JS102011CQN
2
SW32
GPI4
1
3
GPO4
JS102011CQN
2
SW33
GPI5
1
3
GPO5
JS102011CQN
2
SW35
GPI6
1
3
GPO6
D
Input = one (Default);
Input = Zero (change the Switch position)
R90
R91
R92
R93
R94
R95
R96
R97
D
2
2
10K
10K
10K
10K
10K
10K
10K
10K
GPIO0_CONFIG5
3
SW34
1
2
3
4
5
6
7
8
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
Digital OUTUTS
16
15
14
13
12
11
10
9
GPO0
GPO1
GPO4
GPO5
GPO6
GPO7
GPIO8_CONFIG5
JS102011CQN
2
SW37
GPI8
1
3
GPO8
GPO8
JS102011CQN
2
SW38
GPI9
1
3
GPO9
R98
R99
R100
R101
R102
R103
R104
R105
JS102011CQN
2
SW39
GPI10
1
3
GPO10
10K
10K
10K
10K
10K
10K
10K
10K
GPIO10_CONFIG5
B
GPIO11_CONFIG5
GPIO12_CONFIG5
2015-2016 Microchip Technology Inc.
GPIO13_CONFIG5
GPIO14_CONFIG5
GPIO15_CONFIG5
A
JS102011CQN
2
SW41
GPI11
1
3
GPO11
JS102011CQN
2
SW42
GPI12
1
3
GPO12
D7 1
D8 1
1K
D9 1
1K
R110
1K
R111
1K
R112
1K
R113
1K
D10 1
D11 1
D12 1
D13 1
D14 1
3V3
GPO9
GPIO9_CONFIG5
1K
R109
GPO3
SW DIP-8
1K
R107
R108
GPO2
JS102011CQN
2
SW36
GPI7
1
3
GPO7
R106
1
2
3
4
5
6
7
8
GPO12
GPO13
16
15
14
13
12
11
10
9
R115
1K
R117
GPO11
GPI8
GPI9
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
1K
R116
GPO10
SW40
R114
D17 1
1K
1K
R119
1K
R121
GPO15
D16 1
1K
R118
R120
GPO14
D15 1
D18 1
D19 1
D20 1
1K
D21 1
1K
D22 1
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
2
2
2
C
2
2
2
2
2
2
2
2
2
2
2
B
2
2
SW DIP-8
JS102011CQN
2
SW43
GPI13
1
3
GPO13
JS102011CQN
2
SW44
GPI14
1
3
GPO14
JS102011CQN
2
SW45
GPI15
1
3
GPO15
A
JS102011CQN
Chennai
India
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
GPIOs
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
10
of
D
12
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 46
FIGURE B-8:
EVB-LAN9252-HBI+ SCHEMATIC UART, ADC, &DAC
5
4
3
2
1
3V3
3V3
1
POT (Analog Input)
POT1
3352T-1-103LF
CCW 1
SW50
1
470R 1%
WIPER
R141
J27
2
D
ADC1 IN
Switch _IN
SW for Output
LED_OUT
LED for Input
sw_pb_2P
Default Short
D24
3
CW
2
R146
10K
1/10W
1%
2
D
2
A 1
C
1K
R145
GRN
DAC (Analog output)
C
3V3
0.1uF
3
VSS
TEMP IN
R153
10K
1/10W
1%
MCP4726
3
2
1
TC1047A
sot23-3-center3
VDD
VSS
VOUT
SDA
SCL
VREFF
U10
4
5
6
R154
10K
1/10W
1%
VREF
C87 +
10uF
16V
DNP
DNP
0.1uF C84
DAC_OUT
1
C82 +
10uF
16V
1
2
1/10W
1%
2
VOUT
1
R142
100E
2
2
VDD
C81
1
0.1uF C83
Temp sensor
U9
3V3
3V3
DNP
0.1uF C88
C
I2C_SDA_DAC_CTL
I2C_SCL_DAC_CTL
DNP
J26
2
3V3
1
Default Open
J26 Pin 2 = External Vref
Short J26 1-2 for Vfer = 3V3
C87 & C88 = Default DNP
Assemble only when Vref is used
B
B
3V3
C2+
C2TIA/EIA-232
GND
9
10
11
12
TxD
RxD
ROUT2
DIN2
DIN1
ROUT1
RIN2
DOUT2
DOUT1
RIN1
15
8
7
14
13
C80
TxD_232
TxD_232
RxD_232
RxD_232
RS-232
A
J14
TxD
RxD
0.1uF
VCC
VS+
VS-
C78
C1+
C1-
RS-232 I/F
16
2
6
0.1uF
2015-2016 Microchip Technology Inc.
C77 4
0.1uF 5
3V3
0.1uF C79
U8
C76 1
0.1uF 3
CONNECTOR DB9-M
6.7
1
6
2
7
3
8
11
4
10
9
5
1
2
3
4
5
6
DAC_OUT
1
J25
2
DAC_OUT_ADC2
Default Open
Short only when DAC need to be connect to onboard MX.
HRD 6pin
PICkit™ SERIALANALYZER
A
Chennai
India
J24
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
UART, ADC & DAC
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
11
of
D
12
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 47
FIGURE B-9:
EVB-LAN9252-HBI+ SCHEMATIC PIM
3
PIM_DIG_RC1
PIM_DIG_RC2
PIM_DIG_RC3
PIM_DIG_RC4
PIM_PIN10
PIM_PIN11
PIM_PIN12
PIM_MCLR
PIM_PIN14
FIFOSEL_LATCH0
PME_LATCH1
AN5_RB5
AN4_RB4
AN3_RB3
AN1_RB1
AN0_RB0
DNP
10uF C86
1
IRQ_PIM32MZ
1 0R
IRQ_PIM24
3
R149 DNP
2
IRQ
D
RD_RDWR_CONFIG3
WR_ENB_CONFIG3
SQI_SCK
SQI_D1
C
AD5_CONFIG3
AD6_CONFIG3
AD7_CONFIG3
63,
64,
+%,
VDDCORE_PIM
3V3
RD3
RD2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIM1
DNP
2
0.1uF C85 DNP
D
RST_GPIO
AD1_CONFIG3
AD0_CONFIG3
SIO3_CONFIG5
4
AD4_CONFIG3
AD3_CONFIG3
AD2_CONFIG3
SIO2_CONFIG5
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PIM CONN
SoC_SOSCO
SoC_SOSCI
SQI_D0
C
CS_CONFIG3
SQI_CS
J23 DNP
HEADER 14X2
IRQ_PIM24
PIM_DIG_RC1
PIM_DIG_RC2
PIM_DIG_RC3
PIM_DIG_RC4
PIM_RX
PIM_TX
AN5_RB5
AN4_RB4
AN3_RB3
AN1_RB1
AN0_RB0
AN2_RB11
AN9_RB9
AN8_RB8
SoC_OSC2
SoC_OSC1
PIM_RX
PIM_TX
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
U6RX=RPF2
U6TX=RPD1
PIM unused GPIOs with GND porbing option
PIM TXD & RXD can't be used in HBI mode.
In other modes, TXD & RXD can be
extrnally connected to UART
B
IRQ_PIM32MZ
AN2_RB11
2015-2016 Microchip Technology Inc.
AN8_RB8
AN9_RB9
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
B
PGC2
PGD2
A
PIM_PIN10
PIM_PIN11
PIM_PIN12
PIM_PIN14
RN1
4
3
2
1
0E
RN2
1
2
3
4
0E
GPMC_A0_ALE
GPMC_A1_ALEHI
5
6
7
8
8
7
6
5
A4_CONFIG3
A3_CONFIG3
A2_CONFIG3
PIM_SPI2_SCK
PIM_SPI2_SDI
PIM_SPI2_SDO
PIM_SPI2_CS
SQI_SCK
SQI_D1
SQI_D0
SQI_CS
SPI_SCK
SPI_SO
SPI_SI
SPI_CS
RN3
1
2
3
4
0E
8
7
6
5
4
3
2
1
RN4
5
6
7
8
A
SCK_CONFIG5
SIO1_CONFIG5
SIO0_CONFIG5
SCS#_CONFIG5
PIM
RN1
RN2
RN3
RN4
HBI
YES
DNP
DNP
DNP
SPI
DNP
YES
DNP
YES
SQI
DNP
DNP
YES
DNP
Chennai
India
0E
Part Number:
UNG_8043
Size:
Project
Name:
Date:
5
4
3
2
B
JUTLAND
Page:
Board
Name:
PIM
Rev
EVB-LAN9252-HBI
Sheet
Wednesday, February 17, 2016
1
12
of
D
12
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 48
FIGURE B-10:
EVB-LAN9252-HBI+
ETHERCAT® EVALUATION BOARD
USER’S GUIDE
Appendix C. Bill of Materials (BOM)
C.1
INTRODUCTION
This appendix includes the EVB-LAN9252-HBI+ Evaluation Board Bill of Materials (BOM).
2015-2016 Microchip Technology Inc.
DS50002333C-page 49
Reference
Part
PCB Footprint
DNP
Vender
Vender P/N
2
2
C2,C4
10uF
CAP0805
No
Murata
GRM21BR61E106KA73L
3
34
C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17,C18,C21,
C22,C24,C25,C58,C61,C67,C68,C69,C70,C71,C72,C73,
C74,C75,C76,C77,C78,C79,C80,C81,C83
0.1uF
CAP0603
No
Murata
GRM188R71E104KA01D
5
1
C19
1uF
CAP0603
No
Murata
GRM188R61C105KA93D
6
1
C20
470pF
CAP0603
No
Murata
GRM188R71H471KA01D
7
2
C26,C27
18pF
CAP0603
No
Murata
GRM1885C1H180JA01D
2015-2016 Microchip Technology Inc.
9
2
C32,C37
0.022uF
CAP0603
No
Kemet
C0603C223K5RACTU
12
1
C62
10uF
CAP0603
No
TDK
C1608X5R0J106K080AB
13
2
C63,C64
11pF
CAP0603
No
Murata
GRM1885C1H110JA01D
14
2
C65,C66
20pF
CAP0603
No
Murata
GRM1885C1H200JA01D
15
1
C82
10uF
CAP_B_3528
No
AVX
TPSB106K016R0500
17
22
D1,D3,D4,D5,D7,D8,D9,D10,D11,D12,D13,D14,D15,
D16,D17,D18,D19,D20,D21,D22,D23,D24
GRN
LED0603
No
Wurth electronics
150 060 GS7 500 0
18
1
D2
Br_Red‐RA
LED0603
No
Wurth electronics
150 060 RS7 500 0
19
1
D6
DIODE
SOD123
No
Micro Commercial Co
1N4148W‐TP
20
5
FB1,FB2,FB3,FB4,FB5
2A/0.05DCR
RES0603
No
Murata
BLM18EG221SN1D
21
1
J1
SKT_PWR_2R0mm_4A_THRU_RA
th_conn_pwrjack_dc‐210_rt
No
Cui Stack
PJ‐002AH
23
9
J4,J5,J6,J7,J8,J9,J16,J17,J19
HDR_1x3
TH_CONN_1X3P
No
FCI
68000‐103HLF
24
3
J10,J25,J27
CONN_2P
th_conn_1x2p
No
FCI
68000‐102HLF
25
1
J11
HEADER 5X2
TH_CONN_2X5P
No
FCI
67997‐210HLF
26
1
J12
HEADER 2X2
TH_CONN_2X2P
No
FCI
67997‐202HLF
27
1
J13
DBG ICSP Header
TH_CONN_1x6P
No
FCI
68000‐106HLF
28
1
J14
HRD 6pin
TH_CONN_1x6P
No
FCI
68000‐106HLF
30
1
J18
HEADER 3X2
TH_CONN_2X3P
No
FCI
67997‐206HLF
31
1
J20
HEADER 16X2
TH_CONN_2X16P
No
FCI
67997‐232HLF
32
2
J21,J22
CONN_5P
TH_CONN_SMA‐J‐P‐H‐ST‐TH1
No
TE
5‐1814832‐1
34
1
J24
CONNECTOR DB9‐M
th_conn_db9_m_rt
No
TE/AMP
5747840‐4
38
1
POT1
3352T‐1‐103LF
TH_POT_3352T
No
Bourns Inc.
3352T‐1‐103LF
40
1
Q1
NDS355AN_NMOS
sot23‐NDS
No
Fairchild
NDS355AN
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 50
Item Qty
2015-2016 Microchip Technology Inc.
41
7
R1,R15,R29,R61,R62,R87,R122
0R
RES0603
No
Panasonic
ERJ‐3GEY0R00V
42
24
R2,R8,R72,R73,R74,R89,R106,R107,R108,R109,R110,
R111,R112,R113,R114,R115,R116,R117,R118,R119,
R120,R121,R140,R145
1K
RES0603
No
Panasonic
ERJ‐3GEYJ102V
43
1
R3
3.30K
RES0603
No
Yageo America
9C06031A3301FKHFT
44
2
R4,R141
470R
RES0603
No
BOURNS
CR0603‐FX‐4700ELF
45
1
R4A
33R
RES0603
No
BOURNS
CR0603‐FX‐33R0ELF
46
1
R5
4.75K
RES0603
No
Panasonic
ERJ‐3EKF4751V
47
26
R6,R69,R70,R71,R146,R153,R154,R76,R79,R80,R90,
R91,R92,R93,R94,R95,R96,R97,R98,R99,R100,R101,
R102,R103,R104,R105
10.0K
RES0603
No
Panasonic
ERJ‐3EKF1002V
48
2
R7,R142
100E
RES0603
No
Panasonic
ERJ‐3EKF1000V
49
1
R9
2.2K
RES0603
No
Panasonic
ERJ‐3GEYJ222V
50
1
R10
12.1K
RES0603
No
Rohm
CR03ERTF1212
51
8
R11,R12,R13,R14,R25,R26,R27,R28
49.9R
RES0603
No
Yageo America
9C06031A49R9FKHFT
53
8
R17,R19,R21,R23,R31,R33,R35,R37
0R
RES0402
No
Panasonic
ERJ‐2GE0R00X
54
2
R24,R38
0R
RES1210
Vishay
CRCW12100000Z0EA
60
5
R63,R64,R65,R66,R88
4.7K
RES0603
No
Panasonic
ERJ‐3EKF4701V
61
2
R67,R68
2K
RES0603
No
Panasonic
ERJ‐3GEYJ202V
68
1
SW1
SW‐SPDT‐SLIDE
sw_ck_1101m2s3cqe2
No
C&K
1101M2S3CQE2
69
3
SW2,SW27,SW50
sw_pb_2P
sw_pb_2P
No
Panasonic
EVQ‐PJU04K or EVQ‐5PN04K
70
1
SW3
SW DIP‐4/SM
TH_SW_DIP4
No
Wurth electronics
418117270904
450301014042
8
SW5,SW6,SW7,SW8,SW9,SW10,SW24,SW25
JS102011CQN
TH_SW_SPST_3P_10x2p5
No
72A
16
SW5,SW6,SW7,SW8,SW9,SW10,SW24,SW25,SW28,
SW29,SW30,SW31,SW32,SW33,SW35,SW36,SW37,
SW38,SW39,SW41,SW42,SW43,SW44,SW45
HDR_1x3
TH_SW_SPST_3P_10x2p5
No
FCI
68000‐103HLF
73
12
SW11,SW12,SW13,SW14,SW15,SW16,SW17,SW18,
SW19,SW20,SW21,SW26
JS202011CQN
TH_SW_DPDT_6P
No
C&K
JS202011CQN
74
2
SW34,SW40
SW DIP‐8
SW_DIP_SMT_8P‐ADE08S04
No
TE
1‐1825058‐9
75
1
TP1
RED
TH_TP_60D40
No
Keystone
5000
76
1
TP2
ORANGE
TH_TP_60D40
No
Keystone
5003
77
3
TP3,TP4,TP9
BLACK
TH_TP_60D40
No
Keystone
5001
80
2
T1,T2
Pulse ‐ J0011D01BNL
th_conn_pulse_rj45_j0026
No
Pulse Electronics
J0011D01BNL
Bill of Materials (BOM)
DS50002333C-page 51
72
Wurth electronics
1
U1
3_Amp
TH_DC‐DC_VERT_5PIN_P67
82
1
83
1
84
No
Murata
OKR‐T/3‐W12‐C
U2
TPS3125
SOT23_5
No
TI
TPS3125L30DBVR
U3
74LVC1G14
SOT23_5
No
TI
SN74LVC1G14DBVR
1
U4
LAN9252
IC_QFN64
No
Microchip
LAN9252
85
1
U5
24FC512
IC_DIP8_300
No
Microchip
24FC512‐I/P
87
1
U7
PIC32MX775F256L
IC_TQFP100_12x12x1‐0p4mm
No
Microchip
PIC32MX795F512L‐80I/PT
88
1
U8
TRS3232_SO16
IC_SO16
No
TI
TRS3232IDR
89
1
U9
TC1047A
sot23‐3
No
Microchip
TC1047AVNBTR
90
1
U10
MCP4726
SOT23_6
No
Microchip
MCP4726A0T‐E/CH
No Cardinal Components Inc. CSM1Z‐A5B2C5‐40‐25.0D18‐F
91
1
Y1
25.000MHz
XTAL_HCM49
92
1
Y2
32Khz
th_xtal_ecs‐31x‐13‐32khz
No
ECS INC
ECS‐.320‐12.5‐13X
93
1
Y3
8 Mhz
th_hc49us_2p
No
Citizen Finetech
HC‐49/U‐S8000000ABJB
DNP Components
2015-2016 Microchip Technology Inc.
1
1
C1
4.7uF
CAP0603
DNP
4
4
C7,C9,C12,C23
1.0uF
CAP0603
DNP
8
8
C28,C29,C30,C31,C33,C34,C35,C36
10pF
CAP0402
DNP
10
19
C38,C39,C40,C41,C42,C43,C44,C45,C47,C49,C51,
C53,C55,C57,C59,C60,C84,C85,C88
0.1uF
CAP0603
DNP
11
7
C46,C48,C50,C52,C54,C56,C87
10uF
CAP_B_3528
DNP
16
1
C86
10uF
CAP0603
DNP
22
2
J2,J3
FTLF1217P2
CONN_FX_SFP_FTLF1217P2
DNP
29
1
J15
HEADER 10x4
TH_CONN_4X10P
DNP
33
1
J23
HEADER 14X2
TH_CONN_2x14P
DNP
35
1
J26
CONN_2P
th_conn_1x2p
DNP
36
4
L1,L2,L3,L4
1uH
L0805
DNP
37
1
PIM1
PIM CONN
TH_CONN_PIM100
DNP
39
2
P1,P2
HEADER 23x2
TH_CONN_2X23P
DNP
52
8
R16,R18,R20,R22,R30,R32,R34,R36
0R
RES0402
DNP
55
4
R39,R40,R43,R44
82R
RES0603
DNP
56
4
R41,R42,R45,R46
49.9R
RES0603
DNP
57
2
R47,R48
100E
RES0603
DNP
EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide
DS50002333C-page 52
81
2015-2016 Microchip Technology Inc.
58
4
R49,R50,R51,R52
130R
RES0603
DNP
59
12
R53,R54,R55,R56,R57,R58,R59,R60,R81,R82,R84,R85
4.7K
RES0603
DNP
62
19
R75,R77,R78,R123,R124,R125,R126,R127,R128,R129,R130,
R131,R132,R133,R134,R135,R136,R137,R138
10K
RES0603
DNP
64
2
R83,R86
2K
RES0603
DNP
65
4
R139,R143,R144,R152
0R
RES0603
DNP
67
1
R149
0R
RES0603‐3
DNP
71
1
SW4
SW DIP‐4/SM
TH_SW_DIP4
DNP
78
1
TP5
ORANGE
TH_TP_60D40
DNP
79
5
TP6,TP7,TP8,TP10,TP11
WHITE
TH_TP_60D40
DNP
86
1
U6
24FC512
IC_DIP8_300
DNP
Bill of Materials (BOM)
DS50002333C-page 53
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
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Web Address:
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Asia Pacific Office
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Tel: 86-592-2388138
Fax: 86-592-2388130
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Fax: 43-7242-2244-393
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Tel: 86-756-3210040
Fax: 86-756-3210049
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Fax: 45-4485-2829
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
07/14/15
DS50002333C-page 54
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