G704-E1

AvnetCore: Datasheet G704-E1 Framer MC-ACT-ETHCTRL reset_n Version 1.0, July 2006 Intended Use: tx_en tx_er txd col crs tx_clk rx_en Reset — ISDN Terminal Equipment — E2 Interface (multi G704 on chip) — E1-ATM Interface AHB Bus Master Lite AHB Master Bus MAC Control Layer AHB Master TX FIFO MAC RX FIFO rxd rx_clk rx_dv rx_er mdc md_drv_n md_dout md_din Features: — G704 framing de-framing on E1 carriers — Basic & multi frame alignment — Alarm bit processing — Customizable error counters — Selectable conditions for loss of sync — CRC4 error checking and monitoring — Fully synchronous AHB Slave Bus AHB Slave Serial Management Interface Config/ Control int_rx_frame int_bus_error int_mac_paused int_phy_status_changed Interrupts int_tx_frame Ext Address Check MII rx_ext_addr_check_match dest_addr_avbl src_addr_avbl len_type_avbl rx_shift_reg load_ebl sda_in Serial I/F Targeted Devices: — SX-A Family — Axcelerator® Family — ProASICPLUS® Family Block Diagram Core Deliverables: — Netlist Version > Netlist compatible with the Actel Designer place and route tool — RTL Version > VHDL Source Code > Test Bench — All > User Guide The MC-ACT-G704E1 Framer core is designed to handle synchronous frame structures (Recommendation G.704) running on an E1 carrier. Transmitter and receiver part are two completely independent blocks both capable of handling basic and multi frames. Both perform functions such as overhead bit insertion / detection, CRC4 computation and check. A very flexible synchronization unit (Recommendation G.706) synchronizes automatically or by means of an external frame sync signal. The frame builder unit can be configured which of the overhead bits are to be inserted or not. Avnet Memec cores are designed with the philosophy that no global elements should be embedded within the core itself. Global elements include any of the following components: STARTUP, STARTBUF, BSCAN, READBACK, Global Buffers, Fast Output Primitives, IOB Elements, Clock Delay Components, and any of the Oscillator Macros. Avnet Memec cores contain resources present in only the sequential and combinatorial array. This is done to allow flexibility in using the cores with other logic. For instance, if a global clock buffer is embedded within the core, but some external logic also requires that same clock, then an additional global buffer would have to be used. In any instance, where one of our cores generates a clock, that signal is brought out of the core, run through a global buffer, and then brought back into the core. This philosophy allows external logic to use that clock without using another global buffer. A result of this philosophy is that the cores are not self-contained. External logic must be connected to the core in order to complete it. Synthesis and Simulation Support: — Synthesis: Synplicity® — Simulation: ModelSim® — Other tools supported upon request Verification: — Test Bench Functional Description TRANSMITTER The transmitter part consists of the multi frame overhead handler and the frame builder itself. Multi Frame Overhead Handler This block is responsible for providing the overhead bits according to the current frame type. These bits are then forwarded to the frame builder unit that inserts them into the outgoing data stream. Frame Builder The frame builder performs all the tasks necessary to output a valid frame that complies with the E1 carrier system. Basic Frame Synchronizer Generator This block synchronizes the incoming data and provides a basic frame reference signal that identifies every bit within a basic frame. Multi Frame Generator The multi frame generator builds a multi frame reference signal based on the basic frame reference and provides the associated interrupts. TS0 Bit Insertion This unit automatically inserts all the special bits on the fly into time slot 0. It uses the frame reference signal to insert the corresponding bits. It inserts the basic frame alignment, the CRC4 multi frame alignment signal, the computed CRC4 value plus the configured special bits. CRC4 Calculation This block computes the CRC4 value on the outgoing data stream and feeds it back to the TS0 bit insertion block. RECEIVER The receiver part comprises the synchronizer block and the analyzer block. Snychronizer The synchronizer samples the incoming data frame and generates the corresponding frame reference signal and the necessary interrupts. Basic Frame Aligner This block synchronizes the incoming data and provides a basic frame reference signal that identifies every bit within a basic frame. Multi Frame Aligner The multi frame aligner detects multi frame structures and builds a multi frame reference signal based on the basic frame reference and provides the associated interrupts. CRC4 Checker This unit computes the CRC4 on the incoming frame and compares it with the received CRC bits and provides the corresponding status signals. Analyzer This unit uses the frame reference signal to analyze the incoming frame. Alarm Detector This unit samples the alarm bits of the incoming frame. It registers them and outputs an alarm history. Plus it marks the reception of the alarm indication signal. Monitor Counter The monitor counter holds error counters that keep track on the CRC4, FAS and E-bit errors that have been detected on the incoming frames. TS0 Signal Capture This block samples the bits in time slot 0 and stores them into a register bank for further processing. The register bank can hold the TS0 bits of 8 consecutive frames within a multi frame structure. AISLOS Detector This unit detects the alarm indication signal (AIS) and the 2Mbit loss condition. Family SX-A ProASICPLUS Axcelerator Device COMB SX32A-3 APA150-STD AX500-3 760 (42%) n/a 695 (13%) Utilization SEQ 510 (48%) n/a 507 (19%) Total 1270 (44%) 2212 (36%) 1202 (15%) Performance 77 MHz 42 MHz 79 MHz Verification and Compliance Complete functional and timing simulation has been performed on the G704-E1 Framer using ModelSim 5.5d. This core has also been used successfully in customer designs. Signal Descriptions The following signal descriptions define the IO signals. Signal ClkSys resn CfgFSync.SyncMode[1:0] Direction Input Input Input Description System clock: This is the only clock source for the whole G704-E1 core Asynchronous System Reset: active low Configuration of Frame Synchronizer: “00”: transparent (no FSync generated) “01”: free run (generate dummy FSync) “10”: use external FSync “11”: fully automatic sync (G.706) User controlled resync: When toggled form ‘0’ to ‘1’, a resync is initialized Automatic resync after loss of sync: ‘1’: Automatic resync ON ( ‘0’: OFF ) ‘0’: Improved BasicFrame alignment disabled ‘1’: Use improved BasicFrame alignment procedure as in $4.1.1 of G.704/Note 1 (check FA bit 2 of nFAS frames) ‘0’: MultiFrame alignment search disabled (only Basic-Frame search) ‘1’: MultiFrame alignment search enabled Input Input ‘0’: use parallel BFA search (G.706) ‘1’: reuse primary BFA search (PTT simplified search path) ‘0’: MultiFrame alignment loss checking process disabled ‘1’: MultiFrame alignment checking process enabled (if 3 consecutive MFA not found while MFSyncState = InSync, then MFSyncState