GIGABIT_ETHERNET_SFP

EqcoLogic NV Engineering Information Open your Eyes™ EQCO850SC-HS and EQCO875SC-HS Single Coax Transceiver for LVDS and Gigabit Ethernet applications 1.1 Features       1.2 Combined transmitter and receiver with an integrated equalizer to form a full-duplex bidirectional connection over a single 50Ω coax cable (EQCO850SC-HS) or 75Ω coax cable (EQCO875SC-HS)1 Internal LVDS termination resistors for low external discrete count Allows power distribution over the coax, on top of the data signals Single 3.3 V supply 16-pin, 0.65 mm pin pitch, 4 mm QFN package Pb-free and RoHS compliant Applications This solution is useful and economical for many markets and applications, including the following:   1.3 Camera networks - Home Security, Surveillance, industrial/inspection, medical cameras Coax Cable-Distribution infrastructure Typical Equalization Performance Bit Rate 125Mbps 250Mbps 500Mpbs 1Gbps EQCO850SC-HS range using RG174 ( 2.8 mm) RTK ( 2.8 mm) RG58 ( 5 mm) 40 m 30 m 25 m 15 m 70 m 60 m 40 m 25 m 70 m 70 m 50 m 30 m Table 1: Typical Equalization Performance For other cable types, the length that can be reached in full-duplex may have maximally -12dB insertion loss at 625 MHz, for a bit rate of 1.25 Gbps. Equalizer performance works up to much higher levels in half-duplex. For lower bit-rates slightly longer cable lengths can be achieved. 1 EQCO850SC-HS works for 50 coax and the EQCO875SC-HS works for 75 coax. Everything is the same except the part number, the used coax and the characteristic impedance of transmission lines and connectors between the chip and the edge of the boards. See also section 5.1 about the typical application circuit. DS-EQCO850SC-HS-2v0-2014-01-28 Page 1 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 2 Functional Description 2.1 Overview The EQCO850SC-HS single coax transceiver is designed to simultaneously transmit and receive signals on a single 50 Ω coax cable. A sister product, the EQCO875SC-HS can achieve similar performance when used in 75 Ω coaxial systems. The EQCO850SC-HS (EQCO875SC-HS) is ideally suited for simplex and duplex LVDS connections over 50 Ω (75 Ω) coax cable between 125 Mbps and 1.25 Gbps. For correct operation the signals must be NRZ (non-return-to-zero) encoded, DC balanced with a maximum run length of 10 bits. Excellent EMI/RFI shielding of coax cable allows for good EMI properties. The EQCO850SC-HS operates with all kinds of 50 Ω coax cable, including the cost effective 2.8 mm diameter RTK cable (e.g. Leoni Dakar 302), which is the type of coax cable used for radio and navigation antennas in automotive. This cable fits well with the Standardized (DIN and USCAR), high-performance, cost-effective RF connectors - SAE/USCAR-18 “FAKRA/SMB RF Connector”. The EQCO875SC-HS is typically useful in situations where legacy 75 Ω cables are present. Fig. 1 illustrates a typical LVDS Coaxial connection. It can be used for Gigabit Ethernet connections over a single coax cable. Up to 12dB loss DC Balanced LVDS TXVR EQCO850SC 50Ω Coax EQCO850SC (including inline connectors as reqd) DC Balanced LVDS TXVR Figure 1: Typical LVDS Link using EQCO850SC-HS DS-EQCO850SC-HS-2v0-2014-01-28 Page 2 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 2.2 Package and Pinout CCUT DVCC OPT0 DGND 16 15 14 13 AVCC 1 12 SDOp SDIO 2 11 SDOn REF 3 10 SDIp AGND 4 9 SDIn ECQO 850SC.3-HS GND TAB 5 6 7 8 OPT1 CLK SI CD* Figure 2: EQCO850SC-HS (EQCO875SC-HS ) Pin Layout (viewed from top)2 2.3 Pin Descriptions Pin Number Pin Name Signal Type Description (TAB) GND Power Connect to ground of power supply 15 DVCC Power Connect to +3.3 V of power supply 13 DGND Power Connect to ground of power supply 1 AVCC Power 4 AGND Power 2 SDIO Bidirectional 3 REF Bidirectional 8 CD* 10, 9 SDIp/SDIn Output (open drain) Input Analog VCC Connect to +3.3 V of power supply via RF choke and capacitor to cable outer screen Analog GND Connect to cable outer screen Serial Input Output Connect to centre conductor of 50 Ω coax cable. Reference Connect through 50Ω resistor (or impedance matched to cable) to cable outer screen Leave unconnected. Use of this pin is not advised in practice. 12, 11 SDOp/SDOn Output 14, 5 OPT0, OPT1 Input 6, 7 CLK, SI Input Serial Input Positive/Negative Differential serial input. Connect to the LVDS output Serial Output Positive/Negative Differential serial output. Connect to the LVDS input Connect Opt0 and Opt1 both to DVCC (3.3V) for correct mode selection. Used for Production test, Connect to DGND 16 CCUT Analog Not used in LVDS applications. Connect to pin 15 DVCC Table 1: Device Pin List 2 Devices named EQCO850SC.2 can be used for all applications contained in this data-sheet. They are the same in all aspects. DS-EQCO850SC-HS-2v0-2014-01-28 Page 3 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ EQCO850SC SDIp SDIn SDOp Input Pre-Driver Active Signal Splitter/Combiner Transmit wake-up Detection Equalizer Core SDIO REF RX Output Driver SDOn Figure 3: EQCO850SC-HS block diagram showing electrical connections 2.3.1 SDIp/SDIn SDIp/SDIn together form a differential input pair. The serial data received on these pins will be transmitted on SDIO. The Input Pre-Driver automatically corrects for variations in signal levels and different edge slew rates at these inputs before they go into the Active Splitter/Combiner for transmission over the coax. SDIp and SDIn inputs are differentially terminated by 100 Ω on chip. The center of the 100 Ω is connected to DGND with a 10 kΩ resistor for DC biasing. The inputs also have protection diodes to ground for ESD purposes. Always AC-couple these inputs to the outputs of the LVDS driver. A Transmit Wake-up detection circuit puts both the Input Pre-Driver and the Active Signal Splitter/Combiner into a low power mode when no signal is detected on the SDIp/SDIn signal pair (except in mode B, where transmit circuit is permanently ON). 2.3.2 SDIO/REF The signal on the SDIO pin is the sum of the incoming signal (i.e. the signal transmitted by the EQCO850SC-HS on the far end side of the coax) and the outgoing signal (i.e. the signal created based on SDIp/SDIn). The far end signal is extracted by subtraction of the near end signal and it is this voltage that the equalizer analyses and adaptively equalizes for level and frequency response based on the knowledge that the originating signal is DC balanced and Run length encoded before transmission. The REF signal carries a precise anti-phase current to the transmit current on SDIO. REF must be connected directly to AGND at the connector (see Figure ) via a resistor precisely matched to the impedance of the coaxial cable used. 2.3.3 SDOp/SDOn SDOp/SDOn together form a differential pair outputting the reconstructed far end transmit signal. The EQCO850SC-HS uses LVDS drivers with source matching for a 100 Ω transmission line. This LVDS signal can normally be connected (subject to input common mode requirements) directly to the RX signal pair of a standard LVDS receiver. 2.3.4 CLK, SI These pins are used for production test and/or reserved for future options. For normal operation connect them to DGND as indicated in Table 1. DS-EQCO850SC-HS-2v0-2014-01-28 Page 4 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 2.4 Circuit Operation 2.4.1 Pre-driver The Pre-driver removes any dependency on LVDS transmitter for the amplitude and rise time of the outgoing signal on SDIO. 2.4.2 Active signal splitter/combiner The active splitter/combiner [1] controls the amplitude and rise time of the outgoing coax signal and transmits it via a precise 50Ω output termination resistor. The output resistor when balanced with the coax characteristic impedance also forms part of a hybrid splitter circuit which subtracts the TX output from the signal on the SDIO output to give yield the far end TX signal. The return loss of the coax termination is a key factor in the performance of the line hybrid. 2.4.3 Equalizer Core Figure 5: Principal of Equalizer Operation The EQCO850SC-HS has an embedded high speed equalizer [2] in the receive path with unique characteristics:  Auto-adaptive The equalizer controls a multiple pole analog filter which compensates for attenuation of the cable, as illustrated in Figure 5. The filter frequency response needed to restore the signal is automatically determined by the device using a time-continuous feedback loop that measures the frequency components in the signal. Upon the detection of a valid signal, the control loop converges within a few microseconds.  Variable gain EQCO850SC-HSs are used in pairs; one at each end of the coax. The EQCO850SC-HS can be used with any LVDS driver with a differential transmit amplitude in the range of 300 mV to 800 mV; the transmit amplitude on the coax is regulated by the input pre-driver. The receiver equalizer has variable gain to compensate for attenuation through the coax. Example equalizer performance measurements can be found in Appendix 1. DS-EQCO850SC-HS-2v0-2014-01-28 Page 5 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 3 Electrical Specifications 3.1 Absolute Maximum Ratings Stresses beyond those listed under this section may cause permanent damage to the device. These are stress ratings only and are not tested. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Conditions Storage Temperature Ambient Temperature Operating Temperature Supply Voltage to Ground DC Input Voltage DC Voltage to Outputs Output current into Outputs Electro Static Discharge (ESD) HBM Electro Static Discharge (ESD) contact Latch-Up Current Min Power Applied Normal Operation (VCC=3.3 V+5%) Outputs Low JEDEC EIA/JESD-A114A IEC 61000-4-2 Typ Max -65 -55 -40 +150 +125 +85 -0.5 -0.5 -0.5 +4.0 +4.0 +4.0 90 Units o C C o C o >3.3 V V V mA kV >8 kV >200 mA(DC) Table 2: Absolute Maximum Ratings 3.2 Electrical Characteristics Parameter Description Min Typ Max Unit 3.135 3.3 3.465 V 47.5 62.5 75.5 mA 25 35 43 mA 800 mV Power supply VCC Is Isr Supply Voltage Supply Current, both transmitting and receiving 2 2 Supply Current when only receiving SDIp/SDIn Inputs (LVDS like) 2 Vi Input amplitude VSDIp,n Vturnon Minimal Vi to turn on transmit function Vcmin Common-mode input voltage (terminated to 3 DGND via 10 kΩ and with protection diodes) 2 Differential input termination Rinput 250 80 140 200 mV Note 4 0 Note 4 V 93 104 117 Ω 48 (72) 50 (75) 52 (78) Ω 46 (69) 51 (76) 55 (82) Ω SDIO connection to Coax Zcoax Coax Cable Characteristic Impedance 2 RSDIO Input impedance between SDIO and AGND Rloss Coax Return Loss as seen on SDIO pin Frequency range = 10 MHz-625 MHz Transmit Amplitude VTX DS-EQCO850SC-HS-2v0-2014-01-28 15 270 Page 6 of 13 dB 325 380 mV ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ Parameter Description trise_tx Rise/fall time 20% to 80% of Attmax Cable Attenuation Budget @ 625MHz (S800) 3 Minimum input for fully reconstructed output Min Typ Max 350 450 550 3 VTX 3 VRX min Unit ps 12 dB 40 mV SDOp/SDOn Outputs (LVDS compatible) 2 Vo Output amplitude VSDOp,n Vcmout Common-mode output voltage 300 350 400 mV 1.1 1.2 1.3 V -20 0 20 mV 92 102 115 Ω 150 240 350 ps 2 Vo_off Output amplitude VSDOp,n with equalizer OFF Routput Differential termination between SDOp and 2 SDOn Rise /fall time 20% to 80% of VSDOp,n trise_o 3 Table 3: Electrical Characteristics (see notes), EQCO850SC-HS and (EQCO875-HS) 1 Over full VCC range 2 Over full VCC range and full operating temperature range (-40 C to 85 C) Guaranteed by design 3 4 o o SDI Inputs are protected by silicon input diodes, clamping their maximum input voltage to + 0.6V 3.3 Jitter Performance Parameter Conditions Jitter peak to peak on SDO 1 m RG174 coax; over full Vcc,VTX, and Temp range; 125-1250Mbps ; pattern PRBS7 16 m RG174 coax; over full Vcc,VTX, and Temp range; 125-1250Mbps ; pattern PRBS7 Jitter peak to peak on SDO Min Typ Max Units 70 230 ps 170 300 ps Table 4: Jitter at SDO. DS-EQCO850SC-HS-2v0-2014-01-28 Page 7 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 4 Package Drawing A 16 pin Micro Lead frame Package (MLP) also known as Quad Flat No Lead (QFN) package is used. The package outline conforms to JEDEC MO-220. Dimensions in Figure 6 and Figure 7 are in millimeters. Pin 1 Top Mark 4.00+/-0.1 0.9 14 13 12 1 11 2 10 3 9 4 2.10 EQCO 850SC.3-HS YYWWNNN 16 15 7 6 0.60 0.65 Top View 5 0.3 Bottom View < 0.15 8 0.2 0.00-0.05 2.15 2.90 4.35 Figure 6: Package Drawings 0.30 0.65 Figure 7: Recommended PCB Footprint for both types of packages DS-EQCO850SC-HS-2v0-2014-01-28 Page 8 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 5 Application Information 5.1 Typical Application Circuit Figure illustrates a typical schematic implementation: 3V3 100Ω Differential traces Ferrite bead 0.1uF LVDS TX SDIp VCC SDIn AVCC 10nF 0.1uF 10nF 0.1uF Coax Connector SDIO GND LVDS RX 50Ω SDOp REF 10nF 1% SDOn AGND GND 50Ω traces GND GND Figure 8: Example Schematic Implementation for EQCO850SC-HS. For EQCO875SC-HS replace the two 50 references with two times 75. To improve isolation from noise on the board power plane and improve EMC immunity and emissions, it is recommended to power the transmit side of equalizer (AVCC) through a ferrite bead. A 0.1-μF decoupling capacitor should be placed as close as possible to the chip between the VCC pin and the GND pin. Ground vias should be placed as close as possible to the device GND pins to minimize inductance. In full duplex, the maximum length performance depends on the level of near-end cross-talk and far-end return-loss. Therefor it is recommended for full duplex operation to position the chip close to the used connector. Also one has to choose for either a 50- system or a 75- system. All the elements need then to have impedances according to that choice: the chips used on both sides, the impedances between the chip and the connector, the PCB connector itself (!), the connectors on the coax cable, and the coax. If one impendance is wrong (e.g. a 75- BNC connector in a 50- system) this impedance discontinuity will give a sligh or a strong reflection, limiting the performance of the full-duplex maximum cable reach. 5.2 PCB layout Because signals are strongly attenuated by a long cable, special attention must be paid on the PCB layout between the coaxial connector and the EQCO850SC-HS. The EQCO850SC-HS should be as close as is practical to the coaxial connector. The trace between the coaxial connector and the EQCO850SC-HS (EQCO875SC-HS) must be a 50-Ω (75-Ω) trace referenced to GND. To avoid noise pickup, other traces carrying digital signals or fast switching signals should be placed as far away as possible from this trace. The following diagram shows the layout of the critical section of the PCB, from the coax connector to the twin differential input pairs: DS-EQCO850SC-HS-2v0-2014-01-28 Page 9 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ Figure 10: Recommended Layout Figure 9: Circuit diagram (part) The ground layout on the EQCO850SC-HS is critical to the EMC and EMI performance of the circuit. The AGND connection should be made directly to the body of the connector as shown in Figure 9. It should not be connected directly to the GND tab of the chip. Similarly AVCC should be decoupled directly to the connector body (see position of C5). The termination resistor (R1 in Figure 9 and Figure 10) must have its ground connection at the connector body and the C7, the connection between R1 and the connector must be kept as short as possible. The impedance of all the traces must be well controlled, including on the connector itself. The SDIp/SDIn and SDOp/SDOn differential traces should be matched in length to minimize time of arrival skew. For traces longer than a few mm the impedance of the differential transmit and receive signals should be laid out as 100Ω differential traces and the termination to the PHY should be placed close to the PHY, not to the EQCO850SC-HS. EqcoLogic N.V. can design a PCB-layout that allows to reach maximum cable length for any combination of impedance system (50 or 75 ) and coax connector (SMA, BNC, DIN, SMB…) on request. DS-EQCO850SC-HS-2v0-2014-01-28 Page 10 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ 6 Document Control 6.1 Version History Version Date Author Comments 2v0 28 Jan 2014 M. Kuijk 1v0 30 Apr 2010 S. E. Ellwood/M. Kuijk Targeting datasheet for LVDS and Gigabit Ethernet applications. Merging 50 and 75 systems in one o o datasheet. Temperature limits set to -45 C … 85 C Based on EQCO800SC Generic Datasheet, adapted for LVDS. 6.2 Document References [1] [2] Patents & Patents Pending: EP2237419A1, US8164358B2, EP2237435B1 US8488685B2 Patents: EP2182688B1 & US7894515B2 6.3 Ordering Information Order Code Application EQCO850SC.2 EQCO875SC.2 EQCO850SC.HS EQCO875SC.HS 50 Coax 75 Coax 50 Coax 75 Coax Production Package Type End of Life End of Life In Qualification In Qualification 16 Pin, 4 mm QFN 16 Pin, 4 mm QFN 16 Pin, 4 mm QFN 16 Pin, 4 mm QFN Operating Range o o -45 C…+85 C o o -45 C…+85 C o o -45 C…+85 C o o -45 C…+85 C EQCO850SC.2 and EQCO850-HS consist of the same silicon and the same package. EQCO875SC.2 and EQCO875-HS consist of the same silicon and the same package. 6.4 Disclaimer: EQCOLOGIC MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. EqcoLogic reserves the right to make changes without further notice to the materials described herein. EqcoLogic does not assume any liability arising out of the application or use of any product or circuit described herein. EqcoLogic does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of EqcoLogic’s product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies EqcoLogic against all charges. EqcoLogic NV c/0 ETRO/VUB Pleinlaan 2, 1050 Brussels DS-EQCO850SC-HS-2v0-2014-01-28 Page 11 of 13 Phone: +32 2 629 1301 Email: techsupport@eqcologic.com www: www.eqcologic.com ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ Appendix 1: Typical Operating Characteristics All measurements at VCC = 3.3 V, Temp = +25ºC, data pattern = PRBS9, 630 mV PHY Transmit amplitude Fig. 11. Typical eye at SDOp with a 1 m Coax type RG174. Fig. 12. Typical eye at SDIO output through 1 m COAX cable. DS-EQCO850SC-HS-2v0-2014-01-28 Page 12 of 13 ©2014 Eqcologic NV EqcoLogic NV Engineering Information Open your Eyes™ Half duplex Full duplex 1m RG174 5m RG174 10 m RG174 20 m RG174 Fig. 13. Typical system link EYE-diagram at room temperature through a variable cable length full and half duplex. Shown is the differential output, i.e. VSDOp-VSDOn. The Duty Cycle Distortion is due to the used shielded twisted pair cable/connector. DCD is normally very small. DS-EQCO850SC-HS-2v0-2014-01-28 Page 13 of 13 ©2014 Eqcologic NV