HCS365
KEELOQ® Code Hopping Encoder
FEATURES
Security
Two programmable 32-bit serial numbers
Two programmable 64-bit crypt keys
Two programmable 60-bit seed values
Each transmission is unique
67/69-bit transmission code length
32-bit hopping code
Crypt keys are read protected
Operating
•
•
•
•
•
•
•
•
•
•
2.05-5.5V operation
Four button inputs
15 functions available
Four selectable baud rates
Selectable minimum code word completion
Battery low signal transmitted to receiver
Nonvolatile synchronization data
PWM, VPWM, PPM, and Manchester modulation
Button queue information transmitted
Dual Encoder functionality
Other
• On-chip EEPROM
• On-chip tuned oscillator (±10% over voltage and
temperature)
• Button inputs have internal pull-down resistors
• LED output
• PLL control for ASK and FSK
• Low external component count
Typical Applications
The HCS365 is ideal for Remote Keyless Entry (RKE)
applications. These applications include:
•
•
•
•
•
•
Automotive RKE systems
Automotive alarm systems
Automotive immobilizers
Gate and garage door openers
Identity tokens
Burglar alarm systems
© 2011 Microchip Technology Inc.
PDIP, SOIC
S0
1
S1
2
S2
3
S3/SHIFT/
RFEN
4
HCS365
•
•
•
•
•
•
•
PACKAGE TYPES
8
VDD
7
LED
6
DATA
5
Vss
HCS365 BLOCK DIAGRAM
Oscillator
Power
latching
and
switching
Controller
RESET circuit
LED
LED driver
EEPROM
DATA
Encoder
32-bit SHIFT register
VSS
Button input port
VDD
S3/SHIFT S2 S1 S0
RFEN
GENERAL DESCRIPTION
The HCS365 is a code hopping encoder designed for
secure Remote Keyless Entry (RKE) and secure
remote control systems. The HCS365 utilizes the
KEELOQ ® code hopping technology, which incorporates high security, a small package outline, and low
cost to make this device a perfect solution for unidirectional authentication systems and access control systems.
The HCS365 combines a hopping code generated by a
nonlinear encryption algorithm, a serial number, and
status bits to create a secure transmission code. The
length of the transmission eliminates the threat of code
scanning and code grabbing access techniques.
DS41109E-page 1
HCS365
The crypt key, serial number, and configuration data
are stored in an EEPROM array which is not accessible
via any external connection. The EEPROM data is programmable but read protected. The data can be verified only after an automatic erase and programming
operation. This protects against attempts to gain
access to keys or manipulate synchronization values.
In addition, the HCS365 supports a dual encoder. This
allows two manufacturers to use the same device without having to use the same manufacturer’s code in
each of the encoders. The HCS365 provides an easy
to use serial interface for programming the necessary
keys, system parameters, and configuration data.
1.0
SYSTEM OVERVIEW
Key Terms
The following is a list of key terms used throughout this
data sheet. For additional information on KEELOQ and
code hopping, refer to Technical Brief (TB003).
• RKE - Remote Keyless Entry
• Button Status - Indicates what button input(s)
activated the transmission. Encompasses the 4
button status bits S3, S2, S1 and S0 (Figure 3-2).
• Code Hopping - A method by which a code,
viewed externally to the system, appears to
change unpredictably each time it is transmitted.
• Code Word - A block of data that is repeatedly
transmitted upon button activation (Figure 3-2).
• Transmission - A data stream consisting of
repeating code words (Figure 4-1).
• Crypt Key - A unique and secret 64-bit number
used to encrypt and decrypt data. In a symmetrical block cipher such as the KEELOQ algorithm,
the encryption and decryption keys are equal and
will therefore be referred to generally as the crypt
key.
• Encoder - A device that generates and encodes
data.
• Encryption Algorithm - A recipe whereby data is
scrambled using a crypt key. The data can only be
interpreted by the respective decryption algorithm
using the same crypt key.
• Decoder - A device that decodes data received
from an encoder (i.e., HCS5XX).
• Decryption Algorithm - A recipe whereby data
scrambled by an encryption algorithm can be
unscrambled using the same crypt key.
• Learn – Learning involves the receiver calculating
the transmitter’s appropriate crypt key, decrypting
the received hopping code and storing the serial
number, synchronization counter value, and crypt
key in EEPROM. The KEELOQ product family facilitates several learning strategies to be implemented on the decoder. The following are
examples of what can be done.
DS41109E-page 2
- Simple Learning
The receiver uses a fixed crypt key. The crypt
key is common to every component used by
the same manufacturer.
- Normal Learning
The receiver derives a crypt key from the
encoder serial number. Every transmitter has
a unique crypt key.
- Secure Learning
The receiver derives a crypt key from the
encoder seed value. Every encoder has a
unique seed value that is only transmitted by
a special button combination.
• Manufacturer’s Code – A unique and secret 64bit number used to derive crypt keys. Each
encoder is programmed with a crypt key that is a
function of the manufacturer’s code. Each
decoder is programmed with the manufacturer
code itself.
The HCS365 code hopping encoder is designed specifically for keyless entry systems. In particular, typical
applications include vehicles and home garage door
openers. The encoder portion of a keyless entry system is integrated into a transmitter carried by the user.
The transmitter is operated to gain access to a vehicle
or restricted area. The HCS365 is meant to be a costeffective yet secure solution to such systems requiring
very few external components (Figure 2-1).
Most low end keyless entry transmitters are given a
fixed identification code that is transmitted every time a
button is pushed. The number of unique identification
codes in a low end system is usually a relatively small
number. These shortcomings provide an opportunity
for a sophisticated thief to create a device that ‘grabs’
a transmission and retransmits it later or a device that
quickly ‘scans’ all possible identification codes until the
correct one is found.
The HCS365, on the other hand, employs the KEELOQ
code hopping technology coupled with a transmission
length of 67 bits to virtually eliminate the use of code
‘grabbing’ or code ‘scanning’. The high security level of
the HCS365 is based on the patented KEELOQ technology. A block cipher based on a block length of 32 bits
and a key length of 64 bits is used. The algorithm
obscures the information in such a way that if a single
hopping code data bit changes (before encryption), statistically more than 50% of the encrypted data bits will
change.
© 2011 Microchip Technology Inc.
HCS365
As indicated in the block diagram on page one, the
HCS365 has a small EEPROM array which must be
loaded with several parameters before use; most often
programmed by the manufacturer at the time of production. The most important of these are:
• A serial number, typically unique for every
encoder
• A crypt key
• An initial synchronization value
FIGURE 1-1:
The crypt key generation typically inputs the transmitter
serial number and 64-bit manufacturer’s code into the
key generation algorithm (Figure 1-1). The manufacturer’s code is chosen by the system manufacturer and
must be carefully controlled as it is a pivotal part of the
overall system security.
CREATION AND STORAGE OF CRYPT KEY DURING PRODUCTION
Production
Programmer
HCS365
Transmitter
Serial Number
EEPROM Array
Serial Number
Crypt Key
Sync Counter
Manufacturer’s
Code
Key
Generation
Algorithm
The valid synchronization counter is the basis behind
the transmitted code word changing for each transmission; it increments each time a button is pressed. Each
increment of the synchronization value results in more
than 50% of the hopping code bits changing.
Figure 1-2 shows how the key values in EEPROM are
used in the encoder. Once the encoder detects a button
press, it reads the button inputs and updates the synchronization counter. The synchronization counter and
crypt key are input to the encryption algorithm and the
output is 32 bits of encrypted information. This data will
change with every button press while its value will
appear to ‘randomly hop around’. Hence, this data is
referred to as the hopping portion of the code word.
The 32-bit hopping code is combined with the button
information and serial number to form the code word
transmitted to the receiver. The code word format is
explained in greater detail in Section 4.1.
Crypt
Key
.
.
.
In normal operation, each received message of valid
format is evaluated. The serial number is used to determine if it is from a learned transmitter. If the serial number is from a learned transmitter, the message is
decrypted and the synchronization counter is verified.
Finally, the button status is checked to see what operation is requested. Figure 1-3 shows the relationship
between some of the values stored by the receiver and
the values received from the transmitter.
For detailed decoder operation, see Section 7.0.
A receiver may use any type of controller as a decoder.
Typically, it is a microcontroller with compatible firmware that allows the decoder to operate in conjunction
with an HCS365 based transmitter.
A transmitter must first be ‘learned’ by the receiver
before its use is allowed in the system. Learning
includes calculating the transmitter’s appropriate crypt
key, decrypting the received hopping code, storing the
serial number, storing the synchronization counter
value, and storing crypt key in EEPROM.
© 2011 Microchip Technology Inc.
DS41109E-page 3
HCS365
FIGURE 1-2:
BUILDING THE TRANSMITTED CODE WORD (ENCODER)
EEPROM Array
KEELOQ®
Encryption
Algorithm
Crypt Key
Sync Counter
Serial Number
Button Press
Information
Serial Number
32 Bits
Encrypted Data
Transmitted Information
FIGURE 1-3:
BASIC OPERATION OF RECEIVER (DECODER)
1 Received Information
EEPROM Array
Button Press
Information
Serial Number
2
32 Bits of
Encrypted Data
Check for
Match
Manufacturer Code
Serial Number
Sync Counter
Crypt Key
3
KEELOQ®
Decryption
Algorithm
Decrypted
Synchronization
Counter
Verify
4 Counter
Perform Function
5 Indicated by
button press
NOTE: Circled numbers indicate the order of execution.
DS41109E-page 4
© 2011 Microchip Technology Inc.
HCS365
2.0
DEVICE DESCRIPTION
As shown in the typical application circuits (Figure 2-1),
the HCS365 is an easy device to use. It requires only
the addition of buttons and RF circuitry for use as the
encoder in your security application. A description of
each pin is described in Table 2-1. Refer to Figure 2-2
for information on the I/O pins.
Note:
S0-S3 inputs have pull-down resistors. VIN
should be tied high if the step-up regulator
is not used.
TABLE 2-1:
PIN DESCRIPTIONS
Name
Pin
Number
S0
1
Switch input 0
S1
2
Switch input 1
S2
3
Switch input 2
S3/
SHIFT/
RFEN
4
Switch input 3,
SHIFT button or
RF Enable output
VSS
5
Ground reference
DATA
6
Data output pin/
LED
7
Open drain output for LED
VDD
8
Positive supply voltage
Description
© 2011 Microchip Technology Inc.
The HCS365 will normally be in a low power SLEEP
mode. When a button input is taken high, the device will
wake up, start the step-up regulator, and go through the
button debounce delay of TDB before the button code is
latched. In addition, the device will then read the configuration options. Depending on the configuration
options and the button code, the device will determine
what the data and modulation format will be for the
transmission. The transmission will consist of a stream
of code words and will be transmitted TPU after the button is pressed for as long as the buttons are held down
or until a time-out occurs. The code word format can be
either a code hopping format or a seed format.
The time-out time can be selected with the Time-out
Select (TSEL) configuration option. This option allows
the time-out to be set to 0.8s, 3.2s, 12.8s, or 25.6s.
When a time-out occurs, the device will go into SLEEP
mode to protect the battery from draining when a button
gets stuck.
If the device is in the transmit process and detects that
a new button is pressed, the current code word will be
aborted, a new code word will be transmitted and the
time-out counter will RESET. If all the buttons are
released, a minimum number of code words will still be
completed. The minimum code words can be set to 1,
2, 4, or 8 using the Minimum Code Words (MTX) configuration option. If the time for transmitting the minimum code words is longer than the time-out time, the
device will not complete the minimum code words.
DS41109E-page 5
HCS365
The HCS365 has an onboard nonvolatile EEPROM.
This EEPROM is used to store user programmable
data and the synchronization counter. The data is programmed at the time of production and includes the
security related information such as encoder keys,
serial numbers, discrimination values, and seed values. All the security related options are read protected.
The initial counter value is also programmed at the time
of production. From then on the device maintains the
counter itself. The HCS365 has built in redundancy for
protection and can recover from counter corruption.
The counter will not increment if the previous write was
corrupted by low voltage RESET or power failure during TPLL. Instead, the counter will revert back to the
previous count and the HCS370 will attempt to correct
the bad bits. This will continue on every button press
until the voltage increases and the counter is successfully corrected.
FIGURE 2-1:
TYPICAL CIRCUITS
VDD
B0
S0
VDD
B1
S1
LED
B2
S2
DATA
RF PLL
DATA IN
VSS
RFEN
ENABLE
Three buttons remote with PLL control
VDD
B4 B3 B2 B1 B0
S0
VDD
S1
LED
S2
DATA
S3
VSS
Tx out
Five buttons remote control (Note)
VDD
B1 B0
Tx2
Tx1
S0
VDD
S1
LED
S2
DATA
SHIFT
VSS
Tx out
DUAL Transmitter remote control
Note:
DS41109E-page 6
Up to 15 functions can be implemented by
pressing more than one button simultaneously or by using a suitable diode array.
© 2011 Microchip Technology Inc.
HCS365
FIGURE 2-2:
I/O CIRCUITS
FIGURE 2-3:
Figure 2-2(A)
BASIC FLOW DIAGRAM OF
THE DEVICE OPERATION
START
S0, S1, S2
Inputs
Sample Buttons
ZIN
Get Config
Seed
TX?
Yes
Read
Seed
No
Increment
Counter
Figure 2-2(B)
VDD
Encrypt
PFET
DATA OUT
Transmit
DATA I/O
NFET
TimeOut
Yes
No
No
MTX
STOP
Figure 2-2(C)
Yes
VDD
No
Buttons
P
DATA, RFEN
STEP
Outputs
Yes
No
N
Seed
Time
No
No
Yes
Seed
Button
Yes
No
New
Buttons
Yes
© 2011 Microchip Technology Inc.
DS41109E-page 7
HCS365
3.0
EEPROM ORGANIZATION
A summary of the HCS370 EEPROM organization is
shown in the three tables below. The address column
shows the starting address of the option and its length
or bit position. Options larger than 8 bits are stored
with the Most Significant bits at the given address.
TABLE 3-1:
Symbol
Enough consecutive 8-bit blocks are reserved for the
entire option size. Options such as SEED1, which
have a length that is not an exact multiple of 8 bits, is
stored right justified in the reserved space. Additional
smaller options such as SDBT1 may be stored in the
same address as the Most Significant bits.
ENCODER1 OPTIONS (SHIFT=0)
Reference
Section
Description(1)
Address16:Bits
KEY1
1E: 64 bits
Encoder Key
SEED1
14: 60 bits
Encoder Seed Value
3.2.2
3.3
SYNC1
00: 20 bits
00: 18 bits
Encoder Synchronization Counter (CNTSEL=1)
Encoder Synchronization Counter (CNTSEL=0) plus overflow
3.2, 3.2.1
SER1
10: 32 bits
Encoder Serial Number
3.2.2
DISC1
1C: 10 bits
Encoder Discrimination value
MSEL1
1C: ---- 32--
Transmission Modulation
Format
3.2, 3.2.1
Value2
Format
00
PWM
01
Manchester
10
VPWM
4.1
11
PPM
4 TE = 0
10 TE = 1
4.1
28 bits = 0
32 bits = 1
3.2
HSEL1
1C: ---4 ----
Header Select
XSER1
1C: --5- ----
Extended Serial Number
QUEN1
1C: -6-- ----
Queue counter Enable
Disable = 0
Enable = 1
5.5
STEN1
1C: 7--- ----
START/STOP Pulse
Enable
Disable = 0
Enable = 1
4.1
LEDBL1
3F: -6-- ----
Low Voltage LED Blink
Never = 0
Once = 1
5.3
LEDOS1
3F: 7--- ----
LED On Time
Select(1)
SDLM1
3C: ---- ---0
Limited Seed
SDMD1
3C: ---- --1-
Seed Mode
SDBT1
14: 7654 ----
Seed Button Code
SDTM1
3C: ---- 32--
Time Before Seed Code
Word(1)
BSEL1
GSEL1
3C: --54 ----
3C: 76-- ----
100 ms = 1
5.3
Enable = 1
3.3
User = 0
Production = 1
3.3
Value2
Time (s)
3.3
00
0.0
01
0.8
10
1.6
3.3
Transmission Baud Rate
Select(1)
Guard Time Select
50 ms = 0
Disable = 0
(1)
11
3.2
Value2
TE (μs)
00
100
01
200
10
400
11
800
Value2
Time (ms)
00
00
01
6.4
10
51.2
11
102.4
4.1
4.1, 5.2
Note 1: All Timing values vary ±10%.
DS41109E-page 8
© 2011 Microchip Technology Inc.
HCS365
TABLE 3-2:
Symbol
ENCODER2 OPTIONS (SHIFT=1)
Reference
Section
Description(1)
Address16:Bits
KEY2
34: 64 bits
SEED2
2A: 60 bits
Encoder Seed Value
3.3
SYNC2
08: 20 bits
08: 18 bits
Encoder Synchronization Counter (CNTSEL=1)
Encoder Synchronization Counter (CNTSEL=0) plus overflow
3.2,
3.2.1
SER2
26: 32 bits
Encoder Serial Number
3.2, 3.2.2
DISC2
32: 10 bits
Encoder Discrimination value
3.2, 3.2.1
MSEL2
32: ---- 32--
Transmission Modulation
Format
HSEL2
Encoder Key
3.2.1
Value2
Format
00
PWM
01
Manchester
10
VPWM
11
PPM
4 TE = 0
10 TE = 1
4.1
32: ---4 ----
Header Select
XSER2
32: --5- ----
Extended Serial Number
28 bits = 0
32 bits = 1
3.2
QUEN2
32: -6-- ----
Queue counter Enable
Disable = 0
Enable = 1
5.5
STEN2
32: 7--- ----
START/STOP Pulse
Enable
Disable = 0
Enable = 1
4.1
LEDBL2
3D: -6-- ----
Low Voltage LED Blink
Never = 0
Once = 1
5.3
LEDOS2
3D: 7--- ----
LED On Time Select(1)
50 ms = 0
100 ms = 1
5.3
SDLM2
3E: ---- ---0
Limited Seed
Disable = 0
Enable = 1
3.3
SDMD2
3E: ---- --1-
Seed Mode
User = 0
Production = 1
3.3
SDBT2
2A: 7654 ----
Seed Button Code
SDTM2
3E: ---- 32--
Time Before Seed Code
word(1)
Value2
Time (s)
3.3
00
0.0
01
0.8
10
1.6
11
3.2
Value2
TE (μs)
00
100
01
200
10
400
BSEL2
GSEL2
3E: --54 ----
3E: 76-- ----
Transmission Baud Rate
Select(1)
Guard Time Select(1)
4.1
3.3
11
800
Value2
Time (ms)
00
2 TE
01
6.4
10
51.2
11
102.4
4.1
4.1, 5.2
Note 1: All Timing values vary ±10%.
2: Voltage thresholds are ±150 mV.
© 2011 Microchip Technology Inc.
DS41109E-page 9
HCS365
TABLE 3-3:
Symbol
WAKE
DEVICE OPTIONS
3F: ---- --10
Reference
Section
Description(1)
Address16:Bits
Wake-up(1)
Value2
Value
00
No Wake-up
01
75 ms 50%
10
50 ms 33.3%
11
100 ms 16.7%
4.1
CNTSEL
3F: ---- -2--
Counter Select
16 bits = 0
20 bits = 1
3.2.1
VLOWL
3F: ---- 3---
Low Voltage Latch Enable
Disable = 0
Enable = 1
3.2.3.1
VLOWSEL
3F: ---4 ----
Low Voltage Trip Point Select(2)
2.2 V = 0
3.2V = 1
3.2.3.1
PLLSEL
3F: --5- ----
PLL Interface Select
ASK = 0
FSK = 1
5.2
MTX
3D: ---- --10
Minimum Code Words
Value2
Value
2.0
00
1
01
2
10
4
TSEL
3D: --54 ----
Time-out Select(1)
11
8
Value2
Time(s)
00
0.8
01
3.2
10
12.8
11
25.6
DUAL
3D:-----2--
Dual Encoder Enable
Disable = 0
Enable = 1
RFENO
3D: ----3---
RF Enable Output Select
Disable = 0
Enable = 1
2.0
Note 1: All Timing values vary ±10%.
2: Voltage thresholds are ±150 mV.
3.1
Dual Encoder Operation
The HCS365 contains two transmitter configurations
with separate serial numbers, encoder keys, discrimination values, counters, and seed values. This means
that the HCS365 can be used as two independent
encoders. The code word is calculated using one of two
possible encoder configurations. Most options for code
word and modulation formats can be different from
Encoder 1 and Encoder 2. However, LED and RF
transmitter options have to be the same. The SHIFT
input pin is used to select between the encoder configurations. A low on the SHIFT pin will select Encoder 1
and a high will select Encoder 2.
DS41109E-page 10
© 2011 Microchip Technology Inc.
HCS365
3.2
Code Word Format
serial number. This will be stored by the receiver system after a transmitter has been learned. The discrimination bits are part of the information that is to form the
encrypted portion of the transmission.
A KEELOQ code word consists of 32 bits of hopping
code data, 32 bits of fixed code data, and between 3 to
5 bits of status information. Various code word formats
are shown in Figure 3-1 and Figure 3-2.
3.2.1
3.2.2
The 32 bits of fixed code consist of 28 bits of the serial
number (SER) and a copy of the 4-bit function code.
This can be changed to contain the whole 32-bit serial
number by setting the Extended Serial Number (XSER)
configuration option to a 1. If more than one button is
pressed, the function codes are logically OR’ed
together. The function code is repeated in the
encrypted and unencrypted data of a transmission.
HOPPING CODE PORTION
The hopping code portion is calculated by encrypting
the counter, discrimination value, and function code
with the Encoder Key (KEY). The hopping code is calculated when a button press is debounced and remains
unchanged until the next button press.
The counter can be either a 16- or 20-bit counter. The
Configuration Option Counter Select (CNTSEL) value
will determine this. The counter select option must be
the same for both Encoder 1 and Encoder 2. If the 16-bit
counter is selected, the discrimination value is 10 bits
long and there are 2 counter overflow bits (OVR0,
OVR1). Set both bits in production and OVR0 will be
cleared on the first counter overflow and OVR1 on the
second.
TABLE 3-4:
If the counter is 20 bits, the discrimination value is 8 bits
long and there are no overflow bits. The rest of the 32
bits are made up of the function code also known as the
button inputs.
FUNCTION CODES
Button
Function Code
S0
xx1x2
S1
x1xx2
S2
1xxx2
S3
xxx12
3.2.3
STATUS INFORMATION
The status bits will always contain the output of the Low
Voltage (VLOW) detector and Cyclic Redundancy
Check (CRC). If Queue (QUEN) is enabled, button
queue information will be included in the code words.
The discrimination value can be programmed with any
value to serve as a post decryption check on the
decoder end. In a typical system, this will be programmed with the 8 or 10 Least Significant bits of the
FIGURE 3-1:
FIXED CODE PORTION
CODE WORD DATA FORMAT (16-BIT COUNTER)
With XSER=0, 16-bit Counter, QUEN=0
CRC
2 Bits
C1
VLOW
1-Bit
C0
Hopping Code Portion (32 Bits)
Fixed Code Portion (32 Bits)
Status Information
(3 Bits)
BUT
4 Bits
Counter
BUT Overflow
4 Bits 2 Bits
SERIAL NUMBER
(28 Bits)
S2 S1 S0 S3
S2 S1 S0 S3
OVR1
DISC
10 Bits
Synchronization
Counter
16 Bits
0
15
OVR0
With XSER=1, 16-bit Counter, QUEN=1
Status Information
(5 Bits)
QUE
2 Bits
CRC
2 Bits
VLOW
1-Bit
Q1 Q0 C1 C0
Fixed Code Portion (32 Bits)
Hopping Code Portion (32 Bits)
Counter
BUT Overflow
4 Bits 2 Bits
SERIAL NUMBER
(32 Bits)
S2
S1
S0 S3
OVR1
DISC
10 Bits
Synchronization
Counter
16 Bits
0
15
OVR0
Transmission Direction LSB First
© 2011 Microchip Technology Inc.
DS41109E-page 11
HCS365
FIGURE 3-2:
CODE WORD DATA FORMAT (20-BIT COUNTER)
With XSER=0, 20-bit Counter, QUEN=1
Fixed Code Portion (32 Bits)
Status Information
(5 Bits)
QUE
2 Bits
CRC
2 Bits
Q1 Q0 C1 C0
VLOW
1-Bit
BUT
4 Bits
S2 S1 S0
Hopping Code Portion (32 Bits)
SERIAL NUMBER
(28 Bits)
S3
BUT
4 Bits
S2
S1
DISC
8 Bits
Synchronization
Counter
20 Bits
0
19
S0 S3
With XSER=1, 20-bit Counter, QUEN=0
Status Information
(3 Bits)
CRC
2 Bits
VLOW
1-Bit
Fixed Code Portion (32 Bits)
Hopping Code Portion (32 Bits)
SERIAL NUMBER
(32 Bits)
C1 C0
BUT
4 Bits
S2
S1
DISC
8 Bits
Synchronization
Counter
20 Bits
19
0
S0 S3
Transmission Direction LSB First
3.2.3.1
Low Voltage Detector Status (VLOW)
A low battery voltage detector onboard the HCS365
can indicate when the operating voltage drops below a
predetermined value. There are two options available
depending on the Low Voltage Trip Point Select
(VLOWSEL) configuration option. The two options provided are:
• A 2.2V nominal level for 3V operation
• A 3.2V nominal level for 5V operation
The output of the low voltage detector is transmitted in
each code word, so the decoder can give an indication
to the user that the transmitter battery is low. Operation
of the LED changes as well to further indicate that the
battery is low and needs replacing.
The output of the Low Voltage Detector can also be
latched once it has dropped below the selected value.
The Low Voltage Latch (VLOWL) configuration option
enables this option. If this option is enabled, the detector level is raised to 3V or 5V once a low battery voltage
has been detected. The original value is reinstated if
the VDD voltage is raised above this level, indicating
that a new battery has been installed.
The Low Voltage Latch (VLOWL) if enabled works similar to a Schmitt Trigger. This will effectively hold the
VLOW bit high until the battery is replaced. If the Low
Voltage Latch is enabled, then the break after the first
preamble pulse can stretch by 4 ms one time as the
latch changes state.
DS41109E-page 12
© 2011 Microchip Technology Inc.
HCS365
3.3
Seed Code Word Data Format
A seed transmission transmits a code word that consists of 60 bits of fixed data that is stored in the
EEPROM. This can be used for secure learning of
encoders or whenever a fixed code transmission is
required. The seed code word contains the function
code. The seed code also contains the status information (VLOW, CRC, and QUEUE). The Seed code word
format is shown in Figure 3-3. The function code for
seed code words is always 11112.
Seed code words for Encoder 1 and Encoder 2 can be
configured as follows:
• Enabled with the Seed Button Code (SDBT) configuration option or disabled if SDBT = 00002.
• If the Limited Seed (SDLM) configuration option is
set, seed transmissions will be disabled when the
synchronization counter is bigger than 127. Seed
transmissions remain disabled even if the 16/20bit counter rolls over to 0.
• The delay before the seed transmission is transmitted can be set to 0.0s, 0.8s, 1.6s and 3.2s with
the Seed Time (SDTM) configuration option.
When SDTM is set to a value other than 0.0s, the
HCS365 will transmit a code hopping transmission until the selected time expires. After the
selected time expires, the seed code words are
transmitted. This is useful for the decoder to learn
FIGURE 3-3:
the serial number and the seed from a single button press.
• The button code for transmitting a seed code
word can be selected with the Seed Button
(SDBT) configuration option. SDBT bits 0 to 3 correspond to button inputs S0 to S3. Set the bits
high for the button combination that should trigger
a seed transmission (i.e., If SDBT = 10102 then,
S3+S1 will trigger a seed transmission).
• The seed transmissions before the counter increments past 128 can be modified with the Seed
Mode (SDMD) configuration option. Setting this
bit for Production mode will cause the selected
seed button combination to first transmit a normal
hopping code word for the selected Minimum
Code words (MTX) and then at least MTX seed
code words until all buttons are released. This
mode is disabled after the counter reaches 128
even if the 16/20-bit counter rolls over to 0.
• The limit of 127 for SDLM or SDMD can be
reduced by using an initial counter value >0.
Note:
The synchronization counter only increments on code hopping transmissions.
The counter will not advance on a seed
transmission unless Seed Delay or Production mode options are on.
SEED CODE WORD FORMAT
With QUEN = 1
SEED Code
(60 bits)
Open Portion (Not Encrypted)
(9 bits)
QUE
CRC VLOW
(2 Bits) (2 Bits) (1-Bit)
Q1 Q0 C1 C0
1
SEED
Function
(4 Bits)
1
1
1
Transmission Direction LSB First
© 2011 Microchip Technology Inc.
DS41109E-page 13
HCS365
4.0
TRANSMITTED WORD
4.1
Transmission Modulation Format
option. The Header time can be set to 4TE or 10TE with
the Header Select (HSEL) configuration option. These
options can all be set individually for Encoder 1 and
Encoder 2.
The HCS365 transmission is made up of several code
words. Each code word contains a preamble, header,
and data. A code word is separated from another code
word by guard time. The Guard Time Select (GSEL)
configuration option can be set to 0 ms, 6.4 ms, 51.2
ms, or 102.4 ms.
There are four different modulation formats available
on the HCS365 that can be set individually for Encoder
1 or Encoder 2. The Modulation Select (MSEL) Configuration Option is used to select between:
•
•
•
•
All other timing specifications for the modulation formats are based on a basic timing element (TE). This
Timing Element can be set to 100 μs, 200 μs, 400 μs or
800 μs with the Baud Rate Select (BSEL) configuration
FIGURE 4-1:
Pulse Width Modulation (PWM)
Manchester (MAN)
Variable Pulse Width Modulation (VPWM)
Pulse Position Modulation (PPM)
PULSE WIDTH MODULATION (PWM)
TE
TE
TE
LOGIC "0"
LOGIC "1"
TBP
1
16
4-10
xTE
Header
31xTE 50% Preamble
FIGURE 4-2:
Encrypted Portion
Fixed Code Portion
Guard
Time
MANCHESTER (MAN)
TE
TE
LOGIC "0"
LOGIC "1"
TBP
1
2
16
31xTE 50% Preamble
START bit
bit 0 bit 1 bit 2
4 xTE
Header
DS41109E-page 14
Encrypted Portion
STOP bit
Fixed Code Portion
Guard
Time
© 2011 Microchip Technology Inc.
HCS365
FIGURE 4-3:
VARIABLE PULSE WIDTH MODULATION (VPWM)
LOGIC “0”
LOGIC “1”
TE
VPWM BIT ENCODING:
TE
on Transition Low to High
TBP
TBP
2XTE
on Transition High to Low
LOGIC “0”
TE
LOGIC “1”
TE TE
TBP
1
2
31xTE 50% Preamble
FIGURE 4-4:
TBP
2XTE
16
10xTE Header
Encrypted Portion
Guard
Time
Fixed Code Portion
PULSE POSITION MODULATION (PPM)
TE TE TE
LOGIC "0"
LOGIC "1"
TBP
3 X TE
START bit
1
2
16
31xTE 50% Preamble
STOP bit
TBP
10xTE Header
In addition to the Modulation Format, Guard Time, and
Baud Rate, the following options are also available to
change the transmission format:
• If the START/STOP Pulse Enable (STEN) configuration option is enabled, the HCS365 will place a
leading and trailing ‘1’ on each code word. This is
necessary for modulation formats such as Manchester and PPM to interpret the first and last data
bit.
• A wake-up sequence can be transmitted before
the transmission starts. The wake-up sequence is
configured with the Wake-up (WAKE) configuration option and can be disabled or set to 50 ms,
75 ms, or 100 ms of pulses as indicated in
Figure 4-5.
• The WAKE option is the same for both Encoder 1
and Encoder 2.
Encrypted Portion
FIGURE 4-5:
Fixed Code Portion
Guard
Time
WAKE-UP ENABLE
TE TE
WAKE-UP = 75 ms
TE
2TE
WAKE-UP = 50 ms
TE
5TE
WAKE-UP = 100 ms
TG
WAKE-UP CODE
TG
CODE
Guard Time = 6.4 ms, 51.2 ms, or 102.4 ms
© 2011 Microchip Technology Inc.
DS41109E-page 15
HCS365
5.0
SPECIAL FEATURES
5.1
Internal RC Oscillator
The HCS365 has an onboard RC oscillator that controls all the logic output timing characteristics. The
oscillator frequency varies over temperature and voltage variances, but stays within ±10% of the tuned
value. All the timing values specified in this document
are subject to this oscillator variation.
5.2
RF Enable and PLL Interface
The S3/SHIFT/RFEN pin of the HCS365 can be configured to function as a RF enable output signal. This is
done with the RF Enable Output (RFENO) configura-
FIGURE 5-1:
tion option. When enabled, this pin will be driven high
whenever data is transmitted through the DATA pin. If
the RFEN output is enabled it will not be possible to utilize the dual encoder functionality.
In addition, the RF Enable and DATA output interfaces
with RF PLL’s. The PLL interface select (PLLSEL) configuration option selects between the ASK and FSK
interfaces. Figure 5-1 shows the startup sequence for
both ASK and FSK interface options. The RFEN signal
will go low at the end of the last code word, including
the guard time.
If RFENO = 1, the RFEN pin will be driven high whenever data is transmitted through the DATA pin.
ASK/FSK INTERFACE
S0
ASK RFEN
CODE WORD
CODE WORD
CODE WORD
CODE WORD
ASK DATA
FSK RFEN
FSK DATA
TPU
5.3
TPLL
TG
LED Output
The LED pin will be driven low while the HCS365 is
transmitting data. The LED On Time (TLEDON) can be
selected between 50 ms and 100 ms with the LED On
Time Select (LEDOS) configuration option. The LED
Off Time (TLEDOFF) is fixed at 500 ms. When the VDD
voltage drops below the selected VLOW trip point, the
LED will not blink unless the LED Blink (LEDBL) option
is set. If LEDBL is set and VDD is low, then the LED will
only flash once. Waveforms of the LED behavior are
shown in Figure 5-2.
TG
resistor will conserve battery power. This is an open
drain output but it does have a weak pull-up capable of
driving a CMOS input.
For circuits with VDD greater than 3 volts, be sure to
limit the LED circuit with a series resistor. The LED output can safely sink up to 25 mA but adding an external
DS41109E-page 16
© 2011 Microchip Technology Inc.
HCS365
FIGURE 5-2:
LED OPERATION
FIGURE 5-3:
SN
TLEDON
MTX = 012, WAKE > 002
TLEDOFF
LED
VDD > VLOW
SN
QUEN = Disabled
LED
VDD < VLOW
LEDBL=1
DATA
WAKE-UP CODE1
CODE1
WAKE-UP CODE2
CODE2
QUEN = Enabled
LED
VDD < VLOW
LEDBL=0
5.4
CODE WORD COMPLETION
WITH QUEN SETTINGS
DATA
Cyclic Redundancy Check (CRC)
The CRC bits are calculated on the 65 previously transmitted bits. These bits contain the 32-bit hopping code,
32-bit fixed code, and VLOW bit. The decoder can use
the CRC bits to check the data integrity before processing starts. The CRC can detect all single bit errors and
66% of double bit errors. The CRC is computed as follows:
EQUATION 5-1:
6.0
WAKE-UP
CODE1 00
WAKE-UP CODE2 01
CODE2 01
PROGRAMMING
SPECIFICATIONS
Refer to the “HCS365 Programming Specifications”
document (DS41157) in Microchip Literature.
CRC Calculation
CRC [ 1 ] n + 1 = CRC [ 0 ] n ⊕ Di n
and
CRC [ 0 ] n + 1 = ( CRC [ 0 ] n ⊕ Di n ) ⊕ CRC [ 1 ] n
with
CRC [ 1, 0 ] 0 = 0
and Din the nth transmission bit 0
