HV257
32-Channel High-Voltage Sample-and-Hold Amplifier Array
Features
General Description
•
•
•
•
•
•
•
•
•
The HV257 is a 32-channel, high-voltage
sample-and-hold amplifier array integrated circuit. It
operates on a single high-voltage supply, up to 300V,
and two low-voltage supplies, VDD and VNN.
Thirty-two Independent High-voltage Amplifiers
300V Operating Voltage
295V Output Voltage
2.2V/µs Typical Output Slew Rate
Adjustable Output Current Source Limit
Adjustable Output Current Sink Limit
Internal Closed-loop Gain of 72V/V
12 MΩ Feedback Impedance
Layout Ideal for Die Applications
Applications
• Microelectromechanical Systems (MEMS) Driver
• Piezoelectric Transducer Driver
• Optical Crosspoint Switches
(Using MEMS Technology)
All 32 sample-and-hold circuits share a common
analog input, VSIG. The individual sample-and-hold
circuits are selected by a five-to-32 logic decoder. The
sampled voltage on the holding capacitor is buffered by
a low-voltage amplifier and is magnified by a
high-voltage amplifier with a closed-loop gain of 72V/V.
The internal closed-loop gain is set for an input voltage
range of 0V to 4.096V. The input voltage can be up to
5V, but the output will saturate. The maximum output
voltage swing is 5V below the VPP high-voltage supply.
The outputs can drive capacitive loads of up to
3000 pF.
The maximum output source and sink current can be
adjusted by using two external resistors. An external
RSOURCE resistor controls the maximum sourcing
current, and an external RSINK resistor controls the
maximum sinking current. The current limit is
approximately 12.5V divided by the external resistor
value. The setting is common for all 32 outputs. A
low-voltage silicon junction diode is made available to
help monitor the die temperature.
Package Type
100-lead MQFP
(Top view)
100
1
See Table 3-1 for pin information.
2017 Microchip Technology Inc.
DS20005827A-page 1
HV257
Functional Block Diagram
BYP-VPP
BYP-AVDD
BYP-AVNN
Anode
Cathode
To internal VPP bus
VPP
Bias Circuit
AVDD
To internal analog VDD bus
AVNN
To internal analog VNN bus
DVDD
DVNN
To internal digital VDD bus
To internal digital VNN bus
AVDD
VPP
+
VSIG
DVDD
CH
-
A0
A1
A2
A3
A4
HVOUT0
-
Q0
Q1
+
AVNN
AVNN
S/H-0
71R
R
5 to 32
Decoder
AVDD
VPP
+
CH
EN
Q31
+
-
HVOUT1
AVNN
AVNN
S/H-1
DGND
71R
R
AGND
AVDD
RSOURCE
HVOUT
Current
Source
Limiting
VPP
+
To all HVOUT
amplifiers
CH
+
-
HVOUT31
AVNN
RSINK
HVOUT
Current
Sink
Limiting
DS20005827A-page 2
To all HVOUT
amplifiers
S/H-31
AVNN
R 71R
2017 Microchip Technology Inc.
HV257
Typical Application Circuit
HV257
High Voltage
Power Supply
HVOUT0
VSIG
DAC
HVOUT1
Low Voltage
Power Supply
High
Voltage
OpAmp
Array
32
A1
A2
A3
A4
Low Voltage
Channel
Select
Sample
and Hold
EN
DGND
HVOUT3
y
x
x
y
HVOUT30
RSINK
A0
RSOURCE
Micro
Processor
HVOUT2
HVOUT31
MEMS
Array
AGND
VNN
2017 Microchip Technology Inc.
DS20005827A-page 3
HV257
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
High-voltage Supply, VPP ....................................................................................................................................... 310V
Analog Low-voltage Positive Supply, AVDD ................................................................................................................ 8V
Digital Low-voltage Positive Supply, DVDD ................................................................................................................. 8V
Analog Low-voltage Negative Supply, AVNN ............................................................................................................ –7V
Digital Low-voltage Negative Supply, DVNN ............................................................................................................ –7V
Logic Input Voltage.................................................................................................................................. –0.5V to DVDD
Analog Input Signal, VSIG ................................................................................................................................. 0V to 6V
Maximum Junction Temperature, TJ ..................................................................................................................... 150°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
High-voltage Positive Supply
VPP
125
—
300
V
Low-voltage Positive Supply
VDD
6
—
7.5
V
Conditions
Low-voltage Negative Supply
VNN
–4.5
—
–6.5
V
VPP Supply Current
IPP
—
—
0.8
mA
VPP = 300V, All HVOUT = 0V, No load
VDD Supply Current
IDD
—
—
5
mA
VDD = 6V to 7.5V
VNN Supply Current
INN
–6
—
—
mA
VNN = –4.5V to –6.5V
Operating Temperature Range
TJ
–10
—
85
°C
DS20005827A-page 4
2017 Microchip Technology Inc.
HV257
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter
Sym.
Min.
Typ.
Max.
Unit
HVOUT Voltage Swing
HVOUT
0
—
VPP–5
V
Input Voltage Offset
VINOS
—
—
±40
mV
RFB
9.6
12
—
MΩ
Feedback Resistance from HVOUT
to Ground
HVOUT Capacitive Load
HVOUT Sourcing Current Limiting Range
HVOUT Sinking Current Limiting Range
External Resistance Range
for Setting Maximum Current Source
External Resistance Range for Setting
Maximum Current Sink
Conditions
Input referred
CLOAD
0
—
3000
pF
ISOURCE
50
—
500
µA
ISOURCE = 12.5V/RSOURCE
ISINK
50
—
500
µA
ISINK = 12.5V/RSINK
RSOURCE
25
—
250
kΩ
RSINK
25
—
250
kΩ
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter
HVOUT Slew Rate Rise
HVOUT Slew Rate Fall
Sym.
SR
Min.
Typ.
Max.
Unit
—
2.2
—
V/µs
No load
—
2
—
V/µs
No load
VPP = 300V
HVOUT –3 dB Channel Bandwidth
BW
—
4
—
kHz
Open-loop Gain
AO
70
100
—
dB
AV
68.4
72
75.6
V/V
DC Channel-to-channel Crosstalk
Closed-loop Gain
CTDC
–80
—
—
dB
Power Supply Rejection Ratio for VPP,
VDD and VNN
PSRR
–40
—
—
dB
Acquisition Time
tAQ
—
4
—
µs
Pedestal Voltage
VPED
—
1
—
mV
Sample-and-Hold Switch Resistance
RSW
—
5
—
kΩ
CH
—
10
12
pF
VDROOP
—
6
—
V/s
Input Signal Voltage Range
VSIG
0
—
5
V
VSIG Input Capacitance
CSIG
—
33
—
pF
tSU
75
—
—
ns
ns
Conditions
SAMPLE AND HOLD
Sample-and-Hold Capacitor
Voltage Droop Rate During Hold Time
Relative to Input
Input referred
Output referred
LOGIC DECODER
Set-up Time-address to Enable
Hold Time-address to Enable Bar
tH
75
—
—
Input Logic High Voltage
VIH
2.4
—
VDD
V
Input Logic Low Voltage
VIL
0
—
1.2
V
Input Logic High Current
IIH
—
—
1
µA
VIH = VDD
Input Logic Low Current
IIL
–1
—
—
µA
VIL = 0V
Logic Input Capacitance
CIN
—
—
15
pF
2017 Microchip Technology Inc.
DS20005827A-page 5
HV257
AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
PIV
—
—
5
V
Cathode to anode
V
IF = 100 µA, anode to cathode at TA = 25°C
µA
Anode to cathode
TEMPERATURE DIODE
Peak Inverse Voltage
Forward Diode Drop
VF
—
Forward Diode Current
IF
VF Temperature Coefficient
TC
0.6
—
—
—
100
—
–2.2
—
Min.
Typ.
Max.
mV/°C Anode to cathode
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Unit
Conditions
TEMPERATURE RANGE
Maximum Junction Temperature
TJ
—
—
+150
°C
Storage Temperature
TS
–65
—
+150
°C
JA
—
39
—
°C/W
PACKAGE THERMAL RESISTANCE
100-lead MQFP
Timing Waveforms of Sample-and-Hold
tSU
tH
A0-A4
EN
Hold
Sample
Hold
tR/F
Hold Step
(VPEDESTAL)
HVOpamp
Acquisition Window
DECODER FUNCTION TABLE
A4
A3
A2
A1
A0
EN
Selected S/H
L
L
L
L
L
L
L
L
H
0
L
H
H
1
L
L
L
L
L
L
H
L
H
2
H
H
H
3
↕
↕
↕
↕
↕
↕
↕
H
H
H
H
L
H
30
H
H
H
H
H
H
31
X
X
X
X
X
L
All Open
DS20005827A-page 6
2017 Microchip Technology Inc.
HV257
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
600
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
-10OC
700
500
25OC
max
min
600
Vf (mV)
ISINK (μA)
400
300
200
85OC
max
min
500
max
min
max
100
400
min
0
25
150
250
300
1.0
RSINK (kΩ)
FIGURE 2-1:
40
60
80
100
Diode Biasing Current (μA)
ISINK vs. RSINK.
Temperature Diode vs.
FIGURE 2-4:
Temperature.
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
40
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
600
500
20
HVOUT (mV)
ISOURCE (μA)
20
400
300
0
200
-20
max
100
min
0
25
150
-40
250
0
RSOURCE (kΩ)
FIGURE 2-2:
1.0
2.0
3.0
4.0
VSIG Level (V)
ISOURCE vs. RSOURCE.
FIGURE 2-5:
VSIG.
HVOUT Charge Injection vs.
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
3.0
120
(”one RC” response to one volt input step) (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
2.0
+85OC
+25OC
HVOUT (V/sec)
HVOUT (mV)
100
-10OC
80
60
1.0
0
40
25OC
85OC
-1.0
20
-10OC
0
0
2.0
4.0
-2.0
0
VSIG (V)
FIGURE 2-3:
Acquisition Window.
2017 Microchip Technology Inc.
150
280
HVOUT Level (V)
FIGURE 2-6:
HVOUT Droop.
DS20005827A-page 7
HV257
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
3.5
3.0
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
-50
2.5
2.0
Input Offset (mV)
VPP PSRR (dB)
-40
-30
-20
1.5
Offset at -10OC
Offset at 25OC
Offset at 85OC
-2.0
-2.5
-10
-3.0
-3.5
0
10
100
1k
10k
100k
1M
-4.0
Frequency (Hz)
-4.5
1.0
2.0
3.0
VIN (Volts)
FIGURE 2-7:
FIGURE 2-10:
Temperature.
Gain
-40
-30
-20
-10
0
10
100
1k
10k
100k
Input Offset vs. VIN and
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC )
73.97
73.96
73.95
73.94
73.93
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
-50
VDD PSRR (dB)
VPP PSRR vs. Frequency.
72.74
72.73
72.72
72.71
72.70
72.69
1.0
2.0
3.0
VIN (Volts)
1M
Frequency
FIGURE 2-8:
VDD PSRR vs. Frequency.
FIGURE 2-11:
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
-50
HV257DFG-5037047 Q3 Dev # 3, Channel 16
(VPP = 300V, VDD = 6.5V, VNN = -5.0V, VSIG = 1.0V, TA = 25OC)
73.028
HVOUT (V)
VNN PSRR (dB)
73.030
-40
Gain vs. VIN.
-30
-20
73.026
73.024
73.022
73.020
-10
73.018
73.016
0
10
100
1k
10k
100k
1M
Frequency
FIGURE 2-9:
DS20005827A-page 8
VNN PSRR vs. Frequency.
73.014
0
FIGURE 2-12:
Time (hours)
8
HVOUT Drift.
2017 Microchip Technology Inc.
HV257
3.0
PIN DESCRIPTION
The details on the pins of HV257 are listed on
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
HVOUT31
Amplifier output
2
HVOUT30
Amplifier output
3
HVOUT29
Amplifier output
4
HVOUT28
Amplifier output
5
HVOUT27
Amplifier output
6
HVOUT26
Amplifier output
7
HVOUT25
Amplifier output
8
HVOUT24
Amplifier output
9
HVOUT23
Amplifier output
10
HVOUT22
Amplifier output
11
HVOUT21
Amplifier output
12
HVOUT20
Amplifier output
13
HVOUT19
Amplifier output
14
HVOUT18
Amplifier output
15
HVOUT17
Amplifier output
16
HVOUT16
Amplifier output
17
HVOUT15
Amplifier output
18
HVOUT14
Amplifier output
19
HVOUT13
Amplifier output
20
HVOUT12
Amplifier output
21
HVOUT11
Amplifier output
22
HVOUT10
Amplifier output
23
HVOUT9
Amplifier output
24
HVOUT8
Amplifier output
25
HVOUT7
Amplifier output
26
HVOUT6
Amplifier output
27
HVOUT5
Amplifier output
28
HVOUT4
Amplifier output
29
HVOUT3
Amplifier output
30
HVOUT2
Amplifier output
31
HVOUT1
Amplifier output
32
HVOUT0
Amplifier output
33
VPP
High-voltage positive supply. There are two pads.
34
NC
No connection
35
NC
No connection
2017 Microchip Technology Inc.
Description
DS20005827A-page 9
HV257
TABLE 3-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
36
NC
No connection
37
NC
No connection
38
NC
No connection
39
AGND
Analog ground. There are three pads. They need to be externally connected.
40
AVNN
Analog low-voltage negative supply. This should be at the same potential as
DVNN. There are two pads.
41
NC
42
AVDD
Analog low-voltage positive supply. This should be at the same potential as
DVDD. There are two pads.
43
AGND
Analog ground. There are three pads. They need to be externally connected.
44
DVNN
Digital low-voltage negative supply. This should be at the same potential as
AVNN. There are two pads.
45
DVDD
Digital low-voltage positive supply. This should be at the same potential as AVDD.
There are two pads.
46
NC
No connection
47
NC
No connection
48
NC
No connection
49
NC
No connection
50
NC
No connection
51
NC
No connection
52
NC
No connection
53
NC
No connection
54
NC
No connection
55
NC
No connection
56
NC
No connection
57
NC
No connection
58
NC
No connection
59
NC
No connection
60
NC
No connection
61
NC
No connection
62
NC
No connection
63
NC
No connection
64
NC
No connection
65
NC
No connection
66
NC
No connection
67
NC
No connection
68
NC
No connection
69
NC
No connection
70
NC
No connection
71
NC
No connection
DS20005827A-page 10
Description
No connection
2017 Microchip Technology Inc.
HV257
TABLE 3-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
72
NC
No connection
73
NC
No connection
74
NC
No connection
75
NC
No connection
76
NC
No connection
77
NC
No connection
78
NC
No connection
79
NC
No connection
80
EN
Active logic high input. Logic low will keep sample-and-hold switches open.
81
A0
Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
82
A1
Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
83
A2
Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
84
A3
Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
85
A4
Decoder logic input. Addressed channel will close the sample-and-hold switch.
Sample-and-hold switches for unaddressed channels are kept open.
86
DGND
Digital ground
87
DVDD
Digital low-voltage positive supply. This should be at the same potential as AVDD.
There are two pads.
88
DVNN
Digital low-voltage negative supply. This should be at the same potential as
AVNN. There are two pads.
89
AGND
Analog ground. There are three pads. They need to be externally connected.
90
VSIG
Common input signal for all 32 sample-and-hold circuits.
91
AVDD
Analog low-voltage positive supply. This should be at the same potential as
DVDD. There are two pads.
92
BYP-AVNN
Internally generated reference voltage. An external low-voltage (1 nF–10 nF)
capacitor needs to be connected across AVNN and BYP-AVNN.
93
BYP-AVDD
Internally generated reference voltage. An external low-voltage (1 nF–10 nF)
capacitor needs to be connected across AVDD and BYP-AVDD.
94
AVNN
Analog low-voltage negative supply. This should be at the same potential as
DVNN. There are two pads.
95
Anode
The anode side of a low-voltage silicon diode that can be used to monitor die
temperature.
96
Cathode
97
RSINK
98
RSOURCE
2017 Microchip Technology Inc.
Description
The cathode side of a low-voltage silicon diode that can be used to monitor die
temperature.
The external resistor from RSINK to VNN that sets the output current sinking limit.
The current limit is approximately 12.5V divided by the RSINK resistor value.
The external resistor from RSOURCE to VNN that sets the output current
sourcing limit. The current limit is approximately 12.5V divided by RSOURCE
resistor value.
DS20005827A-page 11
HV257
TABLE 3-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
Description
99
BYP-VPP
The internally generated reference voltage. An external low-voltage (1 nF–10 nF)
capacitor needs to be connected across VPP and BYP-VPP.
100
VPP
DS20005827A-page 12
High-voltage positive supply. There are two pads.
2017 Microchip Technology Inc.
HV257
3.1
Pad Configuration
DVDD
DGND
DVNN
VSIG
AGND
AVDD
Byp-AVNN
AVNN
Anode
Byp-AVDD
Do Not Bond.
For testing only.
Cathode
A4
RSINK
A3
RSOURCE
A2
BYP-VPP
VPP
HVOUT31
A1
A0
EN
HVOUT30
HVOUT29
HVOUT28
HVOUT27
HVOUT26
HVOUT25
HVOUT24
HVOUT23
HVOUT22
HVOUT21
HVOUT20
HVOUT19
HVOUT18
HVOUT17
Do Not Bond.
Leave Floating.
HVOUT16
HVOUT15
HVOUT14
HVOUT13
HVOUT12
HVOUT11
HVOUT10
HVOUT9
HVOUT8
HVOUT7
HVOUT6
HVOUT5
HVOUT4
HVOUT3
HVOUT2
HVOUT1
HVOUT0
VPP
DVDD
DVNN
AGND
AVDD
AVNN
AGND
FIGURE 3-1:
Pad Configuration Drawing.
2017 Microchip Technology Inc.
DS20005827A-page 13
HV257
TABLE 3-2:
TABLE 3-2:
PAD COORDINATES
PAD COORDINATES
(CONTINUED)
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name
X (µm)
Y (µm)
Pad Name
X (µm)
Y (µm)
VPP
–8338.5
2708.5
BYP-AVNN
8047
–135.5
HVOUT0
–7895
2305.5
AVDD
8047
–704.5
HVOUT1
–7448.5
2305.5
VSIG
8047
–1072.5
8047
–1424.5
HVOUT2
–7001.5
2305.5
AGND
HVOUT3
–6554.5
2305.5
DVNN
8066.5
–1590
HVOUT4
–6107.5
2305.5
DVDD
8066.5
–1958.5
HVOUT5
–5660.5
2305.5
DGND
7867
–2192
HVOUT6
–5213.5
2305.5
A4
7723
–2684
HVOUT7
–4776.5
2305.5
A3
7319
–2684
6913
–2684
HVOUT8
–4319.5
2305.5
A2
HVOUT9
–3872.5
2305.5
A1
6508.5
–2684
HVOUT10
–3425.5
2305.5
A0
6103.5
–2684
5698
–2684
HVOUT11
–2978.5
2305.5
EN
HVOUT12
–2513.5
2305.5
NC
5043.5
–2686
HVOUT13
–2084.5
2305.5
NC
4638.5
–2686
4233.5
–2686
HVOUT14
–1637.5
2305.5
NC
HVOUT15
–1190.5
2305.5
NC
3828.5
–2686
HVOUT16
–743.5
2305.5
NC
3423.5
–2686
3018.5
–2686
HVOUT17
–296.5
2305.5
NC
HVOUT18
150
2305.5
NC
2613.5
–2686
HVOUT19
597.5
2305.5
NC
2208.5
–2686
1803.5
–2686
HVOUT20
1044.5
2305.5
NC
HVOUT21
1491.5
2305.5
NC
1398.5
–2686
HVOUT22
1938.5
2305.5
NC
993.5
–2686
588.5
–2686
HVOUT23
2385.5
2305.5
NC
HVOUT24
2832.5
2305.5
NC
183.5
–2686
HVOUT25
3279.5
2305.5
NC
–221.5
–2686
–626.5
–2686
HVOUT26
3726.5
2305.5
NC
HVOUT27
4173.5
2305.5
NC
–1031.5
–2686
HVOUT28
4620.5
2305.5
NC
–1436.5
–2686
–2412
–2686
HVOUT29
5067.5
2305.5
NC
HVOUT30
5514.5
2305.5
NC
–2817
–2686
HVOUT31
5961.5
2305.5
NC
–3222
–2686
–3627
–2686
VPP
6659
2709
NC
BYP-VPP
7045
2709
NC
–4032
–2686
RSOURCE
7489
2709
NC
–4437
–2686
RSINK
7969
2709
NC
–4842
–2686
–5247
–2686
CATHODE
8366
2709
NC
ANODE
8366
2199
NC
–5652
–2686
–6052
–2686
–6462
–2686
AVNN
8047
425
NC
BYP-AVDD
8047
125.5
NC
DS20005827A-page 14
2017 Microchip Technology Inc.
HV257
TABLE 3-2:
PAD COORDINATES
(CONTINUED)
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name
X (µm)
Y (µm)
NC
–6867
–2686
NC
–7272
–2686
NC
–7677
–2686
NC
–8082
–2686
DVDD
–8373
–2250.5
DVNN
–8373
–1949
AGND
–8367
–1561
AVDD
–8387
–1143
AVNN
–8338.5
577.5
AGND
–8341
916.5
2017 Microchip Technology Inc.
DS20005827A-page 15
HV257
4.0
FUNCTIONAL DESCRIPTION
4.1
Power-up/Power-down Sequence
4.1.1
EXTERNAL DIODE PROTECTION
4.1.2
The device can be damaged due to improper
power-up/power-down sequence. To avoid this, please
follow
the
acceptable
power-up/power-down
sequences in Table 4-1 and Table 4-2 and add two
external diodes as shown in Figure 4-1. The first diode
is a high-voltage diode across VPP and VDD where the
anode of the diode is connected to VDD and the
cathode of the diode is connected to VPP. Any
low-current high-voltage diode such as a 1N4004 will
be adequate. The second diode is a Schottky diode
across VNN and DGND where the anode of the Schottky
diode is connected to VNN and the cathode is
connected to DGND. Any low-current Schottky diode
such as a 1N5817 will be sufficient.
VDD
RECOMMENDED
POWER-UP/POWER-DOWN
SEQUENCE
The HV257 needs all power supplies to be fully up and
all channels refreshed with VSIG = 0V to force all
high-voltage outputs to 0V. Before that time, the
high-voltage outputs may have temporary voltage
excursions above or below GND level, depending on
selected power-up sequence. To minimize the
excursions, the VDD and VNN power supplies should be
applied at the same time (or within a few
nanoseconds). In addition, all channels should be
continuously refreshed with VSIG = 0V, just before, and
while the VPP is ramping up. The suggested VPP ramp
up speed should be 10 milliseconds or longer and the
ramp-down should be 1 millisecond or longer.
VPP
1N4004 or similar
VNN
DGND
1N5817 or similar
FIGURE 4-1:
Diode Configuration.
TABLE 4-1:
ACCEPTABLE POWER-UP SEQUENCES
Option 2
Option 1
Step
1
2
3
4
Description
VPP
VNN
VDD
Inputs and Anode
TABLE 4-2:
Step
1
2
3
4
Step
4
VNN
VDD
VPP
Inputs and Anode
Step
1
2
3
4
Description
VDD and VNN
Inputs
VPP
Anode
ACCEPTABLE POWER-DOWN SEQUENCES
Option 2
Option 1
1
2
3
Description
Option 3
Description
Inputs and Anode
VDD
VNN
VPP
DS20005827A-page 16
Step
1
2
3
4
Description
Inputs and Anode
VPP
VDD
VNN
Option 3
Step
1
2
3
4
Description
Anode
VPP
Inputs
VNN and VDD
2017 Microchip Technology Inc.
HV257
A0 - A4
0
1
2
31
0
0
1
EN
300V
VPP
0V
6.5V
0V
VDD
0V
VNN
-5.5V
VSIG
0V
GND ± V offset x 72
HVOUT
FIGURE 4-2:
0V
Recommended Power-up/Power-down Timing.
VDD Before VNN
VNN Before VDD
VPP
VDD
0V
6.5V
0V
VPP
VDD
0V
VNN
HVOUT
FIGURE 4-3:
-5.5V
0V
-5.5V
VNN
0V
6.5V
0V
0V
-5.5V
HVOUT
6.5V
0V
HVOUT Level at Power-up.
2017 Microchip Technology Inc.
DS20005827A-page 17
HV257
4.2
RSINK/RSOURCE
The VDD_BYP, VDD_BYP and VNN_BYP pins are
internal high-impedance-current mirror gate nodes
brought out to maintain stable opamp biasing currents
in noisy power supply environments. When 0.1 µF/25V
bypass capacitors are added between VPP_BYP and
VPP, between VDD_BYP and VDD and between
VNN_BYP and VNN, they will force the high-impedance
gate nodes to follow the fluctuation of power lines. The
expected voltages at the VDD_BYP and VNN_BYP pins
are typically 1.5V from their respectful power supply.
The expected voltage at VPP_BYP is typically 3V below
VPP.
VPP
Current limit
BYP_VPP Cap
0.1µF/25V
BYP_VPP
Set by RSOURCE
BYP_VDD
To internal biasing
BYP_VDD Cap
0.1µF/25V
HVOpamp
HVOUT0
HVOpamp
HVOUT31
VDD
BYP_VNN
Set by RSINK
Current limit
BYP_VNN Cap
0.1µF/25V
VNN
FIGURE 4-4:
DS20005827A-page 18
Internal Reference Current Diagram.
2017 Microchip Technology Inc.
HV257
4.3
Ground Isolation
(AGND/DGND Isolation)
It is important that the AGND pin is connected to a
clean ground. The hold capacitors are internally
connected to the AGND, and any ground noise will
directly couple to the high-voltage outputs (with a gain
of 72). The analog and digital ground traces on the PCB
should be physically separated to reduce digital
switching noise, degrading the signal to noise
performance.
DGND
EN, A0 - A4
C2
C3
DVDD
DVNN
DAC
VSIG
External bypass caps
C1 = 0.1µF / 500V
C2, C3, C4, C5 = 0.1µF / 25V:
HVOUT
Sample
switch
LVOpamp
HVOpamp
1R
AVNN
C4
C5
AVDD
C_hold
10pF
C6
VPP
C_comp
71R
C_comp
C1
AGND1 (pins 89, 43)
Single star GND
FIGURE 4-5:
AGND2 (pin 39)
AGND/DGND Ground Isolation.
2017 Microchip Technology Inc.
DS20005827A-page 19
HV257
5.0
PACKAGE MARKING INFORMATION
5.1
Packaging Information
100-lead MQFP
Example
XXXXXXX e3
YYWWNNN
HV257FG e3
1712463
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005827A-page 20
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2017 Microchip Technology Inc.
HV257
100-Lead MQFP Package Outline (FG)
20.00x14.00mm body, 3.15mm height (max), 0.65mm pitch, 3.20mm footprint
D
D1
E
E1
Note 1
(Index Area
E1/4 x D1/4)
100
θ1
1
e
b
Top View
View B
A A2
L
L1
Seating
Plane
A1
Gauge
Plane
L2
Side View
Seating
Plane
θ
View B
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEH DPROGHGPDUNLGHQWL¿HU DQHPEHGGHGPHWDOPDUNHU RU
a printed indicator.
Symbol
A
MIN
A1
A2
b
2.50* 0.00 2.50 0.22
Dimension
NOM
2.70
(mm)
MAX 3.15 0.25 2.90 0.40
D
D1
E
E1
22.95*
19.80*
16.95*
13.80*
0.65
1.60 0.25
14.00
0.88
BSC
REF BSC
14.20*
1.03
23.20
20.00
17.20
23.45*
20.20*
17.45*
e
L
L1
L2
0.73
ș
ș
0O
5O
-
-
7O
16O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings are not to scale.
S
D
# DSPD 100MQFPFG V i F041309
2017 Microchip Technology Inc.
DS20005827A-page 21
HV257
NOTES:
DS20005827A-page 22
2017 Microchip Technology Inc.
HV257
APPENDIX A:
REVISION HISTORY
Revision A (September 2017)
• Converted Supertex Doc# DSFP-HV257
to Microchip DS20005827A
• Changed the part marking format
• Made minor text changes throughout the document
2017 Microchip Technology Inc.
DS20005827A-page 23
HV257
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
Device
-
Package
Options
X
-
Environmental
X
Media Type
Device:
HV257
=
32-Channel High-Voltage Sample-and-Hold
Amplifier Array
Package:
FG
=
100-lead MQFP
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
66/Tray for a K6 Package
DS20005827A-page 24
Example:
a) HV257FG-G:
32-Channel High-Voltage
Sample-and-Hold Amplifier Array,
100-lead MQFP, 66/Tray
2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2184-9
== ISO/TS 16949 ==
2017 Microchip Technology Inc.
DS20005827A-page 25
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Finland - Espoo
Tel: 358-9-4520-820
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
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Fax: 86-10-8528-2104
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Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
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Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20005827A-page 26
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-3326-8000
Fax: 86-21-3326-8021
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
France - Saint Cloud
Tel: 33-1-30-60-70-00
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Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Norway - Trondheim
Tel: 47-7289-7561
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Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
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Sweden - Gothenberg
Tel: 46-31-704-60-40
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Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
2017 Microchip Technology Inc.
11/07/16
