HV2601FG-G

HV2601/HV2701 Low-Charge Injection, 16-Channel, High-Voltage Analog Switch Features General Description • High-Voltage CMOS Technology for High Performance • 16-Channel High-Voltage Analog Switch • 3.3V Input Logic Level Compatible • 20 MHz Data Shift Clock Frequency • Very Low Quiescent Power Dissipation (–10 µA) • Low Parasitic Capacitance • DC to 50 MHz Small Signal Frequency Response • –60 dB Typical OFF-Isolation at 5.0 MHz • CMOS Logic Circuitry for Low Power • Excellent Noise Immunity • Cascadable Serial Data Register with Latches • Flexible Operating Supply Voltages • Integrated Bleed Resistors on the Outputs (HV2701 Only) The HV2601/HV2701 devices are low-charge injection, 16-channel, high-voltage analog switch integrated circuits (ICs). These devices are designed for use in applications requiring high-voltage switching controlled by low-voltage control signals, such as medical ultrasound imaging and other piezoelectric transducer drivers. The HV2701 has integrated bleed resistors which eliminate voltage build-up on capacitive loads, such as piezoelectric transducers. Applications The device is suitable for various combinations of highvoltage supplies, e.g., VPP/VNN: +40V/–160V, +100V/–100V, and +160V/–40V. • • • • Medical Ultrasound Imaging NDT Metal Flaw Detection Piezoelectric Transducer Drivers Optical MEMS Modules These ICs shift input data into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using High-Voltage CMOS technology, these devices combine high-voltage, bilateral DMOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals. Package Types† 42-Ball Bumped Die (Top View) 48-Lead LQFP (Top View) 48-Lead TQFP (Top View) 48 48 3 2 1 6 7 5 12 18 17 22 21 20 19 26 25 24 23 10 16 1 4 13 11 1 9 8 15 14 34 33 32 31 30 29 28 27 42 41 40 39 38 37 36 35 See Table 2-1 and Table 2-2 for pin information. † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative.  2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 1 HV2601/HV2701 Functional Block Diagram Latches D LE CLR Level Shifters Output Switches Bleed Resistors SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW14 D LE CLR SW15 DIN CLK 16-Bit Shift Register DOUT VDD GND LE CLR VNN VPP RGND HV2701 only Note: Bleed resistors and RGND apply to HV2701 only. DS20005391E-page 2  2015-2022 Microchip Technology Inc. and its subsidiaries HV2601/HV2701 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD Logic Supply ..................................................................................................................................... –0.5V to +7.0V VPP – VNN Differential Supply.................................................................................................................................. 220V VPP Positive Supply........................................................................................................................ –0.5V to VNN + 200V VNN Negative Supply............................................................................................................................... +0.5V to –200V Logic Input Voltage ......................................................................................................................... –0.5V to VDD + 0.3V Analog Signal Range ..................................................................................................................................... VNN to VPP Peak Analog Signal Current/Channel ...................................................................................................................... 3.0A Storage Temperature ............................................................................................................................–65°C to +150°C Power Dissipation 42-Ball Bumped Die .................................................................................................................. 1.5W Power Dissipation 48-Lead LQFP/TQFP ................................................................................................................ 1.0W † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (1, 2, 3) Symbol Parameter Value VDD Logic Power Supply Voltage 3.0V to 5.5V VPP Positive High-Voltage Supply +40V to VNN +200V VNN Negative High-Voltage Supply –40V to –160V VIH High-Level Input Voltage 0.9VDD to VDD VIL Low-Level Input Voltage 0V to 0.1 VDD Analog Signal Voltage Peak-to-Peak VNN + 10V to VPP – 10V Operating Free Air Temperature 0°C to 70°C VSIG TA Note 1: Power-up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2: VSIG must be within VNN and VPP or floating during power-up/down transition. 3: Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1 ms. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise noted. Parameter Small Signal Switch ON-Resistance Symbol RONS 0°C +25°C +70°C Min. Max. Min. Typ. Max. Min. Max. — 30 — 26 38 — 48 — 25 — 22 27 — 32 — 25 — 22 27 — 30 — 18 — 18 24 — 27 — 23 — 20 25 — 30 Units Conditions ISIG= 5.0 mA VPP= +40V V ISIG= 200 mA NN= –160V Ω ISIG= 5.0 mA VPP= +100V ISIG= 200 mA VNN= –100V ISIG= 5.0 mA VPP= +160V V ISIG= 200 mA NN= –40V — 22 — 16 25 — 27 Small Signal Switch ON-Resistance ∆RONS Matching — 20 — 5.0 20 — 20 % ISIG= 5.0 mA, VPP = +100V, VNN = –100V Large Signal Switch ON-Resistance — — — 15 — — — Ω VSIG = VPP – 10V, ISIG = 1.0A RONL  2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 3 HV2601/HV2701 DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Over recommended operating conditions unless otherwise noted. Parameter Symbol 0°C +25°C Min. Max. Min. Typ. +70°C Max. Min. Max. Units Conditions Value of Output Bleed Resistor (HV2701 Only) RINT — — 20 35 50 — — kΩ Output Switch to RGND IRINT = 0.5 mA Switch OFF Leakage per Switch ISOL — 5.0 — 1.0 10 — 15 µA VSIG = VPP – 10V and VNN + 10V (Note 1) — 300 — 100 300 — 300 mV — 500 — 100 500 — 500 mV HV2601:100 kΩ load HV2701: no load (Note 1) DC Offset Switch OFF DC Offset Switch ON VOS Quiescent VPP Supply Current IPPQ — — — 10 50 — — µA All switches OFF Quiescent VNN Supply Current INNQ — — — –10 –50 — — µA All switches OFF Quiescent VPP Supply Current IPPQ — — — 10 50 — — µA All switches ON, ISW = 5.0 mA Quiescent VNN Supply Current INNQ — — — –10 –50 — — µA All switches ON, ISW = 5.0 mA Switch Output Peak Current ISW — 3.0 — 3.0 2.0 — 2.0 A VSIG duty cycle < 0.1% Output Switching Frequency fSW — — — — 50 — — — 6.5 — — 7.0 — 8.0 — 4.0 — — 5.5 — 5.5 — 4.0 — — 5.0 — 5.5 VPP = +160V VNN = –40V — 6.5 — — 7.0 — 8.0 VPP = +40V VNN = –160V — 4.0 — — 5.0 — 5.5 — 4.0 — — 5.0 — 5.5 IDD — 4.0 — — 4.0 — 4.0 mA fCLK = 5.0 MHz, VDD = 5.0V Quiescent VDD Supply Current IDDQ — 10 — — 10 — 10 µA All logic inputs are static Data Out Source Current ISOR 0.45 — 0.45 0.70 — 0.40 — mA VOUT = VDD – 0.7V Data Out Sink Current ISINK 0.45 — 0.45 0.70 — 0.40 — mA VOUT = 0.7V Logic Input Capacitance CIN — 10 — — 10 — 10 pF Average VPP Supply Current Average VNN Supply Current Average VDD Supply Current IPP INN kHz Duty cycle = 50% VPP = +40V VNN = –160V mA mA VPP = +100V VNN = –100V VPP = +100V VNN = –100V VPP = +160V VNN = –40V All output switches are turning ON and OFF at 50 kHz with no load. All output switches are turning ON and OFF at 50 kHz with no load. Note 1: See Figure 3-1. DS20005391E-page 4  2015-2022 Microchip Technology Inc. and its subsidiaries HV2601/HV2701 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VDD=5.0V, tR = tF≤5.0 ns, 50% duty cycle, CLOAD = 20 pF, unless otherwise noted. Parameter Symbol Setup Time Before LE Rises tSD Time Width of LE tWLE Clock Delay Time to Data Out tDO 0°C +25°C +70°C Min. Max. Min. Typ. Max. Min. Max. 25 — 25 — — 25 — 56 12 50 15 55 21 7.0 — — 100 40 — — — — — 50 15 55 — — 56 12 78 30 — 21 7.0 — — 100 40 — — — 56 12 50 15 55 21 7.0 — — 100 40 — — — Time Width of CLR tWCLR Setup Time Data to Clock tSU Hold Time Data from Clock tH 2.0 — 2.0 — — 2.0 Clock Frequency fCLK — — 8.0 20 — — — — 8.0 20 Clock Rise and Fall Times tR,tF — 50 — — Turn ON Time tON — 5.0 — Turn OFF Time tOFF — 5.0 dv/dt — — — Maximum VSIG Slew Rate OFF Isolation Units Conditions ns ns ns VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V ns ns VDD = 3.0V VDD = 5.0V — ns VDD = 3.0 or 5.0V — — 8.0 20 MHz 50 — 50 ns — 5.0 — 5.0 — — 5.0 — 5.0 20 20 20 — — — — — — 20 20 20 — — — 20 20 20 –30 — –30 –33 — –30 — KCR –58 –60 — — –58 –60 — –70 — — –58 –60 — — dB KO VDD = 3.0V VDD = 5.0V VSIG = VPP – 10V, RLOAD = 10 kΩ (Note 1) VSIG = VPP – 10V, µs RLOAD = 10 kΩ (Note 1) VPP = +40V, VNN = –160V V/ns VPP = +100V, VNN = –100V VPP = +160V, VNN = –40V µs dB f = 5.0 MHz, 1.0 kΩ//15 pF load (Note 1) f = 5.0 MHz, 50Ω load (Note 1) f = 5.0 MHz, 50Ω load (Note 1) Switch Crosstalk Output Switch Isolation Diode Current OFF Capacitance SW to GND IID — 300 — — 300 — 300 mA 300 ns pulse width, 2.0% duty cycle (Note 1) CSG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0 MHz ON Capacitance SW to GND CSG(ON) 25 50 25 38 50 25 50 pF 0V, f = 1.0 MHz — — — — 150 — — — — — — 150 — — — — — — 150 — — — — — 820 — — — — — — 600 — — — — — — 350 — — — +VSPK Output Voltage Spike Charge Injection -VSPK +VSPK -VSPK +VSPK -VSPK QC VPP = +40V, VNN = –160V, RLOAD = 50Ω (Note 1) mV VPP = +100V, VNN = –100V, RLOAD = 50Ω (Note 1) VPP = +160V, VNN = –40V, RLOAD = 50Ω (Note 1) pC VPP = +40V, VNN = –160V, VSIG = 0V (Note 1) VPP = +100V, VNN = –100V, VSIG = 0V (Note 1) VPP = +160V, VNN = –40V, VSIG = 0V (Note 1) Note 1: See Figure 3-1.  2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 5 HV2601/HV2701 2.0 PIN DESCRIPTION The locations of the pads/balls are listed in Package Types†. TABLE 2-1: Pin # PIN DESCRIPTION: 42-BALL BUMPED DIE PACKAGE HV2601 HV2701 Description 1 NC RGND 2 VPP VPP Positive supply voltage No connect/Ground for bleed resistor 3 VNN VNN Negative supply voltage 4 DOUT DOUT Data out logic output 5 CLR CLR Latch clear logic input 6 CLK CLK Clock logic input for shift register Ground 7 GND GND 8 SW15A SW15A 9 SW15B SW15B 10 LE LE Latch-enable logic input, low active Logic supply voltage Analog switch 15 terminal A Analog switch 15 terminal B 11 VDD VDD 12 SW0A SW0A Analog switch 0 terminal A 13 SW0B SW0B Analog switch 0 terminal B 14 SW14A SW14A Analog switch 14 terminal A 15 SW14B SW14B 16 DIN DIN 17 SW1A SW1A Analog switch 1 terminal A 18 SW1B SW1B Analog switch 1 terminal B Analog switch 14 terminal B Data in logic input 19 SW13A SW13A Analog switch 13 terminal A 20 SW13B SW13B Analog switch 13 terminal B 21 SW2A SW2A Analog switch 2 terminal A 22 SW2B SW2B Analog switch 2 terminal B 23 SW12A SW12A Analog switch 12 terminal A 24 SW12B SW12B Analog switch 12 terminal B 25 SW3A SW3A Analog switch 3 terminal A 26 SW3B SW3B Analog switch 3 terminal B 27 SW11A SW11A Analog switch 11 terminal A 28 SW11B SW11B Analog switch 11 terminal B 29 SW9B SW9B Analog switch 9 terminal B 30 SW8B SW8B Analog switch 8 terminal B 31 SW7A SW7A Analog switch 7 terminal A 32 SW6A SW6A Analog switch 6 terminal A 33 SW4A SW4A Analog switch 4 terminal A 34 SW4B SW4B Analog switch 4 terminal B 35 SW10B SW10B Analog switch 10 terminal B 36 SW10A SW10A Analog switch 10 terminal A 37 SW9A SW9A Analog switch 9 terminal A 38 SW8A SW8A Analog switch 8 terminal A 39 SW7B SW7B Analog switch 7 terminal B 40 SW6B SW6B Analog switch 6 terminal B 41 SW5B SW5B Analog switch 5 terminal B 42 SW5A SW5A Analog switch 5 terminal A DS20005391E-page 6  2015-2022 Microchip Technology Inc. and its subsidiaries HV2601/HV2701 TABLE 2-2: PIN DESCRIPTION: 48-LEAD LQFP/TQFP Pin # HV2601 HV2701 Description 1 NC NC No connect No connect 2 NC NC 3 SW4B SW4B Analog switch 4 terminal B 4 SW4A SW4A Analog switch 4 terminal A 5 SW3B SW3B Analog switch 3 terminal B 6 SW3A SW3A Analog switch 3 terminal A 7 SW2B SW2B Analog switch 2 terminal B 8 SW2A SW2A Analog switch 2 terminal A 9 SW1B SW1B Analog switch 1 terminal B 10 SW1A SW1A Analog switch 1 terminal A 11 SW0B SW0B Analog switch 0 terminal B 12 SW0A SW0A 13 VNN VNN Negative supply voltage Analog switch 0 terminal A 14 NC NC No connect 15 VPP VPP Positive supply voltage 16 NC NC 17 GND GND Ground No connect 18 VDD VDD Logic supply voltage 19 DIN DIN Data in logic input 20 CLK CLK 21 LE LE Clock logic input for shift register Latch-enable logic input, low active 22 CLR CLR Latch clear logic input 23 DOUT DOUT Data out logic output 24 NC RGND No connect/Ground for bleed resistor 25 SW15B SW15B Analog switch 15 terminal B 26 SW15A SW15A Analog switch 15 terminal A 27 SW14B SW14B Analog switch 14 terminal B 28 SW14A SW14A Analog switch 14 terminal A 29 SW13B SW13B Analog switch 13 terminal B 30 SW13A SW13A Analog switch 13 terminal A 31 SW12B SW12B Analog switch 12 terminal B 32 SW12A SW12A Analog switch 12 terminal A 33 SW11B SW11B Analog switch 11 terminal B 34 SW11A SW11A Analog switch 11 terminal A 35 NC NC No connect No connect 36 NC NC 37 SW10B SW10B 38 SW10A SW10A Analog switch 10 terminal A 39 SW9B SW9B Analog switch 9 terminal B 40 SW9A SW9A Analog switch 9 terminal A 41 SW8B SW8B Analog switch 8 terminal B 42 SW8A SW8A Analog switch 8 terminal A 43 SW7B SW7B Analog switch 7 terminal B 44 SW7A SW7A Analog switch 7 terminal A  2015-2022 Microchip Technology Inc. and its subsidiaries Analog switch 10 terminal B DS20005391E-page 7 HV2601/HV2701 TABLE 2-2: PIN DESCRIPTION: 48-LEAD LQFP/TQFP (CONTINUED) Pin # HV2601 HV2701 45 SW6B SW6B Analog switch 6 terminal B 46 SW6A SW6A Analog switch 6 terminal A 47 SW5B SW5B Analog switch 5 terminal B 48 SW5A SW5A Analog switch 5 terminal A DS20005391E-page 8 Description  2015-2022 Microchip Technology Inc. and its subsidiaries HV2601/HV2701 3.0 DETAILED DESCRIPTION 3.1 Application Information VPP -10V VPP -10V ISOL 10kΩ RLOAD VOUT VOUT Open RLOAD Open (HV2601 only) RGND VPP VPP VDD VNN VNN GND 5V RGND RGND VPP VPP VDD VNN VNN GND Switch Off Leakage per Switch 5V VPP VPP VDD VNN VNN GND 5V TON/TOFF Test Circuit DC Offset Switch ON/OFF VIN = 10VP-P @5MHz VIN = 10VP-P @5MHz VSIG IID VOUT VNN RLOAD NC 50Ω 50Ω RGND RGND RGND VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VPP VDD VNN VNN GND VPP VDD VNN VNN GND VOUT KCR = 20Log VIN Output Switch Isolation Diode Current OFF Isolation 5V VOUT VIN Switch Crosstalk +VSPK ΔVOUT VOUT VOUT –VSPK 1000pF RLOAD VSIG 50Ω RGND RGND 1kΩ VPP VPP VDD VNN VNN GND Q = 1000pF x ΔVOUT Charge Injection FIGURE 3-1: 5V VPP 5V VPP VPP VDD VNN VNN GND 5V Output Voltage Spike Test Circuits.  2015-2022 Microchip Technology Inc. and its subsidiaries DS20005391E-page 9 HV2601/HV2701 TABLE 3-1: D0 D1 L LOGIC FUNCTION TABLE ... D7 D8 D15 LE CLR SW0 SW1 — — — — L L OFF H — — L — — — L L — — — L L — — H — — — L — — — — L — — — — — L L — — — L — — L L — — — H — — L L — — — — — L — L L — — — — — H — L L — — — — — — L L — — — — — — L L — — — — — L L — — — — — L L — — — — — — — — — L L L — — — — OFF — — — — H L L — — — — ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF ... ... ... ... SW7 SW8 ... SW15 — — — — ON — — — — — OFF — — — L — ON — — — L — — — — — — — — — — OFF — — ON — — OFF — — ON — — — — — — — — — — — — — — — ... ... — — Note 1: The 16 switches operate independently. 2: Serial data is clocked in on the L to H transition of the CLK. 3: All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the shift registers data flow through the latch. 4: DOUT is high when data in the shift register 15 are high. 5: Shift registers clocking has no effect on the switch states if LE is high. 6: The CLR clear input overrides all other inputs. DN+1 DN DATA IN DIN 50% LE 50% DN-1 50% 50% tWLE tSD CLOCK CLK 50% tSU tDO DATA OUT DOUT VOUT (typ) FIGURE 3-2: DS20005391E-page 10 th DO 50% tOFF OFF tON 90% 10% ON CLR 50% 50% tWCL 50% Logic Timing Waveforms.  2015-2022 Microchip Technology Inc. and its subsidiaries HV2601/HV2701 4.0 PACKAGING INFORMATION† 4.1 Package Marking Information † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative. 42-Ball Bumped Die Example HV2601 e3 BD^^ 2126256 XXXXXXX e3 XXXXX^^ YYWWNNN 48-Lead LQFP XXXXXX XXXXXX e3 ^^YYWW NNN 48-Lead TQFP YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: HV2701 e3 BD^^ 2126256 Example Example HV 2601FG e3 ^^2126 256 HV 2701FG e3 ^^2126 256 Example Example HV 2601TQ 2126256 XXXXXX XXXXXX Example HV 2701TQ 2126256 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. 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