HV265
4-Channel, 205V, High-Voltage Amplifiers Array
Features
General Description
•
•
•
•
•
•
•
•
•
The HV265 device is a 4-channel high-voltage
operational amplifier array with an optional internal
feedback resistor network.
Four Independent High Voltage Amplifiers
Up to +205 V Output Voltage
Gain of 82 V/V with Internal Feedback Resistors
0.02 V/s Minimum Output Slew Rate
Less than 10 ms Settling Time
Less than 1 k Output Impedance
Up to 200 pF Output Load
30 kHz Gain Bandwidth Product
24-lead TSSOP Package
Application
• MEMS Driver
The amplifier array IC operates on a 225 V high-voltage
supply and a 5 V low-voltage supply. Each channel has
its independent input and output ports. When the
internal feedback resistor network is used, the closedloop gain is set to 82 V/V. High value SiCr resistors are
used for internal feedback networks to minimize the
power consumption. The input accepts voltage in the
range of 0.05V and 2.5V.
The output impedance of the amplifier is less than 1 k
and the output can drive a capacitive load up to 200 pF.
The amplifier is designed to have good temperature
stability and low output drift.
Typical Application Circuit
2019 Microchip Technology Inc.
DS20006234A-page 1
HV265
Package Types (Top View)
HV265
24-Lead TSSOP
See Table 2-1.
Block Diagram
DS20006234A-page 2
2019 Microchip Technology Inc.
HV265
NOTES:
2019 Microchip Technology Inc.
DS20006234A-page 3
HV265
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Low supply voltage (VDD)............................................................................................................................. -0.5V to 6.5V
High supply voltage (VPP) ........................................................................................................................... -0.5V to 250V
Input analog voltage (VIN) ............................................................................................................................ - 0.3V to VDD
Maximum junction temperature ............................................................................................................................ +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
ESD Rating low voltage pins .................................................................2 kV HBM, 500 V CDM, 750 V CDM corner lead
ESD Rating high voltage pins............................................................. 500 V HBM, 500 V CDM, 750 V CDM corner lead
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 1-1:
OPERATING SUPPLY VOLTAGES
Electrical Specifications: Unless otherwise specified: TA = +25°C. Boldface specifications apply over the TA range
of -40 to +85°C.
Parameter
Sym.
Min.
Typ.
Max.
Units
High Voltage Supply
VPP
50
—
225
V
Low Voltage Supply
VDD
4.5
5.0
5.5
V
Note 1:
Conditions
Note 1
Specification is obtained by characterization and is not 100% tested.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: unless otherwise specified, VDD = 5.0V, VPP = 225V, TA = +25°C.
Parameter
Input Ground Range
Sym.
Min.
Typ.
Max.
Units
RGND
0
0
VDD
V
Conditions
VIN
0
—
3.3
V
Quiescent VPP Supply Current
IPPQ
—
300
500
µA
VIN = 0 or 5V
Quiescent VDD Supply Current
IDDQ
Input Analog Voltage
VPP Supply Current
IPP
VDD Supply Current
IDD
HVOUT Output Voltage Range
HVOUT Sink Current
HVOUT Source Current
HVOUT High Level Output
HVOUT Input DC Offset
HVOUT Drift Over Time
(Room Temperature)
HVOUT Temperature Coefficient
(Drift Over Temperature)
—
3
5
mA
VIN= 0 or 5V
—
—
500
µA
VIN= 2VP-P 100 Hz sine,
CL = 200 pF
—
—
5
mA
VIN= 2VP-P 100 Hz sine,
CL = 200 pF
HVOUT
1.85
V
CL = 200 pF
ISINK
3
VPP - 10
mA
CL = 200 pF
ISOURCE
3
mA
VOH
204.8
V
HVOS
±16
CL = 200 pF
CL = 200 pF, VIN= 2.7V
mV
Note 3 CL = 200 pF
Drift
±30
mV
Note 3 CL = 200 pF,
VIN= 2.5V
Temp.
±115
mV
Note 3 CL = 200 pF,
VIN= 2.5V
TJ = -40°C to 85°C
Note 1: Recommended Operating Conditions: VIN=0V, VDD=5.0V, VPP=+225V unless noted. Tj=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
DS20006234A-page 4
2019 Microchip Technology Inc.
HV265
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: unless otherwise specified, VDD = 5.0V, VPP = 225V, TA = +25°C.
Parameter
HVOUT Output Impedance
Gain Bandwidth Product
Sym.
Min.
Typ.
ZOUT
GBWP
30
Slew Rate
(HVOUT from 10% to 90% and
from 90% to 10%)
SR
0.02
Settling Time
(Within 1% of final HVOUT)
tST
-
Max.
Units
Conditions
1000
Note 3 VIN= 1.25 VDC
Test Frequency = 100 Hz
CL = 200 pF
kHz
Note 3 CL = 200 pF
-
V/s
CL = 200 pF
10
ms
Note 3 CL = 200 pF,
VIN= 0 to 2.4 V
Feedback Impedance Rf + Ri
RFB
4.9
7.0
-
M
Note 2
Closed Loop Gain (dVo/dVin)
(Internal Feedback Resistor
Network)
AV
75.4
82
88.4
V/V
CL = 200 pF
HVOUT Capacitive Load
CL
0
200
pF
Note 2
Output Referred Noise
VN
10
mVRMS
Note 3 Noise from 1 Hz
to 10 kHz.
VDD Power Supply Rejection
PSRR1
30
dB
Note 3 1 kHz
VPP Power Supply Rejection
PSRR2
50
dB
Note 3 1 kHz
Note 3 VIN= 0 to 2.5V
100 Hz sine, CL = 200 pF
Note 1: Recommended Operating Conditions: VIN=0V, VDD=5.0V, VPP=+225V unless noted. Tj=25°C
Crosstalk Rejection
Xtalk
80
dB
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
2019 Microchip Technology Inc.
DS20006234A-page 5
HV265
TEMPERATURE SPECIFICATIONS
Electrical Specifications: unless otherwise specified, VDD = 5.0V, VPP = 225V
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
TJ
-40
—
+85
°C
TJ(MAX)
—
—
+125
°C
TA
-65
—
+150
°C
JA
—
87
—
°C/W
Package Thermal Resistances
Thermal Resistance, 24L-TSSOP
DS20006234A-page 6
2019 Microchip Technology Inc.
HV265
1.1
Note:
Typical Performance Curves
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 1-1:
Typical Small-Signal Pulse
Response (VIN=0.9~1.1V pulse 100 Hz.
CL=200 pF).
FIGURE 1-4:
Typical Fall Time (VIN =
0~2V Pulse 100 Hz. CL=200 pF).
Typical Bode Plot
Vin = 0.1Vrms + 1.25VDC, CL = 220pF
45
40
35
B
d30
in
e
d
tu
i
gn
a
M25
20
15
10
100
1000
10000
100000
1000000
Frequency in Hz
FIGURE 1-2:
Typical Large-Signal Pulse
Response (VIN = 0~2V pulse 100 Hz.
CL=200 pF).
FIGURE 1-5:
Typical Bode Plot of
Small Signal Input (VIN=100 mVp-p with
1.25 VDC).
Crosstalk Rejection
HVOUT = Full Swing, CL = 220pF
105
100
95
B 90
d
n
i
n
o
it
ce
je 85
R
lk
at
ss
o
r
C 80
75
70
65
10
100
1000
10000
Frequency in Hz
FIGURE 1-3:
Typical Rise Time (VIN =
0~2V Pulse 100 Hz. CL=200 pF).
2019 Microchip Technology Inc.
FIGURE 1-6:
vs Frequency.
Typical Crosstalk Rejection
DS20006234A-page 7
HV265
Note:
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
Typical HVOUT Drift over Time at 25 °C
(VIN=2.5V)
30
20
10
Drift (mV)
0
-10
-20
-30
-40
0
1
2
3
4
5
Time Duration (Hour)
FIGURE 1-7:
Typical Crosstalk Rejection
in Time Domain (Source VIN = 0~2.5V Sine).
FIGURE 1-10:
Typical HVOUT Drift Over
Time. VPP=225V,VDD=5.0V,VIN=2.5V @TA=25°C.
Typical Distribution of HVOUT Input Offset Voltage (HVOS) at 25 °C
35
30
25
Count
20
15
10
5
0
-15 -14 -13 -12 -11 -10
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
HVOUT Input Offset in mV
FIGURE 1-8:
TA = 25°C.
Distribution of Input Offset at
FIGURE 1-11:
Typical Power Supply
Rejection from VDD vs Frequency.
HVOUT drift over temperature, Vin = 2.5V
with respect to 20 degree C
250
200
150
100
Voltage in mV
50
0
-50
-100
-150
-200
-250
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature in degree C
FIGURE 1-9:
Distribution of Typical
HVOUT Drift Over Temperature (VIN = 2.5VDC in
Reference to TA = 20°C.
DS20006234A-page 8
FIGURE 1-12:
Typical Power Supply
Rejection from VPP vs Frequency.
2019 Microchip Technology Inc.
HV265
NOTES:
2019 Microchip Technology Inc.
DS20006234A-page 9
HV265
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number
PIN FUNCTION TABLE
Symbol
Description
1
VIN1
2
RGND1
Resistor Ground 1. Typically grounded.
3
GND
Low Voltage Ground
4
VIN2
Amplifier Input 2
5
RGND2
Resistor Ground 2. Typically grounded.
6
VDD
Positive Low Voltage Supply
7
GND
Low Voltage Ground
8
VIN3
Amplifier Input 3
9
RGND3
Resistor Ground 3. Typically grounded.
10
GND
Low Voltage Ground
11
VIN4
Amplifier Input 4
12
RGND4
Resistor Ground 4. Typically grounded.
13
NC
No Connection
14
FB4
Feedback Input 4
15
HVOUT4
High Voltage Output 4
16
FB3
Feedback Input 3
17
HVOUT3
High Voltage Output 3
18
HVGND
High Voltage Ground
19
VPP
Positive High Voltage Supply
20
FB2
Feedback Input 2
21
HVOUT2
High Voltage Output 2
22
FB1
Feedback Input 1
23
HVOUT1
High Voltage Output 1
24
NC
No Connection
DS20006234A-page 10
Amplifier Input 1
2019 Microchip Technology Inc.
HV265
3.0
DEVICE DESCRIPTION
3.1
Power-On/Power-Off Sequence
The device can be damaged by an improper powerup/down sequence. The acceptable power-on/off
sequences are shown in Table 3-1 and Table 3-2. The
TABLE 3-1:
user may add an external diode across VPP and VDD
for additional protection. The anode of the diode is
connected to VDD and the cathode is connected to VPP.
Any low-current high-voltage diode such as a 1N4004
is adequate.
ACCEPTABLE POWER-ON SEQUENCES
Option 1
Option 2
Steps
Description
Steps
Description
1
VDD
1
VDD
2
VPP
2
Inputs
3
Inputs
3
VPP
TABLE 3-2:
ACCEPTABLE POWER-OFF SEQUENCES
Option 1
Option 2
Steps
Description
Steps
1
Inputs
1
VPP
2
VPP
2
Inputs
3
VDD
3
VDD
2019 Microchip Technology Inc.
Description
DS20006234A-page 11
HV265
NOTES:
DS20006234A-page 12
2019 Microchip Technology Inc.
HV265
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
24-Lead TSSOP
Example
XXXXXXXX
e3
XXXXNNN
YYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
HV265
QEX e3
l 123
1910
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
2019 Microchip Technology Inc.
DS20006234A-page 13
HV265
24-Lead Thin Shrink Small Outline Package (QE) - 4.40 mm Body [TSSOP]
Supertex Legacy & Micrel Legacy Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E1
E
N
(DATUM A)
(DATUM B)
2X N2 TIPS
0.20
1 2
24X b
0.10
e
C
C A-B D
TOP VIEW
A
0.05 C
C
SEATING
PLANE
A1
A A2
24X
SIDE VIEW
0.10 C
A
SEE DETAIL B
SHEET 2
VIEW A-A
Microchip Technology Drawing C04-284A Sheet 1 of 2
DS20006234A-page 14
2019 Microchip Technology Inc.
HV265
24-Lead Thin Shrink Small Outline Package (QE) - 4.40 mm Body [TSSOP]
Supertex Legacy & Micrel Legacy Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
T
L
(L1)
DETAIL B
Units
Dimension Limits
Number of Leads
N
e
Lead Pitch
Overall Height
A
Standoff
A1
A2
Molded Package Thickness
Foot Length
L
Footprint
L1
Foot Angle
T
Overall Width
E
Overall Length
D
Molded Package Width
E1
b
Lead Width
D
Mold Draft Angle Top
MIN
0.85
0.05
0.80
0.45
0°
7.70
4.30
0.19
MILLIMETERS
NOM
24
0.65 BSC
0.10
1.00
0.60
1.00 REF
4°
6.40 BSC
7.80
4.40
12° REF
MAX
1.20
0.15
1.15
0.75
8°
7.90
4.50
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-284A Sheet 2 of 2
2019 Microchip Technology Inc.
DS20006234A-page 15
HV265
24-Lead Thin Shrink Small Outline Package (QE) - 4.40 mm Body [TSSOP]
Supertex Legacy & Micrel Legacy Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
24
C
SILK SCREEN
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X24)
X1
Contact Pad Length (X24)
Y1
Contact Pad to Center Pad (X20)
G1
MIN
MILLIMETERS
NOM
0.65 BSC
5.80
MAX
0.45
1.50
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2284A
DS20006234A-page 16
2019 Microchip Technology Inc.
HV265
APPENDIX A:
REVISION HISTORY
Revision A (July 2019)
• Original release of this document.
2019 Microchip Technology Inc.
DS20006234A-page 17
HV265
NOTES:
DS20006234A-page 18
2019 Microchip Technology Inc.
HV265
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
-X
PART NO.
Device
/XX
Temperature
Range
Package
Device:
HV265: 4-Channel, 205V, High-Voltage Amplifiers Array
Temperature
Range:
I
Package:
QE =
=
Example:
a)
HV265-I/QE:
4-Channel 205V High-Voltage
Amplifier Array, -40°C to +85°C,
24LD TSSOP package
-40°C to +85°C
24LD TSSOP 4.4mm
2019 Microchip Technology Inc.
DS20006234A-page 19
HV265
NOTES:
DS20006234A-page 20
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
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suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
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Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
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TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
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CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
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ZENA are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated in
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The Adaptec logo, Frequency on Demand, Silicon Storage
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GestIC is a registered trademark of Microchip Technology Germany
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All other trademarks mentioned herein are property of their
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© 2019, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
ISBN: 978-1-5224-4776-4
DS20006234A-page 21
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Tel: 66-2-694-1351
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006234A-page 22
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
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05/14/19
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