HV2705FG-G-M931

HV2605/HV2705 16-Channel Low Harmonic Distortion High-Voltage Analog Switches Features Description • 16-channel High-voltage Analog Switch • Low Harmonic Distortion • Integrated Bleed Resistors on the Outputs for HV2705 • 3.3V Input Logic Level Compatible • –60 dB typical OFF-isolation at 5 MHz • 20 MHz Data Shift Clock Frequency • 10 µA Low-quiescent Power Dissipation • Low Parasitic Capacitance • DC to 50 MHz Small-signal Frequency Response • CMOS logic Circuitry for Low Power • Cascadable Serial Data Register with Latches • Flexible Operating Supply Voltages The HV2605 and HV2705 are 16-channel low harmonic distortion high-voltage analog switch integrated circuits (ICs). These devices are designed for applications requiring high-voltage switching controlled by low-voltage control signals, such as medical ultrasound imaging and other piezoelectric transducer drivers. The HV2705 has integrated bleed resistors which eliminate voltage build-up on capacitive loads such as piezoelectric transducers. These ICs shift input data into a 16-bit Shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. This device combines high-voltage, bilateral DMOS switches and low-power CMOS logic to provide efficient control of high-voltage analog signals. Applications • • • • The device is suitable for various combinations of highvoltage supplies, e.g., VPP/VNN: +40V/–160V, +100V/–100V and +160V/–40V. Medical Ultrasound Imaging Non-destructive Metal Flaw Detection Piezoelectric Transducer Drivers Optical MEMS Modules Package Types† 48-lead LQFP (Top view) 48-lead TQFP (Top view) 42-Ball Bumped Die (Top view) 48 48 3 2 1 6 7 5 12 18 17 22 21 20 19 26 25 24 23 10 16 1 4 13 11 1 9 8 15 14 34 33 32 31 30 29 28 27 42 41 40 39 38 37 36 35 See Table 2-1 and Table 2-2 for pin information. † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative.  2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 1 HV2605/HV2705 Functional Block Diagram Latches D LE CLR Level Shifters Output Switches Bleed Resistors SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW14 D LE CLR SW15 DIN CLK 16-Bit Shift Register DOUT VDD GND LE CLR VNN VPP RGND HV2705 only DS20005498C-page 2  2017-2022 Microchip Technology Inc. and its subsidiaries HV2605/HV2705 1.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS† Logic Supply, VDD ..................................................................................................................................... –0.5V to +7V Differential Supply, VPP–VNN ................................................................................................................................. 220V Positive Supply, VPP ...................................................................................................................... –0.5V to VNN +200V Negative Supply, VNN ............................................................................................................................. +0.5V to –200V Logic Input Voltage ......................................................................................................................... –0.5V to VDD +0.3V Analog Signal Range ..................................................................................................................................... VNN to VPP Peak Analog Signal Current/Channel ........................................................................................................................ 3A Storage Temperature, TS ....................................................................................................................... –65°C to 150°C Power Dissipation: 42-Ball Bumped Die .................................................................................................................................... 1.5W 48-Lead TQFP/LQFP....................................................................................................................................... 1W † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Sym. Min. Typ. Max. Unit Conditions Logic Power Supply Voltage VDD 3 — 5.5 V Note 1, Note 3 Positive High-voltage Supply VPP 40 — VNN+200V V Note 1, Note 3 Negative High-voltage Supply VNN –40 — –160 V Note 1, Note 3 High-level Input Voltage VIH 0.9 VDD — VDD V Low-level Input Voltage Analog Signal Voltage Peak-to-Peak Note 1: 2: 3: VIL 0 — 0.1 VDD V VSIG VNN +10V — VPP–10V V Note 2 Power-up/power-down sequence is arbitrary except GND must be powered up first and powered down last. VSIG must be within VNN VSIGVPP or floating during power-up/power-down transition. Rise and fall times of power supplies VDD, VPP and VNN should not be less than 1 millisecond.  2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 3 HV2605/HV2705 DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Min. Max. Min. Typ. Max. Min. Max. Unit Conditions — 30 — 26 38 — 48 Ω — 25 — 22 27 — 32 Ω VPP = +40V ISIG = 200 mA VNN = –160V — 25 — 22 27 — 30 Ω ISIG = 5 mA — 18 — 18 24 — 27 Ω VPP = +100V ISIG = 200 mA VNN= –100V — 23 — 20 25 — 30 Ω ISIG = 5 mA — 22 — 16 25 — 27 Ω ∆RONS — 20 — 5 20 — 20 % ISIG = 5 mA, VPP = +100V, VNN = –100V Large Signal Switch ON-resistance RONL — — — 15 — — — Ω VSIG = VPP–10V, ISIG = 1A Output Bleed Resistor (HV2705 only) RINT — — 20 35 50 — — kΩ Output Switch to RGND IRINT = 0.5 mA Switch OFF Leakage per Switch ISOL — 5 — 1 10 — 15 µA VSIG = VPP–10V and VNN+10V (See Section 3.1 “Test Circuits”.) — 300 — 100 300 — 300 — 500 — 100 500 — 500 mV HV2605:100 kΩ load HV2705: No load mV (See Section 3.1 “Test Circuits”.) Small Signal Switch ON-resistance Small Signal Switch ON-resistance Matching RONS DC Offset Switch OFF DC Offset Switch ON VOS ISIG = 5 mA VPP = +160V ISIG = 200 mA VNN = –40V Quiescent VPP Supply Current IPPQ — — — 10 50 — — µA All switches off Quiescent VNN Supply Current INNQ — — — –10 –50 — — µA All switches off Quiescent VPP Supply Current IPPQ — — — 10 50 — — µA All switches on, ISW = 5 mA Quiescent VNN Supply Current INNQ — — — –10 –50 — — µA All switches on, ISW = 5 mA Switch Output Peak Current ISW — 3 — 3 2 — 2 A VSIG duty cycle < 0.1% Output Switching Frequency fSW — — — — 50 — — kHz Duty cycle = 50% — 6.5 — — 7 — 8 mA VPP = +40V VNN = –160V — 4 — — 5.5 — 5.5 mA VPP = +100V VNN = –100V — 4 — — 5 — 5.5 mA VPP = +160V VNN = –40V — 6.5 — — 7 — 8 mA VPP = +40V VNN = –160V — 4 — — 5 — 5.5 mA VPP = +100V VNN = –100V — 4 — — 5 — 5.5 mA VPP = +160V VNN = –40V IDD — 4 — — 4 — 4 mA fCLK = 5 MHz, VDD = 5V IDDQ — 10 — — 10 — 10 µA Average VPP Supply Current Average VNN Supply Current Average VDD Supply Current Quiescent VDD Supply Current DS20005498C-page 4 IPP INN 50 kHz output switching frequency with no load 50 kHz output switching frequency with no load All logic inputs are static.  2017-2022 Microchip Technology Inc. and its subsidiaries HV2605/HV2705 DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Over recommended operating conditions unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Min. Max. Min. Typ. Max. Min. Max. Unit Conditions Data Out Source Current ISOR 0.45 — 0.45 0.7 — 0.4 — mA VOUT = VDD–0.7V Data Out Sink Current ISINK 0.45 — 0.45 0.7 — 0.4 — mA VOUT = 0.7V CIN — 10 — — 10 — 10 pF Logic Input Capacitance AC ELECTRICAL CHARACTERISTICS Electrical Specifications: VDD = 5V, tr = tf ≤ 5 ns, 50% duty cycle and CLOAD = 20 pF unless otherwise noted. Parameter Sym. Set-up Time before Latch Enable Rises tSD Time Width of LE Clock Delay Time to Data Out Time Width of CLR tWLE tDO tWCLR Set-up Time Data to Clock tSU Hold Time Data from Clock tH Clock Frequency fCLK Clock Rise and Fall Times tr, tf Turn ON Time Turn OFF Time Maximum VSIG Slew Rate OFF Isolation Switch Crosstalk TON TOFF dv/dt 0°C 25°C 70°C Min. Max. Min. Typ. Max. Min. Max. Unit 25 — 25 — — 25 — ns 56 — — 56 — 56 — ns VDD = 3V 12 — — 12 — 12 — ns VDD = 5V 50 100 50 78 100 50 100 ns VDD = 3V 15 40 15 30 40 15 40 ns VDD = 5V 55 — 55 — — 55 — ns 21 — — 21 — 21 — ns VDD = 3V 7 — — 7 — 7 — ns VDD = 5V 2 — 2 — — 2 — ns VDD = 3V or 5V — 10 — — 10 — 10 MHz VDD = 3V — 20 — — 20 — 20 — 50 — — 50 — 50 MHz VDD = 5V ns — 5 — — 5 — 5 µs VSIG = VPP–10V, RLOAD = 10 kΩ (See Section 3.1 “Test Circuits”.) VSIG = VPP–10V, RLOAD = 10 kΩ (See Section 3.1 “Test Circuits”.) — 5 — — 5 — 5 µs — 20 — — 20 — 20 V/ns VPP = +40V, VNN = –160V — 20 — — 20 — 20 V/ns VPP = +100V, VNN = –100V — 20 — — 20 — 20 V/ns VPP = +160V, VNN = –40V –30 — –30 –33 — –30 — dB f = 5 MHz, 1 kΩ//15 pF load (See Section 3.1 “Test Circuits”.) –58 — –58 — — –58 — dB f = 5 MHz, 50Ω load (See Section 3.1 “Test Circuits”.) –60 — –60 –70 — –60 — dB f = 5 MHz, 50Ω load (See Section 3.1 “Test Circuits”.) KO KCR Conditions  2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 5 HV2605/HV2705 AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: VDD = 5V, tr = tf ≤ 5 ns, 50% duty cycle and CLOAD = 20 pF unless otherwise noted. Parameter Sym. 0°C 25°C 70°C Min. Max. Min. Typ. Max. Min. Max. Unit Conditions IID — 300 — — 300 — 300 300 ns pulse width, 2% duty cycle mA (See Section 3.1 “Test Circuits”.) OFF Capacitance SW to GND CSG(OFF) — 15 — 10 15 — 15 pF 0V, f = 1 MHz ON Capacitance SW to GND CSG(ON) — 18 — 13 18 — 18 pF 0V, f = 1 MHz +VSPK — — — — — — –VSPK — — — — — — +VSPK — — — — — — Output Switch Isolation Diode Current 150 150 Output Voltage Spike –VSPK — — — — — — +VSPK — — — — — — –VSPK — — — — — — 150 — Charge Injection QC — — DS20005498C-page 6 — — — — — — 820 600 350 — — — — — — — — — VPP = +40V, mV V = –160V, NN RLOAD = 50Ω mV (See Section 3.1 “Test Circuits”.) VPP = +100V, mV V = –100V, NN RLOAD = 50Ω mV (See Section 3.1 “Test Circuits”.) VPP = +160V, mV V = –40V, NN RLOAD = 50Ω mV (See Section 3.1 “Test Circuits”.) pC VPP = +40V, VNN = –160V, VSIG = 0V (See Section 3.1 “Test Circuits”.) pC VPP = +100V, VNN = –100V, VSIG = 0V (See Section 3.1 “Test Circuits”.) pC VPP = +160V, VNN = –40V, VSIG = 0V (See Section 3.1 “Test Circuits”.)  2017-2022 Microchip Technology Inc. and its subsidiaries HV2605/HV2705 TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Conditions TEMPERATURE RANGE Operating Ambient Temperature TA 0 — 70 °C Storage Temperature TS –65 — 150 °C θJA — 52 — PACKAGE THERMAL RESITANCE 48-lead LQFP Note 1: °C/W Note 1 Mounted on an FR-4 board, 25 mm x 25 mm x 1.57 mm Timing Waveforms DN+1 DN DATA IN DIN 50% LE 50% DN-1 50% 50% tWLE tSD CLOCK CLK 50% tSU tDO DATA OUT DOUT VOUT (typ) th DO 50% tOFF OFF tON 90% 10% ON CLR 50% 50% tWCL  2017-2022 Microchip Technology Inc. and its subsidiaries 50% DS20005498C-page 7 HV2605/HV2705 2.0 PIN DESCRIPTION The description of pins in the 42-ball bumped die, 48lead TQFP and 48-lead LQFP packages are listed on Table 2-1 and Table 2-2, respectively. The locations of the pads/balls are listed in Package Types†. TABLE 2-1: Pin Number 1 42-BALL BUMPED DIE PIN FUNCTION TABLE HV2605 Pin Name HV2705 Pin Name NC — — RGND Description No connection Ground for bleed resistor 2 VPP VPP Positive supply voltage 3 VNN VNN Negative supply voltage 4 DOUT DOUT Data out logic output 5 CLR CLR Latch clear logic input 6 CLK CLK Clock logic input for Shift register 7 GND GND Ground 8 SW15A SW15A Analog Switch 15 Terminal A 9 SW15B SW15B Analog Switch 15 Terminal B 10 LE LE 11 VDD VDD 12 SW0A SW0A Analog Switch 0 Terminal A 13 SW0B SW0B Analog Switch 0 Terminal B 14 SW14A SW14A Analog Switch 14 Terminal A 15 SW14B SW14B Analog Switch 14 Terminal B Latch enable logic input, low active Logic supply voltage 16 DIN DIN 17 SW1A SW1A Data in logic input Analog Switch 1 Terminal A 18 SW1B SW1B Analog Switch 1 Terminal B 19 SW13A SW13A Analog Switch 13 Terminal A 20 SW13B SW13B Analog Switch 13 Terminal B 21 SW2A SW2A Analog Switch 2 Terminal A 22 SW2B SW2B Analog Switch 2 Terminal B 23 SW12A SW12A Analog Switch 12 Terminal A 24 SW12B SW12B Analog Switch 12 Terminal B 25 SW3A SW3A Analog Switch 3 Terminal A 26 SW3B SW3B Analog Switch 3 Terminal B 27 SW11A SW11A Analog Switch 11 Terminal A 28 SW11B SW11B Analog Switch 11 Terminal B 29 SW9B SW9B Analog Switch 9 Terminal B 30 SW8B SW8B Analog Switch 8 Terminal B 31 SW7A SW7A Analog Switch 7 Terminal A 32 SW6A SW6A Analog Switch 6 Terminal A 33 SW4A SW4A Analog Switch 4 Terminal A 34 SW4B SW4B Analog Switch 4 Terminal B 35 SW10B SW10B Analog Switch 10 Terminal B 36 SW10A SW10A Analog Switch 10 Terminal A 37 SW9A SW9A Analog Switch 9 Terminal A 38 SW8A SW8A Analog Switch 8 terminal A DS20005498C-page 8  2017-2022 Microchip Technology Inc. and its subsidiaries HV2605/HV2705 TABLE 2-1: 42-BALL BUMPED DIE PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name 39 SW7B SW7B Analog Switch 7 Terminal B 40 SW6B SW6B Analog Switch 6 Terminal B 41 SW5B SW5B Analog Switch 5 Terminal B 42 SW5A SW5A Analog Switch 5 Terminal A TABLE 2-2: Description 48-LEAD TQFP/LQFP PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name 1 NC NC No connection No connection Description 2 NC NC 3 SW4B SW4B Analog Switch 4 Terminal B 4 SW4A SW4A Analog Switch 4 Terminal A 5 SW3B SW3B Analog Switch 3 Terminal B 6 SW3A SW3A Analog Switch 3 Terminal A 7 SW2B SW2B Analog Switch 2 Terminal B 8 SW2A SW2A Analog Switch 2 Terminal A 9 SW1B SW1B Analog Switch 1 Terminal B 10 SW1A SW1A Analog Switch 1 Terminal A 11 SW0B SW0B Analog Switch 0 Terminal B 12 SW0A SW0A 13 VNN VNN Analog Switch 0 Terminal A Negative supply voltage 14 NC NC No connection 15 VPP VPP Positive supply voltage 16 NC NC 17 GND GND No connection 18 VDD VDD Logic supply voltage 19 DIN DIN Data in logic input 20 CLK CLK 21 LE LE Ground Clock logic input for Shift register Latch-enable logic input, low active 22 CLR CLR Latch clear logic input 23 DOUT DOUT Data out logic output NC — — RGND Ground for bleed resistor 25 SW15B SW15B Analog Switch 15 Terminal B 26 SW15A SW15A Analog Switch 15 Terminal A 27 SW14B SW14B Analog Switch 14 Terminal B 28 SW14A SW14A Analog Switch 14 Terminal A 29 SW13B SW13B Analog Switch 13 Terminal B 30 SW13A SW13A Analog Switch 13 Terminal A 31 SW12B SW12B Analog Switch 12 Terminal B 32 SW12A SW12A Analog Switch 12 Terminal A 33 SW11B SW11B Analog Switch 11 Terminal B 34 SW11A SW11A Analog Switch 11 Terminal A 24  2017-2022 Microchip Technology Inc. and its subsidiaries No connection DS20005498C-page 9 HV2605/HV2705 TABLE 2-2: 48-LEAD TQFP/LQFP PIN FUNCTION TABLE Pin Number HV2605 Pin Name HV2705 Pin Name 35 NC NC No connection 36 NC NC No connection 37 SW10B SW10B Analog Switch 10 Terminal B 38 SW10A SW10A Analog Switch 10 Terminal A 39 SW9B SW9B Analog Switch 9 Terminal B 40 SW9A SW9A Analog Switch 9 Terminal A 41 SW8B SW8B Analog Switch 8 Terminal B 42 SW8A SW8A Analog Switch 8 Terminal A 43 SW7B SW7B Analog Switch 7 Terminal B 44 SW7A SW7A Analog Switch 7 Terminal A 45 SW6B SW6B Analog Switch 6 Terminal B 46 SW6A SW6A Analog Switch 6 Terminal A 47 SW5B SW5B Analog Switch 5 Terminal B 48 SW5A SW5A Analog Switch 5 Terminal A DS20005498C-page 10 Description  2017-2022 Microchip Technology Inc. and its subsidiaries HV2605/HV2705 3.0 FUNCTIONAL DESCRIPTION 3.1 Test Circuits Figure 3-1 to Figure 3-8 show the test circuits for HV2605/HV2705. VIN = 10VP-P @5MHz ISOL VPP -10V VOUT Open RLOAD Open RGND RGND VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND KO = 20Log FIGURE 3-1: Switch. Switch Off Leakage per VOUT FIGURE 3-4: VSIG 5V VOUT VIN Off Isolation. IID RLOAD VNN (HV2605 only) RGND RGND VPP VPP VDD VNN VNN GND FIGURE 3-2: 5V Switch DC Offset. VPP VPP VDD VNN VNN GND FIGURE 3-5: Diode Current. VPP -10V 5V Output Switch Isolation VIN = 10VP-P @5MHz 10kΩ RLOAD VOUT 50Ω RGND RGND VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND KCR = 20Log FIGURE 3-3: 50Ω NC TON/TOFF Test Circuit.  2017-2022 Microchip Technology Inc. and its subsidiaries FIGURE 3-6: 5V VOUT VIN Switch Crosstalk. DS20005498C-page 11 HV2605/HV2705 ΔVOUT VOUT 1000pF VSIG RGND VPP VPP VDD VNN VNN GND 5V Q = 1000pF x ΔVOUT FIGURE 3-7: Charge Injection. +VSPK VOUT –VSPK RLOAD 50Ω RGND 1kΩ VPP VPP VDD VNN VNN GND FIGURE 3-8: DS20005498C-page 12 5V Output Voltage Spike.  2017-2022 Microchip Technology Inc. and its subsidiaries HV2605/HV2705 TABLE 3-1: D0 D1 L TRUTH FUNCTION TABLE ... D7 D8 D15 LE CLR SW0 SW1 — — — — L L OFF H — — L — — — L L — — — L L — — H — — — L — — — — L — — — — — L L — — — L — — L L — — — H — — L L — — — — — L — L L — — — — — H — L L — — — — — — L L — — — — — — L L — — — — — L L ... ... ... ... SW7 SW8 ... SW15 — — — — ON — — — — — OFF — — — L — ON — — — L — — — — — — — — — — OFF — — ON — — OFF — — ON — — — — — — — — — — — — — — — ... ... — — — — — — — L L — — — — — — — — — L L L — — — — OFF — — — — H L L — — — — ON X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Note 1: The 16 switches operate independently. 2: Serial data is clocked in on the low-to-high transition of the clock. 3: All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the Shift registers data flow through the latch. 4: DOUT is high when data in the Shift register 15 is high. 5: Shift registers clocking has no effect on the switch states if LE is high. 6: The CLR clear input overrides all other inputs.  2017-2022 Microchip Technology Inc. and its subsidiaries DS20005498C-page 13 HV2605/HV2705 4.0 PACKAGING INFORMATION† 4.1 Package Marking Information † Notice: The LQFP package is not recommended for new designs. Please use TQFP package as an alternative. 42-Ball Bumped Die XXXXXXX e3 XXXXX^^ YYWWNNN 48-Lead LQFP XXXXXX XXXXXX e3 ^^YYWW NNN 48-Lead TQFP XXXXXX XXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005498C-page 14 Example HV2605 e3 BD^^ 2126256 Example HV2705 e3 BD^^ 2126256 Example Example HV 2605FG e3 ^^2126 256 HV 2705FG e3 ^^2126 256 Example Example HV 2605TQ 2126256 HV 2705TQ 2126256 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. 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