HV5622
32-Channel Serial-to-Parallel Converter With Open Drain Outputs
Features
General Description
•
•
•
•
•
•
The HV5622 is a low-voltage serial-to-high-voltage
parallel converter with open drain outputs. This device
has
been
designed
as
a
driver
for
AC-electroluminescent displays. It can also be used in
any application requiring multiple-output high-voltage
current-sinking capabilities such as driving inkjet and
electrostatic print heads, plasma panels, vacuum
fluorescent and large matrix LCD displays.
100 mA Minimum Sink Current
8 MHz Shift Register Speed
Polarity and Blanking Inputs
CMOS-compatible Inputs
Forward and Reverse Shifting Options
Diode to VPP allows Efficient Power Recovery
Applications
• Inkjet and Electrostatic Print Heads
• AC-electroluminescent Displays
• Microelectromechanical Systems Applications
The device consists of a 32-bit Shift register, 32 latches
and control logic to perform the polarity select and
blanking of the outputs. Data is shifted through the Shift
register on the high-to-low transition of the clock. The
HV5622 shifts in a clockwise direction when viewed
from the top of the package. A data output buffer is
provided for cascading devices. This output reflects the
current status of the last bit of the Shift register. The
operation of the Shift register is not affected by the latch
enable (LE), blanking (BL) and polarity (POL) inputs.
Transfer of data from the Shift register to the latch
occurs when the LE input is high. The data in the latch
is stored when LE is low.
Package Types
44-lead PLCC
(Top view)
44-lead PQFP
(Top view)
6
1 44
40
44
1
See Table 2-1 and Table 2-2 for pin information.
2017 Microchip Technology Inc.
DS20005854A-page 1
HV5622
Functional Block Diagram
POL
BL
LE
HVOUT1
DATA
IN
Latch
HVOUT2
CLK
Latch
32-Bit
Shift
Register
(Outputs 3 to 30 not shown)
HVOUT31
Latch
HVOUT32
DATA
OUT
Latch
DS20005854A-page 2
2017 Microchip Technology Inc.
HV5622
Typical Application Circuit
2017 Microchip Technology Inc.
DS20005854A-page 3
HV5622
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage, VDD (Note 1) .................................................................................................................. –0.5V to +15V
Output Voltage, VPP (Note 1) ................................................................................................................ –0.5V to +230V
Logic Input Levels (Note 1) .............................................................................................................. –0.5V to VDD+0.5V
Ground Current (Note 2) ......................................................................................................................................... 1.5A
Operating Ambient Temperature, TA .................................................................................................... –40°C to +85°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
Continuous Total Power Dissipation:
44-lead PQFP (Note 3) ............................................................................................................................ 1200 mW
44-lead PLCC (Note 3) ............................................................................................................................ 1200 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: All voltages are referenced to VSS.
2: Duty cycle is limited by the total power dissipated in the package.
3: For operations above 25°C ambient, derate linearly to the maximum operating temperature at 20 mW/°C.
RECOMMENDED OPERATING CONDITIONS
Parameter
Logic Supply Voltage
Sym.
Min.
Typ.
Max.
Unit
VDD
10.8
—
13.2
V
HVOUT
–0.3
—
+220
V
High-level Input Voltage
VIH
VDD–2
—
VDD
V
Low-level Input Voltage
VIL
0
—
2
V
Clock Frequency
fCLK
—
—
8
MHz
–40
—
+85
°C
High-voltage Output Voltage
Operating Ambient Temperature
DS20005854A-page 4
TA
Conditions
2017 Microchip Technology Inc.
HV5622
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over recommended operating conditions unless otherwise stated
Parameter
Sym.
Min.
IDD
—
—
IDDQ
—
IO(OFF)
High-level Logic Input Current
Low-level Logic Input Current
VDD Supply Current
Quiescent VDD Supply Current
Off State Output Current
High-level Output Data Out
Low-level Output Voltage
HVOUT
Unit
Conditions
15
mA
fCLK = 8 MHz, fDATA = 4 MHz
—
100
µA
VIN = 0V
—
—
10
µA
All outputs high, all SWS
parallel
IIH
—
—
1
µA
VIH = VDD
IIL
—
—
–1
µA
VIL = 0V
VOH
VDD–1V
—
—
V
IDOUT = –100 µA
—
—
15
V
IHVOUT = 100 mA
—
—
1
V
IDOUT = 100 µA
—
—
–1.5
V
IOL = –100 mA
VOL
Data Out
HVOUT Clamp Voltage
VOC
Typ. Max.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VDD = 12V, TA = 25°C
Parameter
Sym.
Min.
fCLK
—
—
8
MHz
tWL, tWH
62
—
—
ns
tSU
25
—
—
ns
Clock Frequency
Clock Width, High or Low
Data Set-up Time before CLK Falls
Data Hold Time after CLK Falls
Typ. Max. Unit
Conditions
tH
10
—
—
ns
Turn-on Time, HVOUT from Enable
tON
—
—
500
ns
RL = 2 kΩ to VPP maximum
Delay Time Clock to Data High to Low
tDHL
—
—
100
ns
CL = 15 pF
Delay Time Clock to Data Low to High
tDLH
—
—
100
ns
CL = 15 pF
Delay Time Clock to Latch Enable Low to High
tDLE
50
—
—
ns
Latch Enable Pulse Width
tWLE
50
—
—
ns
Latch Enable Setup Time before Clock Falls
tSLE
50
—
—
ns
Sym.
Min.
Operating Ambient Temperature
TA
–40
—
+85
°C
Storage Temperature
TS
–65
—
+150
°C
44-lead PQFP
JA
—
51
—
°C/W
44-lead PLCC
JA
—
37
—
°C/W
TEMPERATURE SPECIFICATIONS
Parameter
Typ. Max.
Unit
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
2017 Microchip Technology Inc.
DS20005854A-page 5
HV5622
Timing Waveforms
VIH
DATA
IN
50%
Data Valid
50%
VIL
tSU
tH
VIH
CLK
50%
50%
50%
50%
VIL
tWH
tWL
VOH
50%
DATA
OUT
VOL
tDLH
VOH
50%
VOL
tDHL
VIH
50%
50%
LE
VIL
tWLE
tDLE
VOH
HVOUT
w/ S/R HIGH
10%
tON
DS20005854A-page 6
tSLE
VOL
2017 Microchip Technology Inc.
HV5622
2.0
PIN DESCRIPTION
The details on the pins of HV5622 44-lead PQFP and
44-lead PLCC are in Table 2-1 and Table 2-2,
respectively. Refer to Package Types for the location
of pins.
TABLE 2-1:
44-LEAD PQFP PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
HVOUT22
High-voltage output
2
HVOUT21
High-voltage output
3
HVOUT20
High-voltage output
4
HVOUT19
High-voltage output
5
HVOUT18
High-voltage output
6
HVOUT17
High-voltage output
7
HVOUT16
High-voltage output
8
HVOUT15
High-voltage output
9
HVOUT14
High-voltage output
10
HVOUT13
High-voltage output
11
HVOUT12
High-voltage output
12
HVOUT11
High-voltage output
13
HVOUT10
High-voltage output
14
HVOUT9
High-voltage output
15
HVOUT8
High-voltage output
16
HVOUT7
High-voltage output
17
HVOUT6
High-voltage output
18
HVOUT5
High-voltage output
19
HVOUT4
High-voltage output
20
HVOUT3
High-voltage output
21
HVOUT2
High-voltage output
22
HVOUT1
High-voltage output
23
DATA OUT
Data output pin
24
NC
No connection
25
NC
No connection
26
NC
No connection
27
POL
Inverts the polarity of the HVOUT pins
28
CLK
Clock pin. Shift registers shift data on the falling edge of the input clock.
29
VSS
Reference voltage (usually ground)
30
VDD
Logic supply voltage
31
LE
32
DATA IN
33
BL
This blanking pin sets all HVOUT pins low or high depending upon the state of
polarity. See Table 3-2.
34
NC
No connection
2017 Microchip Technology Inc.
Latch enable pin. Data is shifted from the Shift register to the latches on logic
input high.
Data input pin
DS20005854A-page 7
HV5622
TABLE 2-1:
44-LEAD PQFP PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
35
HVOUT32
High-voltage output
36
HVOUT31
High-voltage output
37
HVOUT30
High-voltage output
38
HVOUT29
High-voltage output
39
HVOUT28
High-voltage output
40
HVOUT27
High-voltage output
41
HVOUT26
High-voltage output
42
HVOUT25
High-voltage output
43
HVOUT24
High-voltage output
44
HVOUT23
High-voltage output
TABLE 2-2:
Description
44-LEAD PLCC PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
HVOUT17
High-voltage output
2
HVOUT16
High-voltage output
3
HVOUT15
High-voltage output
4
HVOUT14
High-voltage output
5
HVOUT13
High-voltage output
6
HVOUT12
High-voltage output
7
HVOUT11
High-voltage output
8
HVOUT10
High-voltage output
9
HVOUT9
High-voltage output
10
HVOUT8
High-voltage output
11
HVOUT7
High-voltage output
12
HVOUT6
High-voltage output
13
HVOUT5
High-voltage output
14
HVOUT4
High-voltage output
15
HVOUT3
High-voltage output
16
HVOUT2
High-voltage output
17
HVOUT1
High-voltage output
18
DATA OUT
Data output pin
19
NC
No connection
20
NC
No connection
21
NC
No connection
22
POL
Inverts the polarity of the HVOUT pins
23
CLK
Clock pin. Shift registers shift data on the falling edge of the input clock.
24
VSS
Reference voltage (usually ground)
25
VDD
Logic supply voltage
26
LE
DS20005854A-page 8
Latch enable pin. Data is shifted from the Shift register to the latches on logic
input high.
2017 Microchip Technology Inc.
HV5622
TABLE 2-2:
44-LEAD PLCC PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
27
DATA IN
28
BL
This blanking pin sets all HVOUT pins low or high depending upon the state of
polarity. See Table 3-2.
29
NC
No internal connection
30
HVOUT32
High-voltage output
31
HVOUT31
High-voltage output
32
HVOUT30
High-voltage output
33
HVOUT29
High-voltage output
34
HVOUT28
High-voltage output
35
HVOUT27
High-voltage output
36
HVOUT26
High-voltage output
37
HVOUT25
High-voltage output
38
HVOUT24
High-voltage output
39
HVOUT23
High-voltage output
40
HVOUT22
High-voltage output
41
HVOUT21
High-voltage output
42
HVOUT20
High-voltage output
43
HVOUT19
High-voltage output
44
HVOUT18
High-voltage output
2017 Microchip Technology Inc.
Description
Data input pin
DS20005854A-page 9
HV5622
3.0
FUNCTIONAL DESCRIPTION
Follow the steps in Table 3-1 to power up and power
down the HV5622.
TABLE 3-1:
POWER-UP AND POWER-DOWN SEQUENCE
Power-up
Step
Power-down
Description
1
2
3
Step
Connect ground.
Apply VDD.
Set all inputs to a known state.
TABLE 3-2:
1
2
3
TRUTH FUNCTION TABLE
Outputs
Inputs
Function
Shift Register
Data
CLK
LE
BL
All On
X
X
X
All Off
X
X
X
Invert Mode
X
X
Load S/R
H or L
Load Latches
Transparent
Latch Mode
Note:
Description
Remove all inputs.
Remove VDD.
Disconnect ground.
High-voltage Output
Data Out
POL
1
2
...
32
1
2
...
32
L
L
p1
p2
...
p32
On
On
...
On
d
L
H
p1
p2
...
p32
Off
Off
...
Off
d
L
H
L
p1
p2
...
p32
p1
p2
...
p32
d
↓
L
H
H
H or L
p1
...
p31
p1
p2
...
p32
p32
X
H or L
↑
H
H
p1
p2
...
p32
p1
p2
...
p32
d
X
H or L
↑
H
L
p1
p2
...
p32
p1
p2
...
p32
d
L
↓
H
H
H
L
p1
...
p31
Off
p1
...
p31
p32
H
↓
H
H
H
H
p1
...
p31
On
p1
...
p31
p32
H = High-logic level
L = Low-logic level
X = Irrelevant
↓ = High-to-low transition
↑ = Low-to-high transition
d = Current state of the data output
pn = “p” represents the current state of the Shift register output, and
“n” represents the channel order.
VDD
VDD
HVOUT
DATA
OUT
DATA
IN
HVIN
VSS
VSS
VSS
Logic Inputs
FIGURE 3-1:
DS20005854A-page 10
Logic Data Output
High Voltage Outputs
Input and Output Equivalent Circuits.
2017 Microchip Technology Inc.
HV5622
4.0
PACKAGE MARKING INFORMATION
4.1
Packaging Information
44-lead PQFP
Example
XXXXXXXXX
e3 YYWWNNN
HV5622PG
e3 1724198
44-lead PLCC
Example
XXXXXXXXXXX
e3 YYWWNNN
HV5622PJ
e3 1722741
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2017 Microchip Technology Inc.
DS20005854A-page 11
HV5622
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
44
1
b
e
Top View
View B
A
L2
A2
Gauge
Plane
Seating
Plane
L
A1
θ
L1
Side View
Seating
Plane
View B
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEH DPROGHGPDUNLGHQWL¿HU DQHPEHGGHGPHWDOPDUNHU RU
a printed indicator.
Symbol
MIN
Dimension
NOM
(mm)
MAX
A
A1
A2
b
D
D1
E
E1
1.95*
0.00
1.95
0.30
13.65*
9.80*
13.65*
9.80*
-
-
2.00
-
13.90
10.00
13.90
10.00
2.35
0.25
2.10
0.45
14.15*
10.20* 14.15* 10.20*
e
L
L1
L2
0.80
BSC
0.88
1.03
ș
0O
0.73
1.95
REF
0.25
BSC
3.5O
7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings not to scale.
S
D
# DSPD 44PQFPPG V i C041309
DS20005854A-page 12
2017 Microchip Technology Inc.
HV5622
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
D
D1
1 44
.048/.042 x 45O
6
.150 MAX
.056/.042 x 45O
40
Note 1
(Index Area)
.075 MAX
E1
E
Note 2
.020max
(3 Places)
Top View
Vertical Side View
View B
b1
A
Base
Plane
A2
.020 MIN
Seating
Plane
e
A1
b
Horizontal Side View
R
View B
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Notes:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEH DPROGHGPDUNLGHQWL¿HU DQHPEHGGHGPHWDOPDUNHU RU
a printed indicator.
2. $FWXDOVKDSHRIWKLVIHDWXUHPD\YDU\
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
E1
MIN
.165
.090
.062
.013
.026
.685
.650
.685
.650
NOM
.172
.105
-
-
-
.690
.653
.690
.653
MAX
.180
.120
.083
.021
.036†
.695
.656
.695
.656
e
R
.025
.050
BSC
.035
.045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005854A-page 13
HV5622
NOTES:
DS20005854A-page 14
2017 Microchip Technology Inc.
HV5622
APPENDIX A:
REVISION HISTORY
Revision A (October 2017)
• Converted Supertex Doc # DSFP-HV5622 to
Microchip DS20005854A
• Removed “Processed with HVCMOS®
Technology” in the Features section
• Changed the package marking format
• Removed the 44-lead PQFP PG M919 and
44-lead PLCC PJ M903 media types
• Made minor changes throughout the document
2017 Microchip Technology Inc.
DS20005854A-page 15
HV5622
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
PART NO.
Device
Device:
Packages:
Environmental:
Media Types:
XX
-
Package
Options
HV5622
X
-
Environmental
=
X
Media Type
32-Channel Serial-to-Parallel Converter
with Open Drain Outputs
PG
=
44-lead PQFP
PJ
=
44-lead PLCC
G
=
Lead (Pb)-free/RoHS-compliant Package
(blank)
=
96/Tray for a PG Package
(blank)
=
27/Tube for a PJ Package
DS20005854A-page 16
Examples:
a) HV5622PG-G:
32-Channel Serial-to-Parallel
Converter with Open Drain
Outputs, 44-lead PQFP,
96/Tray
b) HV5622PJ-G:
32-Channel Serial-to-Parallel
Converter with Open Drain
Outputs, 44-lead PLCC,
27/Tube
2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
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QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
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Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
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and other countries.
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trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
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CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
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MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
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PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
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Silicon Storage Technology is a registered trademark of Microchip
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All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2257-0
== ISO/TS 16949 ==
2017 Microchip Technology Inc.
DS20005854A-page 17
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
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DS20005854A-page 18
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2017 Microchip Technology Inc.
10/10/17
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