HV7321K6-G

HV7321 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches Features General Description • Power Sequencing Free 5 Output Levels including RTZ (Return-to-Zero) • -44 dB Single-Cycle Pulse-Inversion Second Harmonic Distortion (HD2) at 5 MHz • Output Voltage up to ±80V • ±2.5A Peak Output Current • ±300 mA Current from VPP1/VNN1 in CW Mode-0 • Integrated T/R Switch & RX Damper Switch • Bleeder Switches Achieve True Zero during RTZ • Supports Both Transparent and Re-Timing Mode • Re-Timing Clock Frequency Supports up to 220 MHz • Built-In Output Protection Diodes and Clamp Diodes • +2.5/+3.3V Input Logic • Built-In CW Switches to Pair with External CW Transmitters (CW Mode-1) • 9 mm x 9 mm 64-Lead VQFN Package The HV7321 is a 4-channel, 5-level, ultrasound transmitter with built-in T/R switches, output protection diodes and clamp diodes. The HV7321 can provide up to ±2.5A and the output voltage swing can be up to ±80V. The HV7321 supports both Transparent and Re-Timing mode. The re-timing clock frequency can support up to 220 MHz. The re-timing feature helps reduce the output jitter introduced by the driving the field-programmable gate array (FPGA). Applications The HV7321 has two different modes CW transmission, CW-Mode 0 and CW-Mode 1. for In CW-Mode 0 (Mode = 0, PWS = 0), the VPP1 and VNN1 rails are used for CW transmission. The output current is reduced in CW Mode-0. In CW-Mode 1, the HV7321 accepts the output of an external CW beamformer as CW source. The HV7321 is LVCMOS 2.5V/3.3V input compatible, which can be interfaced with the FPGA directly. The HV7321 is available in a 9 mm x 9 mm 64-Lead VQFN package. • Medical Ultrasound Imaging Systems • NDT Ultrasound • Piezoelectric or Capacitive Transducer Drivers  2016 Microchip Technology Inc. DS20005639A-page 1 HV7321 POS0 NEG0 SEL0 MODE VDD GND VGN VPP0 VPP0 CPF0 CNF0 VNN0 VNN0 VNN2 VNN1 CNF1 Package Types 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CWIN0 1 48 CPF1 SEL1 2 47 VPP1 NEG1 3 46 TX0 POS1 4 45 RX0 CWIN1 5 44 RGND OEN 6 43 RX1 PWS 7 42 TX1 CLK 8 41 CPOS GND 9 40 CNEG 65 VSUB POS2 14 35 TX3 CWIN2 15 34 VPP1 SEL3 16 33 CPF1 17 18 19 20 21 22 23 24 25 26 27 28 29 DS20005639A-page 2 30 31 32 CNF1 RX3 VNN1 36 VNN2 13 VNN0 NEG2 VNN0 RGND CNF0 37 CPF0 12 VPP0 SEL2 VPP0 RX2 VGP 38 GND 11 VDD REN OTPN TX2 CWIN3 39 POS3 10 NEG3 VLL  2016 Microchip Technology Inc.  2016 Microchip Technology Inc. HV7321 – Block Diagram +2.5V/3V 2 µF VLL +5V 2 µF VDD 0 to +80V 2 µF 100V 2 µF +10V 2 µF 1 µF CPOS CPF0 VGP LR VPOS VPOS GND CWIN0-3 MODE REN OEN VPP0 0 to +80V 2 µF 2 µF 100V CPF1 VPP1 LR VPF0 LR VPF1 VPF0 VGN VPP0 VPF1 VGN VPP1 VPP1 VPP0 to CWSW1-3 CWSW0 PWS OTPN POS0 NEG0 SEL0 Logic and Retiming VPF0 VPF0 VNEG VNF0 VNF1 VPOS TX0 X0 TRSW0 Rb RX0 RX0 VNN0 VNN1 RTZSW0 RXDMP0 To Ch. 1-3 POS3 Rb R GND 1 of 4 channels RGND NEG3 TX1,2,3 SEL3 VNEG GND VGN VNN2 GND VGN SUB VSUB CNEG 2 µF 1 µF -10V VNN2 1 µF 100V VNF1 VGP VNN1 LR VNF0 LR VNF1 CNF0 VNN0 2 µF 1 µF 100V 0 to -80V CNF1 RX1,2,3 VNN1 2 µF 2 µF 100V 0 to -80V HV7321 DS20005639A-page 3 LR VNEG CLK VNF0 VGP VNN0 HV7321 HV7321 – Typical Application Circuit +2.5V +5V +10V CDD = 2µF 10V CLL= 2 µF 10V CCPOS = 1µF 10V CGP = 2 µF 16V CTRN[3:0] OEN VLL VDD CPOS VGP 1 of 4 Channels REN +80V MODE CPF0 PWS TXFPGA I/Os OTPN CPP0 = 2 µF 100V VPP0 CCPF1 = 2 µF 10V VPF0 VNF0 OTPN VNN2 VNN0 DT[63:0] -80V CNN0 = 2 µF 100V CNF0 CCNF0 = 2 µF 10V SEL0 +60V NEG0 CPP1 = 2 µF 100V VPP1 POS0 CPF1 Decode & Level Shift SEL3 VPF1 VNF1 CCPF1 = 2 µF 10V -60V CNN1 = 2 µF 100V VNN1 NEG3 CNF1 POS3 CCNF1 = 2 µF 10V TX0 X0 RTZSW to other ICs TRSW RX0 TRSW RX0 CLK For CW Mode-1 Connect to a low-voltage CW source (such as the MD1730) RXDMP CWIN0 CWIN1 CWIN2 CWIN3 CWSW RGND RGND TX1-3 RX1-3 SUB GND CNEG VGN VSUB CGN = 2 µF 16V CCNEG = 1 µF 10V -10V DS20005639A-page 4  2016 Microchip Technology Inc. HV7321 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Positive logic supply (VLL).......................................................................................................................... -0.5V to +5.5V All I/O & CLK pin voltage (VIO)................................................................................................................... -0.5V to +5.5V Positive voltage supply (VDD)..................................................................................................................... -0.5V to +5.5V Positive gate driver supply (VGP) ............................................................................................................. -0.5V to +13.5V Negative gate driver supply (VGN) ........................................................................................................... -13.5V to +0.5V High voltage positive supply (VPP0,1) .......................................................................................................... -1.0V to +85V High voltage negative supply (VNN0,1,2)...................................................................................................... -85V to +1.0V CW input voltage (VCWIN) .......................................................................................................................... -7.5V to +7.5V TX pin voltage (VTX)..................................................................................................................................... -85V to +85V RX pin to GND voltage (VRX) ....................................................................................................................... ±0.7 to ±1.4V Operating temperature ................................................................................................................................ 0°C to +85°C Storage temperature ............................................................................................................................... -55°C to +150°C Maximum junction temperature............................................................................................................................ +130°C Maximum not-latch-up current ........................................................................................................................... +100 mA ESD Rating CWIN,TX, VPP, VNN pins ......................................................................................................................±500V ESD Rating – all other pins ....................................................................................................................................... ±2kV † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions VLL 2.25 2.50 3.60 V Note 1 Positive Voltage Supply VDD 4.75 5.0 5.25 V Note 1 Positive Gate Driver Supply VGP 8.0 10 12 Negative Gate Driver Supply VGN -12 -10 -8.0 V Note 1 See Table 3-1. VPP0 0 — 80 VPP1 0 — 80 V Note 1 Must be VPP0 ≥ VPP1 VNN0 -80 — 0 VNN1 -80 — 0 V Note 1 Must be VNN0  VNN1 VLL Quiescent Current ILLQ — 0.06 0.7 μA VDD Quiescent Current IDDQ — 30 80 µA VPP0 Quiescent Current IPP0Q — 0.37 6 µA VNN0 Quiescent Current INN0Q -9 -0.78 — µA Operating Supply Voltages Positive Logic Supply High Voltage Positive Supply High Voltage Negative Supply Operating Supply Current VPP1 Quiescent Current IPP1Q — 0.44 10 µA VNN1 Quiescent Current INN1Q -10 -1.46 — µA VNN2 Quiescent Current INN2Q -7 -3.84 — µA Note 1: 2: OEN = REN = 0 Characterized only; not 100% tested in production. Design guidance only.  2016 Microchip Technology Inc. DS20005639A-page 5 HV7321 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter VDD Current Sym. Min. Typ. Max. Unit IDDEN — 0.9 1.0 mA VPP0 Current IPP0EN — 0.1 0.13 mA VNN0 Current INN0EN -0.12 -0.1 — mA VPP1 Current IPP1EN — 0.1 0.13 mA VNN1 Current INN1EN -0.12 -0.1 — mA VNN2 Current INN2EN -0.05 -0.03 — mA VLL Current with Re-Timing ILLRT — 0.11 0.3 mA VDD Current with Re-Timing IDDRT — 7.08 8 mA VLL Max. Current of SEL = 0/1 ILL5 — 23 40 μA VDD Max. Current of SEL = 0/1 IDD5 — 1.5 1.7 mA VGP Max. Current of SEL = 0/1 IGP5 — 2.6 4 mA VGN Max. Current of SEL = 0/1 IGN5 -14 -9 — mA VPP0 Current of SEL = 0 (1) IPP05 — 136 146 mA VNN0 Current of SEL = 0 (1) INN05 -132 -125 — mA VPP1 Current of SEL = 1 (1) IPP15 — 148 158 mA VNN1 Current of SEL = 1 (1) Conditions f = 0 MHz fCLK = 0 MHz MODE = 0 or 1 fCLK = 80 MHz TX one-channel output, no load, continuous, Note 1 CLK = 0 PWS = 1 MODE = 0 IPP05/INN05 and IPP15/INN15 are calculated using TX one channel output continuous, no load, at 5 MHz. INN15 -150 -143 — mA IGPCW — 1.0 2.0 mA VGN Current of SEL = 1 IGNCW -8.0 -5.0 — mA VPP1 Current of SEL = 1 IPP1CW — 17 26 mA VNN1 Current of SEL = 1 INN1CW -20 -15 — mA VCWIN0–3 -7.0 — +7.0 V CWSW Analog Switch On-Resistance (1) RCWSW — 26.5 35 Ω ICWSW = ±100 mA TRSW Off Withstand Voltage VCWSW -80 — +80 V ISW = ±1.0 μA — 5.0 — — 60 — pF MODE = 1, 1 MHz, 0 dBm, DC 0V, Note 1 — 800 1100 — 66 90 ns 50% MODE rise to CWSW on/off Note 1 — 8.5 19 VGP Current of SEL = 1 TX one-channel output 5 MHz, continuous, no load VPP1/VNN1 = ±5V PWS = MODE = 0 CW Mode-0, Note 1 CWSW High-Voltage Analog Switch CW Switch Input Voltage CWSW Off Capacitance to GND CWSW On Capacitance to GND CWSW Switching On Time CWSW Switching Off Time CCWSW tCWSW TX Output P-Channel MOSFET on VPP0 On-Resistance Peak Output Current Note 1: 2: RON_P0 Ω ISD = 100 mA 1 1.5 — A VPP0 = +25V, RL = 1.0Ω to GND Note 1 2.0 2.8 — A VPP0 = +80V, RL = 1.0Ω to GND Note 1 IOUT_P0 Characterized only; not 100% tested in production. Design guidance only. DS20005639A-page 6  2016 Microchip Technology Inc. HV7321 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions TX Output P-Channel MOSFET on VPP1 On-Resistance at PWS = 1 RON_P1 On-Resistance at PWS = 0 Peak Output Current at PWS = 1 (1) IOUT_P1 Peak Output Current at PWS = 0 (1) — 16 21 — 33 43 Ω ISD = 100 mA 0.8 1.0 — VPP0,1 = +25V, RL = 1.0Ω to GND 1.5 1.75 — VPP0,1= +80V, RL = 1.0Ω to GND 0.4 0.5 — 0.8 0.95 — — 8 10 Ω ISD = 100 mA -1.4 -1.7 — A VNN0 = -25V, RL = 1.0Ω to GND -2.0 -2.3 — A VNN0 = -80V, RL = 1.0Ω to GND — 11 13 — 36 45 Ω ISD = 100 mA — -1.2 -1.0 A VPP0,1 = +25V, RL = 1.0Ω to GND VPP0,1 = +80V, RL = 1.0Ω to GND TX Output N-Channel MOSFET on VNN0 On-Resistance RON_N0 Peak Output Current (1) IOUT_N0 TX Output N-Channel MOSFET on VNN1 On-Resistance at PWS = 1 On-Resistance at PWS = 0 RON_N1 Peak Output Current at PWS = 1 (1) IOUT_N1 Peak Output Current at PWS = 0 (1) VNN0,1 = -25V, RL = 1.0Ω to GND — -1.6 -1.3 — -0.4 -0.3 — -0.55 -0.4 — 7.0 16 Ω ISD = 100 mA 2.3 2.7 — A RL = 1.0Ω from -25V to TX 2.3 2.8 — A RL = 1.0Ω from -80V to TX — 7.0 16 Ω ISD = 100 mA — -2.0 -1.8 A RL = 1.0Ω from +25V to TX — -2.3 -2.0 A RL = 1.0Ω from +80V to TX A VNN0,1 = -80V, RL = 1.0Ω to GND VNN0,1 = -25V, RL = 1.0Ω to GND VNN0,1= -80V, RL = 1.0Ω to GND TX Damping P-Channel MOSFET on GND On-Resistance RON_PDMP Peak Output Current (1) IOUT_PDMP TX Damping N-Channel MOSFET on GND On-Resistance RON_NDMP Peak Output Current (1) IOUT_NDMP RTZSW Auto Bleed High-Voltage Analog Switch RTZSW On-Resistance (1) RRTZSW — 238 270 Ω ISD = ±1.0 mA RTZSW Off Withstand Voltage (1) VRTZSW -80 — +80 V ISW = ±100 μA IFM = 300 mA, Note 1 TX OUTPUT Isolation Diodes and Bleed Resistor Diode Forward Voltage VF — 0.96 1.9 V Forward Continuous Current IFM — 300 — mA Peak Forward Pulse Current IFSM — 3.0 — A PW = 50 ns, Note 2 Total Capacitance of 2-diode CT — 3.5 — pF at 1 MHz, 1 dBm, 0V DC, Note 2 TX/RX Bleed Resistor to GND Rb 11 15 20 kΩ Note 1 Note 1: 2: Note 2 Characterized only; not 100% tested in production. Design guidance only.  2016 Microchip Technology Inc. DS20005639A-page 7 HV7321 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. Min. Typ. Max. Unit Conditions TRSW Analog Switch On-Resistor RTRSW — 18 22 Ω ITRSW = ±1.0 mA Note 1 TRSW Off Withstand Voltage VTRSW -80 — +80 V ISW = ±100 μA, Note 1 RX to GND Protection Diode VF — 1.5 2.2 V IF = ±100 mA, Note 1 RRXDMP — 17 21 Ω ISD = ±1.0 mA, Note 1 CRXG — — 7.0 pF 1 MHz, 1 dBm, 0V DC, Note 2 TRSW and RXDMP Switches RXDMP Switch On-Resistance RX Pin to GND Capacitance Built-In Gate Drive Voltage Linear Regulators Output P-Channel Gate Drive Voltage Referenced to VPP0 VPF0 -5.2 -4.6 -3.8 V VGN - VPP0 < -10V Output P-Channel Gate Drive Voltage Referenced to VPP1 VPF1 -5.2 -4.6 -3.8 V VGN - VPP1 < -10V Output N-Channel Gate Drive Voltage Referenced to VNN0 VNF0 3.3 4.2 5.2 V VGP - VNN0 > 10V Output N-Channel Gate Drive Voltage Referenced to VNN1 VNF1 3.3 4.2 5.2 V VGP - VNN1 > 10V Output N-Channel Gate Drive Voltage Referenced to GND VPOS 3.2 4.2 5.2 V Output P-Channel Gate Drive Voltage Referenced to GND VNEG -5.2 -4.5 -3.8 V Dropout Voltage of (VPP0 - VGN) VDOPF0 -2.9 -2.6 -2.4 V Dropout Voltage of (VPP1 - VGN) VDOPF1 -2.9 -2.6 -2.4 V Dropout Voltage of (VGP - VNN0) VDONF0 3.0 3.3 3.6 V Dropout Voltage of (VGP - VNN1) VDONF1 3.0 3.3 3.6 V Dropout Voltage of (VNEG - VGN) VDONEG 2.9 3.3 3.5 V Dropout Voltage of (VGP - VPOS) VDOPOS -2.8 -2.6 -2.4 V — 0.2 VLL V Logic & Clock Input Characteristics Input Logic Low Voltage VIL 0 Input Logic High Voltage VIH 0.8 VLL — VLL V Input Logic Low Current IIL -1.0 — — μA Note 1 Input Logic High Current IIH — — 1.0 μA Note 1 Input Capacitance CIN — 2.0 3.0 pF Note 2 — 200 — µs 50% OEN rise to TX ready, Note 2 — 20 — ns 50% OEN fall to TX all output FETs on HV rails are off, Note 1 — — 5.25 V — — 0.1 V at 100 μA — — 0.4 V at 4.0 mA — — 15 μA 25°C, at 5.25V pull-up, Note 1 OEN Switching On Time tOEN OEN Switching Off Time Thermal protection OTPN & UVLO OTPN Output Max. Pull-Up VOH OTPN Output Low Max. Voltage VOL OTPN Output High Current IOFF Note 1: 2: Characterized only; not 100% tested in production. Design guidance only. DS20005639A-page 8  2016 Microchip Technology Inc. HV7321 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Thermal Shutdown Trip Point Sym. Min. Typ. Max. Unit TTRIP 125 138 160 °C °C OTPN = LO when thermal shutdown occurs, Note 1 V Note 1 THYS — 38 — VDD OK On Voltage VDDUVON 3.45 3.7 4.05 VDD UVLO Trip Voltage Thermal Shutdown Hysteresis VDDUVOFF 3.05 3.4 3.85 VLL OK On Voltage VLLUVON 1.59 1.7 1.81 VLL UVLO Trip Voltage VLLUVOFF 1.39 1.6 1.71 Conditions TX Output HD2 & Timing Characteristics Second Harmonic Distortion HD2 — -44 -40 Output Rise Time from 0V to VPP0 tr1 — 10 12 Output Fall Time from 0V to VNN0 tf1 — 10 12 Output Rise Time from VNN0 to VPP0 tr2 — 17 19 Output Fall Time from VPP0 to VNN0 tf2 — 17 19 Output Rise Time from VNN0 to 0V tr3 — 10 13.5 Output Fall Time from VPP0 to 0V tf3 — 10 13.5 Propagation Delay Rise Time 1 tdr1 — 16 18 Propagation Delay Fall Time 1 tdf1 — 16 18 Propagation Delay Rise Time 2 tdr2 — 17.5 19 Propagation Delay Fall Time 2 tdf2 — 17.5 19 Propagation Delay Rise Time 3 tdr3 — 14 16 Propagation Delay Fall Time 3 tdf3 — 14 16 Output Rise Time from 0V to VPP1 tr4 — 15 17 Output Fall Time from 0V to VNN1 tf4 — 15 17 Output Rise Time from VNN1 to VPP1 tr5 — 24 27 Output Fall Time from VPP1 to VNN1 tf5 — 24 27 Output Rise Time from VNN1 to 0V tr6 — 10 13 Output Fall Time from VPP1 to 0V tf6 — 10 13 Propagation Delay Rise Time 4 tdr4 — 15 17 Propagation Delay Fall Time 4 tdf4 — 15 17 Propagation Delay Rise Time 5 tdr5 — 16 18 Propagation Delay Fall Time 5 tdf5 — 16 18 Propagation Delay Rise Time 6 tdr6 — 15 17 Propagation Delay Fall Time 6 tdf6 — 15 17 Delay Time Matching with SEL = L ∆td1 — 1.5 2.0 ns Delay Time Matching with SEL = H ∆td2 — 1.5 2.0 ns Note 1: 2: dB ns ns VPP0/VNN0 = ±70V launched in 100 µs apart, with load of 220 pF//1k (Second Harmonic Distortion). HD2, single-cycle inverting 5.0 MHz Note 1 All these tr,tf,td values, at VPP0,1/VNN0,1 = ±70V, 220 pF//1k Note 1 ns All these tr,tf,td values at VPP0,1/VNN0,1 = ±70V, 220 pF//1k Note 1 ns P to N, ch.-to-ch. matching in IC, typ. at VPP0,1/VNN0,1,2 = ±70V, 220 pF//1k, Note 1 Characterized only; not 100% tested in production. Design guidance only.  2016 Microchip Technology Inc. DS20005639A-page 9 HV7321 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the operating temperature range of TA = TJ = 0 to +85°C. Parameter Sym. TRSW Switch On Delay Time TRSW Switch Off Delay Time RTZSW Switch On Delay Time RTZSW Switch Off Delay Time RXDMP Damp Switch On Delay Time RXDMP Damp Switch Off Delay Time Min. Typ. Max. Unit Conditions 130 180 230 ns From POS = 0 & NEG = 0, Note 1 tTRSW 8 12 16 ns From POS = 1 or NEG = 1, Note 1 130 180 240 ns From POS = 0 & NEG = 0, Note 1 11 21 31 ns From POS = 1 or NEG = 1, Note 1 3 10 15 ns From POS = 1 or NEG = 1, Note 1 0.55 1.4 2.35 us From POS = 0 & NEG = 0, Note 1 Note 2 tRTZSW tRXDMP PWS = 0 to 1 Mode Change Time tMC — 220 — ns Output Max. Frequency Range fOUT — 20 — MHz 100Ω resistor load, Note 2 Re-Timing Clock Frequency fCLK 10 — 220 MHz Note 2 Re-Timing Clock Rise & Fall Times tRC,tFC — 0.5 5.0 ns Note 2 Set-Up Time, POS/NEG to CLK tsu 2.0 — — ns Note 2 Hold Time, CLK to POS/NEG tH 1.0 — — ns Note 2 tCLK_LO 2.0 — 100 tCLK_HI 2.0 — 100 tCLK_REC — 2.0 — ns tCLK_RLS 150 330 500 CLK input must be activated before POS and NEG inputs are high. CLK input must be deactivated after POS and NEG inputs are low. Clock Time Low (2) Clock Time High (2) Clock Recognition Time (1) Clock Release Time (1) Note 1: 2: Characterized only; not 100% tested in production. Design guidance only. TEMPERATURE CHARACTERISTICS Unless otherwise indicated, all parameters apply with VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V, VSUB = 0V, OEN = REN = 1 Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Ambient Temperature Range TOA 0 — +85 °C Storage Temperature Range TST -55 — +150 °C Maximum Junction Temperature TJ — — +130 °C Total Power Dissipation PD — 3.0 — W Thermal Package Resistances (64LD 9 mm x 9 mm VQFN) Junction-to-Ambient Thermal Resistance JA — 16.3 — °C/W JEDEC (2S2P) 4L PCB 114.3 mm x 76.2 mm x1.6 mm TA = 85°C Junction-to-Board Thermal Resistance JB — 2.55 — °C/W JEDEC (2S2P) 4L PCB 114.3 mm x 76.2 mm x1.6 mm TA = 85°C Junction-to-Case Top Thermal Resistance JC — 0.2 — °C/W JEDEC (2S2P) 4L PCB 114.3 mm x 76.2 mm x1.6 mm TA = 85°C DS20005639A-page 10  2016 Microchip Technology Inc. HV7321 TABLE 1-1: INPUT OUTPUT LOGIC TRUTH TABLE (TRANSPARENT, CLK = 0) Logic Inputs Function OTPN OEN MODE PWS CLK SEL NEG POS TX Output RTZSW & TRSW CWSW RXDMP 1 1 0 1 0 0 0 0 RTZ OFF OFF ON 1 1 0 1 0 0 0 1 VPP0 OFF OFF ON 1 1 0 1 0 0 1 0 VNN0 OFF OFF ON 1 1 0 1 0 0 1 1 RTZ+(4) ON OFF OFF 1 1 0 1 0 1 0 0 RTZ OFF OFF ON 1 1 0 1 0 1 0 1 VPP1 OFF OFF ON 1 1 0 1 0 1 1 0 VNN1 OFF OFF ON 1 1 0 1 0 1 1 1 high Z OFF OFF ON 1 1 0 0 0 0 0 0 RTZ OFF OFF ON 1 1 0 0 0 0 0 1 VPP0 OFF OFF ON 1 1 0 0 0 0 1 0 VNN0 OFF OFF ON 1 1 0 0 0 0 1 1 RTZ+(4) ON OFF OFF 1 1 0 0 0 1 0 0 RTZ OFF OFF ON 1 1 0 0 0 1 0 1 VPP1 OFF OFF ON 1 1 0 0 0 1 1 0 VNN1 OFF OFF ON 1 1 0 0 0 1 1 1 high Z OFF OFF ON CW Mode-1 (3) 1 1 1 x x high Z OFF ON ON ON OFF OFF Device Disabled x 0 x x Thermal Protection Activated 0 x x x Pulsed-Echo Mode (1) CW Mode-0 (2) Note 1: 2: 3: 4: other than 011 (4) 0 1 1 RTZ+ x x x x high Z OFF OFF ON x x x x high Z OFF OFF ON In Pulsed-Echo mode, low duty cycle must be used due to the IC power dissipation limit. When PWS = 0, VPP1/VNN1 output current is reduced for low-voltage CW mode-0. VPP0/VNN0 output current is unaffected when PWS = 1, as in Pulsed-Echo mode. In CW MODE = 1, the CWSW is turned on to use external CW waveform at CWIN, if the channel SEL = NEG = POS = 0. When SEL = 0, NEG = 1, POS = 1, the channel is in Receiving mode (RTZ+).  2016 Microchip Technology Inc. DS20005639A-page 11 HV7321 TABLE 1-2: INPUT OUTPUT LOGIC TRUTH TABLE (WITH CLK RE-TIMING, CLK  10MHZ) Logic Inputs Function OTPN 1 OEN MODE PWS CLK SEL NEG POS 1 0 1 ↑ 0 0 0 TX Output RTZSW & TRSW CWSW RXDMP RTZ OFF OFF ON 1 1 0 1 ↑ 0 0 1 VPP0 OFF OFF ON 1 1 0 1 ↑ 0 1 0 VNN0 OFF OFF ON RTZ+(4) ON OFF OFF 1 1 0 1 ↑ 0 1 1 1 1 0 1 ↑ 1 0 0 RTZ OFF OFF ON 1 1 0 1 ↑ 1 0 1 VPP1 OFF OFF ON 1 1 0 1 ↑ 1 1 0 VNN1 OFF OFF ON 1 1 0 1 ↑ 1 1 1 high Z OFF OFF ON 1 1 0 0 ↑ 0 0 0 RTZ OFF OFF ON 1 1 0 0 ↑ 0 0 1 VPP0 OFF OFF ON 1 1 0 0 ↑ 0 1 0 VNN0 OFF OFF ON 1 1 0 0 ↑ 0 1 1 RTZ+(4) ON OFF OFF 1 1 0 0 ↑ 1 0 0 RTZ OFF OFF ON 1 1 0 0 ↑ 1 0 1 VPP1 OFF OFF ON 1 1 0 0 ↑ 1 1 0 VNN1 OFF OFF ON 1 1 0 0 ↑ 1 1 1 high Z OFF OFF ON CW Mode-1 (3) 1 1 1 x x high Z OFF ON ON ON OFF OFF Device Disabled x 0 x x Thermal Protection Activated 0 x x x Pulsed-Echo Mode (1) CW Mode-0 (2) Note 1: 2: 3: 4: other than 011 RTZ+ (4) 0 1 1 x x x x high Z OFF OFF ON x x x x high Z OFF OFF ON In Pulsed-Echo mode, low duty cycle must be used due to the IC power dissipation limit. When PWS = 0, VPP1/VNN1 output current is reduced for low-voltage CW mode-0. VPP0/VNN0 output current is unaffected when PWS = 1, as in Pulsed-Echo mode. In CW MODE = 1, the CWSW is turned on to use external CW waveform at CWIN, if the channel SEL = NEG = POS = 0. When SEL = 0, NEG = 1, POS = 1, the channel is in Receiving mode (RTZ+). DS20005639A-page 12  2016 Microchip Technology Inc. HV7321 1.1 TYPICAL TIMING DIAGRAMS Figure 1-1 shows the timing of control inputs and RTZ, T/R and RXDMP switches per each channel of the HV7321. Upon the completion of a receiving period, an RTZ period (SEL, NEG, POS = 000) should be asserted before transmitting again. SEL input NEG input POS input 001 tdr1 TX output 010 tdf2 000 tdr3 010 tdf1 001 tdr2 tdf3 101 tdr4 tr1 100 tdr6 110 tdf4 101 tdr5 tdf6 tf5 tr6 tf4 tr5 tf6 110 000 tr4 tr3 tf2 FIGURE 1-1: 110 tdf5 tr2 tf1 tf3 Logic Input Timing Diagram. B-Mode PWS input tMC CW-mode SEL input 011 NEG input POS input 000 001 010 VPP0 000 101 011 VPP1 TX output RTZ RTZ RTZ+ RTZ+ 011 VNN0 tRTZSW(OFF) RTZSW switch RTZ VNN1 000 ON OFF ON tTRSW(ON) OFF ON tTRSW(OFF) TRSW switch ON tRXDMP(OFF) tRXDMP(ON) ON OFF RXDMP switch MODE Input SEL Input NEG Input POS Input HV7321 Tx Output RTZ OFF TX time RX time FIGURE 1-2: tRTZSW(ON) RX time TX Output Timing Diagram. MODE = 1 MODE = 0 External CW source 000 000 Per Ch CW Delay in external CW source External CW Source CW end VCW+ Hi-Z RTZ External CW Source VCW- FIGURE 1-3: Timing Diagram of HV7321 TX Output and Switches in CW Mode-1 Driven by External CW Source.  2016 Microchip Technology Inc. DS20005639A-page 13 HV7321 NOTES: DS20005639A-page 14  2016 Microchip Technology Inc. HV7321 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.5 50 0.4 40 0.3 30 IDDQ (ȝA) ILLQ (ȝA) Note: 0.2 0.1 0 10 0 25 50 Temperature (°C) 75 0 100 ILLQ vs. Temperature. 4 0 3 -1 2 25 50 Temperature (°C) 75 100 IDDQ vs. Temperature. -2 -3 1 0 0 FIGURE 2-4: INN0Q (ȝA) IPP0Q (ȝA) FIGURE 2-1: 0 25 50 Temperature (°C) 75 -4 100 IPP0Q vs. Temperature. FIGURE 2-2: 0 25 50 Temperature (°C) 75 100 INN0Q vs. Temperature. FIGURE 2-5: 3 0 -1 2 INN1Q (ȝA) IPP1Q (ȝA) 20 1 -2 -3 0 0 FIGURE 2-3: 25 50 Temperature (°C) 75 IPP1Q vs. Temperature.  2016 Microchip Technology Inc. 100 -4 0 FIGURE 2-6: 25 50 Temperature (°C) 75 100 INN1Q vs. Temperature. DS20005639A-page 15 HV7321 100 A B 80 Voltage (V) 60 40 20 0 -20 -40 -60 -80 -100 0 0.1 0.2 Time (µs) 0.3 0.4 FIGURE 2-7: TX Output Waveform, 1-Cycle 5 MHz with 220 pF//1K Load. 20 A+B A-B HD2 = -52.9 dB Amplitude (dB) 10 0 -10 -20 -30 -40 -50 -60 0 5 10 15 20 Frequency (MHz) 25 30 FIGURE 2-8: TX Output HD2, 1-Cycle Inverting, 5 MHz with 220pF//1K Load. DS20005639A-page 16  2016 Microchip Technology Inc. HV7321 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Symbol Description 1 CWIN0 External CW input for channel 0 2 SEL1 SEL input logic pin selects transmission high-voltage rails for channel 1. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1. 3 NEG1 NEG input logic pin turns on/off corresponding output N-channel MOSFET for channel 1. See Table 1-1. 4 POS1 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 1. See Table 1-1. 5 CWIN1 External CW input for channel 1 6 OEN Output enable logic input pin. When OEN = VLL, the transmitter outputs are enabled. When OEN = 0, the transmitter outputs are disabled. 7 PWS Logic input pin. When PWS = 0, the output FETs for VPP1 and VNN1 are scaled down to reduce the output current for CW Mode-0. 8 CLK Re-timing clock input pin. Connect CLK to ground for transparent mode. 9, 22, 59 GND Ground 10 VLL Input logic power supply pin 11 REN Enable pin for the built-in voltage regulators.See section Section 4.3 “Operation Modes” for details. 12 SEL2 SEL input logic pin selects transmission high-voltage rails for channel 2. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1. 13 NEG2 NEG input logic pin turns on/off corresponding output N-channel MOSFET for channel 2. See Table 1-1. 14 POS2 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 2. See Table 1-1. 15 CWIN2 External CW input for channel 2 16 SEL3 SEL input logic pin selects transmission high-voltage rails for channel 3. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1. 17 NEG3 NEG input logic pin turns on/off corresponding output N-channel MOSFET for channel 3. See Table 1-1. 18 POS3 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 3. See Table 1-1. 19 CWIN3 External CW input for channel 3 20 OTPN Temperature sensor open drain output 21, 60 VDD +5V supply 23 VGP +10V supply pin for the linear regulator 24, 25, 56, 57 VPP0 Positive high-voltage supply pin. VPP0 must be equal to or greater than VPP1. 26, 55 CPF0 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VPP0. 27, 54 CNF0 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VNN0. 28, 29, 52, 53 VNN0 Negative high-voltage supply pin. VNN0 must be equal to or more negative than VNN1,2 30, 51 VNN2 Negative high-voltage supply pin. VNN2 connects to the most negative supply rail. 31, 50 VNN1 Negative high-voltage supply pin. VNN1 must be equal to or less negative than VNN0. 32, 49 CNF1 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VNN1. 33, 48 CPF1 Internal linear regulator output pin. Connect 2 µF 10V capacitor to VPP1. 34, 47 VPP1 Positive high voltage supply VPP1. Must be equal to or lower than VPP0. 35 TX3 Channel 3 transmitter output pin  2016 Microchip Technology Inc. DS20005639A-page 17 HV7321 TABLE 3-1: PIN FUNCTION TABLE (CONTINUED) Pin Symbol Description 36 RX3 Channel 3 T/R switch output 37, 44 RGND Power ground 38 RX2 Channel 2 T/R switch output 39 TX2 40 CNEG Internal linear regulator output pin. Connect 1 µF 10V capacitor to GND. Channel 2 transmitter output pin 41 CPOS Internal linear regulator output pin. Connect 1 µF 10V capacitor to GND. 42 TX1 Channel 1 transmitter output pin 43 RX1 Channel 1 T/R switch output 45 RX0 Channel 0 T/R switch output 46 TX0 Channel 0 transmitter output pin 58 VGN -10V supply pin for the linear regulator 61 MODE CW Mode selection pin. See section Section 4.3 “Operation Modes”. 62 SEL0 SEL input logic pin selects transmission high-voltage rails for channel 0. If SEL = 0, select VPP0/VNN0. If SEL = 1, select VPP1/VNN1. See Table 1-1. 63 NEG0 NEG input logic pin turns on/off corresponding output N-channel MOSFET for channel 0. See Table 1-1. 64 POS0 POS input logic pin turns on/off corresponding output P-channel MOSFET for channel 0. See Table 1-1. Thermal Pad VSUB Connect to ground. DS20005639A-page 18  2016 Microchip Technology Inc. HV7321 4.0 DEVICE DESCRIPTION 4.2 4.1 Overview Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering-up sequences in Table 4-1 are only recommended in order to minimize possible in-rush current. Figure 4-1 shows the timing diagram of related signals. The HV7321 is a 4-channel, 5-level ultrasound transmitter with built-in T/R switches, output protection diodes and clamp diodes. The HV7321 can provide up to 2.6A and the output voltage swing can be up to 80V. The HV7321 supports both Transparent and Re-Timing mode. The re-timing clock frequency can support up to 220 MHz. The re-timing feature helps reduce the output jitter introduced by the driving FPGA. Recommended Power-up Sequence TABLE 4-1: POWER-UP SEQUENCE Step Power-Up Description 1 VLL ON with logic signal low 2 VDD, VGP and VGN ON 3 REN = 1 4 VPP0,1 and VNN0,1 ON 5 OEN = 1 & Logic control signal active VLL input VDD > VDDUVON VDD input Internal VDD Power-Good Signal PGD internal VGP input |VGN| VPP input |VNN| REN input (Power Saving) OEN input VCPOS output VCNEG output VPP ࡳ VCPF VCNF ࡳ VNN (3V) FIGURE 4-1: 4.3 Ready to Work tOEN_ON Power-On Events and Power-Saving Time Diagram. 4.3.2 Operation Modes There are five modes of operation: Device Disabled, Output Disabled, Pulsed-Echo Mode, CW Mode-0 and CW Mode-1. 4.3.1 DEVICE ENABLE MODE In Device Disabled mode, the regulators are turned off when REN is low. The regulators are ON when REN = VLL. All regulators are ON except VNEG and VPOS for power saving when REN = 1. When REN is low, OEN = X (OEN = 1 or 0) since device is disabled. Refer to Table 4-2. TABLE 4-2: OUTPUT HIGH Z MODE In Output Disabled mode, regulators are enabled REN = 1 and OEN = 0 (Output Enable logic input) and output pins (TX0-3) are in high Z state. OEN = 1 enables the outputs. 4.3.3 PULSED-ECHO MODE Pulsed-Echo mode (B-mode) enables the 5-level waveform generation. OEN = 1, MODE = 0, and PWS = 1 enable Pulsed-Echo mode after HV7321 powers on. SEL/NEG/POS inputs of desired channel determine the corresponding TX Output pulse. REN & OEN LOGIC INPUTS REN OEN Device TX Output 0 X Disabled high Z 1 0 Enabled high Z 1 1 Enabled ON  2016 Microchip Technology Inc. DS20005639A-page 19 HV7321 4.3.4 CW MODE-0 TABLE 4-3: CW Mode-0 enables continuous wave mode provided solely by the HV7321. OEN = 1, MODE = 0 and PWS = 0 activate CW Mode-0. FPGA selects VPP1 and VNN1 amplitudes via SEL/NEG/POS inputs. 4.3.5 0 0 CW Mode-0 0 1 Pulsed-Echo 1 X CW Mode-1 State +5V +2.5V VLL CTRN[3:0] External CW Beamformer Option (CW Mode-1) The MD1730 supports both differential and single-ended signals using CLKP and CLKN inputs. The MD1730 enables setting the CW output phase delay and frequency for channels via SPI. Please refer to the MD1730 data sheet for more information. MODE & PWS LOGIC INPUTS PWS State One suggested external CW beamformer is the MD1730, which has very low phase noise and 8-channel CW output. A pair of HV7321s can operate with the MD1730 as an 8-channel CW waveform generator. See Figure 4-2. CW Mode-1 is enabled using an external CW signal source for continuous wave mode. OEN = 1 and MODE = 1 activate CW Mode-1. External CW signals can connect to any of CWIN0-3. In this mode, the CW signal source also feeds the CLK input. See Table 4-3 for details. Mode PWS The HV7321 has built-in CW switches that allow the use of an external CW beamformer to further minimize jitter and phase noise on CW waveforms. This mode is called CW Mode-1. CW MODE-1 TABLE 4-3: Mode 4.3.5.1 In theory, VPP0 and VNN0 can be selected but this is strongly discouraged since VPP0 and VNN0 usage increases power consumption and causes excessive heating in CW Mode-0. MODE & PWS LOGIC INPUTS +10V VGP VPP OEN 0V to +80V 1 of 4 channles REN VPP0 MODE TX FPGAI/Os PWS VPF0 VNF0 OTPN OTPN DT[63:0] 0V to -80V VNN0 VPP1 SEL0 0V to +80V NEG0 +2.5V +5V +1V to +8V +10V POS0 VLL VPP CBE0,1 CLK CLK SCK SDI SDO CS SPIM EN TXRW VGP VLL CBE1 CLK SEL3 CKB0 CBE0 VLL VCW+ VPF VNF 1 of 8 channels VCW- FIGURE 4-2: DS20005639A-page 20 CW0 CW1 CW2 CW3 to other ICs TRSW RX0 TRSW RX0 CLK RXDMP CWIN0 CWIN1 CWIN2 CWIN3 CWSW HV7321 RGND RGND TX1-3 RX1-3 CW4~7 MD1730 -10V to next HV7321 CLK X0 RTZSW POS3 CKB1 SPI CW Fre. Dvdr & Phase Delay TX0 NEG3 CLK SUB GND DAP VGN 0V to -80V VNN1 CPF VCW+ LVDS CLK other CW channels VPF1 VNF1 Decode & Level Shift SUB CNF VCW- to next HV7321 CWIN03 -1V to -8V GND VSUB VGN -10V HV7321 + MD1730 Integration.  2016 Microchip Technology Inc. HV7321 4.4 High Temperature Protection When overtemperature is detected, OTPN = 0 and all outputs are high Z regardless of OEN and the other logic control inputs. Table 4-4 shows the relationship between REN, OEN inputs, OTPN output, and the corresponding device status. TABLE 4-4: REN, OEN, OTPN VS. DEVICE STATUS OTPN REN OEN Device TX Output 0 0 X Disabled high Z 0 1 X Enabled high Z 1 0 X Disabled high Z 1 1 0 Enabled high Z 1 1 1 Enabled ON  2016 Microchip Technology Inc. DS20005639A-page 21 HV7321 NOTES: DS20005639A-page 22  2016 Microchip Technology Inc. HV7321 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 64-Lead VQFN (9 x 9 x 1.0 mm) Example HV7321K6 e3 1642256 Legend:XX...XProduct Code or Customer-specific information YYear code (last digit of calendar year) YYYear code (last 2 digits of calendar year) WWWeek code (week of January 1 is week ‘01’) NNNAlphanumeric traceability code 3 ePb-free JEDEC designator for Matte Tin (Sn) *This package is Pb-free. The Pb-free JEDEC designator ( can be found on the outer packaging for this package. Note: ) e3 In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo.  2016 Microchip Technology Inc. DS20005639A-page 23 HV7321 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. DS20005639A-page 24  2016 Microchip Technology Inc. HV7321 APPENDIX A: REVISION HISTORY Revision A (October 2016) • Original Release of this Document.  2016 Microchip Technology Inc. DS20000000A-page 25 HV7321 NOTES: DS20000000A-page 26  2016 Microchip Technology Inc. HV7321 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX -X Device Package Environmental Device: HV7321: 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches Package: K6 = Very Thin Plastic Quad Flat Pack, No Lead Package, 9.00 x9.00 x1.0 mm Body, 0.50 mm Pitch, 64-Lead (VQFN) Environmental: G = Lead (Pb)-free/ROHS-compliant package  2016 Microchip Technology Inc. Examples: a) HV7321K6-G: 4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches 64LD 9x9 mm VQFN package DS20000000A-page 27 HV7321 NOTES: DS20000000A-page 28  2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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